soc/intel/common/blk/memory: Make mixed topo work

When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.

Tested on system76/lemp10. Unit boots with and without DIMM installed.

Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>

.gitmodules

@@ -1,62 +1,62 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

Documentation/mainboard/index.md

@@ -188,6 +188,7 @@ The boards in this section are not real mainboards, but emulators.
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Gazelle 15](system76/gaze15.md)
+- [Gazelle 16](system76/gaze16.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Oryx Pro 5](system76/oryp5.md)

Documentation/mainboard/system76/gaze16.md

@@ -0,0 +1,87 @@
+# System76 Gazelle 16 (gaze16)
+
+## Specs
+
+- CPU
+  - Intel Core i7-11800H
+- Chipset
+  - Intel HM570
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+  - eDP displays
+    - 15.6" 1920x1080@144Hz LCD (AUO B156HAN08.4)
+    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
+  - External outputs
+    - RTX 3050/3050 Ti
+      - 1x HDMI
+      - 1x Mini DisplayPort 1.4
+    - RTX 3060
+      - 1x HDMI
+      - 1x Mini DisplayPort 1.2
+      - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+    - Either onboard Intel I219-V or Realtek RTL8111H controller
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - RTX 3050/3050 Ti
+    - 150W AC barrel adapter
+      - Included: Chicony A17-150P2A, using a C5 power cord
+  - RTX 3060
+    - 180W AC barrel adapter
+      - Included: Chicony A17-180P4A, using a C5 power cord
+  - 48.96Wh 4-cell battery
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - SD card reader
+    - Realtek RTS5227S on RTX 3050/3050 Ti models
+    - Realtek OZ711LV2 on RTX 3060 models
+- USB
+  - 1x USB 3.2 Gen 2 Type-C
+    - Supports DisplayPort over USB-C on RTX 3060 models only
+    - Does not support USB-C charging (USB-PD) or Thunderbolt
+  - 1x USB 3.2 Gen 2 Type-A
+  - 1x USB 3.2 Gen 1 Type-A
+  - 1x USB 2.0 Type-A
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B127D           |
++---------------------+---------------------+
+| Size                | 16 MiB              |
++---------------------+---------------------+
+| Package             | SOIC-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U51 on 3050 variant, U52 on 3060 variant) is left of the top DIMM slot.

Documentation/releases/coreboot-4.14-relnotes.md

@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
 
 coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP

Documentation/releases/coreboot-4.15-relnotes.md

@@ -1,7 +1,7 @@
-Upcoming release - coreboot 4.15
+coreboot 4.15
 ================================
 
-The 4.15 release is planned for November 5th, 2021.
+coreboot 4.15 was released on November 5th, 2021.
 
 Since 4.14 there have been more than 2597 new commits by more than 219 developers.
 Of these, over 73 contributed to coreboot for the first time.

Documentation/releases/coreboot-4.16-relnotes.md

@@ -1,7 +1,7 @@
 Upcoming release - coreboot 4.16
 ================================
 
-The 4.16 release is planned for Februrary, 2022. 
+The 4.16 release is planned for February, 2022.
 
 We are increasing the frequency of releases in order to enable others to release quarterly on
 a fresher version of coreboot.

Documentation/releases/index.md

@@ -27,4 +27,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.16 - May 2022](coreboot-4.16-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)

payloads/external/Makefile.inc

@@ -146,7 +146,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
-		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
+		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \

payloads/external/tianocore/Makefile

@@ -9,7 +9,7 @@ project_git_repo=https://github.com/mrchromebox/edk2
 project_git_branch=uefipayload_202107
 upstream_git_repo=https://github.com/tianocore/edk2
 
-build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
 
 ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
 project_git_branch=coreboot_fb

src/Kconfig

@@ -1179,7 +1179,7 @@ config DEBUG_INTEL_ME
 endif
 
 config DEBUG_FUNC
-	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
+	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
 	default n
 	help
 	  This option enables additional function entry and exit debug messages

src/acpi/acpi.c

@@ -266,7 +266,8 @@ void acpi_create_madt(acpi_madt_t *madt)
 static unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0,
+			CONFIG_ECAM_MMCONF_BUS_NUMBER - 1);
 	return current;
 }
 
@@ -291,7 +292,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 	header->length = sizeof(acpi_mcfg_t);
 	header->revision = get_acpi_table_revision(MCFG);
 
-	if (CONFIG(MMCONF_SUPPORT))
+	if (CONFIG(ECAM_MMCONF_SUPPORT))
 		current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum. */

src/acpi/dsdt_top.asl

@@ -31,13 +31,13 @@ Method (_PIC, 1)
 	PICM = Arg0
 }
 
-#if CONFIG(MMCONF_SUPPORT)
+#if CONFIG(ECAM_MMCONF_SUPPORT)
 Scope(\_SB) {
 	/* Base address of PCIe config space */
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+	Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
 
 	/* Length of PCIe config space, 1MB each bus */
-	Name(PCLN, CONFIG_MMCONF_LENGTH)
+	Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
 
 	/* PCIe Configuration Space */
 	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */

src/arch/arm/include/armv4/arch/smp/spinlock.h

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _ARCH_SMP_SPINLOCK_H
-#define _ARCH_SMP_SPINLOCK_H
-
-#define DECLARE_SPIN_LOCK(x)
-#define spin_is_locked(lock)	0
-#define spin_unlock_wait(lock)	do {} while (0)
-#define spin_lock(lock)		do {} while (0)
-#define spin_unlock(lock)	do {} while (0)
-
-#include <smp/node.h>
-#define boot_cpu() 1
-
-#endif

src/arch/x86/include/arch/pci_io_cfg.h

@@ -69,7 +69,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
 	outl(value, 0xCFC);
 }
 
-#if !CONFIG(MMCONF_SUPPORT)
+#if !CONFIG(ECAM_MMCONF_SUPPORT)
 
 /* Avoid name collisions as different stages have different signature
  * for these functions. The _s_ stands for simple, fundamental IO or

src/arch/x86/include/arch/pci_ops.h

@@ -4,7 +4,7 @@
 #define ARCH_I386_PCI_OPS_H
 
 #include <arch/pci_io_cfg.h>
-#if CONFIG(MMCONF_SUPPORT)
+#if CONFIG(ECAM_MMCONF_SUPPORT)
 #include <device/pci_mmio_cfg.h>
 #endif
 

src/arch/x86/include/arch/smp/spinlock.h

@@ -15,10 +15,6 @@ typedef struct {
 
 #define SPIN_LOCK_UNLOCKED { 1 }
 
-#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE
-
-#if STAGE_HAS_SPINLOCKS
-
 #define DECLARE_SPIN_LOCK(x)	\
 	static spinlock_t x = SPIN_LOCK_UNLOCKED;
 
@@ -71,14 +67,4 @@ static __always_inline void spin_unlock(spinlock_t *lock)
 		: "=m" (lock->lock) : : "memory");
 }
 
-#else
-
-#define DECLARE_SPIN_LOCK(x)
-#define spin_is_locked(lock)	0
-#define spin_unlock_wait(lock)	do {} while (0)
-#define spin_lock(lock)		do {} while (0)
-#define spin_unlock(lock)	do {} while (0)
-
-#endif
-
 #endif /* ARCH_SMP_SPINLOCK_H */

src/arch/x86/smbios.c

@@ -224,6 +224,9 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 					 unsigned long *current, int *handle,
 					 int type16_handle)
 {
+	struct spd_info info;
+	get_spd_info(dimm->ddr_type, dimm->mod_type, &info);
+
 	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
 						     sizeof(*t), *handle);
 
@@ -244,24 +247,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	}
 	t->data_width = 8 * (1 << (dimm->bus_width & 0x7));
 	t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3);
-
+	t->form_factor = info.form_factor;
-	switch (dimm->mod_type) {
-	case SPD_RDIMM:
-	case SPD_MINI_RDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_RIMM;
-		break;
-	case SPD_UDIMM:
-	case SPD_MICRO_DIMM:
-	case SPD_MINI_UDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_DIMM;
-		break;
-	case SPD_SODIMM:
-		t->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		break;
-	default:
-		t->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
-		break;
-	}
 
 	smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t);
 	smbios_fill_dimm_serial_number(dimm, t);
@@ -278,19 +264,8 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	t->maximum_voltage = dimm->vdd_voltage;
 
 	/* Fill in type detail */
-	switch (dimm->mod_type) {
+	t->type_detail = info.type_detail;
-	case SPD_RDIMM:
+
-	case SPD_MINI_RDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case SPD_UDIMM:
-	case SPD_MINI_UDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	default:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	}
 	/* Synchronous = 1 */
 	t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
 	/* no handle for error information */

src/device/Kconfig

@@ -499,13 +499,21 @@ config PCI
 
 if PCI
 
-config NO_MMCONF_SUPPORT
+config NO_ECAM_MMCONF_SUPPORT
 	bool
 	default n
+	help
+	  Disable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
-config MMCONF_SUPPORT
+config ECAM_MMCONF_SUPPORT
 	bool
-	default !NO_MMCONF_SUPPORT
+	default !NO_ECAM_MMCONF_SUPPORT
+	help
+	  Enable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
 config PCIX_PLUGIN_SUPPORT
 	bool
@@ -540,20 +548,20 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	hex
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_LENGTH
+config ECAM_MMCONF_LENGTH
 	hex
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
-	default 0x04000000 if MMCONF_BUS_NUMBER = 64
+	default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
-	default 0x08000000 if MMCONF_BUS_NUMBER = 128
+	default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
-	default 0x10000000 if MMCONF_BUS_NUMBER = 256
+	default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
 	default 0x0
 
 config PCI_ALLOW_BUS_MASTER
@@ -619,7 +627,7 @@ config PCIEXP_CLK_PM
 config PCIEXP_L1_SUB_STATE
 	prompt "Enable PCIe ASPM L1 SubState"
 	bool
-	depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT)
+	depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
 	default n
 	help
 	  Detect and enable ASPM on PCIe links.
@@ -635,8 +643,8 @@ if PCIEXP_HOTPLUG
 
 config PCIEXP_HOTPLUG_BUSES
 	int "PCI Express Hotplug Buses"
-	default  8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <=  64
+	default  8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <=  64
-	default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
+	default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
 	default 32
 	help
 	  This is the number of buses allocated for hotplug PCI express

src/device/azalia_device.c

@@ -227,7 +227,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
-static void codec_init(struct device *dev, u8 *base, int addr)
+void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -252,7 +252,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	/* 2 */
 	reg32 = read32(base + HDA_IR_REG);
 	printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
-	verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
+	verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb);
 
 	if (!verb_size) {
 		printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
@@ -261,19 +261,22 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
 
 	/* 3 */
-	azalia_program_verb_table(base, verb, verb_size);
+	const int rc = azalia_program_verb_table(base, verb, verb_size);
-	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
+	if (rc < 0)
+		printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n");
+	else
+		printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
 
 	mainboard_azalia_program_runtime_verbs(base, reg32);
 }
 
-static void codecs_init(struct device *dev, u8 *base, u16 codec_mask)
+void azalia_codecs_init(u8 *base, u16 codec_mask)
 {
 	int i;
 
 	for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 		if (codec_mask & (1 << i))
-			codec_init(dev, base, i);
+			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 	}
 
 	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
@@ -297,7 +300,7 @@ void azalia_audio_init(struct device *dev)
 
 	if (codec_mask) {
 		printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
-		codecs_init(dev, base, codec_mask);
+		azalia_codecs_init(base, codec_mask);
 	}
 }
 

src/device/device_util.c

@@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index,
 void mmconf_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource = new_resource(dev, index);
-	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_MMCONF_LENGTH;
+	resource->size = CONFIG_ECAM_MMCONF_LENGTH;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 

src/device/dram/ddr3.c

@@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 
 		switch (info->dimm_type) {
 		case SPD_DDR3_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR3_SPD_SODIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
-			dimm->mod_type = SPD_72B_SO_CDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR3_SPD_UDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR3_SPD_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UNDEFINED:
 		default:

src/device/dram/ddr4.c

@@ -299,16 +299,16 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel
 
 		switch (info->dimm_type) {
 		case SPD_DDR4_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR4_SPD_SODIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR4_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR4_SPD_UDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR4_SPD_RDIMM;
 			break;
 		default:
 			dimm->mod_type = SPD_UNDEFINED;

src/device/dram/spd.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/dram/spd.h>
+#include <spd.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id)
 {
@@ -38,3 +39,219 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
 		return NULL;
 	}
 }
+
+static void convert_default_module_type_to_spd_info(struct spd_info *info)
+{
+	info->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
+	info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+}
+
+static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR2_SPD_RDIMM:
+	case DDR2_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR2_SPD_UDIMM:
+	case DDR2_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR2_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR2_SPD_SODIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR3_SPD_RDIMM:
+	case DDR3_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR3_SPD_UDIMM:
+	case DDR3_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR3_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR3_SPD_SODIMM:
+	case DDR3_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR4_SPD_RDIMM:
+	case DDR4_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR4_SPD_UDIMM:
+	case DDR4_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR4_SPD_SODIMM:
+	case DDR4_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR5_SPD_RDIMM:
+	case DDR5_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR5_SPD_UDIMM:
+	case DDR5_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR5_SPD_SODIMM:
+	case DDR5_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR5_SPD_2DPC:
+		info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case LPX_SPD_NONDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_ROC;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info)
+{
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+		convert_ddr2_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR3:
+		convert_ddr3_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR4:
+		convert_ddr4_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR5:
+		convert_ddr5_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		convert_lpx_module_type_to_spd_info(module_type, info);
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static uint8_t convert_default_form_factor_to_module_type(void)
+{
+	return SPD_UNDEFINED;
+}
+
+static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_DIMM:
+		return DDR2_SPD_UDIMM;
+	case MEMORY_FORMFACTOR_RIMM:
+		return DDR2_SPD_RDIMM;
+	case MEMORY_FORMFACTOR_SODIMM:
+		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM
+				: DDR3_SPD_SODIMM;
+		return module_type;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor form_factor)
+{
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_ROC:
+		return LPX_SPD_NONDIMM;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+	case MEMORY_TYPE_DDR3:
+	case MEMORY_TYPE_DDR4:
+	case MEMORY_TYPE_DDR5:
+		module_type = convert_ddrx_form_factor_to_module_type(memory_type, form_factor);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		module_type = convert_lpx_form_factor_to_module_type(form_factor);
+		break;
+	default:
+		module_type = convert_default_form_factor_to_module_type();
+		break;
+	}
+
+	return module_type;
+}

src/device/pci_ops.c

@@ -7,7 +7,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 
-u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
+u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 
 /**
  * Given a device, a capability type, and a last position, return the next

src/drivers/amd/agesa/romstage.c

@@ -36,22 +36,18 @@ static void romstage_main(void)
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
-	unsigned int initial_apic_id = initial_lapicid();
 	int cbmem_initted = 0;
 
 	fill_sysinfo(cb);
 
-	if (initial_apic_id == 0) {
+	timestamp_add_now(TS_START_ROMSTAGE);
 
-		timestamp_add_now(TS_START_ROMSTAGE);
+	board_BeforeAgesa(cb);
 
-		board_BeforeAgesa(cb);
+	console_init();
-
-		console_init();
-	}
 
 	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
-		initial_apic_id, cpuid_eax(1));
+	       initial_lapicid(), cpuid_eax(1));
 
 	set_ap_entry_ptr(ap_romstage_main);
 

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus with GC6 3.0
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+        // TODO: use GPU config to generate address
+	OperationRegion (RPCX, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus graphics device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}

src/drivers/intel/fsp1_1/romstage.c

@@ -103,9 +103,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* Display parameters */
-	if (!CONFIG(NO_MMCONF_SUPPORT))
+	if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
-		printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
+		printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n",
-			CONFIG_MMCONF_BASE_ADDRESS);
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using FSP 1.1\n");
 
 	/* Display FSP banner */

src/ec/system76/ec/Kconfig

@@ -13,6 +13,11 @@ config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	bool
 	default n
 
+config EC_SYSTEM76_EC_DGPU
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
 config EC_SYSTEM76_EC_OLED
 	depends on EC_SYSTEM76_EC
 	bool

src/ec/system76/ec/acpi/s76.asl

@@ -117,6 +117,9 @@ Device (S76D) {
 	Method (NFAN, 0, Serialized) {
 		Return (Package() {
 			"CPU fan",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU fan",
+#endif
 		})
 	}
 
@@ -144,6 +147,9 @@ Device (S76D) {
 	Method (NTMP, 0, Serialized) {
 		Return (Package() {
 			"CPU temp",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU temp",
+#endif
 		})
 	}
 

src/include/cpu/intel/cpu_ids.h

@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1

src/include/device/azalia_device.h

@@ -23,6 +23,8 @@ int azalia_enter_reset(u8 *base);
 int azalia_exit_reset(u8 *base);
 u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb);
 int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size);
+void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes);
+void azalia_codecs_init(u8 *base, u16 codec_mask);
 void azalia_audio_init(struct device *dev);
 extern struct device_operations default_azalia_audio_ops;
 

src/include/device/dram/spd.h

@@ -3,8 +3,18 @@
 #ifndef DEVICE_DRAM_SPD_H
 #define DEVICE_DRAM_SPD_H
 
+#include <smbios.h>
 #include <types.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id);
 
+struct spd_info {
+	uint16_t type_detail;
+	uint8_t form_factor;
+};
+
+void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info);
+uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor);
+
 #endif /* DEVICE_DRAM_SPD_H */

src/include/device/pci_ids.h

@@ -3332,6 +3332,10 @@
 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6		0x4b3d
 #define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7		0x4b3e
 
+#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP1		0x464d
+#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP2		0x460d
+#define PCI_DEVICE_ID_INTEL_ADL_P_PCIE_RP3		0x463d
+
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP1		0x51b8
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP2		0x51b9
 #define PCI_DEVICE_ID_INTEL_ADP_P_PCIE_RP3		0x51ba

src/include/device/pci_mmio_cfg.h

@@ -25,17 +25,17 @@ union pci_bank {
 	uint32_t reg32[4096 / sizeof(uint32_t)];
 };
 
-#if CONFIG(MMCONF_SUPPORT)
+#if CONFIG(ECAM_MMCONF_SUPPORT)
 
-#if CONFIG_MMCONF_BASE_ADDRESS == 0
+#if CONFIG_ECAM_MMCONF_BASE_ADDRESS == 0
-#error "CONFIG_MMCONF_BASE_ADDRESS undefined!"
+#error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!"
 #endif
 
-#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH
+#if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH
-#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!"
+#error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!"
 #endif
 
-/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
+/* By not assigning this to CONFIG_ECAM_MMCONF_BASE_ADDRESS here we
    prevent some sub-optimal constant folding. */
 extern u8 *const pci_mmconf;
 

src/include/dimm_info_util.h

@@ -28,7 +28,7 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size,
  *
  * Use this when setting dimm_info.mod_type.
  */
-uint8_t
+uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type,
-smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor);
+		smbios_memory_form_factor form_factor);
 
 #endif

src/include/rules.h

@@ -292,6 +292,17 @@
 #define ENV_INITIAL_STAGE		ENV_BOOTBLOCK
 #endif
 
+#if ENV_X86
+#define STAGE_HAS_SPINLOCKS		!ENV_ROMSTAGE_OR_BEFORE
+#elif ENV_RISCV
+#define STAGE_HAS_SPINLOCKS		1
+#else
+#define STAGE_HAS_SPINLOCKS		0
+#endif
+
+/* When set <arch/smp/spinlock.h> is included for the spinlock implementation. */
+#define ENV_STAGE_SUPPORTS_SMP		(CONFIG(SMP) && STAGE_HAS_SPINLOCKS)
+
 /**
  * For pre-DRAM stages and post-CAR always build with simple device model, ie.
  * PCI, PNP and CPU functions operate without use of devicetree. The reason

src/include/smp/spinlock.h

@@ -1,7 +1,7 @@
 #ifndef SMP_SPINLOCK_H
 #define SMP_SPINLOCK_H
 
-#if CONFIG(SMP)
+#if ENV_STAGE_SUPPORTS_SMP
 #include <arch/smp/spinlock.h>
 #else /* !CONFIG_SMP */
 

src/include/spd.h

@@ -197,18 +197,70 @@ enum spd_memory_type {
 #define MODULE_BUFFERED                  1
 #define MODULE_REGISTERED                2
 
-/* Byte 3: Module type information */
 #define SPD_UNDEFINED 0x00
-#define SPD_RDIMM 0x01
-#define SPD_UDIMM 0x02
-#define SPD_SODIMM 0x04
-#define SPD_72B_SO_CDIMM 0x06
-#define SPD_72B_SO_RDIMM 0x07
-#define SPD_MICRO_DIMM 0x08
-#define SPD_MINI_RDIMM 0x10
-#define SPD_MINI_UDIMM 0x20
-
 #define SPD_ECC_8BIT (1<<3)
 #define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
 
+/* Byte 3: Module type information */
+enum ddr2_module_type {
+	DDR2_SPD_RDIMM = 0x01,
+	DDR2_SPD_UDIMM = 0x02,
+	DDR2_SPD_SODIMM = 0x04,
+	DDR2_SPD_72B_SO_CDIMM = 0x06,
+	DDR2_SPD_72B_SO_RDIMM = 0x07,
+	DDR2_SPD_MICRO_DIMM = 0x08,
+	DDR2_SPD_MINI_RDIMM = 0x10,
+	DDR2_SPD_MINI_UDIMM = 0x20,
+};
+
+enum ddr3_module_type {
+	DDR3_SPD_RDIMM = 0x01,
+	DDR3_SPD_UDIMM = 0x02,
+	DDR3_SPD_SODIMM = 0x03,
+	DDR3_SPD_MICRO_DIMM = 0x04,
+	DDR3_SPD_MINI_RDIMM = 0x05,
+	DDR3_SPD_MINI_UDIMM = 0x06,
+	DDR3_SPD_MINI_CDIMM = 0x07,
+	DDR3_SPD_72B_SO_UDIMM = 0x08,
+	DDR3_SPD_72B_SO_RDIMM = 0x09,
+	DDR3_SPD_72B_SO_CDIMM = 0x0a,
+	DDR3_SPD_LRDIMM = 0x0b,
+	DDR3_SPD_16B_SO_DIMM = 0x0c,
+	DDR3_SPD_32B_SO_RDIMM = 0x0d,
+};
+
+enum ddr4_module_type {
+	DDR4_SPD_RDIMM = 0x01,
+	DDR4_SPD_UDIMM = 0x02,
+	DDR4_SPD_SODIMM = 0x03,
+	DDR4_SPD_LRDIMM = 0x04,
+	DDR4_SPD_MINI_RDIMM = 0x05,
+	DDR4_SPD_MINI_UDIMM = 0x06,
+	DDR4_SPD_72B_SO_UDIMM = 0x08,
+	DDR4_SPD_72B_SO_RDIMM = 0x09,
+	DDR4_SPD_16B_SO_DIMM = 0x0c,
+	DDR4_SPD_32B_SO_RDIMM = 0x0d,
+};
+
+enum ddr5_module_type {
+	DDR5_SPD_RDIMM = 0x01,
+	DDR5_SPD_UDIMM = 0x02,
+	DDR5_SPD_SODIMM = 0x03,
+	DDR5_SPD_LRDIMM = 0x04,
+	DDR5_SPD_MINI_RDIMM = 0x05,
+	DDR5_SPD_MINI_UDIMM = 0x06,
+	DDR5_SPD_72B_SO_UDIMM = 0x08,
+	DDR5_SPD_72B_SO_RDIMM = 0x09,
+	DDR5_SPD_SOLDERED_DOWN = 0x0b,
+	DDR5_SPD_16B_SO_DIMM = 0x0c,
+	DDR5_SPD_32B_SO_RDIMM = 0x0d,
+	DDR5_SPD_1DPC = 0x0e,
+	DDR5_SPD_2DPC = 0x0f,
+};
+
+enum lpx_module_type {
+	LPX_SPD_LPDIMM = 0x07,
+	LPX_SPD_NONDIMM = 0x0e,
+};
+
 #endif

src/lib/Kconfig

@@ -70,7 +70,7 @@ config HWBASE_DYNAMIC_MMIO
 
 config HWBASE_DEFAULT_MMCONF
 	hex
-	default MMCONF_BASE_ADDRESS
+	default ECAM_MMCONF_BASE_ADDRESS
 
 config HWBASE_DIRECT_PCIDEV
 	def_bool y

src/lib/dimm_info_util.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <device/dram/spd.h>
 #include <dimm_info_util.h>
 #include <smbios.h>
 #include <spd.h>
@@ -72,18 +73,8 @@ uint32_t smbios_memory_size_to_mib(uint16_t memory_size, uint32_t extended_size)
 		return memory_size;
 }
 
-uint8_t
+uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type,
-smbios_form_factor_to_spd_mod_type(smbios_memory_form_factor form_factor)
+		smbios_memory_form_factor form_factor)
 {
-	/* This switch reverses the switch in smbios.c */
+	return convert_form_factor_to_module_type(memory_type, form_factor);
-	switch (form_factor) {
-	case MEMORY_FORMFACTOR_DIMM:
-		return SPD_UDIMM;
-	case MEMORY_FORMFACTOR_RIMM:
-		return SPD_RDIMM;
-	case MEMORY_FORMFACTOR_SODIMM:
-		return SPD_SODIMM;
-	default:
-		return SPD_UNDEFINED;
-	}
 }

src/lib/thread.c

@@ -398,10 +398,10 @@ enum cb_err thread_join(struct thread_handle *handle)
 	if (handle->state == THREAD_UNINITIALIZED)
 		return CB_ERR_ARG;
 
-	stopwatch_init(&sw);
-
 	printk(BIOS_SPEW, "waiting for thread\n");
 
+	stopwatch_init(&sw);
+
 	while (handle->state != THREAD_DONE)
 		assert(thread_yield() == 0);
 

src/mainboard/amd/majolica/chromeos.c

@@ -3,6 +3,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void fill_lb_gpios(struct lb_gpios *gpios)

src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c

@@ -85,7 +85,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
 		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
 		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,

src/mainboard/emulation/qemu-i440fx/Kconfig

@@ -3,7 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_QEMU_X86
-	select NO_MMCONF_SUPPORT
+	select NO_ECAM_MMCONF_SUPPORT
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select HAVE_OPTION_TABLE
 	select HAVE_CMOS_DEFAULT

src/mainboard/emulation/qemu-q35/Kconfig

@@ -56,10 +56,10 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "QEMU x86 q35/ich9"
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xb0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 

src/mainboard/emulation/qemu-q35/bootblock.c

@@ -11,12 +11,12 @@ static void bootblock_northbridge_init(void)
 {
 	/*
 	 * The "io" variant of the config access is explicitly used to
-	 * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
+	 * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
 	 * to true. That way all subsequent non-explicit config accesses use
 	 * MCFG. This code also assumes that bootblock_northbridge_init() is
 	 * the first thing called in the non-asm boot block code. The final
 	 * assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under
 	 * 4GiB.

src/mainboard/emulation/qemu-q35/chromeos.c

@@ -2,6 +2,7 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void fill_lb_gpios(struct lb_gpios *gpios)

src/mainboard/emulation/qemu-q35/memmap.c

@@ -14,7 +14,7 @@
 
 static uint32_t encode_pciexbar_length(void)
 {
-	switch (CONFIG_MMCONF_BUS_NUMBER) {
+	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
 		case 256: return 0 << 1;
 		case 128: return 1 << 1;
 		case  64: return 2 << 1;
@@ -24,7 +24,7 @@ static uint32_t encode_pciexbar_length(void)
 
 uint32_t make_pciexbar(void)
 {
-	return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 }
 
 /* Check that MCFG is active. If it's not, QEMU was started for machine PC */

src/mainboard/google/auron/chromeos.c

@@ -2,12 +2,12 @@
 
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/chromeos.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 
-/* SPI Write protect is GPIO 16 */
+#include "onboard.h"
-#define CROS_WP_GPIO	58
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {

src/mainboard/google/auron/onboard.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AURON_ONBOARD_H
+#define AURON_ONBOARD_H
+
+/* SPI Write protect is GPIO 58 */
+#define CROS_WP_GPIO	58
+
+#endif

src/mainboard/google/beltino/chromeos.c

@@ -6,10 +6,9 @@
 #include <device/device.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-
+#include "onboard.h"
-#define GPIO_SPI_WP	58
-#define GPIO_REC_MODE	12
 
 #define FLAG_SPI_WP	0
 #define FLAG_REC_MODE	1
@@ -26,6 +25,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
+static bool raw_write_protect_state(void)
+{
+	return get_gpio(GPIO_SPI_WP);
+}
+
+static bool raw_recovery_mode_switch(void)
+{
+	return !get_gpio(GPIO_REC_MODE);
+}
+
 int get_write_protect_state(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@@ -44,11 +53,11 @@ void init_bootmode_straps(void)
 	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
 
 	/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
-	if (get_gpio(GPIO_SPI_WP))
+	if (raw_write_protect_state())
 		flags |= (1 << FLAG_SPI_WP);
 
 	/* Recovery: GPIO12 = RECOVERY_L, active low */
-	if (!get_gpio(GPIO_REC_MODE))
+	if (raw_recovery_mode_switch())
 		flags |= (1 << FLAG_REC_MODE);
 
 	/* Developer: Virtual */

src/mainboard/google/beltino/onboard.h

@@ -16,6 +16,12 @@
 /* WLAN wake is GPIO 10 */
 #define WLAN_WAKE_GPIO		10
 
+/* Recovery: GPIO12 = RECOVERY_L, active low */
+#define GPIO_REC_MODE	12
+
+/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+#define GPIO_SPI_WP	58
+
 /* IT8772F defs */
 #define IT8772F_BASE 0x2e
 #define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1)

src/mainboard/google/brya/Kconfig

@@ -14,12 +14,15 @@ config BOARD_GOOGLE_BRYA_COMMON
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_ALC1015
+	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_NAU8825
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_INTEL_DPTF
+	select PMC_IPC_ACPI_INTERFACE
+	select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER

src/mainboard/google/brya/Kconfig.name

@@ -27,6 +27,7 @@ config BOARD_GOOGLE_GIMBLE
 	bool "->  Gimble"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
 	select CHROMEOS_DSM_CALIB if CHROMEOS
+	select CHROMEOS_DSM_PARAM_FILE_NAME if CHROMEOS
 	select DRIVERS_I2C_MAX98390
 
 config BOARD_GOOGLE_REDRIX

src/mainboard/google/brya/chromeos.c

@@ -5,6 +5,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void fill_lb_gpios(struct lb_gpios *gpios)

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -68,6 +68,9 @@ chip soc/intel/alderlake
 	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
 	register "PchHdaIDispCodecEnable" = "1"
 
+        # FIVR RFI Spread Spectrum 1.5%
+        register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/baseboard/brask/gpio.c

@@ -2,7 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <commonlib/helpers.h>
+#include <types.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -318,9 +318,9 @@ static const struct pad_config gpio_table[] = {
 	/* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
 	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 	/* R6 : I2S2_TXD ==> DMIC_CLK1_R */
-	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 	/* R7 : I2S2_RXD ==> DMIC_DATA1_R */
-	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 
 	/* S0 : SNDW0_CLK ==> NC */
 	PAD_NC(GPP_S0, NONE),

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -74,6 +74,9 @@ chip soc/intel/alderlake
 	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
 	register "PchHdaIDispCodecEnable" = "1"
 
+	# FIVR RFI Spread Spectrum 1.5%
+	register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/baseboard/brya/gpio.c

@@ -2,7 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <commonlib/helpers.h>
+#include <types.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/mainboard/google/brya/variants/felwinter/overridetree.cb

@@ -7,7 +7,7 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	register "SaGv" = "SaGv_Disabled"
+	register "SaGv" = "SaGv_Enabled"
 
 	# FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn
 	# bypass rails implemented.
@@ -132,16 +132,16 @@ chip soc/intel/alderlake
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
 				device generic 0 on
-					chip drivers/intel/pmc_mux/conn
-						register "usb2_port_number" = "2"
-						register "usb3_port_number" = "2"
-						device generic 1 alias conn1 on end
-					end
 					chip drivers/intel/pmc_mux/conn
 						register "usb2_port_number" = "3"
 						register "usb3_port_number" = "3"
 						device generic 2 alias conn2 on end
 					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "2"
+						register "usb3_port_number" = "2"
+						device generic 1 alias conn1 on end
+					end
 				end
 			end
 		end

src/mainboard/google/brya/variants/gimble/overridetree.cb

@@ -34,6 +34,7 @@ chip soc/intel/alderlake
 	register "SaGv" = "SaGv_Enabled"
 	register "TcssAuxOri" = "1"
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+	register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
 	register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
 	register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
@@ -135,7 +136,7 @@ chip soc/intel/alderlake
 				register "name" = ""MXW0""
 				register "r0_calib_key" = ""dsm_calib_r0_0""
 				register "temperature_calib_key" = ""dsm_calib_temp_0""
-				register "dsm_param_file_name" = ""dsm_param""
+				register "dsm_param_file_name" = ""dsm_param_R""
 				register "vmon_slot_no" = "0"
 				register "imon_slot_no" = "1"
 				device i2c 0x38 on
@@ -147,7 +148,7 @@ chip soc/intel/alderlake
 				register "name" = ""MXW1""
 				register "r0_calib_key" = ""dsm_calib_r0_1""
 				register "temperature_calib_key" = ""dsm_calib_temp_1""
-				register "dsm_param_file_name" = ""dsm_param""
+				register "dsm_param_file_name" = ""dsm_param_L""
 				register "vmon_slot_no" = "1"
 				register "imon_slot_no" = "0"
 				device i2c 0x3c on

src/mainboard/google/brya/variants/kano/gpio.c

@@ -30,10 +30,14 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_D3, NONE),
 	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6  : SRCCLKREQ1# ==> APU_PEN_DETECT_ODL */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D6, NONE, PLTRST),
 	/* D7  : SRCCLKREQ2# ==> NC */
 	PAD_NC(GPP_D7, NONE),
 	/* D8  : SRCCLKREQ3# ==> NC */
 	PAD_NC(GPP_D8, NONE),
+	/* D17  : UART1_RXD ==> APU_PEN_DETECT_ODL */
+	PAD_CFG_GPI_SCI(GPP_D17, NONE, DEEP, EDGE_SINGLE, NONE),
 	/* D18 : UART1_TXD ==> NC */
 	PAD_NC(GPP_D18, NONE),
 

src/mainboard/google/brya/variants/kano/overridetree.cb

@@ -15,6 +15,15 @@ end
 chip soc/intel/alderlake
 	register "SaGv" = "SaGv_Enabled"
 
+	# GPE configuration
+	register "pmc_gpe0_dw1" = "GPP_D"
+
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2_C1
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"		# Disable M.2 WWAN
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"		# Disable M.2 Bluetooth
+
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Disable M.2 WWAN
+
 	# FIVR configurations for kano are disabled since the board doesn't have V1p05 and Vnn
 	# bypass rails implemented.
 	register "ext_fivr_settings" = "{
@@ -223,6 +232,19 @@ chip soc/intel/alderlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 0x10 on end
 			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				# GPP_D6 is the IRQ source, and GPP_D17 is the wake source
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D6)"
+				register "key.wake_gpe" = "GPE0_DW1_17"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on end
+			end
 		end
 		device ref i2c2 on
 			chip drivers/i2c/sx9324

src/mainboard/google/brya/variants/primus/overridetree.cb

@@ -22,7 +22,16 @@ fw_config
 end
 
 chip soc/intel/alderlake
-
+	# This disabled autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses; need to clarify
+	# the minimum PCH IRQ pulse width with Intel, b/180111628
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "MaxDramSpeed" = "3733"
 

src/mainboard/google/brya/variants/redrix/overridetree.cb

@@ -34,6 +34,8 @@ chip soc/intel/alderlake
 	register "SaGv" = "SaGv_Enabled"
 
 	register "CnviBtAudioOffload" = "true"
+	# FIVR RFI Spread Spectrum 6%
+	register "FivrSpreadSpectrum" = "FIVR_SS_6"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+

src/mainboard/google/brya/variants/taeko/gpio.c

@@ -46,8 +46,8 @@ static const struct pad_config override_gpio_table[] = {
 
 	/* D3  : ISH_GP3 ==> NC */
 	PAD_NC(GPP_D3, NONE),
-	/* D5  : SRCCLKREQ0# ==> NC */
+	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
-	PAD_NC(GPP_D5, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 	/* D9  : ISH_SPI_CS# ==> NC */
 	PAD_NC(GPP_D9, NONE),
 	/* D10 : ISH_SPI_CLK ==> NC */
@@ -174,6 +174,27 @@ static const struct pad_config early_gpio_table[] = {
 	 * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 	 */
 	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* CPU PCIe VGPIO for PEG60 */
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
+	PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
 };
 
 const struct pad_config *variant_gpio_override_table(size_t *num)

src/mainboard/google/brya/variants/taeko/overridetree.cb

@@ -221,6 +221,13 @@ chip soc/intel/alderlake
 				device generic 0 alias dptf_policy on end
 			end
 		end
+		device ref pcie4_0 on
+			# Enable CPU PCIE RP 1 using CLK 0
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_req = 0,
+				.clk_src = 0,
+			}"
+		end
 		device ref tbt_pcie_rp0 off end
 		device ref tbt_pcie_rp1 off end
 		device ref tbt_pcie_rp2 off end

src/mainboard/google/butterfly/chromeos.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
@@ -8,12 +7,10 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include <ec/quanta/ene_kb3940q/ec.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
-
+#include "onboard.h"
-#define WP_GPIO		6
-#define DEVMODE_GPIO	54
-#define FORCE_RECOVERY_MODE	0
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
@@ -42,23 +39,13 @@ int get_lid_switch(void)
 	return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1;
 }
 
+/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */
 int get_recovery_mode_switch(void)
 {
-	int ec_rec_mode = 0;
+	if (ENV_RAMSTAGE)
+		return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO);
 
-	if (FORCE_RECOVERY_MODE) {
+	return 0;
-		printk(BIOS_DEBUG, "FORCING RECOVERY MODE.\n");
-		return 1;
-	}
-
-	if (ENV_RAMSTAGE) {
-		if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO)
-			ec_rec_mode = 1;
-
-		printk(BIOS_DEBUG, "RECOVERY MODE FROM EC: %x\n", ec_rec_mode);
-	}
-
-	return ec_rec_mode;
 }
 
 static const struct cros_gpio cros_gpios[] = {

src/mainboard/google/butterfly/early_init.c

@@ -79,7 +79,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
 		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
 		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,

src/mainboard/google/butterfly/onboard.h

@@ -16,4 +16,8 @@
 
 /* 0x00: White LINK LED and Amber ACTIVE LED */
 #define BUTTERFLY_NIC_LED_MODE		0x00
+
+/* SPI write protect, active low */
+#define WP_GPIO		6
+
 #endif

src/mainboard/google/corsola/Kconfig

@@ -22,6 +22,8 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	string
 	default "Corsola" if BOARD_GOOGLE_CORSOLA
+	default "Kingler" if BOARD_GOOGLE_KINGLER
+	default "Krabby" if BOARD_GOOGLE_KRABBY
 
 config BOOT_DEVICE_SPI_FLASH_BUS
 	int

src/mainboard/google/corsola/Kconfig.name

@@ -3,3 +3,11 @@ comment "Corsola"
 config BOARD_GOOGLE_CORSOLA
 	bool "->  Corsola"
 	select BOARD_GOOGLE_CORSOLA_COMMON
+
+config BOARD_GOOGLE_KINGLER
+	bool "->  Kingler"
+	select BOARD_GOOGLE_CORSOLA_COMMON
+
+config BOARD_GOOGLE_KRABBY
+	bool "->  Krabby"
+	select BOARD_GOOGLE_CORSOLA_COMMON

src/mainboard/google/corsola/Makefile.inc

@@ -8,9 +8,11 @@ verstage-y += reset.c
 
 romstage-y += memlayout.ld
 romstage-y += chromeos.c
+romstage-y += regulator.c
 romstage-y += romstage.c
 
 ramstage-y += memlayout.ld
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
+ramstage-y += regulator.c
 ramstage-y += reset.c

src/mainboard/google/corsola/mainboard.c

@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <soc/usb.h>
 
 static void mainboard_init(struct device *dev)
 {
+	setup_usb_host();
 }
 
 static void mainboard_enable(struct device *dev)

src/mainboard/google/corsola/regulator.c

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <soc/mt6366.h>
+#include <soc/regulator.h>
+
+#define REGULATOR_NOT_SUPPORT -1
+
+static const int regulator_id[] = {
+	[MTK_REGULATOR_VDD1] = REGULATOR_NOT_SUPPORT,
+	[MTK_REGULATOR_VDD2] = REGULATOR_NOT_SUPPORT,
+	[MTK_REGULATOR_VDDQ] = MT6366_VDDQ,
+	[MTK_REGULATOR_VMDDR] = REGULATOR_NOT_SUPPORT,
+	[MTK_REGULATOR_VCORE] = MT6366_VCORE,
+	[MTK_REGULATOR_VCC] = REGULATOR_NOT_SUPPORT,
+	[MTK_REGULATOR_VCCQ] = REGULATOR_NOT_SUPPORT,
+	[MTK_REGULATOR_VDRAM1] = MT6366_VDRAM1,
+	[MTK_REGULATOR_VMCH] = MT6366_VMCH,
+	[MTK_REGULATOR_VMC] = MT6366_VMC,
+};
+
+_Static_assert(ARRAY_SIZE(regulator_id) == MTK_REGULATOR_NUM, "regulator_id size error");
+
+void mainboard_set_regulator_vol(enum mtk_regulator regulator,
+				 uint32_t voltage_uv)
+{
+	assert(regulator < MTK_REGULATOR_NUM);
+
+	if (regulator_id[regulator] < 0) {
+		printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator);
+		return;
+	}
+	mt6366_set_voltage(regulator_id[regulator], voltage_uv);
+}
+
+uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator)
+{
+	assert(regulator < MTK_REGULATOR_NUM);
+
+	if (regulator_id[regulator] < 0) {
+		printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator);
+		return 0;
+	}
+	return mt6366_get_voltage(regulator_id[regulator]);
+}

src/mainboard/google/corsola/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/stages.h>
+#include <soc/mt6366.h>
 
 void platform_romstage_main(void)
 {
+	mt6366_init();
 }

src/mainboard/google/cyan/chromeos.c

@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* The WP status pin lives on MF_ISH_GPIO_4 */

src/mainboard/google/daisy/chromeos.c

@@ -5,6 +5,7 @@
 #include <ec/google/chromeec/ec_commands.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <bootmode.h>
 

src/mainboard/google/dedede/Kconfig.name

@@ -150,6 +150,7 @@ config BOARD_GOOGLE_BUGZZY
 	select BASEBOARD_DEDEDE_LAPTOP
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_DA7219
+	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 
 config BOARD_GOOGLE_CORORI
 	bool "->  Corori"

src/mainboard/google/dedede/chromeos.c

@@ -5,6 +5,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void fill_lb_gpios(struct lb_gpios *gpios)

src/mainboard/google/dedede/variants/baseboard/gpio.c

@@ -2,7 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <commonlib/helpers.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage*/

src/mainboard/google/dedede/variants/bugzzy/overridetree.cb

@@ -63,12 +63,18 @@ chip soc/intel/jasperlake
 		},
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 133,
+			.fall_time_ns = 29,
 		},
 		.i2c[2] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 227,
+			.fall_time_ns = 9,
 		},
 		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 91,
+			.fall_time_ns = 2,
 		},
 		.i2c[4] = {
 			.speed = I2C_SPEED_FAST,
@@ -114,10 +120,10 @@ chip soc/intel/jasperlake
 					}
 				}"
 				register "controls.charger_perf" = "{
-					[0] = {  55, 3500 },
+					[0] = { 255, 2800 },
-					[1] = {  47, 3000 },
+					[1] = {  39, 2500 },
-					[2] = {  39, 2500 },
+					[2] = {  31, 2000 },
-					[3] = {  31, 2000 },
+					[3] = {  23, 1500 },
 				}"
 				device generic 0 on end
 			end

src/mainboard/google/dedede/variants/galtic/variant.c

@@ -1,9 +1,31 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <ec/google/chromeec/ec.h>
 #include <fw_config.h>
 #include <sar.h>
 
+enum {
+	GALTIC_SKU_START    = 0x120000,
+	GALTIC_SKU_END      = 0x12ffff,
+	GALITH_SKU_START    = 0x130000,
+	GALITH_SKU_END      = 0x13ffff,
+	GALLOP_SKU_START    = 0x150000,
+	GALLOP_SKU_END      = 0x15ffff,
+	GALTIC360_SKU_START = 0x260000,
+	GALTIC360_SKU_END   = 0x26ffff,
+	GALITH360_SKU_START = 0x270000,
+	GALITH360_SKU_END   = 0x27ffff,
+};
 const char *get_wifi_sar_cbfs_filename(void)
 {
-	return "wifi_sar-galtic.hex";
+	uint32_t sku_id = google_chromeec_get_board_sku();
+
+	if (sku_id >= GALTIC_SKU_START && sku_id <= GALTIC_SKU_END)
+		return "wifi_sar-galtic.hex";
+	if (sku_id >= GALTIC360_SKU_START && sku_id <= GALTIC360_SKU_END)
+		return "wifi_sar-galtic360.hex";
+	if (sku_id >= GALITH360_SKU_START && sku_id <= GALITH360_SKU_END)
+		return "wifi_sar-galith360.hex";
+
+	return WIFI_SAR_CBFS_DEFAULT_FILENAME;
 }

src/mainboard/google/dedede/variants/magolor/overridetree.cb

@@ -19,6 +19,7 @@ fw_config
 		option TS_RAYD_0001 4
 		option TS_WDHT0002 5
 		option TS_GTCH7503 6
+		option TS_ELAN_9004 7
 	end
 	field AUDIO_CODEC_SOURCE 49 51
 		option AUDIO_CODEC_UNPROVISIONED 0
@@ -227,6 +228,26 @@ chip soc/intel/jasperlake
 					probe TS_SOURCE TS_ELAN_6918
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TS_SOURCE TS_ELAN_9004
+				end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WDHT0002""
 				register "generic.desc" = ""WDT Touchscreen""

src/mainboard/google/dedede/variants/metaknight/overridetree.cb

@@ -243,15 +243,28 @@ chip soc/intel/jasperlake
 				register "hid" = ""10EC1015""
 				register "desc" = ""Realtek SPK AMP L""
 				register "uid" = "0"
-				device i2c 28 on end
+				device i2c 28 on
+					probe AUDIO_AMP UNPROVISIONED
+					probe AUDIO_AMP RT1015_I2C
+				end
 			end
 			chip drivers/i2c/generic
 				register "hid" = ""10EC1015""
 				register "desc" = ""Realtek SPK AMP R""
 				register "uid" = "1"
-				device i2c 29 on end
+				device i2c 29 on
+					probe AUDIO_AMP UNPROVISIONED
+					probe AUDIO_AMP RT1015_I2C
+				end
 			end
 		end
-		device pci 1f.3 on end # Intel HDA
+		device pci 1f.3 on
+			chip drivers/generic/alc1015
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
+				device generic 0 on
+					probe AUDIO_AMP RT1015P_AUTO
+				end
+			end
+		end # Intel HDA
 	end
 end

src/mainboard/google/deltaur/chromeos.c

@@ -8,6 +8,7 @@
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <security/tpm/tss.h>
 #include <device/device.h>
@@ -32,24 +33,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
-static int cros_get_gpio_value(int type)
+int get_write_protect_state(void)
 {
-	const struct cros_gpio *cros_gpios;
+	return gpio_get(GPIO_PCH_WP);
-	size_t i, num_gpios = 0;
+}
 
-	cros_gpios = variant_cros_gpios(&num_gpios);
+static bool raw_get_recovery_mode_switch(void)
-
+{
-	for (i = 0; i < num_gpios; i++) {
+	return !gpio_get(GPIO_REC_MODE);
-		const struct cros_gpio *gpio = &cros_gpios[i];
-		if (gpio->type == type) {
-			int state = gpio_get(gpio->gpio_num);
-			if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
-				return !state;
-			else
-				return state;
-		}
-	}
-	return 0;
 }
 
 void mainboard_chromeos_acpi_generate(void)
@@ -62,11 +53,6 @@ void mainboard_chromeos_acpi_generate(void)
 	chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
 }
 
-int get_write_protect_state(void)
-{
-	return cros_get_gpio_value(CROS_GPIO_WP);
-}
-
 int get_recovery_mode_switch(void)
 {
 	static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
@@ -92,7 +78,7 @@ int get_recovery_mode_switch(void)
 		state = REC_MODE_REQUESTED;
 
 	/* Read state from the GPIO controlled by servo. */
-	if (cros_get_gpio_value(CROS_GPIO_REC))
+	if (raw_get_recovery_mode_switch())
 		state = REC_MODE_REQUESTED;
 
 	/* Store the state in case this is called again in verstage. */

src/mainboard/google/drallion/chromeos.c

@@ -6,6 +6,7 @@
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <security/tpm/tss.h>
 #include <device/device.h>
@@ -30,24 +31,14 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
-static int cros_get_gpio_value(int type)
+int get_write_protect_state(void)
 {
-	const struct cros_gpio *cros_gpios;
+	return gpio_get(GPP_E15);
-	size_t i, num_gpios = 0;
+}
 
-	cros_gpios = variant_cros_gpios(&num_gpios);
+static bool raw_get_recovery_mode_switch(void)
-
+{
-	for (i = 0; i < num_gpios; i++) {
+	return !gpio_get(GPP_E8);
-		const struct cros_gpio *gpio = &cros_gpios[i];
-		if (gpio->type == type) {
-			int state = gpio_get(gpio->gpio_num);
-			if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
-				return !state;
-			else
-				return state;
-		}
-	}
-	return 0;
 }
 
 void mainboard_chromeos_acpi_generate(void)
@@ -60,11 +51,6 @@ void mainboard_chromeos_acpi_generate(void)
 	chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
 }
 
-int get_write_protect_state(void)
-{
-	return cros_get_gpio_value(CROS_GPIO_WP);
-}
-
 int get_recovery_mode_switch(void)
 {
 	static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
@@ -90,7 +76,7 @@ int get_recovery_mode_switch(void)
 		state = REC_MODE_REQUESTED;
 
 	/* Read state from the GPIO controlled by servo. */
-	if (cros_get_gpio_value(CROS_GPIO_REC))
+	if (raw_get_recovery_mode_switch())
 		state = REC_MODE_REQUESTED;
 
 	/* Store the state in case this is called again in verstage. */

src/mainboard/google/eve/chromeos.c

@@ -4,6 +4,7 @@
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
 #include <soc/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 #include "gpio.h"

src/mainboard/google/fizz/chromeos.c

@@ -5,6 +5,7 @@
 #include <gpio.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 #include <variant/gpio.h>

src/mainboard/google/fizz/variants/baseboard/gpio.c

@@ -2,7 +2,7 @@
 
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <commonlib/helpers.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */

src/mainboard/google/glados/chromeos.c

@@ -4,6 +4,7 @@
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
 #include <soc/gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <variant/gpio.h>
 

src/mainboard/google/guybrush/bootblock.c

@@ -31,8 +31,8 @@ void mb_set_up_early_espi(void)
 void bootblock_mainboard_early_init(void)
 {
 	uint32_t dword;
-	size_t base_num_gpios, override_num_gpios;
+	size_t num_gpios, override_num_gpios;
-	const struct soc_amd_gpio *base_gpios, *override_gpios;
+	const struct soc_amd_gpio *gpios, *override_gpios;
 
 	/* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped
 	   on Picasso and older compared to Renoir/Cezanne and newer */
@@ -50,11 +50,12 @@ void bootblock_mainboard_early_init(void)
 	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
 		return;
 
-	base_gpios = variant_early_gpio_table(&base_num_gpios);
+	gpios = variant_espi_gpio_table(&num_gpios);
-	override_gpios = variant_early_override_gpio_table(&override_num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 
-	gpio_configure_pads_with_override(base_gpios, base_num_gpios,
+	gpios = variant_early_gpio_table(&num_gpios);
-			override_gpios, override_num_gpios);
+	override_gpios = variant_early_override_gpio_table(&override_num_gpios);
+	gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios);
 
 	/* Set a timer to make sure there's enough delay for
 	 * the Fibocom 350 PCIe init
@@ -99,8 +100,4 @@ void bootblock_mainboard_init(void)
 
 	gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
 					  override_num_gpios);
-
-	/* FPMCU check needs to happen after EC initialization for FW_CONFIG bits */
-	if (variant_has_fpmcu())
-		variant_fpmcu_reset();
 }

src/mainboard/google/guybrush/chromeos.c

@@ -4,6 +4,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 void fill_lb_gpios(struct lb_gpios *gpios)

src/mainboard/google/guybrush/mainboard.c

@@ -209,13 +209,7 @@ static void mainboard_enable(struct device *dev)
 	pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
 }
 
-static void mainboard_final(void *chip_info)
-{
-	variant_finalize_gpios();
-}
-
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
 	.enable_dev = mainboard_enable,
-	.final = mainboard_final,
 };