mb/system76/adl: galp6: Fix GLAN RTD3

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I9d5cf318dcbbe4bda916b1a17469e1ad6b6b58e4

src/drivers/smmstore/ramstage.c

@@ -57,18 +57,22 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
-	/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
-	__asm__ __volatile__ (
-		"outb %%al, %%dx"
-		: "=a" (eax)
-		: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
-		  "b" (ebx),
-		  "d" (APM_CNT)
-		: "memory");
+	for (int retries = 0; retries < 3; retries++) {
+		/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
+		__asm__ __volatile__ (
+			"outb %%al, %%dx"
+			: "=a" (eax)
+			: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
+			  "b" (ebx),
+			  "d" (APM_CNT)
+			: "memory");
 
-	if (eax != SMMSTORE_RET_SUCCESS) {
-		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");
-		return;
+		if (eax == SMMSTORE_RET_SUCCESS) {
+			printk(BIOS_INFO, "SMMSTORE: Installed com buffer\n");
+			break;
+		}
+
+		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer: 0x%x\n", eax);
 	}
 }
 

src/mainboard/system76/adl/Kconfig

@@ -1,6 +1,7 @@
 config BOARD_SYSTEM76_ADL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID

src/mainboard/system76/adl/ramstage.c

@@ -23,6 +23,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
 
 	params->SataPortsSolidStateDrive[1] = 1;
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
 
 static void mainboard_init(void *chip_info)

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -151,12 +151,6 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
-				register "srcclk_pin" = "4" # SSD1_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux

src/mainboard/system76/adl/variants/galp6/gpio.c

@@ -7,7 +7,7 @@ static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
 	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
 	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
-	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+	PAD_NC(GPD2, NONE),
 	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
 	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
 	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
@@ -16,7 +16,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
 	PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
 	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
-	PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+	PAD_NC(GPD11, NONE),
 
 	/* ------- GPIO Group GPP_A ------- */
 	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
@@ -41,7 +41,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
 	PAD_NC(GPP_A20, NONE),
 	PAD_NC(GPP_A21, NONE),
-	PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
+	PAD_NC(GPP_A22, NONE),
 	PAD_NC(GPP_A23, NONE),
 
 	/* ------- GPIO Group GPP_B ------- */
@@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
-	PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST), // GPIO_LANRTD3
 	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
 	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
 	// GPP_C8 missing
@@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
 	// GPP_F5 (CNVI_CLKREQ) programmed by FSP
 	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
-	PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST), // LAN_PLT_RST#
 	// GPP_F8 missing
 	PAD_NC(GPP_F9, NONE),
 	PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#

src/mainboard/system76/adl/variants/galp6/overridetree.cb

@@ -165,6 +165,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C5)" # GPIO_LANRTD3
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
 				register "srcclk_pin" = "6" # LAN_CLKREQ#
 				device generic 0 on end

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -103,14 +103,6 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable tied to 3.3VS?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "disable_l23" = "true"
-				register "srcclk_pin" = "1" # SSD1_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp9 on
 			# PCIe RP#9 x1, Clock 6 (GLAN)
@@ -119,13 +111,6 @@ chip soc/intel/alderlake
 				.clk_req = 6,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable tied to VDD3?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "6" # GLAN_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp10 on
 			# PCIe RP#10 x1, Clock 2 (WLAN)
@@ -134,12 +119,6 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "2" # WLAN_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp11 on
 			# PCIe RP#11 x1, Clock 5 (CARD)
@@ -148,13 +127,6 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable tied to 3.3VS?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "5" # CARD_CLKREQ#
-				device generic 0 on end
-			end
 		end
 	end
 end

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -109,12 +109,6 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "2" # WLAN_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp6 on
 			# PCIe root port #6 x1, Clock 5 (CARD)
@@ -123,12 +117,6 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: No enable_gpio = no D3cold?
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "5" # CARD_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp7 on
 			# PCIe root port #7 x1, Clock 6 (GLAN)
@@ -147,14 +135,6 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable tied to 3.3VS?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "disable_l23" = "true" # Fixes suspend on WD drives
-				register "srcclk_pin" = "1" # SSD_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref gbe on end
 	end

src/mainboard/system76/adl/variants/lemp11/overridetree.cb

@@ -137,12 +137,6 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST#
-				register "srcclk_pin" = "1" # SSD1_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -150,12 +150,6 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "2" # WLAN_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 6 (CARD)
@@ -164,12 +158,6 @@ chip soc/intel/alderlake
 				.clk_req = 6,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable connected directly to 3.3VS?
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "6" # CARD_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie_rp8 on
 			# PCIe RP#8 x1, Clock 5 (GLAN)
@@ -178,15 +166,7 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable connected directly to VDD3?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "5" # GLAN_CLKREQ#
-				device generic 0 on end
-			end
 		end
-
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
 				device generic 0 on

src/mainboard/system76/cml-u/Makefile.inc

@@ -3,6 +3,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 bootblock-y += bootblock.c
 bootblock-y += gpio_early.c
 
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/rpl/Kconfig

@@ -1,6 +1,7 @@
 config BOARD_SYSTEM76_RPL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID

src/mainboard/system76/rpl/variants/addw3/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5200 MT/s memory
-	register "max_dram_speed_mts" = "5200"
+	# Support 5600 MT/s memory
+	register "max_dram_speed_mts" = "5600"
 
 	device domain 0 on
 		subsystemid 0x1558 0xa671 inherit

src/mainboard/system76/rpl/variants/bonw15/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5200 MT/s memory
-	register "max_dram_speed_mts" = "5200"
+	# Support 5600 MT/s memory
+	register "max_dram_speed_mts" = "5600"
 
 	device domain 0 on
 		subsystemid 0x1558 0x3702 inherit

src/mainboard/system76/rpl/variants/serw13/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5200 MT/s memory
-	register "max_dram_speed_mts" = "5200"
+	# Support 5600 MT/s memory
+	register "max_dram_speed_mts" = "5600"
 
 	device domain 0 on
 		subsystemid 0x1558 0xd502 inherit

src/mainboard/system76/tgl-h/Kconfig

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_GFX_NVIDIA

src/mainboard/system76/tgl-h/devicetree.cb

@@ -68,9 +68,6 @@ chip soc/intel/tigerlake
 	# rdmsr --bitfield 31:24 --decimal 0x1A2
 	register "tcc_offset" = "8"
 
-	# Enable CNVi BT
-	register "CnviBtCore" = "true"
-
 # PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "PMC_GPP_R"
@@ -103,6 +100,8 @@ chip soc/intel/tigerlake
 		# From PCH EDS(615985)
 		device ref shared_ram on end
 		device ref cnvi_wifi on
+			register "CnviBtCore" = true
+			register "CnviBtAudioOffload" = true
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end

src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c

@@ -18,4 +18,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Remap PEG2 as PEG1
 	params->CpuPcieRpFunctionSwap = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c

@@ -15,4 +15,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CpuPcieRpAdvancedErrorReporting[1] = 0;
 	params->CpuPcieRpLtrEnable[1] = 1;
 	params->CpuPcieRpPtmEnabled[1] = 0;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c

@@ -21,4 +21,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Low latency legacy I/O
 	params->PchLegacyIoLowLatency = 1;
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-u/devicetree.cb

@@ -62,9 +62,6 @@ chip soc/intel/tigerlake
 	# Thermal
 	register "tcc_offset" = "12"
 
-	# Enable CNVi BT
-	register "CnviBtCore" = "true"
-
 # Actual device tree
 	device cpu_cluster 0 on
 		device lapic 0 on end
@@ -90,6 +87,8 @@ chip soc/intel/tigerlake
 		device ref gna on end
 		device ref shared_ram on end
 		device ref cnvi_wifi on
+			register "CnviBtCore" = true
+			register "CnviBtAudioOffload" = true
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end

src/soc/intel/alderlake/cpu.c

@@ -301,10 +301,10 @@ uint8_t get_supported_lpm_mask(void)
 	case ADL_M: /* fallthrough */
 	case ADL_N:
 	case ADL_P:
-	case RPL_HX:
 	case RPL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:
+	case RPL_HX:
 		return LPM_S0i2_0 | LPM_S0i2_1;
 	default:
 		printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);

src/soc/intel/alderlake/include/soc/gpio.h

@@ -5,8 +5,13 @@
 
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 #include <soc/gpio_defs_pch_s.h>
+#if CONFIG(SOC_INTEL_RAPTORLAKE)
+#define CROS_GPIO_NAME		"INTC1085"
+#define CROS_GPIO_DEVICE_NAME	"INTC1085:00"
+#else
 #define CROS_GPIO_NAME		"INTC1056"
 #define CROS_GPIO_DEVICE_NAME	"INTC1056:00"
+#endif
 #elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 #include <soc/gpio_defs.h>
 #define CROS_GPIO_NAME		"INTC1057"

src/soc/intel/alderlake/include/soc/iomap.h

@@ -20,8 +20,14 @@
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
 #endif
 
+/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define PCH_PRESERVED_BASE_ADDRESS	0xe0000000
+#define PCH_PRESERVED_BASE_SIZE		0x1e800000
+#else
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE		0x02000000
+#endif
 
 #define UART_BASE_SIZE		0x1000