mb/system76/rpl: gaze18, serw13: Fix USB2 on USB-C port

Use USB2_PORT_MID instead of USB2_PORT_TYPE_C, as was done for addw3.

Change-Id: I7df2bbf1ba70c4e08319b760b2784e15c880a105
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/drivers/gfx/nvidia/romstage.c

@@ -19,15 +19,15 @@ void nvidia_set_power(const struct nvidia_gpu_config *config)
 	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
 
 	gpio_set(config->reset_gpio, 0);
-	mdelay(4);
+	mdelay(10);
 
 	if (config->enable) {
 		gpio_set(config->power_gpio, 1);
-		mdelay(4);
+		mdelay(25);
 		gpio_set(config->reset_gpio, 1);
 	} else {
 		gpio_set(config->power_gpio, 0);
 	}
 
-	mdelay(4);
+	mdelay(10);
 }

src/ec/system76/ec/Kconfig

@@ -18,6 +18,11 @@ config EC_SYSTEM76_EC_DGPU
 	bool
 	default n
 
+config EC_SYSTEM76_EC_LOCKDOWN
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
 config EC_SYSTEM76_EC_OLED
 	depends on EC_SYSTEM76_EC
 	bool

src/ec/system76/ec/Makefile.inc

@@ -2,6 +2,7 @@
 ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
 
 all-y += system76_ec.c
+ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
 smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
 
 endif

src/ec/system76/ec/lockdown.c

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/region.h>
+#include <fmap.h>
+#include <spi_flash.h>
+
+#include "system76_ec.h"
+
+static int protect_region_by_name(const char *name)
+{
+	int res;
+	struct region region;
+
+	res = fmap_locate_area(name, &region);
+	if (res < 0) {
+		printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	res = spi_flash_ctrlr_protect_region(
+		boot_device_spi_flash(),
+		&region,
+		WRITE_PROTECT
+	);
+	if (res < 0) {
+		printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	printk(BIOS_INFO, "protected '%s'\n", name);
+	return 0;
+}
+
+static void lock(void *unused)
+{
+	uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	if (system76_ec_security_get(&state) < 0) {
+		printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
+		state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	}
+
+	printk(BIOS_INFO, "security state: %d\n", state);
+	if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
+		// Protect WP_RO region, which should contain FMAP and COREBOOT
+		protect_region_by_name("WP_RO");
+		// Protect RW_MRC_CACHE region, this must be done after it is written
+		protect_region_by_name("RW_MRC_CACHE");
+		//TODO: protect entire flash except when in SMM?
+	}
+}
+
+/*
+ * Keep in sync with mrc_cache.c
+ */
+
+#if CONFIG(MRC_WRITE_NV_LATE)
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
+#else
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
+#endif

src/ec/system76/ec/system76_ec.c

@@ -3,6 +3,7 @@
 #include <arch/io.h>
 #include <console/system76_ec.h>
 #include <timer.h>
+#include "system76_ec.h"
 
 // This is the command region for System76 EC firmware. It must be
 // enabled for LPC in the mainboard.
@@ -11,15 +12,22 @@
 
 #define REG_CMD 0
 #define REG_RESULT 1
+#define REG_DATA 2
 
 // When command register is 0, command is complete
 #define CMD_FINISHED 0
 
 // Print command. Registers are unique for each command
 #define CMD_PRINT 4
-#define CMD_PRINT_REG_FLAGS 2
-#define CMD_PRINT_REG_LEN 3
-#define CMD_PRINT_REG_DATA 4
+#define CMD_PRINT_REG_FLAGS REG_DATA
+#define CMD_PRINT_REG_LEN (REG_DATA + 1)
+#define CMD_PRINT_REG_DATA (REG_DATA + 2)
+
+// Get security state command
+#define CMD_SECURITY_GET 20
+
+// OK result, any other values are errors
+#define RESULT_OK 0
 
 static inline uint8_t system76_ec_read(uint8_t addr)
 {
@@ -59,3 +67,81 @@ void system76_ec_print(uint8_t byte)
 	if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
 		system76_ec_flush();
 }
+
+// Issue a command not checking if the console needs to be flushed
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_unsafe(uint8_t cmd, uint8_t * data, int length) {
+	// Error if length is too long
+	if (length > (SYSTEM76_EC_SIZE - REG_DATA)) {
+		return -1;
+	}
+
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Write command data
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, data[i]);
+	}
+
+	// Start command
+	system76_ec_write(REG_CMD, cmd);
+
+	// Wait for command completion, for up to 10 milliseconds, with a
+	// test period of 1 microsecond
+	wait_us(10000, system76_ec_read(REG_CMD) == CMD_FINISHED);
+
+	// Error if command did not complete
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Read command data
+	for (int i = 0; i < length; i++) {
+		data[i] = system76_ec_read(REG_DATA + i);
+	}
+
+	// Check result
+	if (system76_ec_read(REG_RESULT) != RESULT_OK) {
+		return -1;
+	}
+
+	return 0;
+}
+
+// Wrapper to allow issuing commands while console is being used
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_command(uint8_t cmd, uint8_t * data, int length) {
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Flush print buffer if it has data
+	// Checked for completion by system76_ec_unsafe
+	if (system76_ec_read(CMD_PRINT_REG_LEN) > 0) {
+		system76_ec_flush();
+	}
+
+	// Run command now that print buffer is flushed
+	int res = system76_ec_unsafe(cmd, data, length);
+	if (res < 0) {
+		return res;
+	}
+
+	// Clear command data (for future prints)
+	// Length is checked by system76_ec_unsafe
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, 0);
+	}
+
+	return 0;
+}
+
+// Get security state
+int system76_ec_security_get(uint8_t * state) {
+	*state = 0;
+	return system76_ec_command(CMD_SECURITY_GET, state, sizeof(uint8_t));
+}

src/ec/system76/ec/system76_ec.h

@@ -0,0 +1,16 @@
+#ifndef EC_SYSTEM76_EC_H
+#define EC_SYSTEM76_EC_H
+
+// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
+// Flashing is allowed, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
+// Flashing will be prevented on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
+// Flashing will be allowed on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
+
+// Get security state
+int system76_ec_security_get(uint8_t * state);
+
+#endif /* EC_SYSTEM76_EC_H */

src/include/cpu/intel/cpu_ids.h

@@ -62,7 +62,11 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
-#define CPUID_RAPTORLAKE_P_J0		0xb06a2
-#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
+#define CPUID_RAPTORLAKE_E_S_HX_B0	0xb0671
+#define CPUID_RAPTORLAKE_HX_S_8_8_C0	0xb06f2
+#define CPUID_RAPTORLAKE_H_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_S_6_0_C0	0xb06f5
+#define CPUID_RAPTORLAKE_S_A0		0xb0670
+#define CPUID_RAPTORLAKE_U_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -3462,6 +3462,35 @@
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
 
+#define PCI_DID_INTEL_RPP_S_PCIE_RP1			0x7a38
+#define PCI_DID_INTEL_RPP_S_PCIE_RP2			0x7a39
+#define PCI_DID_INTEL_RPP_S_PCIE_RP3			0x7a3a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP4			0x7a3b
+#define PCI_DID_INTEL_RPP_S_PCIE_RP5			0x7a3c
+#define PCI_DID_INTEL_RPP_S_PCIE_RP6			0x7a3d
+#define PCI_DID_INTEL_RPP_S_PCIE_RP7			0x7a3e
+#define PCI_DID_INTEL_RPP_S_PCIE_RP8			0x7a3f
+#define PCI_DID_INTEL_RPP_S_PCIE_RP9			0x7a30
+#define PCI_DID_INTEL_RPP_S_PCIE_RP10			0x7a31
+#define PCI_DID_INTEL_RPP_S_PCIE_RP11			0x7a32
+#define PCI_DID_INTEL_RPP_S_PCIE_RP12			0x7a33
+#define PCI_DID_INTEL_RPP_S_PCIE_RP13			0x7a34
+#define PCI_DID_INTEL_RPP_S_PCIE_RP14			0x7a35
+#define PCI_DID_INTEL_RPP_S_PCIE_RP15			0x7a36
+#define PCI_DID_INTEL_RPP_S_PCIE_RP16			0x7a37
+#define PCI_DID_INTEL_RPP_S_PCIE_RP17			0x7a40
+#define PCI_DID_INTEL_RPP_S_PCIE_RP18			0x7a41
+#define PCI_DID_INTEL_RPP_S_PCIE_RP19			0x7a42
+#define PCI_DID_INTEL_RPP_S_PCIE_RP20			0x7a43
+#define PCI_DID_INTEL_RPP_S_PCIE_RP21			0x7a44
+#define PCI_DID_INTEL_RPP_S_PCIE_RP22			0x7a45
+#define PCI_DID_INTEL_RPP_S_PCIE_RP23			0x7a46
+#define PCI_DID_INTEL_RPP_S_PCIE_RP24			0x7a47
+#define PCI_DID_INTEL_RPP_S_PCIE_RP25			0x7a48
+#define PCI_DID_INTEL_RPP_S_PCIE_RP26			0x7a49
+#define PCI_DID_INTEL_RPP_S_PCIE_RP27			0x7a4a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP28			0x7a4b
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3536,6 +3565,7 @@
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
+#define PCI_DID_INTEL_RPP_S_SATA		0x7a62
 
 /* Intel PMC device Ids */
 #define PCI_DID_INTEL_SPT_LP_PMC		0x9d21
@@ -3671,6 +3701,13 @@
 #define PCI_DID_INTEL_ADP_M_N_I2C4		0x54c5
 #define PCI_DID_INTEL_ADP_M_N_I2C5		0x54c6
 
+#define PCI_DID_INTEL_RPP_S_I2C0		0x7a4c
+#define PCI_DID_INTEL_RPP_S_I2C1		0x7a4d
+#define PCI_DID_INTEL_RPP_S_I2C2		0x7a4e
+#define PCI_DID_INTEL_RPP_S_I2C3		0x7a4f
+#define PCI_DID_INTEL_RPP_S_I2C4		0x7a7c
+#define PCI_DID_INTEL_RPP_S_I2C5		0x7a7d
+
 #define PCI_DID_INTEL_MTL_I2C0			0x7e78
 #define PCI_DID_INTEL_MTL_I2C1			0x7e79
 #define PCI_DID_INTEL_MTL_I2C2			0x7e7a
@@ -3748,6 +3785,11 @@
 #define PCI_DID_INTEL_ADP_M_N_UART2		0x54c7
 #define PCI_DID_INTEL_ADP_M_N_UART3		0x54da
 
+#define PCI_DID_INTEL_RPP_S_UART0		0x7a28
+#define PCI_DID_INTEL_RPP_S_UART1		0x7a29
+#define PCI_DID_INTEL_RPP_S_UART2		0x7a7e
+#define PCI_DID_INTEL_RPP_S_UART3		0x7a5c
+
 #define PCI_DID_INTEL_MTL_UART0			0x7e25
 #define PCI_DID_INTEL_MTL_UART1			0x7e26
 #define PCI_DID_INTEL_MTL_UART2			0x7e52
@@ -3833,6 +3875,12 @@
 #define PCI_DID_INTEL_ADP_M_N_SPI1		0x54ab
 #define PCI_DID_INTEL_ADP_M_SPI2		0x54fb
 
+#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI		0x7a24
+#define PCI_DID_INTEL_RPP_S_SPI0		0x7a2a
+#define PCI_DID_INTEL_RPP_S_SPI1		0x7a2b
+#define PCI_DID_INTEL_RPP_S_SPI2		0x7a7b
+#define PCI_DID_INTEL_RPP_S_SPI3		0x7a79
+
 #define PCI_DID_INTEL_SPR_HWSEQ_SPI		0x1bca
 
 #define PCI_DID_INTEL_MTL_HWSEQ_SPI		0x7e23
@@ -3983,6 +4031,10 @@
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
+#define PCI_DID_INTEL_RPL_HX_GT1			0xa788
+#define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
+#define PCI_DID_INTEL_RPL_HX_GT3			0x4688
+#define PCI_DID_INTEL_RPL_HX_GT4			0x468b
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
@@ -4106,6 +4158,14 @@
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
+#define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
+#define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
+#define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
+#define PCI_DID_INTEL_RPL_HX_ID_4		0xa72a
+#define PCI_DID_INTEL_RPL_HX_ID_5		0xa719
+#define PCI_DID_INTEL_RPL_HX_ID_6		0x4637
+#define PCI_DID_INTEL_RPL_HX_ID_7		0x463b
+#define PCI_DID_INTEL_RPL_HX_ID_8		0x4647
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
@@ -4136,6 +4196,7 @@
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
+#define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4172,6 +4233,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
+#define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4240,6 +4302,14 @@
 #define PCI_DID_INTEL_ADP_S_AUDIO_8		0x7ad7
 #define PCI_DID_INTEL_ADP_P_AUDIO		0x51c8
 #define PCI_DID_INTEL_RPP_P_AUDIO		0x51ca
+#define PCI_DID_INTEL_RPP_S_AUDIO_1		0x7a50
+#define PCI_DID_INTEL_RPP_S_AUDIO_2		0x7a51
+#define PCI_DID_INTEL_RPP_S_AUDIO_3		0x7a52
+#define PCI_DID_INTEL_RPP_S_AUDIO_4		0x7a53
+#define PCI_DID_INTEL_RPP_S_AUDIO_5		0x7a54
+#define PCI_DID_INTEL_RPP_S_AUDIO_6		0x7a55
+#define PCI_DID_INTEL_RPP_S_AUDIO_7		0x7a56
+#define PCI_DID_INTEL_RPP_S_AUDIO_8		0x7a57
 
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1		0x54c8
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2		0x54c9
@@ -4296,6 +4366,10 @@
 #define PCI_DID_INTEL_ADP_M_CSE1		0x54e1
 #define PCI_DID_INTEL_ADP_M_CSE2		0x54e4
 #define PCI_DID_INTEL_ADP_M_CSE3		0x54e5
+#define PCI_DID_INTEL_RPP_S_CSE0		0x7a68
+#define PCI_DID_INTEL_RPP_S_CSE1		0x7a69
+#define PCI_DID_INTEL_RPP_S_CSE2		0x7a6c
+#define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 
 /* Intel XDCI device Ids */
@@ -4319,6 +4393,7 @@
 #define PCI_DID_INTEL_MTL_XDCI			0x7e7e
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
+#define PCI_DID_INTEL_RPP_S_XDCI		0x7a61
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4459,6 +4534,10 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1		0x7e41
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3		0x7a73
 
 /* Intel Crashlog */
 #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM		0x9a0d
@@ -4469,6 +4548,7 @@
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
+#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32

src/mainboard/system76/adl/Kconfig

@@ -1,38 +1,81 @@
-if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
+config BOARD_SYSTEM76_ADL_COMMON
+	def_bool n
 	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
-	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
-	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+	select EC_SYSTEM76_EC_LOCKDOWN
+	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
-	select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select NO_UART_ON_SUPERIO
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_ALDERLAKE_S3
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_CRASHLOG
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
+config BOARD_SYSTEM76_DARP8
+	select BOARD_SYSTEM76_ADL_COMMON
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+
+config BOARD_SYSTEM76_GALP6
+	select BOARD_SYSTEM76_ADL_COMMON
+
+config BOARD_SYSTEM76_GAZE17_3050
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_LEMP11
+	select BOARD_SYSTEM76_ADL_COMMON
+	select HAVE_SPD_IN_CBFS
+
+config BOARD_SYSTEM76_ORYP9
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_I2C_TAS5825M
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+
+config BOARD_SYSTEM76_ORYP10
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+
+if BOARD_SYSTEM76_ADL_COMMON
+
 config MAINBOARD_DIR
-	default "system76/adl-p"
+	default "system76/adl"
 
 config VARIANT_DIR
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -43,6 +86,8 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -50,25 +95,28 @@ config MAINBOARD_PART_NUMBER
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP8
 	default "Galago Pro" if BOARD_SYSTEM76_GALP6
+	default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
 	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
 
 config MAINBOARD_VERSION
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
-config CBFS_SIZE
-	default 0xA00000
-
 config CONSOLE_POST
 	default y
 
 config DIMM_SPD_SIZE
 	default 512
 
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
 config ONBOARD_VGA_IS_PRIMARY
 	default y
 

src/mainboard/system76/adl/Kconfig.name

@@ -4,6 +4,12 @@ config BOARD_SYSTEM76_DARP8
 config BOARD_SYSTEM76_GALP6
 	bool "galp6"
 
+config BOARD_SYSTEM76_GAZE17_3050
+	bool "gaze17 3050"
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+	bool "gaze17 3060-b"
+
 config BOARD_SYSTEM76_LEMP11
 	bool "lemp11"
 

src/mainboard/system76/adl/Makefile.inc

@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 

src/mainboard/system76/adl/board.fmd

@@ -0,0 +1,15 @@
+FLASH 32M {
+	SI_DESC 4K
+#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION
+	SI_GBE 8K
+#endif
+	SI_ME 4824K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/adl/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Enable
+me_state=Disable

src/mainboard/system76/adl/devicetree.cb

@@ -11,8 +11,6 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
-	register "s0ix_enable" = "1"
-
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 
@@ -72,9 +70,8 @@ chip soc/intel/alderlake
 		device ref heci1 on end
 		device ref sata on
 			register "sata_salp_support" = "1"
-			register "sata_ports_enable[1]" = "1" # SSD1
-			# FIXME: DevSlp breaks S0ix
-			#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
+			register "sata_ports_enable[1]" = "1"
+			register "sata_ports_dev_slp[1]" = "1"
 		end
 		device ref pch_espi on
 			register "gen1_dec" = "0x00040069" # EC PM channel

src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze17-3050
+Release year: 2022

src/mainboard/system76/adl/variants/gaze17-3050/gpio.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
-#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -221,7 +221,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_T3, NONE),
 };
 
-void variant_configure_gpios(void)
+void mainboard_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
@@ -10,7 +10,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
 };
 
-void variant_configure_early_gpios(void)
+void mainboard_configure_early_gpios(void)
 {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }

src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c

@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x1558866d, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x1558866d),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),

src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h

@@ -10,9 +10,4 @@
 #define DGPU_GC6	GPP_F13
 #define DGPU_SSID	0x866d1558
 
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
 #endif

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -1,16 +1,49 @@
 chip soc/intel/alderlake
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
 	device domain 0 on
 		subsystemid 0x1558 0x866d inherit
 
-		device ref igpu on
-			# DDIA is eDP
-			register "ddi_portA_config" = "1"
-			register "ddi_ports_config" = "{
-				[DDI_PORT_A] = DDI_ENABLE_HPD,
-				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+		device ref pcie5_0 on
+			# PCIe PEG2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
 			}"
-
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref pcie4_0 on
 			# PCIe PEG0 x4, Clock 0 (SSD2)
@@ -20,6 +53,34 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR,
 			}"
 		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 off end
+		device ref tbt_pcie_rp0 off end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			device ref tcss_root_hub on
+				device ref tcss_usb3_port1 on end
+			end
+		end
 		device ref xhci on
 			# USB2
 			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1

src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze17-3060-b
+Release year: 2022

src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
-#include <variant/gpio.h>
 
 static const struct pad_config gpio_table[] = {
 	/* ------- GPIO Group GPD ------- */
@@ -221,7 +221,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_T3, NONE),
 };
 
-void variant_configure_gpios(void)
+void mainboard_configure_gpios(void)
 {
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }

src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <variant/gpio.h>
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
@@ -8,7 +8,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
 };
 
-void variant_configure_early_gpios(void)
+void mainboard_configure_early_gpios(void)
 {
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }

src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c

@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x1558867c, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x1558867c),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),

src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h

@@ -10,9 +10,4 @@
 #define DGPU_GC6	GPP_F13
 #define DGPU_SSID	0x867c1558
 
-#ifndef __ACPI__
-void variant_configure_early_gpios(void);
-void variant_configure_gpios(void);
-#endif
-
 #endif

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -1,7 +1,50 @@
 chip soc/intel/alderlake
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
 	device domain 0 on
 		subsystemid 0x1558 0x867c inherit
 
+		device ref pcie5_0 on
+			# PCIe PEG2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
+		end
 		device ref igpu on
 			# DDIA is eDP
 			register "ddi_portA_config" = "1"
@@ -17,7 +60,33 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR,
 			}"
 		end
-		device ref tbt_pcie_rp0 on end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 off end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			device ref tcss_root_hub on
+				device ref tcss_usb3_port1 on end
+			end
+		end
 		device ref tcss_dma0 on end
 		device ref xhci on
 			# USB2

src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -18,13 +18,17 @@ chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x65f5 inherit
 
-		device ref pcie5_0 off
+		device ref pcie5_0 on
 			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
 			register "cpu_pcie_rp[CPU_RP(2)]" = "{
 				.clk_src = 3,
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp10/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl/variants/oryp9/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/gaze16/variants/gaze16-3050/include/variant/dgpu.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_DGPU_H
-#define VARIANT_DGPU_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F8
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_K11
-#define DGPU_SSID	0x50151558
-
-#endif

src/mainboard/system76/gaze16/variants/gaze16-3060/include/variant/dgpu.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef VARIANT_DGPU_H
-#define VARIANT_DGPU_H
-
-#include <soc/gpio.h>
-
-#define DGPU_RST_N	GPP_F8
-#define DGPU_PWR_EN	GPP_F9
-#define DGPU_GC6	GPP_K11
-#define DGPU_SSID	0x50e11558
-
-#endif

src/mainboard/system76/gaze17/Kconfig

@@ -1,73 +0,0 @@
-if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_GFX_NVIDIA
-	select DRIVERS_I2C_HID
-	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD
-	select EC_SYSTEM76_EC_DGPU
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MAINBOARD_HAS_TPM2
-	select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE17_3060_B
-	select MEMORY_MAPPED_TPM
-	select NO_UART_ON_SUPERIO
-	select PCIEXP_HOTPLUG
-	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
-	select SOC_INTEL_ALDERLAKE_PCH_P
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_CRASHLOG
-	select SPD_READ_BY_WORD
-	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
-
-config MAINBOARD_DIR
-	default "system76/gaze17"
-
-config MAINBOARD_PART_NUMBER
-	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
-	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Gazelle"
-
-config MAINBOARD_VERSION
-	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
-	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
-
-config VARIANT_DIR
-	default "3050" if BOARD_SYSTEM76_GAZE17_3050
-	default "3060" if BOARD_SYSTEM76_GAZE17_3060_B
-
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
-config CBFS_SIZE
-	default 0xA00000
-
-config CONSOLE_POST
-	default y
-
-config DIMM_SPD_SIZE
-	default 512
-
-config ONBOARD_VGA_IS_PRIMARY
-	default y
-
-config POST_DEVICE
-	default n
-
-config UART_FOR_CONSOLE
-	default 0
-
-# PM Timer Disabled, saves power
-config USE_PM_ACPI_TIMER
-	default n
-
-endif

src/mainboard/system76/gaze17/Kconfig.name

@@ -1,5 +0,0 @@
-config BOARD_SYSTEM76_GAZE17_3050
-	bool "gaze17 3050"
-
-config BOARD_SYSTEM76_GAZE17_3060_B
-	bool "gaze17 3060-b"

src/mainboard/system76/gaze17/bootblock.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <variant/gpio.h>
-
-void bootblock_mainboard_init(void)
-{
-	variant_configure_early_gpios();
-}

src/mainboard/system76/gaze17/devicetree.cb

@@ -1,134 +0,0 @@
-chip soc/intel/alderlake
-	register "common_soc_config" = "{
-		// Touchpad I2C bus
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 80,
-			.fall_time_ns = 110,
-		},
-	}"
-
-# ACPI (soc/intel/alderlake/acpi.c)
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
-
-	register "s0ix_enable" = "1"
-
-# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c)
-	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
-
-# FSP Silicon (soc/intel/alderlake/fsp_params.c)
-	# FIVR configuration
-	#   Read EXT_RAIL_CONFIG to determine bitmaps
-	#     sudo devmem2 0xfe0011b8
-	#     0x0
-	#   Read EXT_V1P05_VR_CONFIG
-	#     sudo devmem2 0xfe0011c0
-	#     0x1a42000
-	#   Read EXT_VNN_VR_CONFIG0
-	#     sudo devmem2 0xfe0011c4
-	#     0x1a42000
-	# TODO: v1p05 voltage and vnn icc max?
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = 0,
-		.vnn_enable_bitmap = 0,
-		.v1p05_supported_voltage_bitmap = 0,
-		.vnn_supported_voltage_bitmap = 0,
-		.v1p05_icc_max_ma = 500,
-		.vnn_sx_voltage_mv = 1050,
-	}"
-
-	# Thermal
-	register "tcc_offset" = "10"
-
-	# Enable CNVi BT
-	register "cnvi_bt_core" = "true"
-
-# PM Util (soc/intel/alderlake/pmutil.c)
-	# GPE configuration
-	register "pmc_gpe0_dw0" = "PMC_GPP_R"
-	register "pmc_gpe0_dw1" = "PMC_GPP_B"
-	register "pmc_gpe0_dw2" = "PMC_GPP_D"
-
-# Actual device tree
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		#From CPU EDS(TODO)
-		device ref system_agent on end
-		device ref pcie5_0 on
-			# PCIe PEG2 x8, Clock 3 (DGPU)
-			register "cpu_pcie_rp[CPU_RP(2)]" = "{
-				.clk_src = 3,
-				.clk_req = 3,
-				.flags = PCIE_RP_LTR,
-			}"
-			chip drivers/gfx/nvidia
-				device pci 00.0 on end # VGA controller
-				device pci 00.1 on end # Audio device
-				device pci 00.2 on end # USB xHCI Host controller
-				device pci 00.3 on end # USB Type-C UCSI controller
-			end
-		end
-		device ref tcss_xhci on
-			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
-			device ref tcss_root_hub on
-				device ref tcss_usb3_port1 on end
-			end
-		end
-
-		device ref shared_sram on end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN0412""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
-			end
-			chip drivers/i2c/hid
-				register "generic.hid" = ""FTCS1000""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
-				register "generic.detect" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref heci1 on end
-		device ref sata on
-			register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
-			register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
-		end
-		device ref pch_espi on
-			register "gen1_dec" = "0x00040069" # EC PM channel
-			register "gen2_dec" = "0x00fc0E01" # AP/EC command
-			register "gen3_dec" = "0x00fc0F01" # AP/EC debug
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end
-		device ref p2sb on end
-		device ref pmc hidden end
-		device ref hda on
-			register "pch_hda_idisp_codec_enable" = "1"
-			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
-			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
-		end
-		device ref smbus on end
-		device ref fast_spi on end
-	end
-end

src/mainboard/system76/gaze17/ramstage.c

@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <smbios.h>
-#include <soc/ramstage.h>
-#include <variant/gpio.h>
-
-smbios_wakeup_type smbios_system_wakeup_type(void)
-{
-	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
-}
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
-	params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
-
-	params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
-	params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
-	params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
-	params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
-
-	params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
-	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
-
-	variant_configure_gpios();
-}

src/mainboard/system76/rpl/Kconfig

@@ -0,0 +1,122 @@
+config BOARD_SYSTEM76_RPL_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_LOCKDOWN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_SUPPORT_RESIZABLE_BARS
+	select SOC_INTEL_ALDERLAKE_S3
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_RAPTORLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_SYSTEM76_ADDW3
+	def_bool n
+	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_ALDERLAKE_PCH_S
+
+config BOARD_SYSTEM76_GAZE18
+	def_bool n
+	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_ORYP11
+	def_bool n
+	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+
+config BOARD_SYSTEM76_SERW13
+	def_bool n
+	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_ALDERLAKE_PCH_S
+
+if BOARD_SYSTEM76_RPL_COMMON
+
+config MAINBOARD_DIR
+	default "system76/rpl"
+
+config VARIANT_DIR
+	default "addw3" if BOARD_SYSTEM76_ADDW3
+	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "oryp11" if BOARD_SYSTEM76_ORYP11
+	default "serw13" if BOARD_SYSTEM76_SERW13
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "addw3" if BOARD_SYSTEM76_ADDW3
+	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "oryp11" if BOARD_SYSTEM76_ORYP11
+	default "serw13" if BOARD_SYSTEM76_SERW13
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Adder WS" if BOARD_SYSTEM76_ADDW3
+	default "Gazelle" if BOARD_SYSTEM76_GAZE18
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
+	default "Serval WS" if BOARD_SYSTEM76_SERW13
+
+config MAINBOARD_VERSION
+	default "addw3" if BOARD_SYSTEM76_ADDW3
+	default "gaze18" if BOARD_SYSTEM76_GAZE18
+	default "oryp11" if BOARD_SYSTEM76_ORYP11
+	default "serw13" if BOARD_SYSTEM76_SERW13
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 512
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
+	default 36
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0 if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11
+	default 2 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_SERW13
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif

src/mainboard/system76/rpl/Kconfig.name

@@ -0,0 +1,11 @@
+config BOARD_SYSTEM76_ADDW3
+	bool "addw3"
+
+config BOARD_SYSTEM76_GAZE18
+	bool "gaze18"
+
+config BOARD_SYSTEM76_ORYP11
+	bool "oryp11"
+
+config BOARD_SYSTEM76_SERW13
+	bool "serw13"

src/mainboard/system76/rpl/Makefile.inc

@@ -1,12 +1,12 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 
-romstage-y += romstage.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
 
 ramstage-y += ramstage.c
-ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c

src/mainboard/system76/rpl/acpi/mainboard.asl

@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
 #include <variant/gpio.h>
+#endif
 
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
@@ -10,8 +12,17 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#else // CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 		Scope (PEG2) {
 			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
 		}
+#endif // CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#endif // CONFIG(DRIVERS_GFX_NVIDIA)
 	}
 }

src/mainboard/system76/rpl/board_info.txt

@@ -1,7 +1,5 @@
 Vendor name: System76
-Board name: gaze17
 Category: laptop
-Release year: 2022
 ROM package: WSON-8
 ROM protocol: SPI
 ROM socketed: n

src/mainboard/system76/rpl/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}

src/mainboard/system76/rpl/cmos.default

@@ -1,3 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
-me_state=Enable
+me_state=Disable

src/mainboard/system76/rpl/devicetree.cb

@@ -0,0 +1,73 @@
+chip soc/intel/alderlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP, DDIB is HDMI
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c1 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+
+		device ref heci1 on end
+		device ref sata on
+			register "sata_salp_support" = "1"
+			register "sata_ports_enable[1]" = "1" # SSD1
+			# FIXME: DevSlp breaks S0ix
+			#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end

src/mainboard/system76/rpl/dsdt.asl

@@ -19,7 +19,9 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/alderlake/acpi/southbridge.asl>
-		#include <soc/intel/alderlake/acpi/tcss.asl>
+		#if CONFIG(BOARD_SYSTEM76_ORYP11)
+			#include <soc/intel/alderlake/acpi/tcss.asl>
+		#endif // CONFIG(BOARD_SYSTEM76_ORYP11)
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/rpl/include/mainboard/gpio.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif

src/mainboard/system76/rpl/ramstage.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	// TODO: Pin Mux settings
+
+	// Enable reporting CPU C10 state over ESPI
+	params->PchEspiHostC10ReportEnable = 1;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};