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140 Commits

Author SHA1 Message Date
Tim Crawford
baf80abc62 mb/system76/rpl: gaze18, serw13: Fix USB2 on USB-C port
Use USB2_PORT_MID instead of USB2_PORT_TYPE_C, as was done for addw3.

Change-Id: I7df2bbf1ba70c4e08319b760b2784e15c880a105
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-22 08:40:46 -06:00
Jeremy Soller
192f165edb addw3: Set USB-C ports as USB2_PORT_MID to prevent use of port reset messaging
Change-Id: I1f13edcc3fa757cc0d763be45e6eea0474077984
2023-03-21 19:56:29 -06:00
Subrata Banik
a2c83fb9f9 soc/intel: Update API name pmc_send_bios_reset_pci_enum_done
This patch updates PMC API name from `pmc_send_pci_enum_done` to
`pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done
is also set along with PMC enumeration being done.

BUG=b:270942083
TEST=Able to build and boot google/rex.

Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-21 15:47:22 -06:00
Jeremy Soller
a55e829ae3 soc/intel/alderlake: Correct PCH-S XHCI port information
Change-Id: I405b4f73584f4391152941bbd32e828a2bd0e6aa
2023-03-21 13:39:23 -06:00
Jeremy Soller
20c9608c05 system76/rpl: Remove retimer and PMC driver
Change-Id: Ief2c6db7c1673c414bb2eefdce5efc64144179da
2023-03-21 13:30:23 -06:00
Michał Żygowski
290b1bcda2 soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
2023-03-20 12:22:44 -06:00
Michał Żygowski
77fce247ff soc/intel/alderlake: Hook up P2SB PCI ops
P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.

This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.

TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
2023-03-20 12:22:28 -06:00
Michał Żygowski
84937d76fb soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
2023-03-20 12:21:36 -06:00
Jeremy Soller
09f9c48146 addw3: fix overridetree syntax
Change-Id: I74be236abed233d1211c10131c1a8c27158e0b96
2023-03-20 08:14:16 -06:00
Jeremy Soller
2565fe1bc3 Move RPP-S XHCI from USB4 driver to XHCI driver
Change-Id: I7853de5010123875cb0e0150c2e3763f1d3eaff8
2023-03-18 07:48:47 -06:00
Jeremy Soller
6d4e6615cf addw3: Add pmc_mux driver back
Change-Id: I8e341e34735c23e1cd6de78b264289d3c02e3e59
2023-03-17 12:20:11 -06:00
Tim Crawford
c0e6fa5707 mb/system76/rpl: gaze18: Select TPM_RDRESP_NEED_DELAY
Fixes the SLB 9672 FW15 failing to stop/resume on S3.

Change-Id: Icb950e02374529547de6d12ee589cde0164d4576
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-17 12:09:22 -06:00
Jeremy Soller
8e85530d32 addw3: add USB PLD definitions
Change-Id: Ic09e58df50f188ccffd9f0cfc8931f15dfc9971a
2023-03-17 11:29:08 -06:00
Jeremy Soller
0cfee4eb33 addw3: mark TBT as hotplug
Change-Id: Iaf73d68de6673c5ae89e0b9cad3e7749b2c5db2d
2023-03-17 10:54:50 -06:00
Jeremy Soller
a75c608019 addw3: Add USB ACPI definitions and PMC driver to overridetree
Change-Id: I04d71bfef6b238975fc43a32b08c23ac1b842f70
2023-03-17 10:04:37 -06:00
Jeremy Soller
7285446cc7 addw3: Set LAN clock as free running
Change-Id: I9c3ab8b3af16ff23ebd6751b260ebea30021ec61
2023-03-17 09:10:17 -06:00
Jeremy Soller
a2bbbc6769 mb/system76/tgl-u: Enable reporting CPU C10 state over ESPI
Change-Id: Ia811187df194af596eeea7d4fd7be0de5fa9254c
2023-03-10 13:29:28 -07:00
Tim Crawford
f3c764303c mb/system76/rpl: Declare child device on GLAN port
Declare a child device on the GLAN port so the Ethernet controller is
detected as an onboard device (eno) and not a plugged device (enp).

Change-Id: I43f1b3b749081fd989bb2e5c04f3b616642a5a4f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-09 09:54:15 -07:00
Tim Crawford
b425847fc7 mb/system76/rpl: gaze18: Remove unused card GPIOs
The power and reset lines from the PCH to the card reader are not
actually connected. Power comes directly from the 3.3V rail, and reset
is controlled by `BUF_PLT_RST#`.

Change-Id: I0a0969e9bcdf1dcf5dfdb512cf329409f187f1b5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-09 08:26:16 -07:00
Tim Crawford
3a8ee1a86e mb/system76/adl: Convert gaze17 to variants
Change-Id: I086a13a293986bb82692c08aae8fd675083ff16b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-08 12:57:17 -07:00
Jeremy Soller
05bdd8036d mb/system76/gaze17: reduce diff with mb/system76/adl
Change-Id: Iabb5486576a2c71af58e4abf3e870ff87af60895
2023-03-07 09:58:18 -07:00
Jeremy Soller
ceeb13e465 mb/system76/gaze17: reset HDA codec during init
Change-Id: Ibb69f6d836c56587bfdc4a76f86a48cb4581d3ea
2023-03-07 09:58:18 -07:00
Jeremy Soller
2f39f745c7 mb/system76/gaze17: enable EC lockdown support
Change-Id: I3db7cfc20a5c9b913e88e8cbff0cd2a5c5d4cad9
2023-03-07 09:58:18 -07:00
Jeremy Soller
a6907dc9c0 mb/system76/gaze17: add board.fmd
Change-Id: I70bdedb0b44da4406e91056425b7c0ee28705fb5
2023-03-07 09:58:18 -07:00
Jeremy Soller
065a7147ca mb/system76/gaze17: disable ME by default
Change-Id: I5fd34adba3fe5296c20763136d83025e63fd8a26
2023-03-07 09:58:18 -07:00
Jeremy Soller
0352415888 mb/system76/gaze17: switch to S3
Change-Id: I65d4dc008addceb95d5f37758b98f243b2a290dd
2023-03-07 09:58:18 -07:00
Jeremy Soller
e7d0cb6415 board/system76/adl: Add board.fmd file for all variants
Change-Id: I79f1b0ef9fac4593ce55451a5dc78021790fc830
2023-03-07 09:58:18 -07:00
Jeremy Soller
af0255c565 board/system76/tgl-h: Add board.fmd file for GBE and non-GBE variants
Change-Id: Iacc8ce5225097db3d99181cf8cec5f61f2e7056e
2023-03-07 09:58:18 -07:00
Jeremy Soller
c4393852e5 board/system76/tgl-u: Add board.fmd file for all variants
Change-Id: I408c633e4993bf08853bd0cae98e57d53baa3a79
2023-03-07 09:58:18 -07:00
Jeremy Soller
bf5f325757 board/system76/rpl: Add board.fmd files per variant
Change-Id: If51ae6f4ce71fde6044f9f4d3ae6a9581f48663d
2023-03-07 09:58:18 -07:00
Jeremy Soller
ae35884b09 ec/system76: Support lockdown based on EC security state
Change-Id: I00701aa1397c24efe6f2d163822968b528f5b915
2023-03-07 09:58:18 -07:00
Tim Crawford
4e370bf6ad mb/system76/gaze16: Remove directory
These models were moved to tgl-h. Remove the duplicated files.

Change-Id: If5f719fb162099db340b1f9a1d7a9d29460bc0a3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-06 11:15:23 -07:00
Jeremy Soller
43d7fd9d8a addw3: Force TBT power
Change-Id: I40af5500343ea3838545e8053b767670d00ea90a
2023-03-03 10:30:28 -07:00
Jeremy Soller
4f2e68fc4b Move TCSS code to oryp11
Change-Id: I76eec8f7ca69bdc32a57f2e41b64f1e82730c361
2023-03-03 10:29:37 -07:00
Jeremy Soller
c6341b2a42 Revert "soc/intel/alderlake: make it possible to enable TCSS on PCH-S"
This reverts commit c81af77eeb.
2023-03-03 10:23:13 -07:00
Jeremy Soller
983387dbd7 rpl: add one TBT port to devicetree
Change-Id: I0b15f9161f576970ef9feeab7ba7ffdb27070505
2023-03-03 09:16:57 -07:00
Jeremy Soller
c81af77eeb soc/intel/alderlake: make it possible to enable TCSS on PCH-S
Change-Id: I46f29bbe61cdc4fa21ccdabccc7743d0f3cc95b2
2023-03-03 09:16:35 -07:00
Jeremy Soller
7414fdfc54 oryp11: fix subsystem ID
Change-Id: I35e2389d9da16352f2311addfc8572836f3088d2
2023-03-01 09:50:28 -07:00
Jeremy Soller
ef7c7ece8d addw3: attempt to enable GBE
Change-Id: I4dd6ba9487488ab1efe44618795b546cdc518bc0
2023-02-28 14:56:07 -07:00
Tim Crawford
f081430b87 drivers/gfx/nvidia: Increase power sequence delays
The serw13 with the 4070 RTX sometimes fails to enumerate the dGPU.
Increasing the delays allows the dGPU to be enumerated consistently. The
values are arbitrary, but still less than the values from proprietary
firmware.

Change-Id: Ibbfda596a324df4b51d583af8d6a36b5cd53a561
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-28 14:17:36 -07:00
Jeremy Soller
ee6e82c96f rpl: remove drivers/gfx/nvidia from overridetrees
Change-Id: I142802b24b176e0662434a6c2005ab52bbf4508b
2023-02-28 12:21:22 -07:00
Jeremy Soller
58f4c7fe95 addw3: Do not configure GPIOs already configured
Change-Id: Ic2702d798ae46cff22e8ef2e9f76e1f69966ea86
2023-02-27 14:25:28 -07:00
Jeremy Soller
314b707dc5 rpl: Set UART_FOR_CONSOLE based on each variant
Change-Id: I43c9f828344981ddd9fd58e671767fbc6fb28de1
2023-02-27 14:25:04 -07:00
Jeremy Soller
e484088ff0 Add RPP-S crashlog IDs
Change-Id: I6837dd95b89e59a90ac8d75433da1fc1195b9ed6
2023-02-27 13:43:45 -07:00
Jeremy Soller
ce9c271317 Add RPP-S CSE IDs
Change-Id: I53b625ed1b2382c33f20cb7fff663d6bd62dc971
2023-02-27 13:43:44 -07:00
Jeremy Soller
15c05a7ac2 adl: Disable ME by default
Change-Id: I90119ef9bf8fa207dcda6c3f64246148344cde40
2023-02-27 13:01:18 -07:00
Jeremy Soller
57aecc8c0a adl: Switch to S3
Change-Id: Ief43a23fd5af37f6d8384d21254d6d1ad7697376
2023-02-27 13:01:05 -07:00
Jeremy Soller
d9f6e2e5fa Revert "rpl: disable stage cache and mcache, which fixes S3"
This reverts commit d50557739d.
2023-02-27 13:00:41 -07:00
Jeremy Soller
caad869cac rpl: Disable ME by default
Change-Id: Id198487f23284f0d3b307d05998d7b209835c680
2023-02-27 12:58:20 -07:00
Jeremy Soller
6215792619 rpl: Re-enable TPM_MEASURED_BOOT
Change-Id: I0ab5dd4e8ca371646f7615d2ea52038420157f93
2023-02-27 12:30:03 -07:00
Jeremy Soller
3dc572fc6d security/tpm/tspi/log: Respect cbmem TPM log size when copying preram entries
Change-Id: I0f08a5bbdb7b823e3a12770154101d49055f263e
2023-02-27 12:29:28 -07:00
Jeremy Soller
0c44e8ed3e security/tpm/tspi: Fix preram TPM log max entries
Change-Id: I671fcd891367d3cbae4fc2d18db5a73ee8c15e8f
2023-02-27 12:16:12 -07:00
Jeremy Soller
87058c3e2a Temporarily disable TPM_MEASURED_BOOT
Change-Id: I6fcad9de26a52c51d2a88a041ec277a63239d05d
2023-02-27 11:52:10 -07:00
Jeremy Soller
7f3969da81 oryp11: Do not configure clock reqs, FSP will do that
Change-Id: I75e0b2fe7dfbcbc9400825e03218a6c21c265ff2
2023-02-27 08:47:19 -07:00
Jeremy Soller
53bf009c47 oryp11: Add GPIO definitions
Change-Id: I58001b408e89fcfb232f6707fb762c10ca55d84c
2023-02-27 08:42:59 -07:00
Jeremy Soller
d50557739d rpl: disable stage cache and mcache, which fixes S3
Change-Id: Ibb662bedc25c70bd5e077f1e91d2402bac16fe0c
2023-02-25 20:32:36 -07:00
Jeremy Soller
c941132543 rpl: Enable resizable BAR
Change-Id: I513974b521b774bfdd550a118ac9007b94b187f1
2023-02-25 20:32:36 -07:00
Jeremy Soller
69353f4094 Revert "rpl: Switch to S0iX"
This reverts commit e0bf2e4691.
2023-02-25 20:32:36 -07:00
Tim Crawford
5263effa38 serw13: Disable AER for SSD1
Enabling AER causes a constant flood of corrected error messages being
logged when using a 980 PRO, quickly filling the drive's free space.

Change-Id: Ib89c579f36e2fc53c9816f0033cd981aae4d7526
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-24 15:48:43 -07:00
Jeremy Soller
4d321cd02e rpl: Ensure touchpad IRQs are correct on RPL-H
Change-Id: I4e210df8494263618e8fe21cfc2fd250963b37ed
2023-02-22 19:07:14 -07:00
Jeremy Soller
22e04bcb30 rpl: Enable reporting CPU C10 state over ESPI
Change-Id: Ie1a574191da9d677d41f3dab6dce51c714bc26a9
2023-02-22 15:49:12 -07:00
Jeremy Soller
3078f35bff Missing endif
Change-Id: Ib6fa6512540f5bfbc68fea2ff355dc36f7102b8c
2023-02-22 14:32:14 -07:00
Jeremy Soller
b4768db0a7 Use PEG1 for NVIDIA ACPI only on PCH-S
Change-Id: I5ea775dd1f1770bd883bb4138404ea57a7cb6f22
2023-02-22 13:33:54 -07:00
Jeremy Soller
e0bf2e4691 rpl: Switch to S0iX
Change-Id: I2ae9d42d422fec32b9a7431ab44e7c7f4073a5da
2023-02-22 13:33:53 -07:00
Tim Crawford
17baeffcd9 mb/system76/rpl: gaze18: Fix DGPU_GC6 define
Change-Id: I7f622dd65f9d4d40cd64d2b470850d4bc12fe807
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 13:04:51 -07:00
Jeremy Soller
ca0d8b9d20 serw13: Add NVIDIA driver to device tree
Change-Id: I5464c174c0c3a0d9c62f601d26c38ad717479b28
2023-02-22 12:52:58 -07:00
Jeremy Soller
b1207772fb oryp11: Add NVIDIA driver to device tree
Change-Id: If8d5a36b0626eed70206bdd794a2d4dafe509551
2023-02-22 12:52:47 -07:00
Jeremy Soller
2c975776d9 gaze18: Add NVIDIA driver to device tree
Change-Id: If2252e1a38b84544cbbececbb9592cf017d35acf
2023-02-22 12:52:32 -07:00
Jeremy Soller
d6b75b94c5 addw3: Add NVIDIA driver to device tree
Change-Id: Ie7a284ae92e1e0ba73a2273a730e88921ee2d2c9
2023-02-22 12:51:59 -07:00
Jeremy Soller
85a606a538 oryp10: Add NVIDIA driver to device tree
Change-Id: Ife9863cc554b8fab945ab1975ed6c06b005e7e6c
2023-02-22 12:51:39 -07:00
Jeremy Soller
bf0be396f3 oryp11: Add GPIO group comments
Change-Id: Icb2d4eb6b286c79872ec2c1936d34538a35bb2ee
2023-02-22 12:41:16 -07:00
Jeremy Soller
08074e46a5 gaze18: Fix bootblock DGPU_RST#_PCH setting
Change-Id: I42b2a89ea4d835914acc038ad0e02d94e1bffeab
2023-02-22 12:41:02 -07:00
Jeremy Soller
01d7fc7c1d gaze18 and oryp11: Fix CPU root port definitions
Change-Id: I1d1834786b08f2b8ba00642477dd26d9d1201e0f
2023-02-22 12:40:46 -07:00
Jeremy Soller
46ef7b3b19 oryp11: Fix DGPU GPIOs
Change-Id: Ibcac2cc95fd15b6d34f90804730ae0aab461ebef
2023-02-22 12:32:20 -07:00
Tim Crawford
e319f594fc soc/intel/alderlake: Hook up ucode for RPL-P/H/U
Hook up microcode from 3rdparty repo for:

- 06-ba-02 (CPUID signature: 0xb06a2)

Change-Id: I2ae315ed6e24a8d640f60af352928ebd091db3ab
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 12:17:04 -07:00
Tim Crawford
4acddb41cf Update intel-microcode to 2023-02-14 release
Update the submodule to 2be47edc99ee.

This release contains the ucode for RPL-P/H/U.

Change-Id: I8497557e9362749a6a89f07f2515201c625e5d1d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 12:16:20 -07:00
Jeremy Soller
305577aebe Fix leftover addp3 identifiers
Change-Id: I64bedcfeac06377454d42fb79325bb6e256da6ba
2023-02-22 08:16:40 -07:00
Jeremy Soller
d5f1eef200 Update kconfigs to match renamed boards
Change-Id: Ia9334a27b4e03783152b6a228faca0cb0c166594
2023-02-22 08:04:27 -07:00
Jeremy Soller
3cd2a6acb7 Move gaze18-3050 variant to gaze18
Change-Id: I7cff4e39699e66284d0fa75e4c9d3029367c6cbd
2023-02-22 08:01:00 -07:00
Jeremy Soller
0015839d31 Move gaze18-40x0 variant to addw3
Change-Id: Ie4fbe445b275723a38164cb3624f5119ba500cb7
2023-02-22 08:00:43 -07:00
Jeremy Soller
88eb602d56 Move addp3 variant to oryp11
Change-Id: Ic805522570a45834dabd7f8b3162b5657f690dc8
2023-02-22 08:00:26 -07:00
Jeremy Soller
2c46f6d0cf Move oryp11 variant to serw13
Change-Id: I8d8301cbfb7abdd1dee57bc1a657c156cf55e271
2023-02-22 08:00:13 -07:00
Jeremy Soller
5eb848d959 mainboard/system76/rpl: Add kconfig for ADDP3
Change-Id: I3eb2574e3f26f9a4ed68c128ac23b94be17f8c1c
2023-02-21 20:08:49 -07:00
Jeremy Soller
4b321d278e mb/system76/rpl: addp3: Add board
Change-Id: Ic641698af43ee81314a1e492ecdaf4752dfcbdd3
2023-02-21 15:43:30 -07:00
Tim Crawford
0689097632 mb/system76/rpl: gaze18-3050: Add USB and PCIe RP configs
Change-Id: Ic9863d3aa8129e7081f36bc302cfa8ca68140eae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-21 08:15:28 -07:00
Tim Crawford
6529e3d712 mb/system76/rpl: gaze18-3050: Document GPIOs
Change-Id: I5a74d0d8bf752d081975cd26ddf9d5b749c0ae9b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-20 11:46:16 -07:00
Jeremy Soller
e0bda81015 gaze18-40x0: Leave CNVi clkreq configured by FSP and configure reset
Change-Id: Ic7e2f5c0b806474c17029fae5a39f415a51101b9
2023-02-15 16:18:37 -07:00
Tim Crawford
1ba9380a21 mb/system76/rpl: oryp11: Configure CNVi reset
It seems to be sufficient to just take the device out of reset, so
configure it in coreboot instead of FSP.

Change-Id: I408229072ba7eb169c3ba6693f95f5b32fca10e1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-15 15:44:27 -07:00
Tim Crawford
a98f4ead4c mb/system76/rpl: oryp11: Fix CNVi
According to the schematics:

- PCH_LAN_WAKE# is not connected
- M.2_BT_PCMIN is not connected

Addtionally, leave both CLKREQ and RST# for CNVi as FSP configured.

Change-Id: I6f249ca778ad741469475b02163a2eee2e7626de
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-15 15:24:39 -07:00
Tim Crawford
6f02b2f73f mb/system76/rpl: oryp11: Fix USB port configs
Change-Id: Icc026451ac9ac5ff9def64096629d86beca4ec3c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 16:10:28 -07:00
Tim Crawford
45ca4334b5 mb/system76/rpl: oryp11: Leave CLKREQ as FSP configured
Change-Id: If19f463ad63b74cbbafa4fdd31815697f608f0ed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 16:09:52 -07:00
Jeremy Soller
b87e2021ad gaze18-40x0: document GPIOs
Change-Id: Ib1f3c1cdbe20dd759fd5c57105ba2640ec2b038b
2023-02-13 14:52:36 -07:00
Tim Crawford
23dd117ccf soc/intel/adl: Fix PL1 name for RPL-HX
Change-Id: I9ccb589338bd2e185186987f77b1eab62cdad2c1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 10:06:11 -07:00
Tim Crawford
654a08acd4 oryp11: dGPU port and TP GPIO
Change-Id: Ie3f9edbf5cb9fcaba3c50e949afb55f990cd846d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-10 13:44:00 -07:00
Jeremy Soller
dbf7480795 rpl: fix NVIDIA ACPI scope
Change-Id: Iccc78c15ef115a56fd071a7b891310026ed16501
2023-02-10 12:56:27 -07:00
Jeremy Soller
71f18f129f gaze18-40x0: enable NVIDIA GPU
Change-Id: Iefb6de5bdc481934d7c661516c05ee945e8717db
2023-02-10 12:43:57 -07:00
Jeremy Soller
d30cad4127 Add more RPP-S PCI ID definitions
Change-Id: I3682701a169dd51b1e55227b4e089310bcf42a0f
2023-02-10 12:05:25 -07:00
Jeremy Soller
74e0453ef2 Add RPP-S PCI root port definitions
Change-Id: I6ec9757b0402299be9c96fc0019890068f2f5e43
2023-02-10 11:59:51 -07:00
Jeremy Soller
d70be6d118 Add RPP-S PCI ID definitions
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
2023-02-10 11:57:04 -07:00
Jeremy Soller
5da590435a gaze18-40x0: Set touchpad interrupt GPIO
Change-Id: I88c2be3948ca38b3ace04c7b45d989e696405be5
2023-02-10 11:12:11 -07:00
Jeremy Soller
e1506c52bb rpl: touchpad irq on GPP_E7
Change-Id: I8a7072591d04ce73bd8861bfcd20ae2ef4460498
2023-02-10 10:47:10 -07:00
Jeremy Soller
c54358d8fc gaze18-40x0: fill in overridetree
Change-Id: Ie411e9f103b07b079681a73cef11f44cd58f0976
2023-02-10 09:39:08 -07:00
Tim Crawford
c918d36889 [WIP] soc/intel/adl: Add RPL-HX support
Change-Id: I62efdd8bea7cc5134621f4602d2b2523651076da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 16:25:42 -07:00
Tim Crawford
e707f1efc3 [WIP] soc/intel/adl: Add RPL-HX support
Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.5)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 14:28:22 -07:00
Tim Crawford
2e0291e7c3 oryp11: Set dq_pins_interleaved
Change-Id: I094e86b39df9cedcb2813a88785ef907b9bf2308
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 11:25:23 -07:00
Tim Crawford
4c9edaa4d0 oryp11: Fix TBT RP
Change-Id: I18f04fcfab73ae1144dc9f1625a55af0b708ba36
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 09:16:21 -07:00
Tim Crawford
af1241f3a8 mb/system76/rpl: oryp11: Add USB and PCIe RP configs
Change-Id: Ibe15461b58a5d133456779e7e28c8bd1db7ee320
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 09:12:33 -07:00
Tim Crawford
da67e5e8a3 mb/system76/rpl: Use S3 instead of S0ix
Change-Id: Ib161c3eb6cf5af815e2ab53f38b5f7786b2e1949
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 08:44:16 -07:00
Tim Crawford
2cd15a2f72 mb/system76/rpl: Add oryp11 smart amp extract
Extract the configuration block from the proprietary firmware module
PlatformInitAdvancedPostMem.

The proprietary firmware does not use a multiple of 4 for the smart amp
data like coreboot expects, so duplicate the last 2 dwords.

Change-Id: I563a92b87ebf7672963a03a15166aed194fc57fe
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 14:11:12 -07:00
Tim Crawford
ae0d0f6d26 mb/system76/rpl: Drop unneeded rcomp value
Change-Id: I7901e3a38fd8b03aad4cd0534c4646beaa13b521
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 10:48:45 -07:00
Tim Crawford
7689625cf0 soc/intel/alderlake: Hook up ucode for RPL-HX
Hook up microcode from 3rdparty repo for:

- 06-b7-01 (CPUID signature: 0xb0671)

Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 08:50:01 -07:00
Tim Crawford
1e3e8494f7 Set MAX_CPUS in SoC Kconfig
Change-Id: Ia7c0504d6d15931d2f0cfba92f0f8b700c91e37d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 08:48:08 -07:00
Jeremy Soller
ca1c4bd7e7 Set MAX_CPUs for RPL-HX boards to 32
Change-Id: Ic10220124e2b32c7a1d674150687d27b94770873
2023-02-08 08:21:07 -07:00
Jeremy Soller
b787eb1e16 Use interleaved DQ for gaze18-40x0, remove rcomp resistor setting
Change-Id: I9e527774c0ea08c7079c9722fa91f3876d23475e
2023-02-08 08:15:03 -07:00
Jeremy Soller
17db22596e Move RPL models to new folder
Change-Id: If343c3d1c45ea88cef5e1b8912d929b1e8793b2c
2023-02-07 14:33:25 -07:00
Jeremy Soller
fa2aa1d2a4 Select ADL-S PCH for some new RPL models
Change-Id: I6c3193c30f694ae1150ef1fba715c4eafc0a60b3
2023-02-07 14:22:44 -07:00
Jeremy Soller
ac4c79fe67 Add gaze18-40x0
Change-Id: I5a7a00dd197de3d4dc4e18b16c327e8a9bc0065d
2023-02-07 14:02:59 -07:00
Tim Crawford
f385486beb mb/system76/adl: Add Oryx Pro 11 as a variant
Change-Id: Ib9cf93dc88cd51d429222540ce0721c6e5f4013a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-07 11:40:49 -07:00
Tim Crawford
d2fc079b71 mb/system76/adl: Add Gazelle 18 (3050) as a variant
There will be two versions of firmware for the Gazelle 18:

- One for units using NVIDIA RTX 3050
- One for units using NVIDIA RTX 40x0

Change-Id: I7c1a51fda012fe4e7a43bbe5ef98a3aec38373a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 11:06:51 -07:00
Tim Crawford
bfb21044f4 mb/system76/adl: oryp10: Enable dGPU
I forgot this when performing the rebase.

Change-Id: I855968469ed339bdf2a5a40d5d91878a262ce954
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 11:04:42 -07:00
Tim Crawford
29632b4b9d mb/system76/adl: Restructure board configs
Use a common block for all ADL/RPL boards.

Change-Id: I0ac73751c37a116b205f200c42b814182ca32bde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 10:54:03 -07:00
Tim Crawford
c5a2f794ad mb/system76: Rename adl-p to adl
The directory hold boards other than ADL-P, such as ADL-U and ADL-H, and
will also contain the RPL boards.

Change-Id: I1b42246bcf1eaed9de51f59021209e9eb836df15
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 10:53:53 -07:00
Tim Crawford
40e8d68d3b soc/intel/alderlake: Fix IRQ for PEG0, PEG1
Fixes the following warnings on Linux:

    pcieport 0000:00:06.0: can't derive routing for PCI INT D
    pcieport 0000:00:06.2: can't derive routing for PCI INT B

Change-Id: I49406e0db77cf2391972f6660729bd0a41a34f13
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:16 -07:00
Tim Crawford
c6ef149a55 mb/system76: Enable dGPUs
Change-Id: Ia0d6c952541cbd09d14e82336e6dc6d7d7d18b44
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
3f278aa9fc mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
0f67cd9bd5 mb/system76/tgl-h: Disable D3cold for TCSS
The TGL-H boards use S3 instead of S0ix.

Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Jeremy Soller
e927aff3d7 mb/system76: select TPM_RDRESP_NEED_DELAY
Change-Id: I7909b05e9203ce9ad07c8e87a847bc46cf281b34
2023-01-23 10:55:15 -07:00
Jeremy Soller
6b23f22d59 mb/system76/addw1: Disable SaOcSupport to eliminate hangs with 3200MT/s memory
Change-Id: I586e8cf97a52b2fa8386ce3742a4f4ae9465bbcf
2023-01-23 10:55:15 -07:00
Tim Crawford
779872ff4d mb/system76: Add custom backlight levels for Intel GMA
Add custom backlight levels for all models except:

- addw1
- bonw14: Does not use the iGPU

Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Jeremy Soller
8414aa8f14 drivers/gfx/nvidia: Add driver for NVIDIA GPU
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, and a function for enabling the GPU power in romstage.

Tested on system76/gaze15.

References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
5fd3a476f7 soc/intel/alderlake: Add IRQ for non-existent CPU PCIe device
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.

Fixes the following error in Linux:

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10

Which in turn resolves the conflict with the PCH HDA device...again:

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
ff79195b49 soc/intel/alderlake: Use channel 0 for memory-down
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the
System76 Lemur Pro 11 (lemp11).

Change-Id: I216b7b67c2674e0a14fdbbf96776759e55d0ec09
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Jeremy Soller
ecfc4d9e81 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
2023-01-23 10:55:14 -07:00
Jeremy Soller
b60f563ef2 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-01-23 10:55:14 -07:00
Jeremy Soller
95e709f64e mb/system76/gaze17: Add Gazelle 17
The gaze17 comes in 2 variants due to differences in the discrete GPU
and network controller used.

- NVIDIA RTX 3050, using Realtek Ethernet Controller
- NVIDIA RTX 3060, using onboard I219-V Ethernet Controller

Tested with a custom TianoCore UefiPayloadPkg payload.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting to Pop!_OS Linux 22.04 with kernel 5.18.10
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics: Requires NVIDIA driver
- mDP/HDMI displays on 3060 variant: Requires NVIDIA driver
- Detection of devices in TBT slot on boot
- S3 suspend: MP init eventually fails

Not tested:

- Thunderbolt devices

Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
981f234f17 mb/system76/adl-p: Add Oryx Pro 10 as a variant
oryp10 is nearly identical to the oryp9, with the differences being:

- Uses DDR5 RAM instead of DDR4 RAM
- Uses Realtek ALC1306 instead of TI TAS5825M
- Has an option for OLED display

Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
ab542a2461 mb/system76/adl-p: Add Oryx Pro 9 as a variant
The Oryx Pro 9 (oryp9) is an Alder Lake-P board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- Both M.2 NVME SSD slots (with MZVL2500HCJQ)
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics
- HDMI output (requires NVIDIA GPU)
- Mini DisplayPort output (requires NVIDIA GPU)
- Detection of devices in TBT slot on boot

Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
32ba9ac585 mb/system76/adl-p: Add Lemur Pro 11 as a variant
The Lemur Pro 11 (lemp11) is an Alder Lake-U board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- DIMM slot (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- M.2 SATA SSD (with WDS100T2B0B)
- All USB ports
- SD card reader
- Webcam
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- Booting Pop!_OS Linux 22.04 with kernel 5.18.5
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- On-board RAM: Requires CB:65567
- Detection of devices in TBT slot on boot
- S0ix suspend/resume

Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:13 -07:00
Tim Crawford
ab052d2b54 mb/system76/tgl-u: Leave TBT LSX0 as FSP configured
Do not reconfigured LSX0 so that the FSP values are used.

Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:13 -07:00
Tim Crawford
2212d28b56 submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2023-01-23 10:55:13 -07:00
264 changed files with 11677 additions and 189 deletions

34
.gitmodules vendored
View File

@@ -1,67 +1,67 @@
[submodule "3rdparty/blobs"]
path = 3rdparty/blobs
url = ../blobs.git
url = https://review.coreboot.org/blobs.git
update = none
ignore = dirty
[submodule "util/nvidia-cbootimage"]
path = util/nvidia/cbootimage
url = ../nvidia-cbootimage.git
url = https://review.coreboot.org/nvidia-cbootimage.git
[submodule "vboot"]
path = 3rdparty/vboot
url = ../vboot.git
url = https://review.coreboot.org/vboot.git
branch = main
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = ../arm-trusted-firmware.git
url = https://review.coreboot.org/arm-trusted-firmware.git
[submodule "3rdparty/chromeec"]
path = 3rdparty/chromeec
url = ../chrome-ec.git
url = https://review.coreboot.org/chrome-ec.git
[submodule "libhwbase"]
path = 3rdparty/libhwbase
url = ../libhwbase.git
url = https://review.coreboot.org/libhwbase.git
[submodule "libgfxinit"]
path = 3rdparty/libgfxinit
url = ../libgfxinit.git
url = https://review.coreboot.org/libgfxinit.git
[submodule "3rdparty/fsp"]
path = 3rdparty/fsp
url = ../fsp.git
url = https://review.coreboot.org/fsp.git
update = none
ignore = dirty
[submodule "opensbi"]
path = 3rdparty/opensbi
url = ../opensbi.git
url = https://review.coreboot.org/opensbi.git
[submodule "intel-microcode"]
path = 3rdparty/intel-microcode
url = ../intel-microcode.git
url = https://review.coreboot.org/intel-microcode.git
update = none
ignore = dirty
branch = main
[submodule "3rdparty/ffs"]
path = 3rdparty/ffs
url = ../ffs.git
url = https://review.coreboot.org/ffs.git
[submodule "3rdparty/amd_blobs"]
path = 3rdparty/amd_blobs
url = ../amd_blobs
url = https://review.coreboot.org/amd_blobs
update = none
ignore = dirty
[submodule "3rdparty/cmocka"]
path = 3rdparty/cmocka
url = ../cmocka.git
url = https://review.coreboot.org/cmocka.git
update = none
branch = stable-1.1
[submodule "3rdparty/qc_blobs"]
path = 3rdparty/qc_blobs
url = ../qc_blobs.git
url = https://review.coreboot.org/qc_blobs.git
update = none
ignore = dirty
[submodule "3rdparty/intel-sec-tools"]
path = 3rdparty/intel-sec-tools
url = ../9esec-security-tooling.git
url = https://review.coreboot.org/9esec-security-tooling.git
[submodule "3rdparty/stm"]
path = 3rdparty/stm
url = ../STM
url = https://review.coreboot.org/STM
branch = stmpe
[submodule "util/goswid"]
path = util/goswid
url = ../goswid
url = https://review.coreboot.org/goswid.git
branch = trunk

View File

@@ -207,12 +207,16 @@ The boards in this section are not real mainboards, but emulators.
- [Galago Pro 6](system76/galp6.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md)
## Texas Instruments

View File

@@ -0,0 +1,65 @@
# System76 Gazelle 17 (gaze17)
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
## Specs
- CPU
- Intel Core i5-12500H
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 3050
- NVIDIA GeForce RTX 3050 Ti
- NVIDIA GeForce RTX 3060
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
- Networking
- Gigabit Ethernet
- 3050: Realtek RTL8111H controller
- 3060: Onboard Intel I219-V
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX201
- Power
- 3050: 150W (20V, 7.5A) AC barrel adapter
- 3060: 180W (20V, 9A) AC barrel adapter
- Lite-On PA-1181-76, using a C5 power cord
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The position of the flash chip depends on the variant:
- 3050: U24, below the bottom DIMM slot.
- 3060: U55, left of the PCIe 4.0 M.2 slot.

View File

@@ -0,0 +1,62 @@
# System76 Lemur Pro 11 (lemp11)
## Specs
- CPU
- Intel Core i5-1235U
- Intel Core i7-1255U
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.0" 1920x1080@60Hz LCD
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
- Networking
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5 mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-A
- 1x USB 3.2 (Gen 1) Type-A
- Dimensions
- 1.65cm x 32.2cm x 21.68cm, 1.15kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U41) is left of the DIMM slot.

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# System76 Oryx Pro 10 (oryp10)
## Specs
- CPU
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
- eDP options:
- 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
- 80Wh 6-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- Realtek ALC1306 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
- 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the DIMM slots.

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# System76 Oryx Pro 9 (oryp9)
## Specs
- CPU
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
- eDP options:
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
- 80Wh 6-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- TI TAS5825M smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
- 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the DIMM slots.

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config DRIVERS_GFX_NVIDIA
bool
default n
help
Support for NVIDIA Optimus graphics
config DRIVERS_GFX_NVIDIA_BRIDGE
hex "PCI bridge for the GPU device"
default 0x01
depends on DRIVERS_GFX_NVIDIA

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# SPDX-License-Identifier: GPL-2.0-only
romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

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/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
// Memory mapped PCI express config space
OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
Field (PCIC, ByteAcc, NoLock, Preserve) {
PVID, 16,
PDID, 16,
Offset (0x248),
, 7,
L23E, 1, /* L23_Rdy Entry Request */
L23R, 1, /* L23_Rdy to Detect Transition */
Offset (0xC20),
, 4,
P0AP, 2, /* Additional power savings */
Offset (0xC38),
, 3,
P0RM, 1, /* Robust squelch mechanism */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 1
P0AP = 3
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
L23R = 1
Sleep (16)
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
P0RM = 0
P0AP = 0
Printf(" GPU PORT L23D FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

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/* SPDX-License-Identifier: GPL-2.0-only */
#define NV_ERROR_SUCCESS 0x0
#define NV_ERROR_UNSPECIFIED 0x80000001
#define NV_ERROR_UNSUPPORTED 0x80000002
#include "nvjt.asl"
Method (_DSM, 4, Serialized) {
Printf("GPU _DSM")
If (Arg0 == ToUUID (JT_DSM_GUID)) {
If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
Return (NVJT(Arg2, Arg3))
} Else {
Printf(" Unsupported JT revision: %o", SFST(Arg1))
Return (NV_ERROR_UNSUPPORTED)
}
} Else {
Printf(" Unsupported GUID: %o", IDST(Arg0))
Return (NV_ERROR_UNSPECIFIED)
}
}

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/* SPDX-License-Identifier: GPL-2.0-only */
Device (DEV0) {
Name(_ADR, 0x00000000)
#include "utility.asl"
#include "dsm.asl"
#include "power.asl"
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
#define JT_REVISION_ID_MIN 0x00000100
#define JT_REVISION_ID_MAX 0x00000200
#define JT_FUNC_SUPPORT 0x00000000
#define JT_FUNC_CAPS 0x00000001
#define JT_FUNC_POWERCONTROL 0x00000003
//TODO: SMI traps and EGIN/XCLM
#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
#define JT_DFGC_NONE 0 // Handle request immediately
#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
// Deferred GC6 enter/exit until D3-cold (saved DFGC)
Name(DFEN, 0)
// Deferred GC6 enter control (saved GPC)
Name(DFCI, 0)
// Deferred GC6 exit control (saved GPCX)
Name(DFCO, 0)
Method (NVJT, 2, Serialized) {
Printf(" GPU NVJT")
Switch (ToInteger(Arg0)) {
Case (JT_FUNC_SUPPORT) {
Printf(" Supported Functions")
Return(ITOB(
(1 << JT_FUNC_SUPPORT) |
(1 << JT_FUNC_CAPS) |
(1 << JT_FUNC_POWERCONTROL)
))
}
Case (JT_FUNC_CAPS) {
Printf(" Capabilities")
Return(ITOB(
(1 << 0) | // G-SYNC NSVR power-saving features are enabled
(1 << 1) | // NVSR disabled
(2 << 3) | // Panel power and backlight are on the suspend rail
(0 << 5) | // self-refresh controller remains powered while panel is powered
(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
(0 << 8) | // Combined power rail for all GPUs
(0 << 10) | // External SPI ROM
(1 << 11) | // No SMI handler for kernel panic exit while in GC6
(0 << 12) | // Supports notify on GC6 state done
(1 << 13) | // Support deferred GC6
(1 << 14) | // Support fine-grained root port control
(2 << 15) | // GC6 version is GC6-R
(0 << 17) | // GC6 exit ISR is not supported
(0 << 18) | // GC6 self wakeup not supported
(JT_REVISION_ID_MAX << 20) // Highest revision supported
))
}
Case (JT_FUNC_POWERCONTROL) {
Printf(" Power Control: %o", SFST(Arg1))
CreateField (Arg1, 0, 3, GPC) // GPU power control
CreateField (Arg1, 4, 1, PPC) // Panel power control
CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
// Save deferred GC6 request
If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
DFEN = DFGC
DFCI = GPC
DFCO = GPCX
}
// Buffer to cache current state
Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
CreateField (JTBF, 0, 3, CGCS) // Current GC state
CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
// If doing deferred GC6 request, return now
If (ToInteger(DFGC) != 0) {
CGCS = 1
CGPS = 1
Return (JTBF)
}
// Apply requested state
Switch (ToInteger(GPC)) {
Case (JT_GPC_GSS) {
Printf(" Get current GPU GCx sleep status")
//TODO: include transitions!
If (GTXS(DGPU_RST_N)) {
// GPU powered on
CGCS = 1
CGPS = 1
} ElseIf (GTXS(DGPU_PWR_EN)) {
// GPU powered off, GC6
CGCS = 3
CGPS = 0
} Else {
// GPU powered off, D3 cold
CGCS = 2
CGPS = 0
}
}
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
CPSS = 1
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
If (ToInteger(PPC) == 0) {
CPSS = 0
}
}
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Case (JT_GPC_XGIS) {
Printf(" Exit GC6 for self-refresh update")
GC6O()
CGCS = 1
CGPS = 1
If (ToInteger(PPC) != 0) {
CPSS = 0
}
}
Default {
Printf(" Unsupported GPU power control: %o", SFST(GPC))
}
}
Return (JTBF)
}
Default {
Printf(" Unsupported function: %o", SFST(Arg0))
Return (NV_ERROR_UNSUPPORTED)
}
}
}

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/* SPDX-License-Identifier: GPL-2.0-only */
//TODO: evaluate sleeps
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, DwordAcc, NoLock, Preserve) {
Offset (0x40),
SSID, 32, // Subsystem vendor and product ID
}
// Enter GC6
Method(GC6I, 0, Serialized) {
Printf(" GPU GC6I START")
// Enter L23
^^DL23()
Sleep(5)
// Put GPU into reset
Printf(" Put GPU into reset")
CTXS(DGPU_RST_N)
Sleep(5)
Printf(" GPU GC6I FINISH")
}
// Exit GC6
Method(GC6O, 0, Serialized) {
Printf(" GPU GC6O START")
// Bring GPU out of reset
Printf(" Bring GPU out of reset")
STXS(DGPU_RST_N)
Sleep(5)
// Exit L23
^^L23D()
Sleep(5)
Printf(" GPU GC6O FINISH")
}
Method (_ON, 0, Serialized) {
Printf(" GPU _ON START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCO)) {
Case (JT_GPC_XGXS) {
Printf(" Exit GC6 and stop self-refresh")
GC6O()
}
Default {
Printf(" Unsupported DFCO: %o", SFST(DFCO))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power on")
STXS(DGPU_PWR_EN)
Sleep(5)
GC6O()
}
Printf(" GPU _ON FINISH")
}
Method (_OFF, 0, Serialized) {
Printf(" GPU _OFF START")
If (DFEN == JT_DFGC_DEFER) {
Switch (ToInteger(DFCI)) {
Case (JT_GPC_EGNS) {
Printf(" Enter GC6 without self-refresh")
GC6I()
}
Case (JT_GPC_EGIS) {
Printf(" Enter GC6 with self-refresh")
GC6I()
}
Default {
Printf(" Unsupported DFCI: %o", SFST(DFCI))
}
}
DFEN = JT_DFGC_NONE
} Else {
Printf(" Standard RTD3 power off")
GC6I()
CTXS(DGPU_PWR_EN)
Sleep(5)
}
Printf(" GPU _OFF FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PWRR._ON")
// Restore SSID
^^SSID = DGPU_SSID
Printf(" Restore SSID: %o", SFST(^^SSID))
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PWRR._OFF")
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })

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/* SPDX-License-Identifier: GPL-2.0-only */
// Convert a byte to a hex string, trimming extra parts
Method (BHEX, 1) {
Local0 = ToHexString(Arg0)
Return (Mid(Local0, SizeOf(Local0) - 2, 2))
}
// UUID to string
Method (IDST, 1) {
Local0 = ""
Fprintf(
Local0,
"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
BHEX(DerefOf(Arg0[3])),
BHEX(DerefOf(Arg0[2])),
BHEX(DerefOf(Arg0[1])),
BHEX(DerefOf(Arg0[0])),
BHEX(DerefOf(Arg0[5])),
BHEX(DerefOf(Arg0[4])),
BHEX(DerefOf(Arg0[7])),
BHEX(DerefOf(Arg0[6])),
BHEX(DerefOf(Arg0[8])),
BHEX(DerefOf(Arg0[9])),
BHEX(DerefOf(Arg0[10])),
BHEX(DerefOf(Arg0[11])),
BHEX(DerefOf(Arg0[12])),
BHEX(DerefOf(Arg0[13])),
BHEX(DerefOf(Arg0[14])),
BHEX(DerefOf(Arg0[15]))
)
Return (Local0)
}
// Safe hex conversion, checks type first
Method (SFST, 1) {
Local0 = ObjectType(Arg0)
If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
Return (ToHexString(Arg0))
} Else {
Return (Concatenate("Type: ", Arg0))
}
}
// Convert from 4-byte buffer to 32-bit integer
Method (BTOI, 1) {
Return(
DerefOf(Arg0[0]) |
(DerefOf(Arg0[1]) << 8) |
(DerefOf(Arg0[2]) << 16) |
(DerefOf(Arg0[3]) << 24)
)
}
// Convert from 32-bit integer to 4-byte buffer
Method (ITOB, 1) {
Local0 = Buffer(4) { 0, 0, 0, 0 }
Local0[0] = Arg0 & 0xFF
Local0[1] = (Arg0 >> 8) & 0xFF
Local0[2] = (Arg0 >> 16) & 0xFF
Local0[3] = (Arg0 >> 24) & 0xFF
Return (Local0)
}

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/* SPDX-License-Identifier: GPL-2.0-only */
/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
// Port mapped PCI express config space
OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
Field (PCIC, AnyAcc, NoLock, Preserve) {
Offset(0x52), /* LSTS - Link Status Register */
, 13,
LASX, 1, /* 0, Link Active Status */
Offset(0x60), /* RSTS - Root Status Register */
, 16,
PSPX, 1, /* 16, PME Status */
Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */
, 30,
HPEX, 1, /* 30, Hot Plug SCI Enable */
PMEX, 1, /* 31, Power Management SCI Enable */
Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
SCB0, 1, /* Scratch bit 0 */
Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */
, 2,
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
}
Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */
, 30,
HPSX, 1, /* 30, Hot Plug SCI Status */
PMSX, 1 /* 31, Power Management SCI Status */
}
// Enter L23
Method (DL23, 0, Serialized) {
Printf(" GPU PORT DL23 START")
L23E = 1
Sleep (16)
Local0 = 0
While (L23E) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 1
Printf(" GPU PORT DL23 FINISH")
}
// Exit L23
Method (L23D, 0, Serialized) {
Printf(" GPU PORT L23D START")
If ((SCB0 == 1)) {
L23R = 1
Local0 = 0
While (L23R) {
If ((Local0 > 4)) {
Break
}
Sleep (16)
Local0++
}
SCB0 = 0
Local0 = 0
While ((LASX == 0)) {
If ((Local0 > 8)) {
Break
}
Sleep (16)
Local0++
}
}
Printf(" GPU PORT L23D FINISH")
}
Method (HPME, 0, Serialized) {
Printf(" GPU PORT HPME START")
If (PMSX == 1) {
Printf(" Notify GPU driver of PME SCI")
Notify(DEV0, 0x2)
Printf(" Clear PME SCI")
PMSX = 1
Printf(" Consume PME notification")
PSPX = 1
}
Printf(" GPU PORT HPME FINISH")
}
// Main power resource
PowerResource (PWRR, 0, 0) {
Name (_STA, 1)
Method (_ON, 0, Serialized) {
Printf("GPU PORT PWRR._ON")
HPME();
If (PMEX == 1) {
Printf(" Disable power management SCI")
PMEX = 0
}
^^DEV0._ON()
_STA = 1
}
Method (_OFF, 0, Serialized) {
Printf("GPU PORT PWRR._OFF")
^^DEV0._OFF()
If (PMEX == 0) {
Printf(" Enable power management SCI")
PMEX = 1
HPME()
}
_STA = 0
}
}
// Power resources for entering D0
Name (_PR0, Package () { PWRR })
// Power resources for entering D3
Name (_PR3, Package () { PWRR })
#include "common/gpu.asl"

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
#define _DRIVERS_GFX_NVIDIA_CHIP_H_
struct drivers_gfx_nvidia_config {
/* TODO: Set GPIOs in devicetree? */
};
#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
#define _DRIVERS_GFX_NVIDIA_GPU_H_
#include <stdbool.h>
struct nvidia_gpu_config {
/* GPIO for GPU_PWR_EN */
unsigned int power_gpio;
/* GPIO for GPU_RST# */
unsigned int reset_gpio;
/* Enable or disable GPU power */
bool enable;
};
void nvidia_set_power(const struct nvidia_gpu_config *config);
#endif /* _DRIVERS_NVIDIA_GPU_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
static void nvidia_read_resources(struct device *dev)
{
printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
pci_dev_read_resources(dev);
// Find all BARs on GPU, mark them above 4g if prefetchable
for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
struct resource *res = probe_resource(dev, bar);
if (res) {
if (res->flags & IORESOURCE_PREFETCH) {
printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar);
res->flags |= IORESOURCE_ABOVE_4G;
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar);
}
} else {
printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar);
}
}
}
static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
{
pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations nvidia_device_ops_pci = {
.set_subsystem = nvidia_set_subsystem,
};
static struct device_operations nvidia_device_ops = {
.read_resources = nvidia_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = pci_rom_write_acpi_tables,
.acpi_fill_ssdt = pci_rom_ssdt,
#endif
.init = pci_dev_init,
.ops_pci = &nvidia_device_ops_pci,
};
static void nvidia_enable(struct device *dev)
{
if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
return;
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
return;
dev->ops = &nvidia_device_ops;
}
struct chip_operations drivers_gfx_nvidia_ops = {
CHIP_NAME("NVIDIA Optimus Graphics Device")
.enable_dev = nvidia_enable
};

View File

@@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
#include "chip.h"
#include "gpu.h"
void nvidia_set_power(const struct nvidia_gpu_config *config)
{
if (!config->power_gpio || !config->reset_gpio) {
printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
return;
}
printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
gpio_set(config->reset_gpio, 0);
mdelay(10);
if (config->enable) {
gpio_set(config->power_gpio, 1);
mdelay(25);
gpio_set(config->reset_gpio, 1);
} else {
gpio_set(config->power_gpio, 0);
}
mdelay(10);
}

View File

@@ -18,6 +18,11 @@ config EC_SYSTEM76_EC_DGPU
bool
default n
config EC_SYSTEM76_EC_LOCKDOWN
depends on EC_SYSTEM76_EC
bool
default n
config EC_SYSTEM76_EC_OLED
depends on EC_SYSTEM76_EC
bool

View File

@@ -2,6 +2,7 @@
ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
all-y += system76_ec.c
ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
endif

View File

@@ -0,0 +1,61 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <commonlib/region.h>
#include <fmap.h>
#include <spi_flash.h>
#include "system76_ec.h"
static int protect_region_by_name(const char *name)
{
int res;
struct region region;
res = fmap_locate_area(name, &region);
if (res < 0) {
printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
return res;
}
res = spi_flash_ctrlr_protect_region(
boot_device_spi_flash(),
&region,
WRITE_PROTECT
);
if (res < 0) {
printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
return res;
}
printk(BIOS_INFO, "protected '%s'\n", name);
return 0;
}
static void lock(void *unused)
{
uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
if (system76_ec_security_get(&state) < 0) {
printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
}
printk(BIOS_INFO, "security state: %d\n", state);
if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
// Protect WP_RO region, which should contain FMAP and COREBOOT
protect_region_by_name("WP_RO");
// Protect RW_MRC_CACHE region, this must be done after it is written
protect_region_by_name("RW_MRC_CACHE");
//TODO: protect entire flash except when in SMM?
}
}
/*
* Keep in sync with mrc_cache.c
*/
#if CONFIG(MRC_WRITE_NV_LATE)
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
#else
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
#endif

View File

@@ -3,6 +3,7 @@
#include <arch/io.h>
#include <console/system76_ec.h>
#include <timer.h>
#include "system76_ec.h"
// This is the command region for System76 EC firmware. It must be
// enabled for LPC in the mainboard.
@@ -11,15 +12,22 @@
#define REG_CMD 0
#define REG_RESULT 1
#define REG_DATA 2
// When command register is 0, command is complete
#define CMD_FINISHED 0
// Print command. Registers are unique for each command
#define CMD_PRINT 4
#define CMD_PRINT_REG_FLAGS 2
#define CMD_PRINT_REG_LEN 3
#define CMD_PRINT_REG_DATA 4
#define CMD_PRINT_REG_FLAGS REG_DATA
#define CMD_PRINT_REG_LEN (REG_DATA + 1)
#define CMD_PRINT_REG_DATA (REG_DATA + 2)
// Get security state command
#define CMD_SECURITY_GET 20
// OK result, any other values are errors
#define RESULT_OK 0
static inline uint8_t system76_ec_read(uint8_t addr)
{
@@ -59,3 +67,81 @@ void system76_ec_print(uint8_t byte)
if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
system76_ec_flush();
}
// Issue a command not checking if the console needs to be flushed
// Do not print from this command to avoid EC protocol issues
static int system76_ec_unsafe(uint8_t cmd, uint8_t * data, int length) {
// Error if length is too long
if (length > (SYSTEM76_EC_SIZE - REG_DATA)) {
return -1;
}
// Error if command is in progress
if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
return -1;
}
// Write command data
for (int i = 0; i < length; i++) {
system76_ec_write(REG_DATA + i, data[i]);
}
// Start command
system76_ec_write(REG_CMD, cmd);
// Wait for command completion, for up to 10 milliseconds, with a
// test period of 1 microsecond
wait_us(10000, system76_ec_read(REG_CMD) == CMD_FINISHED);
// Error if command did not complete
if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
return -1;
}
// Read command data
for (int i = 0; i < length; i++) {
data[i] = system76_ec_read(REG_DATA + i);
}
// Check result
if (system76_ec_read(REG_RESULT) != RESULT_OK) {
return -1;
}
return 0;
}
// Wrapper to allow issuing commands while console is being used
// Do not print from this command to avoid EC protocol issues
static int system76_ec_command(uint8_t cmd, uint8_t * data, int length) {
// Error if command is in progress
if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
return -1;
}
// Flush print buffer if it has data
// Checked for completion by system76_ec_unsafe
if (system76_ec_read(CMD_PRINT_REG_LEN) > 0) {
system76_ec_flush();
}
// Run command now that print buffer is flushed
int res = system76_ec_unsafe(cmd, data, length);
if (res < 0) {
return res;
}
// Clear command data (for future prints)
// Length is checked by system76_ec_unsafe
for (int i = 0; i < length; i++) {
system76_ec_write(REG_DATA + i, 0);
}
return 0;
}
// Get security state
int system76_ec_security_get(uint8_t * state) {
*state = 0;
return system76_ec_command(CMD_SECURITY_GET, state, sizeof(uint8_t));
}

View File

@@ -0,0 +1,16 @@
#ifndef EC_SYSTEM76_EC_H
#define EC_SYSTEM76_EC_H
// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
// Flashing is allowed, cannot be set with CMD_SECURITY_SET
#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
// Flashing will be prevented on the next reboot
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
// Flashing will be allowed on the next reboot
#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
// Get security state
int system76_ec_security_get(uint8_t * state);
#endif /* EC_SYSTEM76_EC_H */

View File

@@ -62,7 +62,11 @@
#define CPUID_ALDERLAKE_N_A0 0xb06e0
#define CPUID_METEORLAKE_A0_1 0xa06a0
#define CPUID_METEORLAKE_A0_2 0xa06a1
#define CPUID_RAPTORLAKE_P_J0 0xb06a2
#define CPUID_RAPTORLAKE_P_Q0 0xb06a3
#define CPUID_RAPTORLAKE_E_S_HX_B0 0xb0671
#define CPUID_RAPTORLAKE_HX_S_8_8_C0 0xb06f2
#define CPUID_RAPTORLAKE_H_P_J0 0xb06a2
#define CPUID_RAPTORLAKE_S_6_0_C0 0xb06f5
#define CPUID_RAPTORLAKE_S_A0 0xb0670
#define CPUID_RAPTORLAKE_U_Q0 0xb06a3
#endif /* CPU_INTEL_CPU_IDS_H */

View File

@@ -3462,6 +3462,35 @@
#define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d
#define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d
#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a
#define PCI_DID_INTEL_RPP_S_PCIE_RP4 0x7a3b
#define PCI_DID_INTEL_RPP_S_PCIE_RP5 0x7a3c
#define PCI_DID_INTEL_RPP_S_PCIE_RP6 0x7a3d
#define PCI_DID_INTEL_RPP_S_PCIE_RP7 0x7a3e
#define PCI_DID_INTEL_RPP_S_PCIE_RP8 0x7a3f
#define PCI_DID_INTEL_RPP_S_PCIE_RP9 0x7a30
#define PCI_DID_INTEL_RPP_S_PCIE_RP10 0x7a31
#define PCI_DID_INTEL_RPP_S_PCIE_RP11 0x7a32
#define PCI_DID_INTEL_RPP_S_PCIE_RP12 0x7a33
#define PCI_DID_INTEL_RPP_S_PCIE_RP13 0x7a34
#define PCI_DID_INTEL_RPP_S_PCIE_RP14 0x7a35
#define PCI_DID_INTEL_RPP_S_PCIE_RP15 0x7a36
#define PCI_DID_INTEL_RPP_S_PCIE_RP16 0x7a37
#define PCI_DID_INTEL_RPP_S_PCIE_RP17 0x7a40
#define PCI_DID_INTEL_RPP_S_PCIE_RP18 0x7a41
#define PCI_DID_INTEL_RPP_S_PCIE_RP19 0x7a42
#define PCI_DID_INTEL_RPP_S_PCIE_RP20 0x7a43
#define PCI_DID_INTEL_RPP_S_PCIE_RP21 0x7a44
#define PCI_DID_INTEL_RPP_S_PCIE_RP22 0x7a45
#define PCI_DID_INTEL_RPP_S_PCIE_RP23 0x7a46
#define PCI_DID_INTEL_RPP_S_PCIE_RP24 0x7a47
#define PCI_DID_INTEL_RPP_S_PCIE_RP25 0x7a48
#define PCI_DID_INTEL_RPP_S_PCIE_RP26 0x7a49
#define PCI_DID_INTEL_RPP_S_PCIE_RP27 0x7a4a
#define PCI_DID_INTEL_RPP_S_PCIE_RP28 0x7a4b
/* Intel SATA device Ids */
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00
#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02
@@ -3536,6 +3565,7 @@
#define PCI_DID_INTEL_MTL_SATA 0x7e63
#define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3
#define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7
#define PCI_DID_INTEL_RPP_S_SATA 0x7a62
/* Intel PMC device Ids */
#define PCI_DID_INTEL_SPT_LP_PMC 0x9d21
@@ -3671,6 +3701,13 @@
#define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5
#define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6
#define PCI_DID_INTEL_RPP_S_I2C0 0x7a4c
#define PCI_DID_INTEL_RPP_S_I2C1 0x7a4d
#define PCI_DID_INTEL_RPP_S_I2C2 0x7a4e
#define PCI_DID_INTEL_RPP_S_I2C3 0x7a4f
#define PCI_DID_INTEL_RPP_S_I2C4 0x7a7c
#define PCI_DID_INTEL_RPP_S_I2C5 0x7a7d
#define PCI_DID_INTEL_MTL_I2C0 0x7e78
#define PCI_DID_INTEL_MTL_I2C1 0x7e79
#define PCI_DID_INTEL_MTL_I2C2 0x7e7a
@@ -3748,6 +3785,11 @@
#define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7
#define PCI_DID_INTEL_ADP_M_N_UART3 0x54da
#define PCI_DID_INTEL_RPP_S_UART0 0x7a28
#define PCI_DID_INTEL_RPP_S_UART1 0x7a29
#define PCI_DID_INTEL_RPP_S_UART2 0x7a7e
#define PCI_DID_INTEL_RPP_S_UART3 0x7a5c
#define PCI_DID_INTEL_MTL_UART0 0x7e25
#define PCI_DID_INTEL_MTL_UART1 0x7e26
#define PCI_DID_INTEL_MTL_UART2 0x7e52
@@ -3833,6 +3875,12 @@
#define PCI_DID_INTEL_ADP_M_N_SPI1 0x54ab
#define PCI_DID_INTEL_ADP_M_SPI2 0x54fb
#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI 0x7a24
#define PCI_DID_INTEL_RPP_S_SPI0 0x7a2a
#define PCI_DID_INTEL_RPP_S_SPI1 0x7a2b
#define PCI_DID_INTEL_RPP_S_SPI2 0x7a7b
#define PCI_DID_INTEL_RPP_S_SPI3 0x7a79
#define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca
#define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23
@@ -3983,6 +4031,10 @@
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
#define PCI_DID_INTEL_RPL_HX_GT1 0xa788
#define PCI_DID_INTEL_RPL_HX_GT2 0xa78b
#define PCI_DID_INTEL_RPL_HX_GT3 0x4688
#define PCI_DID_INTEL_RPL_HX_GT4 0x468b
#define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0
@@ -4106,6 +4158,14 @@
#define PCI_DID_INTEL_MTL_P_ID_2 0x7D02
#define PCI_DID_INTEL_MTL_P_ID_3 0x7d14
#define PCI_DID_INTEL_MTL_P_ID_4 0x7d15
#define PCI_DID_INTEL_RPL_HX_ID_1 0xa702
#define PCI_DID_INTEL_RPL_HX_ID_2 0xa729
#define PCI_DID_INTEL_RPL_HX_ID_3 0xa728
#define PCI_DID_INTEL_RPL_HX_ID_4 0xa72a
#define PCI_DID_INTEL_RPL_HX_ID_5 0xa719
#define PCI_DID_INTEL_RPL_HX_ID_6 0x4637
#define PCI_DID_INTEL_RPL_HX_ID_7 0x463b
#define PCI_DID_INTEL_RPL_HX_ID_8 0x4647
#define PCI_DID_INTEL_RPL_P_ID_1 0xa706
#define PCI_DID_INTEL_RPL_P_ID_2 0xa707
#define PCI_DID_INTEL_RPL_P_ID_3 0xa708
@@ -4136,6 +4196,7 @@
#define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3
#define PCI_DID_INTEL_MTL_SMBUS 0x7e22
#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
/* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
@@ -4172,6 +4233,7 @@
#define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0
#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
/* Intel P2SB device Ids */
#define PCI_DID_INTEL_APL_P2SB 0x5a92
@@ -4240,6 +4302,14 @@
#define PCI_DID_INTEL_ADP_S_AUDIO_8 0x7ad7
#define PCI_DID_INTEL_ADP_P_AUDIO 0x51c8
#define PCI_DID_INTEL_RPP_P_AUDIO 0x51ca
#define PCI_DID_INTEL_RPP_S_AUDIO_1 0x7a50
#define PCI_DID_INTEL_RPP_S_AUDIO_2 0x7a51
#define PCI_DID_INTEL_RPP_S_AUDIO_3 0x7a52
#define PCI_DID_INTEL_RPP_S_AUDIO_4 0x7a53
#define PCI_DID_INTEL_RPP_S_AUDIO_5 0x7a54
#define PCI_DID_INTEL_RPP_S_AUDIO_6 0x7a55
#define PCI_DID_INTEL_RPP_S_AUDIO_7 0x7a56
#define PCI_DID_INTEL_RPP_S_AUDIO_8 0x7a57
#define PCI_DID_INTEL_ADP_M_N_AUDIO_1 0x54c8
#define PCI_DID_INTEL_ADP_M_N_AUDIO_2 0x54c9
@@ -4296,6 +4366,10 @@
#define PCI_DID_INTEL_ADP_M_CSE1 0x54e1
#define PCI_DID_INTEL_ADP_M_CSE2 0x54e4
#define PCI_DID_INTEL_ADP_M_CSE3 0x54e5
#define PCI_DID_INTEL_RPP_S_CSE0 0x7a68
#define PCI_DID_INTEL_RPP_S_CSE1 0x7a69
#define PCI_DID_INTEL_RPP_S_CSE2 0x7a6c
#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
#define PCI_DID_INTEL_MTL_CSE0 0x7e70
/* Intel XDCI device Ids */
@@ -4319,6 +4393,7 @@
#define PCI_DID_INTEL_MTL_XDCI 0x7e7e
#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
#define PCI_DID_INTEL_RPP_S_XDCI 0x7a61
/* Intel SD device Ids */
#define PCI_DID_INTEL_LPT_LP_SD 0x9c35
@@ -4459,6 +4534,10 @@
#define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41
#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42
#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73
/* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
@@ -4469,6 +4548,7 @@
#define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM 0xa0ef
#define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d
#define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d
#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM 0x7a27
/* Intel Ethernet Controller device Ids */
#define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32

View File

@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC

View File

@@ -1,4 +1,4 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

View File

@@ -1,11 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#define EC_GPE_SCI 0x03 /* GPP_K3 */
#define EC_GPE_SWI 0x06 /* GPP_K6 */
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
Device (PEGP) {
Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
}
}
}
Scope (\_GPE) {

View File

@@ -58,6 +58,12 @@ chip soc/intel/cannonlake
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on # SA Thermal device

View File

@@ -1,7 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
@@ -20,8 +22,20 @@ static const struct cnl_mb_cfg memcfg = {
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
// Allow higher memory speeds
memupd->FspmConfig.SaOcSupport = 1;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
// Disable higher memory speeds
memupd->FspmConfig.SaOcSupport = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

View File

@@ -3,7 +3,16 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_SSID 0x65d11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

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@@ -3,7 +3,16 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_C12
#define DGPU_SSID 0x65e11558
#ifndef __ACPI__
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif
#endif

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@@ -1,70 +0,0 @@
if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
config MAINBOARD_DIR
default "system76/adl-p"
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
default "Galago Pro" if BOARD_SYSTEM76_GALP6
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
config CBFS_SIZE
default 0xA00000
config CONSOLE_POST
default y
config DIMM_SPD_SIZE
default 512
config POST_DEVICE
default n
config TPM_MEASURED_BOOT
default y
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@@ -1,5 +0,0 @@
config BOARD_SYSTEM76_DARP8
bool "darp8"
config BOARD_SYSTEM76_GALP6
bool "galp6"

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@@ -0,0 +1,136 @@
config BOARD_SYSTEM76_ADL_COMMON
def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_LOCKDOWN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
config BOARD_SYSTEM76_DARP8
select BOARD_SYSTEM76_ADL_COMMON
select EC_SYSTEM76_EC_COLOR_KEYBOARD
config BOARD_SYSTEM76_GALP6
select BOARD_SYSTEM76_ADL_COMMON
config BOARD_SYSTEM76_GAZE17_3050
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select TPM_RDRESP_NEED_DELAY
config BOARD_SYSTEM76_GAZE17_3060_B
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select MAINBOARD_USES_IFD_GBE_REGION
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select TPM_RDRESP_NEED_DELAY
config BOARD_SYSTEM76_LEMP11
select BOARD_SYSTEM76_ADL_COMMON
select HAVE_SPD_IN_CBFS
config BOARD_SYSTEM76_ORYP9
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select DRIVERS_I2C_TAS5825M
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
config BOARD_SYSTEM76_ORYP10
select BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_GFX_NVIDIA
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
if BOARD_SYSTEM76_ADL_COMMON
config MAINBOARD_DIR
default "system76/adl"
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
default "Galago Pro" if BOARD_SYSTEM76_GALP6
default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
config CONSOLE_POST
default y
config DIMM_SPD_SIZE
default 512
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
config ONBOARD_VGA_IS_PRIMARY
default y
config POST_DEVICE
default n
config TPM_MEASURED_BOOT
default y
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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@@ -0,0 +1,20 @@
config BOARD_SYSTEM76_DARP8
bool "darp8"
config BOARD_SYSTEM76_GALP6
bool "galp6"
config BOARD_SYSTEM76_GAZE17_3050
bool "gaze17 3050"
config BOARD_SYSTEM76_GAZE17_3060_B
bool "gaze17 3060-b"
config BOARD_SYSTEM76_LEMP11
bool "lemp11"
config BOARD_SYSTEM76_ORYP9
bool "oryp9"
config BOARD_SYSTEM76_ORYP10
bool "oryp10"

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@@ -0,0 +1,16 @@
## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
SPD_SOURCES = samsung-P4AAF165WA-BCWDE

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@@ -1,5 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(DRIVERS_GFX_NVIDIA)
#include <variant/gpio.h>
#endif
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
#if CONFIG(DRIVERS_GFX_NVIDIA)
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#endif
}
}

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@@ -0,0 +1,15 @@
FLASH 32M {
SI_DESC 4K
#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION
SI_GBE 8K
#endif
SI_ME 4824K
SI_BIOS@16M 16M {
RW_MRC_CACHE 64K
SMMSTORE(PRESERVE) 256K
WP_RO {
FMAP 4K
COREBOOT(CBFS)
}
}
}

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@@ -1,3 +1,3 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable
me_state=Disable

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@@ -11,8 +11,6 @@ chip soc/intel/alderlake
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
register "s0ix_enable" = "1"
# Enable C6 DRAM
register "enable_c6dram" = "1"
@@ -72,9 +70,8 @@ chip soc/intel/alderlake
device ref heci1 on end
device ref sata on
register "sata_salp_support" = "1"
register "sata_ports_enable[1]" = "1" # SSD1
# FIXME: DevSlp breaks S0ix
#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
register "sata_ports_enable[1]" = "1"
register "sata_ports_dev_slp[1]" = "1"
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel

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@@ -0,0 +1,33 @@
# Samsung P4AAF165WA-BCWDE
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 DE DE
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 CE 00 00 00 00 00 00 00 50 34 41 41 46 31 36
35 57 41 2D 42 43 57 44 45 20 20 20 20 00 80 CE
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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@@ -0,0 +1,2 @@
Board name: gaze17-3050
Release year: 2022

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@@ -0,0 +1,227 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
PAD_NC(GPP_A11, NONE),
PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
//PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN
PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST#
//PAD_NC(GPP_B9, NONE),
//PAD_NC(GPP_B10, NONE),
PAD_NC(GPP_B11, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP
//PAD_NC(GPP_B19, NONE),
//PAD_NC(GPP_B20, NONE),
//PAD_NC(GPP_B21, NONE),
//PAD_NC(GPP_B22, NONE),
PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
PAD_NC(GPP_C3, NONE), // SML0_CLK
PAD_NC(GPP_C4, NONE), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP
PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL
PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA
//PAD_NC(GPP_C8, NONE),
//PAD_NC(GPP_C9, NONE),
//PAD_NC(GPP_C10, NONE),
//PAD_NC(GPP_C11, NONE),
//PAD_NC(GPP_C12, NONE),
//PAD_NC(GPP_C13, NONE),
//PAD_NC(GPP_C14, NONE),
//PAD_NC(GPP_C15, NONE),
//PAD_NC(GPP_C16, NONE),
//PAD_NC(GPP_C17, NONE),
//PAD_NC(GPP_C18, NONE),
//PAD_NC(GPP_C19, NONE),
//PAD_NC(GPP_C20, NONE),
//PAD_NC(GPP_C21, NONE),
//PAD_NC(GPP_C22, NONE),
//PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
PAD_NC(GPP_D13, NONE),
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE#
PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_NC(GPP_E12, NONE),
PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
PAD_NC(GPP_E18, NONE),
PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE),
//PAD_NC(GPP_F8, NONE),
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST#
PAD_NC(GPP_F11, NONE), // ADDS_CODE
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_F15, NONE),
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_NC(GPP_F17, NONE),
PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE),
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA
PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
PAD_NC(GPP_H12, NONE),
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
//PAD_NC(GPP_H14, NONE),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
//PAD_NC(GPP_H16, NONE),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_NC(GPP_R5, NONE),
PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK
PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256, /* Vendor ID */
0x1558866d, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x1558866d),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {
// Adjust mic coefficient
0x02050007,
0x02040202,
};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x866d1558
#endif

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chip soc/intel/alderlake
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
device domain 0 on
subsystemid 0x1558 0x866d inherit
device ref pcie5_0 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 off end
device ref tbt_pcie_rp0 off end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
end
device ref pcie_rp5 on
# PCIe RP#5 x4, Clock 1 (SSD)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true"
register "srcclk_pin" = "1" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp9 on
# PCIe RP#9 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to VDD3?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "6" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp10 on
# PCIe RP#10 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp11 on
# PCIe RP#11 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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Board name: gaze17-3060-b
Release year: 2022

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16)
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_NC(GPP_A8, NONE),
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD
PAD_NC(GPP_A16, NONE), // USB_OC3#
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE#
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
//PAD_CFG_GPO(GPP_B9, 0, DEEP),
//PAD_CFG_GPO(GPP_B10, 0, DEEP),
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24
//PAD_CFG_GPO(GPP_B19, 0, DEEP),
//PAD_CFG_GPO(GPP_B20, 0, DEEP),
//PAD_CFG_GPO(GPP_B21, 0, DEEP),
//PAD_CFG_GPO(GPP_B22, 0, DEEP),
PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA
//PAD_NC(GPP_C8, NONE),
//PAD_NC(GPP_C9, NONE),
//PAD_NC(GPP_C10, NONE),
//PAD_NC(GPP_C11, NONE),
//PAD_NC(GPP_C12, NONE),
//PAD_NC(GPP_C13, NONE),
//PAD_NC(GPP_C14, NONE),
//PAD_NC(GPP_C15, NONE),
//PAD_NC(GPP_C16, NONE),
//PAD_NC(GPP_C17, NONE),
//PAD_NC(GPP_C18, NONE),
//PAD_NC(GPP_C19, NONE),
//PAD_NC(GPP_C20, NONE),
//PAD_NC(GPP_C21, NONE),
//PAD_NC(GPP_C22, NONE),
//PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW
//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ#
//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ#
//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ#
PAD_NC(GPP_D9, NONE),
PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24
PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_NC(GPP_E10, NONE),
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN#
PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
PAD_NC(GPP_E20, NONE),
PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
//PAD_CFG_GPO(GPP_F8, 0, DEEP),
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST#
PAD_NC(GPP_F11, NONE),
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_NC(GPP_F14, NONE),
PAD_NC(GPP_F15, NONE),
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST#
PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24
PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD
PAD_NC(GPP_H12, NONE),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1
//PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
//PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC
PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS
//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
PAD_NC(GPP_R5, NONE),
PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1
PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256, /* Vendor ID */
0x1558867c, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x1558867c),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_F13
#define DGPU_SSID 0x867c1558
#endif

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chip soc/intel/alderlake
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
device domain 0 on
subsystemid 0x1558 0x867c inherit
device ref pcie5_0 on
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
end
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref i2c1 off end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref tcss_dma0 on end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: No enable_gpio = no D3cold?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 6 (GLAN)
# Clock source is shared with LAN and hence marked as free running.
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
}"
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true" # Fixes suspend on WD drives
register "srcclk_pin" = "1" # SSD_CLKREQ#
device generic 0 on end
end
end
device ref gbe on end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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Board name: lemp11
Release year: 2022

Binary file not shown.

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_NC(GPD11, NONE),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_NC(GPP_A8, NONE),
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
PAD_NC(GPP_A14, NONE),
PAD_NC(GPP_A15, NONE),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
PAD_NC(GPP_A17, NONE),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT#
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
// GPP_B9 missing
// GPP_B10 missing
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#
PAD_NC(GPP_B18, NONE), // NO REBOOT strap
// GPP_B19 missing
// GPP_B20 missing
// GPP_B21 missing
// GPP_B22 missing
PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
// GPP_C8 missing
// GPP_C9 missing
// GPP_C10 missing
// GPP_C11 missing
// GPP_C12 missing
// GPP_C13 missing
// GPP_C14 missing
// GPP_C15 missing
// GPP_C16 missing
// GPP_C17 missing
// GPP_C18 missing
// GPP_C19 missing
// GPP_C20 missing
// GPP_C21 missing
// GPP_C22 missing
// GPP_C23 missing
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),
// GPP_D5 (SSD0_CLKREQ#) configured by FSP
// GPP_D6 (SSD1_CLKREQ#) configured by FSP
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
PAD_NC(GPP_D15, NONE),
PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED#
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_NC(GPP_E2, NONE),
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_NC(GPP_E10, NONE),
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_NC(GPP_E13, NONE),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_NC(GPP_E17, NONE),
// GPP_E18 (TBT_LSX0_TXD) configured by FSP
// GPP_E19 (TBT_LSX0_RXD) configured by FSP
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
// GPP_F5 (CNVI_CLKREQ) configured by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
// GPP_F8 missing
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST#
PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_NC(GPP_F14, NONE),
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
// GPP_F19 (CARD_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST#
PAD_NC(GPP_H1, NONE),
PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
// GPP_H10 (UART0_RX) configured in bootblock
// GPP_H11 (UART0_TX) configured in bootblock
PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
PAD_NC(GPP_H13, NONE),
// GPP_H14 missing
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
// GPP_H16 missing
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN#
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE),
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE), // DMIC_CLK
PAD_NC(GPP_R7, NONE), // DMIC_DAT
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256,
0x15587718,
11,
AZALIA_SUBVENDOR(0, 0x15587718),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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chip soc/intel/alderlake
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 46,
.tdp_pl4 = 65,
}"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_A"
register "pmc_gpe0_dw1" = "PMC_GPP_R"
register "pmc_gpe0_dw2" = "PMC_GPD"
device domain 0 on
subsystemid 0x1558 0x7718 inherit
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
register "srcclk_pin" = "0" # SSD0_CLKREQ#
device generic 0 on end
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""TBT Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Left""
register "type" = "UPC_TYPE_A"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Right""
register "type" = "UPC_TYPE_A"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 3G/LTE""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Left""
register "type" = "UPC_TYPE_A"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Right""
register "type" = "UPC_TYPE_A"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb3_port3 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref pcie_rp5 on
# PCIe RP#5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe RP#6 x1, Clock 6 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref pcie_rp9 on
# PCIe RP#9 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST#
register "srcclk_pin" = "1" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
# J_TYPEC1
use usb2_port3 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
end
end
end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_MIXED,
.cbfs_index = 0,
.smbus[1] = { .addr_dimm[0] = 0x52, },
};
const bool half_populated = false;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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Board name: oryp10
Release year: 2022

Binary file not shown.

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_NC(GPD7, NONE),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_NC(GPD11, NONE),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
// GPP_A14 (DGPU_PWR_EN) configured in bootblock
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
PAD_NC(GPP_A16, NONE), // USB_OC3#
PAD_NC(GPP_A17, NONE),
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
PAD_NC(GPP_A19, NONE),
_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
PAD_NC(GPP_A21, NONE),
PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
// GPP_B2 (DGPU_RST#_CPU) configured in bootblock
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
// GPP_B9 missing
// GPP_B10 missing
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_NC(GPP_B14, NONE), // Top swap override
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
// GPP_B19 missing
// GPP_B20 missing
// GPP_B21 missing
// GPP_B22 missing
PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
// GPP_C8 missing
// GPP_C9 missing
// GPP_C10 missing
// GPP_C11 missing
// GPP_C12 missing
// GPP_C13 missing
// GPP_C14 missing
// GPP_C15 missing
// GPP_C16 missing
// GPP_C17 missing
// GPP_C18 missing
// GPP_C19 missing
// GPP_C20 missing
// GPP_C21 missing
// GPP_C22 missing
// GPP_C23 missing
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
// GPP_D5 (SSD0_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
// GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
// GPP_E18 (TBTA_LSX2_TXD) configured by FSP
// GPP_E19 (TBTA_LSX2_RXD) configured by FSP
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE), // Strap
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
// GPP_F5 (CNVI_CLKREQ) configured by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
// GPP_F8 missing
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
PAD_NC(GPP_F11, NONE),
PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
PAD_NC(GPP_F13, NONE),
PAD_NC(GPP_F14, NONE),
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
PAD_NC(GPP_F18, NONE),
// GPP_F19 (CARD_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
// GPP_H10 (UART0_RX) configured in bootblock
// GPP_H11 (UART0_TX) configured in bootblock
PAD_NC(GPP_H12, NONE),
PAD_NC(GPP_H13, NONE),
// GPP_H14 missing
PAD_NC(GPP_H15, NONE),
// GPP_H16 missing
PAD_NC(GPP_H17, NONE),
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
// GPP_H19 (SSD1_CLKREQ#) configured by FSP
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
// GPP_H23 (GLAN_CLKREQ#) configured by FSP
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC1220 */
0x10ec1220, /* Vendor ID */
0x155867f5, /* Subsystem ID */
152, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155867f5),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
// Enable DMIC microphone on ALC1220
0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
// ALC1306 smart amp
0x02050027, 0x02040010, 0x02050029, 0x02040000,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003f,
0x0205002b, 0x02041000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040004,
0x0205002b, 0x02040600, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x0204c0c0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204ffd0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003a,
0x0205002b, 0x02040dfe, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x02040442, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040005,
0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040006,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040008,
0x0205002b, 0x0204b000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204002e,
0x0205002b, 0x02040800, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x020400c3, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x0204d4a0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x020400cc, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x0204400a, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x020400c1, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x02040320, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040039,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003b,
0x0205002b, 0x0204ffff, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x02049142, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x020400c0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fcf0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003c,
0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040080,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040062,
0x0205002b, 0x02048000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040063,
0x0205002b, 0x02045f5f, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040064,
0x0205002b, 0x02042000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040065,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040066,
0x0205002b, 0x02044004, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040067,
0x0205002b, 0x02040802, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040068,
0x0205002b, 0x0204890f, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040069,
0x0205002b, 0x0204e021, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040070,
0x0205002b, 0x02048012, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040071,
0x0205002b, 0x02043450, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040072,
0x0205002b, 0x02040123, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040073,
0x0205002b, 0x02044543, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040074,
0x0205002b, 0x02042100, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040075,
0x0205002b, 0x02044321, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040076,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040046,
0x0205002b, 0x0204c22e, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040050,
0x0205002b, 0x02048200, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040051,
0x0205002b, 0x02040707, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040052,
0x0205002b, 0x02044090, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x02040090, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x0204721f, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040012,
0x0205002b, 0x0204dfdf, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204009e,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040004,
0x0205002b, 0x02040500, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006a,
0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204006c,
0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x02040060,
0x0205002b, 0x02042213, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003a,
0x0205002b, 0x02041dfe, 0x0205002c, 0x0204b424,
0x02050027, 0x02040010, 0x02050029, 0x0204003f,
0x0205002b, 0x02043000, 0x0205002c, 0x0204b424,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_A7
#define DGPU_SSID 0x65f51558
#endif

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chip soc/intel/alderlake
# HACK: Limit PL4 to prevent power off on battery power.
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_psyspl2 = 135,
.tdp_pl4 = 72,
}"
# Thermal
register "tcc_offset" = "10"
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_A"
register "pmc_gpe0_dw1" = "PMC_GPP_R"
register "pmc_gpe0_dw2" = "PMC_GPD"
device domain 0 on
subsystemid 0x1558 0x65f5 inherit
device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref igpu on
register "ddi_portA_config" = "1"
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
end
device ref pcie4_0 on
# CPU PCIe RP#1 x4, Clock 0 (SSD1)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
end
device ref pcie4_1 on
# CPU PCIe RP#3 x4, Clock 4 (SSD2)
register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR,
}"
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 TYPEC2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB2""
register "type" = "UPC_TYPE_A"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB1""
register "type" = "UPC_TYPE_A"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Per-KB""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Fingerprint""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 TYPEC2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB2""
register "type" = "UPC_TYPE_A"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB2""
register "type" = "UPC_TYPE_A"
device ref usb3_port3 on end
end
end
end
end
device ref sata off end
device ref pcie_rp5 on
# PCIe RP#5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe RP#6 x1, Clock 6 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable connected directly to 3.3VS?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "6" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp8 on
# PCIe RP#8 x1, Clock 5 (GLAN)
register "pch_pcie_rp[PCH_RP(8)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable connected directly to VDD3?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
# TYPEC2
use usb2_port9 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
end
end
end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR5,
.rcomp = { .resistor = 100, },
.ect = true,
.LpDdrDqDqsReTraining = 1,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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Board name: oryp9
Release year: 2022

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <mainboard/gpio.h>
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_NC(GPD7, NONE),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_NC(GPD11, NONE),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
// GPP_A14 (DGPU_PWR_EN) configured in bootblock
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
PAD_NC(GPP_A16, NONE), // USB_OC3#
PAD_NC(GPP_A17, NONE),
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
PAD_NC(GPP_A19, NONE),
_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
PAD_NC(GPP_A21, NONE),
PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
// GPP_B2 (DGPU_RST#_CPU) configured in bootblock
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
// GPP_B9 missing
// GPP_B10 missing
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_NC(GPP_B14, NONE), // Top swap override
PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
// GPP_B19 missing
// GPP_B20 missing
// GPP_B21 missing
// GPP_B22 missing
PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
// GPP_C8 missing
// GPP_C9 missing
// GPP_C10 missing
// GPP_C11 missing
// GPP_C12 missing
// GPP_C13 missing
// GPP_C14 missing
// GPP_C15 missing
// GPP_C16 missing
// GPP_C17 missing
// GPP_C18 missing
// GPP_C19 missing
// GPP_C20 missing
// GPP_C21 missing
// GPP_C22 missing
// GPP_C23 missing
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
// GPP_D5 (SSD0_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
// GPP_D8 (GPU_PCIE_CLKREQ#) configured by FSP
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
// GPP_E18 (TBTA_LSX2_TXD) configured by FSP
// GPP_E19 (TBTA_LSX2_RXD) configured by FSP
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE), // Strap
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
// GPP_F5 (CNVI_CLKREQ) configured by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
// GPP_F8 missing
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
PAD_NC(GPP_F11, NONE),
PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
PAD_NC(GPP_F13, NONE),
PAD_NC(GPP_F14, NONE),
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
PAD_NC(GPP_F18, NONE),
// GPP_F19 (CARD_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
// GPP_H10 (UART0_RX) configured in bootblock
// GPP_H11 (UART0_TX) configured in bootblock
PAD_NC(GPP_H12, NONE),
PAD_NC(GPP_H13, NONE),
// GPP_H14 missing
PAD_NC(GPP_H15, NONE),
// GPP_H16 missing
PAD_NC(GPP_H17, NONE),
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
// GPP_H19 (SSD1_CLKREQ#) configured by FSP
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
// GPP_H23 (GLAN_CLKREQ#) configured by FSP
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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