Compare commits

...

1838 Commits

Author SHA1 Message Date
Tim Crawford
baf80abc62 mb/system76/rpl: gaze18, serw13: Fix USB2 on USB-C port
Use USB2_PORT_MID instead of USB2_PORT_TYPE_C, as was done for addw3.

Change-Id: I7df2bbf1ba70c4e08319b760b2784e15c880a105
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-22 08:40:46 -06:00
Jeremy Soller
192f165edb addw3: Set USB-C ports as USB2_PORT_MID to prevent use of port reset messaging
Change-Id: I1f13edcc3fa757cc0d763be45e6eea0474077984
2023-03-21 19:56:29 -06:00
Subrata Banik
a2c83fb9f9 soc/intel: Update API name pmc_send_bios_reset_pci_enum_done
This patch updates PMC API name from `pmc_send_pci_enum_done` to
`pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done
is also set along with PMC enumeration being done.

BUG=b:270942083
TEST=Able to build and boot google/rex.

Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-21 15:47:22 -06:00
Jeremy Soller
a55e829ae3 soc/intel/alderlake: Correct PCH-S XHCI port information
Change-Id: I405b4f73584f4391152941bbd32e828a2bd0e6aa
2023-03-21 13:39:23 -06:00
Jeremy Soller
20c9608c05 system76/rpl: Remove retimer and PMC driver
Change-Id: Ief2c6db7c1673c414bb2eefdce5efc64144179da
2023-03-21 13:30:23 -06:00
Michał Żygowski
290b1bcda2 soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
2023-03-20 12:22:44 -06:00
Michał Żygowski
77fce247ff soc/intel/alderlake: Hook up P2SB PCI ops
P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.

This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.

TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
2023-03-20 12:22:28 -06:00
Michał Żygowski
84937d76fb soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
2023-03-20 12:21:36 -06:00
Jeremy Soller
09f9c48146 addw3: fix overridetree syntax
Change-Id: I74be236abed233d1211c10131c1a8c27158e0b96
2023-03-20 08:14:16 -06:00
Jeremy Soller
2565fe1bc3 Move RPP-S XHCI from USB4 driver to XHCI driver
Change-Id: I7853de5010123875cb0e0150c2e3763f1d3eaff8
2023-03-18 07:48:47 -06:00
Jeremy Soller
6d4e6615cf addw3: Add pmc_mux driver back
Change-Id: I8e341e34735c23e1cd6de78b264289d3c02e3e59
2023-03-17 12:20:11 -06:00
Tim Crawford
c0e6fa5707 mb/system76/rpl: gaze18: Select TPM_RDRESP_NEED_DELAY
Fixes the SLB 9672 FW15 failing to stop/resume on S3.

Change-Id: Icb950e02374529547de6d12ee589cde0164d4576
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-17 12:09:22 -06:00
Jeremy Soller
8e85530d32 addw3: add USB PLD definitions
Change-Id: Ic09e58df50f188ccffd9f0cfc8931f15dfc9971a
2023-03-17 11:29:08 -06:00
Jeremy Soller
0cfee4eb33 addw3: mark TBT as hotplug
Change-Id: Iaf73d68de6673c5ae89e0b9cad3e7749b2c5db2d
2023-03-17 10:54:50 -06:00
Jeremy Soller
a75c608019 addw3: Add USB ACPI definitions and PMC driver to overridetree
Change-Id: I04d71bfef6b238975fc43a32b08c23ac1b842f70
2023-03-17 10:04:37 -06:00
Jeremy Soller
7285446cc7 addw3: Set LAN clock as free running
Change-Id: I9c3ab8b3af16ff23ebd6751b260ebea30021ec61
2023-03-17 09:10:17 -06:00
Jeremy Soller
a2bbbc6769 mb/system76/tgl-u: Enable reporting CPU C10 state over ESPI
Change-Id: Ia811187df194af596eeea7d4fd7be0de5fa9254c
2023-03-10 13:29:28 -07:00
Tim Crawford
f3c764303c mb/system76/rpl: Declare child device on GLAN port
Declare a child device on the GLAN port so the Ethernet controller is
detected as an onboard device (eno) and not a plugged device (enp).

Change-Id: I43f1b3b749081fd989bb2e5c04f3b616642a5a4f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-09 09:54:15 -07:00
Tim Crawford
b425847fc7 mb/system76/rpl: gaze18: Remove unused card GPIOs
The power and reset lines from the PCH to the card reader are not
actually connected. Power comes directly from the 3.3V rail, and reset
is controlled by `BUF_PLT_RST#`.

Change-Id: I0a0969e9bcdf1dcf5dfdb512cf329409f187f1b5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-09 08:26:16 -07:00
Tim Crawford
3a8ee1a86e mb/system76/adl: Convert gaze17 to variants
Change-Id: I086a13a293986bb82692c08aae8fd675083ff16b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-08 12:57:17 -07:00
Jeremy Soller
05bdd8036d mb/system76/gaze17: reduce diff with mb/system76/adl
Change-Id: Iabb5486576a2c71af58e4abf3e870ff87af60895
2023-03-07 09:58:18 -07:00
Jeremy Soller
ceeb13e465 mb/system76/gaze17: reset HDA codec during init
Change-Id: Ibb69f6d836c56587bfdc4a76f86a48cb4581d3ea
2023-03-07 09:58:18 -07:00
Jeremy Soller
2f39f745c7 mb/system76/gaze17: enable EC lockdown support
Change-Id: I3db7cfc20a5c9b913e88e8cbff0cd2a5c5d4cad9
2023-03-07 09:58:18 -07:00
Jeremy Soller
a6907dc9c0 mb/system76/gaze17: add board.fmd
Change-Id: I70bdedb0b44da4406e91056425b7c0ee28705fb5
2023-03-07 09:58:18 -07:00
Jeremy Soller
065a7147ca mb/system76/gaze17: disable ME by default
Change-Id: I5fd34adba3fe5296c20763136d83025e63fd8a26
2023-03-07 09:58:18 -07:00
Jeremy Soller
0352415888 mb/system76/gaze17: switch to S3
Change-Id: I65d4dc008addceb95d5f37758b98f243b2a290dd
2023-03-07 09:58:18 -07:00
Jeremy Soller
e7d0cb6415 board/system76/adl: Add board.fmd file for all variants
Change-Id: I79f1b0ef9fac4593ce55451a5dc78021790fc830
2023-03-07 09:58:18 -07:00
Jeremy Soller
af0255c565 board/system76/tgl-h: Add board.fmd file for GBE and non-GBE variants
Change-Id: Iacc8ce5225097db3d99181cf8cec5f61f2e7056e
2023-03-07 09:58:18 -07:00
Jeremy Soller
c4393852e5 board/system76/tgl-u: Add board.fmd file for all variants
Change-Id: I408c633e4993bf08853bd0cae98e57d53baa3a79
2023-03-07 09:58:18 -07:00
Jeremy Soller
bf5f325757 board/system76/rpl: Add board.fmd files per variant
Change-Id: If51ae6f4ce71fde6044f9f4d3ae6a9581f48663d
2023-03-07 09:58:18 -07:00
Jeremy Soller
ae35884b09 ec/system76: Support lockdown based on EC security state
Change-Id: I00701aa1397c24efe6f2d163822968b528f5b915
2023-03-07 09:58:18 -07:00
Tim Crawford
4e370bf6ad mb/system76/gaze16: Remove directory
These models were moved to tgl-h. Remove the duplicated files.

Change-Id: If5f719fb162099db340b1f9a1d7a9d29460bc0a3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-03-06 11:15:23 -07:00
Jeremy Soller
43d7fd9d8a addw3: Force TBT power
Change-Id: I40af5500343ea3838545e8053b767670d00ea90a
2023-03-03 10:30:28 -07:00
Jeremy Soller
4f2e68fc4b Move TCSS code to oryp11
Change-Id: I76eec8f7ca69bdc32a57f2e41b64f1e82730c361
2023-03-03 10:29:37 -07:00
Jeremy Soller
c6341b2a42 Revert "soc/intel/alderlake: make it possible to enable TCSS on PCH-S"
This reverts commit c81af77eeb.
2023-03-03 10:23:13 -07:00
Jeremy Soller
983387dbd7 rpl: add one TBT port to devicetree
Change-Id: I0b15f9161f576970ef9feeab7ba7ffdb27070505
2023-03-03 09:16:57 -07:00
Jeremy Soller
c81af77eeb soc/intel/alderlake: make it possible to enable TCSS on PCH-S
Change-Id: I46f29bbe61cdc4fa21ccdabccc7743d0f3cc95b2
2023-03-03 09:16:35 -07:00
Jeremy Soller
7414fdfc54 oryp11: fix subsystem ID
Change-Id: I35e2389d9da16352f2311addfc8572836f3088d2
2023-03-01 09:50:28 -07:00
Jeremy Soller
ef7c7ece8d addw3: attempt to enable GBE
Change-Id: I4dd6ba9487488ab1efe44618795b546cdc518bc0
2023-02-28 14:56:07 -07:00
Tim Crawford
f081430b87 drivers/gfx/nvidia: Increase power sequence delays
The serw13 with the 4070 RTX sometimes fails to enumerate the dGPU.
Increasing the delays allows the dGPU to be enumerated consistently. The
values are arbitrary, but still less than the values from proprietary
firmware.

Change-Id: Ibbfda596a324df4b51d583af8d6a36b5cd53a561
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-28 14:17:36 -07:00
Jeremy Soller
ee6e82c96f rpl: remove drivers/gfx/nvidia from overridetrees
Change-Id: I142802b24b176e0662434a6c2005ab52bbf4508b
2023-02-28 12:21:22 -07:00
Jeremy Soller
58f4c7fe95 addw3: Do not configure GPIOs already configured
Change-Id: Ic2702d798ae46cff22e8ef2e9f76e1f69966ea86
2023-02-27 14:25:28 -07:00
Jeremy Soller
314b707dc5 rpl: Set UART_FOR_CONSOLE based on each variant
Change-Id: I43c9f828344981ddd9fd58e671767fbc6fb28de1
2023-02-27 14:25:04 -07:00
Jeremy Soller
e484088ff0 Add RPP-S crashlog IDs
Change-Id: I6837dd95b89e59a90ac8d75433da1fc1195b9ed6
2023-02-27 13:43:45 -07:00
Jeremy Soller
ce9c271317 Add RPP-S CSE IDs
Change-Id: I53b625ed1b2382c33f20cb7fff663d6bd62dc971
2023-02-27 13:43:44 -07:00
Jeremy Soller
15c05a7ac2 adl: Disable ME by default
Change-Id: I90119ef9bf8fa207dcda6c3f64246148344cde40
2023-02-27 13:01:18 -07:00
Jeremy Soller
57aecc8c0a adl: Switch to S3
Change-Id: Ief43a23fd5af37f6d8384d21254d6d1ad7697376
2023-02-27 13:01:05 -07:00
Jeremy Soller
d9f6e2e5fa Revert "rpl: disable stage cache and mcache, which fixes S3"
This reverts commit d50557739d.
2023-02-27 13:00:41 -07:00
Jeremy Soller
caad869cac rpl: Disable ME by default
Change-Id: Id198487f23284f0d3b307d05998d7b209835c680
2023-02-27 12:58:20 -07:00
Jeremy Soller
6215792619 rpl: Re-enable TPM_MEASURED_BOOT
Change-Id: I0ab5dd4e8ca371646f7615d2ea52038420157f93
2023-02-27 12:30:03 -07:00
Jeremy Soller
3dc572fc6d security/tpm/tspi/log: Respect cbmem TPM log size when copying preram entries
Change-Id: I0f08a5bbdb7b823e3a12770154101d49055f263e
2023-02-27 12:29:28 -07:00
Jeremy Soller
0c44e8ed3e security/tpm/tspi: Fix preram TPM log max entries
Change-Id: I671fcd891367d3cbae4fc2d18db5a73ee8c15e8f
2023-02-27 12:16:12 -07:00
Jeremy Soller
87058c3e2a Temporarily disable TPM_MEASURED_BOOT
Change-Id: I6fcad9de26a52c51d2a88a041ec277a63239d05d
2023-02-27 11:52:10 -07:00
Jeremy Soller
7f3969da81 oryp11: Do not configure clock reqs, FSP will do that
Change-Id: I75e0b2fe7dfbcbc9400825e03218a6c21c265ff2
2023-02-27 08:47:19 -07:00
Jeremy Soller
53bf009c47 oryp11: Add GPIO definitions
Change-Id: I58001b408e89fcfb232f6707fb762c10ca55d84c
2023-02-27 08:42:59 -07:00
Jeremy Soller
d50557739d rpl: disable stage cache and mcache, which fixes S3
Change-Id: Ibb662bedc25c70bd5e077f1e91d2402bac16fe0c
2023-02-25 20:32:36 -07:00
Jeremy Soller
c941132543 rpl: Enable resizable BAR
Change-Id: I513974b521b774bfdd550a118ac9007b94b187f1
2023-02-25 20:32:36 -07:00
Jeremy Soller
69353f4094 Revert "rpl: Switch to S0iX"
This reverts commit e0bf2e4691.
2023-02-25 20:32:36 -07:00
Tim Crawford
5263effa38 serw13: Disable AER for SSD1
Enabling AER causes a constant flood of corrected error messages being
logged when using a 980 PRO, quickly filling the drive's free space.

Change-Id: Ib89c579f36e2fc53c9816f0033cd981aae4d7526
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-24 15:48:43 -07:00
Jeremy Soller
4d321cd02e rpl: Ensure touchpad IRQs are correct on RPL-H
Change-Id: I4e210df8494263618e8fe21cfc2fd250963b37ed
2023-02-22 19:07:14 -07:00
Jeremy Soller
22e04bcb30 rpl: Enable reporting CPU C10 state over ESPI
Change-Id: Ie1a574191da9d677d41f3dab6dce51c714bc26a9
2023-02-22 15:49:12 -07:00
Jeremy Soller
3078f35bff Missing endif
Change-Id: Ib6fa6512540f5bfbc68fea2ff355dc36f7102b8c
2023-02-22 14:32:14 -07:00
Jeremy Soller
b4768db0a7 Use PEG1 for NVIDIA ACPI only on PCH-S
Change-Id: I5ea775dd1f1770bd883bb4138404ea57a7cb6f22
2023-02-22 13:33:54 -07:00
Jeremy Soller
e0bf2e4691 rpl: Switch to S0iX
Change-Id: I2ae9d42d422fec32b9a7431ab44e7c7f4073a5da
2023-02-22 13:33:53 -07:00
Tim Crawford
17baeffcd9 mb/system76/rpl: gaze18: Fix DGPU_GC6 define
Change-Id: I7f622dd65f9d4d40cd64d2b470850d4bc12fe807
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 13:04:51 -07:00
Jeremy Soller
ca0d8b9d20 serw13: Add NVIDIA driver to device tree
Change-Id: I5464c174c0c3a0d9c62f601d26c38ad717479b28
2023-02-22 12:52:58 -07:00
Jeremy Soller
b1207772fb oryp11: Add NVIDIA driver to device tree
Change-Id: If8d5a36b0626eed70206bdd794a2d4dafe509551
2023-02-22 12:52:47 -07:00
Jeremy Soller
2c975776d9 gaze18: Add NVIDIA driver to device tree
Change-Id: If2252e1a38b84544cbbececbb9592cf017d35acf
2023-02-22 12:52:32 -07:00
Jeremy Soller
d6b75b94c5 addw3: Add NVIDIA driver to device tree
Change-Id: Ie7a284ae92e1e0ba73a2273a730e88921ee2d2c9
2023-02-22 12:51:59 -07:00
Jeremy Soller
85a606a538 oryp10: Add NVIDIA driver to device tree
Change-Id: Ife9863cc554b8fab945ab1975ed6c06b005e7e6c
2023-02-22 12:51:39 -07:00
Jeremy Soller
bf0be396f3 oryp11: Add GPIO group comments
Change-Id: Icb2d4eb6b286c79872ec2c1936d34538a35bb2ee
2023-02-22 12:41:16 -07:00
Jeremy Soller
08074e46a5 gaze18: Fix bootblock DGPU_RST#_PCH setting
Change-Id: I42b2a89ea4d835914acc038ad0e02d94e1bffeab
2023-02-22 12:41:02 -07:00
Jeremy Soller
01d7fc7c1d gaze18 and oryp11: Fix CPU root port definitions
Change-Id: I1d1834786b08f2b8ba00642477dd26d9d1201e0f
2023-02-22 12:40:46 -07:00
Jeremy Soller
46ef7b3b19 oryp11: Fix DGPU GPIOs
Change-Id: Ibcac2cc95fd15b6d34f90804730ae0aab461ebef
2023-02-22 12:32:20 -07:00
Tim Crawford
e319f594fc soc/intel/alderlake: Hook up ucode for RPL-P/H/U
Hook up microcode from 3rdparty repo for:

- 06-ba-02 (CPUID signature: 0xb06a2)

Change-Id: I2ae315ed6e24a8d640f60af352928ebd091db3ab
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 12:17:04 -07:00
Tim Crawford
4acddb41cf Update intel-microcode to 2023-02-14 release
Update the submodule to 2be47edc99ee.

This release contains the ucode for RPL-P/H/U.

Change-Id: I8497557e9362749a6a89f07f2515201c625e5d1d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-22 12:16:20 -07:00
Jeremy Soller
305577aebe Fix leftover addp3 identifiers
Change-Id: I64bedcfeac06377454d42fb79325bb6e256da6ba
2023-02-22 08:16:40 -07:00
Jeremy Soller
d5f1eef200 Update kconfigs to match renamed boards
Change-Id: Ia9334a27b4e03783152b6a228faca0cb0c166594
2023-02-22 08:04:27 -07:00
Jeremy Soller
3cd2a6acb7 Move gaze18-3050 variant to gaze18
Change-Id: I7cff4e39699e66284d0fa75e4c9d3029367c6cbd
2023-02-22 08:01:00 -07:00
Jeremy Soller
0015839d31 Move gaze18-40x0 variant to addw3
Change-Id: Ie4fbe445b275723a38164cb3624f5119ba500cb7
2023-02-22 08:00:43 -07:00
Jeremy Soller
88eb602d56 Move addp3 variant to oryp11
Change-Id: Ic805522570a45834dabd7f8b3162b5657f690dc8
2023-02-22 08:00:26 -07:00
Jeremy Soller
2c46f6d0cf Move oryp11 variant to serw13
Change-Id: I8d8301cbfb7abdd1dee57bc1a657c156cf55e271
2023-02-22 08:00:13 -07:00
Jeremy Soller
5eb848d959 mainboard/system76/rpl: Add kconfig for ADDP3
Change-Id: I3eb2574e3f26f9a4ed68c128ac23b94be17f8c1c
2023-02-21 20:08:49 -07:00
Jeremy Soller
4b321d278e mb/system76/rpl: addp3: Add board
Change-Id: Ic641698af43ee81314a1e492ecdaf4752dfcbdd3
2023-02-21 15:43:30 -07:00
Tim Crawford
0689097632 mb/system76/rpl: gaze18-3050: Add USB and PCIe RP configs
Change-Id: Ic9863d3aa8129e7081f36bc302cfa8ca68140eae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-21 08:15:28 -07:00
Tim Crawford
6529e3d712 mb/system76/rpl: gaze18-3050: Document GPIOs
Change-Id: I5a74d0d8bf752d081975cd26ddf9d5b749c0ae9b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-20 11:46:16 -07:00
Jeremy Soller
e0bda81015 gaze18-40x0: Leave CNVi clkreq configured by FSP and configure reset
Change-Id: Ic7e2f5c0b806474c17029fae5a39f415a51101b9
2023-02-15 16:18:37 -07:00
Tim Crawford
1ba9380a21 mb/system76/rpl: oryp11: Configure CNVi reset
It seems to be sufficient to just take the device out of reset, so
configure it in coreboot instead of FSP.

Change-Id: I408229072ba7eb169c3ba6693f95f5b32fca10e1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-15 15:44:27 -07:00
Tim Crawford
a98f4ead4c mb/system76/rpl: oryp11: Fix CNVi
According to the schematics:

- PCH_LAN_WAKE# is not connected
- M.2_BT_PCMIN is not connected

Addtionally, leave both CLKREQ and RST# for CNVi as FSP configured.

Change-Id: I6f249ca778ad741469475b02163a2eee2e7626de
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-15 15:24:39 -07:00
Tim Crawford
6f02b2f73f mb/system76/rpl: oryp11: Fix USB port configs
Change-Id: Icc026451ac9ac5ff9def64096629d86beca4ec3c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 16:10:28 -07:00
Tim Crawford
45ca4334b5 mb/system76/rpl: oryp11: Leave CLKREQ as FSP configured
Change-Id: If19f463ad63b74cbbafa4fdd31815697f608f0ed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 16:09:52 -07:00
Jeremy Soller
b87e2021ad gaze18-40x0: document GPIOs
Change-Id: Ib1f3c1cdbe20dd759fd5c57105ba2640ec2b038b
2023-02-13 14:52:36 -07:00
Tim Crawford
23dd117ccf soc/intel/adl: Fix PL1 name for RPL-HX
Change-Id: I9ccb589338bd2e185186987f77b1eab62cdad2c1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-13 10:06:11 -07:00
Tim Crawford
654a08acd4 oryp11: dGPU port and TP GPIO
Change-Id: Ie3f9edbf5cb9fcaba3c50e949afb55f990cd846d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-10 13:44:00 -07:00
Jeremy Soller
dbf7480795 rpl: fix NVIDIA ACPI scope
Change-Id: Iccc78c15ef115a56fd071a7b891310026ed16501
2023-02-10 12:56:27 -07:00
Jeremy Soller
71f18f129f gaze18-40x0: enable NVIDIA GPU
Change-Id: Iefb6de5bdc481934d7c661516c05ee945e8717db
2023-02-10 12:43:57 -07:00
Jeremy Soller
d30cad4127 Add more RPP-S PCI ID definitions
Change-Id: I3682701a169dd51b1e55227b4e089310bcf42a0f
2023-02-10 12:05:25 -07:00
Jeremy Soller
74e0453ef2 Add RPP-S PCI root port definitions
Change-Id: I6ec9757b0402299be9c96fc0019890068f2f5e43
2023-02-10 11:59:51 -07:00
Jeremy Soller
d70be6d118 Add RPP-S PCI ID definitions
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
2023-02-10 11:57:04 -07:00
Jeremy Soller
5da590435a gaze18-40x0: Set touchpad interrupt GPIO
Change-Id: I88c2be3948ca38b3ace04c7b45d989e696405be5
2023-02-10 11:12:11 -07:00
Jeremy Soller
e1506c52bb rpl: touchpad irq on GPP_E7
Change-Id: I8a7072591d04ce73bd8861bfcd20ae2ef4460498
2023-02-10 10:47:10 -07:00
Jeremy Soller
c54358d8fc gaze18-40x0: fill in overridetree
Change-Id: Ie411e9f103b07b079681a73cef11f44cd58f0976
2023-02-10 09:39:08 -07:00
Tim Crawford
c918d36889 [WIP] soc/intel/adl: Add RPL-HX support
Change-Id: I62efdd8bea7cc5134621f4602d2b2523651076da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 16:25:42 -07:00
Tim Crawford
e707f1efc3 [WIP] soc/intel/adl: Add RPL-HX support
Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.5)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 14:28:22 -07:00
Tim Crawford
2e0291e7c3 oryp11: Set dq_pins_interleaved
Change-Id: I094e86b39df9cedcb2813a88785ef907b9bf2308
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 11:25:23 -07:00
Tim Crawford
4c9edaa4d0 oryp11: Fix TBT RP
Change-Id: I18f04fcfab73ae1144dc9f1625a55af0b708ba36
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 09:16:21 -07:00
Tim Crawford
af1241f3a8 mb/system76/rpl: oryp11: Add USB and PCIe RP configs
Change-Id: Ibe15461b58a5d133456779e7e28c8bd1db7ee320
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 09:12:33 -07:00
Tim Crawford
da67e5e8a3 mb/system76/rpl: Use S3 instead of S0ix
Change-Id: Ib161c3eb6cf5af815e2ab53f38b5f7786b2e1949
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-09 08:44:16 -07:00
Tim Crawford
2cd15a2f72 mb/system76/rpl: Add oryp11 smart amp extract
Extract the configuration block from the proprietary firmware module
PlatformInitAdvancedPostMem.

The proprietary firmware does not use a multiple of 4 for the smart amp
data like coreboot expects, so duplicate the last 2 dwords.

Change-Id: I563a92b87ebf7672963a03a15166aed194fc57fe
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 14:11:12 -07:00
Tim Crawford
ae0d0f6d26 mb/system76/rpl: Drop unneeded rcomp value
Change-Id: I7901e3a38fd8b03aad4cd0534c4646beaa13b521
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 10:48:45 -07:00
Tim Crawford
7689625cf0 soc/intel/alderlake: Hook up ucode for RPL-HX
Hook up microcode from 3rdparty repo for:

- 06-b7-01 (CPUID signature: 0xb0671)

Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 08:50:01 -07:00
Tim Crawford
1e3e8494f7 Set MAX_CPUS in SoC Kconfig
Change-Id: Ia7c0504d6d15931d2f0cfba92f0f8b700c91e37d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-08 08:48:08 -07:00
Jeremy Soller
ca1c4bd7e7 Set MAX_CPUs for RPL-HX boards to 32
Change-Id: Ic10220124e2b32c7a1d674150687d27b94770873
2023-02-08 08:21:07 -07:00
Jeremy Soller
b787eb1e16 Use interleaved DQ for gaze18-40x0, remove rcomp resistor setting
Change-Id: I9e527774c0ea08c7079c9722fa91f3876d23475e
2023-02-08 08:15:03 -07:00
Jeremy Soller
17db22596e Move RPL models to new folder
Change-Id: If343c3d1c45ea88cef5e1b8912d929b1e8793b2c
2023-02-07 14:33:25 -07:00
Jeremy Soller
fa2aa1d2a4 Select ADL-S PCH for some new RPL models
Change-Id: I6c3193c30f694ae1150ef1fba715c4eafc0a60b3
2023-02-07 14:22:44 -07:00
Jeremy Soller
ac4c79fe67 Add gaze18-40x0
Change-Id: I5a7a00dd197de3d4dc4e18b16c327e8a9bc0065d
2023-02-07 14:02:59 -07:00
Tim Crawford
f385486beb mb/system76/adl: Add Oryx Pro 11 as a variant
Change-Id: Ib9cf93dc88cd51d429222540ce0721c6e5f4013a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-07 11:40:49 -07:00
Tim Crawford
d2fc079b71 mb/system76/adl: Add Gazelle 18 (3050) as a variant
There will be two versions of firmware for the Gazelle 18:

- One for units using NVIDIA RTX 3050
- One for units using NVIDIA RTX 40x0

Change-Id: I7c1a51fda012fe4e7a43bbe5ef98a3aec38373a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 11:06:51 -07:00
Tim Crawford
bfb21044f4 mb/system76/adl: oryp10: Enable dGPU
I forgot this when performing the rebase.

Change-Id: I855968469ed339bdf2a5a40d5d91878a262ce954
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 11:04:42 -07:00
Tim Crawford
29632b4b9d mb/system76/adl: Restructure board configs
Use a common block for all ADL/RPL boards.

Change-Id: I0ac73751c37a116b205f200c42b814182ca32bde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 10:54:03 -07:00
Tim Crawford
c5a2f794ad mb/system76: Rename adl-p to adl
The directory hold boards other than ADL-P, such as ADL-U and ADL-H, and
will also contain the RPL boards.

Change-Id: I1b42246bcf1eaed9de51f59021209e9eb836df15
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-02-06 10:53:53 -07:00
Tim Crawford
40e8d68d3b soc/intel/alderlake: Fix IRQ for PEG0, PEG1
Fixes the following warnings on Linux:

    pcieport 0000:00:06.0: can't derive routing for PCI INT D
    pcieport 0000:00:06.2: can't derive routing for PCI INT B

Change-Id: I49406e0db77cf2391972f6660729bd0a41a34f13
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:16 -07:00
Tim Crawford
c6ef149a55 mb/system76: Enable dGPUs
Change-Id: Ia0d6c952541cbd09d14e82336e6dc6d7d7d18b44
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
3f278aa9fc mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
0f67cd9bd5 mb/system76/tgl-h: Disable D3cold for TCSS
The TGL-H boards use S3 instead of S0ix.

Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Jeremy Soller
e927aff3d7 mb/system76: select TPM_RDRESP_NEED_DELAY
Change-Id: I7909b05e9203ce9ad07c8e87a847bc46cf281b34
2023-01-23 10:55:15 -07:00
Jeremy Soller
6b23f22d59 mb/system76/addw1: Disable SaOcSupport to eliminate hangs with 3200MT/s memory
Change-Id: I586e8cf97a52b2fa8386ce3742a4f4ae9465bbcf
2023-01-23 10:55:15 -07:00
Tim Crawford
779872ff4d mb/system76: Add custom backlight levels for Intel GMA
Add custom backlight levels for all models except:

- addw1
- bonw14: Does not use the iGPU

Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Jeremy Soller
8414aa8f14 drivers/gfx/nvidia: Add driver for NVIDIA GPU
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, and a function for enabling the GPU power in romstage.

Tested on system76/gaze15.

References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:15 -07:00
Tim Crawford
5fd3a476f7 soc/intel/alderlake: Add IRQ for non-existent CPU PCIe device
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.

Fixes the following error in Linux:

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10

Which in turn resolves the conflict with the PCH HDA device...again:

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
ff79195b49 soc/intel/alderlake: Use channel 0 for memory-down
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the
System76 Lemur Pro 11 (lemp11).

Change-Id: I216b7b67c2674e0a14fdbbf96776759e55d0ec09
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Jeremy Soller
ecfc4d9e81 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
2023-01-23 10:55:14 -07:00
Jeremy Soller
b60f563ef2 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-01-23 10:55:14 -07:00
Jeremy Soller
95e709f64e mb/system76/gaze17: Add Gazelle 17
The gaze17 comes in 2 variants due to differences in the discrete GPU
and network controller used.

- NVIDIA RTX 3050, using Realtek Ethernet Controller
- NVIDIA RTX 3060, using onboard I219-V Ethernet Controller

Tested with a custom TianoCore UefiPayloadPkg payload.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting to Pop!_OS Linux 22.04 with kernel 5.18.10
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics: Requires NVIDIA driver
- mDP/HDMI displays on 3060 variant: Requires NVIDIA driver
- Detection of devices in TBT slot on boot
- S3 suspend: MP init eventually fails

Not tested:

- Thunderbolt devices

Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
981f234f17 mb/system76/adl-p: Add Oryx Pro 10 as a variant
oryp10 is nearly identical to the oryp9, with the differences being:

- Uses DDR5 RAM instead of DDR4 RAM
- Uses Realtek ALC1306 instead of TI TAS5825M
- Has an option for OLED display

Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
ab542a2461 mb/system76/adl-p: Add Oryx Pro 9 as a variant
The Oryx Pro 9 (oryp9) is an Alder Lake-P board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- Both M.2 NVME SSD slots (with MZVL2500HCJQ)
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics
- HDMI output (requires NVIDIA GPU)
- Mini DisplayPort output (requires NVIDIA GPU)
- Detection of devices in TBT slot on boot

Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:14 -07:00
Tim Crawford
32ba9ac585 mb/system76/adl-p: Add Lemur Pro 11 as a variant
The Lemur Pro 11 (lemp11) is an Alder Lake-U board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- DIMM slot (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- M.2 SATA SSD (with WDS100T2B0B)
- All USB ports
- SD card reader
- Webcam
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headset + mic 3.5mm audio
- Booting Pop!_OS Linux 22.04 with kernel 5.18.5
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- On-board RAM: Requires CB:65567
- Detection of devices in TBT slot on boot
- S0ix suspend/resume

Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:13 -07:00
Tim Crawford
ab052d2b54 mb/system76/tgl-u: Leave TBT LSX0 as FSP configured
Do not reconfigured LSX0 so that the FSP values are used.

Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-01-23 10:55:13 -07:00
Tim Crawford
2212d28b56 submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2023-01-23 10:55:13 -07:00
Matt DeVillier
decbf7b4d9 soc/intel/{adl,mtl,tgl}: change selection for DEFAULT_SOFTWARE_CONNECTION_MANAGER
Needs to be selected for ChromeOS mainboards even for non-ChromeOS
builds, else Thunderbolt/USB4 doesn't work under Windows (and likely
Linux as well).

TEST=build/boot Windows on drobit/banshee, verify TB functional

Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22 00:37:42 +00:00
Bora Guvendik
adb52533fc intel/common/block: Fix potential buffer overflow
Possible Buffer Overflow - Array Index Out of Bounds. Array
regions size is 256 but 'i' iterates from 0 to 256.

Found-by: Klockwork
BUG=None
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22 00:36:49 +00:00
Felix Held
5e2d9c0979 soc/amd/stoneyridge: clean up global NVS
Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22 00:35:33 +00:00
Felix Held
4a5f2e9e96 soc/amd/picasso: clean up global NVS
Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22 00:35:17 +00:00
Anil Kumar
a98d7a9ed1 Revert "mb/google/brya: Add EC mux device to brya0"
This reverts commit 197d550d06.

Reason for revert: breaks TBT and TypeC display on Brya0

Bug=265375098
Branch=firmware-brya-14505.B
Test=Build and boot Skolas board with Brya0 image. Test TBT
and TypeC display functionality.

Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081
Reviewed-by: Prashant Malani <pmalani@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22 00:34:34 +00:00
Subrata Banik
84d812cafe soc/intel/apollolake: Add PMC macros for common code usage
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the APL EDS vol 1 (doc 569262) to be able to implement common
code API to clear the power failure status bits.

Note: as per the EDS those newly added power management failure bits
are RO and shouldn't change any functionality of the existing APL SoC
code. The reason behind adding those macro definitions is to fix the
compilation issue due to code change targeted for the Intel SKL and
Xeon-SP.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22 00:32:39 +00:00
Subrata Banik
6d03f8986d soc/intel/denverton_ns: Add PMC macros for common code usage
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the DNV EDS vol (doc 558579) to be able to implement common
code API to clear the power failure status bits.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-22 00:31:24 +00:00
Jan Samek
256918bd6d mb/siemens/mc_apl1/var/mc_apl6: Enable early POST
Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.

BUG=none
TEST=Boot on mc_apl6 and observe that POST codes are
displayed before DRAM training.

Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-22 00:30:01 +00:00
Jan Samek
9d67142ccb mb/siemens/mc_apl1: Move POST logic to mainboard level
Move logic previously used only in the mc_apl2 variant to
the mainboard level so that other variants can also make
use of it without code duplication.

This functionality on the mc_apl6 variant will be enabled
in a follow-up patch.

BUG=none
TEST=Boot on siemens/mc_apl2 and observe that the POST
codes are displayed before DRAM training.

Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-22 00:29:36 +00:00
Elyes Haouas
105d3091f9 nb/amd/pi/Kconfig: Remove unused CONSOLE_VGA_MULTI
Change-Id: I93455f38663cf29d8b5160ac21c94db08eb44fa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21 09:14:02 +00:00
Elyes Haouas
5a5852f7ab sb/amd/pi/hudson/Kconfig: Remove unused AZ_PIN
Change-Id: I1542c5662162e919752c334baa9c31cddc5036af
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21 09:13:48 +00:00
Elyes Haouas
48fa6dd8f9 arch/x86/Kconfig: Remove unused NUM_IPI_STARTS
Change-Id: I3b781c42ef6c23a5dcd31215c14fb9d7104822f2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21 09:13:28 +00:00
Elyes Haouas
91a48367a4 arch/x86/include: Remove unused <stddef.h>
Change-Id: I2a4b00d06c92eea1b83002c69d93037f84592393
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72111
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21 09:12:36 +00:00
Elyes Haouas
cdede5dbaf sb/amd/pi/hudson/Kconfig: Remove AHCI_ROM_FILE
Remove AHCI_ROM_FILE since it's not used and there is no ahci.bin file.

Change-Id: I008c6ac78957500d4ce301fe70f5b6d4a549b573
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-21 09:12:06 +00:00
Elyes Haouas
09b8babefe soc/intel/baytrail: Fix indentation for the PMC (pm.h) macros
This patch fixes the alignment of the PMC macros defined in the
pm.h file.

Change-Id: Ib5ff87e2f6524ca1be69027080149a3fbe2df7d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72158
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21 09:10:51 +00:00
Elyes Haouas
894079ece8 soc/intel/braswell: Fix indentation for the PMC (pm.h) macros
This patch fixes the alignment of the PMC macros defined in the
pm.h file.

Change-Id: I9a55e1b099a53180e40eedcc52120d65558e7f8b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72157
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21 09:10:43 +00:00
Subrata Banik
89faeca93d soc/intel/apollolake: Fix indentation for the PMC (pm.h) macros
This patch fixes the alignment of the PMC macros defined in the
pm.h file.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8d35a5d104658b7900fde7f7b8c6f88530a614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72129
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-21 03:19:05 +00:00
Tarun Tuli
b81ad9c6b1 mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS
1) Update location of TGP (MAGA) to Params2[15:0]
2) Add TPPA (value of 25W)

Package:

...
Case (0x02)
{
      Local0 = Buffer (0x31)
      {
            0x22, 0x05, 0x10, 0x1C, 0x01
      }
      CreateWordField (Local0, 0x1D, MAGA)
      CreateWordField (Local0, 0x19, TPPA)
      CreateDWordField (Local0, 0x15, CEO0)
      MAGA = 0x50
      TPPA = 0xC8
      CEO0 = 0x0200
      Return (Local0)
}
...

BUG=b:214581372
TEST=build and verify DSDT on device

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 23:55:33 +00:00
Rex Chou
a16da93680 mb/google/skyrim/var/frostflow: Update I2C setting for touchpad
Update setting for touchpad I2C frequency and hold time to meet touchpad
i2c SPEC.
- Frequency: 380 ~ 400 kHz
- hold time : 0.3 ~ 0.9 us

BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 393.7 kHz
Hold time = 0.604 us

Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 23:16:02 +00:00
Felix Held
0e9dbf0843 soc/amd/glinda,mendocino,phoenix/espi_util: add comment about register
Even though the register name begins with ESPI, it resides in the SPI
registers and not in the eSPI registers, so add a comment to point this
out to hopefully avoid some confusion.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20 22:23:50 +00:00
Felix Held
b85fd1e84f soc/amd/glinda/espi_util: update file to match documentation
Checked against document #57396 revision 1.52 and removed the
DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-20 22:22:55 +00:00
Felix Held
d7130cb1cf soc/amd/phoenix/espi_util: remove TODO after checking
Checked against both documents #57019 revision 1.59 and #57396 revision
1.50 that the definitions and the code still apply to Phoenix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id65301ec730793f41044696f2e99356f2e899137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-20 22:11:52 +00:00
Felix Held
3b74bad537 soc/amd/glinda: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1c3c25591deadb27b7bf38a81dcd6fe746de55b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72096
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 17:41:18 +00:00
Felix Held
7fd67947a3 soc/amd/phoenix: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 17:40:57 +00:00
Felix Held
98391baf3b soc/amd/mendocino: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 17:40:38 +00:00
Felix Held
b2394e853b soc/amd/cezanne: clean up global NVS
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 17:40:29 +00:00
Felix Held
703778cb83 soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checking
All field definitions in the IndexField object match both the info in
the PPR #57243 revision 3.02 and also match the defines in soc/amd/
mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines
the subset of the IRQ mapping registers that are used or likely needed
in the future. This is handled in the same way for the other AMD SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 16:51:20 +00:00
Elyes Haouas
18d8fe27b2 soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" comment
Change-Id: If44a07503470f57037b59d03eea830703a3c604a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 16:11:44 +00:00
Jan Samek
6ea58346c6 mb/siemens: Unify and clean lcd_panel.c coding style
With the addition of the mc_ehl3 board variant, a few
points about commenting the code arose either from the
review or during the implementation itself.

This patch unifies structure of these files, which
have a similar structure across more Siemens boards
utilizing the PTN3460 eDP-to-LVDS bridge.

BUG=none
TEST=Check that images for the affected boards can be
built.

Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 16:11:00 +00:00
Jan Samek
d6244534de mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridge
This board contains in addition to its base variant, mc_ehl2,
an LCD panel driven through the PTN3460 eDP-to-LVDS bridge.

This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c, based upon a similar implementation in siemens/mc_apl7.

BUG=none
TEST=Boot with the LCD panel attached and observe whether
the picture is stable and free of artifacts coming from wrong
resolution, timing etc.

Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-20 16:10:11 +00:00
Mike Shih
c5625c53c4 mb/google/brya/var/gaelin: Add touch panel module setting
1. Enable multiple GPIOs to support the touch panel.
2. Add I2C setting for touch panel.

BUG=b:260818082, b:264812909
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot

Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f
Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-01-20 16:08:48 +00:00
Fred Reitberger
eb8ee59f87 soc/amd/mendocino: Remove TODO after review
Remove TODO comment after reviewing against mendocino ppr #57243, rev
3.00

BUG=b:263563246

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9a89751df71eb32b2c8d99c568341dd669b5f065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72073
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 15:56:26 +00:00
Elyes Haouas
244a3655e1 soc/intel: Remove unused <stddef.h>
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20 05:41:21 +00:00
Elyes Haouas
1a0a280cff drivers/intel/gma/hires_fb/gma-gfx_init.adb: Remove spaces before tabs
Change-Id: Ifab3fcd2de8f0c1672d1a9a21c8e0c5dba5b7443
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72077
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20 05:36:39 +00:00
Elyes Haouas
0dc1a005d8 soc/intel/common/block/fast_spi/Makefile.inc: Remove spaces before tabs
Change-Id: Id2b408e24f74367777b1b949623d6692f2f19e6d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20 05:35:57 +00:00
Elyes Haouas
39108a73cd mb/intel/adlrvp/spd/Makefile.inc: Remove spaces before tabs
Change-Id: I7bd29bab2c77da2ffe86167d54e87c9941355ea7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20 05:35:02 +00:00
Elyes Haouas
c9f8380638 drivers/intel/gma/text_fb/gma-gfx_init.adb: Remove spaces before tabs
Change-Id: I421602c81d9a186eb36a289d6e5048b5aa343a2d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20 05:34:41 +00:00
Jan Samek
2a959be092 mb/siemens/mc_ehl3: Use device/mmio.h instead of device/pci_ops.h
The {read,write}{16,32}() functions used in this file come from the
mmio.h header, so include it directly.

BUG=none
TEST=Read out the SD card controller (device 1a.1) PCI registers
in Linux and check whether the values reflect the ones defined
in this file.

Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-19 16:33:21 +00:00
Felix Held
9abc411c89 soc/amd/stoneyridge/northbridge: use acpi_align_current
Use acpi_align_current to align the ACPI tables on a 16 byte boundary.
This changes the alignment of the HEST, IVRS, SRAT and SLIT tables from
8 bytes to 16 bytes. The alignment of the ALIB and PSTATE SSDT tables
was already 16 bytes before, so the alignment of those isn't changed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8933e3731b67012bcae0773db2f7f8de7cd31b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72055
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19 15:19:48 +00:00
Kapil Porwal
e988cc20b6 intel/meteorlake: remove skip_mbp_hob SOC chip config
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to
control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.

This new option is hooked with `SkipMbpHob` UPD and is always
disabled for ChromeOS platforms.

This made skip_mbp_hob SOC chip config variable redundant
which is also removed as part of this change.

BUG=none
TEST=Build and boot to Google/Rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19 09:48:44 +00:00
Kapil Porwal
b10a4bf002 soc/intel/meteorlake: Increase cbmem buffer size for the debug image
Currently most of the FSP debug messages (when enabled) are truncated
due to insufficient size of cbmem buffer.

Increase premem cbmem console size to 0x16000 bytes and cbmem buffer
size to 0x100000 bytes so that cbmem buffer can contain most of the
debug logs when FSP debug messages are enabled.

BUG=b:265683565
TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled
but MRC debug message.

Note: Still 350/2200 lines of premem messages are missing.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I120423e1dd2bc468cf9cec6da1246ac3c0a155e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19 09:48:10 +00:00
Kapil Porwal
1eb4425203 soc/intel/meteorlake: Increase cbmem buffer size to 256KB
Current size of the cbmem buffer (128KB) is insufficient to contain the
complete debug logs which is more than 166KB hence, cbmem console buffer has wound off to contain the maximum possible debug messages within the allocated buffer as results, we are seeing truncated debug message while looking into the cbmem console.

This patch increases cbmem buffer size to 256KB so that the complete
debug log can be stored in it.

BUG=b:265683565
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ibeabb61d60491b831252b7161c9d3181fbe09e73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72047
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19 09:47:55 +00:00
Frank Wu
febcc020fd mb/google/skyrim/var/frostflow: set dxio_tx_vboost_enable
Turn on the dxio_tx_vboost_enable for frostflow in coreboot.

It needs to confirm the PCIe Signal Integrity after enabled.

BUG=b:259007881, b:248221908
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19 06:06:59 +00:00
Kane Chen
56e448b8d5 drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
This patch supports projects to use _DSM to control USB3 U1/U2
transition per port.

More details can be found in
https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-

The ACPI and USB driver of linux kernel need corresponding functions
to support this feature. Please see
https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm

BUG=b:253402457
TEST=tested on felwinter and found _DSM method is created.

Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19 05:58:33 +00:00
Sen Chu
56d8313925 soc/mediatek/mt8188: Allow SSPM to access PWRAP interface
Allow SSPM to access PWRAP interface.

BUG=b:254566089
TEST=build pass and boot to OS.

Change-Id: I4b134983dcde1cc293f4b798f91b997baf96d299
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-01-19 05:49:37 +00:00
Felix Singer
ad6e3c847f tree: Drop Intel Ice Lake support
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.

As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.

This affects the following components and their related code:

  * Intel Ice Lake SoC
  * Intel Ice Lake CRB mainboard
  * Documentation

Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19 01:26:36 +00:00
Frank Wu
89a269af9d mb/google/skyrim/var/markarth: set dxio_tx_vboost_enable
Turn on the dxio_tx_vboost_enable for markarth in coreboot.

It needs to confirm the PCIe Signal Integrity after enabled.

BUG=b:263534907, b:263216451
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
2023-01-19 00:22:03 +00:00
Jan Samek
16d6d66094 mb/siemens/mc_ehl: Remove '_' from mc_ehl3 part number
Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3
from "MC_EHL3" to "MC EHL3".

Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 22:08:55 +00:00
Paul Menzel
e88bf30d12 vc/siemens/hwilib: Use 3rd person singular in comment
Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-18 22:07:07 +00:00
Werner Zeh
fcff39f0ea vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'
The parameter 'maxlen' can be a bit confusing as it actually is
referring to the size of the destination memory block where the
requested parameter is stored to. Rename it to 'dstsize' and change
the type to size_t to be more clear here.

In addition, add a comment line for this parameter in the description
of the function 'hwilib_get_field()'.

This patch has no impact to the generated binary (checked with timeless
build).

Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-01-18 22:06:35 +00:00
Martin Roth
610be7018b Documentation: Update list of boards supported by vboot
This is the list generated by util/vboot_list/vboot_list.sh

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib782a676fed312a2c84e89914f871984a289f610
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72003
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 22:05:51 +00:00
Frank Chu
21a7b6c279 mb/google/brya/var/marasov: Remove wlan RTD3 support
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L.
Remove unused RTD3 driver.

BUG=b:263448873
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 22:05:11 +00:00
Martin Roth
411b4fc9f2 mb/google/skyrim: Add custom amdfw.cfg file to remove fwTPM
Skyrim doesn't use the firmware TPM, so remove the binary from the
image.

Note that because this was not used, removing it doesn't change the boot
time.

BUG=None
TEST=Boot

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 22:04:21 +00:00
Werner Zeh
9a8e119110 vc/siemens/hwilib: Fix coding style
As per the code style there is no space before the opening brace of a
function declaration. Delete the space in hwilib.c and hwilib.h.

Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 22:03:01 +00:00
Felix Held
2b01e97c6f soc/amd/common/block/acpi/cppc: drop outdated comment
Since commit d5ab24cd48 ("soc/amd/common/acpi/cppc: add nominal and
minimum frequencies") the fields that got added in CPPC version 3 get
populated, so remove the now outdated comment about the fields added in
version 3 always being set to CPPC_UNSUPPORTED.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4c975b42fc4f67329170801b871d6bbdf9637d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-18 18:43:28 +00:00
Tarun Tuli
ec8eb4947f soc/intel/alderlake: Add print that MRC training screen displayed
Add a INFO print indicating that we did infact attempt to display the
MRC training message to the user.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Print seen in cbmem -c

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I1a20fb221aa2fa0eeaf9b7f8cf3d8a8ab0b91133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-01-18 17:50:01 +00:00
Felix Held
5c56b16533 soc/amd/*/agesa_acpi: add TODO for adding CRAT table
The Picasso SoC code generates a CRAT ACPI table which is not done for
Cezanne and newer. A significant part of the Picasso CRAT generation
code can likely be moved to the common AMD SoC code and then used in all
SoCs, but this still needs to be checked.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 14:06:30 +00:00
Felix Held
4235fb6015 soc/amd/glinda/agesa_acpi: use acpi_align_current to align IVRS & ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I965791fbbe499702e191dcbf1f5fbfcb5e1bab6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:06:10 +00:00
Felix Held
192945e61c soc/amd/phoenix/agesa_acpi: use acpi_align_current to align IVRS & ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I766260aefcac6876609d6b45202b41a3e9e44385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:05:58 +00:00
Felix Held
19f4c39cfe soc/amd/mendocino/agesa_acpi: use acpi_align_current to align IVRS&ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b48a7cbed84551e7651992589c38eac54f27d1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:05:25 +00:00
Felix Held
68143e88a8 soc/amd/cezanne/agesa_acpi: use acpi_align_current to align IVRS & ALIB
This changes the alignment of the IVRS table from 8 bytes to 16 bytes
and aligns the ALIB table to a 16 byte boundary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4de66ab11508814da5d7fb440a1083a52551bcf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:05:00 +00:00
Felix Held
8f1e004107 soc/amd/picasso/agesa_acpi: align ALIB with acpi_align_current
This makes sure that the ALIB table is aligned on a 16 byte boundary.

TEST=Mandolin still boots Linux and the position and size of the ACPI
tables in memory shown by dmesg hasn't changed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90781ef98b729c0a8d1f5dde46fc9ca5d08618b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:04:17 +00:00
Felix Held
f03706a2ba soc/amd/picasso/agesa_acpi: use acpi_align_current to align CRAT & IVRS
This changes the alignment of the CRAT and IVRS tables from 8 bytes to
16 bytes.

TEST=Mandolin still boots Linux and the position and size of the ACPI
tables in memory shown by dmesg hasn't changed.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88df331c8410d8dca41a414543f051f5e4656ff1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 14:04:10 +00:00
Subrata Banik
ea0c91fdc9 soc/intel/elkhartlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0


Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib43d3402f94f47dc576fb99a6b2a7acf6f0af220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71982
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 11:51:37 +00:00
Subrata Banik
ffa5ff8470 soc/intel/icelake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/dragonegg.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0e5a6e54abc7c03a2fbffa308db20c392e2a600b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71983
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 11:51:07 +00:00
Subrata Banik
a5a357ca10 soc/intel/jasperlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/dedede.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id2c1f24a8fa54eea512b5bd3dd91423f9892687d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71984
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18 11:50:50 +00:00
Subrata Banik
ecf7db873c soc/intel/tigerlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/volteer.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0e48b110826f16d13d18c138fce03a56c85b9d1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71985
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-18 11:50:23 +00:00
Subrata Banik
55546699f1 soc/intel/alderlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/taeko.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I52f9c261f4eea34e6d2300c8de97ee018d886189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71987
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 11:50:11 +00:00
Subrata Banik
b03d6f15b4 soc/intel/meteorlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/rex.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idc40045445cccc5b34fb49901d9ef548f2f0560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71986
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 11:49:59 +00:00
Subrata Banik
6d64155cc8 soc/intel/cannonlake: Fix incorrect prev_sleep_state issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).

As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.

TEST=Able to build and boot google/hatch.

Without this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 5

With this patch:

Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.

    pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
    GEN_PMCON: d1215238 00002200
    ....
    prev_sleep_state 0

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I05a2fab75c3d931651885db0003ab8c5748a1568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71934
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 08:41:48 +00:00
Dinesh Gehlot
a464af451e soc/intel/elkhartlake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I73bac9560d0ff315d6fe6f4efc3ee9011f77c660
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72036
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 05:20:01 +00:00
Dinesh Gehlot
58cc96f0ca soc/intel/apollolake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Iccf37a340880e4b5a18f51c3add9a15a74e1d7b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72030
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 05:19:52 +00:00
Dinesh Gehlot
ba09eb71c8 soc/intel/braswell: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I55fa5941a9255f60c2aa23b90d16cf342d6f458f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72032
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18 05:19:19 +00:00
Dinesh Gehlot
4da8830c3d soc/intel/jasperlake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: If069e66f2762eb373d35d635c09226ac5be99c7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72039
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18 05:19:02 +00:00
Dinesh Gehlot
770a46c6d7 soc/intel/skylake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I02fe236506abbc0d97982747cfcf3c0e9ef4897a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72040
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18 05:18:42 +00:00
Dinesh Gehlot
6fecff20c1 soc/intel/xeon_sp: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I8135dc918cb04c854dc003966b7657806a42bad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72042
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18 05:18:22 +00:00
Dinesh Gehlot
3e866812e9 soc/intel/tigerlake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I12497d46e58aae41ec8dcb5d567267579dc12fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72041
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18 05:18:05 +00:00
Dinesh Gehlot
8a2c904616 soc/intel/cannonlake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.

BUG=b:261778357
TEST=Able to build and boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I349a2b24ecdee347548b5c7b292c5075e6150a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72033
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-18 05:15:59 +00:00
Elyes Haouas
5e2602ae48 soc/amd: Include <gpio.h> instead of <soc/gpio.h>
<gpio.h> chain-include <soc/gpio.h>.

Change-Id: I112e41ad4c7ee638954dfe3f1ddfeb10c138459a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-18 05:13:30 +00:00
Felix Held
8f2e5c90e4 soc/amd: introduce and use common amd_cpu_bus_ops struct
The device operations for the CPU bus are identical for all AMD SoCs, so
introduce a common device operations struct for this and use it in all
AMD SoC's chipset devicetrees as ops for the CPU cluster.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id32f89b8a33db8dbb747b917eeac3009fbae6631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17 19:26:16 +00:00
Subrata Banik
d4cc902c57 soc/intel/meteorlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.

This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.

TEST=Able to build and boot Google/Rex successfully.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 19:25:35 +00:00
Subrata Banik
55812d6430 soc/intel/alderlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.

This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.

TEST=Able to build and boot Google/Marasov successfully.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 19:25:13 +00:00
Martin Roth
b486fe95bf soc/amd: Use fixed EFS location for Phoenix & Glinda
The AMD SoCs no longer have a variable position for EFS - it's now fixed
at 0xff020000 - 128KiB into the 16MiB ROM decode region.

It's a little more complex than that because the chip can be larger than
16MiB, and the entire ROM can be decoded if mapped above the 4GiB
boundary, but we don't currently support doing that in coreboot, so this
is enough for now.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17 16:08:18 +00:00
Evgeny Zinoviev
3f5985972d payloads/*/Kconfig.name: update documentation link
Old wiki is outdated for years but Kconfig help messages
of some payloads still reference it.

This commit changes those links to the corresponding page at
doc.coreboot.org.

Change-Id: I81653f1b010d8a3ac4dfc4c6ad4fa714ce5d59a1
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-17 15:20:24 +00:00
Martin Roth
c29340df3c mb/google/skyrim: Set winterhold SPI fast read speed to 100MHz
Winterhold runs with the SPI fast read speed set to 100MHz.  This
decreases boot time by roughly 100ms.

BUG=None
TEST=Examine boot times.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-17 15:02:21 +00:00
Subrata Banik
7d1995cc68 soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

BUG=b:261800015
Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found'
lists all stages.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6a49f88aff07841d105cd3916086aa9e496654c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71921
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 04:40:51 +00:00
Subrata Banik
f288a7ed82 mb/google/marasov: Skip MBP HOB creation to save boot time
This change skips the MBP HOB creation since coreboot doesn't
use it and also helps to reduce the boot time by ~10msec.

Boot time data:
Before:
*  955:returning from FspSiliconInit    897,278 (33,603)
After:
* 955:returning from FspSiliconInit     864,543 (21,273)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 04:40:34 +00:00
Elyes Haouas
24769421cd treewide: Fix old-style declarations
Replace old style declaration "const static" with "static const".
This to enable "Wold-style-declaration" command option.

Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17 04:23:49 +00:00
Martin Roth
4d661eebe9 Documentation: Add 4.20 release notes template and update index
Also update Month abbreviations to full month names.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I99c1a037c0fc3d0cfec6464956f4263debdfccd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71941
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 04:09:17 +00:00
Martin Roth
23ce296c68 Documentation/releases: Finalize the 4.19 release notes
These are the final 4.19 release notes before tagging the release.

Final updates to statistics and removal of comments saying "planned" and
"Upcoming" will be removed after the release is tagged.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie20ad22732ce2e1d92e47b8e48268c6a5a34ca5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71942
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17 04:08:33 +00:00
Sean Rhodes
38483e5e94 mb/starlabs/starbook/adl: Fix alignment
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-17 01:12:25 +00:00
Felix Held
8c41000862 soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definition
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file
and use this definition in the mainboard code, so port this back to
Picasso.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-16 15:45:14 +00:00
Martin L Roth
c2ed1e9ba0 Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"
This reverts commit 0e945a3426.

Reason for revert: Breaks build.  Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the
register that this patch enables

Signed-off-by: Martin L Roth <gaumless@gmail.com>
Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-16 12:29:39 +00:00
Maximilian Brune
c5f16c9f0d Revert ".gitmodules: Fix submodule revision to v0.1 tag"
This reverts commit 59a1a30ae1.

git submodule updates currently break, since apparently you can't use
git tags in the .gitmodules file.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibbc2bee21a723bd6d602ca435cada1dc0da03091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-16 05:18:27 +00:00
Sean Rhodes
0e945a3426 mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-16 01:12:17 +00:00
Shelley Chen
419cf93502 commonlib/storage: Add common eMMC functions
Now that multiple platforms are trying to initialize eMMC in coreboot
instead of depthcharge, lets move common functionality into commonlib
instead of copying the same functionality between multiple platforms.
Note for consistency, changed name of set_early_mmc_wake_status() to
mmc_set_early_wake_status().  Also adding an mmc_send_cmd1() function
for retrieving the Operating Conditions Register (OCR) contents.

BUG=b:218406702
BRANCH=None
TEST=emerge-herobrine coreboot chromeos-bootimage
     flash onto villager device and make sure still boots ChromeOS

Change-Id: Id00535b05bbd379081712601ef10e762c1831747
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-16 00:33:11 +00:00
Nicholas Chin
8ef2f7c77c util/kconfig: Add comment explaining difference from upstream
coreboot adds a patch on top of upstream Kconfig which allows the
generated Kconfig dependency files to be placed in a separate
directory than the autoconfig files based on the KCONFIG_SPLITCONFIG
variable. Add a comment to explain this difference.

Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 17:59:39 +00:00
Nicholas Chin
6e902bcfcb util/kconfig: Fix patch to be compatible with quilt
The patch added in commit b7f92a0b6a (util/kconfig: Add patch to
move Kconfig deps to build/config) uses git diff formatting, which
is incompatible with quilt.

Change-Id: I95bfe6571e3a2cc2b38074b4338f1610a4c8a595
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 17:58:53 +00:00
Martin Roth
dd7a04e7d7 mb/bostentech: Update name in Kconfig
The Bostentech mainboard appears out of order - this can be fixed either
by renaming the mainboard to start with S, or by the simpler method
used here by putting the mainboard directory name as the main name, then
noting that the full name is "Shenzhen Bostrontium Teng Technology".

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-15 17:57:31 +00:00
Elyes Haouas
7fd39ffbdd soc/intel/apollolake/pmutil.c: Fix smi_sts_bits[HSMBUS_SMI_STS_BIT]
Found using -Woverride-init command option.

Change-Id: I9f0755de9fae678fc5d78a709453fd1098d70e50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-15 09:03:45 +00:00
Tim Chu
a231d2c13e soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKS
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15 02:30:20 +00:00
Tim Chu
8e4500aa57 soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOAD
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL
MSR at a late BS_PAYLOAD_LOAD boot state.

This MSR is in platform scope and must only be locked once on each
socket. Add a spinlock to do so.

Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15 02:29:51 +00:00
Karthikeyan Ramasubramanian
ef1297689d soc/amd/mendocino: PSP_INCLUDES_HSP
Select HSP config to indicate that the SoC includes Hardware Security
Processor. This will allow PSP verstage to get and report the HSP state.

BUG=None
TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim.  Verify
that HSP is reported during the boot sequence.

Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 02:27:11 +00:00
Karthikeyan Ramasubramanian
e5f627ab85 soc/amd/common/psp_verstage: Report HSP Secure State
Get Hardware Security Processor(HSP) state in PSP Verstage through the
SVC call and report it in cbmem logs.

BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.

Change-Id: Ic4875d1732f22783a90434329188192b106168f4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 02:24:08 +00:00
Karthikeyan Ramasubramanian
8420ccc6e9 vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State
Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.

BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.

Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15 02:22:48 +00:00
Felix Held
683e43dbc6 soc/amd/mendocino/include/acpi,lpc: remove TODO after review
Remove TODO comment after checking against Mendocino PPR #57243, rev
3.02.

BUG=b:263563246

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15 02:22:17 +00:00
EricKY Cheng
a1f499f4d1 mb/google/skyrim/var/winterhold: Update USB port A0 setting
Update USB port Type-A Port A0 setting.

BUG=b:261650602
TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command.

Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-01-15 02:21:30 +00:00
Frank Chu
4eba742ee6 mb/google/brya/var/marasov: Update Aux settings
Follow hardware design to correct aux setting on USB-C ports to
fix DP monitor can not output data through type-C port 0

USB-C port 0 did not have retimer.
USB-C port 1 have retimer.

USB-C port 0 AUX_DC_P connect to GPP_E22.
USB-C port 0 AUX_DC_N connect to GPP_E23.

BUG=b:263212450
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
     DP monitor display normally

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15 02:06:25 +00:00
Dtrain Hsu
429df8adbe mb/google/skyrim/var/winterhold: Update I2C bus0 settings
Update settings for touchpad I2C frequency and data hold time.
I2C frequency and data hold time need to meet touchpad spec.
- I2C frequency: 380kHz - 400kHz
- Data hold time: 0.3us - 0.9us

BUG=b:262320419
TEST=On winterhold, touchpad i2c measurement from vendor,
Frequencies: 395 kHz, Data hold time: 0.66 us

Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15 02:05:15 +00:00
Felix Singer
a4f85470f7 docs/releases/4.19: Add note about ASL 2.0 conversion
Change-Id: I30d827043e3eb3bf21551b1cb6c0b4c369a70083
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-15 02:04:18 +00:00
Elyes Haouas
7726a31830 docs/releases/4.19: Add toolchain updates
Change-Id: If8c3f8e18ccbec8770917cc97aa562eac7417aaf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-15 02:04:04 +00:00
Martin Roth
13aef57841 Documentation/releases: Start getting ready for the 4.19 release
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-15 02:03:55 +00:00
Matt DeVillier
cf440b6530 drivers/uart/acpi: Drop 'disable_gpio_export_in_crs' flag
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.

There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.

This mirrors the change made for drivers/i2c/generic.

TEST=untested, as no boards selected this option.

Change-Id: Icb60502a4a7c5e7a1fcf1ee60e23c77e00d6de7b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71851
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15 02:02:18 +00:00
Matt DeVillier
ce7b252c4f drivers/spi/acpi: Drop 'disable_gpio_export_in_crs' flag
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.

There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.

This mirrors the change made for drivers/i2c/generic.

TEST=untested, as no boards selected this option.

Change-Id: I4f95d0e453d89b7e1978d3efac304518304495d1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71850
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15 02:02:01 +00:00
Matt DeVillier
4902e9b35f drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flag
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.

Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.

BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.

Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 02:01:48 +00:00
Sridhar Siricilla
2e6c55946c soc/intel/common: Use 'enum cb_error' values
The patch uses 'enum cb_error' values as return values for below
functions:
1. cse_get_rw_rdev()
2. cse_erase_rw_region()
3. cse_write_rw_region()
4. cse_locate_area_as_rdev_rw()
5. cse_get_target_rdev()
6. cse_copy_rw

TEST=Build, boot and perform CSE downgrade test on the Gimble board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15 01:58:17 +00:00
Sridhar Siricilla
dd7d51d12f soc/intel/common: Use 'enum cb_err' values
The patch uses cb_err enum values as return values for function
cse_get_boot_performance_data() instead of true/false.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15 01:57:18 +00:00
Sridhar Siricilla
ad6d3128f8 soc/intel/common: Use enum cb_err values
The patch uses cb_err enum values as return values for below functions:

1. cse_hmrfpo_enable()
2. cse_boot_to_ro()
3. cse_prep_for_rw_update()
4. cse_sub_part_get_target_rdev()
5. cse_get_sub_part_fw_version()
6. cse_prep_for_component_update()

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-15 01:56:23 +00:00
Elyes Haouas
2fed41d462 drivers/intel/i210/Makefile.inc: Fix "No such file or directory" error
Fix:
cc1: error: src/drivers/intel/i210: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I94b0f99353ed3a582ea590cbc6b12dec6294c75d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-14 13:28:50 +00:00
Martin Roth
d0d33d40ce configs/google_skyrim.no_video: Fix typo and regenerate
There was a typo in the config disabling bootblock
should have been:

# CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK is not set

As the line moved, it is the missing underscore after CONFIG,
preventing it from working as intended.

The other changes are updates to allow it to match what we get by
copying it to .config, then running:

make olddefconfig; make savedefconfig

Change-Id: Ic41a91e0a6ecd254a86d0872da19a0d4d321b8e3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71840
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-14 05:31:22 +00:00
Shelley Chen
83ac83015a commonlib/storage: fix int-to-pointer-cast error
When pulling in commonlib/storage/pci_sdhci.c into herobrine, am
seeing an "error: cast to pointer from integer of different size
[-Werror=int-to-pointer-cast]", so fixing that.

BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot
     Make sure that we can build without errors

Change-Id: Ib1718f156708a619f7eeb181e19b1a8c620de1f8
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71828
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-14 05:23:20 +00:00
Bora Guvendik
e8d4baca77 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00
The headers added are generated as per FSP v3503.00

BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Cq-Depend: chrome-internal:5318308, chrome-internal:5318129
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2023-01-13 23:42:27 +00:00
Ritul Guru
75a073d5ff soc/amd/phoenix: update mmconf base address and size
0xF8000000 was taken from old platform during phoenix porting, updating
it to 0xE0000000 to make room for 256 pci busses which is required for
usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256
busses are used.

Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13 23:42:04 +00:00
Felix Held
7137562135 soc/amd/glinda: use common SMU S3/4/5 entry message code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:36:46 +00:00
Felix Held
65d822e680 soc/amd/phoenix: use common SMU S3/4/5 entry message code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:36:30 +00:00
Felix Held
7a2c1c7b11 soc/amd/mendocino: use common SMU S3/4/5 entry message code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:36:22 +00:00
Felix Held
cdc6e82bbc soc/amd/cezanne: use common SMU S3/4/5 entry message code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:36:03 +00:00
Felix Held
43529966a0 soc/amd/picasso: use common SMU S3/4/5 entry message code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:35:56 +00:00
Felix Held
4a973324da soc/amd: introduce common SMU S3/4/5 entry message code
The smu_sx_entry function is identical for all AMD SoCs, so introduce it
as common code that can be selected to be included in the build via the
SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific
difference in this function is the ID of the SMC_MSG_S3ENTRY message
which is defined in each SoC's soc/smu.h include file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-13 23:35:48 +00:00
Martin Roth
e18d45cdf7 mb/google/skyrim: remove morthal variant
Morthal has been overcome by events.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13 21:07:50 +00:00
Fred Reitberger
eb59493a06 soc/amd/glinda: Use common fsp-s preloader
Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13 20:10:10 +00:00
Fred Reitberger
010c408044 soc/amd/phoenix: Use common fsp-s preloader
Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13 20:09:51 +00:00
Angel Pons
1cb930b5d1 mb/lenovo/t520: Disable SATA2 and Thermal on W520
If a discoverable device (e.g. a PCI device) does not appear in the
devicetree (typically because it is removable), coreboot enables it
by default. Disable the SATA2 (device for SATA ports 4 and 5, which
is not used in AHCI mode) and Thermal devices on W520 as well. Both
devices were only disabled on the T520.

Tested, this change fixes a long boot time when using MrChromebox's
edk2 payload on the W520, likely related to the following errors:

    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 0
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 1
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 2
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 3
    AHCI: Error interrupt reported PxIS: 40000001
    Non data transfer failed at retry 4

Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13 17:17:24 +00:00
Angel Pons
9ed576fbcd mb/lenovo/t520: Also disable PCI bridge on W520
As per Kendo3-WS schematics, the conventional PCI bridge is not used.

Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-13 17:15:24 +00:00
Elyes Haouas
419a2a75df mainboard: Remove duplicated <soc/gpio.h>
<gpio.h> chain-include <soc/gpio.h>.

Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-13 16:58:15 +00:00
Elyes Haouas
5316abe56c soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>
<gpio.h> chain-include <soc/gpio.h>.

Change-Id: If2af7f77e2d910a3f3470d15dbfc98775a2633b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-13 16:51:36 +00:00
Elyes Haouas
4d616e372f vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" error
Fix:
cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-13 16:49:18 +00:00
Elyes Haouas
15790c842c drivers/i2c/pca9538/Makefile.inc: Remove unused path
Change-Id: I435837381a966b61081d023447a6e7fdfd9a9348
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13 16:47:36 +00:00
Tim Crawford
d7c8d7d7c5 mb/system76/adl-p: Enable AER on CPU PCIe RP
Tested with the following drives:

- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)

Test:

- Drive is functional and has no unrecoverable errors on boot
- Drive is functional and has no unrecoverable errors after S0ix

Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13 16:42:14 +00:00
Tim Crawford
e51f96f741 mb/system76/adl-p: Add CPU PCIe RP RTD3 configs
Tested with the following drives:

- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)

Test:

- System still asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` still increases after suspend

Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-13 16:41:45 +00:00
Arthur Heymans
1d380128aa drivers/intel/i210.h: Remove 'extern' from declaration
"extern" is always implied with function declarations.
Also remove the comment as the linker will just tell you the same if a
definition is missing.

Change-Id: I53679ab57981790f82affb46a006281b348af574
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-13 16:11:48 +00:00
Michał Żygowski
9f87ad2c2f mb/msi/ms7d25: Add support for DDR5 variant
The DDR5 board is almost identical to the DDR4 one. The only major
difference is the board's DDR5 memory design.

TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory:
Crucial CT8G48C40U5.M4A1 in all 4 slots.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I652a879d1616df4708fe4690797ad98384897f53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-01-13 10:53:20 +00:00
Arthur Heymans
61ef0e4aa5 security/vboot: Check RW_NVRAM at buildtime
This avoids runtime failures of lacking a RW_NVRAM section in fmap or
one having a size too small.

Change-Id: I3415bd719428a23b21210eb2176dbe15fa44eb9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71868
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-01-13 08:25:33 +00:00
Sridhar Siricilla
8f9c1535a4 soc/intel : Use 'enum cb_err' values
Use 'enum cb_err' values for below cse lite functions instead of true or
false.

Functions whose return values updated in this patch:
 1. cse_set_next_boot_partition()
 2. cse_data_clear_request()
 3. cse_set_and_boot_from_next_bp()
 4. cse_boot_to_rw()
 5. cse_fix_data_failure_err()

TEST= Do boot test on Gimble.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13 04:51:15 +00:00
Sridhar Siricilla
4b6e8ca3a1 soc/intel: Use 'enum cb_err' instead of bool
The patch uses 'enum cb_err' values as return values for
cse_get_bp_info() function.

TEST=Build the code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13 04:50:59 +00:00
jamie_chen
a088887acf mb/google/brya/var/omnigul: Update GPIO settings
Configure GPIOs based from EE.

BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I5cfaa8fce6df7f09b744fb3e0b7b1d5b6acdc79b
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-13 01:04:30 +00:00
Fred Reitberger
41c7e31b0a soc/amd/mendocino: Use common fsp-s preloader
Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12 20:39:45 +00:00
Fred Reitberger
16f55f237c soc/amd/cezanne: Use common fsp-s preloader
Use the common preloader for fsp-s

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12 20:39:03 +00:00
Fred Reitberger
330a7b5c2c soc/amd/common/fsp: Introduce SOC_AMD_COMMON_FSP_PRELOAD_FSPS
The function to start preloading the fsp-s is identical in cezanne and
newer socs, so move it to common with a new Kconfig option to enable it.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12 20:38:53 +00:00
Fred Reitberger
672788d26b soc/amd/mendocino/include/soc/southbridge.h: Use BIT macro for consistency
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2dd17774b79c5adb64c2575ac55dec476c434842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71843
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12 20:35:52 +00:00
Fred Reitberger
b931ca89a3 soc/amd/mendocino: Remove TODO after review
Remove TODO comment after reviewing against mendocino ppr #57243, rev
3.00

BUG=b:263563246

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-01-12 20:35:41 +00:00
Felix Held
65335ffa48 soc/amd/mendocino/include/platform_descriptors: remove TODO after review
This header file is correct for Mendocino, so remove the TODO.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 20:32:22 +00:00
Elyes Haouas
8168e285bc soc/mediatek/common/mcu.c: Use 'enum cb_err' instead of 'int'
mtk_init_mcu() function already returns enum cb_err.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I562bfbdc5c917a17ce1aa656046b69eb56dce48c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2023-01-12 10:33:56 +00:00
Sridhar Siricilla
0ae7a8b765 soc/intel/common: Use enum csme_failure_reason
The patch updates return type for below functions as they uses
'enum csme_failure_reason' type return values.

 1. cse_sub_part_trigger_update()
 2. handle_cse_sub_part_fw_update_rv()
 3. cse_sub_part_fw_update()

TEST=Build coreboot code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 05:44:24 +00:00
Elyes Haouas
3ca8477901 soc/intel/skylake/Makefile.inc: Remove path to non-existent directories
Fix:
cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs]
cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs]
...

Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:10:10 +00:00
Elyes Haouas
1f9080a7c5 soc/intel/braswell/Makefile.inc: Remove path to non-existent directories
Found using 'Wmissing-include-dirs' command option.

Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:09:46 +00:00
Elyes Haouas
977c807418 vc/eltan/security/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:09:29 +00:00
Elyes Haouas
03a27b89ee mb/intel/jasperlake_rvp/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I5fee0053ab0281b713c33dbc5862c1d4587e854e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:09:09 +00:00
Elyes Haouas
44a7045481 mb/intel/elkhartlake_crb/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I1c6f6d99cfb3bc08966d662282c023e22e111f90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:08:23 +00:00
Elyes Haouas
c9cd886a4b treewide: Remove unused <cpu/x86/smm.h>
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:07:30 +00:00
Elyes Haouas
8b93a173fb treewide: Remove unused <cpu/amd/mtrr.h>
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12 05:07:21 +00:00
John Su
8afb45e0a6 mb/google/skyrim/var/markarth: Update devicetree setting
Update devicetree based on the schematic_20230105.

BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot

Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-12 05:02:33 +00:00
Jason Glenesk
2626b3eab4 3rdparty/amd_blobs:Advance submodule pointer
This picks up the following changes:
  acf73954 phoenix: rename morgana to phoenix
  a2c15297 mendocino: Upgrade SMU to 90.35.166
  28983855 Update Picasso FSP binaries

This also updates the phoenix fw.cfg file that points to the submodule.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 03:13:38 +00:00
Martin Roth
20646cdbe8 soc/amd: Change Morgana codename to Phoenix
Now that the next generation of APUs is officially announced, we can
unmask morgana.

The chip formerly known as Morgana is actually Phoenix.

Surprise!

This patch just changes the name across the entire codebase.

Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 03:13:17 +00:00
Jeremy Compostella
ba2cef5b54 soc/intel/common/block/early_graphics: Introduce a 200 ms delay
It has been reported that the PEIM graphics driver may temporarily
fail communication with the display if the time between libgfxinit
turning off the displays and the PEIM driver initialization is too
short. 200 ms has been identified as a safe delay.

This is a temporary workaround and an investigation is in progress to
come up with a better and long term solution.

BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is systematically seen

Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 03:02:02 +00:00
Jeremy Compostella
1f4d7c772e soc/intel/alderlake: Inform user of memory training
If memory training is going to happen and early graphics is supported
by the mainboard, an on-screen text message is displayed to inform the
end user.

Memory training can take a while and an impatient end user facing a
black screen for a while may reset the device unnecessarily.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On screen text message during MRC training observed on skolas

Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 02:57:12 +00:00
Jeremy Compostella
a439406bdc mb/google/brya: Add romstage early graphics for brya
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On-screen text message seen during MRC training on skolas
     with a few extra patches

Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
2023-01-12 02:56:22 +00:00
Jeremy Compostella
9df11973ca soc/intel/alderlake: Add romstage early graphics support
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verify that VGA text mode is functional in romstage

Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 02:55:53 +00:00
Jeremy Compostella
4475263bdf drivers/intel/gma: Enable Alder Lake libgfxinit support
This CL requires the following libgfxinit patches:
- https://review.coreboot.org/c/libgfxinit/+/65087
- https://review.coreboot.org/c/libgfxinit/+/65178
- https://review.coreboot.org/c/libgfxinit/+/67489
- https://review.coreboot.org/c/libgfxinit/+/65140
- https://review.coreboot.org/c/libgfxinit/+/67490
- https://review.coreboot.org/c/libgfxinit/+/67491
- https://review.coreboot.org/c/libgfxinit/+/67492
- https://review.coreboot.org/c/libgfxinit/+/67493
- https://review.coreboot.org/c/libgfxinit/+/67494
- https://review.coreboot.org/c/libgfxinit/+/67495
- https://review.coreboot.org/c/libgfxinit/+/67496
- https://review.coreboot.org/c/libgfxinit/+/67497
- https://review.coreboot.org/c/libgfxinit/+/67498
- https://review.coreboot.org/c/libgfxinit/+/67499
- https://review.coreboot.org/c/libgfxinit/+/67500
- https://review.coreboot.org/c/libgfxinit/+/67800
- https://review.coreboot.org/c/libgfxinit/+/67801
- https://review.coreboot.org/c/libgfxinit/+/67802
- https://review.coreboot.org/c/libgfxinit/+/69341

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit is compiled with the Alder Lake configuration 

Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70301
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 02:54:41 +00:00
Jeremy Compostella
47f154c8e5 soc/intel/common/block: Add Intel VGA early graphics support
This patch introduces an early graphics driver which can be used in
romstage in cache-as-ram mode. The implementation relies on
`libgfxinit' and provide VGA text mode support.

SoCs wanting to take advantage of this driver must implement the
`early_graphics_soc_panel_init' function to set the panel power
sequence timing parameters.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Graphics bring up observed on skolas with extra patches

Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12 02:54:09 +00:00
Subrata Banik
ca025203a8 mb/google/brya: Enable eNEM support for Tanik and Skolas
TEST=Able to build and boot Google/Tanik and Skolas to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a21122dbc324d3a396e8934e21d42f471cdb0bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11 21:06:05 +00:00
Werner Zeh
2f46a1780b mb/siemens/mc_ehl1: Enable real-time tuning
Enable the real-time tuning to improve performance in the real-time
environment for this mainboard.

Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 21:05:44 +00:00
Werner Zeh
adbdc5c1bd soc/intel/elkhartlake: Provide a way to enable real-time tuning
Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve
real-time behaviour of the SoC (see Intel doc #640979). It describes,
amongst knobs for the OS, a couple of firmware settings that need to be
set properly to reduce latencies in all the subsystems. Things like
clock and power gating as well as low power states for peripherals and
buses are disabled in this scenario.

This patch takes the mentioned UEFI parameters from the guide and
translates them to FSP-M and FSP-S parameters. In addition, a chip
config switch guards this tuning which can be selected on mainboard
level if needed.

When this real-time tuning is enabled, the overall system performance
in a real-time environment can be increased by 2-3%.

Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-11 21:05:32 +00:00
Dinesh Gehlot
7df8a69b26 soc/intel/meteorlake: Move ME firmware status register structures to
pertinent header file

This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.

The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.

The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarilly share the same SoC directory.

BUG=b:260309647
Test=Able to build and boot Google/rex

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11 21:04:25 +00:00
Dinesh Gehlot
bd8112ae2b soc/intel/alderlake: Move ME firmware status register structures to
pertinent header file

This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.

The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.

The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarilly share the same SoC directory.

BUG=b:260309647
Test=Able to build and boot Google/brya.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 21:03:12 +00:00
Maximilian Brune
59a1a30ae1 .gitmodules: Fix submodule revision to v0.1 tag
The goswid tool gets a rework and this shouldn't break coreboot builds. Therefore, a v0.1 tag was created to tie coreboot to a known working commit of goswid.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9d14f7653465c6b9e72dd3661e991d13b76c24c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-11 18:58:43 +00:00
Maximilian Brune
3b3f94757c src/sbom/Makefile.inc: Remove quotes on CONFIG_SBOM_ paths
Make will not find the build targets unless quotes are removed.

Change-Id: Iddf4e0cd8a11eaf327d6f55baf38a30c566d0f28
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 18:58:25 +00:00
Martin Roth
f3a672908f device/Kconfig: Fix selection of software connection manager
The patch that introduced the selection of software connection manager,
CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for
SCM and FCM) added a default to enable the software configuration
manager directly in the choice.

This leads to warnings when running make menuconfig:
src/soc/intel/alderlake/Kconfig:439:
warning: defaults for choice values not supported
src/soc/intel/meteorlake/Kconfig:337:
warning: defaults for choice values not supported
src/soc/intel/tigerlake/Kconfig:299:
warning: defaults for choice values not supported

I'm not sure why the Kconfig linter didn't catch this, but this
issue is currently breaking the build for me.  This patch fixes
it so that instead of setting the default directly, a new Kconfig
value is selected that then sets the default correctly.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I674046a93af8f7c2f3003900804deefa89dae295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11 16:53:59 +00:00
Prashant Malani
8c3fa461f3 ec/google/chromeec: Add retimer flag for mux device
Not all ports have retimers. Add a property to denote that a particular
port has a retimer (instead of assuming that all ports have retimers).

BUG=b:263964979
TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when
device tree is updated accordingly.

Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 16:37:38 +00:00
Sergii Dmytruk
c807d55798 security/tpm/tspi/log.c: fix strncpy() usage
Change-Id: Ib24129829bef3764a8ba1e2c0d92bc42c5cfbc8d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11 16:03:49 +00:00
Sergii Dmytruk
26203e7292 security/tpm: make tspi/crtm.c agnostic to log format
Change-Id: I3013bd5f29f1412fbe646dc74d8946704b750a66
Ticket: https://ticket.coreboot.org/issues/423
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11 16:03:22 +00:00
Sergii Dmytruk
2710df765b treewide: stop calling custom TPM log "TCPA"
TCPA usually refers to log described by TPM 1.2 specification.

Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022
Ticket: https://ticket.coreboot.org/issues/423
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-11 16:00:55 +00:00
Felix Singer
16a444c501 util/crossgcc/Makefile.inc: Terminate quoted string
`make help` does not execute successfully because a quoted string is
unterminated. Fix that.

Change-Id: I643fde1270a154ba523eb21522dcf5f6d4023110
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-11 15:36:08 +00:00
Bo-Chen Chen
817c6a7a4c mb/google/geralt: Use BOE_TV110C9M_LL0 as default mipi panel
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the
panel setting.

BUG=none
TEST=emerge-geralt coreboot;
     see panel-BOE_TV110C9M_LL0 in coreboot.rom

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 15:35:36 +00:00
Bo-Chen Chen
1fd7d9dc90 mb/google/geralt: Keep booting even if MIPI panel not found
We should keep booting even failed to get the MIPI panel.

BUG=none
TEST=emerge-geralt coreboot;

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 15:35:04 +00:00
Rex Chou
f488a40120 mb/google/skyrim/var/frostflow: Update I2C setting for touchpad
Update setting for touchpad I2C frequency.
And meet touchpad i2c SPEC (380 ~ 400 kHz).

BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 389 kHz

Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-01-11 14:57:43 +00:00
Johnny Lin
651e3e06a5 drivers/ocp/vpd: add get_cxl_mode_from_vpd()
cxl_mode VPD variable supports 3 modes: CXL_DISABLED,
CXL_SYSTEM_MEMORY and CXL_SPM.

Change-Id: Ib3bf85fbe687680db3c11efa908c4fb351be9c44
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11 14:57:20 +00:00
Jonathan Zhang
da538cb38f soc/intel/xeon_sp: Setup DPR for all VT-d devices
The Data Protected Range (DPR) needs to be set for all DPR devices,
not only the root device. Separate the setup from the memory
resource map reservation.

Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11 14:56:50 +00:00
Jakub Czapiga
b911c4896d soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.h
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ
define name.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-11 14:02:31 +00:00
Jeremy Compostella
765e5df0dd drivers/intel/gma: Hook up libgfxinit in romstage
A mainboard port needs to:

- select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT'

- implement the Ada package `GMA.Mainboard' with a single function
  `ports' that returns a list of ports to be probed for displays.

- set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use
  in romstage (and ramstage) for the graphic device.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit compiles in romstage.
     libgfxinit successfully executes in romstage and ramstage using
     the requested MMIO setting on skolas.

Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 13:59:54 +00:00
Jeremy Compostella
ea2dbdba2e soc/intel/meteorlake: Define SA_DEV_IGD for common code
SA_DEV_IGD is used by the early graphics feature implemented by the
Intel common block.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Compilation

Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-11 13:58:41 +00:00
Akihiko Odaki
d027dcef03 README.md: Update links
The links referred to the old wiki. They are updated to refer to
the current latest documentations.

Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Change-Id: I63cf5ab46124ae573e4bbc2dd725ec5b0732c286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-11 11:11:32 +00:00
Werner Zeh
6ffbae39b5 soc/intel/elkhartlake/chip.h: Include types.h instead of stdint.h
As the used 'bool' type is defined in stdbool.h, include types.h
(instead of stdint.h) which includes all needed header files.

Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11 06:41:39 +00:00
Harsha B R
4954a0f611 mb/intel/mtlrvp: Configure USB devices for MTL-RVP
This patch adds OC configuration of USB devices for MTL-RVP
as per MTL-RVP design specification,

USB 2.0
usb2_ports0 -> OC0
usb2_ports1 -> OC0
usb2_ports2 -> OC0
usb2_ports3 -> OC0
usb2_ports4 -> OC0
usb2_ports5 -> OC0
usb2_ports6 -> OC_SKIP
usb2_ports7 -> OC_SKIP
usb2_ports8 -> OC_SKIP
usb2_ports9 -> OC_SKIP

USB 3.2 Gen 2x1
usb3_ports0 -> OC0
usb3_ports1 -> OC0

TCPx
tcss_ports0 -> OC0
tcss_ports1 -> OC0
tcss_ports2 -> OC0
tcss_ports3 -> OC0

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
(on top of CB: 66190).

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-11 06:19:54 +00:00
Reka Norman
8b32e404e1 mb/google/nissa/var/craask: Disable storage devices based on fw_config
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).

BUG=b:263920313
TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned
fw_config and fw_config set correctly.

Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11 00:34:24 +00:00
Reka Norman
72fb5a915a mb/google/nissa/var/yaviks: Disable storage devices based on fw_config
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).

BUG=b:251055188
TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned
fw_config and fw_config set correctly.
On UFS SKU with fw_config set, eMMC no longer shows up in lspci.
(On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan
so there's no change in behaviour.)

Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-11 00:33:54 +00:00
Amanda Huang
2475e022e2 mb/google/brya/var/omnigul: Add memory parts support
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:

1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B

BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I699070596a77c975254660a1ba74b0f40026186d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-11 00:33:41 +00:00
Akihiko Odaki
64c0df58e2 soc/amd/common/fsp/Makefile: Fix an error message
It used to say "FSP-M binary larger than FSP_M_FILE", but
FSP_M_FILE is the binary itself. The binary file size is
actually compared with FSP_M_SIZE.

Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10 15:17:09 +00:00
Maximilian Brune
a0da5063ca Documentation/acronyms: Add several acronyms
Change-Id: I3d925516e48231b15d9aa78c5ef05b6de1ef42ca
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71665
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-10 14:44:53 +00:00
Pratikkumar Prajapati
c262b44d7c utils/inteltool: Add support to print Key Locker status
Add command-line option "-k" to print status.

Sample output:

$ inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : NO
===========================================================

Change-Id: Icb1b08619b1dbc535640127f7ab5f6b49d70a6fe
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-10 14:43:22 +00:00
Jamie Ryu
12367e0db1 mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.

Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N

BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-10 14:42:37 +00:00
Liam Flaherty
21c3c44ef5 mb/google/dedede/var/dibbi: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.

BUG=b:260934724, b:255447299
BRANCH=dedede
TEST=build

Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 14:40:37 +00:00
Frank Chu
e7bdc5fb8f mb/google/brya/var/marasov: Update DPTF parameters
Add the first version DPTF parameters.

BUG=b:264217345
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10 14:40:02 +00:00
Patrick Rudolph
98ecaa4a55 ifdtool: Determine max regions from IFD
IFDv1 always has 8 regions, while IFDv2 always has 16 regions.

It's platform specific which regions are used or are reserved.
The 'SPI programming guide' as the name says is a guide only,
not a specification what the hardware actually does.
The best to do is not to rely on the guide, but detect how many
regions are present in the IFD and expose them all.

Very early IFDv2 chipsets, sometimes unofficially referred to as
IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when
operating on an IFDv1.5 detect how much space is actually present
in the IFD.

Fixes IFD corruption on Wellsburg/Lynxpoint when writing a new
flash layout.

Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2023-01-10 13:55:17 +00:00
Sridhar Siricilla
d9c82695f5 soc/intel: Add Kconfigs to define scaling factor for cores
The patch adds Kconfigs to define scaling factor for Efficient and
Performance cores instead of using hard coded values in the soc code.
Also, the patches uses the Kconfigs directly to calculate the core's
nominal performance. So, we don't need to implement soc function
soc_get_scaling_factor() to get the scaling factor data for different
core types. Hence, soc_get_scaling_factor() function is removed.

TEST=Build the code for Gimble and Rex. Also, I have verified that
build system logs error when the Kconfigs are undefined.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 13:53:24 +00:00
Dinesh Gehlot
166c75c778 soc/intel/meteorlake: Use common gpio.h include
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h
includes with the common gpio.h which will include soc/gpio.h
which will include intelblocks/gpio.h which will include
soc/gpio_defs.h

BUG=b:261778357
TEST=Able to build and boot Google/rex.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I58e428cde5e13f4f0dfe528d798c0613b7f8a94a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71630
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-10 11:32:18 +00:00
Runyang Chen
268a18d58c soc/mediatek/common: Reset the watchdog timer before triggering reset
When the watchdog timer reaches 0, the timer value won't reset to the
default value unless there is an external reset or a kick. It will
result in the watchdog failing to trigger the reset signal.

We kick the watchdog to reset the timer to the default value. Also,
because WDT hardware needs about 94us to synchronize the registers,
add a 100us delay before triggering the reset signal.

BUG=b:264003005, b:264017048
BRANCH=corsola
TEST= Reboot successfully with the following cmd
      stop daisydog
      sleep 60 > /dev/watchdog&

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 09:39:51 +00:00
Derek Huang
da3812208e chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.

This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.

BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow

Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 09:33:47 +00:00
Felix Singer
b3ebf5ba0b util/liveiso: Update from 22.05 to 22.11
Update and also adjust configs so that they work with NixOS 22.11.

Change-Id: Ia0fed68f5449ccf56b25660f5cdbc8c239064748
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-01-10 07:20:29 +00:00
Subrata Banik
eab108f68b mb/google/brya: Allow respective variant to choose NEM config
This patch introduces a new config named `DEFAULT_ADL_NEM` and
allows respective brya variants with Alder Lake ESx samples to
choose NEM over eNEM as eNEM was fuse disabled till ESx.

TEST=The boot flow related to eNEM and NEM behaviour remains the
same with and without this patch.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-10 00:47:46 +00:00
Frank Chu
3b23fa6092 mb/google/brya/var/marasov: Disable touch panel power for non-touch sku
Disable touch panel power for non-touch sku by fw_config TOUCH field.

BUG=b:263452842
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4736f94481512806377b733b26fdc7290046c555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71691
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10 00:46:43 +00:00
Werner Zeh
ce6cdb3608 mb/siemens/mc_ehl1: Limit SATA speed to Gen 2
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause
issues as the margin is not big enough. Limit SATA speed to Gen 2 to
achieve a more robust SATA connection.

Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-10 00:30:59 +00:00
Werner Zeh
921bb34c91 soc/intel/elkhartlake: Make SATA speed limit configurable
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SataSpeedLimit' allows to set the speed limit.

This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.

Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-10 00:30:47 +00:00
Elyes Haouas
fc84ae7aa3 treewide: Remove unused <cpu/amd/msr.h>
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09 21:17:08 +00:00
Matt DeVillier
c3cef7e7b0 mb/google/dedede: Use runtime detection for touchscreens
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple dedede variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 21:10:30 +00:00
Matt DeVillier
7ab6ee6e71 mb/google/dedede: Set touchscreen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I212533ffdfb05f841e722c130b52c2976272e670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 21:10:19 +00:00
Matt DeVillier
3d5475d66c mb/google/dedede: Implement touchscreen power sequencing
For touchscreens on dedede variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).

Since the fast majority of dedede variants have a touchscreen option,
and those that do use the same GPIOs for enable/reset, set the GPIOs for
touchscreen operation in the baseboard and then override for the few (3)
variants that do not have a touchscreen.

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 21:10:10 +00:00
Matt DeVillier
af6029ba1a mb/google/dedede: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 21:10:02 +00:00
Elyes Haouas
3cd06cc427 soc/amd: Remove dummy SOC_SPECIFIC_OPTIONS
Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09 20:32:41 +00:00
Ritul Guru
6de377ef78 soc/amd/morgana: Double max number of cpus for morgana
Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09 17:32:27 +00:00
Ritul Guru
bf299f0d67 soc/amd/morgana: update morgana cpuid
Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09 17:31:51 +00:00
Fred Reitberger
b77f9a3d84 soc/amd/mendocino/Kconfig: Remove TODO after review
Remove TODO comments after reviewing against mendocino ppr #57243, rev
3.00

BUG=263563246
TEST=build skyrim

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 17:31:15 +00:00
Fred Reitberger
92982b669c soc/amd/common/block/graphics: Fix whitespace consistency
Replace spaces with tabs for consistency.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-09 17:30:58 +00:00
Marc Jones
45174112b6 soc/intel/xeon_sp/skx: Remove nested check for ACPI support
Remove redundant nested check for ACPI support.

Change-Id: Ie4b40382d304028135bcdd7851e2f48333570421
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-09 06:42:06 +00:00
Arthur Heymans
890117b880 configs: Build x201 for 64bit
This now also tests a lot of debug code on 64bit.

Change-Id: Iea3d5b8926fd8300c9daba0bc6dac91b9e55cdd6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-09 06:20:04 +00:00
Arthur Heymans
d7fc0688e5 sb/intel/common/spi: Fix building for 64bit
This avoids the warning of casting pointers to integers of different
size.

Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69389
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-09 06:19:11 +00:00
Tarun Tuli
b5445ade38 mb/google/brya: Increase Resizable BAR address space limit to 33 bits
The dGPU used for some Brya projects requests 33 bits of address
space for one of its BARs via the Resizable BAR mechanism
(requires 6GB).

This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33
bits for brya boards, which is enough for the GPU.

BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated

Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12
Signed-off-by: Tarun Tuli <tarun@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-09 06:16:03 +00:00
Robert Chen
ef485f66ff mb/google/brya/var/lisbon: Update RTL8168 LAN LED config
Adjust LAN LED config to 0x060f.

BUG=b:246657849
TEST=emerge-brask coreboot

Change-Id: Idd5ed2bf7eb4ee5990f2a842cba43f967ae3825e
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71698
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09 06:15:10 +00:00
Robert Chen
34d2600592 mb/google/brya/var/gladios: Update RTL8168 LAN LED config
Adjust LAN LED config to 0x060f.

BUG=b:239513596
TEST=emerge-brask coreboot

Change-Id: I17b844b89569fb7653454fd08782fc961c715817
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71697
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
2023-01-09 06:13:40 +00:00
Felix Singer
87a63fab53 MAINTAINERS: Add maintainers for the cross toolchain
Add the following people as maintainers for the cross toolchain.

  * Martin Roth
  * Felix Singer
  * Elyes Haouas

Change-Id: I3fad10baa0f0177693e009a4bbc218c6064611b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-09 05:26:32 +00:00
Sridhar Siricilla
205437b759 soc/intel/common: Fix cpu index calculation
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.

Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.

The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc  on each reboot.

TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.

The coreboot log with code instrumentation, before this patch:

[DEBUG]   my_apic_id:0x10 cpu_index: 0x6
[DEBUG]   my_apic_id:0x11 cpu_index: 0x6
[DEBUG]   my_apic_id:0x42 cpu_index: 0x6
[DEBUG]   my_apic_id:0x21 cpu_index: 0x6
[DEBUG]   my_apic_id:0x40 cpu_index: 0x6
[DEBUG]   my_apic_id:0x31 cpu_index: 0x6
[DEBUG]   my_apic_id:0x39 cpu_index: 0x6
[DEBUG]   my_apic_id:0xa cpu_index: 0x3
[DEBUG]   my_apic_id:0x0 cpu_index: 0x0
[DEBUG]   my_apic_id:0x8 cpu_index: 0x2
[DEBUG]   my_apic_id:0x4 cpu_index: 0x2
[DEBUG]   my_apic_id:0x28 cpu_index: 0x6
[DEBUG]   my_apic_id:0x2 cpu_index: 0x1
[DEBUG]   my_apic_id:0x38 cpu_index: 0x6
[DEBUG]   my_apic_id:0x29 cpu_index: 0x6
[DEBUG]   my_apic_id:0xe cpu_index: 0x5
[DEBUG]   my_apic_id:0x6 cpu_index: 0x2
[DEBUG]   my_apic_id:0x20 cpu_index: 0x6
[DEBUG]   my_apic_id:0x30 cpu_index: 0x6
[DEBUG]   my_apic_id:0x19 cpu_index: 0x6
[DEBUG]   my_apic_id:0xc cpu_index: 0x4
[DEBUG]   my_apic_id:0x18 cpu_index: 0x6

We can see same cpu_index for multiple cores before fix.

After this patch..
[DEBUG]   my_apic_id:0x10 cpu_index: 0x8
[DEBUG]   my_apic_id:019 cpu_index: 0xb
[DEBUG]   my_apic_id:0x11 cpu_index: 0x9
[DEBUG]   my_apic_id:0x18 cpu_index: 0xa
[DEBUG]   my_apic_id:0x40 cpu_index: 0x14
[DEBUG]   my_apic_id:0x30 cpu_index: 0x10
[DEBUG]   my_apic_id:0x42 cpu_index: 0x15
[DEBUG]   my_apic_id:0xc cpu_index: 0x6
[DEBUG]   my_apic_id:0x2 cpu_index: 0x1
[DEBUG]   my_apic_id:0x29 cpu_index: 0xf
[DEBUG]   my_apic_id:0xe cpu_index: 0x7
[DEBUG]   my_apic_id:0x20 cpu_index: 0xc
[DEBUG]   my_apic_id:0x0 cpu_index: 0x0
[DEBUG]   my_apic_id:0x31 cpu_index: 0x11
[DEBUG]   my_apic_id:0x28 cpu_index: 0xe
[DEBUG]   my_apic_id:0x21 cpu_index: 0xd
[DEBUG]   my_apic_id:0xa cpu_index: 0x5
[DEBUG]   my_apic_id:0x38 cpu_index: 0x12
[DEBUG]   my_apic_id:0x8 cpu_index:  0x4
[DEBUG]   my_apic_id:0x4 cpu_index: 0x2
[DEBUG]   my_apic_id:0x39 cpu_index: 0x13

Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09 04:44:00 +00:00
Subrata Banik
c8b840ffba soc/intel/alderlake: Disable Intel TXT based on INTEL_TXT config
This patch makes the call into TXT lib in order to disable the TXT
if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT
would be helpful to access VGA framebuffer prior calling into FSP-M.

TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 04:31:03 +00:00
Subrata Banik
ad87a82ca7 security/intel/txt: Add helper function to disable TXT
Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP
firmware can disable TXT if TXT fails or TPM is already enabled.

On platforms with TXT disabled, the memory can be unlocked using
MSR 0x2e6.

TEST=Able to perform disable_txt on SoC SKUs with TXT enabled.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 04:30:39 +00:00
Martin Roth
93f12985e6 Docs/releases: Update board support doc for 4.17 & 4.18 branches
Add the list of boards removed after the 4.18 release and update
other text.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id90a84eb9a417836a7d3fdd9b6f2f3ae34c95fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 02:41:07 +00:00
Martin Roth
d15bda4fab Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3
This removal was announced in 4.16, but didn't make it into the 4.17 or
4.18 release notes.

Those platforms have now been removed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I35607a86242c37e1578874b3a79ff0387a55b146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-09 02:39:28 +00:00
John Su
a07fca1eeb mb/google/skyrim/var/markarth: Enable DPTC support
Enable DPTC support for markarth.

BUG=b:263216451
TEST=emerge-skyrim coreboot

Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 00:26:45 +00:00
Ian Feng
d5d6ecf63a mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team.

1. Enable TS3 thermal sensor.
2. Set TS3 passive policy to 63.
3. Set TS3 critical policy to 73.
4. Modify TSR2 passive policy to CPU.

BUG=b:263554342
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 00:25:54 +00:00
Robert Chen
c28382eda2 mb/google/brya/var/gladios: Add ACPI DmaProperty for RTL8168 ethernet
Add ACPI DmaProperty for gladios.

BUG=b:239513596
TEST=Verified SSDT on gladios unit.

Before:
Scope (\_SB.PCI0.RP01)
    {
        Device (RLTK)
        {
            Name (_HID, "R8168")  // _HID: Hardware ID
            Name (_UID, 0xD0E889DD)  // _UID: Unique ID
            Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
            Name (_ADR, 0x00000000)  // _ADR: Address
            Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
            {
                0x07,
                0x03
            })
        }
    }

After:
Scope (\_SB.PCI0.RP01)
    {
        Device (RLTK)
        {
            Name (_HID, "R8168")  // _HID: Hardware ID
            Name (_UID, 0xD0E889DD)  // _UID: Unique ID
            Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
            Name (_ADR, 0x00000000)  // _ADR: Address
            Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
            {
                0x07,
                0x03
            })
            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
            {
                ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
                Package (0x01)
                {
                    Package (0x02)
                    {
                        "DmaProperty",
                        One
                    }
                }
            })
        }
    }

Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71699
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-09 00:24:50 +00:00
Pratikkumar Prajapati
bd26394496 soc/intel/common: Untie PRMRR from SGX
PRMRR is used by many Intel SOC features, not just Intel SGX.
As of now SGX and Key Locker are the features that need PRMRR.
Untie it from Intel SGX specific files and move to common cpulib.
Also rename PRMRR size config option. Use the renamed PRMRR size
config option to set the PRMRR size.

TEST=Able to set PRMRR size using config.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-08 19:36:43 +00:00
Subrata Banik
6a2495d8d9 security/intel/txt: Create Intel TXT lib with helper functions
This patch decouples useful TXT related operations from the romstage.c
file alone and moves them into a helper txtlib.c. This effort will be
helpful for SoC users to perform TXT related operations
(like Disabling TXT) even without selecting INTEL_TXT config.

At present, those helper functions are only available upon selecting
INTEL_TXT which is not getting enabled for most of the SoC platform in
the scope of the Chromebooks.

TEST=Able to access functions from txtlib.c even without selecting
INTEL_TXT config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-08 16:50:44 +00:00
Tim Chu
d292c4f0ea include/memory_info.h: Add soc_num to dimm_info struct
Sometimes, server platforms may have more than one socket on server
board. However, there's no field to store information about which
socket the DIMM comes from in dimm_info structure.

This patch adds soc_num field in dimm_info structure to store socket
ID of the DIMM.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1b9e2b87fda2d7c32ecb8ce9d989795c8b869cea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08 01:33:23 +00:00
Johnny Lin
6b1e7dd061 soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO
Also disable TCO timer through calling tco_configure().

If tco_configure() is not called, the TCO timeout would
trigger SMI periodically about every 2 seconds with SMM log:
"TCO_STS: BIT18 TIMEOUT"

Tested=On AC CRB, does not see periodic SMI log.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08 01:32:28 +00:00
Jonathan Zhang
43b0ed7089 soc/intel/xeon_sp: Improve final MTRR solution
If cbmem_top is not 1M aligned there will be a hole between DPR base
and cbmem_top that the allocator will consider as unassigned memory.
Resources could incorrectly be assigned to that region and the final
MTRR solution will also try to skip that hole, therefore using a lot
more variable MTRRs than needed.

TESTED on Archer City 2S system: Uses 1 variable MTRR in the final
setup instead of 7.

Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08 01:31:29 +00:00
Li, Jincheng
aa990125b8 arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields
values by macros

Macro definitions are from DMTF System Management BIOS (SMBIOS)
Reference Specification (DSP0134) Chapter 7.5.5.

Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-08 01:27:14 +00:00
Sean Rhodes
060df17f1d soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
Software Connection Manager doesn't work with Linux 5.13 or later,
resulting in TBT ports timing out. Not advertising this results
in Firmware Connection Manager being used and TBT works
correctly.

Add Kconfig options to chose between SCM (Software Connection
Manager) and FCM (Firmware Connection Manager). FCM is primary, as
it's more compatible save for ChromeOS devices as ChromeOS uses
SCM.

Linux patch:
torvalds/linux@c6da62a
c6da62a219d028de10f2e22e93a34c7ee2b88d03

Tested with StarBook Mk VI (i7-1260P).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-08 01:26:25 +00:00
Kapil Porwal
ae5bc43d3b soc/intel/meteorlake: Add support to configure package c-state demotion
This patch adds the support to enable/disable package c-state demotion
feature from the devicetree based on mainboard requirement.

Port of commit 4be8d9e80d ("soc/intel/adl: Add support to configure
package c-state demotion")

BUG=none
TEST=Boot to the OS on Google/Rex.

Snippet from FSP log:
[SPEW ]   PkgCState Demotion : 0x1

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08 01:24:18 +00:00
Kapil Porwal
ae5ba37a55 soc/intel/meteorlake: Set max Pkg C-states to Auto
This patch configures max Pkg C-state to Auto which limits the max
C-state to deep C-state.

Port of commit af42906efa ("soc/intel/alderlake: Set max Pkg C-states
to Auto")

BUG=none
TEST=Boot to the OS on Google/Rex.

Snippet from FSP log:
[SPEW ]   PkgCStateLimit : 0xFF

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08 01:22:56 +00:00
Martin Roth
bf3f94dbb2 drivers/amd: Update to use defined post codes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-08 01:22:15 +00:00
Martin Roth
cba09c8f13 mb/google/skyrim: Switch from LZMA to LZ4 compression for ramstage
Because skyrim is loading ramstage from SPI with the DMA engine, the
size of the compressed image is less important to load speed than
decompression time.

Because the LZ4 decompression is so much faster than LZMA, compressing
with LZ4 saves us roughly 30ms in boot time.

For size, we're spending roughly 57KiB:
fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed)
fallback/ramstage 0x9b00 stage 189126 LZ4  (305316 decompressed)

Right now we have 2MiB empty space in Skyrim's RO before this change,
and roughly 550KiB empty space in RW, so there aren't currently any
size worries.

Just for fun, I also tested uncompressed ramstage, and it was still
18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4.

BUG=b:264409477
TEST=Boot skyrim, look at boot speed.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-08 01:21:58 +00:00
Martin Roth
03511b4770 src/lib: Include LZMA in romstage for FSP-M
Previously, LZMA was included in romstage because it was almost always
needed to decompress ramstage.  When compressing ramstage with LZ4, but
using LZMA compression for FSP-M, we still need the LZMA decompression
to be present, so update when the Makefile includes the LZMA decoder.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-01-08 01:21:46 +00:00
Martin Roth
40729a58ea Kconfig: Add option to compress ramstage with LZ4
When ramstage is loaded asynchronously, as on the skyrim boards, the
faster decompression of LZ4 allows for faster boot times than the
tighter compression of LZMA.

To make this change, the name of the existing ramstage_compression
option needs to be updated.

BUG=b:264409477
TEST=Boot skyrim, look at boot speed

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08 01:20:15 +00:00
Liam Flaherty
c08585674a mb/google/dedede: Create dibbi variant
Create the dibbi variant of the waddledee reference board by
copying the template files to a new directory.

BUG=b:260934018
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a includes
GOOGLE_DIBBI

Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08 01:19:06 +00:00
John Su
df89c7d79d mb/google/skyrim/var/markarth: Update RAM ID table
Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B.
Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B

The RAM ID table has been assigned as:
DRAM Part Name                 ID to assign
K3KL8L80CM-MGCT                0 (0000)
H58G56BK7BX068                 0 (0000)
MT62F1G32D2DS-026 WT:B         0 (0000)
K3KL9L90CM-MGCT                1 (0001)
H58G66BK7BX067                 1 (0001)
MT62F2G32D4DS-026 WT:B         1 (0001)
MT62F512M32D2DR-031 WT:B       2 (0010)

BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot

Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-01-08 01:17:46 +00:00
Reka Norman
1a81e0a147 mb/google/nissa: Enable eNEM
Enable eNEM for all nissa variants. This is mostly done to be consistent
with other recent Intel platforms. It's not strictly necessary since on
nissa the LLC size is larger than the total code + data size used in
CAR. There is no change in boot time.

BUG=None
TEST=Boot to OS on craask

Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-08 01:17:00 +00:00
Eric Lai
e31c7e38c0 mb/google/nissa/var/craask: remove SAR UNUSED fw_config
This bit is dropped in factory. All skus can use table ID_0.

BUG=b:251287101
TEST=build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-08 01:14:30 +00:00
David Wu
a883c95bd8 mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and
SSFC is not set, it will treat missing SSFC as zero, so Kano needs
to set the ov2740 to 0 to avoid probing wrong mipi camera.

Before patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT

After patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>I2C: 00:20 disabled by fw_config
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT

BUG=b:262939431
TEST=Boot on kano and check functional with ov2740 camera.

Change-Id: I46fac6c820d6006956680a07198db82225630905
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08 01:10:08 +00:00
Jeremy Compostella
84c3b5e051 drivers/pc80/vga: Add legacy VGA romstage support
This is support for adding legacy VGA support into romstage.
Support for this is being provided by libgfxinit.

The current use case allows us to initialize the display
before memory init (prior to physical memory init) to inform
the user when lengthy memory training is needed.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=VGA code compiles for romstage

Change-Id: I81309871e8db71657b2a9816708141f121d767d3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70278
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-07 17:46:54 +00:00
Subrata Banik
114f87bf2e mb/google/rex: Disable stage cache
This patch disables the stage cache to save boot time.

Note: S3 is not POR for Intel MTL mobile skus.

Boot time is reduced by ~8ms.

Boot time before:
   4:end of romstage                1,391,225 (13,724)
 100:start of postcar               1,403,339 (12,114)

Boot time after:
   4:end of romstage                1,380,262 (5,618)
 100:start of postcar               1,392,323 (12,060)

Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-07 16:20:32 +00:00
Martin Roth
19c35f1a8f mb/amd: Update pademelon to eval board
While pademelon may be a desktop board, it's not available for purchase,
which means it should be presented here as an eval board.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-07 06:07:41 +00:00
Sean Rhodes
c07f165b08 mb/starlabs: Remove the bios_version function
Remove smbios_mainboard_bios_version so that the default
CONFIG_LOCALVERSION can be used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-01-07 03:32:13 +00:00
Martin Roth
fbd13a84cf vc/google: Add and use POST_CODE_CLEAR definition
The CR50 code clears the post code value.  Add this as a #define.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-07 03:31:41 +00:00
Sridhar Siricilla
4c3014feb2 soc/intel/: Rename small and big cores references
The patch addresses Intel heterogeneous cores as `Efficient` and
`Performance` cores instead of `small` and `big` cores. It is to ensure
coreboot code has uniform reference to the heterogeneous cores. So, the
patch renames all `small` and `big` core references to `efficient` (eff)
and `performance` (perf) cores respectively.

TEST=Build the code for Brya and Rex boards

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-06 21:34:54 +00:00
Pratikkumar Prajapati
63fcc4acc2 soc/intel/common: Check PRMRR dependent features
Add below mentioned functions:

is_sgx_configured_and_supported():
	Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
	Checks if Key Locker is configured and supported
check_prm_features_enabled():
	Checks if any of the features that need PRM are configured
	and supported. As of now SGX and Key Locker are the only
	features that need PRM.

Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-06 19:19:34 +00:00
Pratikkumar Prajapati
dd63dc1dc5 soc/intel/common: Add Kconfig option for Intel Key Locker
Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The
specification of Key Locker can be found via document #343965
on Intel's site.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06 19:19:03 +00:00
Elyes Haouas
ed2494e545 mb/amd/mandolin/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: src/mainboard/amd/mandolin/acpi: No such file or directory [-Werror=missing-include-dirs]

Change-Id: Ifbe6fda12088ddf51b6a177116aa542dbacc7672
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-06 13:13:38 +00:00
Elyes Haouas
9f90964415 mb/amd/bilby/Makefile.inc: Remove path to non-existent directory
Fix:
cc1: error: src/mainboard/amd/bilby/acpi: No such file or directory [-Werror=missing-include-dirs]

Change-Id: Ie167cd362b55e38870d26a877d8181b2b07b8639
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-06 13:13:32 +00:00
Kapil Porwal
cca3c90ed9 soc/intel/meteorlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows MTL boards to dynamically assign PCI IRQs. This means not relying
on FSP defaults, which eliminates the problem of PCI IRQs interfering
with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC
routing.

BUG=none
TEST=Build and boot to google/rex. Check dmesg and make sure that there
is no regression.

IO-APIC interrupts before:
   1:   IO-APIC    1-edge      i8042
   8:   IO-APIC    8-edge      rtc0
   9:   IO-APIC    9-fasteoi   acpi
  14:   IO-APIC   14-fasteoi   INTC1083:00
  16:   IO-APIC   16-fasteoi   idma64.5, ttyS0, intel-ipu6
  28:   IO-APIC   28-fasteoi   idma64.6, pxa2xx-spi.6
  29:   IO-APIC   29-fasteoi   i2c_designware.3
  30:   IO-APIC   30-fasteoi   i2c_designware.4
  32:   IO-APIC   32-fasteoi   idma64.0, i2c_designware.0
  33:   IO-APIC   33-fasteoi   idma64.1, i2c_designware.1
  35:   IO-APIC   35-fasteoi   idma64.2, i2c_designware.2
  88:   IO-APIC   88-fasteoi   ELAN0000:00
  89:   IO-APIC   89-fasteoi   chromeos-ec
  99:   IO-APIC   99-edge      cr50_i2c
 106:   IO-APIC  106-fasteoi   chromeos-ec

IO-APIC interrupts after:
   1:   IO-APIC    1-edge      i8042
   8:   IO-APIC    8-edge      rtc0
   9:   IO-APIC    9-fasteoi   acpi
  14:   IO-APIC   14-fasteoi   INTC1083:00
  16:   IO-APIC   16-fasteoi   intel-ipu6
  20:   IO-APIC   20-fasteoi   idma64.5, ttyS0
  27:   IO-APIC   27-fasteoi   idma64.0, i2c_designware.0
  28:   IO-APIC   28-fasteoi   idma64.1, i2c_designware.1
  30:   IO-APIC   30-fasteoi   idma64.2, i2c_designware.2
  31:   IO-APIC   31-fasteoi   i2c_designware.3
  32:   IO-APIC   32-fasteoi   i2c_designware.4
  35:   IO-APIC   35-fasteoi   idma64.6, pxa2xx-spi.6
  88:   IO-APIC   88-fasteoi   ELAN0000:00
  89:   IO-APIC   89-fasteoi   chromeos-ec
  99:   IO-APIC   99-edge      cr50_i2c
 106:   IO-APIC  106-fasteoi   chromeos-ec

_PRT before:
  Package (0x04) ==> 0x001FFFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x001FFFFF, One, Zero, 0x11
  Package (0x04) ==> 0x001FFFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x001FFFFF, 0x03, Zero, 0x13
  Package (0x04) ==> 0x001EFFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x001EFFFF, One, Zero, 0x11
  Package (0x04) ==> 0x001EFFFF, 0x02, Zero, 0x1B
  Package (0x04) ==> 0x001EFFFF, 0x03, Zero, 0x1C
  Package (0x04) ==> 0x001CFFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x001CFFFF, One, Zero, 0x11
  Package (0x04) ==> 0x001CFFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x001CFFFF, 0x03, Zero, 0x13
  Package (0x04) ==> 0x0019FFFF, Zero, Zero, 0x1D
  Package (0x04) ==> 0x0019FFFF, One, Zero, 0x1E
  Package (0x04) ==> 0x0019FFFF, 0x02, Zero, 0x1F
  Package (0x04) ==> 0x0017FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0016FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0016FFFF, One, Zero, 0x11
  Package (0x04) ==> 0x0016FFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x0016FFFF, 0x03, Zero, 0x13
  Package (0x04) ==> 0x0015FFFF, Zero, Zero, 0x20
  Package (0x04) ==> 0x0015FFFF, One, Zero, 0x21
  Package (0x04) ==> 0x0015FFFF, 0x02, Zero, 0x22
  Package (0x04) ==> 0x0015FFFF, 0x03, Zero, 0x23
  Package (0x04) ==> 0x0014FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0014FFFF, One, Zero, 0x11
  Package (0x04) ==> 0x0014FFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x0012FFFF, Zero, Zero, 0x1A
  Package (0x04) ==> 0x0012FFFF, One, Zero, 0x25
  Package (0x04) ==> 0x0012FFFF, 0x02, Zero, 0x19
  Package (0x04) ==> 0x0010FFFF, Zero, Zero, 0x17
  Package (0x04) ==> 0x0010FFFF, One, Zero, 0x16
  Package (0x04) ==> 0x000DFFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x000DFFFF, One, Zero, 0x11
  Package (0x04) ==> 0x000BFFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0008FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0007FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0007FFFF, One, Zero, 0x11
  Package (0x04) ==> 0x0007FFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x0007FFFF, 0x03, Zero, 0x13
  Package (0x04) ==> 0x0006FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0006FFFF, One, Zero, 0x11
  Package (0x04) ==> 0x0006FFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x0006FFFF, 0x03, Zero, 0x13
  Package (0x04) ==> 0x0005FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0004FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0002FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0001FFFF, Zero, Zero, 0x10
  Package (0x04) ==> 0x0001FFFF, One, Zero, 0x11
  Package (0x04) ==> 0x0001FFFF, 0x02, Zero, 0x12
  Package (0x04) ==> 0x0001FFFF, 0x03, Zero, 0x13

_PRT after:
  Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011
  Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012
  Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0006FFFF, 0x01, 0x00, 0x00000011
  Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012
  Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013
  Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014
  Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015
  Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016
  Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017
  Package (0x04) ==> 0x000BFFFF, 0x00, 0x00, 0x00000013
  Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000014
  Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000015
  Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000016
  Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000017
  Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x00000018
  Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x00000019
  Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000011
  Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000012
  Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x0000001A
  Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000013
  Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x0000001B
  Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x0000001C
  Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x0000001D
  Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x0000001E
  Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000014
  Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000015
  Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000016
  Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000017
  Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x0000001F
  Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x00000020
  Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x00000021
  Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011
  Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012
  Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013
  Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000014
  Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000015
  Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x00000022
  Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x00000023
  Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000017
  Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000014
  Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000015
  Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000016

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I013cd5faab6f425ab1af91fe2a36ac3b8aeef443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06 11:54:28 +00:00
jamie_chen
780f99b61c mb/google/brya/var/omnigul: use i2c1 for TPM
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
omnigul variant.

BUG=b:263060849
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-06 11:53:41 +00:00
jamie_chen
423b812e48 mb/google/brya/var/omnigul: use RPL FSP headers
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL.

Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL
FSP headers for omnigul.

BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>

Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06 11:53:19 +00:00
Ren Kuo
9965c8b5b4 mb/google/nissa/var/craask: Modify GPIOs for NVMe
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for
commonality of GPIO settings. To reserve craask GPIO table and add
craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will
be 2 and clksrc is still 1.

BUG=b:259211172
TEST=Verify on reworked craask DUT to boot up from NVMe.

Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06 11:52:55 +00:00
Reka Norman
91fe94ac9f mb/google/nissa: Disable stage cache
Although S3 is supported on nissa, only S0ix is used on user devices,
so we can ignore optimising the S3 resume time. Disable the stage
cache to save boot time at the cost on increasing the S3 resume time.

Boot time is reduced by ~6 ms. This is mostly from adding postcar to
the stage cache, which is slow since TSEG is not cached in romstage.
Adding ramstage and FSP-S take negligible time.

The S3 resume time is increased by ~89 ms total from loading and
decompressing ramstage and FSP-S.

Boot time before:
  3:after RAM initialization                          573,295 (931)
  4:end of romstage                                   583,569 (10,274)
100:start of postcar                                  587,729 (4,160)

Boot time after:
  3:after RAM initialization                          571,527 (830)
  4:end of romstage                                   575,712 (4,185)
100:start of postcar                                  579,866 (4,153)

S3 resume time before:
101:end of postcar                                    368,904 (0)
 10:start of ramstage                                 369,165 (260)
971:loading FSP-S                                     385,742 (16,577)
 30:device enumeration                                407,105 (21,362)

S3 resume time after:
101:end of postcar                                    363,101 (0)
  8:starting to load ramstage                         363,101 (0)
 15:starting LZMA decompress (ignore for x86)         382,802 (19,701)
 16:finished LZMA decompress (ignore for x86)         431,620 (48,817)
  9:finished loading ramstage                         431,850 (230)
 10:start of ramstage                                 431,927 (76)
971:loading FSP-S                                     448,357 (16,430)
 17:starting LZ4 decompress (ignore for x86)          474,420 (26,062)
 18:finished LZ4 decompress (ignore for x86)          474,627 (206)

BUG=b:247940538, b:192032803
TEST=Boot and S3 suspend/resume on craask

Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-06 10:39:45 +00:00
Reka Norman
166c30309e Kconfig: Allow mainboards to disable stage cache
On recent Intel ChromeOS devices, although S3 is still supported, only
S0ix is used on user devices, so we don't care about optimising S3
resume time. Disabing the stage cache saves boot time at the cost of
increasing the S3 resume time. E.g. on nissa this reduces boot time by
6 ms and increases S3 resume time by 89 ms.

BUG=b:247940538, b:192032803
TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE
selected.

Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-06 10:39:35 +00:00
Pratikkumar Prajapati
17c847b5ea soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro
Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU
capabilities flags using cpuid_ext inline function.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71646
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-06 03:38:18 +00:00
John Su
2819edb497 mb/google/skyrim/var/markarth: Update GPIO settings
Configure GPIOs based on b/263534907#comment4 from EE.

BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05 17:59:09 +00:00
Elyes Haouas
692fc58a6f Update vboot submodule to upstream main
Updating from commit id 196b0843e9 :
to a09b792e6a : Makefile: Remove old include directories
This brings in 9 new commits.

Fix:
cc1: error: firmware/lib/cryptolib/include: No such file or directory [-Werror=missing-include-dirs]
cc1: error: firmware/lib20/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I292d3a4046c1a1890a640747cbbd00e79e5e56b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71582
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-05 17:57:33 +00:00
Chris.Wang
adec2e6c45 mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.

It needs to confirm the PCIe Signal Integrity after enabled.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05 17:56:55 +00:00
Frank Chu
81016b5c24 mb/google/brya/var/marasov: Disable FPMCU interface
Set fingerprint control GPIO to NC by HW design.

BUG=b:264340020
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I304862f0dd201da100b89c79a473eb116fc8263e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71650
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-05 17:56:15 +00:00
Tim Crawford
7c92712cf0 mb/system76/tgl-u: Add FSP-S configs per variant
Configure CPU PCIe RP and IOM per variant.

Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-01-05 17:55:17 +00:00
Elyes Haouas
06545e0744 nb/intel/haswell: Specify supported memory type
Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-05 05:32:47 +00:00
jamie_chen
314ace1604 mb/google/brya: Create omnigul variant
Create the omnigul variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:263060849
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OMNIGUL

Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-05 00:45:22 +00:00
Jakub Czapiga
ae0a4f609c Revert "mb/google/brya: Define a more suitable MRC training text message"
This reverts commit e45f70423e.

Reason for revert: Merged out of order, broke tree

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-04 22:28:35 +00:00
Jakub Czapiga
43b7e60e3e Revert "mb/google/brya: Add romstage early graphics for brya"
This reverts commit 96d9b75669.

Reason for revert: Merged out of order, broke tree

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 20:30:38 +00:00
Jeremy Compostella
e45f70423e mb/google/brya: Define a more suitable MRC training text message
This message is designed to reduce end-user confusion who may not
know what memory training is. It also provides a maximum time
estimation calibrated for brya devices.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=New message observed on skolas

Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 16:39:10 +00:00
Jeremy Compostella
96d9b75669 mb/google/brya: Add romstage early graphics for brya
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On-screen text message seen during MRC training on skolas
     with a few extra patches

Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-04 16:37:42 +00:00
Kapil Porwal
9395cf9a2f soc/intel: Create common function to check PCH slot
BUG=none
TEST=Build and boot to google/taniks. Check dmesg and make sure that
there is no regression.

Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt
assignment.

IO-APIC interrupts before and after this patch:
  1: IO-APIC 1-edge i8042
  8: IO-APIC 8-edge rtc0
  9: IO-APIC 9-fasteoi acpi
 14: IO-APIC 14-fasteoi INTC1055:00
 23: IO-APIC 23-fasteoi idma64.5, ttyS0
 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0
 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1
 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2
 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3
 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4
 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6
 77: IO-APIC 77-edge cr50_i2c
 100: IO-APIC 100-fasteoi ELAN0000:00
 103: IO-APIC 103-fasteoi chromeos-ec

_PRT before and after this patch:
  Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011
  Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012
  Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012
  Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013
  Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014
  Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015
  Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016
  Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017
  Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011
  Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013
  Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018
  Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019
  Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014
  Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015
  Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A
  Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B
  Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C
  Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D
  Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E
  Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F
  Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016
  Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020
  Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021
  Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022
  Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023
  Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017
  Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024
  Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011
  Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025
  Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026
  Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027
  Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028
  Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012
  Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013
  Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014
  Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015
  Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016
  Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029
  Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A
  Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B
  Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011
  Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012
  Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013
  Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010
  Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011
  Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012
  Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013
  Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017
  Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014
  Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C
  Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D
  Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016
  Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017
  Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014
  Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 14:12:29 +00:00
Elyes Haouas
f82e68c900 spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>.

Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 12:39:32 +00:00
Harsha B R
af6cd3f0b4 mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required
to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig
option, CSE reboots the system into CSE_RW FW region on cold reboot.

BUG=b:224325352
TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe
CSE boot to RW FW region as part of coreboot console log,

localhost ~ # cbmem -c | grep cse
[DEBUG]  cse_lite: Number of partitions = 3
[DEBUG]  cse_lite: Current partition = RW
[DEBUG]  cse_lite: Next partition = RW

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 10:58:06 +00:00
Elyes Haouas
d2ebc4d39f nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONS
Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04 07:23:53 +00:00
Elyes Haouas
5a04746714 spd.h: Move enum ddr2_module_type to ddr2.h
Move specific enum ddr2_module_type to <device/dram/ddr2.h>.

Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04 07:22:58 +00:00
Elyes Haouas
0461005908 nb/intel/ironlake: Specify supported memory type
Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-04 07:22:33 +00:00
Paul Menzel
1868991a36 payloads: Update GRUB2 stable version from 2.04 to 2.06
GRUB2 was released on June 8th, 2021 [1].

[1]: https://lists.gnu.org/archive/html/grub-devel/2021-06/msg00022.html

Change-Id: I050a78c769c3cd4c9ae627c7e3124a4894a018d7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-04 07:15:48 +00:00
Chris.Wang
ad12b4f440 soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization
Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 07:15:10 +00:00
John Su
e66fcb87fe mb/google/skyrim/var/markarth: Generate RAM IDs for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name                 ID to assign
K3KL8L80CM-MGCT                0 (0000)
H58G56BK7BX068                 0 (0000)
K3KL9L90CM-MGCT                1 (0001)
H58G66BK7BX067                 1 (0001)
MT62F2G32D4DS-026 WT:B         1 (0001)

BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04 07:08:41 +00:00
Chao Gui
ca07e1cff9 mb/google/skyrim: Create markarth variant
Create the markarth variant of the skyrim reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:262092858
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MARKARTH

Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82
Signed-off-by: Chao Gui <chaogui@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-01-04 07:06:27 +00:00
Wisley Chen
cdf7ec6faa mb/google/nissa/var/yaviks: Disable external fivr
In next phase, yaviks will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.

BUG=b:263842258
TEST=build, boot to OS, suspend/resume work normally.

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-01-04 07:02:24 +00:00
Subrata Banik
6f5be8ff30 mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into
safe state aka LOW/PD.

BUG=b:263411621
TEST=Able to build and boot Google, Rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 07:00:29 +00:00
Kapil Porwal
a2a9e8ea8f soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSID
BUG=none
TEST=Verify presence of subsystem ID for fast_spi device on google/rex.

lspci output before this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]

lspci output after this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
        Subsystem: Intel Corporation Device [8086:7e23]

Note: UPD SiSkipSsidProgramming was set to 1 for above test.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-04 04:50:56 +00:00
Pratikkumar Prajapati
08e8067a58 soc/intel/common: Add API to check Key Locker support
Add is_keylocker_supported() API in common cpulib.

This function checks if the CPU supports Key Locker feature.
Returns true if Key Locker feature is supported otherwise false.

Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04 03:41:39 +00:00
Mike Shih
644b0f5f45 mb/google/brya/var/gaelin: Use RPL FSP headers
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP.

Since we use RPL FSP and it will support ADL as well, we rename
"Gaelin4ADL" to "Gaelin".

BUG=b:258603624
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot

Cq-Depend: chrome-internal:5227091, chromium:4113361
Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c
Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-04 00:48:17 +00:00
Kevin Chiu
7f5adef634 mb/google/brya/var/lisbon: Update audio codec i2c timing
Adjust audio codec i2c timing to 399 kHz.

BUG=b:263050944
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I8495a88f2034e5e4ccf28ff53c81e0d6561e2e0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-03 18:52:14 +00:00
Chris.Wang
1162f7a1fe mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe
winterhold/whiterun has different H/W topology to skyrim that the eMMC device
is on a different GPP:
skyrim: GPP1 -> SD
winterhold : GPP1 -> eMMC

BUG=b:263763288
BRANCH=none
TEST=s0i3 stress over 2500 cycles.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-01-03 18:16:00 +00:00
Elyes Haouas
b3a28c3a66 vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
Fix:
    CC         romstage/mainboard/amd/pademelon/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/amd/gardenia/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

    CC         romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-03 18:09:50 +00:00
Elyes Haouas
82fe13eef8 soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent directories
Found using 'Wmissing-include-dirs' command option.
Fix:
cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03 18:08:00 +00:00
Elyes Haouas
dba65d24b9 soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent directories
Found using 'Wmissing-include-dirs' command option.
Fix:
cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03 18:07:33 +00:00
Elyes Haouas
553335fbe2 soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent directory
Found using 'Wmissing-include-dirs' command option.
Fix:
cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs]

Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-03 18:06:54 +00:00
Matt DeVillier
7cfedc8b1b soc/intel/baytrail: add _HRV to GPIO ACPI devices
For some reason, the Windows LPEA drivers won't attach without
 _HRV (hardware version) defined for the GPIO controllers.
Add it, using value taken from Intel baytrail/valleyview edk2
reference code.

TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load
properly.

Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03 17:48:13 +00:00
Matt DeVillier
e20165d7bb soc/intel/baytrail: add _HRV to I2C ACPI devices
For some reason, the Windows i2c drivers won't attach without
_HRV (hardware version) defined for the i2c controllers.
Add it, using value taken from Intel baytrail/valleyview edk2
reference code.

TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load
properly.

Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03 17:47:51 +00:00
Matt DeVillier
93572c573a mb/google/samus: Set hidden flag for RT5677AA ACPI device
Coolstar's Windows drivers don't utilize it, and the Linux drivers
don't care about _STA, so hide it from Windows to tidy up Device
Manager.

Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03 17:46:45 +00:00
Matt DeVillier
cecf5f01ea mb/google/slippy/peppy: Set cypress TP IRQ to Level vs Edge
Change the IRQ triggering from edge to level for cypress touchpad
on peppy variant for compatibility with Windows drivers.

TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad
functional.

Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-03 17:46:16 +00:00
Elyes Haouas
6a4c517850 nb/intel/e7505: Specify supported memory type
Change-Id: Idda0a8330463205efe5ec5faa82a1f458894e521
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 22:45:27 +00:00
Matt DeVillier
80bf8efeaa mb/google/drallion: Use runtime detection for touchscreens
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on drallion, verify touchscreen functional
in OS, dump ACPI and verify only i2c devices actually present on the
board have entries in the SSDT.

Change-Id: I67c3d1fc3d34e9b67ddb26afcaad3a47ffa92e2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 20:40:50 +00:00
Matt DeVillier
dde3278708 mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 20:40:18 +00:00
Matt DeVillier
631d77eca9 mb/google/drallion: Implement touchscreen power sequencing
For touchscreens on drallion, drive the enable GPIO high starting in
romstage while holding in reset, then disable the reset GPIO in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens during ACPI SSDT generation (implemented in a subsequent
commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 20:40:00 +00:00
Matt DeVillier
17a07b38a1 mb/google/drallion: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty implementation to
be used in a subsequent commit for touchscreen power sequencing.
Call method in romstage to program any GPIOs that may need to be set.

TEST=tested with rest of patch train

Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 20:39:27 +00:00
Elyes Haouas
bfcea14a16 nb/intel/i440bx: Specify supported memory type
Change-Id: If94037f2b010527440795e6920dd7a533c52f606
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-02 20:37:46 +00:00
Subrata Banik
01c190e382 mb/google/rex: Update USB2-C1 mapping
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1
as per latest Rex schematics dated 12/06/2022.

TEST=Hardward awaited.

Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02 09:20:02 +00:00
Subrata Banik
2bc46c9601 mb/google/rex: Remove USB2_8 Connection
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect.

BUG=b:263494661
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02 09:19:53 +00:00
Subrata Banik
d38baae038 mb/google/rex: Revise config for the Proto 1 build
1. Rename DB_USB4 for KB8010 while adding ANX7452 as different
DB_USB4 option.
2. Add audio component for Soundwire.
3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S.

Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02 09:19:45 +00:00
Subrata Banik
3e3b78a391 drivers/pc80/vga: Add API to write multi-line video message
This patch provides an API to allow users to output multi-line
messages using VGA framebuffer.

The current limitation with multiline message is that,
vga_line_write() function is unable to understand newline character
hence, eventually output multiple lines separated with a newline
character with a single line statement.

This patch ensures to parse the entire string and split it into
multiple lines based on the newline character and print each line
separately to the VFG framebuffer.

User can choose to align the output video message as per given choice
between left/center/right of the screen
(i.e. enum VGA_TEXT_ALIGNMENT ).

Additionally, added macros to define the horizontal screen alignment
as well. Ideally if user would like to print the video message at the
middle of the screen then the vertical alignment would be
`VGA_TEXT_CENTER` and horizontal alignment would be
`VGA_TEXT_HORIZONTAL_MIDDLE`.

TEST=Able to build and boot Google/Taeko.

While output a video message such as :

"Your device is finishing an update. This may take 1-2 minutes.\nPlease
do not turn off your device."

Without this patch:

Your device is finishing an update. This may take 1-2 minutes. nPlease
do not turn off your device.

With this patch:

(in Left Alignment):
Your device is finishing an update. This may take 1-2 minutes.
Please do not turn off your device.

(in Right Alignment):
         Your device is finishing an update. This may take 1-2 minutes.
                                    Please do not turn off your device.

(in Center Alignment):
   Your device is finishing an update. This may take 1-2 minutes.
              Please do not turn off your device.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-02 05:45:23 +00:00
Pratikkumar Prajapati
e51978f26f soc/intel/common: Move SGX supported API to cpulib
Move is_sgx_supported() API to common cpulib code, so that
this function can be used by other code without enabling
SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option.

Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-02 03:55:04 +00:00
Elyes Haouas
9693bcb4c4 apollolake/include/soc/meminit.h: Add missing stdbool
stdbool is added through types.h file.

Change-Id: I317faf322a7e73b706724802d99815ab50e655e2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-01 02:47:17 +00:00
Elyes HAOUAS
411aba22bf security/intel/stm/StmPlatformResource.c: Fix typo on "threads"
Change-Id: Id57a9c689d5fa35cf1b4df9c37b12dd95cb9ef23
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-31 09:30:54 +00:00
Kevin Chiu
00562ebcde mb/google/brya/var/gladios: Update audio codec i2c timing
Adjust audio codec i2c timing to 399 kHz.

BUG=b:262959586
TEST=FW_NAME=gladios emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2f621e3af39fb40ab270c9de35d51dd43147b8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-31 00:35:14 +00:00
Yu-Ping Wu
8112c95a06 Enable VBOOT_VBNV_FLASH for SOC_INTEL_BRASWELL
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL.

Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for
CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However,
there seems to be no particular reason on those platforms. We've dropped
the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that
VBOOT_VBNV_FLASH can be enabled.

VBOOT_VBNV_FLASH is enabled for the following boards:

- facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the
  FW_MAIN_A(CBFS) size reduced by 0x2000.
- google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM.

[1] https://issuetracker.google.com/issues/235293589
[2] commit 6c2568f4f5
    ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config")

BUG=b:235293589
TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected)
TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a
TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a

Change-Id: I46542c2887b254f59245f20b8642b023a7871708
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31 00:34:13 +00:00
Yu-Ping Wu
d9b646d96a mb/facebook/fbg1701: Enlarge COREBOOT region for VBOOT by 64kB
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not
large enough. Therefore, adjust vboot-rw.fmd (which is used only with
VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to
COREBOOT(CBFS) region.

TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected)

Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-12-31 00:33:08 +00:00
Yu-Ping Wu
64b341e722 mb/google/rambi: Drop ChromeOS support
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace
with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early
flash access in romstage:

/usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd:
Cache as RAM area is too full
/usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd:
section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps
section .car.data VMA [00000000fe000000,00000000fe008787]
make: *** [src/arch/x86/Makefile.inc:194:
coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1

More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data
size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected,
then the _bss region will increase by 0x10c8 bytes (for global variables
such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed
0x8000.

Since rambi has reached its AUE (2021-09-01), disable
MAINBOARD_HAS_CHROMEOS and VBOOT configs.

[1] https://issuetracker.google.com/issues/235293589

BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a
TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a

Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-31 00:30:11 +00:00
Bora Guvendik
5f012d0778 fw_config: Fix typo in document
There is no fw_config_probe_one api, change it to
fw_config_probe.

BUG=none
TEST=none

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I916713c038f72a1718be8c9d4e8e21420effbf76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-30 07:14:58 +00:00
John Su
f0de94d436 mb/google/skyrim/var/frostflow: Update I2C setting for touchpad
Update setting for touchpad I2C frequency.
And meet touchpad i2c SPEC (380 ~ 400 kHz).

BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 390.1 kHz

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ied00e43e87404489af2b570206a70b685e554b78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-30 00:46:23 +00:00
Felix Singer
fcdb03d079 {ec,mb}/system76/acpi: Use Printf() for debug prints
Change-Id: Ia5ae30a1ee976b8059936027b28ac56f37279217
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71516
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29 16:30:15 +00:00
Harsha B R
7fb5bf8893 mb/intel/mtlrvp: Add configuration for UART devices
This patch adds below configuration for MTL-RVP UART devices,
Interface -> UART0
PCI -> 0:0x1e:0
Device -> AP UART

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp ito chromeOS
using subsequent patches in the train. UART logs appear on AP console.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29 07:10:55 +00:00
Harsha B R
ec0a85b580 mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVP
Configure GPIO Tier-1 GPE's that defines the route for GPE
events for MTL-RVP. Configure GPE route as below,
PMC_GPE0_DW0 -> GPP_B
PMC_GPE0_DW1 -> GPP_D
PMC_GPE0_DW2 -> GPP_E

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to ChromeOS
using subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29 07:10:46 +00:00
Julius Werner
2bd18edc84 coding_style: Add more guidelines on error handling, die() and assert()
This patch adds a new section to the coding style which codifies
existing practices about how to handle errors and how to use the die()
and assert() macros. Also clean up some references to Linux-specific
facilities that do not exist in coreboot in the adjacent function return
type guidelines, and add a small blurb of documentation to the
definition of the assert() macro itself.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ice37ed9f995a56d69476e95a352209041b337284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-28 05:41:23 +00:00
Maximilian Brune
5cbf45e1e8 src/security/vboot: Fix wrong CONFIG name
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2af3bc9bf9eaf258b9180da5fc5494b21764f379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71518
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28 05:39:32 +00:00
David Wu
872079656b mb/google/brya/var/kuldax: Add wifi sar table
Add wifi sar table for kuldax

BUG=b:248367859
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: I5ade590c739aae391e47e8bb66ee03c086e8d56e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71270
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-28 00:56:00 +00:00
Dinesh Gehlot
d910fec9a6 soc/intel/alderlake: Use common gpio.h include
Replace the intelblocks/gpio.h and soc/gpio.h includes with the
common gpio.h which will include soc/gpio.h which will include
intelblocks/gpio.h

BUG=b:261778357
TEST=Able to build and boot Google/brya.

Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27 15:23:11 +00:00
David Wu
a1b9f0588b mb/google/brya/var/kano: Enable Fast VMode for kano
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log

Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27 15:21:15 +00:00
Harsha B R
a256bd6fe5 mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVP
Add devicetree and GPIO configuration for MTL-RVP
Changes include,
1. Add initial devicetree to support MTL-RVP board & variant
2. Add initial setup for ramstage gpio config

BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
using subsequent patches in the train.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3173c3f32b36d24467431df3652badd70efeab93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27 10:42:55 +00:00
Harsha B R
bd91aa7609 mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP
This patch adds initial bootblock code. This also configures required
GPIOs for early board initialization.

1. Add bootblock file for MTL-RVP
2. Add early gpio config for MTL-P variant in gpio.c

BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform to
ChromeOS with the subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27 10:42:07 +00:00
Subrata Banik
b052683d46 mb/google/rex: Enable PMC IPC config
TEST=Able to build and boot Google/Rex.

Device (PMC)
{
    Name (_HID, "INTC1026")  // _HID: Hardware ID
    Name (_DDN, "Intel(R) Meteor Lake IPC Controller")  // _DDN: DOS Dev
ice Name
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
         Return (0x0B)
    }
    ...
}

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 10:05:46 +00:00
Felix Singer
9df60d36b2 tree/acpi: Replace constant "Zero" with actual number
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:06:47 +00:00
Felix Singer
42efd7f593 {superio,ec}/acpi: Replace constant "Zero" with actual number
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:06:29 +00:00
Felix Singer
fa06bcba06 mainboard/acpi: Replace constant "Zero" with actual number
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27 09:05:56 +00:00
Felix Singer
7b8ac0030c {acpi,arch,soc}/acpi: Replace constant "One" with actual number
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:05:15 +00:00
Felix Singer
dfbb634ae1 mainboard/acpi: Replace constant "One" with actual number
Change-Id: Id1078b14a805eea53d2a7c5a8183a5413f26e115
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71521
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:04:02 +00:00
Felix Singer
ca4b587f95 {superio,ec}/acpi: Replace constant "One" with actual number
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27 09:03:34 +00:00
Subrata Banik
b4767ce169 mb/google/brya/var/marasov: Add DmaProperty for ISH
On Marasov, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on Marasov.

TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.

Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0

After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1

Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27 04:41:33 +00:00
Subrata Banik
3a60e5c827 drivers/intel/ish: Add ADL-P ISH DID
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is
added into SSDT.

With this patch:
   Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-27 04:41:12 +00:00
Subrata Banik
11e1950d26 mb/google/brya/var/marasov: Remove ISH firmware-name
For marasov, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.

TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.

Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
2022-12-27 04:40:56 +00:00
Elyes Haouas
1e9344481a sio/winbond/w83627hf/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntax
Replace Divide (a,b,c,d) with:
  c = a % b
  d = a / b

Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 20:43:25 +00:00
Felix Singer
8171364d06 tree/acpi: Replace Divide(a,b,c,d) with ASL 2.0 syntax
Replace `Divide (a, b, c, d)` with these instructions:

  c = a % b
  d = a / b

Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-26 19:57:44 +00:00
Felix Singer
eaa31d95c2 mb/lenovo/s230u/acpi: Replace Not(a, b) with ASL 2.0 syntax
Replace `Not (a, b)` with `b = ~a`.

Change-Id: I0f18119c8e91222e59a56b8509f12c6ece6d04ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71514
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 19:57:09 +00:00
Felix Singer
c87c1abffb tree/acpi: Replace Not(a) with ASL 2.0 syntax
Replace `Not (a)` with `~a`.

Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 19:56:04 +00:00
Subrata Banik
25b717ad84 drivers/pc80/vga: Add NULL check for vga_line_write()
This patch ensures vga_line_write() returns if the argument 1
(aka output string) is NULL.

TEST=Able to build and boot Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-26 15:55:28 +00:00
Elyes Haouas
cfdd488440 sio/acpi/pnp.asl: Replace Not(a) with ASL 2.0 syntax
Change-Id: Icbd2ab736b9fc3300ee82896c31b373fe92e1d54
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71509
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 11:45:10 +00:00
Elyes Haouas
e007893a8e nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntax
Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 08:53:07 +00:00
Elyes Haouas
2369818c3d nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntax
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 08:52:19 +00:00
Elyes Haouas
9ede493c73 nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntax
Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 08:51:55 +00:00
Elyes Haouas
f451bfb1a5 soc/intel/baytrail/acpi: Replace Index(a, b) with ASL 2.0 syntax
Change-Id: Iab611cda1083da4378a6e509d11ea26bdbb45edd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71503
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 08:51:39 +00:00
Elyes Haouas
ffc0d2455c soc/intel/braswell/acpi: Replace Index(a, b) with ASL 2.0 syntax
Change-Id: I7da6ee3c5bce6b32874e59ad46290b86db8f97c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71502
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26 08:50:46 +00:00
Dinesh Gehlot
14a0876de8 soc/intel/meteorlake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled()
functions combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.

TEST=Able to build and boot without any regression seen on MTL.

Port of 'commit 50134eccbd ("soc/intel/alderlake: Make use
of is_devfn_enabled() function")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-25 15:26:03 +00:00
Dinesh Gehlot
d4f2d14d52 soc/intel: Move max speed API to common
This patch moves API "smbios_cpu_get_max_speed_mhz()"
to common code from board specific. This API was made
generic in 'commit d34364bdea ("soc/intel/alderlake:
Utilize `CPU_BCLK_MHZ` over dedicated macro")'

BUG=NONE
TEST=Boot and verified that SMBIOS max speed value is
correct on brya and rex.
(brya) dmidecode -t : "Max Speed: 4400 MHz"
(rex) dmidecode -t : "Max Speed: 3400 MHz"

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I87040ab23319097287e191d7fc9579f16d716e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25 15:24:36 +00:00
Elyes Haouas
2179c7fdb7 arch/riscv: Use 'enum cb_err'
Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25 15:09:48 +00:00
Elyes Haouas
9523e3b790 arch/x86: Use 'enum cb_err'
Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-25 15:09:16 +00:00
Martin Roth
70191da272 util/docker: Update setuptools to get dtc building
python3-setuptools installed via apt-get is not currently working to
build dtc from git.kernel.org.  Falling back to setuptools version
58.2.0 allows it to build again.

The failure message was:
/usr/lib/python3/dist-packages/setuptools/installer.py:27:
SetuptoolsDeprecationWarning: setuptools.installer is deprecated.
Requirements should be satisfied by a PEP 517 installer.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I04cb6d776c3748f9a4b0cfc4ffd4f46458560d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71500
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25 13:22:13 +00:00
Subrata Banik
265dc1d793 util/mb/google: Add support for rex
Add the file templates for creating a new variant of Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4abca1f999accc008eb2549fcc13199b8d9bdc7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24 23:39:08 +00:00
zhaojohn
92d49da163 mb/google/rex: Enable DPTF functionality for Rex
Enable DPTF functionality for Meteor Lake Rex board.

BUG=b:262498724
TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board.

Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24 23:37:56 +00:00
Tracy Wu
387ec919d9 soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE
With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.

BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-24 23:36:59 +00:00
Johnny Li
2a12b6a9a4 mb/google/volteer/eldrid: Correct DDR4 SPDs for Eldrid
Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017.

DRAM Part Name    ID to assign
H5AG36EXNDX017    0 (0000)

BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If248714088835eb5dd48fa12223c273199297228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24 23:35:44 +00:00
Johnny Li
7866193eee spd/ddr4: Correct Hynix ddr4 part number from H5AG36EXNDX019 to H5AG36EXNDX017
Correct Hynix ddr4 part number H5AG36EXNDX019 to H5AG36EXNDX017 by Hynix Memory spec.

BUG=b:236739240
BRANCH=Volteer
TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully.

Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I6195fa1402691afc303f5223de48f552660cd97f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71159
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24 23:35:31 +00:00
David Wu
cedd4d14f4 mb/google/brya/var/zydron: Use SSFC for mipi instead of fw_config
Kano didn't use SSFC in mass production, however
Zydron needs SSFC for 2rd source mipi instead of fw_config.

BUG=b:262939431
TEST=Boot to OS and check functional with ov2740/hi556 camera.

Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-12-24 19:11:22 +00:00
Karthikeyan Ramasubramanian
716c8f0711 soc/amd/mendocino: Split the EFS from the AMDFW body
Contents of unsigned AMDFW in RW sections are verified twice in PSP
verstage - first time by vboot verifying the firmware body, second time
by CBFS verification while the file is loaded to update PSP about the
boot region. This redundant verification adds to boot time. Minimize the
redundancy by splitting the EFS header from the AMDFW body and keep them
as 2 separate CBFS files. This helps to improve the boot time by another
25 ms.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe boot time
improvement of ~25ms.
Before:
   6:end of verified boot              363,676 (16)
  11:start of bootblock                641,392 (277,716)
After:
   6:end of verified boot              361,655 (16)
  11:start of bootblock                616,967 (255,312)

Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24 19:10:17 +00:00
Karthikeyan Ramasubramanian
ecb4e31531 util/amdfwtool: Write EFS and AMDFW body in separate files
Add support to write EFS and AMDFW body to separate files. This is done
through passing an optional --body-location parameter to the amdfwtool.
If that option is not passed, then EFS will be written in the same file
as the AMDFW body. This will help to keep the minimum data to be
loaded/mapped from CBFS in PSP verstage.

BUG=None
TEST=Build and boot to OS in Skyrim.

Change-Id: I79325c81394cf8a0c663752d094adf6660896127
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24 19:09:59 +00:00
Subrata Banik
7c55aab199 mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODL
BUG=b:263413949
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24 13:25:41 +00:00
Subrata Banik
9a97df3010 mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SEL
BUG=b:263412235
TEST=Able to build and boot Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24 13:25:27 +00:00
Eric Lai
beb2826ffd mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filename
Use get_wifi_sar_fw_config_filename to remove the duplicate code.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I04176fee373e534d42c72506df73a092ad55e65b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:51:39 +00:00
Eric Lai
3c53300002 mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filename
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:51:15 +00:00
Eric Lai
bffa9066fa mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filename
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:50:54 +00:00
Eric Lai
51f1822421 mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filename
Use get_wifi_sar_fw_config_filename to remove the duplicate code.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:50:25 +00:00
Eric Lai
8cb2f185d1 vc/google/chromeos: use fw_config field to return sar filename
Use fw_config field to return sar filename instead of fw_config probe.
Return filename unconditionly because the sar_id must be valid in
CBI. If invalid sar_id, the file won't exist in CBFS by design.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:50:13 +00:00
Eric Lai
9f2faca246 lib: add stub for fw_config_get_field
Return UNDEFINED_FW_CONFIG with disabled fw_config.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0d31ff3ba7706039c622bd1ec825d216a0f21fe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24 05:50:00 +00:00
Sergii Dmytruk
4ee03170e0 Revert "security/tpm/: turn tis_{init,open} into tis_probe"
This reverts commit d43154486d.

From CB:68991: This causes CraterLake boot up process to die.
Investigation in progress.

Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: siemens-bot
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23 21:31:11 +00:00
Sergii Dmytruk
025d20eaeb Revert "drivers/pc80/tpm: probe for TPM family of a device"
This reverts commit 907a81e2a7.

This reportedly breaks TPM and measured boot flow completely.

Change-Id: Id0d98ecc7807faa1617ad16dc9a24343c5a66b06
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23 21:30:54 +00:00
Matt DeVillier
86425c81af mb/google/poppy: Use runtime detection for touchscreens/digitizers
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens/digitizers.
This removes non-present devices from the SSDT and relieves the OS of
the burden of probing.

BUG=b:121309055
TEST=build/boot Windows/linux on all poppy variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 20:58:57 +00:00
Matt DeVillier
1c2f5cea7e mb/google/poppy: Set touchpad/touchscreen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 20:58:41 +00:00
Matt DeVillier
74edda99dd mb/google/poppy: Implement touchscreen,digitizer power sequencing
For touchscreens/digitizers on poppy variants, drive the enable
GPIO high and hold in reset in romstage, then release from reset in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens/digitizers during ACPI SSDT generation (enabled in a
subsequent commit).

TEST=tested with the rest of patch train

Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-23 20:58:28 +00:00
Werner Zeh
9d40a0be2f mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7
Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz
leads to poor signaling. Therefore limit the I2C speed to 100 kHz for
this bus. In addition, add a generic I2C device with 100 kHz bus speed
to the devicetree so that the OS will not switch to higher clock rates,
too.

Test= Measure the I2C signals at coreboot and OS runtime and ensure the
clock is always at 100 kHz.

Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 15:56:50 +00:00
Werner Zeh
a1a3be1df8 mb/siemens/mc_apl7: Init I2C controller before PTN3460 is initialized
When PTN3460_EARLY_INIT is selected, the PTN3460 (DP-2-LVDS-bridge) will
be initialized before all devices are initialized. This is necessary to
get a valid EDID data set into the PTN3460 before the graphic controller
is initialized in order to be able to show a splash screen.

For ptn3460_init() to work properly the I2C bus this bridge is connected
to needs to be initialized. As this I2C bus initialization would be done
too late in the normal flow, it needs to be called here explicitly
before ptn3460_init() to initialize the  I2C bus with the needed
conditions. Otherwise the default I2C settings of the controller will be
used which results in a clock rate too high for this mainboard.

Test=Measure I2C bus signals and make sure that the clock is <= 400 kHz.

Change-Id: I1775fb7c2d29f765224d0e7c7ff9fcd4dbf847c5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71226
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 15:55:40 +00:00
Arthur Heymans
4d75dbd1c1 cpu/x86: Set up a separate stack for APs
APs use a lot less stack, so set up a separate stack for those in .bss.

Now that CPU_INFO_V2 is the only code path that is used, there is no
need to align stacks in c_start.S.

Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-23 14:29:01 +00:00
Tim Chu
96b49b5acb soc/intel/cmn/block/pmc: Add pmc_or_mmio32 utility function
Change-Id: I5f9845dd3ea098d990710eaaa2d5db495f876cdd
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 14:22:57 +00:00
Matt DeVillier
ef72defdce soc/intel/broadwell: Add Kconfig option to hide Intel ME
On broadwell devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.

Change-Id: If670d548c46834740f4e21bb2361b537807c32bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23 14:21:47 +00:00
Matt DeVillier
52c553e838 sb/intel/lynxpoint: Add Kconfig option to hide Intel ME
On lynxpoint devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.

Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-23 14:20:39 +00:00
Subrata Banik
42f704a967 soc/intel/meteorlake: Add DPTF ACPI Device IDs into header file
This patch adds DPTF ACPI Device IDs into the header file
(soc/dptf.h).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib78258ac1b9a5252bb5e6fae4d7cc30a3f103e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71126
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 13:01:03 +00:00
Subrata Banik
e9ac9f97e8 soc/intel: Drop SoC specific DPTF implementation
This patch drops the SoC specific implementation as DPTF driver can
now fillin those platform specific data using SoC specific macros.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If65976f15374ba2410b537b1646ce466ba02969b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-23 13:00:30 +00:00
Subrata Banik
af20628a48 drivers/intel/dptf: Implement API to fill DPTF platform info
This patch fills in a generic platform info structure based on the
inputs from the SoC dptf header file (soc/dptf.h).

It will help to make things common and drop unnecessary back and
forth call between common code and SoC code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3521882495485cef686655abd65337515bae5faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 12:55:59 +00:00
Yidi Lin
63d26b82a3 soc/mediatek: Add DEVAPC_DEBUG option
Add DEVAPC_DEBUG option and set this option to disabled by default.
This option prevents DEVAPC log flooding during the boot process. Enable
this option when we need to debug DEVAPC issues.

TEST=DEVAPC log is disabled by default.

Change-Id: I26bc0378b8a766c6a8cc4903d64a921c3e96b93f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 12:55:22 +00:00
Liju-Clr Chen
aa9bb44504 mb/google/geralt: Pass SD card detect GPIO to payloads
1. Add an option for SD card initialization.
2. If CONFIG SDCARD_INIT is configured, pass SD card detect GPIO to
   payloads for SD card detection and initialize MSDC for SD card
   configuration.

BUG=b:244250437
TEST=build pass

Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I2d3683eb673f438c9190c11d4679a3ca97c76a98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71136
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-23 12:54:42 +00:00
Felix Singer
d252776668 tree: Replace And(a,b) with ASL 2.0 syntax
Replace `And (a, b)` with `a & b`.

Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 10:18:55 +00:00
Felix Singer
35e65a8bc3 tree: Replace And(a,b,c) with ASL 2.0 syntax
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.

Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 10:18:48 +00:00
Felix Singer
86bc2e708d tree: Replace Or(a,b,c) with ASL 2.0 syntax
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where
possible.

Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 10:17:34 +00:00
Felix Singer
372573eaff tree: Replace ShiftLeft(a,b) with ASL 2.0 syntax
Replace `ShiftLeft (a, b)` with `a << b`.

Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 08:30:39 +00:00
Felix Singer
3c9291b335 tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntax
Replace `ShiftLeft (a, b, c)` with `c = a << b`.

Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 08:30:09 +00:00
Felix Singer
034920c1d4 tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntax
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was
simplified to just `a >> b`.

Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23 03:16:35 +00:00
Kyösti Mälkki
100f92c54f mb,x86/smm: Disable unused IO traps
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented
the IO trap handler.

Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 03:09:20 +00:00
Martin Roth
4c61294498 Docs: Add page for external resources
This is a page to add links to other sites that have firmware related
material, or other things that are of interest to the community.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Icf411e67bf865426b1a3b99ecbabed2302a7b738
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-23 02:54:48 +00:00
Matt DeVillier
3d352a7218 mb/google/poppy/nocturne: Fix touchscreen reset GPIO config
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an
internal pull-down, which puts it in a state of contention when the
reset pin is released / set to high. Fix this by changing the reset
GPIO to PAD_CFG_GPO like all other poppy variants use for the
touchscreen reset.

TEST=build/boot nocturne, touchscreen still works.

Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 00:45:02 +00:00
Matt DeVillier
7f2c0bf838 mb/google/sarien: Add default fmap for non-ChromeOS builds
Test: build/boot google/sarien with non-ChromeOS build, edk2 payload.
Linux 5.15, Windows 11 tested.

Change-Id: Ibc1857e6b120b0bb827ed610981c4d2bf8f78d1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:35:54 +00:00
Matt DeVillier
c5ec497bbc mb/google/hatch: Use runtime detection for touchscreens/digitizers
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple hatch variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 00:22:40 +00:00
Matt DeVillier
251d443e8b mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:22:03 +00:00
Matt DeVillier
4534ed7a62 mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreens
Some ELAN touchscreens were missing the entries for the enable GPIO
and associated delays. Add them to variants with ELAN0001 touchscreens
missing the entries.

TEST=tested with rest of patch train

Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-23 00:21:06 +00:00
Matt DeVillier
525c61f74e mb/google/hatch: Implement touchscreen power sequencing
For touchscreens on hatch variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23 00:19:06 +00:00
Matt DeVillier
c0edb925e6 mb/google/hatch: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:15:45 +00:00
Matt DeVillier
63cde524b7 mb/google/poppy/rammus: disable USB xDCI
With xDCI enabled, the right USB-C port does not work for USB data.
Additionally, it was disabled in stock ChromeOS firmware.

TEST=build/boot rammus, confirm right USB-C port works for booting,
under OS in Windows/Linux.

Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:14:56 +00:00
Matt DeVillier
2328144577 mb/google/zork: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all
touchpad functions work correctly.

Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:12:53 +00:00
Matt DeVillier
74efac1a3f mb/google/volteer: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad
functions work correctly.

Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23 00:11:22 +00:00
Sean Rhodes
823a329bb8 soc/intel/apollolake/acpi: Remove STOM from ACPI
This should only contain resources that the PCI domain uses. Stolen
memory prevents the PCI domain from allocating anything where it is.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 21:17:57 +00:00
Sean Rhodes
a17864c2c9 soc/intel/apollolake/acpi: Improve comments and unify code word spelling
ACPI: Improve comments and unify code word spelling

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1efbe930d0b8daec7c7bd2c1d84a4a3a5cad2ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 21:17:40 +00:00
Sean Rhodes
8264122122 soc/intel/apollolake/acpi: Tidy the Legacy video RAM
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie6572638c6bbe910745de55afa44458fb6b8db9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66240
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 21:17:33 +00:00
Sean Rhodes
197cfe03d5 soc/intel/apollolake/acpi: Tidy the PCI Memory Region
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8997f9c111142a908b60675023d1a7dd86d3632a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66238
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 21:17:26 +00:00
Sean Rhodes
de19bc372b soc/intel/apollolake/acpi: Add bits of TOLUD register
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-22 21:17:16 +00:00
Sean Rhodes
759aa17e79 soc/intel/apollolake/acpi: Remove TOUUD as it is not used
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 21:17:04 +00:00
Sean Rhodes
a49cd32da0 soc/intel/apollolake/acpi: Add PDRC for PCIX and ACPI to allow use of MMCONF
The current implementation of the MCRS had several issues with BARs
and MMCONF not being available:

    [    0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window
    [    0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit]
...
    [    0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138300] PCI: not using MMCONFIG
    [    0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
    [    0.149679] PCI: not using MMCONFIG
    [    0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.

This new MCRS, tested on the Star Lite Mk IV, resolves these issues:

    [    0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb
    [    0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit]
    ...
     [    0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
 0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.138460] PCI: not using MMCONFIG
    [    0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
    [    0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-22 21:16:13 +00:00
Matt DeVillier
6a803bfae6 mb/google/reef: update ACPI HID/CID for Synaptics touchpad
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on coral, verify all touchpad
functions work correctly.

Change-Id: I161eb953bf8bceb353cf43803ee948c522928892
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:44:51 +00:00
Matt DeVillier
f75172fdcc mb/google/poppy: update ACPI HID/CID for Synaptics touchpad
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad
functions work correctly.

Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:44:18 +00:00
Matt DeVillier
2793716910 mb/google/hatch: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad
functions work correctly.

Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:43:12 +00:00
Matt DeVillier
f39e105deb mb/google/kahlee: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad
functions work correctly.

Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:42:33 +00:00
Matt DeVillier
148207a8b7 mb/google/hatch: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad
functions work correctly.

Change-Id: Icb552caa69428908e5e3342139b578a145fa2797
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:41:54 +00:00
Matt DeVillier
61c2446142 mb/google/guybrush: update ACPI HID/CID for Synaptics touchpad
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all
touchpad functions work correctly.

Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:41:34 +00:00
Matt DeVillier
2f5aec4b50 mb/google/dedede: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad
functions work correctly.

Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:40:56 +00:00
Matt DeVillier
e9f0ed5960 mb/google/brya: update ACPI HID/CID for Synaptics touchpads
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).

TEST=untested on brya, but tested under Windows/Linux on all other
boards in the tree using Synaptics touchpads.

Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:40:17 +00:00
Matt DeVillier
ba9f0c3817 mb/google/volteer: Add missing audio codec to HDA probe
Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the
baseboard, but missing from the HDA device probe list in the variant
overridetrees, preventing it from being detected at boot.

TEST=build/boot lindar, verify audio codec identified and HDA device not
disabled by fw_config.

Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:39:12 +00:00
Matt DeVillier
a0e32aafee mb/google/reef: Use runtime detection for touchscreens
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple reef variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I8c90074515b1c7d3ab742768d7bbd904fec256d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:38:05 +00:00
Matt DeVillier
48894ea620 mb/google/reef: Set touchpad/screen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I1000df10eea5670bf1bc8d04c736150b6a5e26a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:37:33 +00:00
Matt DeVillier
beb58a93cf mb/google/reef: Implement touchscreen power sequencing
For touchscreens on reef variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit). As the GPIOs are
already correct in ramstage, only the romstage ones need to be set.

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:36:42 +00:00
Matt DeVillier
40c8cc9cde mb/google/reef: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 20:35:01 +00:00
Matt DeVillier
0d54a65819 mb/google/volteer: Use runtime detection for touchscreens
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.

BUG=b:121309055
TEST=build/boot Windows/linux on multiple volteer variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.

Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:34:03 +00:00
Matt DeVillier
0bffd0a1ae mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:32:25 +00:00
Matt DeVillier
7ed6130428 mb/google/volteer: Implement touchscreen power sequencing
For touchscreens on volteer variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:31:48 +00:00
Matt DeVillier
7413815a01 mb/google/volteer: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 20:27:21 +00:00
Sean Rhodes
1263622106 mb/starlabs/*: Bind console serial output to EDK2_DEBUG
Configure the UART port but only enable UART debug for EDK2
debug builds.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 19:07:40 +00:00
Jonathan Zhang
8ab5e15aca inc/dev/pci_def.h: add definitions for RCEC EA Ext. Capbility
Root Complex Event Collector Endpoint Association Extended
Capability is defined in section 7.9.10 of PCIe 5.0 spec.

Add its Extended Capability ID, association bitmap for RCiEPs
register, and RCEC associated bus numbers register.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 19:06:49 +00:00
Tim Chu
13c44457f1 soc/intel/xeon_sp: Move codes to support new PCH
Different PCHs have different definitions for registers. Here create
a lbg folder and move lbg specific codes to this folder so that we
can add new PCH code under xeon_sp folder.

* Create lbg folder and move lbg specific codes from pch.c to soc_pch.c
  under lbg folder.
* Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg
  folder.
* Rename gpio.c to soc_gpio.c and move to lbg folder.
* Move pcr_ids.h to lbg folder.
* Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg
  folder.
* Create and revise makefile for files under lbg folder.

TEST=Can boot into OS on OCP Delta Lake.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 19:05:13 +00:00
Jonathan Zhang
cfad59a516 doc/mb/ocp/deltalake: add section on how to work on coreboot
Update Delta Lake documentation to add some clarification.

Add a section on how to work on coreboot for the Delta Lake server.

Change-Id: Id756ee0a09cdcd1200752a03e980441db1537ad1
Signed-off-by: Jonzhang Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22 18:55:20 +00:00
Dinesh Gehlot
36b6b055bd soc/intel/meteorlake: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port

TEST=Build and Boot verified on google/rex

Port of 'commit 6e52c1da4a ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 18:54:18 +00:00
Elyes Haouas
9f47f958b3 drivers/intel/fsp2_0: Don't include <commonlib/bsd/compiler.h>
<commonlib/bsd/compiler.h> is automatically included in all
compilation units by the build system.
(see Documentation/contributing/coding_style.md)

Change-Id: I09ed0c5eb2054c3add026f200c0fd3f609f73197
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67905
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 18:53:07 +00:00
Jonathan Zhang
eacd74f223 drivers/ocp: add VPD processing framework
Add VPD processing framework to be shared by OCP mainboards:
* define VPD configuration items in vpd.h.
* add helper functions:
** get_bool_from_vpd()
** get_int_from_vpd_range()

Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22 18:52:00 +00:00
Jonathan Zhang
fb2ebbced7 soc/intel/xeon_sp: Lock down LPC configuration
For LPC, set BIOS interface lock.

Also set the LPC BIOS control to match the SPI BIOS control settings.
BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config
option is set.

Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22 18:48:45 +00:00
Marx Wang
39ede0af15 soc/intel/alderlake: Add Raptor Lake device IDs
Add system agent ID for RPL QDF#Q2MB/Q2PS

TEST=able to build coreboot successfully

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22 18:47:50 +00:00
Chris.Wang
174d2635fd mb/skyrim/var/frostflow: enable dptc tablet mode switch
add dptc power parameter for tablet mode

sustained_power_limit_mW_tablet : 12w

BUG=b:257187831
BRANCH=none
TEST= validate the parameter changes for each mode by AGT

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I22d3f9c79a1eaaccfbef3766019516edb3523964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70674
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-12-22 16:03:33 +00:00
Julius Werner
9a9b2778a1 coreboot_tables: Make existing alignment conventions more explicit
There seem to be some recurring vague concerns about the alignment of
coreboot table entries. While the existing implementation has been
producing tables with a well-defined alignment (4 bytes) for a long
time, the code doesn't always make it very clear. This patch adds an
explicit constant to codify that alignment, assertions to check it after
each entry, and adds explicit padding to the few entry structures that
were relying on compiler padding to return a correct sizeof() value.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaeef29ef255047a855066469e03b5481812e5975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2022-12-22 15:34:28 +00:00
Subrata Banik
ad6c407927 soc/intel/meteorlake: Disable L1 substates for PCIe compliance test mode
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

This patch is backported from
commit 8c46232005 (soc/intel/alderlake:
Disable L1 substates for PCIe compliance test mode).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-22 08:20:21 +00:00
Subrata Banik
2585a999bb soc/intel: Set use_eisa_hids based on DPTF_USE_EISA_HID config
This patch avoids hardcoding to the `use_eisa_hids` variable instead
relying on the SoC config to choose if the SoC platform supports
EISA HID.

If any SoC platform has the support then the `use_eisa_hids` variable
would be set to `true` based on the selection of `DPTF_USE_EISA_HID`
config.

Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.

Ideally, the platform prior to Tiger Lake would set `use_eisa_hids`
to `true`  and platform posts that would set `use_eisa_hids` to
`false`.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:07:12 +00:00
Subrata Banik
4225a796fa soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTF
This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL
platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:06:48 +00:00
Subrata Banik
dd4acf643f drivers/intel/dptf: Add new config for EISA HID support
This patch adds config to let SoC users (config) to choose if EISA HID
is supported. All SoC config would like to support EISA HID need to
select `HAVE_DPTF_EISA_HID` config.

Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf64f74c447b28665d31a64181c33df882d5d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71108
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:06:21 +00:00
Subrata Banik
fbdccebb66 soc/intel/tigerlake: Move DPTF ACPI Device IDs into header file
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

TEST=Able to build and boot Google/Volteer.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:05:54 +00:00
Subrata Banik
fd8c596c40 soc/intel/jasperlake: Move DPTF ACPI Device IDs into header file
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibb31ab29c803dde70ef9ccf2b7c7c2ca0845b568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71106
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:05:43 +00:00
Subrata Banik
e4aee2b178 soc/intel/cannonlake: Move DPTF ACPI Device IDs into header file
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

TEST=Able to build and boot Google/Hatch.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7a9218a41825d2fa40a1c1b96a333465b7f617c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71105
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:05:18 +00:00
Subrata Banik
4b0c8ccb14 soc/intel/apollolake: Move DPTF ACPI Device IDs into header file
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

TEST=Able to build and boot Google/Reef.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:05:02 +00:00
Subrata Banik
80ed5012ef soc/intel/alderlake: Move DPTF ACPI Device IDs into header file
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22 08:04:05 +00:00
Subrata Banik
113d937c80 soc/intel/elkhartlake: Add DPTF ACPI Device IDs into header file
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia4c3f1dbca2c0099cbf00137008c1aa1bcb196b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71125
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 08:03:45 +00:00
Subrata Banik
9ea73d1999 drivers/intel/dptf: Add soc_ prefix for get_dptf_platform_info()
This patch makes the SoC specific callback code more readable by adding
`soc_` prefix into the `get_dptf_platform_info()`.

In nutshell this patch renames `get_dptf_platform_info()` to
`soc_get_dptf_platform_info()`.

TEST=Able to build Google/Rex without any compilation issue.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-22 08:03:16 +00:00
Sridhar Siricilla
193f39bfd5 soc/intel/meteorlake: Update scaling factor MTL big core
The patch updates the scaling factor for MTL big core.

TEST=Build the Rex code

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ife069fb29f4e913c5ef1af1f719b3392a70c55c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70355
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22 06:40:56 +00:00
Yidi Lin
78b29f4567 soc/mediatek: Move dapc_init to common
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this
function to common/devapc.c

TEST=emerge-corsola coreboot; emerge-cherry coreboot;
     emerge-geralt coreboot
TEST=devapc log is shown as expected and the system boots to kernel

Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-22 04:52:00 +00:00
Elyes Haouas
d7326282f9 lib/device_tree.c: Change log level message
Move a "NOTE" message from BIOS_DEBUG to BIOS_NOTICE log level.

Change-Id: If92c1ccb5b10a4b29a5006a41ebd0855294f354e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22 03:27:34 +00:00
Elyes Haouas
9a1d01f48e payloads/libpayload/arch/x86/rom_media.c: Change log level message
Move a warning message from BIOS_INFO to BIOS_WARNING log level.

Change-Id: I4210901a183b54e47fa62a6146ce754c544aab2c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71157
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22 03:27:02 +00:00
Elyes Haouas
16c2ea3bcb nb/intel/sandybridge/raminit_common.h: Add needed <device/dram/ddr3.h>
Change-Id: I059e94ef46fdc959a6e37365eb335409698b987a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22 03:26:00 +00:00
Wisley Chen
ed0e2bd5ee mb/google/nissa/var/yaviks: Extend sd_hold for touchpad/touchscreen
Extend sd_hold to meet touchpad/touchscreen SPEC.

touchscreen:
  tHD > 0.2 us
touchpad:
  0.3 us < tHD < 0.9 us

After applied the change, the tHD meets reqirement.
touchscreen:
   0.056 us -> 0.28 us
touchpad:
   0.056 us -> 0.384 us

BUG=b:263340540
TEST=build and measure the timing meet SPEC

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22 00:50:33 +00:00
Leo Chou
a86af49b9d mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error
Configure eMMC DLL tuning values for Pujjo board Kioxia sku.

BUG=b:261676386
TEST=Use the value to boot on Pujjo successfully.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I46991f26571771620dcd94b90e1112484ade63bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-12-22 00:48:20 +00:00
Dinesh Gehlot
0d76a30767 soc/intel/meteorlake: Select INTEL_GMA_OPREGION_2_1
Meteor Lake supports IGD Opregion version 2.1.

BUG=b:190019970 (for alderlake)
BRANCH=None
TEST=Build and Boot verified on google/rex

Port of 'commit 81d367feee ("soc/intel/alderlake:
Select INTEL_GMA_OPREGION_2_1")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I89e42b481834ed5ab35909b31b76215eaf8c7b36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21 21:34:22 +00:00
Elyes Haouas
a012136fc8 treewide: Remove duplicated includes
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>.

Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-21 21:33:40 +00:00
Sridhar Siricilla
d13a57915d security/vboot: Drop assert call from vbnv_udc_enable_flag()
It's true that vbnv_udc_enable_flag() is called after vbnv_init()
(that's why the assertion was added). However, the former is called in
the ramstage, while the latter in verstage. This means that
vbnv_initialized will be false in ramstage, which leads
to the assertion failure:

[EMERG]  ASSERTION ERROR: file 'src/security/vboot/vbnv.c', line 88

Since the ctx->nvdata will be restored in ramstage (by vb2api_reinit()),
simply remove the assertion. So, the patch drops assert call from
vbnv_udc_enable_flag() function.

TEST=Verify Rex system boots to OS without assert error.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I49022155239febd5c5be5cf2c5eca2019ca61c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-21 18:52:50 +00:00
Nick Vaccaro
4af3df35e5 mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as kano is using a converged firmware image.

BUG=b:253337338
BRANCH=firmware-brya-14505.B
TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
disable hardware write protect and software write protect,
flash and boot kano in end-of-manufacturing mode to kernel.

Cq-Depend: chrome-internal:5246998, chromium:4119763
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>

Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 18:48:36 +00:00
Sergii Dmytruk
907a81e2a7 drivers/pc80/tpm: probe for TPM family of a device
At the moment this is to handle the situation when device ID is the
same for TPM1 and TPM2 versions of a device.  Later this TPM family will
be returned to the caller.

Change-Id: I5464771836c66bcc441efb7189ded416b8f53827
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69023
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 14:50:13 +00:00
Sergii Dmytruk
df853501f8 drivers/spi/tpm: verify device supports TPM2
This is to handle the situation when device ID is the same for TPM1 and
TPM2 versions of a device.

Change-Id: Ib2840a21b3be8928d39570281f86a0e26b38b5f9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69022
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 14:48:59 +00:00
Sergii Dmytruk
d43154486d security/tpm/: turn tis_{init,open} into tis_probe
Init was always followed by open and after successful initialization we
need only send-receive function, which is now returned by tis_probe on
success further reducing number of functions to export from drivers.

Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68991
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 14:48:00 +00:00
Sergii Dmytruk
86f845ad0d drivers/i2c/tpm: splice tpm_vendor_specific struct
Move `locality` field to `struct tpm_inf_dev` and put the rest directly
into `tpm_chip`.

Change-Id: Ic3644290963aca9f8dc7cd8ef754352865ef8d2c
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-21 14:46:54 +00:00
Matt DeVillier
bf3c648fa7 soc/intel/skl; mb/google/eve,poppy: Update NHLT methods
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309.

Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514
codecs to program the render and feedback slot numbers as appropriate.

TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify
audio functional with both Google project campfire drivers as well as
coolstar's AVS audio drivers.

Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21 14:00:13 +00:00
Matt DeVillier
ca342e1082 lib/nhlt, soc/intel/skl: Update NHLT to program feedback config
Adapted from WIP (and abandoned) patch CB:25334, this patch:

1. Ensures SSP endpoint InstanceId is 0
2. Adds capability_size parameter at the end of the nhlt
3. Adsd more config_type enum values to accommodate feedback stream
4. Programs virtual_slot values for max98373, max98927,
   and rt5514 nhlt files
5. Adds NHLT feedback_config parameters

Default feedback configs are added here to the max98373, max98927, and
rt5514 codecs; in a follow-on patch, these will be overridden at the
board level.

TEST=tested with subsequent patch

Change-Id: I59285e332de09bb448b0d67ad56c72a208588d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21 13:57:48 +00:00
Jan Samek
343644006f mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0
Remove the PSE TSN GbE device #0 as it's unused on the board and not
visible during the PCI enumeration.

Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:51:45 +00:00
Jan Samek
12b2a3a477 mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaks
Contrary to mc_ehl2, which this variant is based on, this board
doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the
attempts to modify the bridge's registers unnecessary.

Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:50:25 +00:00
Martin Roth
37cb922374 util/testing: Disable tegra and gitconfig tests until they're fixed
Both the tegra builds and the gitconfig tests are causing issues.
They're disabled until someone fixes them.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1ed272e3579a2e7cdd6b58df24e719410d47082c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-21 13:48:14 +00:00
Matt DeVillier
0c3806db69 mb/google/octopus: Use runtime detection for touchscreens/digitizers
Switch from using ACPI "probed" flag to "detect" flag for all i2c
touchscreens and digitizers. This removes non-present devices from the
SSDT and relieves the OS of the burden of probing.

Test: build/boot Windows/Linux on various octopus variants, verify
touchscreens/digitizers functional, dump ACPI tables and verify only i2c
devices actually present on the board have entries in the SSDT.

Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:42:30 +00:00
Matt DeVillier
dc8074560c mb/google/octopus: Set touchpad/screen IRQs to LEVEL vs EDGE
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.

TEST=tested with rest of patch train

Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:41:22 +00:00
Matt DeVillier
34ffa64ba8 mb/google/octopus: Implement touchscreen/digitizer power sequencing
For octopus variants with a touchscreen/digitizer, drive the enable and
reset GPIOs high in romstage, then disable the reset GPIOs in ramstage.
Where available, only set the GPIOs for SKUs which have a touchscreen.
This will allow coreboot to detect the presence of i2c touchscreens
during ACPI SSDT generation (implemented in a subsequent commit).

TEST=tested with rest of patch train

Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:40:31 +00:00
Matt DeVillier
53bf72b131 mb/google/octopus: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.

TEST=tested with rest of patch train

Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:38:06 +00:00
Karthikeyan Ramasubramanian
0822ce8b08 soc/amd/common/psp_verstage: Report previous boot status
Add support to report previous PSP boot failure to verified boot. This
is required specifically on mainboards where the signed AMDFW blobs are
excluded from vboot verification.

BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Corrupt either
one of SIGNED_AMDFW_A/B sections or both the sections to ensure that the
appropriate FW slot is chosen.

Cq-Depend: chromium:4064425
Change-Id: Iada0ec7c373db75765ba42cb531b16c2236b6cc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70382
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:37:32 +00:00
Karthikeyan Ramasubramanian
7b49d1b198 vc/amd,soc/amd/mendocino: Add SVC_CMD_GET_PREV_BOOT_STATUS
Add an SVC command to get the previous boot status. If there is any
pre-x86 boot failure in the previous boot cycle, PSP stores it in warm
reset persistent register and triggers a warm reset. PSP verstage on the
subsequent boot gets the previous boot status and reports any failure to
the vboot before a FW slot is selected.

BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure
scenario by corrupting certain firmware blobs and observe that PSP
reports the failure boot status. On a normal boot, observed that PSP
reports successful boot.

Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 13:36:25 +00:00
Elyes Haouas
a0ff874489 payloads/seabios: Update stable from 1.16.0 to 1.16.1
Short summary:
- virtio-blk.{mmio,pci} and virtio-scsi.{mmio,pci} improved.
- Several fixes and code refactor pci_config_*() functions.
- Improved AML parsing.

Change-Id: I04b35d006a2bcd1621e28ac2f1b12b9af99b7552
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71064
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 12:08:00 +00:00
Harsha B R
500da54891 mb/intel/mtlrvp: Enable ChromeOS build for mtlrvp
This patch enables building ChromeOS for mtlrvp.
Patch includes,
1. Add cros_gpios for mtlrvp
2. Add chrome OS configuration in Kconfig
3. Add Chromeos.c

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train (CB: 69886)

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 11:57:53 +00:00
Sridhar Siricilla
1e638ba27c soc/intel/meteorlake/romstage: Rewrite the if condition
The patch rewrites `if` condition by connecting two different conditions
using the logical and(&&) operator without changing the semantics to
improve the code readability.

TEST=Build the code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I8c912f694d801768b1553f33de78f01215be7f0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70479
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2022-12-21 09:35:42 +00:00
Subrata Banik
1542d16173 soc/intel/{adl,mtl,tgl}: Drop unnecessary dptf.asl
This patch drops unused `dptf.asl` from the latest IA SoC platforms
as DPTF ACPI code generation is now relies on runtime aka SSDT
rather than having fixed dptf.asl files to include inside the
mainboard dsdt.asl.

TEST=Able to build Google/Kano without any compilation issue.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-21 06:20:38 +00:00
Karthikeyan Ramasubramanian
380411422e mb/google/skyrim: Fix Bluetooth configuration
Power resource for Bluetooth device is not configured correctly in the
device tree. Fix Bluetooth devicetree configuration.

BUG=b:262785310
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able
to connect to a Bluetooth headset.

Change-Id: Id980424349537be35860dec04cc823d419cefe2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21 00:33:04 +00:00
Chris.Wang
9ac0984c5a soc/amd/mendocino: add dptc tablet mode support
add dptc support for different power parameter on tablet/clamshell
mode.

BUG=b:257187831
BRANCH=none
TEST=validate the parameter change for each mode by AGT.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20 21:05:47 +00:00
Rex Chou
134d740168 mb/google/skyrim/var/frostflow: Config I2C frequency for touchpad.
1.Config setting for touchpad I2C

BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies:
1.I2C0 (Touchpad): 385.7kHz

Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20 21:02:27 +00:00
Johnny Lin
161d090d22 soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bit
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE
and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the
same MSR that has been locked by another thread.

Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock
bit.

Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-20 19:53:42 +00:00
Sean Rhodes
57789db4d2 mb/starlabs/starbook/adl: Set thermal trip based on power profile
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20 16:46:44 +00:00
Kapil Porwal
0dd4494063 soc/intel/cmn/block/cnvi: Add missing CNVI IDs for ADL
Add missing CNVI IDs for ADL -
ADL-P: 0x51f2, 0x51f3
ADL-S: 0x7af1, 0x7af2, 0x7af3

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I189be9a8c8895a93d98886e6591e771bbce5f564
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-20 15:48:41 +00:00
Felix Held
a36f4f5fc6 doc/contributing/coding_style: change example to use __fallthrough
While the fall through comment is sufficient for gcc to notice that the
fall-through is intentional, clang requires a special attribute which
also works for gcc. Update the documentation to use this attribute
instead of the comment.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I08dbac8ff1f9e04770a03fb74fabf0d397b50989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71102
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-20 14:45:09 +00:00
Elyes Haouas
17a9849010 soc/intel/*/crashlog.[ch]: Remove unused includes
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20 12:35:57 +00:00
Harsha B R
63444c7739 mb/intel/mtlrvp: Add files required for ramstage and SMM
This patch adds files required for ramstage and SMM.
1. Add file required for ramstage (mainboard.c)
2. Add smihandler.c for SMM

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20 12:34:40 +00:00
Jamie Ryu
071d7f3cef mb/intel/mtlrvp: Enable EC for mtlrvp
This patch will initialize EC for mtlrvp which includes,
1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC)
2. Add respective ACPI configuration
3. Add ec.c required for ramstage
4. Program EC ranges as part of devicetree.cb
5. Enable VBOOT in Kconfig

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with
CHROME_EC using subsequent patches in the train

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20 12:33:45 +00:00
Elyes Haouas
1201fb9a91 src/soc: Remove unneeded <assert.h>
As _Static_assert() is a compiler built-in, <assert.h> is not needed.

Change-Id: I578b4bf286538d0606569d19ec760a1846c8145b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-20 12:07:46 +00:00
Martin Roth
d96aaa6634 Update intel-microcode submodule to upstream master
Updating from commit id 6c0c469:
2022-05-10 15:51:47 -0700 - (Merge pull request #59 from esyr-rh/microcode-20220510-releasenote-fixes)

to commit id 262f0c9:
2022-11-08 08:00:36 -0800 - (microcode-20221108 Release)

This brings in 2 new commits:
262f0c9 microcode-20221108 Release
cffdeb8 microcode-20220809 Release

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I92d2f68e99fe92e0b0f8c472a893fa6ea0e39958
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19 21:40:46 +00:00
Martin Roth
527fc8515f Update amd_blobs submodule to upstream master
Updating from commit id 4ed38e5:
2022-10-25 15:14:53 -0700 - (glinda: add placeholder blobs)

to commit id a2c1529:
2022-12-15 17:46:33 -0800 - (mendocino: Upgrade SMU to 90.35.166)

This brings in 2 new commits:
a2c1529 mendocino: Upgrade SMU to 90.35.166
2898385 Update Picasso FSP binaries

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie13237e2bc1a0c6552396410cb8470b7137f3a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19 21:40:07 +00:00
Martin Roth
60a2faf4a0 Update fsp submodule to upstream master
Updating from commit id 2047412:
2022-11-29 17:52:03 +0800 - (Elkhart Lake MR5 FSP)

to commit id 6f2f17f:
2022-12-14 12:36:46 -0700 - (Deleted old Release Notes and Integration Guides)

This brings in 6 new commits:
6f2f17f Deleted old Release Notes and Integration Guides
3868f73 Updated for SGXFlex - New UPDs available
a649f0f Whitley FSP 2.2.0.3A
f99be62 Merge branch 'master' of https://github.com/intel/FSP
1787bc7 Updated IoT ADL-PS MR1 (3404_00) FSP
1e833b0 Elkhart Lake MR5 FSP

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1dbd85ef06b057305428d42dd6cd6de0f2618439
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19 21:37:59 +00:00
Martin Roth
e1e0b5cbaa Update qc_blobs submodule to upstream master
Updating from commit id e8efa5d:
2022-05-30 15:47:07 +0530 - (sc7180/boot: Update qclib blobs binaries from 44 to 46)

to commit id 33cc4f2:
2022-10-26 14:21:20 +0530 - (sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69)

This brings in 10 new commits:
33cc4f2 sc7280/qtiseclib: Update qtiseclib blobs binaries and release notes from 63 to 69
6c82214 sc7180/boot: Update qclib blobs binaries from 48 to 50
e570e02 Reland "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
6206ab8 Revert "sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063"
82bbf78 sc7280/aop: Update aop blobs binaries and release notes version from 379 to 410
e3a760d sc7180/boot: Update qclib blobs binaries from 46 to 48
741abaa sc7280/boot/shrm: Update qclib blobs binaries from 30 to 35
436cb87 sc7280/cpucp: Update cpucp blobs binaries and release notes version from 060 to 063
3f44ba0 sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes update from 044 to 050
eef51c6 sc7280/qcsec: Update qcsec blobs binaries and release notes for 27

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I72b91e384b74e4e44864ef5f29be78ebac4262fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-19 21:37:29 +00:00
Felix Singer
274fa64e3d tree: Replace Or(a,b) with ASL 2.0 syntax
Replace `Or (a, b)` with `a | b`.

Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19 16:20:23 +00:00
Felix Singer
251d86bad1 tree: Replace LAnd(a,b) with ASL 2.0 syntax
Replace `LAnd (a, b)` with `a && b`.

Change-Id: I6b7b958e2d2a43926663a8dc8755613abb07e949
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70844
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19 16:16:30 +00:00
Felix Singer
f3649f03f3 tree: Replace XOr(a,b,c) with ASL 2.0 syntax
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where
possible.

Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19 16:13:50 +00:00
Subrata Banik
848c37da42 soc/intel/meteorlake: Remove dependency of FSP-S CpuMpPei Module
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
 1. CpuMpPpi  ------> Passing `NULL` as coreboot assume FSP don't need
                      to use coreboot wrapper for performing any
                      operation over APs.

 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
                      to skip FSP running CPU feature programming.

Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.

FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name
`UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).

Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.

Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.

Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.

TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.

Without this patch:

Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.

[SPEW ]  Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ]  Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
         CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ]  Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ]  Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
         Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ]  Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
  APICID - 0x00000000, BIST - 0x00000000
[SPEW ]  Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ]  Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ]  Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0

With this patch:

No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.

This patch is backported from
commit 8409f156d5 (soc/intel/alderlake:
Remove dependency of FSP-S CpuMpPei Module)

Change-Id: I7d9fb37ca1cd4bf325edc951ee7293e459fa2ea4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70600
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-19 14:14:11 +00:00
Subrata Banik
f251a6a439 soc/intel/meteorlake: Implement MultiPhase SI Init Index 2 callback
The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.

The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).

The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.

Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).

This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).

The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.

This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).

In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.

Note: At present, Intel Meteor Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).

This patch is backported from
commit b6c3a0325b (soc/intel/alderlake:
Implement MultiPhase SI Init Index 2 callback).

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.

Change-Id: I2ea1a8bb2b142e39c2bc9d248b7fd0041366c0db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70558
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19 14:13:26 +00:00
Subrata Banik
b9d53a0c8c drivers/intel/fsp2_0: Implement mps2_noop_get_number_of_processors()
This patch implements mps2_noop_get_number_of_processors() API with
minimal information required for Intel MTL FSP to utilise the
`MP_SERVICES_PPI_V2_NOOP` config.

The major difference between Intel ADL and MTL FSP in terms of doing
CPU feature programming aka utilizing MP PPI wrapper code is that,
starting with MTL, FSP has dropped the `SkipMpInit` UPD.

It means now, coreboot doesn't have any way to skip FSP doing MP Init
operation. But during ADL, coreboot had introduced the
MP_SERVICES_PPI_V2_NOOP config that is used to skip FSP about
actually running any CPU feature programming on APs.

The idea is to use the same config even in MTL to provide only the
must have information (to bypass any assert in FSP during debug image)
to FSP.

Passing `FSP_UNSUPPORTED` from mps2_noop_get_number_of_processors()
results in `assert` while compiling FSP in debug mode hence,
implementing the function to pass only the information about BSP being
the active processor along with passing `FSP_SUCCESS` (eventually it
makes FSP happy and doesn't run into any issue in debug and/or release
mode).

TEST=Able to build and boot Google/Rex and Google/Kano while
coreboot skip calling into FSP for doing MP init.

Change-Id: I75d7e151699782210e86be564b0055d572cacc3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70555
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-19 14:12:59 +00:00
Sean Rhodes
836881935f ec/starlabs/merlin: Add EC related files for Cezanne laptops
Add EC memory layout and Q events for AMD Cezanne based boards,
the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE
5570E.

Change-Id: I87806b830b3d58a6ce3b89f45b5a07f4502a87f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68333
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-19 14:12:11 +00:00
Matt DeVillier
6dc05a369e mb/google/octopus: Add NHLT endpoints for Cirrus Logic codec
Add NHLT endpoints for octopus boards using CS42L42 codec.
Reuse method to add da7219 endpoint as the routing is identical.

TEST=boot Windows, verify audio working with coolstar's audio drivers.

Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19 03:47:47 +00:00
Matt DeVillier
f8fdd7a8de mb/google/octopus: update variant VBTs
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP
display init to use native panel resolution instead.

TEST=build/boot multiple google/octopus variants with edk2 payload,
verify boot logo not distorted/stretched.

Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19 03:47:08 +00:00
Matt DeVillier
3a59fef511 mb/google/hatch/kohaku: set VBT boot resolution to 1080p
Boot menus are too small at native 4K res on some panels, so
set fixed display resolution to 1920x1090p

TEST=build/boot KOHAKU with 4K display, verify boot menu text legible.

Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19 03:46:40 +00:00
Frank Chu
f99f308826 mb/google/brya/var/marasov: Configure I2C high and low time
Adjust I2C speed for codec, TPM, touchpad, touchscreen.

BUG=b:260565911
TEST=Built and verified adjusted I2C speed

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2022-12-19 02:21:32 +00:00
Martin Roth
3b32af950d util/crossgcc: Add option to get packages from coreboot's mirror
coreboot has been keeping a mirror of all the toolchain packages used
for releases for quite a while now.  This adds an option to fetch the
packages from the coreboot mirror directly to buildgcc.

This can help with both our releases and when one of the various
servers experiences interruptions or changes a path.

To do this, the URL and filename needed to be split apart, which led to
quite a few changes in the buildgcc script.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-18 00:43:32 +00:00
Jeremy Compostella
50139d00bd lib: Hook up libhwbase in romstage
It's hidden behind the configuration option `CONFIG_ROMSTAGE_LIBHWBASE'.

This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.

Running Ada code in romstage and more particular libhwbase brings a few
challenges as global initialized variables are not supported in
Cache-As-Ram mode.

1. The libhwbase dynamic mmio driver implementation makes the Gnat
   compiler generate some global initialized variables.

   For this reason, when compiled for romstage or for romstage and
   ramstage the static mmio driver is enforced (`HWBASE_STATIC_MMIO').

2. The Gnat compiler generates elaboration functions to initialize
   program data at runtime. These elaboration functions are called by
   the romstage_adainit() function.

   The data references symbols suffixed by `_E'. Even though these
   symbols, at compilation time, do not contain any data and are
   filled with zeros, the Gnat compiler installs them in the .data
   section.

   Since these symbols are actually filled with zeros, it is safe to
   install them in the .bss section.

   cf. https://docs.adacore.com/gnat_ugn-docs/html/gnat_ugn/gnat_ugn/elaboration_order_handling_in_gnat.html#elaboration-code

This patch requires the libhwbase
https://review.coreboot.org/c/libhwbase/+/69854 CL.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libhwbae compiles for romstage and loads successfully

Change-Id: I670249d33506e886a683e55d1589cb2bf9b16aa3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70275
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:51:38 +00:00
Jeremy Compostella
fa83887e48 Add option to use Ada code in romstage
If selected, libgnat is linked into romstage. In addition, a call to
romstage_adainit() is added to support Ada program data
initialization.

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Ada code compiles for romstage and loads successfully

Change-Id: I74f0460f6b14fde2b4bd6391e1782b2e5b217707
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70274
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:48:06 +00:00
Michał Żygowski
e6b96dceab util/chromeos/gen_test_hwid.sh: Replace usage of hexdump
Hexdump command is not available in coreboot-sdk. Replace it with
equivalent implementation using commands that are present in the
container.

TEST=Passed "VP46XX" as prefix variable and it produced the same
crc32 result before and after the change.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Icad93933335b8c5ebd8fee74cc9aaed36bb56482
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-17 20:45:42 +00:00
Johnny Lin
a3e68c9f95 soc/intel/cmn: Clear interrupt status after HECI-1 has been received
According to Intel doc#630774, BIOS should clear Host Interrupt Status
if it has read all the slots of the message from the ME circular buffer.
Since this is not found in client ME document, add a Kconfig
SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server
ME SKU.

On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the
change can avoid seeing below Linux warning during boot with Linux
v5.12:
[   17.868929] irq 16: nobody cared (try booting with the "irqpoll" option)
[   17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0
[   17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1
[   17.922327] Call Trace:
[   17.927780]  <IRQ>
[   17.932253]  dump_stack+0x64/0x7c
[   17.939640]  __report_bad_irq+0x37/0xb1
[   17.948206]  note_interrupt.cold.11+0xa/0x63
[   17.957713]  handle_irq_event_percpu+0x6a/0x80
[   17.967626]  handle_irq_event+0x2a/0x50
[   17.976163]  handle_fasteoi_irq+0x9e/0x140
[   17.985305]  __common_interrupt+0x38/0x90
[   17.994255]  common_interrupt+0x7a/0xa0
[   18.002821]  </IRQ>
[   18.007514]  asm_common_interrupt+0x1e/0x40

Change-Id: I1cf21112870e53a11134d43e461b735ead239717
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17 20:44:10 +00:00
Eric Lai
5b89bf4666 lib: Introduce fw_config_get_field
In some cases, fw_config is used for ids like sar_id, sku_id etc.
To avoid calling fw_config_probe over and over, hence provide the
method to return the value then caller can use the switch case
instead of if else statement.

TEST=get fw_config field value on nivviks.
[INFO ]  fw_config get field name=DB_USB, mask=0x3, shift=0, value =0x1

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iae89668e8fe7322d5a4dcbf88a97d7ed36619af5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17 20:43:16 +00:00
Reka Norman
f49fcc6bf5 util/cbfstool: Change %lu to %zu for size_t argument
With commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map"), builds are failing on 32-bit platforms with:

../cbfstool/cbfstool.c:397:30: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat]
                printf("Image SIZE %lu\n", image_size);
                                   ~~~     ^~~~~~~~~~
                                   %zu

Change the format specifier from %lu to %zu.

TEST=`emerge-cherry coreboot-utils` now succeeds

Change-Id: I3602f57cf91c330122019bfa921faef6deb2b4ce
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70848
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-17 20:41:14 +00:00
Jan Samek
a1a8f58a07 mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settings
Based upon hardware differences from mc_ehl2, disable RP7
and enable RP3 and RP5.

Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:39:44 +00:00
Jan Samek
a2035cc4d0 mb/siemens/mc_ehl3: Add board variant based on mc_ehl2
Add a new mc_ehl variant, which is based on mc_ehl2 implementation.

This patch uses a copy of mc_ehl2 with changes only in naming
as a starting point for the new mc_ehl3 variant.

Follow-up patches will introduce the functional changes against
mc_ehl3.

Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-17 20:39:02 +00:00
Reka Norman
5e78090306 util/genbuild_h: Only use version tags in expected format
With commit 0110e1abe0 ("util/genbuild_h: Update printf %d to %s for
sh compatability"), the ChromeOS coreboot build is failing with:

In file included from src/lib/version.c:4:
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:10:32: error: 'v1' undeclared here (not in a function)
   10 | #define COREBOOT_MAJOR_VERSION v1
      |                                ^~
src/lib/version.c:35:46: note: in expansion of macro 'COREBOOT_MAJOR_VERSION'
   35 | const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION;
      |                                              ^~~~~~~~~~~~~~~~~~~~~~
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:11:32: error: 'v9308' undeclared here (not in a function)
   11 | #define COREBOOT_MINOR_VERSION v9308
      |                                ^~~~~
src/lib/version.c:36:46: note: in expansion of macro 'COREBOOT_MINOR_VERSION'
   36 | const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION;
      |                                              ^~~~~~~~~~~~~~~~~~~~~~

This is because the ChromeOS coreboot repo has a tag which is not in the
expected <major>.<minor> format:
$ git tag
v1.9308_26_0.0.22

Change genbuild_h.sh to only use the version from `git describe` if it's
in the expected <major>.<minor> format.

TEST=ChromeOS coreboot build now succeeds, with versions set to 0:
 #define COREBOOT_MAJOR_VERSION 0
 #define COREBOOT_MINOR_VERSION 0

Building upstream coreboot, the versions are still set correctly:
 #define COREBOOT_MAJOR_VERSION 4
 #define COREBOOT_MINOR_VERSION 18

Change-Id: I81b2317a83cdec4cc2aad60af2990e5e3f4ad694
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Usha P <usha.p@intel.com>
2022-12-17 20:37:22 +00:00
Reka Norman
f7bb72333a soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-N
On nissa, sending EOP late improves boot time by about 57ms.

Before (SOC_INTEL_CSE_SEND_EOP_EARLY):
943:after sending EOP to ME                           931,206 (58,431)
943:after sending EOP to ME                           932,911 (58,427)
943:after sending EOP to ME                           930,908 (58,429)
943:after sending EOP to ME                           941,357 (61,748)
943:after sending EOP to ME                           933,289 (62,050)
943:after sending EOP to ME                           939,578 (62,453)
943:after sending EOP to ME                           932,491 (62,050)
943:after sending EOP to ME                           929,693 (62,655)
943:after sending EOP to ME                           942,247 (62,654)
943:after sending EOP to ME                           936,984 (61,751)

After (SOC_INTEL_CSE_SEND_EOP_LATE):
943:after sending EOP to ME                           1,107,816 (3,498)
943:after sending EOP to ME                           1,053,286 (25,212)
943:after sending EOP to ME                           1,124,095 (3,511)
943:after sending EOP to ME                           1,098,591 (3,498)
943:after sending EOP to ME                           1,107,772 (3,499)
943:after sending EOP to ME                           1,080,008 (45,969)
943:after sending EOP to ME                           1,081,754 (8,024)
943:after sending EOP to ME                           1,109,193 (4,102)
943:after sending EOP to ME                           1,088,866 (4,201)
943:after sending EOP to ME                           1,081,684 (4,203)

BUG=b:247902068
TEST=EOP time is improved on nissa (measurements above).

Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:33:52 +00:00
Jakub Czapiga
e8bef613df tests/Makefile.inc: Build utilities in separate directory
Utilities like kconfig/conf now will be built inside tests build tree.
It will eliminate possible colisions of target names when using test
framework in more than one place (see CB:70110)

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4c1eb901c921f4ec6ee8985b154362153c5fd0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70359
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:32:53 +00:00
Jakub Czapiga
d190e0fa96 tests/Makefile.common: Remove unnecessary dependency to kconfig/conf
Utility will be built while executing kconfig targets so it is not
necessary to keep hard dependency on kconfig here.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I578f3e1d9de63e91ded44746539265bcd55bf579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70298
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:32:12 +00:00
Jakub Czapiga
ab0686109e tests/Makefile.common: Allow to override tests defconfig
Some tools based on test framework might require defconfig other
than one set in tests framework.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If53b9a54ef7389dd979dfe772e6946439f7d6a62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70109
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:31:38 +00:00
Jakub Czapiga
3088e43a5a tests/Makefile.common: Describe available test attributes
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I8ce702b4be254e206e2018deabde985b56cc6cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70475
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 20:30:45 +00:00
Jakub Czapiga
e744ba643d tests: Support linking with system libc
This patch allows for linking selected files with system libc. This
allows for creating libraries interacting with filesystem, standard I/O
and other parts of system. Until now it was only possible using CMocka
proxy functions or functions not masked by code under test.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I652362ba61a25e974d706357fc36479ccee763e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-12-17 20:30:12 +00:00
David Lin
69a6dd6aae drivers/generic/nau8315: Change method for HID assignment
This patch is to change method of HID assignment with compatible id
style in nau8315_config and allow mainboards to set it.

Signed-off-by: David Lin <CTLIN0@nuvoton.com>
Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-17 20:29:15 +00:00
Wisley Chen
964a60360a mb/google/nissa/var/yaviks: Enable wifi SAR
Enable wifi sar function for yaviks.
Use the fw_config to separate SAR setting for different wifi card.

BUG=259199095
TEST=build, enabled iwlwifi debug, and check dmesg

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17 20:26:49 +00:00
Stanley Wu
3228b266b2 mb/google/nissa/var/pujjo: Tunning RegProxCtrl0 register for SX9324
Update SX9324 RegProxCtrl0 register settings based on tunning value
from P-sensor vendor.

BUG=b:242662878
TEST=i2cdump -y -f 13 0x28 on Pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17 20:24:44 +00:00
Sean Rhodes
e56a812a6a soc/intel/common: Remove read-only from chip_get_common_soc_structure
Remove the `const` property from chip_get_common_soc_structure so that
the returned values can be overwritten as required.

Cc: th3fanbus@gmail.com
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-17 20:23:55 +00:00
Matt DeVillier
d14461f403 device/Kconfig: bump desktop framebuffer max height/width to support 4K
Increase the default linear framebuffer max height/width for desktops
so that native display resolution works properly on 2160p and 1440p
ultrawide displays.

TEST=build/boot google/fizz, verify libgfxinit display init works
properly on 3440x1440p and 3840x2160p displays.

Change-Id: I95a1f1275a4faea195b73997c648023119807958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-17 18:11:04 +00:00
Felix Held
719f7bebb0 device/oprom/yabel/io: use __fallthrough instead of comment
Unlike gcc, a clang build will fail when only a comment is used to
indicate that the fallthough is intended. To fix the clang build, use
__fallthrough instead. This will fix the build errors introduced by
commit f45c7671d9 ("Set x86_64 as supported architecture for clang")
that enabled clang builds for a case that uses yabel to run the VBIOS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ed337025adeb833f352d198fc0f13b5e1c209c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70889
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-17 16:45:44 +00:00
Angel Pons
816919b3c8 soc/intel/skylake/irq.c: Fix undefined memcpy()
The original value of the `DevIntConfigPtr` is unknown, and there's no
way to be absolutely certain that it actually points to usable memory.
Instead of copying the data, update the pointer's address to reference
the global variable directly. It is assumed that FSP does not write to
the memory pointed by `DevIntConfigPtr`. Confirming this assumption is
pointless; one might as well reimplement FSP instead.

Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-12-17 12:36:33 +00:00
Sean Rhodes
fd618f3325 Documentation/mb/starlabs: De-duplicate the building instructions
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I20301b3041a62eb416ed61a84544ec4e5cc66c1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68585
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 01:20:58 +00:00
Ben-StarLabs
b2db3659a9 mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variant
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_202209`:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starbook-specification

Signed-off-by: Ben-StarLabs <ben@starlabs.systems>
Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17 01:20:26 +00:00
Karthikeyan Ramasubramanian
1c3da3f236 mb/google/skyrim: Configure RO and RW SPL files
This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.

BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.

Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 01:18:59 +00:00
Karthikeyan Ramasubramanian
c57a0663ab Update 3rdparty/blobs submodule
Updating from commit id f8e84db3:
    mainboard/starlabs/cezanne/starbook: Add EC binary 1.02

to commit id 01ba1566:
    mb/google/skyrim: Add RO SPL table

This brings in 3 new commits:
01ba1566: mb/google/skyrim: Add RO SPL table
ce5566fd: soc/mediatek/mt8186: Update SSPM firmware from v1.0.0 to
			       v2.0.0
55d92ce7: soc/mediatek/mt8188: Update SSPM firmware from v1.88.00 to
			       v1.88.01

Change-Id: Ie8e78f61556da268f74caaba211b30e70f984f13
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70776
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17 01:18:49 +00:00
Kevin Chiu
3cbae049dc mb/google/brya/var/lisbon: Use RPL FSP headers
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL.

Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL
FSP headers for lisbon.

BUG=b:246657849
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=lisbon emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
flash and boot lisbon to kernel.

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-16 21:56:06 +00:00
Felix Held
ca432d1fd9 drivers/i2c/designware: translate return type in dw_i2c_dev_transfer
dw_i2c_transfer returns an enum cb_err type, but dw_i2c_dev_transfer
returns an int, so explicitly translate between the types. Since
dw_i2c_transfer only returns either CB_SUCCESS or CB_ERR which are
defined as 0 and -1, this won't change behavior of dw_i2c_dev_transfer.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2cbcf6564035d5c0fc13f5d5e7ac0d0425e85d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16 19:41:50 +00:00
Arthur Heymans
b12caef23b configs: Add 64bit buildtest for prodrive/hermes
This configuration also boots on real hardware.

Change-Id: Ic62a33f8d8c3fdaa8182e797b2bf6fbed6b55731
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16 17:22:13 +00:00
Arthur Heymans
f45c7671d9 Set x86_64 as supported architecture for clang
This boots on both qemu and real hardware now.

Change-Id: Ibd320059cff575847bbf1844b5bb100312f77916
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16 17:21:17 +00:00
Arthur Heymans
2834d98f52 cpu/intel: Fix clearing MTRR for clang 64bit
Clang generates R_X86_64_32S symbols that get truncated.

TESTED:
- prodrive/hermes boots with GCC and clang
- MTRR are properly cleared (tested by filling in both
MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing)

Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16 17:20:32 +00:00
Angel Pons
1c9a8d8083 nb/intel/haswell: Add native raminit scaffolding
Implement some scaffolding for Haswell native raminit, like bootmode
selection, handling of MRC cache and CPU detection.

Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16 17:19:07 +00:00
Angel Pons
49509189dc sb/intel/lynxpoint: Add native PCH init
Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.

Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16 17:15:53 +00:00
Angel Pons
9c8c858e68 sb/intel/lynxpoint: Add native thermal init
Implement native thermal initialisation for Lynx Point. This is only
needed when MRC.bin is not used.

Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64180
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16 17:13:18 +00:00
Angel Pons
70c6185476 sb/intel/lynxpoint: Add native USB init
Implement native USB initialisation for Lynx Point. This is only needed
when MRC.bin is not used.

TO DO: Figure out how to deal with the FIXME's and TODO's lying around.

Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16 17:12:43 +00:00
Angel Pons
322b1c3d90 haswell/lynxpoint: Add native early ME init
Implement native early ME init for Lynx Point. This is only needed when
MRC.bin is not used.

Change-Id: If416e2078f139f26b4742c564b70e018725bf003
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16 17:08:55 +00:00
Angel Pons
567ece44ea haswell/lynxpoint: Add native DMI init
Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.

TEST=Verify DMI initialises correctly on Asrock B85M Pro4.

Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-16 17:08:00 +00:00
Sridhar Siricilla
b739fd287d soc/intel/common: Drop unreferenced DP related macros
The patch drops the unreferenced DP related timeout macros.

TEST=Build code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-16 17:06:52 +00:00
Frank Chu
0cb7e614d0 mb/google/brya/var/marasov: Update gpio table for EVT
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-16 17:05:53 +00:00
Frank Chu
93197d20b6 mb/google/brya/var/marasov: Disable unused PCIE8 for s0ix
Disable unused PCIE8 for fix system can not enter S0ix completely.

BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-16 17:05:22 +00:00
Liju-Clr Chen
26a8dea551 mb/google/geralt: Revise the naming of MIPI PWM control GPIO
Rename the MIPI PWM control GPIO to be consistent with the schematic.

BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB

Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-16 17:05:05 +00:00
Bo-Chen Chen
f57155bca4 mb/google/geralt: Pass GPIOs to allow backlight control in payloads
There are two ways to control backlight in geralt:
1. MIPI/eDP panel => control backlight via the GPIOs.
   (`backlight chip enable` and `PWM dimming control`)
2. eDP OLED panel => enable backlight via `backlight chip enable` and
   control dimming over AUX.

For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs
will be passed from coreboot. For eDP OLED panel(#2), only the
"backlight enable" GPIO will be passed. If depthcharge successfully gets
the GPIOs, it will use them to control backlight.

BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB

Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16 17:04:35 +00:00
Frank Chu
de4727aecc mb/google/brya/var/marasov: Enable ELAN touchscreen
Correct touchscreen setting to make touchscreen function workable.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchscreen function

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16 17:04:14 +00:00
Felix Held
76364fb66b drivers/i2c/designware/dw_i2c: handle bus < 0 in dw_i2c_dev_transfer
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus
number for a device. In this case return -1 instead of implicitly
casting the -1 to an unsigned int and passing that as bus number to
dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer
already ended up handling this error case correctly, but better handle
the error more directly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16 15:33:00 +00:00
Felix Held
d832bda32b soc/amd/common/block/i2c: don't call die() when MMIO address is NULL
There's no need to call die() in the case that the MMIO address of the
I2C controller is NULL, so handle this case by returning a failure
instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12c143916ad551c56cc4ff75ae23754018817505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16 15:32:02 +00:00
Elyes Haouas
f3c107eb01 soc/intel/apollolake/acpi/northbridge.asl: Fix comment
This fixes the following error:
In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21:
src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment]
                PXEN,   1,      /* Enable */
                                ^

Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-16 06:15:27 +00:00
Karthikeyan Ramasubramanian
f2dcd9dd81 security/vboot: Update vbnv_init signature
If the temporary nvdata storage inside the vboot context is already
initialized then return immediately without reinitializing from the
backup NV storage. This allows vbnv_init to be called more than once.

Also the check to enable USB Device Controller (UDC) happens after
NVdata is initialized. Hence the nvdata in vboot context can be used
instead of reading from the backup storage again.

BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.

Change-Id: Id72709e2fc3fe6a12ee96df8df25e55cf11e50a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-16 01:23:03 +00:00
Felix Singer
d901077335 ec/kontron/it8516e/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I16890206d517f0455d29c1642cbbe642a3312481
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70679
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16 00:59:41 +00:00
Felix Held
ca261091eb cpu/x86/mtrr: rename local cpu_idx variable and make it const
After the previous patch this local variable is no longer the mpinit CPU
index, but the LAPIC ID, so rename it. Since it will only be set once,
it can also be marked as const.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fad4e1095478213727bee8586852f9d5a7d18e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70798
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-12-16 00:30:12 +00:00
Subrata Banik
08529918fc mb/google/rex: Add support for WWAN over USB3
This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1
schematics dated 12/14/2022.

TEST=Able to build Google/Rex.

Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15 18:08:04 +00:00
Subrata Banik
bc6a305f82 mb/google/rex: Modify the PIN name as per schematics
This patch updates the GPIO PIN name as per Proto 1 schematics dated
12/14/2022.

TEST=Not code change, just updated the comment section.

Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15 18:07:45 +00:00
Eran Mitrani
4c9440c673 soc/intel/{adl, common}: provide a list of D-states to enter LPM
This was done previously for ADL. moving the code to common so
it can be leveraged for other platforms (e.g. MTL)

TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15 16:53:51 +00:00
Frank Wu
d27cd2a328 mb/google/skyrim/var/frostflow: Update SPD file for H9JCNNNFA5MLYR-N6E
Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex
instead of spd-9.hex.
Reserve RAM ID 3 for it, so the RAM ID table remains the same.

BUG=b:261530632
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage
Then boot devices successfully

Change-Id: I1b683168310f74a07d246af8618b977cce32287a
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15 14:28:11 +00:00
Frank Wu
3a4e201a21 spd/lp5: Update memory configuration of H9JCNNNFA5MLYR-N6E
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.

BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15 14:28:02 +00:00
Elyes Haouas
315d3264b6 treewide: Remove unused 'include <arch/io.h>'
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15 13:37:41 +00:00
Stanley Wu
8d728c2090 mb/google/nissa/var/pujjo: Modify WWAN warm reset sequence
pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff
minimum 500ms requirement.

BUG=b:260380268
TEST=Build and boot on pujjo

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-15 13:36:18 +00:00
Subrata Banik
5dfec71829 soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration

+-----------------------+-------------------------------+
|    Field Description  |       ASPM Support            |
+-----------------------+-------------------------------+
|     00b               |       No ASPM support         |
+-----------------------+-------------------------------+
|     01b               |       L0s Supported           |
+-----------------------+-------------------------------+
|     10b               |       L1 Supported            |
+-----------------------+-------------------------------+
|     11b               |       L0s and L1 Supported    |
+-----------------------+-------------------------------+

100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).

Additionally, changed enum definition which is now meeting the FSP expectations better.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15 08:11:30 +00:00
Kapil Porwal
0f15030700 mb/google/rex: Add RTD3 support for discrete wifi module
BUG=none
TEST=Build and boot to the OS on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15 08:10:19 +00:00
Karthikeyan Ramasubramanian
dee52d962d Update vboot submodule to upstream main
Updating from commit id 148e5b83:
    Makefile: Fix and simplify the RUNTEST test wrapper

to commit id 196b0843:
    create_new_keys: use single AP RO Verification root key pair

This brings in 30 new commits.

Change-Id: Iedfc6cf0ff2dc1913a7a41a4302dc1951abf8a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-15 03:13:55 +00:00
Elyes Haouas
45d818b4ab nb/intel/sandybridge/sandybridge.h: Remove unnecessary guard
__ACPI__ is covered through __ASSEMBLER__.

Change-Id: I6a637e63c6bbe4af7cd52be1893e47d6b5967886
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70697
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15 03:13:11 +00:00
David Wu
4f29739be3 mb/google/brya/var/zydron: Enable Fast VMode for zydron
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log

Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15 03:12:19 +00:00
Bora Guvendik
8c46232005 soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-15 03:11:24 +00:00
Felix Held
447f5777aa cpu/x86/mtrr: use lapicid instead of cpu_index calls
The cpu_index function can't be used before mpinit, so use lapicid calls
instead. This fixes the regression introduced by commit 4c3749884d
("cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs")
and also reverts also commit b3261661c7 ("cpu/x86/mtrr/mtrr: fix
printk format strings"), since lapicid returns an unsigned int while
cpu_index returns an unsigned long.

TEST=Mandolin boots again and doesn't fail when it first tries to print
the MTRR configuration

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0d226704051ab171891775a618ce7897b74fde16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-15 03:10:08 +00:00
Julius Werner
2cf2bd8197 mem_chip_info: Fix potential overflow
The calculation for mem_chip_info_total_density_bytes() may already
overflow in the intermediate 32-bit calculations before being assigned
to the 64-bit result variable. Fix that.

Fixes Coverity issue: CID 1501510

BRANCH=corsola

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I73da014c953381974c6ede2b17586b68675bde2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-15 02:53:45 +00:00
JasonNien
4a0e5e4741 mb/google/skyrim: Enable PCIe RTD3 support
Add PCIe RTD3 support for Skyrim

BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times

Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 21:31:40 +00:00
Fred Reitberger
267edecccb soc/amd/morgana/Kconfig: Remove TODO after review
Remove more TODO comments after reviwing against morgana ppr #57396, rev
1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14 19:39:10 +00:00
Arthur Heymans
8f95f74eb2 util/cbfstool: Fix building with clang & -Wshadow
Clang -Wshadow is more rigorous than GCC and picks a shadowing of the
optarg global variable in /usr/include/bits/getopt_core.h .

TESTED: builds with both gcc and clang.

Change-Id: Ifc362c84511abb6a000671f03498e841d7747074
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70508
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14 18:31:55 +00:00
Felix Held
c4f5241e66 soc/amd/common/block/espi_util: drop unneeded check in espi_get_config
Since soc_get_common_config will either return a valid pointer or cause
a linking error, this function will also return a valid pointer or cause
a linking error, so no need for additional runtime checks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14 17:58:08 +00:00
Felix Held
993092039b soc/amd/*/config: drop invalid comment
Since commit 28e61f1634 ("device: Use __pci_0_00_0_config in
config_of_soc()") config_of_soc() was changed form being an actual
function to a macro for the __pci_0_00_0_config struct pointer generated
by util/sconfig. This change didn't only improve linker optimizations,
but also turned runtime errors into link-time errors, so it's guaranteed
that __pci_0_00_0_config won't be NULL and config_of_soc() won't
"return" NULL.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14 17:57:45 +00:00
Felix Held
687ec6bd72 soc/amd/common/block/espi_util: make espi_set_initial_config non-fatal
Improve the espi_set_initial_config implementation so that a failure in
there due to an invalid configuration won't call die() and stop booting
at this point, but return an error to the caller so that the rest of the
eSPI configuration will be skipped.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-14 17:07:19 +00:00
Felix Held
84429e092f soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatal
Improve the eSPI pin configuration setup so that a failure in there
won't call die() and stop booting at this point, but return an error to
the caller so that the rest of the eSPI configuration will be skipped.
This will prevent an early boot failure if the EC is missing or the eSPI
interface is in a non-functional state. Also slightly shorten the
function names so that the code still fits into 96 chars.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-12-14 16:05:50 +00:00
Arthur Heymans
4f2b5a5dbd device/cpu_device.c: Zero initialize struct
Don't rely on this being 0.

Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69752
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 13:52:00 +00:00
Arthur Heymans
db65dd60fb cpu/x86/mp_init.c: Improve AP entry point
Make sure that a pointer exists before dereferencing it.

Change-Id: I1a9833bb9686451224249efe599346f64dc37874
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 13:51:40 +00:00
Jakub Czapiga
3c8a3d1295 tests/Makefile.common: Allow to disable test framework with parameter
Test framework can be used as a base for other test-like utilities - for
example look at screenshoot utility in depthcharge. Sometimes CMocka is
not required and even makes things problematic. Thanks to this patch one
can set -no_test_framework parameter to instruct framework not to
include and link selected test against CMocka library.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I01dc7c6c50e6ae2f7f71bd6752c2d5f2cc7c3cdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2022-12-14 13:37:39 +00:00
Sridhar Siricilla
f9ee35ea34 soc/intel/common: Add helper function to get DP mode
The patch adds helper function to get the DP mode.

TEST=Build the code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-14 13:35:36 +00:00
Arthur Heymans
e64b8ac1e7 cpu/intel/206ax: Fix generating C state entries
The struct device passed to this function is the cpu cluster and not
individual lapic. This fixes a regression introduced by
cdb26fd (cpu/intel/model_206ax: Remove fake lapic device)

Change-Id: I586e13a723303b8d639d526a175bd6828465a607
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-14 13:31:09 +00:00
Subrata Banik
d34364bdea soc/intel/alderlake: Utilize CPU_BCLK_MHZ over dedicated macro
This patch drops the redundant macro to define CPU BCLK and instead
uses `CPU_BCLK_MHZ` config to calculate the
`smbios_cpu_get_max_speed_mhz`.

TEST=Able to see max cpu speed is correct in smbios table while trying
on Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 07:03:16 +00:00
Subrata Banik
ba6e66328b soc/intel/meteorlake: Drop NEM support
This patch drops NEM support from MTL and enables eNEM support.

BUG=b:217130861
TEST=Able to build and boot Google/Rex in eNEM mode.

Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14 07:02:31 +00:00
Subrata Banik
43004211e2 soc/intel/meteorlake: Add required configs to enable eNEM
This patch combines all required configs under one umbrella config
named `METEORLAKE_CAR_ENHANCED_NEM`.

MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not
selected.

BUG=b:217130861
TEST=Able to build and boot Google/Rex.

Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14 07:01:59 +00:00
Subrata Banik
8e158597f9 soc/intel/meteorlake: Reorg TCSS related configs
This patch moves all required TCSS related configs under one umbrella
config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will
help in future to deselect the TCSS support for MTL SoC SKUs.

TEST=Able to build and boot Google/Rex.

Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14 07:01:48 +00:00
Subrata Banik
b5fc0c4088 drivers/wwan/fm: Fix typo
This patch fixes a typo by adding `Arg0 = 0` to define warm reset.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14 06:51:15 +00:00
Subrata Banik
6ed431589b vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80
Update header files for FSP for Meteor Lake platform to
version 2431_80, previous version being 2404_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 06:47:47 +00:00
Subrata Banik
10929ef008 soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.

This patch is backported from
commit fad1cb062e (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).

Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 06:35:11 +00:00
Subrata Banik
b25aeb5937 soc/intel/meteorlake: Remove FIXME as SkipMpInit UPD has deprecated
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP
doesn't like to allow an option for boot firmware to perform CPU feature
programming being independent of FSP.

Change-Id: I6447937838ab91551d172936cbb4201ea86a614b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 06:34:16 +00:00
Subrata Banik
95fc5d776a soc/intel/meteorlake: Drop enable_bios_reset_cpl() function
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.

Also, drop 1ms delay after setting the BIOS reset CPL.

This patch is backported from
commit 3f980ca7be (soc/intel/alderlake:
Drop enable_bios_reset_cpl() function).

Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-14 06:33:23 +00:00
Subrata Banik
decb9717ce soc/intel/meteorlake: Enable VMX and VTD
Drops the `FIXME` comment and relevant code as this patch enables
VMX and VTD.

This patch also fixes the problem of additional reboot on every warm
boot due to overriding the CPU soft-strap.

TEST=No extra reboot seen while issuing warm reset from kernel
console.

without this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	10,334,707 (9, 109,447)

with this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	1,334,707 (109,447)

Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14 06:33:09 +00:00
Eran Mitrani
988d3eefa6 mb/google/hatch/dratini: increase power enable to reset deassert delay
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.

TEST=tested on dratini device and observed the issue is resolved.
BUG=b:260253945

Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14 03:46:09 +00:00
Tarun Tuli
0f0a43c9b1 mb/google/poppy: Add support for a variant finalize function
Add a hook to allow a variant finalize to be called at the end of
ramstage.

BUG=b:245954151
TEST=Builds successfully

Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14 03:31:47 +00:00
Felix Singer
fa0709663b sio/winbond/w83627hf/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I6858ddaa8b70194ffdd3b4edcb0ee57aec262b48
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:53:57 +00:00
Felix Singer
84e6123d7e soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:53:09 +00:00
Felix Singer
3dc4d84586 soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:52:52 +00:00
Felix Singer
8cc2962b12 soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:52:23 +00:00
Felix Singer
476fe6ae7e soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 00:52:05 +00:00
Felix Singer
3e90ce547c mb/google/cyan/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:30 +00:00
Felix Singer
1151088c02 mb/google/skyrim/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:18 +00:00
Felix Singer
a006259e6f mb/google/slippy/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I950d776a712a104f2caed614886ce2527028ead7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:01 +00:00
Felix Singer
1bb621c002 sio/winbond/w83667hg-a/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I3809880312af4736407e361da53f0424280e43d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:50:42 +00:00
Felix Singer
a61e6546f6 mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:50:02 +00:00
Felix Singer
69b48d8231 mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:50 +00:00
Felix Singer
c64c9cd5fa mb/aopen/dxplplusu/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:20 +00:00
Felix Singer
4da79a7f25 ec/smsc/mec1308/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I0a419c861e84cd96e8337957dc62a7ca5b981e14
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:01 +00:00
Felix Singer
612801d0f8 ec/quanta/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I00a6ece73048209861221cba5f2c7381adfa54b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:46 +00:00
Felix Singer
ff6b3af113 ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:30 +00:00
Felix Singer
f45a6c2a50 ec/lenovo/h8/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:07 +00:00
Felix Singer
2f308d4957 sb/intel/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I94b2e6ecb90a2616e184ae9331c397c75089e373
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:47:52 +00:00
Felix Singer
b26e255877 mb/51nb/x210/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:56 +00:00
Felix Singer
facf7d077c superio/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ibbecba97dd1628889539c2962dd31964c252c8bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:41 +00:00
Felix Singer
18af706d50 vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:20 +00:00
Felix Singer
52f46525b4 drivers/intel/gma/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ifd3a814228df6a399fe1110abf5b5bc18e6fd6d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 00:46:03 +00:00
Raul E Rangel
0e9cc44d1b Documentation: Add wake source info to device tree documentation
The device tree documentation was promoting using a GPIO wake event and
a GPE wake event. We should only ever have one. This wasn't actually
causing a problem because the wake bit was set on the `irq` property,
but the IO-APIC can't actually wake the system, so it was a no-op.

This change fixes up the markdown so it's formatted correctly, and also
adds a section explaining what the different wake configurations are.

BUG=b:243700486
TEST=mdformat

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67385
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 18:50:54 +00:00
Martin Roth
ae7d8379a5 util/release: Update gerrit_stats script to latest version
This updates a number of things:
- Move the cache directory under the .local directory
- Reformat & clean up with perltidy.  Add the perltidy command line.
- Add username and email aliases to clean up duplicates and unknown
  email addresses.
- Use full length commit IDs
- Collect patch commenters
- Check variables before using them as key values
- Ignore patch submit time, just collect the date
- Get stats about large patches
- Format the output better

Example output:
Statistics from commit c35f281934 to commit f8fbf0917c
Patch, Date, Owner, Author, Submitter, Inserted lines, Deleted lines, Subject, Reviewers, Commenters
"f8fbf0917c722378454b07c2e8ec1a3f87b324ae", 2022/12/10, Frank Chu, Frank Chu, Martin Roth, 22, 1, "mb/google/brya/var/marasov: Change FSP board type to Type3", "Frank Chu, Eric Lai" , "-"
"5778e06771627a5541ca2b137e783f47257f05ec", 2022/12/10, Dinesh Gehlot, Dinesh Gehlot, Subrata Banik, 30, 1, "soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`", "Kapil Porwal, Elyes Haouas" , "Subrata Banik"
"ed8bdefcdf6c19258febb9931d1e8eb12b958bcc", 2022/12/10, Jamie Ryu, Jamie Ryu, Felix Held, 76, 3, "mb/intel/mtlrvp: Add MTL-P RVP board ids", "Usha P,
Sridhar Siricilla, Eric Lai, Subrata Banik" , "Eric Lai, Subrata Banik, Harsha B R, Angel Pons"

- Total Commits: 985
- Average Commits per day: 17.85
- Total lines added: 61475
- Average lines added per commit: 62.41
- Number of patches adding more than 100 lines: 49
- Average lines added per small commit: 37.82
- Total lines removed: 758022
- Average lines removed per commit: 769.57
- Total difference between added and removed: -696547

=== Authors - Number of commits ===
Author                         ,Ptchs ,Revws , Cmnts , Sbmts , Email                                                , Prcnt, Last commit         ,
Earliest_commit
Elyes Haouas                   ,  126 ,   90 ,    28 ,     0 , ehaouas@noos.fr                                      ,12.79%, 2022/12/10 , 2022/10/17
Arthur Heymans                 ,  107 ,   99 ,    28 ,    40 , arthur@aheymans.xyz                                  ,10.86%, 2022/12/10 , 2022/10/17

=== Authors - Lines added ===
Martin Roth                   ,      10103, 16.434%
Kyösti Mälkki                 ,       6044, 9.832%
Arthur Heymans                ,       3314, 5.391%

=== Authors - Lines removed ===
Arthur Heymans                ,    -741944, 97.879%
Felix Held                    ,      -3031,  0.400%
Kyösti Mälkki                 ,      -1680,  0.222%

=== Reviewers - Number of patches reviewed ===
Angel Pons                    ,    272, 27.614%
Eric Lai                      ,    201, 20.406%
Felix Held                    ,    106, 10.761%

=== Submitters - Number of patches submitted ===
Name                          ,      #,  total%,    Own,    own%,  Other,  other%
Felix Held                    ,    482, 48.934%,     56,  11.62%,    426,  88.38%
Martin Roth                   ,    179, 18.173%,     42,  23.46%,    137,  76.54%
Subrata Banik                 ,     54,  5.482%,     31,  57.41%,     23,  42.59%

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie1694116ab36ca4db25d13935adadca10e50068f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-13 18:49:13 +00:00
Fred Reitberger
a6514e2b1f soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 17:43:11 +00:00
Robert Zieba
8ff8937843 util/spd_tools: Format lp5 file to golang standards
This commit formats the lp5.go file according to goland standards.

TEST=Built spd_tools

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If102c90f732efc51a90de6cc0e18c879d56699b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-13 17:42:33 +00:00
Jeff Li
3de39fa36f soc/intel/common/block: add definition of GPIO configuration
Add two macros:
 - PAD_CFG_NF_OWNERSHIP()
 - PAD_CFG_GPIO_OWNERSHIP()

to support setting the Host Software Ownership (own) fields.

Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13 17:42:03 +00:00
Felix Held
2557d02eee mb/google/guybrush,skyrim: use gpio.h include everywhere
Now that gpio.h will only include the defines in the IASL case, gpio.h
can be included instead of soc/gpio.h in the files that will be directly
or indirectly included in the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 15:23:52 +00:00
Felix Held
acf96dfcdc include/gpio: skip everything but soc/gpio.h include in ASM & ACPI cases
When gpio.h gets directly or indirectly included in the DSDT ar an
assembly file, everything but the preprocessor defines for the GPIOs
shouldn't be included to keep IASL or the assembler happy.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I046ed87d3947ba5b1fcd0bdd4cffcda57bc13404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70509
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 15:23:37 +00:00
Elyes Haouas
3cd89a003b vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-13 15:19:58 +00:00
Reka Norman
4ae5873e7f mb/google/nissa/var/nivviks,yaviks: Add DmaProperty for ISH
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on nivviks and yaviks.

BUG=b:259716145
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.

Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ

After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA

Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:52:57 +00:00
Reka Norman
6419fbf193 drivers/intel/ish: Allow adding DmaProperty to _DSD
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Allow adding
DmaProperty to the _DSD of the ISH device. This will result in the
kernel marking the device as untrusted.

BUG=b:249846505
TEST=Check SSDT is correct, and kernel detects the DmaProperty and
firmware-name properties.

SSDT entry on yaviks with both add_acpi_dma_property and firmware_name
set in devictree:
    Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "firmware-name",
                    "adl_ish_lite.bin"
                }
            },

            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Change-Id: Ie1539fc757e72e995e98c3ecf83e705e3bede8c0
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:52:37 +00:00
Fred Reitberger
0423bce8e8 soc/amd/morgana: Update pci int defs
Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:38:06 +00:00
Robert Chen
1cd409f3a8 mb/google/brya/var/lisbon: Add Wifi SAR for lisbon
Add wifi sar for lisbon.

BUG=b:260938760
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: Ia347c4cf56bec971700bb53a5804e36e0bad82fb
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70483
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:37:33 +00:00
Robert Chen
b9a59f74f0 mb/google/brya/var/gladios: Add Wifi SAR for gladios
Add wifi sar for gladios.

BUG=b:260950906
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: I4cd015f17c4ddd28414f51a873ae4afc37863708
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70605
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:37:18 +00:00
Subrata Banik
97a45e6a2a soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resume
This patch skips sending CONN IPC command to PMC if system is resuming
from S3.

Sending CONN IPC command as part of `tcss_configure_dp_mode()` function
results into ERROR while system is resuming from S3.

Additionally, skip `configure_aux_bias_pads()` during S3 resume.

BUG=b:260984500
TEST=Able to test on Google/Rex.

Without this patch:
[ERROR]  pmc_send_ipc_cmd status: fatal
[ERROR]  Port 1 connect request failed
[SPEW ]  [TCSS] TcssInit() - End

With this patch:
No error seen during S3 resume.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-13 14:36:50 +00:00
Sudheer Kumar Amrabadi
982bf99c89 soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
Tranferring a bit to DC through Skuid to update the regulator
node in order to support pro and non-pro

BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs

Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68385
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:35:51 +00:00
Sudheer Kumar Amrabadi
8139fc4be5 soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUs
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid. Modified socinfo_modem_supported() API to utilize
helper functions.

BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:35:21 +00:00
Martin Roth
0110e1abe0 util/genbuild_h: Update printf %d to %s for sh compatability
When printing a date, genbuild_h is printing it as two digits, using
a leading zero if the value is below 10.

The shells like bash, dash, etc don't fully import the numbers 08 and
09 when using the printf conversion specifier %d.  They apparently
interpret the numbers as octal and only import the leading 0, dropping
the 8 or 9. This isn't an issue for 01 to 07, because those are valid
octal numbers, so %d prints them without an issue.  Because 08 and 09
are not valid octal, various shells return different errors:

Example shell returns for 'printf "%d" 08':
 bash: printf: 08: invalid octal number
 dash: printf: 08: not completely converted
 fish: 008: value not completely converted
 yash: printf: `08' is not a valid integer
 sash: printf: 08: not completely converted

To prevent this, just print all of the values as strings.

zsh just seems to ignore the possibility of the value being octal
and prints the value as a single digit 0-9.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I97b6aa74d74379f6bdc1f0fceecc8002cc36ca09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70478
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:34:59 +00:00
Frank Chu
4e37a8dad2 mb/google/brya/var/marasov: Enable PIXA touchpad
Correct touchpad setting to make touchpad function workable.

BUG=b:261393412
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchpad function

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3c816ce4293ae362f0e5c18171f296d42b4307c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70440
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:34:08 +00:00
Elyes Haouas
12149ec0a3 mb/intel/coffeelake_rvp/Makefile.inc: Avoid link to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I178c849d07e61d7a237629f3be1b52d3b4abb513
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:33:12 +00:00
Elyes Haouas
167b7fcdd9 soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:31:41 +00:00
Elyes Haouas
878a99f554 soc/intel/broadwell/early_init.c: Use {read,write}32p()
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:31:11 +00:00
Elyes Haouas
bc849b5459 soc/intel/baytrail/pmutil.c: Use {read,write}32p()
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:30:07 +00:00
Elyes Haouas
f12c2b0837 soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:29:40 +00:00
Elyes Haouas
b988f8aac5 soc/intel/alderlake/bootblock: Use 'false/true' macros
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:28:56 +00:00
Elyes Haouas
347b471901 soc/intel/alderlake/bootblock: Use read32p()
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:27:12 +00:00
Elyes Haouas
50f651baea soc/mediatek/common: Use write32p()
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-13 14:26:41 +00:00
Elyes Haouas
b433470b02 soc/cavium/cn81xx: Use write{32,64}p()
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:26:23 +00:00
Felix Singer
eb99f62456 {drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntax
Replace `ShiftRight (a, b)` with `a >> b`.

Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:17:43 +00:00
Felix Singer
447c399d35 soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:16:44 +00:00
Felix Singer
4bbd807c01 soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntax
Replace `Subtract (a, b)` with `a - b`.

Change-Id: I77028c17dcd7925a392d56488d34090837d660f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:16:04 +00:00
Felix Singer
bf1de40853 {soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax
Replace `Subtract (a, b, c)` with `c = a - b`.

Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:14:15 +00:00
Felix Singer
fe33b4cb7c soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntax
Replace `Add (a, b)` with `a + b`.

Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:13:00 +00:00
Felix Singer
e4c30044f2 soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where
possible.

Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:12:13 +00:00
Felix Singer
9a37ae6ef6 mb/google/jecht/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntax
Replace `LLessEqual (a, b)` with `a <= b`.

Change-Id: I4af47fdf5bab57c6bbfe417f55de35b074753120
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70621
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:11:13 +00:00
Felix Singer
5c8a94ae9e ec/lenovo/h8/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntax
Replace `LLessEqual (a, b)` with `a <= b`.

Change-Id: I76855f9d4564fc08cd70456e2a0b1514cd73e35f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70620
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:09:35 +00:00
Felix Singer
8f75d79e74 soc/intel/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax
Replace `LNotEqual (a, b)` with `a != b`.

Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:09:00 +00:00
Felix Singer
49384da933 mb/google/glados/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: Ic3a49828551b6da45999ff55539d5e3449d475e3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70598
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:07:41 +00:00
Felix Singer
01a06b203e mb/google/rambi/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: Ief985f8b7b14e8879a068140cb1f9b28c7336e94
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70597
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:07:16 +00:00
Felix Singer
096158d6e0 mb/google/cyan/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I9441988c0bf6d07641595a3b501c2af5230ba131
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70596
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:06:33 +00:00
Felix Singer
2ed8992d73 mb/google/slippy/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I50c1831c909163b8eb9b91d6ceb267bd8cc41e11
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70595
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:05:15 +00:00
Felix Singer
b6cbda2717 mb/google/jecht/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I74a6c949fa08a6eb712c053137369242e20e78fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70594
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:04:28 +00:00
Felix Singer
edec4d9b9a soc/intel/braswell/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:02:59 +00:00
Felix Singer
26c7672591 soc/intel/baytrail/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 22:01:02 +00:00
Felix Singer
31c099a7b8 soc/intel/icelake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 21:59:12 +00:00
Felix Singer
c1913705ac mb/lenovo/s230u/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I710d9c8c767a688f423d5a7e3e2708eb6aef11fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70587
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 21:58:32 +00:00
Felix Singer
fef71fcebe mb/aopen/dxplplusu/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I4fa3942216f1638abeafa0c562f4d6a2a499254b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70586
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 21:58:08 +00:00
Felix Singer
b8762ae2dc mb/intel/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual (a, b)` with `a == b`.

Change-Id: I99f34d4c03b0687b8e0c2e4aee85f196679bcf52
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 21:45:10 +00:00
Felix Singer
43b5730962 soc/intel/acpi: Replace Decrement(a) with ASL 2.0 syntax
Replace `Decrement (a)` with `a--`.

Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 21:44:41 +00:00
Felix Singer
5cbf2be43a ec/clevo/it5570e/acpi: Replace Index(a, b) with ASL 2.0 syntax
Replace `Index (FOO, 1337)` with `FOO[1337]`.

Change-Id: If035eac6b6eb06f79eb6596364bc41069ba42f70
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 21:43:31 +00:00
Felix Singer
d056d87806 ec/purism/librem-ec/acpi: Use Printf() for debug prints
Change-Id: Ie29511ad0b8e24feb478152009d7f4e8ed3ad26d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2022-12-12 21:42:56 +00:00
Felix Singer
89734cec05 mb/acer/aspire_vn7_572g/acpi: Use Printf() for debug prints
Change-Id: Ie26b623a3848b929b83aad5931b1ecd90b342d2c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2022-12-12 21:42:27 +00:00
Elyes Haouas
8f53e20955 sb/intel/common/acpi_pirq_gen.h: Fix conflicting types for 'is_slot_pin_assigned'
Found using 'Wenum-int-mismatch' (GCC-13: default with -Wall):
src/southbridge/intel/common/acpi_pirq_gen.c:69:6: error: conflicting types for 'is_slot_pin_assigned' due to enum/integer mismatch; have 'bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  enum pci_pin)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  enum pci_pin)'} [-Werror=enum-int-mismatch]
   69 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
      |      ^~~~~~~~~~~~~~~~~~~~
In file included from src/southbridge/intel/common/acpi_pirq_gen.c:8:
src/southbridge/intel/common/acpi_pirq_gen.h:91:6: note: previous declaration of 'is_slot_pin_assigned' with type 'bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  unsigned int)' {aka '_Bool(const struct slot_pin_irq_map *, unsigned int,  unsigned int,  unsigned int)'}
   91 | bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
      |      ^~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

Change-Id: Ie91947d00feaae42314ec2d1291f39d667a85346
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70387
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-12 18:20:55 +00:00
Sean Rhodes
9d1c9ee212 soc/apollolake: Add DPTF HIDs
Add the HIDs that Windows uses for the DPTF driver.

Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 18:20:20 +00:00
Felix Held
b3261661c7 cpu/x86/mtrr/mtrr: fix printk format strings
Commit 4c3749884d ("cpu/x86/mtrr: Print cpu index number when set up
MTRRs for BSP/APs") added the CPU index number to some prints, but used
%x as format specifier. The cpu_index() call however has a return type
of unsigned long, so %lx needs to be used instead. For consistency, also
change the type of the cpu_idx local variable in commit_fixed_mtrrs to
unsigned long and adjust the printk format specifier accordingly.

TEST=The code builds again on my computer

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b68f8355932b2b75db5f453a0a735185b24b02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70664
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 15:21:46 +00:00
Felix Held
d3690ee19c vc/amd/fsp/glinda/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-12 15:19:45 +00:00
Jeremy Compostella
355471aa74 drivers/pc80/vga: Fix coding style issues
- Use `size_t' for iteration index variables
- Use the `VGA_COLUMN' macro definition instead of the hard-coded
  value

BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verified on Skolas

Change-Id: I1d6595871363ec7602219e72d1260df3722f64de
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70453
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-12 15:06:42 +00:00
Kane Chen
4c3749884d cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs
MTRR setup will be assigned to all APs. It's hard to debug
race condition without showing apic id.

Change-Id: Ifd2e1e411f86fa3ea42ed50546facec31b89c3e1
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-12 13:57:24 +00:00
Anil Kumar
f945118f54 soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDT
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb:

device pci 16.0 alias heci1 on  end
device pci 14.2 alias shared_sram off end

This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel

TEST=Built and tested on brya to confirm errors are not seen.
BUG=b:260258765

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:55:46 +00:00
Bo-Chen Chen
7d94b2b489 mb/google/geralt: Add support for MIPI display
Both eDP and MIPI interfaces are supported in geralt project, so we can
initialize the different displays according to the panel ID.

This patch also generalizes the display initialization. So
`configure_edp_panel_backlight` and `power_on_edp_panel` can be removed.

BUG=b:244208960
TEST=test firmware display pass for MIPI panel on MT8188 EVB.

Change-Id: I7ae9318f56c70446516e197635acaffb8197ab53
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70406
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:55:19 +00:00
Bo-Chen Chen
c07ccd9aac mb/google/geralt: Put eDP panel data in panel_geralt.c
Both eDP and MIPI interfaces are supported in geralt project. Therefore,
we put the eDP panel data in panel_geralt.c to have the consistent
interface `get_active_panel` function.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ib35b3cab31bae4109b9715242201425580339536
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:54:55 +00:00
Bo-Chen Chen
49465167a0 mb/google/geralt: Put MIPI panel data in panel_geralt.c
There are eDP and MIPI panels supported in geralt. We put the panels'
specified functions - `power_on()` and `configure_panel_backlight()` in
panel_geralt.c. Also provide the common interface `get_active_panel()`
in panel.c to generalize the display initialization. Since each board
may support a different set of MIPI panels, we put the MIPI data in a
separate file panel_geralt.c.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-12 13:54:24 +00:00
Nick Vaccaro
80f38227cf mb/google/brya: fix GPP_H13 setting for brya0 and skolas
The EN_PP3300_SD gpio (GPP_H13) was configured as a no-connect, but
should be configured as an output.

This change configures GPP_H13 on brya0 and skolas to be an output.

BUG=b:261901759
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot chromeos-bootimage" and verify skolas boots.

Change-Id: Ia3f01e877a5fea3af9a6e746523ed395f3af3b8a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70512
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:53:22 +00:00
Fred Reitberger
694ef4431b soc/amd/morgana: Remove emmc select
Morgana does not have emmc, so do not select it.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:53:02 +00:00
Sridhar Siricilla
d1237da6cc soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
The patch enables CPPCv3 support for Intel Meteor Lake which is based
on hybrid core architecture.

TEST=Build code for Rex.

Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:52:02 +00:00
Arthur Heymans
e0f08727e1 mb/ocp: Provide better defaults for UART
The baudrate of the SOC console is always 57600 and on tiogapass the
0x2f8 COM port is also used by the SOL console.

Change-Id: Ia7bf9fbe10ec66f49c2c7b41938a1a33967c131a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70500
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:51:46 +00:00
Saurabh Mishra
f339b63b02 vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.h
Changes include:
- FirmwareVersionInfoHob.h is removed to use new header file
  FirmwareVersionInfo.h.

BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12 13:50:04 +00:00
Saurabh Mishra
16ba8e12fa soc/intel/meteorlake: Select DISPLAY_FSP_VERSION_INFO_2
Changes include:
- Add config for Meteor Lake SoC to select FirmwareVersionInfo.h
  using 'DISPLAY_FSP_VERSION_INFO_2'

BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-12 13:49:45 +00:00
Saurabh Mishra
997e9f74a1 vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.h
Changes include:
- Add header file FirmwareVersionInfo.h

BUG=b:260183604
BRANCH=None
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:49:31 +00:00
Nico Huber
710a38a26e Makefile: Add default for HOSTPKG_CONFIG
Kconfig uses this variable to detect `ncurses` compilation and
linking flags. Without it, some guesswork fallback is assumed
that only works by chance.

Change-Id: Iad21bdb2d61db04cf7397ab447c7c045e2067705
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-12 13:40:32 +00:00
Angel Pons
9fdd557f56 nb/intel/haswell: Introduce option to not use MRC.bin
Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
booting coreboot on Haswell mainboards without the need of the closed
source MRC.bin. For now, this option does not work at all; the needed
magic will be implemented in subsequent commits. Add a config file to
make sure the newly-introduced option gets build-tested.

Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 13:39:21 +00:00
Angel Pons
f7571c43f8 commonlib/clamp.h: Add more clamping functions
Add more clamping functions that work with different types.

Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64175
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 13:38:11 +00:00
Bo-Chen Chen
58d2947855 mb/google/geralt: Correct the backlight enabled GPIO naming
According to the schematic, we use the same backlight enabled GPIO
naming in eDP and MIPI panels.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: If8d3ca7098c6b22af41861bba74b764d71d27e1b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70403
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 08:27:15 +00:00
Bo-Chen Chen
c5d0c94868 mb/google/geralt: Add support for getting panel id
According to ID table(go/geralt-id), we add panel_id() to read the
panel id from auxadc channel 5.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: I2c0f4ee5a642c41dda9594fbaf2c63f2b2ebac6e
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70402
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 08:26:58 +00:00
Bo-Chen Chen
7e11dcb510 mb/google/geralt: Correct auxadc channel for SKU ID
According to ID table(go/geralt-id), geralt only uses channel 4 for SKU
ID.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: I0f7303b8809e6000e3e16228b00b525a77feee87
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70401
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 08:26:36 +00:00
Leo Chou
5aabdf6e12 mb/google/nissa/var/pujjo: Add wifi sar table
Add wifi sar table for pujjo intel wifi config.
Use fw_config to separate different project settings.

BUG=b:256042825,b:256042769
Test=emerge-nissa coreboot

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ibdbe1c0a477e47af9cbbc9bf73ac583d06ad7a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70480
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 02:47:42 +00:00
Frank Chu
891e6c37a0 mb/google/brya/var/marasov: Disable unused I2C bus
Disable unused I2C2/I2C4 bus for marasov.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id1c41bfdca9b752e3f027e6b071629d67aa06761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70237
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-12 02:26:37 +00:00
Kapil Porwal
843699e3cf drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driver
BUG=b:259716145
TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains
the value from the devicetree on google/redrix.

Before:
    Scope (\_SB.PCI0.WFA3)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x6D,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    ...
    }

After:
    Scope (\_SB.PCI0.CNVW)
    {
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x6D,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    ...
    }

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:31:48 +00:00
Elyes Haouas
3d1b2db1af vc/mediatek/mt8195/Makefile.inc: Remove path to non-existent folder
The directory src/vendorcode/mediatek/mt8195/dramc/include never
existed, and was added in commit b0b8dc37
(vendor/mediatek: Add MT8195 dram initialization code).
Found using 'Wmissing-include-dirs' command option.


Change-Id: Iec349e816a1b646f1ea5fa1db13e05a78ffe1af8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70464
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:30:26 +00:00
Wisley Chen
200f8f7ec8 mb/google/nissa/var/yaviks:Generate SPD ID for supported memory parts
Add new memory parts
- H58G56BK7BX068
- MT62F1G32D2DS-026 WT:B
- K3KL8L80CM-MGCT

BUG=b:261539879
TEST=run part_id_gen to generate SPD id
Change-Id: I74f35d1afad90c3b6a79679a8126904565695fbc
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70410
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:29:54 +00:00
Reka Norman
427ec78932 util/ifdtool/Makefile.inc: Respect LDFLAGS from environment
The ChromeOS build system performs ASAN builds by appending
-fsanitize=address to CFLAGS and LDFLAGS. Currently, the ASAN build of
ifdtool fails with linker errors because the Makefile does not respect
LDFLAGS.

Modify the Makefile to respect LDFLAGS from the environment. This
is consistent with the Makefiles of most other coreboot utils.

BUG=b:255462682
TEST=`USE=asan emerge-nissa coreboot-utils` now succeeds with CL:4018976

Change-Id: I1a497562d4d979829edb47c4c4b3f2c64266324e
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70054
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:29:41 +00:00
Reka Norman
1d49d3e40b mb/google/brya: Don't add MPTS to both DSDT and SSDT
commit 52ccd293d7 ("mb/google/brya: Implement shutdown function for
dGPU") started unconditionally adding MPTS to the SSDT. On variants
with HAVE_WWAN_POWER_SEQUENCE selected, MPTS is already added to the
DSDT via wwan_power.asl. The duplicate definition results in a kernel
error:
ERR kernel: [    0.109237] ACPI BIOS Error (bug): Failure creating named object [\_SB.MPTS], AE_ALREADY_EXISTS (20210730/dswload2-327)
ERR kernel: [    0.109242] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20210730/psobject-220)

Don't add MPTS to the SSDT if HAVE_WWAN_POWER_SEQUENCE is selected.
There are no variants which use both, so this should only result in
empty MPTS methods being removed.

BUG=b:260380268
TEST=On pujjo, the SSDT no longer contains an empty MPTS method, there's
no kernel error, and the WWAN power-off sequence is met.

Change-Id: I9f411aae81ea87aa9c8fc7754c3709e398771a32
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70146
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:29:27 +00:00
Angel Pons
122e1dfe5d soc/intel/alderlake/Kconfig: Sort defaults alphabetically
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions

Swap the position of two lines so that defaults are listed in
alphabetical order according to the PCH type: M, N, P, S.

Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12 01:28:33 +00:00
Joey Peng
5a724a1adc mb/google/octopus/variants/phaser: Implement variant_memory_sku()
This change override memory ID 3 to 1 to workaround the incorrect
memory straps in hardware.
We would use board_id 7 to identify the specific boards which need
to correct the memory ID.

BUG=b:259301885
BRANCH=Octopus
TEST=Verified on Phaser

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2330b7e16a09f8cc76ed96e81a6165afa80a03a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:26:37 +00:00
Felix Held
bd9ab06808 vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this. Also make sure that the address of the lcl_usb_phy
struct is located below the 4GB boundary, so that the truncation to 32
bits won't result in pointing to a different memory location than
intended. In this error case, which I don't expect to happen, print an
error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its
default values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:26:03 +00:00
Yu-Ping Wu
4f30539b47 drivers/mrc_cache: Prevent printing errors in expected use cases
The following are considered "expected" situations, where we shouldn't
print error messages as in other unexpected errors:

1. When the previous boot is in recovery mode, under certain config
   combination the normal MRC cache would have been invalidated.
   Therefore the "couldn't read metadata" error is expected to show in
   the current normal boot. Special-case this situation by printing a
   different message.
2. If the platform doesn't have recovery cache (!HAS_RECOVERY_MRC_CACHE)
   and vboot starts before romstage (!VBOOT_STARTS_IN_ROMSTAGE), then
   there should be no region for recovery cache. In this case, "failed
   to locate region type 0" will be shown. Since it's pretty clear from
   the code that this is the only case for the error to happen, simply
   change it to BIOS_DEBUG. Also remove a duplicate message when
   mrc_header_valid() fails.

BUG=b:257401937
TEST=emerge-corsola coreboot
TEST=Ran `cbmem -1 | grep ERROR` in recovery boot
TEST=Ran `cbmem -1 | grep ERROR` in normal boot following recovery boot
BRANCH=corsola

Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69542
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 00:50:20 +00:00
Tarun Tuli
bf62e977c0 mb/google/brya/var/agah: Correct dGPU Power GPIOs
PP1800_GPU_X should dynamically move from GPP_E18 to GPP_F12
depending on board revision.

PP0950_GPU_X (PEX) should remain on GPP_E10 for all board
revisions.

BUG=b:242752623
TEST=dGPU is functional on both revisions of the board

Change-Id: I20994fcac4d7b98ee893d5eb98b096c037d31d6c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-11 17:15:03 +00:00
Kyösti Mälkki
56395f4883 sb/intel/common: Move definition of TRAP
Both TRAP and TRP0 are now only defined for i82801gx ASL.

This fixes an issue with updating to IASL 20221020, with many
intel platform builds failing with:

  dsdt.asl     38:  TRP0 = 0
  Error    6084 -     ^ Object does not exist (TRP0)

The error was ignored with older IASL.

Change-Id: Ie8a59803f4a27a8315c16bde401f8ca90ee814a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-11 12:43:55 +00:00
Frank Chu
f8fbf0917c mb/google/brya/var/marasov: Change FSP board type to Type3
Change FSP board type to Type3.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
     check MRC log "Maximum requested frequency" is 4800

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I69365bc726b4faac4cedb94cc7b08baa06056c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70439
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 17:56:11 +00:00
Frank Chu
0029840db9 mb/google/brya/var/marasov: Enable PCIe port 5 for WLAN
Enable PCIe port 5 for WLAN device

BUG=b:261514079
BRANCH=firmware-brya-14505.B
TEST=Build and boot on marasov.
     Ensure that the WLAN module is enumerated in the output of lspci.
localhost ~ # lspci
01:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express Wireless Network Adapter

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I007501bb00e2b7b83de1292f3066874d07646cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70442
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 17:55:35 +00:00
Arthur Heymans
6e23da2983 cpu/cpu.h: Change the function signature
There is no need to pass the CPU index around.

Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-10 17:54:53 +00:00
Martin Roth
2db459edb0 /: Update and rewrite README.md
Update the top level readme file to reflect the updated documentation
and project status.

This is mostly a rewrite, but some text was just reformatted.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-10 17:53:53 +00:00
Elyes Haouas
4faa72f39a include/gpio.h: Add 'IWYU pragma: export' comment
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented headers.

Change-Id: Iedd798eebf3376b7631fc9aa1ca0ba92867382bd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70520
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 17:47:31 +00:00
Frank Wu
593ac8d749 mb/google/skyrim/var/frostflow: Add FW_CONFIG definition
Based on the SKU plan, add FW_CONFIG definition.

BUG=b:260473966
BRANCH=None
TEST=emerge-skyrim coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I727f69e8fe340cfe624adb5a49bd080ba9544786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70418
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 17:47:15 +00:00
Subrata Banik
ff433b7176 soc/intel: Move TCSS FW latency macros to IA common tcss.h
This patch moves TCSS firmware latency related macros from SoC
specific tcss.h to IA common tcss.h

Additionally, ensure other structure definitions belonging to the
IA common code tcss.h are not causing compilation issues for ASL files
(due to including FW latency macros) hence, guarded against
`!defined(__ACPI__)`.

TEST=Able to build and boot Google/Rex and Google/Kano.

Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:02:42 +00:00
Subrata Banik
49204e30f3 soc/intel/tigerlake: Move TCSS FW latency macros to tcss.h
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.

TEST=Able to build and boot Google/Volteer.

Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:02:26 +00:00
Subrata Banik
650de58220 soc/intel/alderlake: Move TCSS FW latency macros to tcss.h
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.

TEST=Able to build and boot Google/Kano.

Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:02:19 +00:00
Subrata Banik
9a59858888 soc/intel/meteorlake: Fix typo
This patch fixes typo mistake `Pyhsical` -> `Physical`.

Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:56 +00:00
Subrata Banik
e2828c0a20 soc/intel/meteorlake: Update DPTF participants ACPI IDs
This patch updates DPTF participants' ACPI IDs based on the Intel
Meteor Lake Reference Code.

TEST=Able to build and boot Google/Rex.

Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:40 +00:00
Dinesh Gehlot
5778e06771 soc/intel/meteorlake: Drop casts around soc_read_pmc_base()
The `soc_read_pmc_base()` function returns an `uintptr_t`, which
is then casted to a pointer type for use with `read32()` and/or
`write32()`. But since commit b324df6a54 ("arch/x86:
Provide readXp/writeXp helpers in arch/mmio.h"), the
`read32p()` and `write32p()` functions live in `arch/mmio.h`.
These functions use the `uintptr_t type for the address parameter
instead of a pointer type, and using them with the
`soc_read_pmc_base()` function allows dropping the casts to pointer.

BUG=none
TEST=Build and Boot verified on google/rex

Port of 'commit f585c6eeea ("soc/intel: Drop casts
around `soc_read_pmc_base()`")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:33 +00:00
Dinesh Gehlot
e7c1f7da25 soc/intel/meteorlake: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.

BUG=none
TEST=Build and Boot verified on google/rex

Port of 'commit bc35bed18e ("soc/intel/*: Allow configuring
8254 timer via CMOS")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:24 +00:00
Subrata Banik
1f5154ee8c soc/intel/meteorlake: Fix unknown voltage field in SMBIOS table
This patch fixes the `unknown` voltage field issue in processor SMBIOS
table.

This patch is backported from
commit 30e8fc1f4e (soc/intel/alderlake:
Fix unknown voltage in SMBIOS)

TEST=Able to see meaningful voltage data in the SMBIOS table.

Without this patch:

localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0004, DMI type 4, 48 bytes
Processor Information
	Socket Designation: CPU0
	Type: Central Processor
	Family: Pentium Pro
	 ...
      	Voltage: Unknown

With this patch:

localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0004, DMI type 4, 48 bytes
Processor Information
	Socket Designation: CPU0
	Type: Central Processor
	Family: Pentium Pro
	...
	Voltage: 0.8 V

Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:15 +00:00
Subrata Banik
c0f4b1258d soc/intel/meteorlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...

This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag

This patch is backported from
commit 096ce1444e (soc/intel/alderlake:
Support PCIe hardware compliance test mode)

Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 08:01:09 +00:00
Subrata Banik
64dd9d000e soc/intel/meteorlake: Skip duplicate PCIe RP CLKSRC programming
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.

Add check and skip PCIe CLKSRC programming without a clock structure.
In addition, a root port can not use a free running clock or clock set
to LAN.

Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.

This patch is backported from
commit edf71a08b4 (soc/intel/alderlake:
Skip PCIe source clock assignment if incorrect)

Change-Id: Ie9179880a57796d8595874325203280590d7ee9d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 07:59:57 +00:00
Subrata Banik
3eac04982a soc/intel/meteorlake: Check clkreq overlap
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.

This change adds a clkreq overlap check and shows a warning message.

This patch is backported from
commit ff553ba8b3 (soc/intel/alderlake:
Check clkreq overlap)

Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 07:59:45 +00:00
Subrata Banik
cb3291965d mb/google/rex: Implement S0ix hooks aka MS0X method
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based
on the state of the system while `SLP_S0_L` signal is `low` (while
the system is in S0ix).

Implemented runtime ASL method (MS0X) being called by PEPD device
_DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit.

Scope (\_SB)
{
   Method (MS0X, 1, Serialized)
   {
      If ((Arg0 == One))
      {
         \_SB.PCI0.CTXS (0x75)
      }
      Else
      {
         \_SB.PCI0.STXS (0x75)
      }
}

BUG=b:256807255
TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 07:57:32 +00:00
Elyes Haouas
8823ba1673 treewide: Include <device/mmio.h> instead of <arch/mmio.h>
<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes

Also sort includes while on it.

Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-10 05:07:14 +00:00
Felix Held
8d1ef734a2 mb/google/skyrim: use gpio.h include
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 05:04:25 +00:00
Felix Held
fa0bf5c2a4 mb/google/guybrush: use gpio.h include
Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa82c10d10e4438b0437b78ddd95b5e823805571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70435
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 03:50:23 +00:00
Elyes Haouas
0a7a2694f9 drivers/siemens/nc_fpga/nc_fpga_early.c: Use write32p()
Change-Id: Ic7139f0adc0ce4556268612f5e77eb01738fc068
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10 00:17:19 +00:00
Elyes Haouas
793403c740 lib/ramtest.c: Use {read,write}32p()
Change-Id: I63abe019490f72bd73bcdbddb974aff2b2bfd803
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-10 00:01:05 +00:00
Elyes Haouas
ca20fc3c6d mb/google/{herobrine,peach_pit,trogdor}: Use {read,write}32p()
Change-Id: I2e1978f20b085f609cbeb0907374383f2d11fbf0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 23:59:40 +00:00
Elyes Haouas
60803c12fc drivers/net/atl1e.c: Use {read,write}32p()
Change-Id: Idc9dd4434a8023af4758f921f6279d09059166d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09 23:59:26 +00:00
Elyes Haouas
456482c8ca drivers/generic/bayhub/bh720.c: Use {read,write}32p()
Change-Id: I97b073bfc291b13719a199b277f22b477647db8e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70470
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 23:59:02 +00:00
Jamie Ryu
ed8bdefcdf mb/intel/mtlrvp: Add MTL-P RVP board ids
This adds MTL-P board id definition. Change include,
1. Add board_id.c implementation
2. Add board_id.h implementation
3. Add board_id config in variants.h
4. Makefile changes

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-09 23:57:03 +00:00
Harsha B R
c03cdc143a mb/intel/mtlrvp: Add initial code for mtlrvp_p_ext_ec variant board
This patch adds the initial code for mtlrvp_p_ext_ec variant board
which includes
1. support for 2 mainboards (Chrome EC and Windows EC) by
adding overridetree.cb to corresponding directory
2. Move devicetree to baseboard/mtlrvp_p
3. Update mainboard name in Kconfig and Kconfig.name
4. Add config option to select corresponding overridetree.cb

Subsequent patches include patch train starting from (CB - 66102)

BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
2022-12-09 23:55:04 +00:00
Shaik Shahina
ba3b2f8fd8 vc/intel/fsp: Update ADL N FSP headers from v3343.04 to v3343.05
Update generated FSP headers for Alder Lake N from v3343.04 to v3343.05.

Changes include:
-FspsUpd.h : Update UfsEnable UPD description in comments

BUG=b:228110908
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: Ieff33df2d2b0884a9788e05e06da5bdae1be08de
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70446
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 20:45:46 +00:00
Elyes Haouas
c8acbdc60c mb/system76/tgl-u/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie0e31fcdbeb219d3ecbe14a492d3e7824f6a51cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70397
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 17:09:28 +00:00
Elyes Haouas
1d99076c7d vc/mediatek/mt8192/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I79457d8548700eeb534419f8e41990fad05edb68
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70398
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 17:08:32 +00:00
Arthur Heymans
478da724be drivers/ipmi/ipmi_ops.c: Fix typo in error message
Change-Id: I43c6dc0eb19d9be908c98fb6316f87747605b91e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51798
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-09 17:07:21 +00:00
Yidi Lin
28188e3e8b soc/mediatek/mt8173: Allow BL31 payload not targeting RAM
selfboot.c blocks the payload that does not target RAM. But MT8173 loads
and runs BL31 payload in SRAM. Make the exception by implementing
`payload_arch_usable_ram_quirk()`.

TEST=load and initialize BL31 successfully

Change-Id: I8951b1c4673cdae7d1ad0c11d7d6c12376acd328
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70344
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 17:07:00 +00:00
Frank Chu
68bbbf8db2 mb/google/brya/var/marasov: Add the FIVR configurations
This patch enables V1p05 and Vnn external bypass VRs for Marasov.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Id28305b02e86f5ac55382ac6d2bd5e0453aae9b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-09 17:06:23 +00:00
Frank Chu
fa93c5bd01 mb/google/brya/var/marasov: Adjust the bit fields in the FW_CONFIG
Adjust the bit fields in the FW_CONFIG for Proto Phase.

BUG=b:254404046
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia71269918092655c11c2b37a26ec19123f759650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-09 17:06:07 +00:00
Elyes Haouas
4f3251ed16 vc/eltan/security/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ia6f72acf0ae90c98ccf1fbbeedd7fbf5f194b4cc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70385
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 16:59:44 +00:00
Elyes Haouas
00b8cbd128 sb/intel/ibexpeak/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I7c2217bbe677810d25c5d5d1062320773ee7e0c8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09 16:59:06 +00:00
Elyes Haouas
c25f61f9c7 sb/intel/i82801jx/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I2e69822575e42b322eb971540821f3b87fb7e903
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09 16:58:50 +00:00
Karthikeyan Ramasubramanian
5d5f6822f9 soc/amd/mendocino: Enable LPC SPI DMA
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while
loading various components synchronously.

BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time
improvement of ~20 ms.
Before:
Total Time: 1,503,032
After:
Total Time: 1,485,536

Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 16:48:01 +00:00
Maciej Pijanowski
1a397369ff util/ifdtool/Makefile: improve cross-compilation support
INSTALL and PREFIX variables will not be overwritten. Also, mkdir was
replaced by a tool from the INSTALL variable to be compatible with other
cross-compilation buildsystems (like Yocto).

Overwriting variables generates problems when we use different
buildsystem like Yocto where tool names are stored in environment
variables. This change may make building the utility easier - the user
of different buildsystem will not have to remember to pass correct tool
names when issuing the make command.

Also, this change does not affect the rest of users - if the variable
was not set before, then it will be configured as before.

Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Change-Id: Ia8dd67d18392e1e11d9160b187ef1a874d69ff5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70105
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 11:06:06 +00:00
Maciej Gabryelski
9d2902f750 util/inteltool/Makefile: improve cross-compilation support
Use tool from INSTALL variable to create directory instead of mkdir to
be compatible with other cross-compilation buildsystems (like Yocto).

Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com>
Change-Id: I0b0949d07baae1ae1d7b22ac3d0b8913f81d89c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70104
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 11:05:56 +00:00
Maciej Gabryelski
1fc12db95f util/superiotool/Makefile: improve cross-compilation support
Use tool from INSTALL variable to create directory instead of mkdir to
be compatible with other cross-compilation buildsystems (like Yocto).

Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com>
Change-Id: I9d455f3d1a6d86c88b8e22da825fe14f9630e971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70103
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 11:05:34 +00:00
Maciej Gabryelski
24858b0ba0 util/ectool/Makefile: improve cross-compilation support
Build variables like CC, INSTALL, and PREFIX, should not be
overwritten by the Makefile. This generates problems when we use
different buildsystem like Yocto where tool names are stored in
environment variables. This change may make building util tool
easier - the user of different buildsystem will not have to remember
to pass correct tool names during running the make command.

Also, this change does not affect the rest of users - if the variable
was not set before, then it will be configured as before.

Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com>
Change-Id: If5c88bde0ae00f0211a250906cbdedfe4f59c67b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70102
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 11:05:27 +00:00
Subrata Banik
e0d497a3b6 mb/google/rex: Enable S0ix
This patch enables S0ix for Google/Rex platform.

BUG=b:256807255
TEST=Able to program FADT table Bit 21 (Low Power Idle S0)

Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-09 07:36:15 +00:00
Frank Chu
951fb00d4e mb/google/brya/var/marasov: Remove __weak for memory override
Drop the __weak qualifier as this function is not overridden.

BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ica25b2bc4325ff9d27be672926b4e3b550c86e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-09 06:02:11 +00:00
Tim Chu
1400875123 include/cper.h: Add CPER Memory Error Section definitions
Add Memory Error Section definitions from UEFI Specification rev 2.10
appendix N.2.5. The structure defined here may be used for machine
check handling.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-09 03:46:33 +00:00
Angel Pons
3cc20202de soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function
to allow creating SMBIOS type 17 entries for unpopulated DIMM slots.

Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64036
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 03:44:41 +00:00
Elyes Haouas
d41f69ccce mb/siemens/*/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 01:56:39 +00:00
Elyes Haouas
894f19bdf6 soc/intel/quark/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie079dcf8c1e662ce6ef068befa43dfe90c89edd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70395
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09 01:56:17 +00:00
Julius Werner
3460aa3a42 mem_chip_info: Update to new format
The original version of the mem_chip_info structure does not record rank
information and does not allow precise modeling of certain DDR
configurations, so it falls short on its purpose to compile all
available memory information. This patch updates the format to a new
layout that remedies these issues. Since the structure was introduced so
recently that no firmware using it has been finalized and shipped yet,
we should be able to get away with this without accounting for backwards
compatibility.

BRANCH=corsola

Cq-Depend: chromium:3980175
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68871
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-12-09 00:48:57 +00:00
Felix Held
ee2f0b499b mb/google/zork: use gpio.h include
Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a33dd8821a00b7edfd1e5b593f71bea0e77630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08 18:50:00 +00:00
Felix Held
2cc2bd2d2f mb/google/kahlee: use gpio.h include
Replace the amdblocks/gpio.h, amdblocks/gpio_defs.h and soc/gpio.h
includes with the common gpio.h which will include soc/gpio.h which will
include amdblocks/gpio.h which will include amdblocks/gpio_defs.h in the
AMD SoC case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I13bc33b91f6e6d52867da9043bb386f3befac5fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70433
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08 18:31:30 +00:00
Felix Held
e1f6db512f vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 18:01:38 +00:00
Felix Held
7969a5c1b4 vc/amd/fsp/mendocino/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-12-08 17:57:41 +00:00
Kevin Chiu
cc846838b6 mb/google/brya/var/gladios: Update fw_config STORAGE field
option STORAGE_EMMC 0
option STORAGE_NVME 1

BUG=b:239513596
TEST=FW_NAME=gladios emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-08 16:59:14 +00:00
EricKY Cheng
fd39a8ef1f mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
Enable Dynamic DPTC support.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08 16:01:44 +00:00
EricKY Cheng
429b19962a soc/amd/common/acpi, mb/google/skyrim: Implement DTTS Proposal
DTTS indicated Dynamic Thermal Table Switching.The proposal would like
to develop the schematic for switching 6 thermal table by lid status,
machine body mode and temperature. After entering the OS, the thermal
table would be table A. If the “Motion” or “Lid status change” is
detected. The thermal table would switch to laptop mode or lid close
mode.

Once the higher environment temperatures are detected,the thermal
table would switch to the corresponding power throttle table (B, D or
F). Based on these table switching mechanisms, no matter how the
end-user uses Chromebook,they could enjoy more humanized thermal
designs.

              Release     Over         Over      Release            .
              Temp.       Temp.        Temp.     Temp.              .
--------------------------------------------------------            .
Desktop mode  Table A     Table B      50C       45C                .
Lid open      (Default)                                             .
--------------------------------------------------------            .
Desktop mode  Table C     Table D      55C       50C                .
Lid close                                                           .
--------------------------------------------------------            .
Laptop mode   Table E     Table F      45C       40C                .
--------------------------------------------------------            .

On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E (Release Temp) can switch to each other.
3. B, D, F (Over Temp) can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. If Lid open/close or mode switch event trigger, temperature release
tables will translation to each other, temperature over tables will
translation to each other.After that event trigger, EC will check the
new temperature condition and decide if the temperature need to be
trigger.For example, if table A will switch to table D, table A will
switch to C with Lid close event, if temperature is over 55C, EC will
trigger temperature to switch form table C to D.
6. EC will trigger 3 times body-detection events during power on boot
without any body-mode and lid status change. For this case if the
previous table label is on same group, we will based on the temperature
to decide the table.

For example, assume table A is current table. When the temperature
reaches 50C, than the table is switched from A to B. The current table
is B. When the temperature is downgrade below 45C, the table is
switched form B to A. The same rule is for C and D, E and F.

BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08 16:01:26 +00:00
EricKY Cheng
5d5efaa97c mb/google/skyrim/var/winterhold: update thermal config
Enable STT and set 6 thermal table profiles for Dynamic Thermal Table
Switching Proposal support.

BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-08 15:53:16 +00:00
Felix Held
0a817eb6e2 soc/amd/common/amdblocks/gpio: update amdblocks/gpio_defs.h include
Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since
gpio_defs.h is not only visible in a local scope, but also as
<amdblocks/gpio_defs.h>.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 15:48:55 +00:00
Subrata Banik
6e7e8bffba mb/google/rex: Add MPTS method for WWAN over PCIe
This patch generates the following for the mainboard:

Scope (\_SB)
{
        Method (MPTS, 1, Serialized)
        {
            Local0 = \_SB.PCI0.RP06.RTD3._STA ()
            If ((Local0 == One))
            {
                \_SB.PCI0.RP06.PXSX.DPTS (Arg0)
            }
        }
}

Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 07:48:35 +00:00
Subrata Banik
2a2488fa67 soc/intel/meteorlake: Enable LPIT support
This patch adds SLP_S0 residency registers and enable LPIT support.

Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document.

TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS.

localhost /home # ls -lt /sys/firmware/acpi/tables/
-r--------. 1 root root   254 Dec  5 06:59 APIC
-r--------. 1 root root    84 Dec  5 06:59 DBG2
-r--------. 1 root root 21819 Dec  5 06:59 DSDT
-r--------. 1 root root   276 Dec  5 06:59 FACP
-r--------. 1 root root    64 Dec  5 06:59 FACS
-r--------. 1 root root    56 Dec  5 06:59 HPET
-r--------. 1 root root   148 Dec  5 06:59 LPIT
-r--------. 1 root root    60 Dec  5 06:59 MCFG
-r--------. 1 root root 21078 Dec  5 06:59 SSDT
-r--------. 1 root root    76 Dec  5 06:59 TPM2

Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 07:43:48 +00:00
Subrata Banik
85e619c514 soc/intel/meteorlake: Implement SoC override to set CPU privilege level
This patch implements SoC overrides to set CPU privilege level for
Meteor Lake SoC.

Change-Id: I33794f51e57dd8e0ffe61dfd2f91c6ef3f9187c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70352
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 07:38:02 +00:00
Subrata Banik
0fbbdfe60e soc/intel/meteorlake: Add missing entry for GSPI2
This patch adds missing ASL entry for GSPI2 device.

Change-Id: I8f8410947b77d1a9bab2fa5929f30c803a78266d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70354
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-08 07:36:51 +00:00
Arthur Heymans
d90154c8de soc/intel: Set IO APIC DMAR entry based on hw
This avoids the need to hardcode the IOAPIC ID.

Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-07 23:03:04 +00:00
Arthur Heymans
f1e78a1349 arch/x86/ioapic.c: Move macros to compilation unit
Some of these macros are too generic like "NONE" and create conflicts in
other compilation units.

Change-Id: I6131a576f115df20df4d3df712d4c3f59c6dceb7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70429
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07 23:01:51 +00:00
Kevin Chiu
b2a6151299 mb/google/brya/var/lisbon: Update fw_config STORAGE field
option STORAGE_EMMC 0
option STORAGE_NVME 1

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Idd52112743ee0d64aca630e54511503607770d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-07 16:02:56 +00:00
Matt DeVillier
4862d53ff2 mb/google/glados/var/lars: Set SKU ID based on VPD
LARS has two variants, LARS and LILI, which are differentiated via
the customization_id field in the VPD. To make differentiation easier
outside of ChromeOS (ie, for Windows/Linux drivers), set the SKU ID
based on VPD so it can be easily read via SMBIOS.

Modeled after similar code in google/reef (snappy variant).

TEST=build/boot lili variant, verify sku1 populated in SMBIOS tables.

Change-Id: I148462b6f86b25fa8db26ea6e1537d1a5e47984b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07 16:02:02 +00:00
Felix Held
96fa6a24d8 soc/amd/common/block/acpi/ivrs: read IOAPIC IDs from hardware
TEST=IVRS table doesn't change on amd/mandolin

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5be04bc91425480992fcad12f8720738f9ca490e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70357
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07 15:35:02 +00:00
Kyösti Mälkki
521e0460e4 sb,soc/intel,mb: Drop leftover comments and TODOs in ASL
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07 11:33:38 +00:00
Kyösti Mälkki
2c3ebd8b9d mb,sb,soc/intel: Drop useless IO trap handlers
There are four requirements for the SMI to hit a printk()
this commit now removes.

Build must have DEBUG_SMI=y, otherwise any printk() is a no-op
inside SMM.
ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value.
Platform needs to have IO Trap #3 enabled at IO 0x800.
The SMI monitor must call io_trap_handler for IO Trap #3.

At the moment, only getac/p470 would meet the above criteria
with TRAP(0x32) in its DSDT _INI method. The ASL ignores any
return value of TRAP() calls made.

A mainboard IO trap handler should have precedence over
a southbridge IO trap handler. At the moment we seem to have
no cases of the latter to support, so remove the latter.

Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07 11:23:15 +00:00
Kyösti Mälkki
3c528f2830 mb/*/smihandler.c: Drop unused <soc/nvs.h>
Change-Id: I4819909cf9460ca550af38ca73a50220b77a385f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07 04:52:10 +00:00
Kyösti Mälkki
791f7a4f63 mb/lenovo/t60,x60: Split dock_(dis)connect() function
Avoid calling a function named mainboard_io_trap_handler() when
the dock (dis)connect is not triggered from IO trap.

Change-Id: Idc258a390f2de2c32d38a0e35fcce896d058d1b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07 04:51:39 +00:00
Kyösti Mälkki
dbbbb8f5c1 util/autoport: Drop lenovo mainboard_io_trap_handler()
See commit cfc93cbb66 ("mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitialization")

Change-Id: I540c543be027410f387803e8194fb71012cc5063
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07 04:51:05 +00:00
Kyösti Mälkki
a0720431b4 sb,soc/intel: Fix SMI handler IO trap data mask
Shift is done in multiples of 8 (1 << 3) bits.
It was fixed already for i82801ix/jx.

Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-07 04:50:40 +00:00
Julius Werner
7a9bd2b2e4 vboot: Force config file inclusion with CBFS integration
CONFIG_VBOOT_CBFS_INTEGRATION images are signed differently than normal
images. futility needs to be able to tell this difference, and it parses
the `config` file included in CBFS to do this. This change codifies that
dependency in Kconfig so that nobody can accidentally break this by
turning off config file inclusion.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2b2d245b850bc65abb4e72f20b4e360312c828f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70157
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07 02:38:50 +00:00
Julius Werner
4924e42275 build: Combine "savedefconfig" and "stripped config" in CBFS config
The intention of CB:69710 was that the expanded config file introduced
there would be a strict superset of the old version and could be used in
all the same cases. This is generally true except for a small oversight:
if a boolean Kconfig is `default y`, but was manually set to `n` by the
user, the new `config` file does not include a line for it. Running
`make olddefconfig` on such a file will again introduce the option as
`y`. It turns out that `make olddefconfig` actually parses those
"load-bearing comments" in that case.

This patch fixes the problem by also generating the minimal defconfig
(like before CB:69710), and then just appending the non-comment lines
from the full config that don't appear in it already. This ensures that
any "load-bearing comments" in the defconfig remain in the file and the
result of Kconfig utilities regenerating a full config from there will
again be the same as before CB:69710. In addition, it clearly separates
the "minimal defconfig" part of the file from the rest, making it easy
for people to extract that if they need it; while also keeping all the
config values in one file to make it easy to grep for a certain value.

Also eliminate that random backslash in the recipe that doesn't seem to
have any good reason to exist and was probably a typo to begin with.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I52ba5d20d3536498fae79d529acf7135f97ef1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-07 02:38:40 +00:00
Kyösti Mälkki
d5c5b5233d sb,soc/amd: Remove unused southbridge_io_trap_handler()
At the moment IO trap is not implemented for AMD platforms.

Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 23:24:48 +00:00
Angel Pons
2b48258865 arch/x86/smbios.c: Allow creating entries for empty DIMM slots
Properly handle meminfo DIMMs with `dimm_size` of 0, which represent
empty slots. This allows platform code to create dummy meminfo DIMMs
so that SMBIOS tables have type 17 entries for empty DIMM slots.

Change-Id: I17ae83edf94483bd2eeef5524ff82721c196b8ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64035
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 21:27:27 +00:00
Reka Norman
7b5a93153a drivers/intel/fsp2_0: Update MRC cache in ramstage
Currently the MRC cache is updated in romstage, immediately after
returning from FSP-M. Since cbmem is not cached in romstage, the update
is slow (~6 ms on nissa). Specifically, the new MRC data returned by the
FSP is stored in the FSP reserved memory in cbmem, so hashing the new
data is slow.

Move the MRC cache update to ramstage, where cbmem is cached. On nissa,
this saves ~5 ms of boot time.

Before:
552:finished loading ChromeOS VPD (RW)                631,667 (16)
  3:after RAM initialization                          637,703 (6,036)
  4:end of romstage                                   650,307 (12,603)

After:
552:finished loading ChromeOS VPD (RW)                631,832 (15)
  3:after RAM initialization                          633,002 (1,169)
  4:end of romstage                                   645,582 (12,580)

In ramstage, save_mrc_data() takes ~138 us.

BUG=b:242667207
TEST=MRC caching still works as expected on nivviks - after clearing the
MRC cache, memory is retrained on the next boot, but cached data is used
on subsequent boots.

Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-06 21:16:24 +00:00
Elyes Haouas
c4fbeacd01 soc/intel/common/block: Use readXXp/writeXXp()
Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:53:34 +00:00
Elyes Haouas
af776d8b66 sb/intel/bd82x6x: Use {read,write}32p
While on it, sort includes.

Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:51:17 +00:00
Elyes Haouas
067642d939 sb/amd/pi/hudson: Use {read,write}16/32p()
Change-Id: Ic8621a18a1b3c299c3d6eb7b4bff39f1ff7d8492
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:48:01 +00:00
Elyes Haouas
a361d35b8d nb/intel/pineview: Use read32p()
Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:46:17 +00:00
Elyes Haouas
9a83eae71e nb/intel/haswell: Use {read,write}32p()
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:45:59 +00:00
Elyes Haouas
a2389ef316 nb/intel/x4x: Use read32p()
Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:45:05 +00:00
Elyes Haouas
421f1ee294 nb/intel/e7505: Use read32p()
Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:41 +00:00
Elyes Haouas
4b7d4054d9 nb/intel/sandybridge: Use read{8,32}p()
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:26 +00:00
Elyes Haouas
285bf097ab soc/cavium/cn81xx: Use read64p()
Change-Id: Ia79816ccc230d17dd1ce2bde7a185b4d502ad107
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:44:06 +00:00
Fred Reitberger
f68bd1273b mb/amd/birman/gpio: Change non-GEvent GPIOs to PAD_INT
Two GPIOs were set as SCI, but are not GEvent capable pins on morgana.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I00dc1b2595c047ce6898b394061d119ac8680755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 19:43:24 +00:00
Sean Rhodes
5d029bbb90 mb/starlabs/lite/{glk,glkr}: Adjust THERMTRIP GPIO
Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as
in it's current configuration, it stops the laptop entering S5.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-06 19:30:12 +00:00
Arthur Heymans
bc8f859b2d acpi/acpi.c: Add a method to generate IOAPIC DMAR entries from hw
This reads back the ioapic id from hardware.

Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70267
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 17:44:20 +00:00
Arthur Heymans
8a3e2b8364 soc/intel/xeon_sp: Read ioapic configuration from hardware
This is more robust than hardcoding whathever FSP has set up and is a
lot less code.

Change-Id: I6423ddc139d742879d791b054ea082768749c0a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 17:06:35 +00:00
Fred Reitberger
8a979d92c9 mb/amd/mayan/gpio: Configure mayan GPIOs
Configure mayan GPIOs per schematic 105-D59700-00A Rev 1.00

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06 17:02:39 +00:00
Kapil Porwal
f90ceb4c3c mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device
DmaProperty must only be present on endpoint devices.

BUG=b:259716145
TEST=TBD

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 16:58:05 +00:00
Arthur Heymans
a3204f7278 google/veyron: Fix old style function definition
Function definitions without a type a deprecated in all versions of C.

Change-Id: I2efb42e653b0deb56ba6b0c9789764a9cabc552e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70138
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06 16:32:36 +00:00
Elyes Haouas
33e9e44a17 vc/cavium/bdk/libbdk-arch/bdk-numa.c: Fix old-style function definition
Change-Id: Ia56f813933143ef69c97f1b7643693c6eade6abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-12-06 16:18:59 +00:00
wanghao11
f38992e608 drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_init
Add retry up to 10 seconds maximal in ipmi_get_device_id.
Without this retry, on OCP Craterlake with BMC version v2022.28.1,
there's a chance that ipmi_get_device_id failed then ipmi device
won't be enabled.

Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-06 15:20:18 +00:00
Michał Kopeć
9c4ae9131c soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurable
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.

Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 15:18:45 +00:00
Arthur Heymans
34a7e66faa util/cbfstool: Add a new mechanism to provide a memory map
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.

This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.

TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.

Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-06 15:09:09 +00:00
Elyes Haouas
ee4646e70e nb/intel/sandybridge: Use write32p()
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-06 15:06:27 +00:00
Harsha B R
a5e04af484 src/ec/intel: Create common code for board_id implementation
This patch creates initial common code structure for board_id
implementation for intel rvp platforms. Board_id helps in
identifying the platform with respect to CHROME_EC and INTEL_EC
(Windows_EC). Changes include
1. Create initial board_id.c and board_id.h
2. Modify the Makefile to include src/ec/intel directory

BUG=b:260654043
TEST=Able to build with the patch and boot the mtlrvp platform with the
subsequent patches in the train

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-06 08:55:57 +00:00
Bora Guvendik
a6f6e6a592 vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.12
The headers added are generated as per FSP v3361.12

BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: Id7986017e1256627027a45325238bf29e0c00cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-05 21:10:26 +00:00
Angel Pons
69a8a53005 soc/intel/common/block/uart: Show ACPI UART in OS
Do not hide UARTs in ACPI mode from the OS, as this prevents using them
on at least Windows. Currently, the driver is only used on the Prodrive
Hermes mainboard.

Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 16:05:44 +00:00
Sergii Dmytruk
0a89d5237e security/tpm: remove tis_close()
This function was never called from outside of drivers and
src/drivers/pc80/tpm/tis.c was the only one doing it in a questionable
way.

tpm_vendor_cleanup() also isn't needed as one of tis_close() functions
was its only caller.

Change-Id: I9df76adfc21fca9fa1d1af7c40635ec0684ceb0f
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05 14:46:43 +00:00
Elyes Haouas
2393ad0bfb Makefile.inc: Use 'Wold-style-definition'
Warn when a definition is using '()' instead of '(void)'.
Use of ‘()’ is considered an old-style definition in C1x standards,
but probably not in C2x.

Change-Id: I734cfffe3e89996ab13e846cc08e13753f24f742
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:44:27 +00:00
Martin Roth
9fc96407e2 Makefile: Add printall as a NOCOMPILE target
Previously, running "make printall" when there was no .config available,
the system would give an error that printall wasn't a valid target. This
is because it was only in an invalid if clause.  This change adds it to
the other branch of the if clause so it will print out a notice of what
the issue is.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I20670ae875be67ac2edf877c53de4702c4fc7c7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:42:19 +00:00
Martin Roth
5161b2ffa7 util/genbuild: Fix style & shellcheck issues
There shouldn't be any change to functionality here - this should be
strictly cleanup.
- STYLE: Put variables inside braces.
- SHELLCHECK: Instead of 'var= ' to clear a variable, use 'var=""'
- SHELLCHECK: Put commands and command variables inside quotes.
- SHELLCHECK: Don't use variables inside the printf commands.
- OTHER: COREBOOT_BUILD needed a date format when the variables in the
our_date() function were put into quotes.  This format matches the
output of 'LANG="" LC_ALL=C TZ=UTC0 date'

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3303caee5c7a53c9df579e6f48d2c3d075a8c278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-12-05 14:41:52 +00:00
Martin Roth
8a79a89ec4 util/genbuild_h: Update version calculation
- 'git describe --match [0-9].[0-9]*' was giving me an error, so use
the basic 'git describe' command instead.
- If a .coreboot-version file exists, use that to determine the version.
This fixes the problem for coreboot releases.
- Don't run git for the versions unless it's being built from a valid
git repository.  Use 0.0 as the default version for timeless or unknown.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5fae2f012cc9b9914d8803af8dd58a885358cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:41:22 +00:00
Angel Pons
def3c5ccab soc/intel/tigerlake: Fix setting HyperThreading
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.

Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:38:11 +00:00
Jonathan Zhang
a3311b9f0f acpi/acpi.c: update ACPI table revisions
Update SRAT table revision to 3 according to ACPI spec.

Add CEDT table revision according to CXL spec.

Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-05 14:34:55 +00:00
Fred Reitberger
64bfc675a5 mb/amd/mayan: Improve naming of EC FW
Change the EC FW CBFS filename prefix to a more accurate "ec/"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:45 +00:00
Tim Van Patten
868c8873ef google/skyrim/Kconfig: Enable DPTC for Morthal
Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable
support for the low/no battery boot feature.

BUG=b:217911928
TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov

Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:33 +00:00
Kapil Porwal
65bcb57eea soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD
BUG=b:259716145
TEST=Verified SSDT on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:32:04 +00:00
Fred Reitberger
9b592f70d6 soc/amd/common/block/include/gpio_defs.h: Fix documentation
Fixing documentation of PAD_INT macro and replacing spaces with a tab to
match the rest of the documentation.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-05 14:31:04 +00:00
Kapil Porwal
7543627f1b acpi: Helper functions to add certain _DSD properties
BUG=b:259716145
TEST=Verified SSDT on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70063
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:30:57 +00:00
Hsuan Ting Chen
06cd7dbe4c commonlib: Add essential comments for ELOG_CROS_DIAG_RESULT
ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum
definition of enumerated histograms.

Hence add comments based on the requirements of enum histograms in
histogram guidelines.

BUG=b:4047421
TEST=none

Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70145
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:28:32 +00:00
Elyes Haouas
7bde4e80be superio/ite/it8772f/chip.h: Use 'bool' when appropriate
Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:28:02 +00:00
Elyes Haouas
9180bae9b2 superio/aspeed/ast2400/chip.h: Include <stdbool.h>
Change-Id: Ib4a0d77e7bb4cb52e91a5965cae0a6c7ddc40090
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:27:45 +00:00
Cliff Huang
0405dbed77 mb/intel/adlrvp: Add RTD3 support for PCIe slot1
Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec

BUG=none
BRANCH=firmware-brya-14505.B

TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
2022-12-05 14:27:33 +00:00
Fred Reitberger
3b45454329 MAINTAINERS: Add AMD mayan reference board
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I85d4d4fe11f0b579c2327f3d1dfce90229ca9dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:26:46 +00:00
David Wu
a874830dcc mb/google/brya: Set power limit values for kano and zydron
Add the RPL CPU power limits to kano and zydron's power limit table.

BUG=b:261127266
BRANCH=brya
TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with
image-zydron.serial.bin and verify zydron boots successfully to kernel.

Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:26:23 +00:00
Bo-Chen Chen
35693c5028 soc/mediatek/mt8188: Add support for MIPI panel
We need to add DSI and MIPI_TX settings to support MIPI panel.

BUG=b:244208960
TEST=emerge-geralt coreboot

Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:58 +00:00
Bo-Chen Chen
bb4c9ca2d6 soc/mediatek: Fix DSI register definition for MT8186
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.

BUG=b:244208960
TEST=build pass
BRANCH=corsola

Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:37 +00:00
Bo-Chen Chen
b1e7adeca1 soc/mediatek/mt8188: Add display data path for MIPI output
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.

BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.

Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:25:00 +00:00
Arthur Heymans
f9679c4287 nb/intel/gm45: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:37 +00:00
Arthur Heymans
31ba9356b8 nb/intel/i945: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:23:13 +00:00
Arthur Heymans
803029685f nb/intel/x4x: Remove apic 0 from devicetree
This is added at runtime.

Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05 14:22:39 +00:00
Arthur Heymans
98c92570d9 cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.

This removes the need for a magic lapic in the devicetree.

Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05 14:22:12 +00:00
Matt DeVillier
6f573217a0 mb/google/zork: Select VBOOT by default
Zork boards will not boot without PSP verstage/VBOOT, so select it
by default.

Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 14:19:56 +00:00
Arthur Heymans
759448893c soc/nvidia/tegra210: Fix flushing SPI fifo
This will avoid clearing the other bits in fifo_status.

Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05 14:19:03 +00:00
Dinesh Gehlot
e29dcdcdd8 soc/intel/meteorlake: Add timestamp for cse_fw_sync
The patch adds timestamp around cse_fw_sync().

BUG=none
TEST=Verified on rex, cbmem -t:

948:starting CSE firmware sync 	1,340,551 (50,657)
949:finished CSE firmware sync 	1,379,348 (38,797)

Port of 'commit b647e35119 ("soc/intel/alderlake: Add timestamp
for cse_fw_sync")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05 11:33:12 +00:00
Subrata Banik
cd6a45029e mb/google/rex: Add PCIe based SD controller
This patch adds PCIe based SD controller at RP 7 (from RP 11) with
Proto 1 schematics dated 11/30.

Additionally, added the RTD3 entries for the SD controller.

Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in
bootblock and SD_PERST_L (GPP_D02) is configured in romstage to
meet the power cycle requirement.

BUG=b:242917011
TEST=Able to build and boot Google/Rex. SD card detection is due
for the Proto 1 hardware.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-03 07:34:55 +00:00
Subrata Banik
8ca7d26626 mb/google/rex: Drop board_id check while configuring GPIO
This patch drops the usage of reading `board_id()` while performing
the GPIO configuration.

The reason to drop the board_id check is to ensure that GPIO
configuration for MLB (mainboard) would remain the same and the only
GPIO PIN configuration that differs would be due to usage of having
different DBs (daughter board) which will be taken care using
CBI (and fw_config.c file) in coreboot.

Additionally, drop unused early GPIO default configuration table.

BUG=b:260804656
TEST=Able to perform the GPIO configuration and able to boot
Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-03 07:34:34 +00:00
Subrata Banik
db59e48870 mb/google/rex: Add probed fw_configs to SMBIOS OEM strings
Enable this feature, and it can use the probe statement in devicetree
to cache of fw_config field as oem string.

TEST=With CBI FW_CONFIG field set to 0x1561

localhost ~ # dmidecode -t 11
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
	String 1: AUDIO-MAX98357_ALC5682I_I2S
	String 2: CELLULAR-CELLULAR_PCIE
	String 3: UFC-UFC_MIPI
	String 4: WFC-WFC_MIPI
	String 5: DB_SD-SD_GL9755S

Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03 07:34:11 +00:00
Shelley Chen
e233fc7ac1 mb/google/herobrine: NVMe id determined by logical (not physical) bit
NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it.  Previously, I thought that it was tied to a
physical pin, but this is not correct.

BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
     initialized in coreboot.

Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03 01:04:20 +00:00
Sridhar Siricilla
dddaeed4c1 soc/intel/alderlake: Update cpu and pch tracehub modes
The patch gets the cpu and pch's tracehub mode from the debug area
of the Descriptor Region and updates the respective UPDs.

TEST=Build, verify the tracehub mode values.

Update CPU' and PCH's Trace Hub modes:
	img=coreboot.rom
	printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc
	printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc

Check coreboot logs:
    [DEBUG]  rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-02 18:01:06 +00:00
Tim Crawford
8e3787eaf0 mb/system76/tgl-h: Convert oryp8 to a variant
Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 15:53:49 +00:00
Jonathon Hall
def33cc5bb mb/purism/librem_14: Enable both lanes of left side USB 3.0 port
Fixes using USB-C devices in either orientation on left-side USB-C
port.

Test: Plug USB-C device in both orientations on left-side USB-C port,
check speed with lsusb -t.

Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:49:13 +00:00
Eran Mitrani
13e151f31c soc/intel/alderlake: skip external buses for D-states list
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)

BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents

Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:48:37 +00:00
David Wu
50a3265017 mb/google/brya/var/zydron: Add WiFi SAR table
Add WiFi SAR table for zydron.

BUG=b:260770999
TEST=build FW and checked SAR table can load by WiFi driver.

Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:48:02 +00:00
Lean Sheng Tan
e98dd0aad8 mb/prodrive/atlas: Enable GPP_B14 buzzer support
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required
for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using
8254 timer counter 2 output. However when 8254 timer is used, S0ix
will not work as 8254 has to be gated instead. For further info on
s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified
Checklist).

This CL also disables s0ix because it is not required by the
platform.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:47:36 +00:00
Lean Sheng Tan
998fdc06cb mb/prodrive/atlas: Add DP++ support
Update VBT configurations for DP++ and DP dongles support.

Tested working on customer's side.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:46:39 +00:00
Lean Sheng Tan
08596f50b7 3rdparty/fsp: Update submodule pointer to latest master
Here are the FSP updates with latest master:
- IoT EHL MR5
- IoT ADL-P MR2
- IoT ADL-S MR3
- IoT ADL-PS PV
- IoT TGL MR7

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If4a76fe25c7b7a2c34e5bb284418c01c77b22abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70153
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:45:57 +00:00
Kapil Porwal
96c605f39a soc/intel/meteorlake: Refactor pmc_lockdown_cfg function
This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.

This patch also locks PMC features like:
1. Debug mode configuration and host read access to PMC XRAM.
2. PMC soft strap message interface.
3. PMC static function.
and then calls into the PMC IPC function that informs about PCI
enumeration.

Port of -
1. commit 2eec87a553 ("soc/intel/alderlake: Refactor
`pmc_lockdown_cfg` function")
2. commit bae4a0b5a1 ("soc/intel/alderlake: Implement PMC
feature lock")
3. commit c2570dc998 ("soc/intel/alderlake: Implement PMC
soft strap interface lock")
4. commit f021952c40 ("soc/intel/alderlake: Implement PMC
static function lock")
5. commit 4578914153 ("soc/intel/alderlake: Call into PMC
IPC to inform PCI enumeration done")

BUG=none
TEST=Boot to OS on google/rex.

Register values in OS -
# busybox devmem 0xfe0018d4 32 #bit31
0x80000000
# busybox devmem 0xfe001024 32 #bit21,18,17,4
0x00362610
# busybox devmem 0xfe001818 32 #bit27,22
0x2B4F0004
# busybox devmem 0xfe00104c 32 #bit0
0x00000001


Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:45:23 +00:00
Elyes Haouas
a521d66116 nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock
Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02 14:44:41 +00:00
Elyes Haouas
5a845ee894 nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'
'gpu_lvds_use_spread_spectrum_clock'is only used on i945.

Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:40:22 +00:00
Elyes Haouas
dc3beea75d sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02 14:39:56 +00:00
Elyes Haouas
87a98b55b2 nb/intel/pineview: Use {true,false} instead of {0,1}
"use_crt" and "use_lvds" are boolean, so use "true/false".

Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 14:33:16 +00:00
Tim Crawford
976050113e mb/system76/adl-p: Disable SATA DevSlp
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in
system76/ec@cc3effb6a4 ("board/system76/common: use SLP_S0# pin for
modern standby detection"), DevSlp blocks suspend entry. Disable it
until it is fixed.

Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:30:51 +00:00
Tim Crawford
fa2c118af4 mb/system76/adl-p: Add Galago Pro 6 as a variant
The Galago Pro 6 (galp6) is an Alder Lake-P board.

Tested with a custom edk2 UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- All USB ports
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.0.6
- Internal flashing with flashrom v1.2-1087-gde016a17

Not working:

- Detection of devices in TBT slot on boot

Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:30:25 +00:00
Tim Crawford
5b7b04c938 mb/system76/cml-u: Convert lemp9 to a variant
Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02 14:29:53 +00:00
Martin Roth
1ef3779516 mb/google/herobrine: Update FMD file for multiple ROM sizes
The Piglin & Hoglin boards were built with a couple of different sizes
of ROM chips.  Despite this, the desire was to use just a single FMD
file.  The different sizes are already accounted for in Kconfig, so
add the Kconfig size here to be used.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02 14:29:11 +00:00
Patrick Georgi
3d4b1710eb kconfig2html: Denote that the script is python3
`python` as a command isn't universally available anymore after the
python2/python3 drama.

Change-Id: I9d68873d86dc3f044238d921c10fc434a83a76f5
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:34:14 +00:00
Patrick Georgi
a6dedb8c22 board-status: Implement handling of "Clone of"
Change-Id: Ifb728ebb5d0e98b0c8a59f3bd8803ce193a05e5f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:34:01 +00:00
Patrick Georgi
52941673b1 board-status: Remove shell version, update docs
Change-Id: I532db49799eadf3214a70297c5fc84aa006bc3f7
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02 08:33:54 +00:00
Subrata Banik
b955304869 soc/intel/meteorlake: Allow sending late EOP cmd to CSE
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.

BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time

Without this patch:

942:before sending EOP to ME	1,795,702 (354)
943:after sending EOP to ME	1,950,526 (154,824)

With this patch:

942:before sending EOP to ME	2,051,406 (35,484)
943:after sending EOP to ME	2,057,583 (6,177)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:52:07 +00:00
Subrata Banik
adbef6d2b3 soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.

Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.

BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-12-02 07:51:58 +00:00
Subrata Banik
17a3da8b99 soc/intel/cmn/cse: API to perform essential CSE operations post EOP
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.

Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.

BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:52 +00:00
Subrata Banik
5214c4091f soc/intel/cmn/cse: Send EOP cmd from .final aka cse_final()
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.

This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.

1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations

Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.

BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:42 +00:00
Subrata Banik
bed82b0c40 soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.

1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.

During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).

Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.

The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.

Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.

The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.

BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 07:51:36 +00:00
Felix Singer
52191f2123 util/crossgcc/buildgcc: Disable LLVM_INCLUDE_{TESTS,EXAMPLES}
Building of LLVM tests and examples is enabled by default, but they are
not necessary. Thus disable them.

Change-Id: I58b09e276967e97856da65e5876b27f0bae3f0cc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:54:05 +00:00
Felix Singer
f8157af3aa util/crossgcc/buildgcc: Use one line per configure option
To improve the readability and visibility of the configure options, move
each of them to a separate line.

Change-Id: Ifc39e4d0849d220d85e1d9ce92fc008fec610694
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:53:40 +00:00
Felix Singer
3e7438b001 util/crossgcc/buildgcc: Put configure option before target dir
Change-Id: If1b724f9c9b4d2a8ce166946794c1c0882ad1653
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-02 06:53:00 +00:00
Wisley Chen
7b1e7c30a7 mb/google/brya/var/anahera: Adjust I2C5 timing for touchpad
Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet
touchpad SPEC.

BUG=b:260540852
BRANCH=firmware-brya-14505.B
TEST=build, checked TP function work normally,
and measure the timing meet SPEC
tLOW  ~1.72 us
tHIGH ~0.63 us
tHD   ~0.69 us
fscl  383 kHz

Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-02 05:16:51 +00:00
Lawrence Chang
cab2c53e3c mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system.

BUG=b:256538132
TEST=executed 3000 cycles of cold boot successfully

Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 03:11:41 +00:00
John Su
69cab3a044 mb/google/skyrim/var/frostflow: Enable DPTC support
Enable DPTC support for frostflow.

BUG=b:257187831
TEST=emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02 01:49:12 +00:00
Nicholas Chin
9eab93168d util/kconfig/README.md: Add notes about adding a new quilt patch
The patches for kconfig need to be in a format compatible with the quilt
tool, and usually also contain a header with some additional info like
the git commit. This header is in the same format as patches produced by
`git format-patch`, but the diff style git uses is incompatible with
quilt and there does not seem to be a straightforward way to format the
diff section to work.

Add some documentation for a method I found to go from a git commit to a
quilt compatible patch with git headers.

Change-Id: I7a8bbe41e0864be1d28116742b6b8b3fc440cc31
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-01 22:12:29 +00:00
Jakub Czapiga
a7f669049d vboot: Allow for comparison of hash without zero-padding
Adjust asserts to allow to store and compare (at S3 resume) hashes
without padding to maximum hash length / slot size.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01 22:12:16 +00:00
Jakub Czapiga
d27fff5923 vboot/vboot_common: Fix vboot_save_data() code exclusion guard
Compilers are not optimizing-out code correctly. This patch fixes
incorrect behavior by splitting if statement and extracting code to
another function, this allowing for better code size optimization and
reduction of undefined references.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-01 22:12:10 +00:00
Raymond Chung
3e6abc98d5 mb/google/brya/var/gaelin: Configure audio in devicetree
Refer to brask board to add audio settings for gaelin.

BUG=b:253177160
BRANCH=firmware-brya-14505.B
TEST=Able to verify audio playback on gaelin with kernel v5.10.

Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01 20:14:12 +00:00
Raymond Chung
7c9753c8ce mb/google/brya/var/gaelin: Add camera module settings
Modify USB2.0 port[4] settings to support camera.

BUG=b:238252678
BRANCH=firmware-brya-14505.B
TEST=with brask overlay changes, camera in camera app works

Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01 20:13:51 +00:00
Subrata Banik
67dbbeaa30 soc/intel/alderlake: Drop duplicate macro PCH_PWRM_BASE_SIZE
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'

`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.

BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01 16:52:03 +00:00
EricKY Cheng
366b205f2d ec/google/chromec: Add DPTC support for host event 1/2/9
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for
host event lid-open/lid-close/Thermal Threshold.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-12-01 15:42:49 +00:00
Mario Scheithauer
23d224069f mb/siemens/mc_ehl2: Disable GSPI2 controller
GSPI2 interface is not used on this mainboard and can be disabled. It
will in addition remove the warning of a leftover static device in the
log.

Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-01 14:05:56 +00:00
Felix Held
d672b5fdd8 mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos case
Commit 2c102232e8 ("mb/amd/chausie,google/skyrim: increase
RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with
the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte
flash size, the amdfw part won't be placed on the expected position,
since the cbfs header is in that exact location and cbfstool places the
amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for
the non-chromeos builds to work around this.

TEST=Non-chromeos chausie build now boots and doesn't fail any more
before releasing the x86 cores from reset

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01 14:04:50 +00:00
Leo Chou
faa0d638dc mb/google/nissa/pujjo: Add new audio sku configure
Add new audio sku configure for Pujjo board.

BUG=b:260538412
TEST=Boot to OS on pujjo and check that audio are configured
based on fw_config.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01 14:04:01 +00:00
Arthur Heymans
1eecb8c814 nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01 10:28:10 +00:00
Arthur Heymans
22d6ee8d9c nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01 10:28:03 +00:00
Arthur Heymans
2fb6f68ef0 nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01 10:27:52 +00:00
Arthur Heymans
ea6a3b488c util/autoport: Update devicetree generation
CPU nodes are now declared in a common chipset.cb.

TESTED: generates a proper devicetree for x220 based on logs.

Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69501
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01 10:27:44 +00:00
Arthur Heymans
cdb26fd011 cpu/intel/model_206ax: Remove fake lapic device
Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.

The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.

Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01 10:27:31 +00:00
Arthur Heymans
d52bfbb6aa cpu/intel/sandybridge: Use enum for ACPI C states
Also remove the now unnecessary comments from the devicetree.

Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01 10:27:10 +00:00
Kapil Porwal
634d88c413 soc/intel/meteorlake: Log CSE RO write protection info for MTL
The patch logs CSE RO's write protection information for Meteor Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.

Port of commit abe0d810f0 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").

BUG=none
TEST=Verify the write protection details on google/rex.

Excerpt from google/rex coreboot log:
[DEBUG]  ME: WP for RO is enabled        : YES
[DEBUG]  ME: RO write protection scope - Start=0x4000, End=0x396FFF

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-01 09:28:34 +00:00
Elyes Haouas
d7d8e0dd5b crossgcc: Upgrade LLVM from 15.0.0 to 15.0.6
Tested with BUILD_TIMELESS=1: binaries stay the same for qemu-i440fx.

Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-01 09:15:13 +00:00
Elyes Haouas
49838af623 crossgcc: Upgrade CMake from 3.24.2 to 3.25.0
Change-Id: Iebccaf984c2c8b449c8f152484a4df1e75e74fd8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69715
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-01 09:14:31 +00:00
Shelley Chen
cd4e3d52ee mb/google/herobrine: Mask out upper bits from sku_id()
When retrieving the SKU id value through the sku_id() function in
mainboard_needs_pcie_init(), we only want the values in the lower 5
bits as we can only represent SKU id up to 27.  Everything in the
higher bits should be masked out because they are not needed.

BUG=b:254281839
BRANCH=None
TEST=Make sure that NVMe is not initialized
     Tested on a herobrine board with SKU id 0

Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 21:53:45 +00:00
Shelley Chen
474da028ab mb/google/herobrine: Only retrieve sku_id from EC once
Currently, we are getting the sku id from the EC every time we call
the sku_id() function.  However, this will never change so we only
need to retrieve it once.  Inserting exit condition if sku id is
already set, then don't get it from the EC again.

Also, removing the ram_code function, which does nothing right now.
There is already a weak stub_function for this in
src/lib/coreboot_table.c that already does the same thing.

BUG=b:260740438,b:182963902
BRANCH=None
TEST=make sure image still boots to login on herobrine device

Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
2022-11-30 21:53:28 +00:00
Fred Reitberger
98d0574746 mb/amd/birman/gpio: Configure birman GPIOs
Configure birman GPIOs per schematic 105-D67000-00B v0.7

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-30 18:48:19 +00:00
EricKY Cheng
33e0df19d9 soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.

BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-30 18:06:29 +00:00
Tim Crawford
c16bd3cc9c mb/system76: Rename gaze16 to tgl-h
Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-11-30 16:54:04 +00:00
Arthur Heymans
4403c56ea2 arch/x86: Buildtest clang targets with VBOOT_STARTS_BEFORE_BOOTBLOCK
TESTED: google/vilboz boots with clang build.

Change-Id: Ie115c27b4cb0b8f83d7647bdd27ffcbac9376399
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69746
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 16:52:23 +00:00
Arthur Heymans
b24f48db7d arch/arm/armv7: Disable generating neon FPU code
By default clang generates code with neon instructions. These are not
supported on all arm targets so default to fpu=none.

Change-Id: I48fc505107d131466be39f466151df62b2d2bd0b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69745
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 16:37:30 +00:00
Arthur Heymans
fa2feae3d6 arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyX
Clang generated code uses this for zero initialized variables.

Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-30 16:37:05 +00:00
Arthur Heymans
c83a17841c arm/armv7/Makefile.inc: Fix processing ld files with clang
When processing linker scripts clang needs to be set for the proper
target or it gets confused by other options.

Change-Id: I040aa14a06c728269ca1026e0002392e5ac8fef8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69744
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 16:36:29 +00:00
Arthur Heymans
8d9cce1e09 ec/google/chromeec: Add packed attribute to structs in union
Clang warns about structs inside a union also needing the packed
attribute.

This files is copied from the chromeec project, so it adds comment next
to the coreboot specific changes as a reference.

TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc.

Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-30 16:34:33 +00:00
Jeremy Compostella
54a6b1f281 mb/google/brya: Enable Fast VMode for brya0, skolas and skolas4es
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.

FSP silicon discards the request if the Voltage Regulator or SoC does
not support the feature.

BUG🅱️259057787
TEST:Verify that the feature is enabled by reading from pcode
     No PnP regression observed
BRANCH=firmware-brya-14505.B

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7e318534f1429af8ec06048430966344ddd346a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 16:02:01 +00:00
Arthur Heymans
fade723b25 nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 15:58:19 +00:00
Arthur Heymans
691d58f999 nb/intel/sandybridge: Add a chipset devicetree
This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.

Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 15:19:06 +00:00
Kapil Porwal
6cecb0d963 soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode
BUG=none
TEST=Build and boot to google/rex.

Excerpt from google/rex coreboot log:
[DEBUG]  ME: Manufacturing Mode          : YES

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-30 15:12:24 +00:00
David Wu
e8f86bc503 mb/google/brya/var/zydron: Add mipi hi556 camera support
This patch supports multiple camera modules based on FW_CONFIG.

BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib0a4f46d889e9f6c2898efee6825cf2d02252d87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-30 15:10:59 +00:00
Gaggery Tsai
ddfbeda3bb mb/google/brya: Enable crashlog
This patch enables crashlog for all brya projects.

BUG=b:190756531, b:259978562
BRANCH=None
TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog
     PCIe device 0xa.0 is enabled and intel-pmt kernel driver is
     loaded.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-30 08:11:15 +00:00
zhourui
d892a336bb mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.

BUG=b:259891452
TEST=Build and verified in sasukette

Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-30 07:56:29 +00:00
Kyösti Mälkki
f2b9852a8e nb/intel/e7505: Hook up PCI domain and CPU ops to devicetree
Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 04:05:55 +00:00
Elyes Haouas
8b8ada6fdb /: Remove extra space after comma
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30 03:07:23 +00:00
Arthur Heymans
cc22607dbf Revert "src/arch/x86: Use core apic id to get cpu_index()"
This reverts commit 095c931cf1.

Previously cpu_info() was implemented with a struct on top of an
aligned stack. As FSP changed the stack value cpu_info() could not be
used in FSP context (which PPI is). Now cpu_info() uses GDT segments,
which FSP does not touch so it can be used.

This also exports cpu_infos from cpu.c as it's a convenient way to get
the struct device * for a certain index.

TESTED on aldrvp: FSP-S works and is able to run code on APs.

Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:58:13 +00:00
Arthur Heymans
aab91213b2 soc/intel/alderlake/acpi.c: Don't look up coreboot CPU index
The coreboot CPU index for a lapic is arbitrary: it depends on which
CPU obtains a spinlock first. Simply using an increasing index will
result in consistent ACPI tables across each boot.

Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:58:09 +00:00
Kapil Porwal
39f5042d9e mb/google/brya: Add ACPI DmaProperty for ethernet devices
Add ACPI DmaProperty for ethernet devices.

BUG=b:259716145
TEST=Verified SSDT on google/osiris.

Before:
Scope (\_SB.PCI0.RP01)
{
    Device (RLTK)
    {
        Name (_HID, "R8168")  // _HID: Hardware ID
        Name (_UID, 0xD0E889DD)  // _UID: Unique ID
        Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
        Name (_ADR, 0x00000000)  // _ADR: Address
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x07,
            0x03
        })
    }
}

After:
Scope (\_SB.PCI0.RP01)
{
    Device (RLTK)
    {
        Name (_HID, "R8168")  // _HID: Hardware ID
        Name (_UID, 0xD0E889DD)  // _UID: Unique ID
        Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
        Name (_ADR, 0x00000000)  // _ADR: Address
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x07,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }
}

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:51:26 +00:00
Kapil Porwal
4c2c2c43d0 drivers/net/r8168: Add support for ACPI DmaProperty
BUG=b:259716145
TEST=Verified SSDT on google/osiris.

Before:
Scope (\_SB.PCI0.RP01)
{
    Device (RLTK)
    {
        Name (_HID, "R8168")  // _HID: Hardware ID
        Name (_UID, 0xD0E889DD)  // _UID: Unique ID
        Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
        Name (_ADR, 0x00000000)  // _ADR: Address
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x07,
            0x03
        })
    }
}

After:
Scope (\_SB.PCI0.RP01)
{
    Device (RLTK)
    {
        Name (_HID, "R8168")  // _HID: Hardware ID
        Name (_UID, 0xD0E889DD)  // _UID: Unique ID
        Name (_DDN, "Realtek r8168")  // _DDN: DOS Device Name
        Name (_ADR, 0x00000000)  // _ADR: Address
        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
        {
            0x07,
            0x03
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }
}

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I647230082362b1093b63793a201eba23a6289121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70016
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:50:59 +00:00
Kapil Porwal
8c56ad116d mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device
BUG=b:259716145
TEST=TBD

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifaa0912b38129ed2db01fb78ed39c0db89e746fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:50:14 +00:00
Kapil Porwal
d7eacd75ae soc/intel/cmn/block/pcie/rtd3: Add support for ACPI DmaProperty
BUG=b:259716145
TEST=Verified SSDT on google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I921b06e8d35ddac0bc8175b13a33c84515b282a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70028
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:49:36 +00:00
Kapil Porwal
0b20a174db drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSD
BUG=b:259716145
TEST=Build google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I991bc822fbb72cfaa9485abe882950fc7bcef498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:48:59 +00:00
Kapil Porwal
ddc52a6481 acpi: Create a common method to add DmaProperty
Create a common method to add DmaProperty.

BUG=b:259716145
TEST=Verified SSDT on google/osiris.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I75b3f22ad29f90f3c3b251bd0d70bae9d75f71fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 19:48:27 +00:00
Frank Wu
3fd1174e76 mb/google/skyrim/var/frostflow: Update RAM ID table
Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP.
Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP.
The RAM ID table has been assigned as:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)
H9JCNNNCP3MLYR-N6E             1 (0001)
MT62F2G32D8DR-031 WT:B         2 (0010)
H9JCNNNFA5MLYR-N6E             3 (0011)
K3LKBKB0BM-MGCP                4 (0100)
K3LKCKC0BM-MGCP                5 (0101)

BUG=b:254758998
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-11-29 17:14:07 +00:00
John Su
72bc673c43 mb/google/skyrim/var/frostflow: Set Package Power Parameters
Set Package Power Parameters from AMD DevHub document #57316.

"stapm_time_constant_s" = "200"

BRANCH=none
BUG=b:257187831
TEST=emerge-skyrim coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69565
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-29 15:27:47 +00:00
Tim Van Patten
5bd21db8eb mb/google/skyrim: Move common DPTC values to devicetree.cb
The Skyrim devices share a common set of DPTC values to enable booting
with low/no battery. Rather than duplicating them in each variant's
overridetree.cb, move them into the baseboard/devicetree.cb.

BUG=b:217911928
TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff

Change-Id: I20f0a8259c2fc986da23026da88feadd69942046
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 15:24:19 +00:00
Werner Zeh
1c727fd784 util/cbmem: Provide a way to override coreboot path
Right now cbmem uses a fix path to reach coreboot src path (../../).
This makes it impossible to compile cbmem out of the coreboot tree (e.g.
copy just the cbmem directory elsewhere and compile).

This patch adapts the technique from cbfstool and adds a variable called
'TOP' which points to coreboot root directory and which can be
overridden at build time by providing it to make as an argument. This
will enable a stand-alone build of cbmem.

Change-Id: I2732f75310e10716e5aa74e094e0bf628ad22f0b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-29 15:15:07 +00:00
Kapil Porwal
bc76109df2 {soc/intel/cmn/pcie, mb/google/volteer}: Rename is_external variable
Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.

BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.

SSDT snippet:
   Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
   {
       ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
       Package (0x01)
       {
           Package (0x02)
           {
               "HotPlugSupportInD3",
               One
           }
       },

       ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
       Package (0x01)
       {
           Package (0x02)
           {
               "ExternalFacingPort",
               One
           }
        }
    })

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29 05:11:56 +00:00
Felix Singer
60a422736b util/crossgcc: Use GitHub for downloading IASL
The download links from acpica.org [1] are not stable, and for some
reason they named the release tarballs with .tar_0.gz. Thus, use the
tarballs from their GitHub repository generated out of the release
tags [2].

Tested locally and also IASL patch applies.

[1] https://www.acpica.org/downloads
[2] https://github.com/acpica/acpica/tags

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70021
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28 19:51:56 +00:00
Kyösti Mälkki
99166482fe sb,soc/intel: Drop spurious SMI entry message
The message only makes sense if ACPI PM base address is
allowed to be dynamic. If requested, it can be logged
in common code.

Change-Id: Iad7a60098c0391cc23384035af49e373dad90233
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-28 10:26:27 +00:00
Paul Menzel
ac23f9da75 Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
GCC 12 incorrectly warns about an array out of bounds issue:

```
$ make V=1 # emulation/qemu-i440fx
[…]
    CC         ramstage/arch/x86/ebda.o
x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32  -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c
In file included from src/arch/x86/ebda.c:6:
In function 'write_ble8',
    inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2,
    inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2,
    inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2,
    inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds]
   27 |         *(uint8_t *)dest = val;
      |         ~~~~~~~~~~~~~~~~~^~~~~
[…]
```

[In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1]
It treats INTEGER_CST addresses smaller than that as assumed results of
pointer arithmetics from NULL while addresses equal or larger than that
as expected user constant addresses. For GCC 13 we can represent results
from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead
of (void*)offset INTEGER_CSTs.

[1]: https://web.archive.org/web/20220711061810/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578

TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0
Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-28 10:22:31 +00:00
Kyösti Mälkki
28c6df7323 sb/intel/common: Rename TCO timeout
Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree.

Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-28 10:10:26 +00:00
Kyösti Mälkki
307320c23f sb,soc/intel: Address TCO SECOND_TO_STS name collision
Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.

In src/soc/intel/denverton_ns:
  #define TCO2_STS_SECOND_TO 0x02

In soc/intel/baytrail,braswell:
  #define SECOND_TO_STS (1 << 17)

Elsewehere
  #define SECOND_TO_STS (1 << 1)

It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.

Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-28 10:09:04 +00:00
Kyösti Mälkki
e8a3af1069 sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.

For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().

Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-28 10:08:23 +00:00
Kyösti Mälkki
560c3f5ccf aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
Both SMM_ASEG and SMM_TSEG choices work.

There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.

Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-28 10:05:28 +00:00
Kyösti Mälkki
0c745347d0 soc/intel/quark: Fix out() parameter order
Change-Id: I4db09632a41d28b0c8e211e6232db4e6d85bdf5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70051
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28 08:54:17 +00:00
Kapil Porwal
07adfa6bf5 soc/intel/meteorlake: Print vars related to ME mfg mode
BUG=none
TEST=Build and boot to google/rex.

Excerpt from google/rex coreboot log:
[DEBUG]  ME: FPFs Committed              : NO
[DEBUG]  ME: Manufacturing Vars Locked   : NO

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iec07c1f951fbbf51541917c8b99d19f2f12980b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69739
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-28 01:08:34 +00:00
Kyösti Mälkki
f38f30a3de Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"
This reverts commit 9f0e21a4da.

It should be allowed for i82801gx/early_init.c to have
   #include <southbridge/intel/common/pmutil.h>

But there is a conflict:

src/southbridge/intel/common/pmutil.h:
   #define TCO1_CNT  0x68
src/southbridge/intel/common/tco.h:
   #define TCO1_CNT  0x08

Followup works resolve the difficulties around the offset
0x60 used for TCO register bank, tree-wide.

Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-27 20:42:30 +00:00
Harsha B R
5b92aa9c64 mb/intel/mtlrvp: Create baseboard structure for mtlrvp
This patch will create the baseboard structure for mtlrvp. Changes
include,
1. Adding Baseboard config for mtlrvp in Kconfig
2. Move gpio.h to corresponding baseboard directory
3. Append header reference to CPPFLAGS_common in Makefile.inc

BUG=none
TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69971
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-27 17:19:09 +00:00
Ritul Guru
f123ffe78c mb/amd/mayan: Add framework for morgana crb mayan
mayan is the reference board for the morgana SoC. It needs to be
updated to match the actual board design as well. amd/mayan is started
as a copy of amd/birman.

Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-27 17:18:13 +00:00
Frank Chu
21e0da3128 mb/google/brya/var/marasov: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=marasov emerge-brya coreboot

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I03b443826d39182eaf23ad3e4e0ba8d6b8a93022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69180
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-26 23:55:18 +00:00
Kapil Porwal
d6152ea1af mb/google/rex: Disable SATA from the devicetree
SATA is not supported on google/rex hence disable it.

BUG=none
TEST=Build and boot to google/rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I35a742ab9782feed86c3af514505d870d181b34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26 23:53:29 +00:00
Saurabh Mishra
060492ecd2 vc/intel/edk2/edk2-stable202111: Safe guard enum macro in SmBios.h
Fix compilation issue due to enum macro redefinition by safeguarding
definitions with DISPLAY_FSP_VERSION_INFO_2 in SoC Kconfig.

Back-ported from commit f7e8adac7b ("edk2-stable202005: Update
MdePkg/Include/IndustryStandard/SmBios.h") to fix compilation issue due
to enum macro redefinition.

BUG=b:260183604
TEST=Verify MTL Rex0 build with the patch
and verify the version output prints no junk data.

Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ibc65d05a8b4bd232b91184ff8cd52a20cd3538ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-26 23:45:26 +00:00
Elyes Haouas
9018dee685 src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26 23:39:16 +00:00
Reka Norman
5aa98964fb mb/google/nissa/var/craask: Add support for NVMe
Enable NVMe GPIOs based on fw_config and add NVMe to devicetree.

Note, eMMC and NVMe are not probed in devicetree. On first boot in
factory, the device needs to boot with unprovisioned fw_config, so all
storage devices should be enabled when unprovisioned. Currently,
devicetree disables all probed devices when unprovisioned. If we want
eMMC and NVMe to be probed, support needs to be added for enabling
probed devices when unprovisioned.

BUG=b:259211172
TEST=Verified by ODM. On craask, LTE and WCAM still work. On craaskneto,
eMMC and NVMe SKUs can both boot.

Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69958
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-26 23:38:43 +00:00
Subrata Banik
fb970a43bd soc/intel/meteorlake: Refactor heci finalize functions
This patch creates a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again FSP config.

Currently, `heci_set_to_d0i3()` function is getting called twice.

BUG=b:260041679
TEST=Able to build google/rex with this patch and observe coreboot log
modification as below:

Without this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms

With this patch:

[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ]  HECI: CSE device 16.1 is disabled
[WARN ]  HECI: CSE device 16.2 is disabled
[WARN ]  HECI: CSE device 16.3 is disabled
[WARN ]  HECI: CSE device 16.4 is disabled
[WARN ]  HECI: CSE device 16.5 is disabled
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-26 08:42:21 +00:00
Subrata Banik
a3c0ba12eb soc/intel/alderlake: Use common code CSE-Lite API for WP information
This patch drops the local implementation
`log_me_ro_write_protection_info` and adopts the API from IA common
code (cse_lite.c).

BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26 08:41:56 +00:00
Subrata Banik
da527ec12b soc/intel/cmn/cse: Create API to get CSE Lite WP Information
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.

BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-26 08:41:49 +00:00
Felix Singer
11433c8e98 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32
Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-26 08:11:52 +00:00
Felix Singer
e12f3bf6e2 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce
Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-26 08:11:42 +00:00
Elyes Haouas
b961910192 Update arm-trusted-firmware submodule to upstream v2.8.0
Updating from commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)

to commit id 9881bb93a:
2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration)

This brings in 227 new commits.

Change-Id: I6c902a7360b5436df22c829c7e387457598c3b94
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-26 02:11:43 +00:00
Ian Feng
c6e6d0d522 mb/google/nissa/var/xivu: Update DPTF parameters
Follow thermal table from thermal team.

1. Modify TS1 passive policy to 68.

BUG=b:249446156
TEST=emerge-nissa coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 16:41:57 +00:00
Mario Scheithauer
68fb5437f9 mb/siemens/mc_ehl2: Disable L1 prefetcher
As for mainboard mc_ehl1, a hard real-time dependency is also required
for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive
which in the end leads to an increased number of cache misses. Disabling
the L1 prefetcher boosts up the performance (in some cases by more than
10 %) in this specific use case.

Change-Id: I07b27dd672533e693a6c2987d16f54333850760e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-25 15:44:46 +00:00
Arthur Heymans
3627f2903c cpu/intel/model_2065x: Don't use a magic APIC
Move the chip configuration to the cpu cluster device.

It looks like none of the devicetree were featuring a lapic 0xacac,
nor was tcc_offset ever set, so this remains a NOP.

Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25 15:04:17 +00:00
Kyösti Mälkki
a5fa534705 ACPI: Flag boards with ACPI_NO_MADT
These boards do no fill MADT with useful information.

Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 15:03:47 +00:00
Arthur Heymans
dd96ab6987 cpu/intel/haswell: Move chip_ops to cpu cluster
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-25 15:03:39 +00:00
Kyösti Mälkki
c87814d750 ACPI MADT: Add LINT1 as NMI source
Set of boards and platforms did not have LINT1 configured
as NMI source.

Change-Id: I65044125562bda363b3a0d92da6137c77a28b587
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 15:02:47 +00:00
Kyösti Mälkki
66b5e1b32d ACPI: Use common code for MADT LAPIC NMIs
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.

Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 15:01:49 +00:00
Kapil Porwal
da1a58a503 {drivers/wifi, mb/google}: Rename is_untrusted to add_acpi_dma_property
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it
makes sense to have a unified name across different device drivers.

BUG=b:259716145
TEST=Verified that the _DSD object is still present in the SSDT.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 13:56:39 +00:00
Martin Roth
c45c2fb1f6 util/testing: Fully clean all but the standard GCC build
We don't currently use the artifacts from the Clang or CrOS GCC
builds, so don't bother saving them.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I69fe803e4b4213a199d0b76089da443aa769aa92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25 13:55:27 +00:00
Eran Mitrani
feed8e4bd9 soc/intel/adl/acpi: add FSPI to DSDT
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI

FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end

This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.

TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182

Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25 13:54:24 +00:00
Werner Zeh
314f280aac commonlib/fsp_relocate.c: Fix cbfstool build on 32-bit host
On a 32-bit host, uintptr_t is defined as 'unsigned int' instead of
'unsigend long int' like on a 64-bit host. When cbfstool is built on a
32-bit host, the printk format specifier '%lx' expects a 'long int'
while new_addr is of type 'uintptr_t', aka 'unsigned int'.
This in the end leads to a build error.

To fix this and make it build on both, 32- and 64-bit hosts, use PRIxPTR
as the format specifier. This macro will be resolved at compile time in
the right way on both, 32- and 64-bit hosts.

Test=Build cbfstool on 32- and 64-bit hosts.

Change-Id: Ia917d2ed31778f3a29c0a6c7368f74c15319b099
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69682
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 13:53:31 +00:00
Elyes Haouas
a45ed44724 crossgcc: Upgrade IASL from 20220331 to 20221020
Changes: https://acpica.org/node/201

Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-25 09:52:18 +00:00
jimlai
bbc8d912e8 drivers/intel/mipi_camera: Remove IPU ES support entry for RPL
The current IPU ES entry value is always set to true for RPL and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.

On Raptor Lake silicon, the production binaries are backward
compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.

BUG=b:258125833
TEST=Verify the Camera functionality by enabling the IPU secure mode
on RPL variants with both ES/QS silicon.

Signed-off-by: Jim Lai <jim.lai@intel.com>
Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-25 01:03:21 +00:00
Elyes Haouas
8aebfd34d9 crossgcc: Upgrade MPFR from 4.1.0 to 4.1.1
Change-Id: I7679c6751fb02ab670ade923b365c6410a6dc118
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-11-25 00:59:37 +00:00
Martin Roth
b357e53bff util/lint: Ignore fmd files when evaluating Kconfig symbols
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I5e3ff8ee10fdd3514033e72bd0c2664a4b2f5310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-24 17:52:07 +00:00
Tim Crawford
705ebbea04 mb/system76: Reset Realtek codec before configuring
Perform a codec reset before configuring to avoid potential issues like
oryp5 had before 86f410479c ("mb/system76/oryp5: Reset HDA before
configuring").

Inspecting proprietary firmware for multiple boards shows that this is
always done as well.

Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-11-24 17:51:54 +00:00
Kapil Porwal
c9cb8ff8fb drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD
Use correct GUID for DmaProperty in ACPI _DSD.

Reference:
https://learn.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports

Before:
Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
{
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
    Package (0x01)
    {
        Package (0x02)
        {
            "DmaProperty",
            One
        }
    }
})

After:
Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
{
    ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
    Package (0x01)
    {
        Package (0x02)
        {
            "DmaProperty",
            One
        }
    }
})

BUG=b:259716145
TEST=Verified the new GUID is reflected in ACPI SSDT at runtime.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-24 17:45:49 +00:00
Arthur Heymans
71e40782b8 google/*/*/sdram_configs.c: Add function argument
A function declaration without a prototype is deprecated in all versions
of C.

Change-Id: Ie22231908233f2fba25d78f6c5f53940011e8158
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69748
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:17:58 +00:00
Martin Roth
8180427a16 soc/amd: Define post codes
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.

picasso/romstage.c did get a couple of post codes removed to match the
other files.

The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.

Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24 15:16:45 +00:00
Arthur Heymans
5e3798ca48 arch/arm: Use unified assembly syntax
Taken from Linux which also updated these files.

Clang only works with this syntax, so this fixes builds for arm.

TESTED on qemu vexpress-a9 and verstage on google/vilboz with
BUILD_TIMELESS=1, binaries remain the same.

Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63058
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:15:41 +00:00
Frank Chu
a9921bcadb mb/google/brya/var/marasov: update pch_espi setting
Add conn0/conn1 for pch_espi.

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5969d2941c02400788d66521680fcd13d3a6b13f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69785
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 15:15:03 +00:00
Subrata Banik
98b696703e soc/intel/meteorlake: Decouple HECI disabling interface from its Kconfig
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.

BUG=b:260183610
TEST=Able to build google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:24:52 +00:00
Frank Chu
fb43107e62 mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov
Declare touchscreen and touchpad under I2C3 and I2C5

BUG=b:254365935
BRANCH=firmware-brya-14505.B
TEST=Built successfully

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:06:18 +00:00
Elyes Haouas
d27b2e818b lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declaration
This reduce the difference with linux v6.0-rc3.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24 06:05:27 +00:00
Elyes Haouas
36d81dfbdb sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.h
Also remove unused DEBUG_PERIODIC_SMIS macro.

Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-24 06:05:08 +00:00
Elyes Haouas
9f0e21a4da sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out.

Change-Id: Id281a3478051c4876ccbe26452d8744769c86654
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:04:40 +00:00
Mario Scheithauer
0f633f7f7f mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
Set downshift counter to 2 for all Marvell PHYs on this mainboard before
the PHY downshifts to the next highest speed.

Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:04:03 +00:00
Mario Scheithauer
16dd1c31c2 drivers/net/phy/m88e1512: Add downshift enable
This patch provides the functionality to enable downshift on Marvell
PHY. By setting a downshift counter, the PHY is correspondingly often
attempted to establish Gigabit link before the PHY downshifts to the
next highest speed. The range is limited to 8 trials. To activate
downshift, a software reset must follow to take effect.

Change-Id: I4224eab6c1fc13824d53556c80435bc130a13bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69853
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:03:38 +00:00
Mario Scheithauer
e19f403770 mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
On this mainboard Marvell PHY INTn is routed to LED[2] pin.

Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:01:58 +00:00
Mario Scheithauer
155cf5cd2e drivers/net/phy/m88e1512: Add interrupt enable
INTn on Marvell PHY can be routed to LED[2] pin. This setting must be
made via LED Timer Control Register on page 3.

Change-Id: Ida1efbb604c382676b9d13ac8bf14de768f93637
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69433
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:01:30 +00:00
Mario Scheithauer
969531b6d8 mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
This mainboard has three Marvel PHYs connected to the internal SOC GbE
controllers. The default LED status after HW reset of this PHYs shows a
different mode than what is needed. LED[2] is not connected on this
mainboard.

This patch sets the following LED status:
LED[0] - 7 = On - 1000 Mbps Link, Off - Else
LED[1] - 1 = On - Link, Blink - Activity, Off - No Link
LED[2] - not connected

TEST=Try different register values to verify LED feature.

Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 06:00:38 +00:00
Mario Scheithauer
1a97c89d7b drivers/net/phy/m88e1512: Provide functionality to customize LED status
For Marvel PHY it could be necessary to customize the shown LED status
at the connector. The LED status can be changed via Function Control
Register on page 3.

Link to the Marvell PHY 88E1512 datasheet:
https://web.archive.org/web/20221109080111/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-phys-transceivers-alaska-88e151x-datasheet.pdf

Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:59:31 +00:00
Werner Zeh
49ec39fa7f device/mdio: Provide helper functions for read and write
This patch provides helper functions to read or write a register via the
MDIO bus. They can be used from drivers to easily access registers on
the MDIO bus.

Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:58:28 +00:00
Mario Scheithauer
d4ab2ee38f drivers/net/phy/m88e1512: Add new driver for Marvell PHY 88E1512
This driver enables the usage of an external Marvell PHY 88E1512 which
should be connected to a SOC internal MAC controller. In a first step it
is only the framework of the driver. Functionality will follow with a
second patch.

Change-Id: I24011860caa7bb206770f9779eb34b689293db10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69384
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:57:11 +00:00
Mario Scheithauer
c16a7fc717 soc/intel/ehl: Add MDIO operation to TSN GbE device
This patch refactors the MDIO access for the TSN GbE device by placing
the MDIO read and write functions into mdio_bus_operations struct which
is assigned to the .ops_mdio member of the PCI device struct. In this
way the MDIO interface of the TSN GbE device is exposed and can be used
by other drivers if needed.

Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-24 05:56:37 +00:00
Mario Scheithauer
67f63e768d src/device + util/sconfig: Introduce new device 'mdio'
This patch extends the available device paths with a new device 'mdio'.
MDIO is the 'Management Data Input/Output' called interface which is
used to access an Ethernet PHY behind a MAC to change settings. The real
payload data path is not handled by this interface.

To address the PHY correctly on the MDIO bus, there is a 5 bit address
needed, which often can be configured via pins on the mainboard.
Therefore, the new introduced device has an 'addr' field to define its
address. If one wants to use a MDIO device in devicetree, the syntax is
straight forward (example):
	device mdio 0x2 on end

As the MDIO interface is driven by the MAC, most likely this MDIO device
will be hooked in as a child device of the (PCI attached) MAC device.

With the new introduced ops_mdio a new interface is added to provide an
API for read and write access over MDIO.

Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:53:55 +00:00
Kapil Porwal
66e44e3252 soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
This patch skips setting D0I3 bit for all HECI devices by FSP.

The learning being made from Alder Lake platform showed that the CSE
EOP cmd response time is highly nondeterministic and letting the EOP
cmd issued by FSP makes the response time even worse.

The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
(late sending of EOP) to ensure there is ample time for CSE to come
to a state where the response to the EOP is almost immediate.

There were a number of refactoring being done to ensure the EOP cmd
can be sent at the later stage.

#1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change)
#2: Modify the CSE related boot state based operation to allow a
proper window for sending late EOP cmd. (Common Code Specific change)

The entire refactoring helps us to save ~60ms of boot time.

Without those code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,248,328(61,954))

With those code change EOP sending timestamp as below:

943:after sending EOP to ME                     1,231,660 (2,754)

Port of commit d6da4ef69e ("soc/intel/alderlake: Skip setting D0I3
bit for HECI devices") to incorporate the #1 which is a SoC specific
code change.

BUG=none
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.

Excerpt from google/rex coreboot log:
[SPEW ]   DisableD0I3SettingForHeci : 0x1

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-24 05:45:06 +00:00
Frank Chu
77c4d6165d mb/google/brya/var/marasov: Update SPD ID assignment
Adjust SPD ID order

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B	0 (0000)
H9JCNNNBK3MLYR-N6E		1 (0001)
MT62F1G32D4DR-031 WT:B		2 (0010)
H9JCNNNCP3MLYR-N6E		3 (0011)

BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3a62cf355508debce387c48d9d089e73763b2bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69784
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:28:50 +00:00
Ivy Jian
461f2a9ba0 mb/google/rex: Adding cros_gpios to rex
Adding cros_gpios for crossystem to access WP GPIO

BUG=b:258048687
TEST= run FAFT firmware_WriteProtect passed.

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69924
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24 05:28:01 +00:00
Zhuohao Lee
d81103c58e mb/google/brask/variants/brask: remove fan setting
The brask doesn't include a real chassis so we don't need to configure
the fan setting in the overridetree.cb. Instead, we can leave the fan
running at full speed after the device boot up.

BUG=b:259643676
BRANCH=firmware-brya-14505.B
TEST=flashed the bios to the device and make sure the fan spinned
     at full speed.

Change-Id: I6075b6171ca4d7b907679efd0ce7e355759385bc
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-24 01:47:03 +00:00
Kevin Chiu
fc0e5a73e8 mb/google/brya/var/gladios: Update gpio table
Based on the latest schematic to update the gpio table.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23 22:22:03 +00:00
Raymond Chung
d999a25212 mb/google/brya/var/gaelin: Configure devicetree settings
Override devicetree configuration based on the latest gaelin schematic.

BUG=b:249000573, b:254375472
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=emerge-brask coreboot

Change-Id: I3a741feec52cf73da8d6ec0b03cc93d6a4cba256
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23 22:21:33 +00:00
Kevin Chiu
2c351d8f34 mb/google/brya/var/gladios: Update devicetree setting
Update devicetree setting per the schematic.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I8746d44daa43c06723bdfcac6803eb90a3c124b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-23 22:21:18 +00:00
Felix Held
75873dbf27 soc/amd/*/fsp_m_params: rework local USB PHY table update
Update the fields that need to be updated directly in the local static
usb_phy_config struct instead of dereferencing the pointer written to
the corresponding UPD field. This will allow updating the type of UPD
field in a follow-up commit to enable 64 bit coreboot builds.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23 19:44:03 +00:00
Felix Held
3b89c95906 soc/amd/*/Makefile: fix readelf parameters to get bootblock size
This ports forward part of commit df09680626 ("soc/amd/picasso: Add
support for 64bit builds") to the newer AMD SoCs.

Use -Wl instead of -l to get the output format that the commands in the
Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this
change, readelf will split the output into two lines in case of a 64 bit
coreboot build. This results in invalid amdcompress and amdfwtool
command lines which will cause the amdfwtool call to fail with

Error: BIOS binary destination and uncompressed size are required

With the old readelf -l command we get this output in a 64 bit build:

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000000080 0x0000000002030000 0x0000000002030000
                 0x0000000000010000 0x0000000000010000  RWE    0x10

while we get the correct output in a 32 bit build:

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  LOAD           0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20

With readelf -Wl we also get the expected output in a 64 bit build:

Program Headers:
  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  LOAD           0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10

TEST=This fixes the 64 bit build on Cezanne with some follow-up patches
applied.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23 19:43:46 +00:00
Nick Vaccaro
170bc7a0fe Revert "mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE"
This reverts commit 7203aa5c2d.

BUG=b:260138434
TEST=None

Cq-Depend: chrome-internal:5126951, chromium:4049177
Change-Id: Ieaa44a33a7c65d384581b5145821b449783ca3fa
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-23 19:33:49 +00:00
Liju-Clr Chen
e1ee23f29d soc/mediatek: Add error handling for dptx_get_edid()
Skip eDP initialization when we failed to get EDID. This prevents the
PLL assertion in dp_intf_config() if the display could not be
initialized properly.

BUG=b:233720142
TEST=boot to depthcharge on MT8188 EVB.

Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 16:31:29 +00:00
Elyes Haouas
977673894f src/soc/qualcomm: Remove unnecessary space after casts
Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69807
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 16:30:58 +00:00
Elyes Haouas
334772008c sb/intel/i82801gx/lpc.c: Use post_code()
Use post_code() instead of 'outb(value, CONFIG_POST_IO_PORT)'.

Change-Id: I1ba6bff810b61a1249cda6e96eb40f4a81381322
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-23 15:24:03 +00:00
EricKY Cheng
9a41333c6b mb/google/skyrim/var/winterhold: Add Vrm setting for SMT
All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.

BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-23 14:00:06 +00:00
Subrata Banik
6a22c5f8ee soc/intel/meteorlake: Select X86_INIT_NEED_1_SIPI Kconfig
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.

Port the Alder Lake 'commit 6526e78967 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake.

Additionally, no performance degradation is observed while running
benchmarks.

BUG=b:211770003
TEST=Able to boot Google, Rex to ChromeOS with all cores enabled.

Without this patch:
30:device enumeration                     1,480,217 (28,232)

With this patch:
30:device enumeration                     1,472,466 (18,334)

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 13:30:51 +00:00
Martin Roth
8c974509ea soc/intel/common: Define post codes
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.

cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done.  This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.

All other post codes remain identical.

POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 03:48:32 +00:00
Martin Roth
d05ea79e40 util/release/build-release: Fix style issues
No real functional changes, just cleaning up shellcheck issues, putting
braces around variables, add comments and the like.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6e79afc8d725e86ddbf7f4eb4685bed190c20738
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67319
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 03:48:10 +00:00
Martin Roth
c87ab01c2d cpu/intel/car: Define post codes
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.

The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values.  Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.

The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.

POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23 03:47:18 +00:00
Elyes Haouas
4911942e94 crossgcc: Remove leftover "../cmake"
"../cmake" introduced on Change-Id: I3144a83
Remove "../cmake" when the build is done.

Change-Id: I289bfaca1fd8d3f004455babd99849ca8aa2d6db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-22 19:54:25 +00:00
Mark Hasemeyer
7d8f7fb85f mb/google/skyrim: Pass Ti50 IRQ to PSP
It shouldn't be assumed that all variants of skyrim will use the same
gpio for TPM interrupts.

Use the PSP's new mailbox command to tell it what gpio the tpm interrupt
comes in on.

BUG=b:248193764
TEST=tast run <ip> hwsec.TPMContest
     Verify log entry:[DEBUG]  PSP: Setting TPM GPIO to 18...OK
     Use incorrect GPIO in mailbox cmd and verify TPMContest test
     failed.

Signed-off-by: Mark Hasemeyer <markhas@google.com>
Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 17:57:14 +00:00
Felix Singer
010ef428b4 util/crossgcc: Limit LLVM targets to the needed ones
coreboot only supports a small subset of the targets that LLVM supports.
It's not needed to enable all possible targets. Thus limit the targets
to the following ones:

  * X86
  * RISC-V
  * AArch32
  * AArch64
  * PowerPC

Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69841
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur.heymans@9elements.com>
2022-11-22 15:21:13 +00:00
Elyes Haouas
3141fbade8 src/acpi: Remove unnecessary space after casts
Change-Id: I3c077dee1c14e4aa45f837361daf799f02d32a29
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69818
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:48:23 +00:00
Elyes Haouas
995dfefdf0 src/commonlib: Remove unnecessary space after casts
Change-Id: Ib20f02cc9e5be0efea8bc29fce6bd148adf28ead
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69817
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:47:15 +00:00
Elyes Haouas
2ba796eb23 src/arch: Remove unnecessary space after casts
Change-Id: I00551dfd963d47a58284bc31f21b0fa12130fe78
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69816
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:46:47 +00:00
Elyes Haouas
3a9980767e src/northbridge: Remove unnecessary space after casts
Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:46:09 +00:00
Elyes Haouas
ab6d94430e src/soc/samsung: Remove unnecessary space after casts
Change-Id: I32b41eded11e4e575627fec3947a75c08fdfd0a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69812
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:44:19 +00:00
Elyes Haouas
a51d9b00f0 src/soc/cavium: Remove unnecessary space after casts
Change-Id: Ieb094096e9e204e59a1f3fcf716d906e7736fb43
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69811
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:43:41 +00:00
Elyes Haouas
41865cc5b4 src/soc/nvidia: Remove unnecessary space after casts
Change-Id: I096e88158027ac22cf93a9450c869807dbc14670
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69810
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:43:16 +00:00
Elyes Haouas
4d4193dcef src/soc/mediatek: Remove unnecessary space after casts
Change-Id: I871579cc434820294f285298fe43da4cd1da27a3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:42:49 +00:00
Elyes Haouas
816dbbc1b8 src/soc/ti: Remove unnecessary space after casts
Change-Id: If4564abf060410726b0b245ba002a35ca9d30769
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69808
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:42:28 +00:00
Elyes Haouas
723b896330 src/southbridge: Remove unnecessary space after casts
Change-Id: Ib82968724696110a8d1655928db5b2a665525d20
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69805
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:41:55 +00:00
Elyes Haouas
d369c66256 src/device/pci_: Remove unnecessary space after casts
Change-Id: I11593245fedc26489e3506d773aaff1ad34188b1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69804
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:41:26 +00:00
Elyes Haouas
1ef547eec7 src/drivers: Remove unnecessary space after casts
Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69803
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:40:56 +00:00
Elyes Haouas
385939f7cf src/include: Remove unnecessary space after casts
Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69802
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 13:00:29 +00:00
Elyes Haouas
4d685d433a src/cpu: Remove unnecessary space after casts
Change-Id: I12463d4d26c03c85fa018b421bb9166fbfeb0b60
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69801
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 12:59:56 +00:00
Elyes Haouas
b538d71e32 security: Remove unnecessary space after casts
Change-Id: Ibd41382d0e0ef58498ac925dc9e10b54a76a798a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69800
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 12:55:26 +00:00
Reka Norman
f903ef1d5f mb/google/nissa/var/nivviks,yaviks: Remove ISH firmware-name
For nissa, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.

BUG=b:234776154
TEST=Boot to OS on nirwen and yaviks UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.

Cq-Depend: chrome-internal:5102230
Change-Id: I68f963e17bc0dbf9db9adaaa3f96f06b8737523b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-11-22 12:53:28 +00:00
Tyler Wang
1b75e25b0f mb/google/nissa/var/craask: Disable SAR Proximity Sensor GPIO pin
BUG=b:253387689
Test:Boot to OS on craask and check SAR Proximity Sensor GPIO pin

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I2b2a2516890b68036e96d1a542e6a10a098cb6a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69790
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22 12:51:43 +00:00
Jonathan Zhang
b09517b2fb drivers/ocp/dmi: move smbios_ec_revision to ocp folder
Move smbios_ec_revision to ocp folder so that all ocp boards
share the same function without implementing again.

TESTED=Execute "dmidecode -t 0" to check corresponding field.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonzhang Zhang <jonzhang@meta.com>
Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22 12:50:05 +00:00
Elyes Haouas
aec294a71a include/spd.h: Fix comment module type information
Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22 12:49:12 +00:00
Martin Roth
adaab4a97e util: Add SPDX license headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7cf35132df0bc23f7b6f78014ddd72d58ea2ab8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22 12:47:09 +00:00
Martin Roth
74a4dca481 ec: Add SPDX license headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-22 12:43:11 +00:00
Thomas Heijligen
2332d29ba9 libpayload: Fix compiler warnings
Following warnings occur when compiling with
`i386-elf-gcc (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0`

drivers/serial/8250.c:75: [-Werror=unused-variable]
  Move variable declaration inside the
  `#if !CONFIG(LP_PL011_SERIAL_CONSOLE)` block

drivers/udc/dwc2.c:505: [-Werror=format=]
  use `%zd` to match type `size_t`

Change-Id: Id285c24cba790f181fa203f3117e5df35bed27c4
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69764
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 21:08:30 +00:00
Martin Roth
6202fbbe90 util/testing: Allow jenkins builders to skip testing areas
With the addition of the clang tests, the jenkins builds are taking a
really long time to run the tests.  This change allows the
"what-jenkins-does" build to be split into separate builds on jenkins.

Additionally, some jenkins builds like coverity don't need (or want)
to build clang or even the linters.

Update help with the variables.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:06:20 +00:00
Martin Roth
b5e9946227 util/testing: Add scanbuild test build to what-jenkins-does
This tests building a single target with scanbuild so to make sure that
option hasn't been broken.  Since it's a different type of build, it
hasn't previously been tested with what-jenkins-does.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:06:05 +00:00
Martin Roth
676e0acb07 util/testing: Use new --name argument for abuild
This gets rid of the duplicated directory and xml filename and uses the
--name argument to abuild instead, which also updates the test name in
the junit xml file.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:53 +00:00
Martin Roth
7df45bbc0c util/abuild: Add --name option to set name of abuild run
Previously, the testclass variable was only updated with the chromeos
or Kconfig option values, and the output directory and xml file names
were updated independently.

With the --name option, all of these can be set simultaneously. This
also prevents jenkins from seeing clang and gcc tests as the same
because the testclass variable wasn't updated.

If --name is not set, all behavior is as it was previously.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:38 +00:00
Martin Roth
36dcabac05 util/testing: Call test-tools target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-tools target, make test-tools from what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:24 +00:00
Martin Roth
b399f103a1 util/testing: Update ABUILD_OPTIONS with long option names
It's hard to tell what is what with the short option names, so use the
long options here.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1371e098bba1077dedfaffa56287a28656197b40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:14 +00:00
Martin Roth
dfafe798a6 util/testing: Call test-abuild target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-abuild target, make test-abuild from what-jenkins-does.

The test-abuild target had not been updated to use the ABUILD_OPTIONS
variable, so update it with the commands from what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:03 +00:00
Martin Roth
b3f60a53da util/testing: Call test-lint target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-lint target, make test-lint with the --junit argument from
what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:04:53 +00:00
Martin Roth
2852cd2b22 util/testing: Unify cleanup in all targets
Instead of having the what-jenkins-does target clean up before building,
have it call the test_cleanup target.

Clean the tegra targets.

Remove distclean from test_cleanup target - I don't think that's
expected, and people might be upset by having their .config deleted.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:04:25 +00:00
Karthikeyan Ramasubramanian
4763a5a470 soc/amd/mendocino: Increase CBFS_MCACHE size
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.

BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.

Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 19:56:34 +00:00
Elyes Haouas
9aea4ec9a5 cpu/intel/socket_*: Clean up Kconfig files
Remove SSE when SSE is already selected by supported CPUs.
Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig.

Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-21 18:42:17 +00:00
Martin Roth
b04eda2ca1 util/abuild: check for PASSED_BOARDS before trying to show it
If no boards are tested by abuild, an error is currently shown because
no boards failed, but no boards passed either.  Account for this
possibility.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21 18:40:55 +00:00
Elyes Haouas
24ca80aab6 src/superio: Remove unnecessary space after casts
Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69814
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-21 15:03:50 +00:00
Felix Held
1840f935d6 include/memlayout.h: update comment about VBOOT2 work buffer size
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in
vboot/firmware/2lib/include/2constants.h, so update the comment.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21 14:07:46 +00:00
Sridhar Siricilla
e5ca71db06 soc/intel/common: Add support to read CPU and PCH Trace Hub modes
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.

For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-11-21 14:04:24 +00:00
Frank Chu
88019ddbdf mb/google/brya/var/marasov: update field STORAGE of fw_config
field STORAGE 30 31
	option STORAGE_UNKNOWN			0
	option STORAGE_NVME			1
	option STORAGE_UFS			2
end

BUG=b:254365935
TEST=emerge-brya coreboot.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69786
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-21 01:14:59 +00:00
Michał Żygowski
e5b8a04f84 mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.

Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 17:38:23 +00:00
Jonathan Zhang
1864f12fda device/pciexp: add pcie_find_dsn()
Add pcie_find_dsn() to detect and match PCIe device serial
number. In addition, vendor ID is matched when provided.

Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20 17:37:09 +00:00
Jonathan Zhang
3dcafa8774 acpi: Add initial support for CEDT
Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.

Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).

TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20 17:35:04 +00:00
Martin Roth
b7f92a0b6a util/kconfig: Add patch to move Kconfig deps to build/config
The change being reverted [1] caused all the Kconfig dependency files
to be generated at the top level of coreboot's build directory.

This reverts that behavior and puts the dependencies back where we're
used to them being.

[1] 1b9e740a81

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 17:29:32 +00:00
Martin Roth
bfdb489032 Docs: Add SPDX headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id229fb22d20c489db3dd7a59f29e7ac10174fd85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-20 15:24:32 +00:00
Jan Samek
97afddf36a drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed comment
There is a note about the default I2C speed of this being 400 kHz
despite the logic in rx6110sa.c sets the fallback (correctly) to
100 kHz.

This information originally comes from the fact the dw_i2c bus
controller default speed is 400 kHz. This is irrelevant to
the default speed of this device as it can be used with any
bus controller.

BUG=none
TEST=coreboot builds correctly (no functional changes).

Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 02:05:53 +00:00
Sergii Dmytruk
97fe17ff59 security/tpm: make log format configurable via Kconfig
This commit doesn't add any new format options, just makes selecting
existing format explicit.

Ticket: https://ticket.coreboot.org/issues/422
Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-19 15:11:09 +00:00
zhaojohn
1d903a24dc mb/google/rex: Enable TCSS DisplayPort detection at preboot
This change enables the DisplayPort detection at preboot for Rex board.

BUG=b:247670186
TEST=Built image and validated DisplayPort feature at preboot on Rex.

Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 15:09:52 +00:00
zhaojohn
7e0b925162 soc/intel/common: Fix the TCSS DisplayPort detection flow
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.

BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.

Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 15:09:03 +00:00
Fred Reitberger
2b9ee5d79e vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda
Update definitions on glinda used by birman.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:47:48 +00:00
Fred Reitberger
4875a1f054 vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
Update definitions to match morgana FSP.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:46:49 +00:00
Caveh Jalali
4e71517e37 ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.

BUG=b:216485035,b:258126464
BRANCH=none
TEST=none

Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 02:41:48 +00:00
Tyler Wang
decd67efad mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-11-19 02:40:55 +00:00
Kapil Porwal
89ea31248e soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from
 1) enabling ACPI Timer emulation in uCode.
 2) disabling the PM ACPI Timer.

Both actions are now done in coreboot.

`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.

Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").

NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.

BUG=none
TEST=Boot to OS on google/rex.

Excerpt from google/rex coreboot log:
[SPEW ]   EnableTcoTimer                      = 1

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-19 02:40:26 +00:00
Subrata Banik
20c64a1210 mb/google/rex: Disable ACPI PM timer
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that
ACPI PM timer remains disabled.

The PM timer (by PMC IP) consumes more power and blocks S0ix so the
timer is emulated by ucode to save power and unblock S0ix.

TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc
BIT 1 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 19:48:14 +00:00
Martin Roth
b699d61b99 mb/google/skyrim: Enable STB Spill-to-DRAM by default
BUG=b:231291430
TEST=See STB Spill-to-DRAM enabled

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib60b7fc2ba85c7a8025c9f8c6495e94049499f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69707
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18 18:01:19 +00:00
Julius Werner
4924cdb9ac build: List all Kconfigs in CBFS config file, compress it
The coreboot build system automatically adds a `config` file to CBFS
that lists the exact Kconfig configuration that this image was built
with. This is useful to reproduce a build after the fact or to check
whether support for a specific feature is enabled in the image.

However, the file is currently generated using the `savedefconfig`
command to Kconfig, which generates the minimal .config file that is
needed to produce the required config in a coreboot build. This is fine
for reproduction, but bad when you want to check if a certain config was
enabled, since many configs get enabled by default or pulled in through
another config's `select` statement and thus don't show up in the
defconfig.

This patch tries to fix that second use case by instead including the
full .config instead. In order to save some space, we can remove all
comments (e.g. `# CONFIG_XXX is not set`) from the file, which still
makes it easy to test for a specific config (if it's in the file you can
extract the right value, if not you can assume it was set to `n`). We
can also LZMA compress it since this file is never read by firmware
itself and only intended for later re-extraction via cbfstool, which
always has LZMA support included.

On a sample Trogdor device the existing (uncompressed) `config` file
takes up 519 bytes in CBFS, whereas the new (compressed) file after this
patch will take up 1832 bytes -- still a small amount that should
hopefully not break the bank for anyone.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-18 17:19:44 +00:00
Jan Samek
be585d2ece drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent
Set the logging message prefix to the device name instead of the
device path in order to make the output consistent with other
logging messages in this and other drivers.

Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69718
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18 16:05:03 +00:00
Jan Samek
6f8fd5d397 mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c device
Instead of creating a dummy I2C device in order to force Linux to
decrease the I2C bus speed, use the own 'bus_speed' field of RV3028
device config structure.

Linux should always set the bus speed to the speed of the slowest
device sitting on the bus. Hence the dummy device is not needed
here anymore.

BUG=none
TEST=See if the RV3028 RTC is visible and working (date/time can
be set/read) in Linux. At the time, a driver modification is needed
to add a match table for the "MCRY3028" ACPI HID. A proper kernel
patch is pending.

Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18 16:04:34 +00:00
Jan Samek
1560648197 drivers/i2c/rv3028c7: Add ACPI generation callbacks
Add ACPI generation callback to the driver after obtaining the
ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY").

Also add I2C bus speed field to the device config structure, which
is a required ACPI entry.

BUG=none
TEST=Disassemble the SSDT table and see whether the device entry
"MC28" is generated correctly. Also check whether the RV3028 driver
in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding
an ACPI match table to it containing the HID. A proper kernel patch
is pending.

Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-18 16:03:53 +00:00
Elyes Haouas
b1bcd5bb8c lib/malloc.c: Fix log messages
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.

Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18 16:02:28 +00:00
Elyes Haouas
799c321914 cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18 16:00:45 +00:00
EricKY Cheng
9cbbba68b6 soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-18 15:54:49 +00:00
Johnson Wang
159e64ca25 soc/mediatek/mt8188: Enable and initialize EINT
Issue:
Device can't wake up using power key.

Root cause and solution:
EINT event mask register is used to mask EINT wakeup sources. All
wakeup sources are masked by default. So we add a driver here to unmask
all wakeup sources.

BUG=none
TEST=wake the device up by power key on MT8188 EVB.

Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-18 15:47:33 +00:00
Shelley Chen
f6307ca9c2 soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
On Herobrine, we will determine if we have an NVMe device based on SKU
id.  Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.

BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
     on villager, which does not have NVMe and made sure that it boots
     still.  Check cbmem dump to make sure that device configuration
     entry is still low since it's not initializing PCIe devices:

     40:device configuration 730,203 (1,295)

Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18 15:47:05 +00:00
Shelley Chen
b5af064f54 mb/google/herobrine: Implement mainboard_needs_pcie_init
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links.  When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.

BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-18 15:46:22 +00:00
Sridhar Siricilla
ce4dc66319 soc/intel/meteorlake: Add Meteor Lake MCH device ID
Add Meteor Lake MCH device ID 0x7d15.

TEST=Build and verify boot on MTL RVP

With patch, coreboot log:
`[DEBUG]  MCH: device id 7d15 (rev 00) is Meteorlake P`

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 15:45:56 +00:00
Krishna P Bhat D
1c6b02a8b6 mb/google/nissa: Modify FMD to redistribute buffer
Modify the chromeos FMD file for nissa variants to redistribute the
buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS
region.

1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME
is 3708K.
2. Modify SI_BIOS region to 12672K. This results in an addition of 32K
buffer each to FW_MAIN_A/B regions.

BUG=b:228936671
BRANCH=firmware-nissa-15217.B
TEST=Verify CSE FW update with new FMD and ME RW blobs on craask.

Cq-Depend: chrome-internal:5094491
Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 03:39:35 +00:00
Johnny Li
d7328abc95 mb/google/brya/variants/crota: Configure TDC current for VR domains.
+-----------+-------+-------+---------+-------------+----------+
| Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
|           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
+-----------+-------+-------+---------+-------------+----------+
|    IA     |  2.8  |  2.8  |    80   |      43     |  28000   |
+-----------+-------+-------+---------+-------------+----------+
|    GT     |  3.2  |  3.2  |    40   |      23     |  28000   |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.

BUG=b:256754175
TEST=Build test image and use PTAT to check IA and GT value
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69135
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-11-18 00:38:25 +00:00
Arthur Heymans
457f77be37 Makefile.inc: Remove workaround ACPI warnings
No boards now have a missing dependency so remove the workaround.

Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69514
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18 00:14:13 +00:00
Martin Roth
35e09ec8ae util/kconfig: Move Kconfig deps back into build/config
revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1]

The above change caused all of the enabled kconfig options to be written
into the top level build directory.  We don't want that, so go back to
the old behavior for the coreboot tree.

[1] 1b9e740a81

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17 23:37:48 +00:00
Kyösti Mälkki
2e65e9cb69 soc/amd: Use ioapic helper functions
Calling setup_ioapic() was only correct for the
IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs.

Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17 23:31:59 +00:00
Arthur Heymans
87d4f114a2 {ec/superio}/acpi: Remove _PRS if no _SRS is implemented
_PRS only makes sense if _SRS is implemented.

Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17 21:20:50 +00:00
Arthur Heymans
148fd99365 superio/acpi/pnp_generic.asl: Add _PRS for each device
Simply return the current resource settings in the _PRS method. This
means that coreboot has to correctly set up the resources on the
device. This won't result in any regression as without _PRS the ACPI
OS would not know what resources settings are valid, so it would never
use _SRS.

Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64218
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17 21:19:22 +00:00
Jonathan Zhang
d57b82111a arch/x86/smbios: Add SMBIOS Type 39
Read FRU product info of PSU to get Type 39 required information.
Further development needed if multi-record info of PSU FRU is required.
For now, the read_fru_areas() only read product chassis and board info.

Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Signed-off-by: ziang <ziang.wang@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I18d056cba1a79b0775c8a42b3a879e819887adca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-11-17 21:17:49 +00:00
David Milosevic
0f5b87cf95 mb/prodrive/atlas: add unique DIMM locators in smbios type17
This patch adds unique device-locators, bank-locators and
asset-tags to the smbios type17 tables by making use of a
DIMMs controller-ID. This way we avoid name clashes when,
for example, two DIMMs share the same channel-ID and DIMM-ID
but have a distinct controller-ID.

Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I8aef79faa43f2475485f581c675ee152e580f678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-17 17:52:18 +00:00
David Milosevic
6be82a4cd8 soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.

This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.

Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.

This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.

Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 17:51:46 +00:00
EricKY Cheng
6943fc769c mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting
Update touchscreen setting.
Change hid as panel team request to fix touchscreen with no function.
The panel team verification result is on b/251378772 comment#17.

BUG=b:251378772
TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is
functional.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I07d446111b1c18bfe15d00b6eacff23382cd461a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-17 17:32:59 +00:00
Kyösti Mälkki
e10bf582aa soc/intel/broadwell: Fix out() parameter order
Change-Id: I0897acddd00bad89a5fd784f82380ed0d0d2c06e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69703
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17 17:23:26 +00:00
Elyes Haouas
c129254655 sb/intel/i82801dx/bootblock.c: Include "i82801dx.h"
Change-Id: I58ff31ab98c4310478cf3bbe8aecce4000ac8205
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69717
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17 14:25:04 +00:00
Dinesh Gehlot
7c6dd796f2 soc/intel/meteorlake: Implement report_cache_info() function
Make use of deterministic cache helper functions from Meteor Lake
SoC code to print useful information during boot as below:

Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64
Sets = 32768
Cache size = 24 MiB

Port of commit 55f5410fcd ("soc/intel/alderlake: Implement report_cache_info() function")

BUG=none
TEST=Build and Boot verified on google/rex

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I561658c8da0136d6c3d9578f22f5d320e542457d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69681
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17 13:39:51 +00:00
Kyösti Mälkki
ac435b4b91 intel/haswell,lynxpoint: Fix out() parameter order
Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-11-17 13:34:24 +00:00
Kyösti Mälkki
8d14633dfb nb/intel/ironlake,sandybridge/gma: Fix out() parameter order
Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17 13:33:33 +00:00
Subrata Banik
0427788e24 mb/google/rex: Add disable_gpio_export_in_crs for rex
None of the touchscreens (over I2C) used in the rex program requires
exporting GPIOs in the ACPI _CRS method.

This can cause i2c devices to malfunction or cause timing
sequence violations if ACPI exports a PowerResource for the
device that uses GPIOs that are also exported in _CRS.

BUG=none
TEST=Able to build and boot Google, Rex platform.

Without this patch:

[ERROR]  I2C: 00:10: Exposing GPIOs in Power Resource and _CRS

With this patch:

None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69612
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:30:22 +00:00
Leo Chou
3e8f8c162d mb/google/nissa/var/pujjo: Tune timing on SD device RTD3
Tune timing between power on and reset on SD device RTD3.

BUG=b:250746988
TEST=Use the value to boot on Pujjo successfully.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I1ea77ec8381000249229653f1c0b9044bdf7866d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-11-17 13:29:18 +00:00
Elyes Haouas
51c311827e arch/{arm64,riscv}: Remove "CRIT: " from log messages
It is no longer necessary to explicitly add "CRIT: " in front of
BIOS_CRIT message.

Change-Id: I506c1d278960c91d1283e9b1936c9c1678a10e17
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:28:48 +00:00
Elyes Haouas
bd5471a048 commonlib/storage/sdhci.c: Remove "ERROR: " from log message
It is no longer necessary to explicitly add "ERROR: " in front of
BIOS_ERR message.

Change-Id: I36e2785ae567d82339212140c1bde0876dfd450d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:28:30 +00:00
Elyes Haouas
336a06f2d1 drivers/uart/Kconfig: Drop unused Kconfig symbol
Change-Id: I43e6b57477cb4fd2c8ab399e9cc74591b0a44684
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:26:55 +00:00
Elyes Haouas
c5b8f8ec50 cpu/x86/Kconfig: Drop unused Kconfig symbol
Change-Id: Id50ebecdaddcce426b15d535afcc3e755f2c5a35
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:26:17 +00:00
Elyes Haouas
185b16d946 nb/amd/pi/Kconfig: Drop unused Kconfig symbol
Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69333
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:25:21 +00:00
Elyes Haouas
a3d3bc5640 soc/intel/common/block/sgx/Kconfig: Add missing default symbol
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by
accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB.

Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 13:24:09 +00:00
Elyes Haouas
a31ef8c242 soc/amd/common/pi/def_callouts.c: Fix log messages
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.

Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:23:09 +00:00
Reka Norman
bedc9b75a7 soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine
Determination", from ADL onwards there are three criteria which
determine whether a device is in production mode:
1. Fuses are programmed
2. SPI descriptor is locked
3. Manufacturing variables are locked

When logging whether the device is in manufacturing mode, 1 and 2 are
already checked. Add a check for 3 as well.

Also add logs for each individual criteria so it's easy to tell why the
overall Manufacturing Mode is set or not.

BUG=b:255462682
TEST=On a nivviks which has not gone through EOM:
Before:
[DEBUG]  ME: Manufacturing Mode          : YES
[DEBUG]  ME: SPI Protection Mode Enabled : NO

After:
[DEBUG]  ME: Manufacturing Mode          : YES
[DEBUG]  ME: SPI Protection Mode Enabled : NO
[DEBUG]  ME: FPFs Committed              : NO
[DEBUG]  ME: Manufacturing Vars Locked   : NO

On an anahera which has gone through EOM:
Before:
[DEBUG]  ME: Manufacturing Mode          : NO
[DEBUG]  ME: SPI Protection Mode Enabled : YES

After:
[DEBUG]  ME: Manufacturing Mode          : NO
[DEBUG]  ME: SPI Protection Mode Enabled : YES
[DEBUG]  ME: FPFs Committed              : YES
[DEBUG]  ME: Manufacturing Vars Locked   : YES

Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69324
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:22:17 +00:00
Rizwan Qureshi
08c77dadf3 soc/intel/alderlake: Update ME HFSTS register definition
Update Alder Lake CSME HFSTS registers definitions as per Intel
doc #627331 revision 1.0.0, section 3.4.8.

Follow up CLs will use the bit definitions for performing
various checks.

TEST=build and boot nivviks platform

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:21:23 +00:00
Angel Pons
fda7d07b7b mb/starlabs/starbook/kbl: Drop redundant option code
Commit 9bbc039c45 ("soc/intel/skylake:
Hook up FSP hyper-threading setting to option API") already hooks up
the `hyper_threading` CMOS option in SoC code, so there's no need to
do it from mainboard code.

Change-Id: I602452266a8465cced12454f800ea023f382ba6f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69522
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:18:59 +00:00
Angel Pons
2e9849aa02 mb/supermicro/x11-lga1151-series: Fix CMOS options
The `hyper_threading` CMOS option was hooked up to the wrong enumeration
and lacked a default value in `cmos.default`. Thus, use the correct enum
for the `hyper_threading` option, remove the now-unused "backwards" enum
and provide a default value in `cmos.default`.

Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:17:16 +00:00
Kyösti Mälkki
8e679f72e9 sb/intel/i82801dx: Improve LPC device early init
Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.

Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17 07:46:58 +00:00
Kyösti Mälkki
806b2cd42b sb/intel/common: Fix GPE0 related register conflict
When ACPI GPE0 block was extended to 64 events or 8 bytes,
ACPI PM register space was slightly modified. After
adjustment, PM2_CNT register moved to 0x50 where register
SS_CNT was previously defined to be.

For platforms that have a valid use for PM2_CNT==0x50 in
their FADT, remove overlapping definition of SS_CNT.

On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status()
incorrectly addressed also GPE0_EN register. For a bit cleaner
implementation, define GPE0_HAS_64_EVENTS.

Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-17 07:44:25 +00:00
Kyösti Mälkki
95932ba9b7 sb/intel/common: Drop duplicate smi_set_eos()
We have equivalent southbridge_smi_set_eos().

Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17 07:43:15 +00:00
Kyösti Mälkki
2e19aa153a mb/emulation/qemu-q35: Split smm_close() and smm_lock()
Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17 07:42:55 +00:00
Kyösti Mälkki
20861b5ad3 mb/emulation/qemu-q35: Release TSEG reserve with SMM_ASEG
If TSEG is not enabled, smm_region() should not reserve the region, so
add a test for T_EN flag in ESMRAMC.

For the SMM_ASEG case this moves CBMEM immediately below top-of-ram.

Change-Id: I2da4b846d0767afe00e98fdee375914c1875ddf5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-17 07:42:35 +00:00
zhaojohn
9f5fea993a soc/intel/meteorlake: Enable FSP multiphase
This patch changes the UPD EnableMultiPhaseSiliconInit to enable the
Meteor Lake FSP multiphase flow.

BUG=b:247670186
TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable.

[SPEW ]  Executing Phase 1 of FspMultiPhaseSiInit
[DEBUG]  FSP MultiPhaseSiInit src/soc/intel/meteorlake/
         fsp_params.c/platform_fsp_multi_phase_init_cb called
[DEBUG]  port C0 DISC req: usage 1 usb3 1 usb2 2
[DEBUG]  Raw Buffer output 0 00000211
[DEBUG]  Raw Buffer output 1 00000000
[DEBUG]  pmc_send_ipc_cmd succeeded
[DEBUG]  port C1 DISC req: usage 1 usb3 3 usb2 4
[DEBUG]  Raw Buffer output 0 00000431
[DEBUG]  Raw Buffer output 1 00000000
[DEBUG]  pmc_send_ipc_cmd succeeded

Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-17 06:32:47 +00:00
Shelley Chen
992883ad0c Revert "mb/google/herobrine: Remove NVMe from device tree"
This reverts commit d164feb726.

Reason for revert: Herobrine program decided that we wanted
to be able to boot from NVMe if one exists.

Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 02:36:51 +00:00
Shelley Chen
6d4641d704 Revert "soc/qualcomm/sc7280: Remove NVMe init"
This reverts commit 1b07797a7b.

Reason for revert: Herobrine program decided that we wanted
to be able to boot from NVMe if one exists.

Change-Id: If675947026095d16b72bdb0f3ec790e583523465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 02:36:42 +00:00
Ian Feng
32a3d93659 mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VD
ALC5682-VS/ALC5682-VD use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.

ALC5682I-VS: _HID = "RTL5682"
ALC5682-VD: _HID = "10EC5682"

BUG=b:246491349
TEST=ALC5682-VD/ALC5682-VS audio codec can work.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 00:55:48 +00:00
Sridhar Siricilla
0c923732dd soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode
As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine
Determination", from ADL onwards there are three criteria which
determine whether a device is in production mode:
1. Fuses are programmed
2. SPI descriptor is locked
3. Manufacturing variables are locked

When logging whether the device is in manufacturing mode, #1 and #2 are
already checked. Add a check for #3 as well.

TEST=Build and boot MTL RVP

Snippet from coreboot log:
[DEBUG]  ME: Manufacturing Mode          : YES

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-17 00:55:35 +00:00
Sridhar Siricilla
026f86ba3b soc/intel/meteorlake: Update CSE firmware status registers
The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per
MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs
the firmware status details as per the new register definition.

TEST=Build and boot the coreboot on Rex

Snippet from coreboot log with the patch:
	[DEBUG]  ME: CPU Debug Disabled          : NO
	[DEBUG]  ME: TXT Support                 : NO

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 00:53:25 +00:00
Kapil Porwal
c89de227eb soc/intel/meteorlake: Hide PMC and IOM devices
Hide these ACPI device so Windows does not warn about missing device
drivers.

Port of commit 907c85ad48 ("soc/intel/alderlake: Hide PMC and IOM
devices").

BUG=none
TEST=Verified _STA method from ACPI tables in OS. USB-C drive is
detected in OS.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic62172bee9120d260a3cd60770ef780cb7dce860
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69576
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 00:41:44 +00:00
vjadeja-intel
0ddeaedbe8 vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00
Update header files for FSP for Meteor Lake platform to
version 2404_00, previous version being 2364_00.

FSPM:
1. Address offset changes
2. Rename `PlatformDebugConsent` to `PlatformDebugOption`

FSPS:
1. Address offset changes

Additionally, incorporate the UPD name change for MTL romstage.

BUG=b:255481471
TEST=Able to build and boot Google, Rex to ChromeOS.

Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17 00:01:56 +00:00
Wisley Chen
a9a97da9e2 mb/google/nissa/var/yaviks: Enable ISH driver and firmware name
Enable ISH driver and set firmware name as "adl_ish_lite.bin"

BUG=b:242291814
TEST=boot into kernel, and check dmesg
"ISH firmware intel/adl_ish_lite.bin loaded"

Change-Id: I4badabba1a0cfceb77fc91f21953496152f19615
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69606
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 21:01:27 +00:00
Fred Reitberger
2dceb126d5 soc/amd/morgana/Kconfig: Remove TODO after review
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 19:59:06 +00:00
Martin Roth
1e0f132ff4 util/testing: Move check of intel-sec-tool to separate target
Testing for the presence of intel-sec-tools doesn't need to happen
inside the what-jenkins-does target.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6faa5bd5292ac5cceba9a64fe81939c0e25b9f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16 19:50:28 +00:00
Tarun Tuli
24fb14a643 mb/google/brya/var/agah: Add Power Limits for RPL SKU
Add power limits for the RPL SKUs of Agah.

BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.

Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-16 17:41:24 +00:00
Ren Kuo
35bd7afafe mb/google/brya/variants/volmar: Update ELAN touchscreen timing
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the volmar's delay time to follow
the requiremnet.

BUG=b:257073343
TEST=Build firmware and measure the T3 timing of resume
     and boot up on volmar DUT.
     Run Suspend/Resume with UI test and got pass.

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-16 17:09:30 +00:00
Kyösti Mälkki
6c78b9115d mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT
Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-16 15:37:28 +00:00
Kyösti Mälkki
bbba201165 cpu/x86/smm: Use common SMM_ASEG region
Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-16 15:34:44 +00:00
Martin Roth
2d4c2b9850 arch/x86: Disable clang build if using verstage_before_bootblock
Clang isn't working so well with the ARM code yet.  This is still
breaking builders after fixing the compiler warnings.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69701
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16 15:22:15 +00:00
Martin Roth
676284f311 Documentation: Add some more acronyms to the list
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2022-11-16 15:20:44 +00:00
Martin Roth
6cf181a49b arch/arm/armv7: Don't set gcc specific options for clang builds
Clang doesn't understand the -Wa,-mno-warn-deprecated option.
Remove it for now.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9f91d6ec2db247e901ba9bc41bc4b888bbe43236
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-16 15:16:42 +00:00
Felix Held
50c0a6d675 drivers/intel/fsp2_0: add log level parameter to fsp_print_guid
Not all functions that call fsp_print_guid print their output with the
BIOS_SPEW log level, so introduce a new log level parameter so that the
caller of fsp_print_guid can specify which log level fsp_print_guid
should use for printing the GUID.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 15:00:00 +00:00
Martin Roth
c420d538ee soc/amd/common: Don't set gcc specific options for clang builds
Clang doesn't understand the -Wstack-usage=40960 option.  Replace it
with -Wframe-larger-than=40960.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16 14:22:22 +00:00
EricKY Cheng
f48faa06c9 mb/google/skyrim/var/winterhold: Update DPTC setting for SMT
Follow Dynamic Thermal Table Switching proposal to initialize
thermal table config E as default table for SMT.
Since the dynamic thermal table switching mechanism is still
under cooking, after discussing with thermal team, suggest
adopting config E(limit Soc not reach to max power) as default
thermal config to avoid any thermal-related issue during phase
build. Once the dynamic thermal table switching mechanism
is finished, will change the default value to config A.

BUG=b:232946420, b:258572474
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-16 13:52:18 +00:00
Chao Gui
42c6025247 mb/google/skyrim: Create crystaldrift variant
Create the crystaldrift variant of the skyrim reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_CRYSTALDRIFT

Signed-off-by: Chao Gui <chaogui@google.com>
Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16 13:50:56 +00:00
Matt DeVillier
2b2df3a180 mb/google/zork: Use detect vs probed flag for touchscreens
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.

BUG=b:121309055
TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.

This mirrors the changes made for skyrim in commit 22683fab
(mb/google/skyrim: Use detect vs probed flag for touchscreens)

Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 13:50:23 +00:00
Matt DeVillier
6da5e0bf37 mb/google/zork: Implement touchscreen power sequencing
As all variants have a touchscreen option, in baseboard tables set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.

This mirrors the change to skyrim in commit f90ff456
(mb/google/skyrim: Implement touchscreen power sequencing)

Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 13:49:53 +00:00
Subrata Banik
f9c075d36d soc/intel/meteorlake: Use index 0x10 instead of 0 for IOE P2SB
This patch uses index 0x10 for IOE P2SB memory resource allocation
instead of static 0.

Additionally, switches to `mmio_resource` from `mmio_resource_kb`.

TEST=Able to build and boot Google/Rex and observed log as below.

Without the code change:

[SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
            gran 0 limit 0 flags f0000200 index 0

With the code change:

[SPEW ]     PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
            gran 0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-11-16 08:44:32 +00:00
Tyler Wang
770e8e3546 mb/google/nissa/var/craask: Correct G2 touchscreen HID
Correct G2 touchscreen HID to GT75CH02.

BUG=b:235919755
Test=Dump the SSDT on craask and check the HID had been modified.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 05:14:00 +00:00
Arthur Heymans
afda49b7ba configs: Buildtest 64bit amd/picasso
Change-Id: Ia7b9925ab0a594a0ec26746cbe938f7cf2aa0118
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16 04:22:29 +00:00
Arthur Heymans
df09680626 soc/amd/picasso: Add support for 64bit builds
Tested on google/vilboz (running the PCI rom with yabel).

Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16 04:22:00 +00:00
Matt DeVillier
c429ee1d97 mg/google/zork: Add functionality to set GPIOs in romstage
Add (empty) baseboard GPIO tables, getter functions, and call to
gpio_configure_pads() in romstage, in preparation for adding
touchscreen GPIO configuration/power sequencing.

Change-Id: If0f626dbc7e601c2f49759e49a0baf027bf25f96
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69482
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-16 03:03:28 +00:00
Matt DeVillier
150b809edf mb/google/kahlee: Implement touchscreen power sequencing
As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.

This mirrors similar changes made for skyrim, guybrush, and zork.

TEST=tested with rest of patch train

Change-Id: Id235815904dfc093549a1ed529e19974010977c7
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69547
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 03:02:48 +00:00
Matt DeVillier
3c148f7e61 mb/google/kahlee: Use detect vs probed flag for touchscreens
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.

BUG=b:121309055
TEST=build/boot ChromeOS and Linux on barla/liara, ensure touchscreen
is functional, and ACPI device entry generated for correct touchscreen
model.

Change-Id: I142a6cdb6e8cef51fd925d34362a19a8736982a5
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69548
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 03:02:24 +00:00
Matt DeVillier
046e295b2b mb/google/kahlee: rename baseboard GPIO table getter for clarity
Rename variant_romstage_gpio_table() to baseboard_romstage_gpio_table()
since the GPIO table comes from the baseboard (and is not overridden by
any variant).

Drop the __weak qualifier as this function is not overridden.

This mirrors similar changes made for skyrim, guybrush, and zork.

Change-Id: I772bd2d74fd6778ffaa1e0809cc53f8d43b153f3
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69546
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 03:02:08 +00:00
Matt DeVillier
2c6bba3fe1 mb/google/kahlee: Disable touchscreen GPIO export in CRS
Disable GPIO export in ACPI _CRS for touchscreens which set the
register "have_power_resource." This eliminates the error:
[ERROR]  I2C: <bus:addr>: Exposing GPIOs in Power Resource and _CRS

TEST=build/boot barla/liara, verify touchscreen functional, no error in
cbmem log.

Change-Id: Ifa8248755f346df37faf7a3182651bf190b0c33d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69549
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 03:00:49 +00:00
Tarun Tuli
c7ec8f1d3c mb/google/brya/var/agah: Set GPP_H13 to reset on PLTRST
GPP_H13 should be reset when going to S5.  Update it to do so on
PLTRST

BUG=b:240617195
TEST=Measured on Agah that PP3300_SD_X goes off in S5.

Change-Id: I959f92f2c486e0ca5cb4269b271c163b4c4925d4
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69340
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 03:00:20 +00:00
Raymond Chung
b2a9209f65 mb/google/brya/var/gaelin: Configure DRIVER_TPM_I2C_BUS
Add TPM I2C bus for gaelin in Kconfig.

BUG=b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and can boot to OS.

Change-Id: Idaac11111a9ba7df0929267567e4730b2811f5f0
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68886
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2022-11-16 02:18:12 +00:00
Kyösti Mälkki
8ea8eba930 mb/emulation/qemu-q35: Use ioapic helper functions
Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69525
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 21:09:54 +00:00
Kyösti Mälkki
93d759f0be mb/emulation/qemu-q35: Cleanup includes
Change-Id: Ib36d855e1dce8eb800bc077c1e444768c444fef8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69524
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 21:09:36 +00:00
Reka Norman
974f7b23cb mb/google/nissa: Add SD_BOOT fw_config
Some nissa devices want to disable boot from SD card. Since nissa has a
single shared depthcharge target, add a program-wide fw_config to allow
disabling it.

BUG=b:253003881
TEST=With depthcharge change, set SD_BOOT_DISABLE on nivviks and check
SD card is not initialised in depthcharge.

Change-Id: I1a3a533e4e74e48d9ce4a9678b812cb62ce2066b
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69541
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 18:56:21 +00:00
Reka Norman
5013f7d152 mb/google/nissa: Remove SI_ME subregions
The SI_ME subregions were added to support using the CSE stitching tools
(cse_serger). Use of the stitching tools has been reverted and probably
won't be re-enabled soon, so the subregions are not currently used by
anything. They also don't match the actual region sizes chosen by the
FIT tool, so remove them to avoid confusion. The other option would be
to manually keep them in sync with the sizes chosen by the FIT tool, but
this would be extra manual effort without much benefit.

BUG=None
TEST=Build and boot on nivviks

Change-Id: I993e07a060445ab8de1b0e40a023e8248867c53c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69540
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-15 16:25:18 +00:00
Felix Held
cf92ecf6f1 soc/amd: commonize generation of the PIC/APIC mapping tables
Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.

BUG=b:182782749

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 14:29:33 +00:00
Liju-Clr Chen
c5b32ee8d8 mb/google/geralt: Enable RTC for eventlog timestamps
Without RTC, the timestamps in the eventlog are currently all
'2000-00-00 00:00:00'. Enable RTC to get the correct timestamps.

localhost ~ # head /var/log/eventlog.txt
0 | 2022-10-15 22:59:38 | Log area cleared | 4088
1 | 2022-10-15 22:59:38 | Memory Cache Update | Normal | Success
2 | 2022-10-15 22:59:45 | System boot | 0
3 | 2022-10-15 22:59:46 | Firmware vboot info | boot_mode=Developer |
fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
localhost ~ #
localhost ~ # date
Sun Oct 16 01:42:59 PDT 2022
localhost ~ #

BUG=b:233720142
TEST=check the timestamp field in /var/log/eventlog.txt

Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69432
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 13:15:31 +00:00
Frank Chu
89321cfff0 mb/google/brya/var/marasov: Add memory config for marasov
Configure the rcomp, dqs and dq tables based on the schematic.

BUG=b:254365935
BRANCH=None
TEST=Built successfully

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69149
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-15 13:15:08 +00:00
Angel Pons
d704c76b9f mb/clevo/cml-u: Fix CMOS options
The `hyper_threading` CMOS option was hooked up to the wrong enumeration
and lacked a default value in `cmos.default`. Thus, use the correct enum
for the `hyper_threading` option, remove the now-unused "backwards" enum
and provide a default value in `cmos.default`.

Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69521
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 13:14:17 +00:00
Felix Held
9a1da4bd07 mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
Gardenia and Pademelon had the same mainboard_picr_data and
mainboard_intr_data data arrays. Compared to Kahlee there were 4
differences for PIRQ_F, PIRQ_SCI, PIRQ_SD and PIRQ_SATA in the IRQ data
arrays.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia460b467990be7c3e6261440505988a9770ea084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68852
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 11:44:31 +00:00
Felix Held
7e247a3fa8 mb/google/kahlee/mainboard: rewrite IRQ mapping handling
Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD
SoCs to allow making the largest part of the corresponding code common
for all AMD SoCs in the coreboot tree.

The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the
data tables which is the PIT IRQ which looks very wrong to me, so it was
changed to PIRQ_NC. Since the ASF and likely also the SDIO controller
are unused, this shouldn't change runtime behavior. The data tables also
had non 0 and non 0x1f entries in the following locations the internal
BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37,
0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the
description in the BKDG says that it controls the IRQ mapping of another
internal PCI device, but that PCI device doesn't exist in the SoC.

TEST=No obvious IRQ-related breakage on google/liara

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68851
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 11:33:33 +00:00
Ravi Sarawadi
33005df7bc soc/intel: Add Meteor Lake IGD device id 0x7d45
Add new IGD device.

Reference: EDS Vol 1 (640228)

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-15 10:46:21 +00:00
Frank Chu
f2e2dc80fa mb/google/brya/var/marasov: use i2c1 for TPM for marasov
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
marasov variant.

BUG=b:254365935
TEST=FW_NAME=marasov emerge-brya coreboot

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I4d155fb35424d1ec12e825ca0aab233bd3cd607e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69376
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15 06:43:50 +00:00
Meera Ravindranath
f337537a03 drivers/wifi: Fix DSM parsing issue
commit b6ebcdfde5 restructured
the DSM implementation which resulted in a regression
and DSM values gets filled with junk values.
This CL fixes this issue and passes the right pointer to the dsm
ids structure.

BUG=b:256938177
TEST=Build, boot Nivviks and check if the DSM values are parsed
correctly in the  SSDT dump.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88782b0b7dde1fca0230472a38628e82dfd9c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69427
Reviewed-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2022-11-15 04:58:49 +00:00
Elyes Haouas
0f864f6ef9 mb/google: Fix log messages
Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'.

Change-Id: Id31c25f5b8686f951ab4f331682b82ff327d5e78
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15 04:17:34 +00:00
Tyler Wang
8f692f41bf mb/google/nissa/var/craask: Remove RFIM settings for Craask
Request by RF team, remove RFIM related settings to disable it.

BUG=b:239657092
Test=RF team test on DUT and check it's disable

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I1eb4d93c2821cb067628dc1228c6c522d292c739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-15 04:16:24 +00:00
Arthur Heymans
574b8b6fd2 testing/Makefile.inc: Fix removing clang builds
The directory names were wrong.

Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69568
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 04:14:59 +00:00
Arthur Heymans
17e68572ca soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion
Explicitly cast integers to fix building for long mode.

Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-14 22:40:02 +00:00
Arthur Heymans
62eb94c9d3 nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree
Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-14 22:34:23 +00:00
Felix Held
e2949b7c9c drv/intel/fsp2_0/hand_off_block: rework fsp_find_extension_hob_by_guid
Use the new fsp_hob_iterator_get_next_guid_extension function in
fsp_find_extension_hob_by_guid instead of iterating through the HOB list
in this function.

TEST=AMD_FSP_DMI_HOB is still found and the same type 17 DMI info is
printed on the console.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d4ce14c8a5494763de3f65ed049f98a768c40a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14 18:53:34 +00:00
Felix Held
2516947fd9 drivers/intel/fsp2_0/hand_off_block: use iterator in fsp_find_range_hob
Drop the find_resource_hob_by_guid implementation and use the new
fsp_hob_iterator_init and fsp_hob_iterator_get_next_guid_resource
functions in fsp_find_range_hob.

TEST=Mandolin still finds the TSEG range HOB and uses the correct TSEG
location.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00786cbeea203fba195ddc953c3242be544a7d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14 18:51:20 +00:00
Felix Held
2e81436be8 soc/amd/*/root_complex: use FSP HOB iterator functions
Use the newly added functions to iterate over the FSP HOBs to report the
resources used by FSP to the resource allocator instead of open coding
the iteration over the HOBs in the SoC code.

TEST=Patch doesn't change reported resources on Mandolin

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14 18:50:45 +00:00
Felix Held
79db98764e drivers/intel/fsp2_0/hand_off_block: add functions to iterate over HOBs
Introduce iterator function to go through the HOBs that will be used in
follow-up commits both from the rest of the common FSP HOB access code
and from SoC-specific code that needs to access specific HOBs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If86dde2a9f41d0ca7941493a92f11b91a77e2ae0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14 18:50:24 +00:00
Arthur Heymans
fa775b7651 cpu/cpu.h: Remove unused functions prototypes
These were dropped with LEGACY_SMP_INIT.

Change-Id: Iecaf9ba3d31d22311557b885b31e98a0edd74d96
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-14 17:22:47 +00:00
Arthur Heymans
e095c462dc device/Kconfig: Don't allow native mode in x86_64
This option is not working so don't advertise it.

Change-Id: I910162756a567289b2484a5445360a3197ae848c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14 15:54:09 +00:00
Arthur Heymans
6e85740236 arch/x86/Kconfig: Move AMD stages arch to common code
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE
needs to be build as x86 stage.

Change-Id: I126801a1f6f523435935bb300f3e2807db347f63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14 15:54:02 +00:00
Leo Chou
32882c97f9 mb/google/nissa/var/pujjo: Modify touch screen hid to ELAN901C
Modify touch screen hid for Pujjo board.

BUG=b:258586760
TEST=Use the value to boot on Pujjo successfully.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-14 01:37:23 +00:00
Kyösti Mälkki
987f46c276 arch/x86/mpspec.c: Drop weak write_smp_table()
Creating MP table is not useful when it does not include
the interrupt routing entries.

Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69489
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 18:49:26 +00:00
Kyösti Mälkki
ca5a793ec3 drivers/generic/ioapic: Drop poor implementation
This disables MP table generation for the affected boards
since interrupt routing entries would now be completely missing.

The mechanism itself is flawed and redundant. The mapping
of integrated PCI devices' INTx pins to IOAPIC pins is
dependent of configuration registers and needs not appear
in the devicetree.cb files at all.

The write_smp_table implementation would skip writing
any entry delivering to destination IOAPIC ID 0. This
does not follow MP table specification.

There were duplicate calls to register_new_ioapic_gsi0(),
with another present under southbridge LPC device.

Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 18:48:52 +00:00
Kyösti Mälkki
9202cab661 mb/gigabyte/ga-945gcm-s2c,skl: Drop HAVE_MP_TABLE
The weak implementation of write_smp_table() is not useful
without DRIVERS_GENERIC_IOAPIC and related entries in
devicetree.cb. No interrupt routing entries are present
in the generated MP table.

Change-Id: I71a209e95ae1fe8c1c90b61c6ac0fb0e7bcc7eca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69490
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 16:51:00 +00:00
Kyösti Mälkki
e975e1bc6c mb/asus/p5gc-mx: Drop HAVE_MP_TABLE
The weak implementation of write_smp_table() is not useful
without DRIVERS_GENERIC_IOAPIC and related entries in
devicetree.cb. No interrupt routing entries are present
in the generated MP table.

Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 16:50:51 +00:00
Marc Jones
efdd3e8c7b acpi: Update default processor string from decimal to hex
Update the default processor sting from decimal to hex to increase
the default number of Processor NamedObjects from 100 to 256
ie: CP00-CP99 is now CP00-CPFF

This fixes MADT table generation for system up to 256 cores.

Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: Id60a39d99fa77d1d89ad655ddecdebcc8a422f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 15:41:59 +00:00
Tim Chu
804c370d74 inc/dev: Add definitions for Link Capability and Slot Capability
Add definitions for Link Capability and Slot Capability and these
definitions may be used in smbios type 9.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 15:41:21 +00:00
Matt DeVillier
bfad0b0651 mb/google/zork: rename baseboard GPIO table getter for clarity
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since
the GPIO table comes from the baseboard (and is not overridden by any
variant).

Drop the __weak qualifier as this function is not overridden.

This is similar to the change made for skyrim in CB:67809

Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 15:38:12 +00:00
Matt DeVillier
c3583173ec soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage
for PCIe reset (currently set in bootblock) and touchscreen power
sequencing (not yet implemented, but will be later in the patch train).

Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 15:37:46 +00:00
Nicholas Chin
16fd5843a2 util/superiotool: Add SMSC MEC5035
Also comment out the SMSC FDC37M602 which has a conflicting
ID and has never had the LDN/register layout anyway.

Tested on a Dell Latitude E6400

Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 15:33:41 +00:00
Nicholas Chin
3d2a6f4956 util/superiotool: Add Nuvoton NCT6685D/NCT6686D
There doesn't seem to be a datasheet available for the NCT6685D, but
there is one for the NCT6686D. The 85D seems to return the same ID as
the 86D, and the registers do seem to be returning valid data other than
LDN 0xf which returns all 1s. The LDN and register layout appears to be
identical to the NCT6687D-W.

Tested on a Lenovo ThinkCentre M900 with a NCT6685D.

Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-13 15:32:26 +00:00
Arthur Heymans
27c94b586c util/xcompile: Fix building for clang + 64bit
-malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name
variable is not needed anymore.

TESTED: This also boots on qemu q35

Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-13 15:27:07 +00:00
Martin Roth
e13b263ef3 mb/emulation/qemu: Move packed attribute
The jenkins build complains about this now that clang has been added.

src/mainboard/emulation/qemu-q35/cpu.c:37:1: error:
attribute '__packed__' is ignored, place it after "union" to apply
attribute to type declaration [-Werror,-Wignored-attributes]
__packed union save_state {

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id8faa24239505d808d09c00d825344edc7c4b7d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-13 13:29:04 +00:00
Arthur Heymans
8855db9542 util/testing: Buildtest with clang
Some platforms correctly build and boot with clang. Add this to our CI.

Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:23:42 +00:00
Arthur Heymans
852ab75005 drivers/ipmi/ocp: Fix building with clang
Fix the following warning:
error: use of logical '&&' with constant operand
[-Werror,-Wconstant-logical-operand]

Change-Id: I9a2f03a0e05088a780ce1e829859421b461032ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69437
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:23:02 +00:00
Arthur Heymans
9df0fee8fa arch/x86/memmove: Add 64bit version
The 64bit handles 64bit input variables properly.

TESTED: Both qemu and real hardware can use LZ4 properly which use this
code.

Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 23:22:17 +00:00
Mario Scheithauer
bf89aaecfa soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbE
For extern ethernet PHY access it is necessary to enable the 'scan_bus'
functionality.

Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69385
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:16:42 +00:00
Sergii Dmytruk
7221a6cfc5 security/tpm: improve tlcl_extend() signature
Until now tcg-2.0/tss.c was just assuming certain buffer size and
hash algorithm. Change it to accept digest type, which the call sites
know.

Also drop `uint8_t *out_digest` parameter which was always `NULL`
and was handled only by tcg-1.2 code.

Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68745
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-11-12 23:16:07 +00:00
Tarun Tuli
3ff77016da mb/google/brya/var/agah: Add RPL Support to Agah
Enable RPL support for Agah.

BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.

Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69398
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:13:57 +00:00
Zheng Bao
5ca1343b5f amdfwtool: Add definition of instance for PSP entry
Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:12:00 +00:00
Ivy Jian
06eb6946d0 mb/google/rex: Add Write Protect GPIO to cros_gpios
This will enable crossystem to access WP GPIO

BUG=b:258048687
TEST= wpsw_cur in crossystem reads the correct gpio

Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:09:44 +00:00
Ren Kuo
ea7c727a94 mb/google/brya/variants/volmar: Disable the unused FP pads
Disable the unused fingerprinter(FP) gpio for zavala by fw_config
FPMCU_MASK field.

BUG=b:250807253
TEST=build firmware and veriify the FP function on volmar DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I0af1b7c3e4829ecab98525ead4f078c3eb6485d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69465
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:09:07 +00:00
Subrata Banik
93001ef9b7 mb/google/brya/var/marasov: Enable ISH driver and firmware name
BUG=b:234776154
TEST=Build and boot Marasov UFS, copy ISH firmware to host
file system /lib/firmware/intel/adl_ish_lite.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adl_ish_lite.bin loaded

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic53a3cbdf83825adc27f37877a14f4f405d4a5ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69377
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12 23:07:38 +00:00
Subrata Banik
6f1a7b6720 mb/google/brya/var/marasov: Select ISH driver
This patch ensures that Marasov selects the ISH driver for
devices with UFS enabled.

BUG=b:256566011
TEST=Able to build Marasov.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I97a0aa3bc6976be32ddbf1fc6b37c16bb62a62e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69379
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-12 23:06:56 +00:00
Macpaul Lin
5d16f8d5b9 soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
This replaces 'SPDX-License-Identifier' tags in all the files under
soc/mediatek/mt8195 for better code re-use in other open source
software stack.

These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces these files to
"GPL-2.0-only OR MIT" license.

Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66625
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-12 23:06:19 +00:00
Caveh Jalali
603de3f763 ec/google/chromeec: Deprecate dev_index from google_chromeec_reboot
This removes the dev_index argument from the google_chromeec_reboot
API. It's always set to 0, so don't bother passing it.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 23:01:47 +00:00
Caveh Jalali
675de7524c ec/google/chromeec: Simplify error handling for GET_VERSION
We don't need to check the lower level error code to determine if an EC
call succeeded. Simply check the return value of the call.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 23:00:38 +00:00
Caveh Jalali
0bab8ed085 ec/google/chromeec: Simplify get_uptime_info error handling
google_chromeec_get_uptime_info() doesn't need to return an error code
from the lower level calls for the caller to interpret. It is more
appropriate to return a success/failure boolean.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 22:59:28 +00:00
Martin Roth
60293e9b1f lib/ramtest.c: Update ram failure post code
coreboot already has a ram failure post code defined, but the ram test
functions weren't using it, and were using 0xea instead.
This changes those failures to display 0xe3, the value defined in
post_codes.h by POST_RAM_FAILURE.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I21ef196e48ff37ffe320b575d6de66b43997e7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-11-12 22:53:14 +00:00
Martin Roth
9a8667a841 device & commonlib: Update pci_scan_bus postcodes
The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end

I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function.  I don't think all three are needed.

0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code.  Those postcodes should be adjusted to avoid conflicting.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 22:52:54 +00:00
Elyes Haouas
898176a24c treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 18:00:16 +00:00
Elyes Haouas
7d67a19cfa util/amdfwtool/amdfwtool: Don't rewrite macros
Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 17:59:20 +00:00
Arthur Heymans
b291dc8776 nb/intel/ironlake: Work around unused variable warning
It's not clear whether this variable should actually be used or not so
leave it be with a FIXME comment.

Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:45:32 +00:00
Arthur Heymans
e55aa0bc8f soc/intel/meteorlake: Fix set but unused variable
Clang complains about this.

Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:45:22 +00:00
Arthur Heymans
d4dfc21f70 cpu/x86: Set thread local storage in C code
Doing this in C code is way easier to understand. Also the thread local
storage is now in .bss instead of the AP stack. This makes it more
robust against stack overflows, as APs stacks overflow in each other.

TESTED: work on qemu.

Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69435
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 14:23:51 +00:00
Arthur Heymans
407e00dca0 include/cpu/msr.h: transform into an union
This makes it easier to get the content of an msr into a full 64bit
variable.

Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 14:23:35 +00:00
Arthur Heymans
0c9fa6f2ce mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
Depending on whether qemu emulates an amd64 or i386 machine the SMM
save state will differ. The smbase offsets are incompatible between
those save states.

TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a
working smihandler, ASEG and TSEG.

Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 10:27:09 +00:00
Arthur Heymans
4c4bd3cd97 soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 08:56:18 +00:00
Kyösti Mälkki
bd72bfece2 cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
The disablement of SSE2 was not honoured since there is explicit
select under CPU_INTEL_MODEL_F2X. The removed commentary originates
probably from ROMCC romstage implementation.

Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-12 05:09:21 +00:00
Kevin Chiu
8e275af3ee mb/google/brya/var/gladios: Add GL9750 SD card reader support
BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12 03:34:58 +00:00
Kevin Chiu
02d4116fd6 mb/google/brya/var/gladios: Include GL9763E driver for eMMC support
Support GL9763E as a eMMC boot disk.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2b29309615df381f1e24f29fc048c6f9bf216b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69425
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12 03:34:33 +00:00
Elyes Haouas
357c229173 sb/intel/i82801dx: Clean up includes
Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-12 03:33:14 +00:00
Michael Niewöhner
3504918b43 mb/clevo/l140mu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I6c4637936761cd62571b5d19fe2afd65560f49a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59850
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:28 +00:00
Michael Niewöhner
dc3e7def5f mb/clevo/l140cu: make use of the new clevo/it5570e ec driver
Hook up the new EC driver.

Tested:
 - Fn hotkeys work (brightness, display, volume, tp toggle, ...)
 - Display lid
 - Sleep/wake
 - Camera (including Fn toggle)
 - Bluetooth (both CNVi and PCIe card)
 - Wi-Fi (both CNVi and PCIe card)
 - CMOS options

Known issues:
 - Touchpad toggle needs OS setup; see CB:68791
 - UCSI is not implemented; see CB:68791

Change-Id: I28ac401ada2945bb58fe862895458b10fed505fe
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:14 +00:00
Michael Niewöhner
d6ac7a9a3a mb/clevo/l140cu: drop System76 EC
Drop System76 EC, since the ODM board does not use it. Clevo EC FW
support will be added and hooked up cleanly in the follow-up changes.

Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59816
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 22:43:01 +00:00
Michael Niewöhner
e1e65cb0f1 ec/clevo/it5570e: add driver for EC used on various Clevo laptops
This adds a driver for the ITE IT5570E EC in combination with Clevo
vendor EC firmware. The interface is mostly identical on various laptop
models. Thus, we have implemented one common driver to support them all.

The following features were implemented:
 - Basics like battery, ac, etc.
 - Suspend/hibernate support: S0ix, S3*, S4/S5
 - Save/restore of keyboard backlight level during S0ix without the need
   for Clevo vendor software (ControlCenter)
 - Flexicharger
 - Fn keys (backlight, volume, airplane etc.)
 - Various configuration options via Kconfig / CMOS options

* Note: S3 support works at least on L140CU (Cometlake), but it's not
        enabled for this board because S0ix is used.

Not implemented, yet:
 - Type-C UCSI: the EC firmware seems to be buggy (with vendor fw, too)
 - dGPU support is WIP

An example of how this driver can be hooked up by a board can be seen in
in change CB:59850, where support for the L140MU is added.

Known issues:

 - Touchpad toggle:
   The touchpad toggle (Fn-F1) has two modes, Ctrl-Alt-F9 mode and
   keycodes 0xf7/0xf8 mode. Ctrl-Alt-F9 is the native touchpad toggle
   shortcut on Windows. On Linux this would switch to virtual console 9,
   if enabled.  Thus, one should use the keycodes mode and add udev
   rules as specified in [1]. If VT9 is disabled, Ctrl-Alt-F9 mode could
   be used to set up a keyboard shortcut command toggling the touchpad.

 - Multi-fan systems
   The Clevo NV41MZ (w/o dGPU) has two fans that should be in-sync.
   However, the second fan does not spin. This needs further
   investigation.

[1] https://docs.dasharo.com/variants/clevo_nv41/post_install/

Testing the various functionalities of this EC driver was done in the
changes hooking up this driver for the boards.

Change-Id: Ic8c0bee9002ad9edcd10c83b775fc723744caaa0
Co-authored-by: Michał Kopeć <michal.kopec@3mdeb.com>
Co-authored-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Co-authored-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11 22:42:46 +00:00
Sean Rhodes
064c6ced40 ec/starlabs/merlin: Rename the Cezanne EC code
This EC code is for the Byte, a Cezanne Mini PC. The EC is different
to the Cezanne StarBook Mk VI. Rename it to `-desktop`, so the laptop
variant becomes the primary.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I25f812cb1c6cefca1ebbe3bee5d20cf521dd60af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 18:24:45 +00:00
Felix Held
9405dd066e drivers/intel/fsp2_0/hand_off_block: remove unneeded line breaks
Since the characters per line limit was increased from 80 to 96, some
line breaks can be removed to improve code readability.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92aa3fec8c8caba143e418efc999ec4a7c5d93c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-11 18:02:37 +00:00
Felix Held
dafc6194a0 soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob case
When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 17:45:18 +00:00
Kevin Chiu
88cf831ed1 mb/google/brya/var/gladios: use i2c1 for TPM support
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.

BUG=b:239513596
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-11 16:04:58 +00:00
Nicholas Chin
81827aad3c drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347
The WCH CH347 presents a USB CDC serial port on interface 4 while in
operating modes 0, 1, and 3. Mode 0 also presents a UART on interface
2 but this is ignored for compatibility with the other modes. Mode 2
uses vendor defined HID usages for communication and is not currently
supported. Like the FT232H the data format is hard coded to 8n1.

Tested using a CH347 breakout board and a Dell Latitude E6400.

Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68264
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-11 13:33:34 +00:00
Kyösti Mälkki
458751c2d5 aopen/dxplplusu: Add early GPIO settings
Required for 2nd COM port to work.

Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-11 12:42:34 +00:00
Arthur Heymans
a83c502d5a util/amdfwtool: Add more instances some types in BDT
Some hardware uses more instances.

Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 00:41:54 +00:00
Arthur Heymans
1f05c8044e util/amdfwtool: Add new types
These are used on newer platforms.

Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-11 00:40:22 +00:00
Martin Roth
e440403683 vc/amd/fsp/mendocino: Update FSP UPD signatures to MNDCNO
The FSPM and FSPS UPD signatures hadn't been updated from their cezanne
origins.  Change them to MNDCNO_M/S.

BUG=b:240573135
TEST=Build & boot, see new signature in boot log.

Change-Id: I9e4fcf7a9bf802aaba88f3dccf6da064c5686e96
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-11-11 00:39:20 +00:00
Jonathan Zhang
d5d9b280de acpi/acpi.c: Fix einj generation pointer arithmetics
Without a cast the aritmetics of

tat = einj + sizeof(acpi_einj_smi_t)

is the same as

tat = (uintptr_t)einj + size(acpi_einj_smi_t) * size(acpi_einj_smi_t)

So it overshoots the intended offset by a lot.

This issue only came apparent because now einj is in the small IMD
region which is close to TSEG. With the wrong aritmetics the tat
pointer ended up inside TSEG which is not accessible from the OS
causing exceptions.

TEST: observe that tat pointer is inside the small IMD below
TSEG (0x78000000 on our setup).
"acpi_create_einj trigger_action_table = 0x77ffe89c"

Change-Id: I3ab64b95c33eef01b2048816a21e17855bcb2f54
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-11 00:36:40 +00:00
Elyes Haouas
aba1c945cd /: Remove "ERROR: "/"WARNING: " prefixes from log messages
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.

Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-10 21:31:18 +00:00
Kyösti Mälkki
1d3c2e6572 arch/x86/ioapic: Reduce API exposure
Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55316
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:21:44 +00:00
Kyösti Mälkki
71c6487cf1 sb/intel/i82870: Use register_new_ioapic()
Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong,
remove it. The only platform affected is aopen/dxplplusu with
i82801dx southbridge.

Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:19:23 +00:00
Kyösti Mälkki
d165357ec3 sb,soc/intel: Use register_new_ioapic_gsi0()
Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:10:42 +00:00
Kyösti Mälkki
c0457358f6 sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()
Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:09:34 +00:00
Kyösti Mälkki
0ea8f89e40 arch/x86: Add register_new_ioapic()
Using this I/O APIC IDs will be assigned incrementally
in the order of calling. I/O APIC ID #0 is reserved for
the I/O APIC delivering GSI #0.

Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:08:57 +00:00
Kyösti Mälkki
c7da027e75 ACPI: Add acpi_create_madt_ioapic_from_hw()
Read I/O APIC ID and vector counts from hardware.

Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-10 19:08:22 +00:00
JingleHsuWiwynn
014901bd9b soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard
to soc

Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.

Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-10 19:06:41 +00:00
Tim Chu
323e5a84eb src/include/smbios: Add definition for smbios type 4 and type 9
Add definition for smbios type 4 and type 9

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-10 19:05:51 +00:00
Jan Dabros
3709186b2b mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
Skyrim platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.

BUG=b:241878652
BRANCH=none
TEST=Build kernel and firmware. Run on skyrim and verify TPM
     functionality.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-11-10 18:56:23 +00:00
Venkat Thogaru
38ea9e3ef4 mb/google/herobrine: Update comment of modem status info
Updated comment as per guidelines.

BUG=b:232302324
TEST=none

Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-10 17:28:05 +00:00
Kacper Stojek
76d2b6699d util/inteltool: Add support for Elkhart lake
Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)

Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-10 16:24:49 +00:00
Fred Reitberger
c989d3cd10 mb/amd/chausie/ec.c: Enable WLAN
Enable WLAN power and deassert the various radio disables.

TEST=boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10 15:52:36 +00:00
Fred Reitberger
fdfd63be3a mb/amd/chausie: Correct naming of EC FW
Change the EC FW CBFS filename prefix to a more accurate "ec/"

TEST=build and boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10 15:52:04 +00:00
Frank Chu
369dee5938 mb/google/brya/var/marasov: use RPL FSP headers
To support an RPL SKU on marasov, marasov must use the FSP for RPL.

Select SOC_INTEL_RAPTORLAKE for marasov so that it will use the RPL
FSP headers for marasov.

BUG=b:254365935
BRANCH=None
TEST=FW_NAME=marasov emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69367
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10 15:50:46 +00:00
Frank Chu
ad00d847f2 mb/google/brya/var/marasov: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.

DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B	0 (0000)
H9JCNNNBK3MLYR-N6E		1 (0001)
MT62F1G32D4DR-031 WT:B		4 (0100)
H9JCNNNCP3MLYR-N6E		5 (0101)

BUG=b:254365935
BRANCH=None
TEST=run part_id_gen to generate SPD id

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-10 15:50:04 +00:00
Frank Chu
8d4cb09048 mb/google/brya/var/marasov: Update devicetree setting for marasov
update devicetree setting per the schematic

BUG=b:254365935
BRANCH=None
TEST=Built successfully

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:49:37 +00:00
Arthur Heymans
961e09c631 soc/nvidia/tegra124: Fix building with clang
This kind of allocation without '=' is not working with clang.

Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:33:32 +00:00
Arthur Heymans
1b2c03b9d8 soc/sifive/ux00ddr.h: Remove set but unused variables
It looks like this code was not finished so it's left commented out
for now.

Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:32:33 +00:00
Ritul Guru
f3e4cec919 drivers/spi: Add support for Macronix SPI ROM MX77U25650F
Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-10 15:14:26 +00:00
Caveh Jalali
21552aee3f ec/google/chromeec: Fix USB_PD_PORTS response data type
The EC_CMD_USB_PD_PORTS host command returns a
struct ec_response_usb_pd_ports, not a
struct ec_response_charge_port_count.

Luckily, both structs have the same memory layout, so this is simply a
name change.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:10:25 +00:00
Caveh Jalali
2320c03087 ec/google/chromeec: Simplify KEYBOARD_BACKLIGHT error handling
Simplify the implementation of setting the keyboard backlight PWM
value. Host command stubs typcially don't need to examine the host
command's return value as stored in cmd_code because that level of
detail is not very interesting. Higher value error codes are returned in
actual result structures.

This host command can return EC_RES_ERROR for out of range PWM values
which is already a generic error and unlikely to happen since we already
limit the range to 0..100 here. Finally, none of the callers in coreboot
check the return value.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:09:48 +00:00
Caveh Jalali
b456a96361 ec/google/chromeec: Fix keyboard_backlight call
The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so
don't specify a result buffer.

BUG=b:258126464
BRANCH=none
TEST=none

Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2022-11-10 15:08:05 +00:00
Rob Barnes
a3148ca504 google/chromeec: Add ACPI method for EC Panic
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.

EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.

This will be a no-op until the kernel driver is also updated to handle
this event.

BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 15:07:09 +00:00
Martin Roth
2204cee6e9 configs: Build test STB features on google skyrim
- Update the google_skyrim.with_binaries to test printing the STB
entries.
- Add a new saved config to test building without video, building
using an x86 verstage, and STB_SPILL_TO_DRAM

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Idddcf2441b91b79575e5dfed1cc56d207234205b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-10 12:51:15 +00:00
Tyler Wang
21f52c8af8 mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_config
BUG=b:257879909
Test:Boot to OS on craask and check stylus GPIO pins

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69138
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 07:31:39 +00:00
Tyler Wang
f346a17ce3 mb/google/nissa/var/craask: Modify DPTF related settings
Request by thermal team, make below changes:

1) tdp_pl2_override: 12 --> 25
2) pl1.min_power: 3000 --> 5500
3) pl1.time_window_max: 32 * MSECS_PER_SEC --> 28 * MSECS_PER_SEC
4) pl2.min_power: 12000 --> 25000
5) pl2.max_power: 12000 --> 25000
6) pl2.time_window_min: 28 * MSECS_PER_SEC --> 1
7) pl2.time_window_max: 32 * MSECS_PER_SEC --> 1

BUG=b:239495499
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68523
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-10 07:30:50 +00:00
Victor Ding
970e33a168 mb/google/nissa/var/pujjo: Update register parameters for SX9324 tunning
Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.

BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
     (Verified register values on Pujjo)

Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10 00:59:48 +00:00
Elyes Haouas
48f9b8b773 mb/kontron/bsl6/romstage.c: Clean up includes
Change-Id: Ie3a08799294729beec83faf819fb1f249c6461cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-11-10 00:21:05 +00:00
Arthur Heymans
bbf6aef4e9 cpu/x86/Kconfig.debug_cpu: Drop unused symbol
Change-Id: I2b611773e596bea4788b05a3f58485fb3e002402
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-10 00:20:38 +00:00
Martin Roth
815c3634e3 util/scripts: Add script to run abuild on specific SOCs
This finds all the boards using a specified Kconfig option and runs both
CrOS and non-CrOS abuilds on them to make sure they're working.

Nobody wants to run the full what-jenkins-does build on their host
machine.  Hopefully this can help get some tests run locally before
pushing to coreboot.org.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-10 00:19:55 +00:00
Arthur Heymans
f158c9c961 cpu/x86/lapic.h: Fix CONFIG_X2APIC_RUNTIME
The deadlock prevention is also needed with CONFIG_X2APIC_RUNTIME when
the cpu is in x2apic mode.

TESTED: Fixes SMI generation on xeon_sp hardware with
CONFIG_X2APIC_RUNTIME.

Change-Id: I6a71204fcff35e11613fc8363ce061b348e73496
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-10 00:19:03 +00:00
Robert Zieba
a23aa1ca90 device/xhci: Factor out struct xhci_usb_info
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.

BUG=b:186792595
TEST=Builds for volteer

Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-09 23:58:03 +00:00
Robert Zieba
4428195692 device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values.

BUG=b:186792595
TEST=Built coreboot for volteer device

Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-09 23:57:49 +00:00
EricKY Cheng
065c5870e4 ec/google/chromec: Expand EC share memory for DTTS
DTTS is Dynamic Thermal Table Switching Proposal.
DTTS needs one bit to save the body detection result from EC.
Define mode change STTB bit for Desktop (1) and laptop (0).
This bit is Switch thermal table by body detection status.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 22:35:27 +00:00
Kyösti Mälkki
7b73e85283 Revert "mb/aopen/dxplplusu: Remove board"
This reverts commit eb76a455cd
and applies minor fixes to make it build again.

PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.

Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-09 18:10:54 +00:00
Arthur Heymans
c8a20b9d3b cpu/*: Drop PARALLEL_MP leftovers
These symbols and codepaths are unused now so drop them.

Change-Id: I7c46c36390f116f8f8920c06e539075e60c7118c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69361
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 18:05:55 +00:00
Felix Held
753827ef33 soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.

TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:31 +00:00
Felix Held
d92bb3c3f1 soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:04 +00:00
Arthur Heymans
600fa266bd nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:30:12 +00:00
Arthur Heymans
58955be0aa soc/intel/common/xhci: Fix building for 64bit
Tested with clang on prodrive/hermes: Boots to payload

Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69234
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:27:44 +00:00
Arthur Heymans
e0fc3da747 mb/intel/harcuvar: Fix strict prototype warning
Clang warns on both the declaration and the definction.

Change-Id: I94d979fcdbe41349c59248656066615bffd215b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09 14:27:08 +00:00
Arthur Heymans
2a86ef5bb8 superio/nuvoton/nct6687d: Fix unexpected expression
Expression after a case statement are not allowed.

This fixes building with clang.

Change-Id: Ie369454f10b515aa5601a5e78330e12f4b7a5e4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-09 14:26:03 +00:00
Arthur Heymans
2dc59e6e08 mb/prodrive/hermes: Fix format mismatch
Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 14:25:27 +00:00
Arthur Heymans
f874fc2717 cpu/x86/smm/module_loader: Fix ASEG loading
This code was never tested with SSE enabled. Now qemu enables it and
FX_SAVE encroaches on the save states. Without SSE enabled the handler
just happened to be aligned downwards enough to have the save states
fit. With SSE enabled that's not the case. The proper fix is to give the
code setting up stubs the right base address, which is the same as for
the TSEG codepath.

Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-09 14:25:03 +00:00
Werner Zeh
cc7634fd69 mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
Provide timing parameter for SSDT generation to achieve the requested
100 kHz speed with a high accuracy.

Test: Measure I2C bus clock, high and low times during I2C access from
Linux and confirm they match the specification.

Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 14:20:09 +00:00
Werner Zeh
eda13db4e9 mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS
In Linux, the I2C speed defaults to 400 kHz if there is no device
registered in ACPI which requests a different speed. Due to board
limitations (layout, bus load), 400 kHz are too fast which results in a
timing violation. Therefore, add a dummy I2C device to both used I2C
buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus
speed in Linux accordingly.

Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09 14:19:40 +00:00
Werner Zeh
14612f698c soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).

This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.

Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09 14:19:15 +00:00
Werner Zeh
6b4a1ab82a drivers/i2c/designware: Add 100 MHz controller base clock
There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as
the base clock for I2C controllers. To support them properly add a
frequency setting for 100 MHz to the designware I2C controller driver.

Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-09 14:18:56 +00:00
Tyler Wang
8ec4024ab8 mb/google/nissa/var/craask: Add wifi sar table
Add wifi sar table for craask/craaskbowl.
Use fw_config to separate different project settings.

BUG=b:247652032,b:251287099,b:251287101
Test=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 14:18:01 +00:00
Karthikeyan Ramasubramanian
5717ce6e99 soc/amd/common/block/spi: Mainboard to override SPI Read Mode
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.

BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
  11:start of bootblock                                688,046
  14:finished loading romstage                         30,865
  16:FSP-M finished LZMA decompress (ignore for x86)   91,049
Total Time: 1,972,625

After:
  11:start of bootblock                                667,642
  14:finished loading romstage                         29,798
  16:FSP-M finished LZMA decompress (ignore for x86)   87,743
Total Time: 1,943,924

Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-09 13:40:02 +00:00
Ian Feng
d08deaabe1 mb/google/nissa/var/xivu: Add Hynix new memory support
Add new ram_id:0 (0000) for memory part H9JCNNNCP3MLYR-N6E.

DRAM Part Name                 ID to assign
H9JCNNNCP3MLYR-N6E             0 (0000)

BUG=b:257867226
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: If663afbcd2e0457636f4a1c7475f1e3e40f0dd96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-09 07:56:03 +00:00
Victor Ding
20265b09dc drivers/i2c/sx9324: Add support for Linux's SX9324 driver
SX9324 driver is updated per Linux's documentation found at
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml

Supporting logic for the deprecated SX932x driver is hence guarded by
DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER

This patch by itself does not introduce functional changes to any board.
The legacy SX932x Linux driver never reached upstream Linux and is only
available in ChromeOS kernel fork of 4.4 and 5.4. Linux later accepted
a different implementation named SX9324 and has been available since
5.4. Ideally all variants should adopt the new driver; however, during
the transition phase, coreboot must support both drivers. It is better
to have a single firmware build that can work with both Linux kernel
drivers by specifying both sets of properties. Legacy driver support
should be deleted once all variants finish migration.

BUG=b:242662878
TEST=Dump ACPI SSDT then verify _DSD entries related to the legacy
     SX932x driver are identical w/ and w/o this patch
     (Tested on Craask and Nivviks)

Change-Id: I42cd6841c3a270c242ed2e739db245e858eadb3b
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69192
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09 07:51:57 +00:00
Eran Mitrani
b4d71e1ab2 mb/google/rex: Add fingerprint SPI
Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631 ("Invoke power cycle of
FPMCU on startup")

TEST=Tested on Rex - setup and logged in using fingerprint

Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-09 03:36:14 +00:00
Shaik Shahina
425413c35f cbfstool: Fix possible memory leak
Handle the possible memory leak scenario.

Foundby=klocwork
BUG=NONE
TEST=Boot to OS on Nivviks

Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220
Reviewed-by: Shahina Shaik <shahina.shaik@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-09 00:26:30 +00:00
Jonathan Zhang
5c1dcd57ee drivers/ipmi/ocp: add functions to get board configuration
These functions are added for ramstage:
* add IPMI OEM command to get board configuration.
* add function to get blade index in the sled.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68779
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 00:25:33 +00:00
Jonathan Zhang
830fec3fbb drivers/ipmi/ocp: add PCIe SEL support
Add Kconfig SOC_RAS_BMS_SEL and corresponding support for
generating PCIe error SEL records and sending them to BMC.

Add PCIe error definitions.

This is needed for SMM, so build the ipmi kcs driver in SMM.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68758
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09 00:19:17 +00:00
Jakub Czapiga
967a76bd81 vboot: Add VBOOT_CBFS_INTEGRATION support
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.

This patch also adapts mainboards and SoCs to new vboot reset
requirements.

TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08 23:03:49 +00:00
Jonathan Zhang
fe17a7d4d4 soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.

Re-define in the common code.

Update coreboot code to use FSP_X_CONFIG consistently.

Tested=On OCP Delta Lake, boot up OS successfully.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>

Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-08 22:55:20 +00:00
Solomon Alan-Dei
a2503fa2e9 util/cbfstool/bpdt_formats: Fix memory leak issues
The functions create_bpdt_hdr and create_cse_layout
in bpdt_1_6.c are defined to return pointers but
not integers as was previouly implemented.

Reported-by: Coverity(CID:1469323)
Reported-by: Coverity(CID:1469353)

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-08 22:51:36 +00:00
Martin Roth
37ccb2ce82 arch/x86 & commonlib: Add macros for postcodes used in x86/tables
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the
coreboot tree other than in arch/x86/tables.c.  Add macros to
standardize these postcodes.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-08 14:51:02 +00:00
Jakub Czapiga
605f793af8 vboot: Introduce handy vboot reboot functions
This patch groups vboot context, recovery reason and subcode saving, and
reboot calls into two handy functions:
- vboot_save_and_reboot() - save context and reboot
- vboot_fail_and_reboot() - store recovery reason and call function
  above

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08 14:44:54 +00:00
Elyes Haouas
699b833bd7 /: Remove unused <inttypes.h>
Change-Id: I16aa756039973e164c887ff5237bda69d042a235
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08 14:43:00 +00:00
Elyes HAOUAS
8fe9e541ad soc/ti/am335x/cbmem.c: Use MiB macro
Use "* MiB" instead of "<< 20".

Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-08 14:39:29 +00:00
Elyes Haouas
ad65e8c041 cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 14:38:28 +00:00
Ravi Sarawadi
df1aea1f2a soc/intel/meteorlake: Remove PM Energy Report WA
Disable Pch PM Energy Report WA was added to enhance boot time
with HFPGA only. SoC needs reporting enabled.

BUG=None
TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression..

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-08 14:13:17 +00:00
Ricky Chang
feab4a4dff mb/google/brask: Disable PCH USB2 phy power gating for brask
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for moli board. Please refer Intel doc#723158 for
more information.

BUG=b:257415959
TEST=Verify the build for brask board

Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4
Signed-off-by: Ricky Chang <rickytlchang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-08 14:12:47 +00:00
Subrata Banik
c8b9608154 soc/intel: Use PWRMBASE over static Index 0 for PMC
This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).

TEST=Able to build and boot Google, Rex to OS.

Without this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0

With this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-08 14:12:27 +00:00
Tyler Wang
c3d5b9d74f mb/google/nissa/var/craask: Add ambient thermal sensor settings
BUG=b:239495499
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
2022-11-08 14:11:06 +00:00
David Wu
4a7a0e9979 mb/google/brya/var/kano: Add mipi hi556 camera support
This patch supports multiple camera modules based on FW_CONFIG.

BUG=b:251235140
TEST=Test the changes with ov2740/hi556 camera.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Ricardo Ribalda <ribalda@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-08 14:10:31 +00:00
Dtrain Hsu
f5ead3f029 mb/google/brya/var/kinox: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kinox board. Please refer Intel doc#723158 for more
information.

BUG=b:257373738
TEST=Verify the build for kinox board

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 14:09:44 +00:00
Kevin Chiu
9429844f81 mb/google/brya/var/lisbon: Disable thunderbolt ports
Lisbon doesn't support thunderbolt.

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 00:27:58 +00:00
Jamie Ryu
4d23b9f18b mb/intel/mtlrvp: Enable ACPI and add ACPI table
This enables ACPI configuration and add ACPI table.

BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-08 00:26:17 +00:00
Ravi Mistry
d92745bb98 util/superiotool/fintek.c: Fix F71808A hardware monitor readouts
Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.

Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.

Tested on a HP 500-319na (Memphis-S / IPM87-MP).

Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 23:20:08 +00:00
Selma Bensaid
67ce1f251a vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
The headers added are generated as per FSP v3361.07

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:254054169
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-07 20:45:00 +00:00
Sudheer Kumar Amrabadi
9620ddc8f2 soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.

BUG=b:218406702
TEST=reboot from AP console (on CRD3)
     prior to fix (from cbmem dump):
         1000:depthcharge start 1,139,809 (152,679)
     after fix (from cbmem dump):
         1000:depthcharge start 1,041,109 (46,353)

Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-11-07 18:06:36 +00:00
Karthikeyan Ramasubramanian
06d5b8b7fe soc/amd/mendocino: Enable x86 SHA accelerator
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.

Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:57:16 +00:00
Karthikeyan Ramasubramanian
4f9853a9a5 security/vboot: Update build rules using x86 SHA extension
Currently build rules allow using x86 SHA extensions for all coreboot
stages when enabled. On some SoCs where verstage can run in non-x86
environment, x86 SHA extension cannot be used. Update build rules
accordingly such that x86 SHA extensions can be used in AMD SoCs. This
is particularly useful when CBFS verificiation is enabled which verifies
the hash of the CBFS file being loaded.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration
is used when a CBFS file is loaded and observe an overall improvement of
10 ms.

Change-Id: I4f388e963eb82990cda41d3880e66ad937334908
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68953
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-07 14:57:01 +00:00
Maximilian Brune
2f548e597b drivers/intel/fsp2_0/memory_init.c: clean code
No need to call a function that just instantly returns.
It greatly enhances readability to just check before calling a funtion
and it also removes an extra argument.

Change-Id: I4d57c45ede520160ef615725c023b7e92289a995
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:39:32 +00:00
Jamie Ryu
0e7a52a138 mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-P
This adds an initial mainboard code for mtlrvp, Intel Meteorlake
reference platform.

BUG=b:224325352
TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07 14:36:35 +00:00
Kane Chen
11be5562b2 soc/intel/common/block/pcie/rtd3: Skip Power On if _STA returns 1
RTD3,_ON method sometimes can create delays during system boot.
Even when the power is already up, kernel still tries to call _ON
method to power up device, but it's unnecessary.

RTD3._STA returns device power, so _ON method can check _STA and see
if the power on process can be skipped

BUG=b:249931687
TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on
     Crota. Suspend stress test passes 100 cycles

Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07 14:36:10 +00:00
Arthur Heymans
778c7af37a mb/intel/adlrvp: Fix expected statement
Switch cases expect a statement so move the default label.

TEST: With BUILD_TIMELESS=1 binary remains identical.

Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66266
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:27:15 +00:00
Ravi Sarawadi
640b040f6f soc/intel/meteorlake: Implement SOC Die lock down configuration
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:22:33 +00:00
Arthur Heymans
7d6bf83afc vendorcode/amd/ccx_cppc_data.h: Fix header guard
Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:21:30 +00:00
Arthur Heymans
4081d6c053 soc/intel/meteorlake: Fix incompatible function pointers
const void is a meaningless return type and clang complains about
incompatible function pointer signatures.

Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07 14:20:54 +00:00
Sean Rhodes
16ab8d591d 3rdparty/blobs: Advance submodule pointer
This contains the following commits:
* 835724d: mainboard/starlabs/starbook: Update the EC binaries
           for StarLabs
* ecbe941: soc/mediatek: Update capitalization of coreboot
* 0e4444e: soc/mediatek/mt8188: Update MCUPM firmware from
           v1.01.02 to v1.01.03
* 88570f6: mainboard/starlabs/starbook/adl: Update the EC binary
           to 1.01 by Sean Rhodes
* f8e84db@ mainboard/starlabs/cezanne/starbook: Add EC binary
           1.02 by Sean Rhodes

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7afd43102718f211fe8d4fd69061dcdce5bfc323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:20:07 +00:00
Sean Rhodes
35354583cd mb/starlabs/*: Enable the Mirror flag for boards that support it
Enable the mirror flag for CML and TGL.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I51678bdb8d876d238076e12c6315a53c5da59628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:19:46 +00:00
Sean Rhodes
b42ca4d0b2 ec/starlabs/merlin: Add support for enabling the mirror flag
When enabled, the EC will mirror the firmware contained inside the
coreboot ROM. This allows it to be updated at the same time as
coreboot.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ief088e012b65be32648f581fc3190e1000bca241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:19:24 +00:00
Matt DeVillier
e477b0e8de Documentation/drivers: Update section on touchscreen runtime detection
Update section now that google/skyrim and google/guybrush implement
power sequencing and touchscreen runtime detection.

Change-Id: Ida63bebf18575d6856edfc65965ff82a4072df87
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07 14:17:46 +00:00
Matt DeVillier
75d67a42c7 mb/google/guybrush: Use detect vs probed flag for touchscreens
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.

BUG=b:121309055
TEST=build/boot ChromeOS and Linux on guybrush, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.

This mirrors the changes made for skyrim in CB:67779.

Change-Id: Ib6a76b969d3a245eccde5352231eb7e36736f2e0
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07 14:17:15 +00:00
Matt DeVillier
c848ff6eb7 mb/google/guybrush: Implement touchscreen power sequencing
As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.

Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.

This mirrors the change to skyrim in CB:67778.

BUG=b:121309055
TEST=build/boot guybrush with rest of patch series

Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-07 14:17:00 +00:00
Martin Roth
65a0e5a92d util/scripts: Add script to show platforms, CPU, type, and date added
This is the script used to generate the list of platforms that were
removed from the master branch at each release.  Generate a list for the
old branch, another for the new, and compare the two.

Representative output:
```eval_rst
+-------------------------+-------------------+------------+----------+
| Vendor/Board            | Processor         | Date added | Brd type |
+=========================+===================+============+==========+
| 51nb/x210               | INTEL_KABYLAKE    | 2020-03-16 | laptop   |
| acer/aspire_vn7_572g    | INTEL_SKYLAKE     | 2022-01-28 | laptop   |
| acer/g43t-am3           | INTEL_X4X         | 2020-09-28 | desktop  |
| amd/bilby               | AMD_PICASSO       | 2021-02-17 | eval     |
| amd/birman              | AMD_MORGANA       | 2022-10-10 | eval     |
| system76/whl-u          | INTEL_WHISKEYLAKE | 2021-04-14 | laptop   |
| ti/beaglebone           | TI_AM335X         | 2013-05-26 | sbc      |
| up/squared              | INTEL_APOLLOLAKE  | 2019-05-22 | mini     |
+-------------------------+-------------------+------------+----------+
```

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f7265d95df31f3a74aa2aa164f6a094c1139750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:16:47 +00:00
Sridhar Siricilla
d55ed57c36 mb/google/brya : Set EPP value for Vell board
The patch sets the EPP to 50% (0x80) for Vell. With EPP at 50%, the Vell
system demonstrated better power improvement without sacrificing the
performance.

PLT Results(Perf) with EPP@40% and EPP@50%:
	EPP@40%: Device1-656 mins, Device2-664 mins.
	EPP@50%: Device1-678 mins, Device2-677 mins.

In short, with EPP@50%, PLT KPI ran for more than 13 to 22mins compared
to EPP@40%.

Branch=firmware-brya-14505.B
BUG=b:215526166
TEST=Verified code build for Vell board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I41b15b84025d25cf59dac2d85826a3de9d725bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-07 14:16:05 +00:00
Victor Ding
00f227a216 mb/google: Probe p-sensor only for selected variants
Only a subset of variants has proximity sensors.

This patch by itself does not introduce functional changes to any board.
It is mainly to ease migrating SX9324 from the legacy driver to the
linux one - allowing gradual migration variant by variant.

BUG=b:242662878
TEST=Dump ACPI SSDT then verify they are identical w/ and w/o this patch

Change-Id: Ic00e0d9eafcef2c9eaf32571fecf6190777cec36
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69191
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:14:38 +00:00
Arthur Heymans
36695f278f device/resource_allocator_v3: Drop code
No platform uses this anymore.

Change-Id: Ifccb59ae45daa8fec41a9a2d46c628ff24a0c998
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69140
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07 14:00:33 +00:00
Arthur Heymans
f4c11dcb53 cpu/x86: Drop !CPU_INFO_V2 code
Now that all platforms use parallel_mp this is the only codepath used
for cpu_info() local thread storage.

Change-Id: I119214e703aea8a4fe93f83b784159cf86d859d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69122
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 14:00:00 +00:00
Arthur Heymans
66b2888b77 cpu/x86: Drop LEGACY_SMP_INIT
This codepath is deprecated after the 4.18 release.

Change-Id: I7e90f457f3979781d06323ef1350d5fb05a6be43
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69121
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:59:35 +00:00
Arthur Heymans
e2d291b5ae mb/qemu/x86: Remove option for LEGACY_SMP_INIT
This is deprecated after the 4.18 release.

Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69128
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 13:59:24 +00:00
Arthur Heymans
03a6ccd20d sb/amd: Remove dropped platforms
This code is now unused by any platform.

Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:59:17 +00:00
Arthur Heymans
1a010236cf nb/amd/agesa: Remove leftover code
This code is now unused by any platform.

Change-Id: I5464daa8cfb8231e2b19447c343fc80ab1d68ce8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69119
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:59:06 +00:00
Arthur Heymans
81a4fefce2 cpu/amd/agesa: Remove leftover code
Now that all agesa CPUs are removed this code is unused.

Change-Id: If0c082bbdb09457e3876962fa75725add11cb67c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69118
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:48 +00:00
Arthur Heymans
0f12381083 vendorcode/amd/agesa: Drop unused common code
No platform uses this.

Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69127
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:40 +00:00
Arthur Heymans
7036ded25d vendorcode/amd/agesa/family16: Drop unused platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:29 +00:00
Arthur Heymans
49af4f7f91 {cpu/nb}/amd/family16: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:23 +00:00
Arthur Heymans
5d15212228 vendorcode/amd/agesa/fam15tn: Drop unused platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69125
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:09 +00:00
Arthur Heymans
9a458e4e58 {cpu/nb}/amd/family15tn: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I18eb1c1ccad16980a4e57318dec411b82c45b25a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69116
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:58:01 +00:00
Arthur Heymans
713e3c087b vendorcode/amd/agesa/fam14: Remove dropped platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:57:45 +00:00
Arthur Heymans
dbdf170dcd {cpu/nb}/amd/family14: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Ieaac0a32e71d208b66fd2c4e26f5349abc921d4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69115
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:57:38 +00:00
Arthur Heymans
eb76a455cd mb/aopen/dxplplusu: Remove board
This board use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:57:22 +00:00
Arthur Heymans
6baee3d287 mb/*/*: Remove AMD agesa family16 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I43c7075fb6418a86c57c863edccbcb750f8ed402
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:57:15 +00:00
Arthur Heymans
f9decbb0c7 mb/*/*: Remove AMD family14 boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:57:06 +00:00
Arthur Heymans
e56f0c7cab mb/*/*: Remove AMD FAMILY15TN boards
These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9efb5cb1149cc4cf6337c47af8a2f4c4b55f4368
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-07 13:56:55 +00:00
Fred Reitberger
5e8e911b7c soc/amd/common/include/gpio_defs.h: Add comment for accuracy
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other
SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times
slightly.

Time  PCO      Others
1mS   0.915mS  1.220mS
2mS   2.013mS  2.684mS

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 12:24:32 +00:00
Frank Chu
502dc54ffc mb/google/brya: Create marasov variant
Create the marasov variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:254365935
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MARASOV

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69052
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07 09:49:55 +00:00
Subrata Banik
ca971d1325 lib: Add LPDDR5x DRAM type
BUG=none
TEST=Able to build and boot Google, Rex SKU2 (Micron LPDDR5x
MT62F1G32D2DS-026).

Without this code change:
[INFO ]  SPD: module type is UNKNOWN

With this code change:
[INFO ]  SPD: module type is LPDDR5X

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If620cf51133ca295fd3f1cbecbb472beb337b9fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69226
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 02:29:23 +00:00
Angel Pons
624bf72709 soc/intel/cannonlake: Fix GPIO reset mapping
According to document 337348-001 (Intel® 300 Series and Intel® C240
Series Chipset Family Platform Controller Hub Datasheet - Volume 2
of 2), the only GPIOs that support PWROK reset are those in the GPD
group. The mappings themselves are correct, but they're assigned to
the wrong communities.

Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07 02:29:09 +00:00
Ren Kuo
6ec48057d0 mb/google/brya/variants/volmar: Add firmware config field for FPMCU
The fingerprint(FP) feature is only for volmar,and it's not for zavala.
Add FPMCU_MASK field in fw_config to disable the FP function for
zavala, and reserve FP function for shipped volmar.
Define the value as following:

	field FPMCU_MASK 10
		option FPMCU_ENABLED		0
		option FPMCU_DISABLED		1
	end

BUG=b:250807253
TEST=build firmware and verify the fp function in volmar DUT.
     write `disable=1` and 'enable=0' in FPCMU_MASK field.
     check the fp function and run `ectool --name cros_fp version`
     It works as expected.

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I867771904811459697056662d5e29c545a1a9474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68917
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 01:24:45 +00:00
Arthur Heymans
27802bb7b2 cpu/x86/mp_init.c: Use existing code to create cpu struct device
Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-05 17:18:33 +00:00
Matt DeVillier
6b8c06dc39 mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table
Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs. Will be used to set
touchscreen GPIOs as part of power sequencing in a subsequent commit.

Rename all variant tables and getter functions to match.

This mirrors the changes made for skyrim in CB:67810

Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05 12:14:19 +00:00
Matt DeVillier
624aa04ed6 mb/google/guybrush: rename baseboard GPIO table getter for clarity
Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since
the GPIO table comes from the baseboard and is overridden by a separate
table from the variant.

Drop the __weak qualifier as this function is not overridden.

This is similar to the change made for skyrim in CB:67809

Change-Id: I14c79fad04f18d874ce6ff7e572bb237445db8b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-05 12:13:50 +00:00
Casper Chang
cf886b54ef mb/google/brask: Disable PCH USB2 phy power gating for moli
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for moli board. Please refer Intel doc#723158 for
more information.

BUG=b:257373742
TEST=Verify the build for moli board

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I457d410501be996f0f29ec622e1829f1581c4970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69193
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
2022-11-05 05:03:18 +00:00
Werner Zeh
44bf309309 soc/intel/block/power_limit: Avoid MSR read if it is not needed
In function 'set_power_limits' there is a path to bail out early if the
Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case
reading the MSR PLATFORM_INFO is useless and can be avoided. So read it
right before the value is needed.

This was found by the scanbuild.

In addition, fix an unnecessary line break to increase code readability.

Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-05 03:01:54 +00:00
Raul E Rangel
ae129fc6d6 drivers/i2c/generic: Print error when using _CRS and PowerResource
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO. I'm making this an error because we should really clean these up.

BUG=b:210694108
TEST=Boot guybrush and see error:
> I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS
> \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2022-11-05 02:09:34 +00:00
Nikolai Vyssotski
b02a5014ea src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR
When using site-local we need to have ability to override
MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in
site-local). site-local Makefiles.inc should be pulled in first
(different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten.

Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04 20:45:24 +00:00
Fred Reitberger
aab7f04904 soc/amd/*/data_fabric: Use common device ops
Use the common device ops instead of an soc-specific device ops.

TEST=builds for each soc

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:39:32 +00:00
Fred Reitberger
1a9ac34721 soc/amd/common/data_fabric: Make common device ops
Add the generic data_fabric_acpi_name function and device ops to common
code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I12053389a12081ddd81912a647bb532b31062093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:38:55 +00:00
Fred Reitberger
63c5a0d516 soc/amd/mendocino/data_fabric.c: Make function more generic
Make the data_fabric_acpi_name function more generic, in preparation to
move it to common.

TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:37:50 +00:00
Matt DeVillier
f72c090b7f mb/google/reef: Fix guarding of reading SKU from VPD
VPD read depends on CONFIG(VPD), not CONFIG(CHROMEOS).

TEST=build/boot snappy, verify SKU set properly in SMBIOS

Change-Id: I8aa57f793bd04dbe31f3b49bbff23e05c96592a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 20:37:43 +00:00
Fred Reitberger
2890841e6f soc/amd/*/data_fabric: Move register offsets to soc
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.

Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:36:49 +00:00
Fred Reitberger
437d011621 soc/amd/common/block/data_fabric: Use register bitslice structs
Now that the socs have defined the DF FICAA and MMIO Control registers,
update the common code to use them.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:36:20 +00:00
zhaojohn
42cdd22597 mb/google/rex: Enable RFIM for CNVi
This patch enables the radio frequency interference mitigation for Rex.

BUG=b:248391777
TEST=Booted to OS on Rex board. Verified RFIM DSM is presented to kernel
through ACPI SSDT.

Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 20:35:43 +00:00
zhaojohn
a923a431c6 soc/intel/meteorlake: Provide mitigation support for CNVi RFI
The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake.

BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.

Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 20:35:34 +00:00
Arthur Heymans
8c740b08a3 lib/coreboot_table: Rename lb_fill_pcie
By convention 'fill_lb_xxx' is used.

Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04 19:17:49 +00:00
Arthur Heymans
9948c521a6 lib/coreboot_table: Simplify API to set up lb_serial
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).

This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.

Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-11-04 19:17:13 +00:00
David Wu
5c38b234ef mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmax
Update PsysPL2 and PsysPmax.

BUG=b:253542746
TEST=Make sure PsysPL2 and PsysPamx values set
     properly (through debug output)

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0ffad751e8a99b282a5d05563a60745ee09e892c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04 19:13:19 +00:00
Tim Chu
55d11577db include/device/pci_def.h: Add some PCIe DPC/AER definitions
* Add DPC related definitions which are defined in 7.9.14 of PCIe
  6.0 spec.
* Add AER related definitions which are defined in 7.8.4 of PCIe
  6.0 spec.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-11-04 19:12:26 +00:00
Felix Held
e141f358eb Revert "soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function"
This reverts commit 3bc9fbb496.

The patch that added hob_enhancedwarningloglib.h was marked as private
after the Jenkins run, so I didn't see and submit it before submitting
the patch that gets reverted by this commit. Temporary revert this patch
to fix the coreboot tree until the issue with the missing patch is
sorted out.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04 18:47:04 +00:00
Felix Held
c8f25e0c05 Revert "drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling"
This reverts commit 059902882c.

A dependency of the previous patch that added the get_ewl_hob function
used by this patch was missing, so this patch needs to be temporary
reverted to revert the patch that breaks the build due to the missing
dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb2fa27e75eede1648ddbf82c8bfbeeb2e9220a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69228
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-04 18:46:53 +00:00
Maximilian Brune
0925bdaeb2 mb/prodrive/atlas: Add IBECC Kconfig option
Add an option on Atlas to enable IBECC (In Band Error Correction Code),
which is currently needed for endurance testing.

Test: start atlas mainboard with Linux. See in dmesg that
IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs
and see in dmesg that Linux handles it.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-11-04 15:17:49 +00:00
Maximilian Brune
2c984883ec soc/intel/alderlake: Add IBECC
Add In Band Error Correction Code to Alderlake SOC's.
It's currently needed and tested for the Prodrive Atlas mainboard.
After enabling it in the UPD, FSP-M takes care of enabling IBECC.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04 15:17:20 +00:00
Martin Roth
ffc79fbe27 payloads: Make PAYLOAD_NONE a bool outside of the choice
Instead of having the config option PAYLOADS_NONE inside the choice of
payloads, make that a separate choice that enables the payload menu.

If the no_payload option is selected, this hides the other options
and keeps them out of the saved config file and config.h

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I932c65630261a5b39809abf4dfbda5bf932c6684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-11-04 13:44:59 +00:00
Elyes Haouas
def74aaced soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-04 13:23:27 +00:00
Shelly Chang
059902882c drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
and prints EWL type 3 primarily associated with MRC training failures.

Change-Id: Ibd5b521bafd457505db4147c5d3fe41364a09045
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04 13:22:35 +00:00
Johnny Lin
3bc9fbb496 soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69144
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-04 13:21:43 +00:00
Johnny Lin
491f66ee59 soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may
contain several warnings/errors related to core, uncore and memory, etc.

mainboard can override it in its romstage.c for its own
Enhanced Warning Log check.

Change-Id: I6f542e71d20307397c398fd757d9408438f681ed
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04 13:20:56 +00:00
Liju-Clr Chen
5ab991d0ab soc/mediatek/mt8188: Disable input-gating for big-core SRAM
The input-gating is an experimental feature (but unfortunately default
enabled) and would lead to crash on MT8188, so we have to disable it
in the firmware stage.

BUG=b:233720142
TEST=CPUfreq in kernel test pass.

Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 13:19:52 +00:00
Liju-Clr Chen
78b7fb2c17 soc/mediatek/mt8188: Fix AP hang when enabling cpufreq-hw driver
When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable side-band to allow MCUPM to
access the secure registers.

BUG=b:236331463
TEST=It works well after boot to login shell.

Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-11-04 13:18:53 +00:00
Kapil Porwal
0feb5ce0c8 mb/google/rex: Fix fw_config probe for UFC and WFC
Fix fw_config probe for UFC and WFC.

BUG=b:255971791
TEST=Build Google Rex.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 03:01:54 +00:00
Martin Roth
90e4f3dd4c util/cbmem: Update formatting for cbmem -l command
Some of the cbmem area names have gotten longer, and were making the
output of cbmem -l look bad, so expand the name area to 20 characters.

Instead of printing a blank area if the name isn't recognized, call it
unknown.

Change the method of printing the title to match the way the actual text
of the table is printed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 01:07:37 +00:00
Angel Pons
12459160d1 soc/intel/**/fast_spi.c: Drop spurious whitespace
Drop 1 (one) newline and 1 (one) space.

Change-Id: I1972d173f99507dd167bd86c73d99434b04701ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69167
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 01:06:38 +00:00
Martin Roth
f2798f752e commonlib: Fix AMD MP2 BUFFER id
Cut and paste error.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Iae6213ac99bc5c64fd5dcd681c7922eafa011fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69165
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:06:12 +00:00
Kevin Chiu
c19a2f09e1 mb/google/brya/var/lisbon: update USB topology in devicetree
update USB topology per the schematic design

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I2976028d3efa20e25deedb34ffb8b3bab43b5f5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-04 01:05:46 +00:00
Tim Crawford
fa5a475206 mb/system76/adl-p: Add Darter Pro 8
The Darter Pro 8 (darp8) is an Alder Lake-P board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD (with MZVL2500HCJQ)
- M.2 SATA SSD (with WDS100T2B0B)
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.1
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined header + mic 3.5mm audio
- S0ix suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 5.18.5
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Detection of devices in TBT slot on boot

Change-Id: Icc84d6cc3aec7149d9b538305288bbe2b56d53e4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 01:04:58 +00:00
Elyes Haouas
1bd23e3922 mainboard: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: Iccb7f28a2c913ae0983bf224a03610d7fdd13c68
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:02:44 +00:00
Elyes Haouas
d1bf9bfe06 soc/intel/skylake: Clean up includes
Change-Id: I505ef39487b2677993423e5952b54e008e24fcc5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 01:01:53 +00:00
Liju-Clr Chen
d222d1add8 Revert "soc/mediatek/mt8188: Allow CPUfreq hardware to access MCUPM registers"
This reverts commit a8172c329f.

In the aforementioned patch, we allowed MCUPM to access secure
registers and set the domain to DOMAIN_2.

Additional attribute settings are also required when a hardware is
set to a specific domain. Otherwise, there would be violation between
hardware. Since MT8188 is in bring-up stage, we simply enable access
register permission for the DOMAIN_0 by default. So remove the wrong
setting for MCUPM, SCP and SSPM.

We will complete DEVAPC setting when the settings are confirmed.

Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-04 01:00:52 +00:00
Martin Roth
bcb610a559 soc/amd: Specify memory types supported by each chip
This change disables support for memory types not used by each of the
chips.  This will in turn remove the files for those memory types from
the platform builds.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:00:27 +00:00
Martin Roth
b6877e401a soc/amd/common: Only call into enabled memory types
Don't call into disabled memory type code, it won't work.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:00:22 +00:00
Elyes Haouas
f2503fce3f nb/intel/pineview: Specify supported memory types
Change-Id: If40010abdf180e40c2aab7a991c7382dc5b2d7d5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 00:57:00 +00:00
Elyes Haouas
649c8cb81c nb/intel/x4x: Specify supported memory types
Change-Id: I07c24ece29616fa008da0935c3fe71e35f16ed2d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 00:56:44 +00:00
Elyes Haouas
9ee9cd30a2 nb/intel/sandybridge: Specify supported memory types
Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 00:56:13 +00:00
Elyes Haouas
49af63b8a1 nb/intel/gm45: Specify supported memory types
Change-Id: I3a3a45a1a36ea6ad0b8fb2d3ee78add0b38460ac
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 00:55:12 +00:00
Elyes Haouas
e845753ce4 nb/intel/i945: Specify supported memory type
Change-Id: I3cc2a9786dfb1f8fb1ec8e78bde7c46c07f8da48
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04 00:54:52 +00:00
Martin Roth
a666af7b01 device/dram: Add kconfig options for memory types
Currently, we're building support for all memory types into every board,
and letting the linker remove anything that isn't needed. This is okay,
but it'd be nice to be able to build in just what's actually needed.

This change adds options to specify both what is used and what is not.
By doing it that way, the default values don't change, but platforms can
start removing support for memory types that are not needed.  When all
platforms (SoCs, CPUs and/or Northbridge chips) specify what memory
types they support, the defaults on the options to use a particular
memory type can be set to no, and the options not to use a memory type
can be removed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I07c98a702e0d67c5ad7bd9b8a4ff24c9288ab569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04 00:54:25 +00:00
Michael Niewöhner
8cfd3f88d3 checkpatch: add Co-authored-by to signature list
Co-authored-by is commonly used for changes that have more than one
author. Add it to the list to make Jenkins happy.

Change-Id: I7f66824febe3be756c64ebf44c94bc653a66f1e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-11-04 00:36:11 +00:00
Felix Held
b95d427f7a Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"
This reverts commit 1bb9786da3 ("cpu/x86/mp_init.c: Set a bogus
initial lapic_id"), since it breaks MP init on amd/mandolin:

[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #3
[INFO ]  Initializing CPU #1
[INFO ]  Initializing CPU #2
[EMERG]  CPU: missing CPU device structureCPU: vendor AMD device 810f81
[DEBUG]  CPU: family 17, model 18, stepping 01
[DEBUG]  microcode: patch id to apply = 0x08108109
[INFO ]  microcode: being updated to patch id = 0x08108109 succeeded
[INFO ]  CPU #1 initialized
[ERROR]  MP record 3 timeout.
[INFO ]  bsp_do_flight_plan done after 1206 msecs.
[ERROR]  MP initialization failure.
[EMERG]  mp_init_with_smm failed. Halting.

TEST=The board boots again with the revert applied

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69186
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03 23:57:41 +00:00
Arthur Heymans
d1862b4e88 cpu/x86/mp_init.c: Handle failed init_bsp()
Bail out of mp_init if this function fails.

Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 21:38:26 +00:00
Arthur Heymans
1bb9786da3 cpu/x86/mp_init.c: Set a bogus initial lapic_id
This makes it easier to catch errors later if the ap_init code fails to
properly set things up.

Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69108
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-11-03 21:21:57 +00:00
Fred Reitberger
506014f624 soc/amd/glinda/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields, updated per
glinda ppr #57254, rev 1.51

Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:49:48 +00:00
Fred Reitberger
89a987899e soc/amd/morgana/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields, updated per
morgana ppr #57396, rev 1.52

Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:49:22 +00:00
Fred Reitberger
cdac3aeb11 soc/amd/mendocino/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I01dcea783542ecc0a761191907c1273016f854c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:52 +00:00
Fred Reitberger
a9b09547d8 soc/amd/picasso/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:24 +00:00
Fred Reitberger
f5df69d1ae soc/amd/cezanne/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:03 +00:00
Fred Reitberger
31e6298429 soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common
The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:47:38 +00:00
Patrick Georgi
3d0303a57c util/docker/coreboot.org-status: Rewrite parser
The current tool is a shell script that mixes data collection and HTML
generation and is generally a pain to work with. It takes 15 minutes to
run.

The new tool is written in go, collects all data first, then generates
the output HTML from the data and a single template, and finishes in
10 seconds.

The goal in this version is to produce output as similar as possible to
the output of the shell script. Some difference will remain because the
shell script returns some trash data whose reproduction would require
more effort than is worth.

Change-Id: I4fab86d24088e4f9eff434c21ce9caa077f3f9e2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-11-03 13:50:30 +00:00
Elyes Haouas
5318d9c9d1 {device,drivers}: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: I1727bf56b4090d040aab413006dec7aca0587d44
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 13:08:23 +00:00
Elyes Haouas
f743e0c0e4 soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 13:07:39 +00:00
Elyes Haouas
35c3ae3bf4 treewide: Add 'IWYU pragma: export' comment
This pragma says to IWYU (Include What You Use) that the current file
is supposed to provide commented headers.

Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-03 13:05:17 +00:00
Elyes Haouas
109bd3b796 include/acpi/acpi_crat.h: Add missing <stdint.h>
Change-Id: Ic157cd820be204035706f8074dd6dbcb95c0f04f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-03 13:03:21 +00:00
Elyes Haouas
6dc65d9047 ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-11-03 13:01:43 +00:00
Eric Lai
01590227f2 test/lib: Add non-existent DIMMs test case in spd_cache-test
Add non-existent DIMMs test case in spd_cache-test.

BUG=b:213964936
TEST=make unit-tests PASSED

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-03 13:00:15 +00:00
Raymond Chung
29bc20f996 mb/google/brya/gaelin: Configure GPIO settings
Override GPIO pad configuration based on the latest gaelin schematic.

BUG=b:249000573
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=emerge-brask coreboot

Change-Id: I649ac5131393008787cbb403fc64b914de23312b
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-03 12:59:27 +00:00
Tim Crawford
c6529c7c0a soc/intel/alderlake: Hook up GMA ACPI brightness controls
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Tested by adding gfx register on system76/lemp11. Backlight controls
work on Windows 10 and Linux 6.1.

Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03 12:58:26 +00:00
Johnny Lin
8541325f38 mb/ocp/deltalake: Revert OVERRIDE_UART_FOR_CONSOLE
This reverts commit f6efeae66c (mb/ocp/deltalake: Override uart base
address via VPD variable). Both SOL and UART would use 0x2f8,
disabling it can also avoid searching flash VPD during each UART tx.

Change-Id: I453fdddbb883eb956bac708913c17bb581f75b9d
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03 12:57:48 +00:00
EricKY Cheng
4b1945ce58 mb/google/skyrim: Disable SD ASPM
Disable ASPM on SD until b/245550573 is root-caused/fixed.
Logical_lane 1 on winterhold is EMMC device.
Disable ASPM for suspend issue.

BUG=b:249914847, b:245550573
TEST=emerge-skyrim coreboot chromeos-bootimage
     and test on whiterun proto emmc sku with
     suspend_stress_test -c 10

Change-Id: If080cdb517a3f22aa89c8053fb6bba9e931c6f76
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68940
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-03 12:55:53 +00:00
Martin Roth
96edc100c0 tests: Add option for debug symbols & no optimization
To make it easier to build the tests with debug symbols, add a check for
the "GDB_DEBUG" environment variable.  If set, build with -g and -Og to
enable the symbols and disable optimization.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3a644dcccb7e15473413b775da8f70617afaefce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-03 12:55:29 +00:00
Matt DeVillier
2494e9361d drivers/i2c/generic: Tweak error text for missing HID
- drop ERROR prefix since already provided by cbmem log
- make error text more clear about cause of error

BUG=none

Change-Id: I1795aee240a5383b21108c697e930a2e4972a0b4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69062
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-03 02:04:14 +00:00
Angel Pons
6397687940 nb/intel/gm45: Make polling loops more explicit
Replace `while (...);` with `do {} while (...);` so that it's easier to
distinguish polling loops from something else, like function calls. The
`{}` can be understood as "nothing", so that the construct is naturally
read as "do nothing while (...)".

Another reason to prefer this method is that Jenkins does not complain.

Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 02:01:14 +00:00
Hsuan Ting Chen
5faaca09b8 util/eventlog: Correct the capitalization for diagnostics types
Correct the capitalization of ELOG_CROS_DIAG_TYPE_STORAGE_HEALTH from
"Storage Health Info" to "Storage health info", which is already widely
used in depthcharge diagnostics tools.

BUG=b:254405481
TEST=none

Change-Id: Ia6c1df9e8d2ee6f8ae11b962e76b52f3c6663c42
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02 21:41:10 +00:00
Matt DeVillier
22683fabf0 mb/google/skyrim: Use detect vs probed flag for touchscreens
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.

BUG=b:121309055
TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.

Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-02 21:40:49 +00:00
Solomon Alan-Dei
b4e94c8b01 util/cbfstool: fix memory leak in compress.c
free the memory allocated in lz4_compress
function before returning from it.

Reported-by: Coverity (CID:1469433)

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-02 21:40:25 +00:00
Tarun Tuli
bb4b793f4a mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on reset
Leakage from the SPI CS line onto the FPMCU VDD rail was preventing
the FPMCU from fully shutting down on AP reset.

Instead of simply turning off the power rail, now ensure the CS
line is not driven high until late in coreboot.

This ensures it is completely off for the requisite minimum of 200ms
(now measured at approx 1100ms).

BUG=b:245953688
TEST=Confirmed FPMCU is still functional on Kohaku.
Confirmed FpRebootPowerCycle unit test now passes
BRANCH=Hatch

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 21:38:16 +00:00
Tarun Tuli
8924280eb1 mb/google/hatch: Add variant finalize support for hatch devices
Provide a variant_finalize() method and call to be invoked from
mainboard_ops.final

BUG=b:245953688
TEST=Hatch and variants build
BRANCH=Hatch

Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 21:37:36 +00:00
Kevin Chiu
c32d7b42bc mb/google/brya/var/lisbon: Enable SaGv
Enable SaGv support for lisbon

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
     pass RMT verification

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02 21:35:42 +00:00
Kevin Chiu
8dafcc6079 mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk
Support GL9763E as a eMMC boot disk

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02 21:35:22 +00:00
Kevin Chiu
53cfdc8660 mb/google/brya: enable PCIe RP12 for lisbon eMMC support
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02 21:35:01 +00:00
Mars Chen
83e9456676 mb/google/corsola: Add new board 'voltorb'
Add a new kingler follower 'voltorb'.

BUG=b:256737049
TEST=emerge-corsola coreboot

Signed-off-by: Mars Chen <chenxiangrui@huaqin.corp-partner.google.com>
Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-02 21:34:37 +00:00
Michael Niewöhner
3fa42ac553 mb/clevo/l140mu: work around PECI staying high when idle, blocking s0ix
According to Intel doc# 575683 the PECI bus should be low when idle and
is pulled up by clients with strong drive. However, for unknown reasons
the bus stays high on this board, blocking s0ix entry.

The PECI reference schematic in the ASPEED AST2400 BMC datasheet
(actually not related to this board) says that a pull-down is *required*
for the idle state.

This might be just a requirement of this BMC, since this is nowhere
documented in Intel datasheets, schematics or elsewhere. However,
configuring a weak pull-down (20 k) on the PECI pad indeed solves this
problem for now.

Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 21:07:12 +00:00
Michael Niewöhner
8998ab8b02 mb/clevo/l140cu: work around PECI staying high when idle, blocking s0ix
According to Intel doc# 575683 the PECI bus should be low when idle and
is pulled up by clients with strong drive. However, for unknown reasons
the bus stays high on this board, blocking s0ix entry.

The PECI reference schematic in the ASPEED AST2400 BMC datasheet
(actually not related to this board) says that a pull-down is *required*
for the idle state.

This might be just a requirement of this BMC, since this is nowhere
documented in Intel datasheets, schematics or elsewhere. However,
configuring a weak pull-down (20 k) on the PECI pad indeed solves this
problem for now.

Change-Id: Ib5a6b0ad3553c2cf795037d6a1982102bcb04644
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68793
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 21:06:51 +00:00
Michael Niewöhner
0ca534e059 mb/clevo/l140cu: enable S0ix
Enable S0ix for the board, as done in vendor fw.

Change-Id: Ifdf93e1e599e7cc03fc02297eafb49d34b1f6172
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68792
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 21:05:11 +00:00
Michael Niewöhner
a972e238dd soc/intel/common: provide display hook in PEP for ECs
Provide PEP display notification hook for ECs.

Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02 21:04:00 +00:00
Michael Niewöhner
060dc7b26d acpigen: export acpigen_write_field_name
It will be used in a follow-up change.

Change-Id: If89f9569c33949995d3b45a5f871ff2cb84a6610
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-02 21:03:40 +00:00
Martin Roth
b621d9bef3 util/release/build-release: Use bash arrays for params
Instead of using unquoted strings for the command line parameters,
use arrays which naturally split into separate elements inside the
quotes.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1c96d5072b98523af4e407cfff8f4d1d28ec3297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-02 20:51:47 +00:00
Michael Niewöhner
df8677c992 device/mmio: add clr/setbitsXp macros
Add clr/setbits*p macros as pendant to read/write*p.

Change-Id: I5b10ccab97c3a372051050b28ada854baec91d18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68790
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 18:44:05 +00:00
Michael Niewöhner
9c2d8135fe soc/intel/common/acpi: provide PTS/WAK hooks for ECs
Provide PTS/WAK hooks for ECs like we do for mainboards.

Change-Id: I687254362a896baa590959bd01ae49579ec12c94
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 18:43:38 +00:00
Arthur Heymans
1a52a4fe51 payloads/grub: Work around entry point issue
With -Os grub-mkimage does not create an elf with the correct entry
point because some parts of the elf images are placed in
.text.unlikely. The linker does not know where to place that and
places it below .text, hence messing up the entry point. To avoid this
use the compiler flag -fno-reorder-functions.

Change-Id: Ic4a12f45d30b781870faa38575e8b2c10e0a42e8
Resolves: https://ticket.coreboot.org/issues/343
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64235
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Hackware <human@hackware.cl>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 18:31:23 +00:00
Kevin Chiu
512b1a7724 mb/google/brya/var/gladios: use RPL FSP headers
To support an RPL SKU on gladios, gladios must use the FSP for RPL.

Select SOC_INTEL_RAPTORLAKE for gladios so that it will use the RPL
FSP headers for gladios.

BUG=b:239513596
BRANCH=None
TEST=FW_NAME=gladios emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ic30f7fe30eb0a3151cdf46fff609819056b2fbfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-02 16:25:34 +00:00
Amanda Huang
001b059322 mb/google/skyrim: Select GOOGLE_SMBIOS_MAINBOARD_VERSION
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying
board revision from the EC.

BUG=b:256723358
TEST=1. emerge-skyrim coreboot chromeos-bootimage
     2. flash the image to the device and check board rev
        by using command `dmidecode -t 1 | grep Version`

Change-Id: I97295083dbca1c285ef7359d86abac7315c654c9
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69087
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02 15:01:43 +00:00
zhaojohn
80a3b96593 mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
Rex board only uses TBT PCIe root ports 0 and 2. This change disables
rp1 and rp3 root ports.

BUG=b:254207628
TEST=Booted to OS and verified rp1 and rp3 root ports were disabled.

Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-02 06:50:12 +00:00
Evgeny Zinoviev
b5d402e388 mb/{lenovo,packardbell}: Enable MEI device
Enable the MEI in device trees of some Ibex Peak, Cougar Point and
Panther Point boards where they have been disabled.

Change-Id: I4327d19d3ed1a93a6466057f6eceed49ab9441c5
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2022-11-01 15:48:56 +00:00
Raihow Shi
2dfa65368e mb/google/brask/variants/moli: remove fan setting
Disable Active Policy and remove fan setting to let ec control fan
indenpendently.

BUG=b:236294162
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ie8851800d30ebf4d948d6eaadda2387c8afe52d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-01 15:23:54 +00:00
Jonathan Zhang
9f9bfdd5a1 drivers/ipmi/ipmi_kcs_ops.c: accommodate BMC revision being 0
BMC major/minor revision may be 0. Get the value directly from
BMC without checking to accommodate such situation.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I0e08c6d02de8f6efceb69b6d6cebad9d61cfd20e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68685
Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-31 03:32:09 +00:00
Jonathan Zhang
cb3eaf680a drivers/ipmi/ipmi_ops.h: add __packed to sel_rec structs
Align with BMC on the SEL record format.

Change-Id: Icfcef684caa253663503eadffc819ad2ab65550f
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68757
Reviewed-by: Shuming Chu (Shuming) <s1218944@gmail.com>
Reviewed-by: TangYiwei
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-31 03:27:52 +00:00
Martin Roth
9231f0b92a soc: Add SPDX license headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-31 03:27:13 +00:00
Matt DeVillier
f90ff456fc mb/google/skyrim: Implement touchscreen power sequencing
Assuming variants have a touchscreen by default, set the enable GPIO
high and hold in reset during romstage, then release reset in ramstage.
This will allow the touchscreen to make use of the runtime I2C detect
feature (enabled in a subsequent commit) so that an ACPI device entry
is created only for the touchscreen actually present.

Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.

BUG=b:121309055
TEST=build/boot skyrim with rest of patch series

Change-Id: Ic4d7ac8f951bb94da2216a24dc85a96275c9d449
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-30 17:00:45 +00:00
Patrick Georgi
aa8796d3fd util/kconfig: Uprev to Linux 6.0's kconfig
Only minor changes in kconfig this time that shouldn't
affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I77cc8517128a973c345c41da2c483b78eeaee89f
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:47:21 +00:00
Patrick Georgi
1215cc7632 util/kconfig: Uprev to Linux 5.19's kconfig
Only minor changes in kconfig this time that shouldn't
affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: Icc83c929dd1ea2d98e1a789560ce26886ded1f12
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:50 +00:00
Patrick Georgi
5526be21ea util/kconfig: Uprev to Linux 5.18's kconfig
Only minor changes in kconfig this time that shouldn't affect us.

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I46f43182ce9ec1b6a5923cb77dcd6e335e44c87a
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:23 +00:00
Patrick Georgi
7eb03cb657 util/kconfig: Uprev to Linux 5.17's kconfig
Another upstream refactoring, another local patch gone!

TEST=`util/abuild/abuild -C` output (build.h and build.conf) remains
the same

Change-Id: I0f99dcbd8ecc7256551f0a6e2c83c060cb1999b6
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:46:03 +00:00
Patrick Georgi
4c9b9e9709 util/kconfig: Uprev to Linux 5.16's kconfig
Linux 5.16 saw a significant rewrite in the boolean handling which
reduces our change set. On the other hand, it's all new code.

Comparing the config.build and config.h files generated by
`util/abuild/abuild -C`, only a few lines of comment in the header
changed.

Change-Id: I52984e15a48236ddf228707aec85e90f71aa4382
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-30 08:45:52 +00:00
Martin Roth
14cedd97a5 MAINTAINERS: Make Misc Fixes
- X86 architecture is maintained, so mark it as such.
- Legacy AMD chips are supported for odd fixes.
- Remove maintainers whose emails are bouncing.
- Remove maintainers who don't have +2 rights in gerrit.
- According to the instructions, we should use S: Orphan, not Orphaned.
- Update incorrect email addresses.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30 01:48:45 +00:00
Martin Roth
b10578a404 MAINTAINERS: Update EC section
- Presumably all of the ec/google subdirectory is maintained
- Add list of Orphan ECs

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia93e8da9898903ae92873a07fb0af2a2aa76e8b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30 01:48:20 +00:00
Martin Roth
dddc808069 MAINTAINERS: Update mainboards
- AMD reference boards are maintained at least for odd fixes.
- Google panther has become a variant of Beltino, so remove it.
- Remove people whose email addresses are bouncing email.
- Remove people who responded to my email about being a maintainer and
asked to be removed.
- Alphabetize list

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic6ecaae77df2f2edaf724160bce04c038cbd115e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30 01:47:45 +00:00
Martin Roth
009f7f1b2a MAINTAINERS: Add orphaned mainboards
The mainboards are broken out into individual entries in hopes that it
will be easier for someone to claim ownership than if they were lumped
into a single "Orphaned Mainboards" group.

The theory behind this is that a single mainboard is really the easiest
piece of coreboot to maintain.  Hopefully some less-experienced people
will be interested in stepping up to take over ownership of a mainboard.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9542b3a7cd87fa8656bc0982c08061e9d0513745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-30 01:29:14 +00:00
Nikolai Vyssotski
d691bf2d5f mainboard/amd/chausie: Don't use APCB_FT6_Updatable
This APCB binary is not used for coreboot builds. Coreboot does not
support RW APCB.

Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29 22:52:03 +00:00
Martin Roth
a523f1d66f Docs/releases: Update release checklist document
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9a79cf92620755e19266faaf593dc2657acdb16f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29 22:51:06 +00:00
Martin Roth
222f1272ba soc/amd/common: Initialize STB Spill-to-DRAM
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I547671d2bcfe011566466665b14e151b8ec05430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29 22:50:26 +00:00
Martin Roth
7bcfa920c1 commonlib...cbmem_id.h: Add AMD STB buffer IDs for CBMEM
- CBMEM_ID_AMD_STB Main Spill-to-DRAM buffer. 2 to 16MiB.
- CBMEM_ID_AMD_MP2 Debug buffer. 128KiB

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I27157ad65df992bcdd0e0d15a6d01b96e24067c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-29 22:49:58 +00:00
Felix Held
396fb3db74 soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device
Don't set bit 2 in _STA in order for Windows not to show a warning about
an unknown device in the device manager for this device. Since the _STA
object just returns a constant, a name definition can be used instead of
a method definition.

TEST=The unknown device with device instance path ACPI\AAHB0000\0
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.

Just shutting down and then booting it again won't clear some internal
state in Windows, so a reboot is needed instead for the change to become
visible.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29 22:49:33 +00:00
Solomon Alan-Dei
a6e60f043b util/lint: fall back to regular grep in kconfig_lint
Automatically fall back to using regular grep if working outside a git
repository and the option to use regular grep is not specified

Signed-off-by: Solomon Alan-Dei <alandei.solomon@gmail.com>
Change-Id: I0cdecf01a0e74c30947c4fe7e7c7d9457a5165a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-29 15:43:18 +00:00
Sean Rhodes
7c09e546af mb/starlabs/*: Change the local version to Kconfig
Replace the string with a Kconfig option

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib11ddd04c44f47b94f4fc9eaed278d554d581b0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29 15:34:46 +00:00
Werner Zeh
833bb448c5 mb/siemens/mc_ehl: Remove spd.bin from CBFS
The SPD data for DRAM init has moved into the hwinfo data structure and
is therefore not used from spd.bin anymore. spd.bin will not receive any
updates, changes will only be done in hwinfo. There is no reason to keep
spd.bin around so remove it for both variants.

Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-29 15:34:01 +00:00
Subrata Banik
4ed30cae08 soc/intel/meteorlake: Move P2SB PCI resource into P2SB device
This patch ensures the P2SB PCI device resource is getting reserved
so that the resource allocator is not assigning this resource to any
other PCI device during the PCI enumeration.

BUG=b:254207628
TEST=Able to ensure on the Google/Rex device, the PCI enumeration
is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3.
Instead the 0xE000_0000 address is being assigned to the P2SB
PCI device.

Without this patch:
[SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align
            20 gran 20 limit ec1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e0000000 size c200000 align 12 gran
             12 limit ec1fffff flags 40000200 index 10

With this patch:
[SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align
            20 gran 20 limit ed1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e1000000 size c200000 align 12 gran
             12 limit ed1fffff flags 40000200 index 10
......
[DEBUG]     PCI: 00:1f.1
[SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align
            0 gran 0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-29 08:33:26 +00:00
Shaik Shahina
14dad2670e soc/intel/common: Fix potential NULL pointer dereference
BUG=NONE
TEST=Boot to OS on Nivviks

Change-Id: I154011963e945b54dfca07f884e473d44dc4e813
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68903
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-29 02:43:41 +00:00
AlanKY Lee
bf2f6e2729 mb/google/brya/var/skolas: Adjust I2C3 CLK to meet 400 kHz
Fine tune I2C3 clock frequency under the 400 kHz. From 402.7 kHz to
382.9 kHz.

BUG=b:255505160
BRANCH=firmware-brya-14505.B
TEST=FW_NAME="skolas" emerge-brya coreboot chromeos-bootimage
     measure by scope with skolas

Signed-off-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Change-Id: Ib6c3f895751387256378964ec76be45a4fcbba4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-29 02:42:43 +00:00
Jakub Czapiga
1799290ea2 acpigen: Always inline helper functions
Acpigen inline helper functions are causing problems while compiling
coreboot with function instrumentation. Sometimes functions are not
inlined and are causing linking errors. Forcing inlining fixes problems
like that, as these functions would normally be inlined anyway.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ibf747573940fe5e76199f327f4e5bc32b4f8c470
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-29 02:42:08 +00:00
Matt DeVillier
0923c62448 util/chromeos/extract_blobs: try using RW_MAIN_A region first
Since the RW firmware may contain newer/additional blobs than the
RO COREBOOT region, try using it first, then fall back to
COREBOOT and eventually BOOT_STUB if necessary.

TEST=extract blobs from dedede and brya firmware images

Change-Id: Ia01b37f8c410685de8a17ea4105ca671931a47c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29 02:39:39 +00:00
Martin Roth
86284c231f mb/amd/birman: Update Birman to work with Morgana or Glinda
Birman should work with either Morgana or Glinda SoCs, so configure the
mainboard to allow building with either.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I56206cd9ad5db99c00b734430b250e04ea9e0609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29 02:38:50 +00:00
Martin Roth
9b6018c4a6 soc/amd/glinda: Don't add amdfw.rom to cbfs in SOC Makefile
CB:66943 - commit 8d66fb1a70 (soc/amd: Add amdfw.rom in coreboot.pre)
changed the build flow for the amd firmware binary after glinda was
branched from morgana.  Update glinda to match the other SoCs.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-29 02:38:34 +00:00
Martin Roth
530b111c42 soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:37:24 +00:00
Martin Roth
300338fccf soc/amd/mendocino: Add code for printing STB to boot log
This adds the mendocino specific code for printing the STB data to the
boot log.  It still needs to be enabled in the mainboard to be used.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:36:22 +00:00
Martin Roth
7e3c1ced40 soc/amd/common: Add code to print AMD STB to boot log
This allows platforms that support AMD's STB (Smart Trace Buffer) to
print the buffer at various points in the boot process.

The STB is roughly a hardware assisted postcode that captures the
time stamp of when the postcode was added to the buffer.  Reading
from the STB clears the data.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:36:02 +00:00
EricKY Cheng
f7a09278b6 soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
Expand extra 5 DPTC thermal related profiles for
Dynamic Thermal Table Switching support.

BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28 21:30:54 +00:00
Arthur Heymans
6e86f77cda soc/intel/xeon_sp: Remove unused madt setup function
Change-Id: I248974c5a88768ee12f63fa77f3fa67a72ea510e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-28 21:30:10 +00:00
Arthur Heymans
48c825ebd1 cpu/x86/mp_init.c: Use linked list data structures
There is no need to keep track of device structures separately.

Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-28 21:28:18 +00:00
EricKY Cheng
49d014f7a0 mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting
Update touchscreen setting.
ELAN900C is the I2C over hid device with slave address 0x10.
MELF0410 is the pure I2C device with slave address 0x34.
The LCD team verification result is on b/251378772 comment#11.

BUG=b:251378772
TEST=Build/boot ChromeOS on winterhold, ensure touchscreen is
functional.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I568346d2abc39d9427e49c3b21f38db0184b8b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28 21:10:22 +00:00
EricKY Cheng
f684530a7f mb/google/skyrim/var/winterhold: Enable DPTC support
Enable DPTC support for Winterhold

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I97c2d3ee29687cd8a9c459e90a45cef05ac4436b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28 20:22:36 +00:00
Fred Reitberger
f78e844b55 soc/amd/cezanne/Kconfig: Enable APOB_HASH
Enable the APOB_HASH feature. This improves boot times by ~9.5ms.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9261d101eb23465208affbf815385d3f1bdbcd69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-28 19:56:58 +00:00
Elyes Haouas
d6317e738e mb/getac/p470: Use 'enum cb_err'
Change-Id: I9650fc672a94343472b44037f8a664d7d15aaf15
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28 17:29:36 +00:00
Elyes Haouas
1733983d55 mb/getac/p470: Remove unused 'ec_oem_write()'
Change-Id: Ia955d8736f9b1835ad33ce43dfbbcd9b6a0a9db4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28 17:29:16 +00:00
Elyes Haouas
15ad9dd1b7 mb/getac/p470: Remove unused 'send_ec_oem_data_nowait()'
Change-Id: If68629f22803ebd61cd00b76b9e61822178325f9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-10-28 17:29:10 +00:00
Michael Niewöhner
8eb7b35010 lint/checkpatch: consider leading + in the line length limit check
The line length limit in coreboot's coding style guidelines applies to
the final file, while checkpatch currently checks the patch line length.
Since patches´ lines start with a `+` (only added content is checked),
the line length being checked is one character longer than the actual
content.

Increase max_line_length by 1 to take this into account.

Change-Id: I8da45bb0d5fbe7d0e12c8b181cf01e5685186bf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-28 15:57:06 +00:00
EricKY Cheng
8bed7ff2d9 mb/google/skyrim/var/winterhold:Generate RAM IDs for new memory parts
Update H58G56BK7BX068 and H58G66BK7BX067 support

BRANCH=None
BUG=b:243337816
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I2aa6169c6e824318e738878f8cd19e76fcfd5713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-28 12:27:01 +00:00
Raihow Shi
d825e479bd mb/google/brask/variants/moli: keep SAGV disable
Since there is not too many low power requirement for moli and it is doing FSI firmware qual, so it is not critical to enable the SAGV and keep SAGV disable.

BUG=b:254600066
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I4115b35fed35b74a307b08f7a10ebced2309297f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68898
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-28 12:26:44 +00:00
EricKY Cheng
3a15fd1621 spd/lp5: Re-generate the SPD data
Re-generate Hynix H58G66BK7BX067 and H58G56BK7BX068 data
with current spd_tools.

BUG=b:243337816
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I19ae0477dea64f2cdd37b6aa51eadd6957c54059
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-28 12:06:29 +00:00
Sridhar Siricilla
6552b99fc9 cpu/intel/common: Fix typecasting issue
The patch fixes the typecasting issue, that is conversion from 'int' to
'unsigned long long int'. This changes value from '0x8000 0000' to
'0xFFFF FFFF 8000 0000'.

During unit testing, the argument is getting changed to an unexpected
number which is resulting to an exception when IA32_HWP_REQUEST MSR is
updated. In this update, the MSR's reserved bits are getting updated, so
this causes exception.

TEST= Verified the code on the Gimble.
No exception is seen after the fix.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I35d382c792b9df260381b7696f3bbff43d6c4dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-28 01:38:21 +00:00
Martin Roth
75a4a6a40e vc/amd/fsp: Add Glinda directory
Copied from Morgana - Needs to be updated.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-27 22:22:16 +00:00
Paz Zcharya
64b502fab5 mb/google/brya: Update Crota's ELAN touchscreen delay to 150 ms
ELAN updated the datasheet of component 4599 (qualification 10511)
to version 0.6 (upload date: Oct 24, 2022), decreasing i2c delay
during power-on sequence from 300 ms to 150 ms.

BUG=b:232893949
TEST=Manually checked touchscreen works after reboot and suspend
(on kernel v5.10)

Signed-off-by: Paz Zcharya <pazz@google.com>
Change-Id: I17e1f7d419637f6dff4049484ce1836ad98017ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68868
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-27 21:01:04 +00:00
Kevin Chiu
8f585cef9b mb/google/brya/var/lisbon: use i2c1 for TPM for lisbon
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
lisbon variant.

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I16be50258db2111d22f7465458873e92f44c7dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27 15:50:32 +00:00
Kevin Chiu
e63049fc15 mb/google/brya: Update devicetree setting for lisbon
update devicetree setting per the schematic

BUG=b:246657849
TEST=emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I4268a5b43690a22bb703337fed84b83c45da4ad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27 15:48:01 +00:00
Kevin Chiu
1be4bbc57a mb/google/brask/var/lisbon: Update gpio table
Based on latest schematic to update the gpio table.

BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I531f9ca9f6902d3318e99dadb58a811a4686a6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-27 15:47:19 +00:00
Zheng Bao
acd3788bb8 mb/google/skyrim: Expand cbmem console buffer
Expand the size of cbmem console buffer from default value 0x20000 to
0x80000. Verified by running "cbmem -l" in Chromium OS shell.

localhost ~ # cbmem -l
CBMEM table of contents:
    NAME          ID           START      LENGTH
 0. FSP MEMORY  46535052  b97fe000   01000000
 1. CONSOLE     434f4e53  b977e000   00080000
 2. RW MCACHE   574d5346  b977d000   00000360
 3. RO MCACHE   524d5346  b977c000   00000f20
 4. FMAP        464d4150  b977b000   0000047c
 5. TIME STAMP  54494d45  b977a000   00000910
 6. VBOOT WORK  78007343  b9766000   00014000
 7. RAMSTAGE    9a357a9e  b9700000   00066000
 8. ACPI BERT   42455254  b96fc000   00004000
 9. CHROMEOS NVS        434e5653  b96fb000   00000f00
10. REFCODE     04efc0de  b96ab000   00050000
11. MEM INFO    494d454d  b96aa000   00000768
12. RAMOOPS     05430095  b95aa000   00100000
13. COREBOOT    43425442  b95a2000   00008000
14. ACPI        41435049  b957e000   00024000
15. TPM2 TCGLOG 54504d32  b956e000   00010000
16. SMBIOS      534d4254  b9566000   00008000
17. FSP RUNTIME 52505346  ba7febe0   00000004
18. POWER STATE 50535454  ba7feb80   00000060
19. ROMSTAGE    47545352  ba7feb60   00000004
20. EARLY DRAM USAGE    4544524d  ba7feb40   00000008
21. ACPI GNVS   474e5653  ba7feb20   00000020

BUG=246268888
TEST=Skyrim

Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-27 15:46:59 +00:00
Elyes Haouas
1bb4f84202 console/post.c: Sort includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I3faa1baf41ff8f0447d18b131a9c9c225e9fc8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-27 15:46:39 +00:00
Jonathan Zhang
3b1eac5c04 cpu/x86/mp_init: adjust timeout for final SIPI
Adjust timeout for final SIPI to satisfy some to-be-launched
server processors.

Add a spew print to display how long it takes for the APs
to be ready. This is intended to facilitate only troubleshooting
and trend analysis.

Change-Id: Id958f18bdcb34d76df8aa443161123252524328e
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68262
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-27 14:15:11 +00:00
Yu-Ping Wu
b9a9dcd8d6 mb/lenovo/haswell: Enable VBOOT_VBNV_FLASH
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for Haswell.

Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for
CPU_INTEL_HASWELL (see [2]). However, there seems to be no
particular reason on those platforms. Flashconsole works on Broadwell,
at least, and it writes to flash as early as bootblock. Therefore,
remove BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES, so that VBOOT_VBNV_FLASH
can be enabled.

[1] https://issuetracker.google.com/issues/235293589
[2] commit 6c2568f4f5 (CB:45740)
    drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config

BUG=b:235293589
TEST=./util/abuild/abuild -t LENOVO_THINKPAD_T440P -a (with VBOOT)

Change-Id: If1430ffd6115a0bc151cbe0632cda7fc5f6c26a6
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-27 13:39:08 +00:00
Subrata Banik
6526e78967 soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.

Additionally, no performance degradation is observed while running
benchmarks.

Refer to Intel Technical White Paper number:751003 for more details.

BUG=b:211770003
TEST=Able to boot to ChromeOS with all cores are enabled.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-10-27 08:50:57 +00:00
Arthur Heymans
2f5025efed Revert "soc/intel/systemagent.c: Fix memory type reporting"
This reverts commit 9c2f3cc9d9.

This broke the smihandler for no clear reason on some platforms.

Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-27 08:41:26 +00:00
Jan Samek
1ed0908282 mb/siemens/mc_apl2: Enable early POST through NC_FPGA
Enable early POST code output for this mainboard, using
the NC FPGA device on PCIe.

This requires the parent PCI bridge to be initialized early.

BUG=none
TEST=boot on siemens/mc_apl2 and observe whether the POST
codes coming from before FSP-M init are visible

Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-27 08:41:16 +00:00
Raymond Chung
40d3409dab mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
The brask DDR4 is set to interleave, due to the limited number of
gaelin PCB layers and the traces need to be smooth,
we will use non-interleave for gaelin DDR4.

BUG=b:255399229, b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and pass MRC memory training

Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-10-27 08:41:00 +00:00
Jakub Czapiga
7ec4671f81 Update vboot submodule to upstream main
Updating from commit id b827ddb9:
2022-09-01 06:37:33 +0000 - (tests: Ensure auxfw sync runs after EC sync)

to commit id 148e5b83:
2022-10-25 09:36:59 +0000 - (Makefile: Fix and simplify the RUNTEST test wrapper)

This brings in 28 new commits:
148e5b83 Makefile: Fix and simplify the RUNTEST test wrapper
a9c47c41 futility/cmd_show: set uninitialized variable
e18a6cda gscvd: presume GBB flags are zero when hashing the RO space contents
0b0aee9c gscvd: refactor discovering GBB in the image
ff1749cb futility: add option to save ro_gscvd section in a blob
84c65cd3 vboot_reference: Check OS/firmware mismatch and report to UMA
9a1be550 cmd_update: avoid variable name aliasing
d0f7fdf6 treewide: Fix copyrights and extra new lines at end of file
0ca75fd1 tpm_lite: Fix copyrights, line endings, extra new lines at end of file
4ca43a34 crossystem: arm: Retry if we fail to read a GPIO
f1a7efc0 futility: updater: Scan patch files for the signer_config manifest
64803227 futility: updater: Support patching GSCVD
2aa69d0c futility: Remove validate_rec_mrc command
0ca7a9e4 firmware: host: futility: Add CBFS metadata hash support
aaeb307f futility: Use ccd update mode for suzyq ti50
aa44b7cf vboot: gbb_flags_common should treat ccd_ti50 like ccd_cr50
ff8bb2d9 futility: Address double free
6a33a0fc treewide: Fix license headers to conform with linter
b2b4f767 DIR_METADATA: Add V2 Test Plans.
5346938c futility gscvd: add option to print out root key hash
5790c0aa gscvd: add support for reading ranges from the image
499e5743 gbb_flags_common.sh: Restore tmpfile cleanup trap
f3f9d2a6 scripts/OWNERS: Fix engeg email chromium -> google
ce620761 tests: Remove --allow-multiple-definition linker option
956c2efb futility: Skip picking apart an x86 kernel if has the EFI stub
9f2e9804 Avoid build failures on recent distros
62cc7885 subprocess: Log subprocess arguments when running
3bd35108 2api: Add a new entry point for only loading and verifying the kernel

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I9a16d6e02cee34140ec375ed6166f47560459140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68540
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-27 04:34:25 +00:00
Meera Ravindranath
9e4488ab06 soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.
c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply
this LTR WA.

BUG=b:252975357
TEST=build and boot nirwen and see no issues in PLT runs

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27 00:34:35 +00:00
Subrata Banik
a00db94270 soc/intel/{adl, cmn}: Allow config to select the OCP workaround
This patch introduces a config option for SoC code to choose
the applicable SoC workaround.

For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE`
to apply UFS OCP timeout disable workaround.

At present ADL SoC only selects so, and in future MTL and others
should check with Intel prior selecting this kconfig.

It's the placeholder to add more workaround in required going forward.

BUG=none
TEST=Able to build and boot Google/Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-27 00:33:42 +00:00
Jason Glenesk
bd12700be8 3rdparty/amd_blobs:Advance submodule pointer
This picks up the following changes:
  4ed38e55 glinda: add placeholder blobs
  6de2d3c2 mendocino: Add all blobs from PI 1.0.0.3

Change-Id: Ic2d024f9e5dcd73abed9123b6a6255fe0c28fd4a
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68870
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-27 00:04:05 +00:00
Felix Held
df14a021d5 mb/google/guybrush,skyrim,zork: rework FCH IRQ mapping table generation
This ports the changes to the way the fch_pic_routing and
fch_apic_routing arrays get populated from Mandolin to Guybrush, Skyrim
and Zork. This is a preparation to move the init_tables implementation
to the common AMD SoC code in a later patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie550238dfa0d4c7cebe849966d40fa0b1984a0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 23:57:04 +00:00
Felix Held
166932c5c0 mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generation
This ports the changes to the way the fch_pic_routing and
fch_apic_routing arrays get populated from Mandolin to Bilby, Birman,
Chausie and Majolica. This is a preparation to move the init_tables
implementation to the common AMD SoC code in a later patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 23:56:53 +00:00
Felix Held
ec69bdcd2f mb/amd/mandolin: handle invalid intr_index values in init_tables
Make sure that the intr_index is valid to avoid out-of-bounds writes to
the fch_pic_routing and fch_apic_routing arrays.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45ab115f3814b212243c4f6cf706daf77b6ff3b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 22:09:39 +00:00
Felix Held
3ad216be1d mb/amd/mandolin: introduce mb_get_fch_irq_mapping
Introduce mb_get_fch_irq_mapping to access the FCH IRQ routing mapping
information and use it in init_tables to get the mapping instead of
directly accessing the array's contents. This is a preparation to move
the init_tables implementation to the common AMD SoC code in a later
patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c39ea9de5ebbf70d2c5a87bfdfe270796548c5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 22:09:27 +00:00
Felix Held
067f703329 mb/amd,google: unify fch_irq_routing struct instance name
Use the same fch_irq_map name in all mainboards using the Picasso,
Cezanne, Mendocino and Morgana instead of using a mainboard-specific
name.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 22:09:07 +00:00
Felix Held
ce934056df mb/google/guybrush,skyrim: add missing string.h include
string.h defines the memset function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I286557d6ad83990bc101eaa930bde04345859c0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 22:08:40 +00:00
Felix Held
711c0e5a54 mb/amd/bilby,mandolin: add missing string.h include
string.h defines the memset function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I242a0382e7020681b6c3a25f75a2a91cbccbe815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26 22:08:24 +00:00
Robert Zieba
b3b27f7dea soc/amd/mendocino: Enable GPP clk req disabling for disabled devices
Enable GPP clk req disabling for disabled PCIe devices. If a clk req
line is enabled for a PCIe device that is not actually present and
enabled then the L1SS could get confused and cause issues with
suspending the SoC.

BUG=b:250009974
TEST=Ran on skyrim proto device, verified that clk reqs are set
appropriately

Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26 22:02:32 +00:00
Robert Zieba
956432cbb7 soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE
Currently the GPP clk req configuration code assumes that the size of
the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that
code to use the `ARRAY_SIZE` macro instead.

BRANCH=guybrush
BUG=b:250009974
TEST=Ran on nipperkin device, verified that clk req settings are
correct.

Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26 22:01:47 +00:00
Robert Zieba
5a040d6662 soc/amd/cezanne: Factor out common GPP clk req code
Factor out the `gpp_dxio_update_clk_req_config` function as it will be
useful for other AMD SoCs.

BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices

Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26 22:01:21 +00:00
Felix Held
bf26485d36 soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIES
Instead of using magic constants for the fch_pic_routing and
fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the
common code headers and use this definition. This also allows to drop
the static assert for the array sizes. In the Stoneyridge mainboard code
the equivalent arrays are named mainboard_picr_data and
mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array
size there.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 17:44:47 +00:00
Felix Held
886c1ffc65 mb/amd,google: move fch_irq_routing struct definition to soc/amd
Define the fch_irq_routing struct once in a common header file instead
of in every mainboard's code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 17:44:33 +00:00
Karthikeyan Ramasubramanian
a7b86c3362 mb/google/skyrim: Enable CBFS Verification
Enable RO verification by GSC and CBFS verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 verstage and PSP verstage.

Change-Id: Idd22a521a913705af0d2aca17acd1aa069a77f29
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 17:20:11 +00:00
Karthikeyan Ramasubramanian
c672a72135 cbfs_verification: Remove dependency on VBOOT_STARTS_BEFORE_BOOTBLOCK
CBFS verification on boards where VBOOT starts before bootblock eg. PSP
verstage has been accommodated by keeping metadata hash outside the
bootblock. Hence the dependency can be removed.

BUG=b:227809919
TEST=Build and boot to OS in skyrim with CBFS verification enabled using
both x86 verstage and PSP verstage.

Change-Id: I0a3254728a51a8ee7d7782afcea15ea06d93da7d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66947
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 17:19:22 +00:00
Karthikeyan Ramasubramanian
26aa7503a7 soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine
Crypto engine prefers the buffer from SRAM. CBFS verification may pass
the mapped address of a CBFS file from SPI flash. This causes PSP crypto
engine to return invalid address. Hence if the buffer is from SRAM, pass
it directly to crypto engine. Else copy into a temporary buffer before
passing it to crypto engine.

BUG=b🅱️227809919
TEST=Build and boot to OS in skyrim with CBFS verification enabled using
both x86 verstage and PSP verstage.

Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 17:19:08 +00:00
Elyes Haouas
69451f17a1 src/drivers: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia40678019b2a54deb246dbfbf33ec37a8c3839e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:38:45 +00:00
Elyes Haouas
04c3b5a016 src/device: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Idd78271f2158bdc29ce9ac8d81f46ad8cbe84c5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:38:11 +00:00
Elyes Haouas
45d3205ba5 cpu/x86: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I01c6651079333686cb0eb68e89e56d7907868124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:37:34 +00:00
Elyes Haouas
deb5645644 cpu/intel: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:27:41 +00:00
Elyes Haouas
6a9ae29c05 src/commonlib: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ieba5a5291209e50dc8b3816efb25bb5b2515fa6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:27:10 +00:00
Elyes Haouas
ae1ca82e87 arch/x86: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:26:31 +00:00
Karthikeyan Ramasubramanian
d1130b7ec0 soc/amd/mendocino: Add GSVCD range
Add region/range of SPI ROM to be verified by Google Security Chip
(GSC).

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:54 +00:00
Karthikeyan Ramasubramanian
0a0e7514bb soc/amd/mendocino: Update build rules for PSP BIOS image
Do not compress PSP BIOS image when CBFS verification is enabled.
Otherwise when a file is added to CBFS, cbfstool is not able to find the
metadata hash anchor magic in the compressed PSP BIOS image.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled for
both x86 and PSP verstage.

Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:45 +00:00
Karthikeyan Ramasubramanian
e30e4f5450 soc/amd/mendocino: Reserve more space for metadata
With CBFS verification enabled, CBFS file header + file name + metadata
consumes more than 64 bytes. Hence reserve additional space aligned to
the next 64 bytes.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Change-Id: I2b7346e2150835443425179048415f3b27d89d89
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 16:00:32 +00:00
Karthikeyan Ramasubramanian
8d66fb1a70 soc/amd: Add amdfw.rom in coreboot.pre
This change ensures that amdfw.rom binary containing metadata hash
anchor is added before any file is added to CBFS. This will allow to
verify all the CBFS files that are not excluded from verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.

Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:10 +00:00
Karthikeyan Ramasubramanian
da5d0251f5 util/cbfstool: Check for metadata hash in verstage
Metadata Hash is usually present inside the first segment of BIOS. On
board where vboot starts in bootblock, it is present in bootblock. On
boards where vboot starts before bootblock, it is present in file
containing verstage. Update cbfstool to check for metadata hash in file
containing verstage besides bootblock.

Add a new CBFS file type for the concerned file and exclude it from CBFS
verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.

Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:58 +00:00
Karthikeyan Ramasubramanian
ab82a9f9b4 soc/amd: Add an optional unsigned section in PSP verstage
To enable RO CBFS verification in AMD platforms with PSP verstage,
metadata hash for RO CBFS is kept as part of verstage. This means any
updates to RO CBFS, before WP is enabled, requires updating the
metadata hash in the verstage. Hence keep the metadata hash outside the
signed range of PSP verstage. This means the metadata hash gets loaded
as part of loading PSP verstage while still being excluded from the
verification of PSP verstage.

This change keeps the metadata hash outside the PSP footer data. This
will help to keep it outside the signed range of PSP verstage & aligned
to 64 bytes.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled with
both x86 and PSP verstage.

Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:10 +00:00
Karthikeyan Ramasubramanian
f19e461f4f lib/metadata_hash: Include metadata_hash in verstage
On boards where vboot starts before bootblock, build metadata_hash in
verstage. This will allow to enable CBFS verification for such
platforms.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 verstage and PSP verstage.

Change-Id: I4269069b66ed66c7b1a47fdef2fd0a8054b2e6a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68134
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:02 +00:00
Karthikeyan Ramasubramanian
7835861f9d util/amdfwtool: Add build rules for amdfwread
Add build rules to build amdfwread tool. Also mark this as a dependency
either while building tools or amdfw.rom.

BUG=None
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:37 +00:00
Karthikeyan Ramasubramanian
8b86f21f45 util/amdfwtool/amdfwread: List AMDFW RO binary entries
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories
and list the entries present in them. Accommodate both recovery A/B
layout and normal layout. This is required to identify the location and
size of each entries in the finally built amdfw.rom. This in turn can be
used to perform any platform specific verification on the relevant
components.

BUG=None
TEST=Build and list the contents of AMDFW binary.
/usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin
Table: FW   Offset     Size
PSPL1: Dir  0x00d97000
+-->PSPL1: 0x48 0x00d98000 0x00001000
    +-->PSPL2: Dir  0x00c30000
        +-->PSPL2: 0x00 0x00c31000 0x00000440
        +-->PSPL2: 0x01 0x00c31500 0x00007580
        +-->PSPL2: 0x02 0x00c38b00 0x00019470
        +-->PSPL2: 0x08 0x00c52000 0x0001f560
        +-->PSPL2: 0x09 0x00c71600 0x00000440
        +-->PSPL2: 0x0b 0x430000041(Soft-fuse)
        +-->PSPL2: 0x0c 0x00c71b00 0x00023100
        +-->PSPL2: 0x12 0x00c94c00 0x00015890
        +-->PSPL2: 0x13 0x00caa500 0x000021c0
        +-->PSPL2: 0x20 0x00cac700 0x00000640
        +-->PSPL2: 0x21 0x00cace00 0x00000030
        +-->PSPL2: 0x22 0x00cad000 0x00001000
        +-->PSPL2: 0x24 0x00cae000 0x00003b60
        +-->PSPL2: 0x28 0x00cb1c00 0x00022890
        +-->PSPL2: 0x2d 0x00cd4500 0x00003100
        +-->PSPL2: 0x30 0x00cd7600 0x0006b550
        +-->PSPL2: 0x3a 0x00d42c00 0x000006d0
        +-->PSPL2: 0x3c 0x00d43300 0x000018c0
        +-->PSPL2: 0x44 0x00d44c00 0x00006610
        +-->PSPL2: 0x45 0x00d4b300 0x00001c70
        +-->PSPL2: 0x50 0x00d4d000 0x00001a00
        +-->PSPL2: 0x51 0x00d4ea00 0x00001020
        +-->PSPL2: 0x52 0x00d4fb00 0x00010180
        +-->PSPL2: 0x55 0x00d5fd00 0x00000600
        +-->PSPL2: 0x5a 0x00d60300 0x00000570
        +-->PSPL2: 0x5c 0x00d60900 0x00000b20
        +-->PSPL2: 0x71 0x00d61500 0x00024710
        +-->PSPL2: 0x73 0x00d85d00 0x00010640
        +-->PSPL2: 0x8d 0x00d96400 0x00000030
        +-->PSPL2: 0x49 0x00d99000 0x00001000
            +-->BIOSL2: Dir  0x00d99000
                +-->BIOSL2: 0x60 0x00d9a000 0x00009924
                +-->BIOSL2: 0x68 0x00da4000 0x00009924
                +-->BIOSL2: 0x61 0x2001000(DRAM-Address)
                +-->BIOSL2: 0x62 0x00dada00 0x00010000
                +-->BIOSL2: 0x63 0x00000000 0x0001e000
                +-->BIOSL2: 0x64 0x00db4200 0x00006310
                +-->BIOSL2: 0x65 0x00dba600 0x000004e0
                +-->BIOSL2: 0x64 0x00dbab00 0x00006180
                +-->BIOSL2: 0x65 0x00dc0d00 0x00000250
                +-->BIOSL2: 0x6b 0x201f000(DRAM-Address)
+-->PSPL1: 0x4a 0x00d98000 0x00001000

Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:18 +00:00
Karthikeyan Ramasubramanian
0b6e63220f util/amdfwtool/amdfwread: Handle recovery A/B layout
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to
handle it.

Also add a generic read_header function to read different header types.

BUG=None
TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to
dump the Softfuse entry.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:04 +00:00
Karthikeyan Ramasubramanian
45257abb79 util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
Optional arguments that involve printing information from the firmware
image is mapped to bit fields with bit 31 set. But instead of just
setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:55:53 +00:00
Karthikeyan Ramasubramanian
852c5dc101 util/amdfwtool/amdfwread: Update relative_offset function
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables

Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 15:55:22 +00:00
Arthur Heymans
e33377250c payloads/LinuxBoot: Fix Linuxboot kernel fetching for v6.x
Change-Id: Ic1d407eab8ec4569e02729afb5c71f39ce174401
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68815
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 14:12:20 +00:00
Arthur Heymans
ea1e36694d coreboot_tables: Drop uart PCI addr
Only edk2 used this to fill in a different struct but even there the
entries go unused, so removing this struct element from coreboot has
no side effects.

Change-Id: Iadd2678c4e01d30471eac43017392d256adda341
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26 14:12:06 +00:00
David Wu
7203aa5c2d mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as kano is using a converged firmware image.

BUG=b:253337338
BRANCH=firmware-brya-14505.B
TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
disable hardware write protect and software write protect,
flash and boot kano in end-of-manufacturing mode to kernel.

Cq-Depend: chrome-internal:5046060, chromium:3967356
Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26 14:11:02 +00:00
Maximilian Brune
401fd381bb mb/prodrive/atlas: Disable S3
The Atlas board has currently the problem that suspending the System
causes the System to freeze. Therefore disable S3, until the cause is
figured out and fixed.

Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 14:10:40 +00:00
Subrata Banik
ea708cd617 mb/google/rex: Move DRIVERS_INTEL_USB4_RETIMER config
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake
SoC to Rex mainboard to maintain the symmetry with previous
generation ChromeOS devices (Brya and Volteer).

BUG=none
TEST=Able to build and boot to Google/Rex with USB4 functionality
remaining intact.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26 14:09:46 +00:00
Arthur Heymans
912a262b7b cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
Pre-sandy bridge hardware is likely affected by the sinkhole
vulnerability. Intel sandy bridge and newer has hardware mitigations
against this attack according to
https://github.com/xoreaxeaxeax/sinkhole.

Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-26 07:46:51 +00:00
Martin Roth
f95a11eff5 soc/amd: Add framework for Glinda SoC
This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.

I believe that there's more that can be made common, but that work will
continue as both platforms are developed.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-25 18:18:37 +00:00
Lawrence Chang
0a5da517c4 soc/intel/alderlake: Add Raptor Lake device IDs
Add system agent ID for RPL QDF# Q271

TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is
gone

Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25 17:35:26 +00:00
Frank Wu
749daf360b mb/google/skyrim/var/frostflow: Update devicetree setting
Update devicetree based on the schematic_20221014.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68482
Reviewed-by: Chao Gui <chaogui@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-10-25 17:20:21 +00:00
Felix Held
6990cb29ab mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard
Move the Raydium touchscreen to the baseboard devicetree. Since only the
liara variant uses a level IRQ as I2C devices are supposed to, all other
board variants still override this to use an edge IRQ which were added
as a workaround to make the touchscreen work on the other devices. Right
now it's unclear to me if that edge IRQ workaround was only needed
temporarily and can now be removed, so I'll keep it as it was for now.
If this turns out to be no longer needed on the other variants, the
overrides can be dropped in the future.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25 17:16:42 +00:00
Martin Roth
771806da49 console: Add an SoC-specific post-code call
Add a post-code call that SoCs can hook to output or save in any way
that is specific to that SoC.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-25 17:15:58 +00:00
Martin Roth
f6fea4fd07 MAINTAINERS: Update instructions
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-25 17:03:05 +00:00
Elyes Haouas
8ed5835a14 soc/intel/common: Clean up includes
Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-25 16:26:51 +00:00
Elyes Haouas
cbbbb6c79d soc/intel/tigerlake: Clean up includes
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-25 16:15:09 +00:00
Matt DeVillier
d7d551523d ec/google/wilco/superio: Fix PS2K under Windows
PS2K device needs to be under PCI0, not LPCB, for Windows to
recognize it. Same change was made to ChromeEC previously.

Test: Boot Win11 on Drallion, verify built-in keyboard functional.

Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25 15:13:54 +00:00
Tim Chu
e27e1c1c63 soc/intel/xeon_sp: Add functions to store/restore uart state in smm
When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware
initialization that may interfere with OS. Here we store the state
before console initialization and restore state before SMM exit.

Tested=On not public yet system, after exiting smm, uart console can
still work well.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-25 15:12:36 +00:00
Tim Chu
5e5335da68 src/drivers/uart: Add definition of FIFO enabled in IIR
Interrupt Identification Register (IIR) is a I/O read-access register.
Add definition of FIFO enabled for this register so that we can check
whether FIFO is enabled or not.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68566
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 15:11:59 +00:00
Sean Rhodes
a52d26f2e5 payloads/edk2: Add the declaration for OBJCOPY
The Shimlayer recipe requires OBJCOPY, so declare it at the top of
the Makefile so this recipe works as intended.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2e04dfe18df6252261836dcdf98f7e8de65287b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-25 15:07:10 +00:00
Werner Zeh
cd906960df soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.

Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.

Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25 15:06:18 +00:00
Werner Zeh
f61070e87c mb/siemens/mc_ehl1: Disable L1 prefetcher
The highly real time driven application executed on mc_ehl1 has shown
that the L1 prefetcher on Elkhart Lake is too aggressive which in the
end leads to an increased number of cache misses. Disabling the L1
prefetcher boosts up the performance (in some cases by more than 10 %)
in this specific use case.

Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25 15:05:35 +00:00
Werner Zeh
d03e896b57 soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
Depending on the real workload that is executed on the system the L1
prefetcher might be too aggressive and will populate the L1 cache ahead
with data that is not really needed. In the end, this will result in a
higher cache miss rate thus slowing down the real application.

This patch provides a devicetree option to disable the L1 prefetcher if
needed. This can be requested on mainboard level if needed.

Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 15:05:18 +00:00
Rex-BC Chen
7fd9b86eae soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so
replace "GPL-2.0-only" with "GPL-2.0-only OR MIT".

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:32:05 +00:00
Bo-Chen Chen
c1345d6d70 mb/google/geralt: Configure firmware display for eDP panel
Add eDP panel power-on sequences and initialize the display in the
ramstage.

eDP panel in MT8188 EVB: "IVO R140NWF5 RH".
Panel spec name: R140NWF5 RH Product Specification

Firmware display eDP panel logs:
configure_display: Starting display initialization
SINK DPCD version: 0x11
SINK SUPPORT SSC!
Extracted contents:
header:          00 ff ff ff ff ff ff 00
serial number:   26 cf 7d 05 00 00 00 00 00 1e
version:         01 04
basic params:    95 1f 11 78 0a
chroma info:     76 90 94 55 54 90 27 21 50 54
established:     00 00 00
standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
extensions:      00
checksum:        fb
Manufacturer: IVO Model 57d Serial Number 0
Made week 0 of 2020
EDID version: 1.4

BUG=b:244208960
TEST=see firmware display using eDP panel in MT8188 EVB.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:31:27 +00:00
Bo-Chen Chen
f09872c5bd soc/mediatek/mt8188: Update mtcmos settings for display and audio
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are
  required.
- For audio, it requires powering on adsp_ao_pwr_con,
  adsp_infra_pwr_con and audio_pwr_con.
- Add new power domain data `ext_buck_iso_bits` for buck isolation
  control.

BUG=b:244208960
TEST=access display registers successfully.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:30:15 +00:00
Bo-Chen Chen
8a604bdbae soc/mediatek/mt8188: Add eDP support for firmware display
MT8188 supports eDP as internal display interface.

BUG=b:244208960
TEST=emerge-geralt coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25 08:29:31 +00:00
Nathan Lu
4ac8598f4b soc/mediatek/mt8188: Add ddp driver to support eDP output
Add DDP (display data path) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DP_INTF0 directly.
Add ddp gclast and output_clamp settings to MT8188 to support
multi-layer display.

BUG=b:244208960
TEST=emerge-geralt coreboot.

Signed-off-by: Nathan Lu <nathan.lu@mediatek.com>
Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:29:03 +00:00
Bo-Chen Chen
511884e7e8 soc/mediatek/mt8188: Rename SPM register
The SPM register at offset 0x0 is often named as poweron_config_set in
previous MediaTek SoCs. To use common driver, we rename it from
poweron_config_en to poweron_config_set.

BUG=none
TEST=emerge-geralt coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:28:11 +00:00
Rex-BC Chen
d641addf38 soc/mediatek: Add support for input 1P mode of dp_intf
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25 08:27:52 +00:00
Bo-Chen Chen
319fce53c8 soc/mediatek: Move DP drivers to common
DP drivers can be shared for both MT8195 and MT8188, so move them to
common folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:27:31 +00:00
Elyes Haouas
193e86b814 mb/clevo/tgl-u: Avoid indirect includes
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-10-24 20:04:15 +00:00
Felix Held
2a09a84f15 mb/google/kahlee: always detect ELAN touchpad
Always detecting the presence of the ELAN touchpad doesn't affect the
functionality, but allows dropping the override for all variants that
have multiple touchpad options.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-24 15:50:46 +00:00
Felix Held
34362d0c0f mb/google/kahlee: use override devicetrees for variants
This helps with deduplicating the identical parts of the variants'
devicetrees.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-24 15:50:39 +00:00
Martin Roth
fed17f968d MAINTAINERS: Add Matt DeVillier to the release team
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f5c10618edb87d2dc12c14187c4620d8675a443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 13:02:39 +00:00
Elyes Haouas
53e3c2414d Update arm-trusted-firmware submodule to upstream master
Updating from commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)

to commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)

This brings in 10 new commits:
61fe7826d Merge "feat(fvp): build delegated attestation in BL31" into integration
cf17f7c45 Merge "chore(rpi3): remove redundant code" into integration
70360382b Merge "docs(maintainers): add NPU driver owners" into integration
60c439435 docs(maintainers): add NPU driver owners
e504ce5fa Merge "fix(versal_net): Enable a78 errata workarounds" into integration
bcc6e4a02 fix(versal_net): Enable a78 errata workarounds
0271eddb0 feat(fvp): build delegated attestation in BL31
6047ab122 Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration
769446a68 fix(versal): enable a72 erratum 859971 and 1319367
2594759d2 chore(rpi3): remove redundant code

Change-Id: Ic32c0889961f529e1762b208ef118a94369c34e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-24 13:01:48 +00:00
Patrick Rudolph
e249b1a313 arch/x86: x86_64 implies SSE2 support
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume
SSE2 is present and enabled when targeting x86_64.

This fixes:
- lzma decompression code is compiled with the -Ofast flag
- 'everything' when compiling with clang.

This mostly affects qemu targets, which did not have this flag selected
yet.

TESTED on qemu.

Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-24 12:16:32 +00:00
Sam McNally
1347571f9b mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBER
For some nissa variants, there are build configurations that need to use
different blobs, but otherwise are identical. Currently, they use the
same choice of board config and configure blob paths appropriately. This
avoids duplication within the Kconfig file, but the resulting firmware
images can be difficult to distinguish, since they report the same
FRID.

Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden
and round-tripped through make oldconfig, allowing customisation of the
reported FRID and other MAINBOARD_PART_NUMBER-derived values with
minimal overhead.

BUG=b:253966060
BRANCH=None
TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully

Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-24 11:58:49 +00:00
Michał Żygowski
b205c5d8c1 util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 09:08:40 +00:00
Martin Roth
94008a81e5 soc/amd/mendocino: Add STB Spill-to-DRAM enum
This is the enum value to initialize the Smart Trace Buffer's
Spill-to-DRAM feature.  More information on how this is used is
available in the STB Linux kernel driver.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-23 14:40:51 +00:00
Elyes Haouas
1e336dd91e scripts/update_submodules: Fix "bad revision" error
Fix "bad revision" error when we run "update_submodules" with no option.
This adds "origin/trunk" branch name for "util/goswid".

Change-Id: Ie84d40fa00c6d0032b93917ad96e60120388eab5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-23 02:39:27 +00:00
Martin Roth
08e7df9d5d configs: Add skyrim config with binaries
We've seen failures because the binaries were not being built into the
image.  In particular, the APCB is modified by the coreboot build
process, so if the APCB isn't built correctly to support the correct
number of SPDs, the build can fail.

The mendocino FSP binaries are not yet pushed, so the build is currently
pointing at the cezanne binaries.  The mendocino FSP will be pushed when
the mendocino chips are released for sale.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31d11c5327416f4339930373c447531ae9f79d28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-22 22:44:09 +00:00
Fred Reitberger
c6d7fca0cc soc/amd/morgana/mca: Update for morgana
Update the MCA bank names for morgana per PPR #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 22:30:09 +00:00
David Wu
44cc1b9cac mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W
based on fw_config.

BUG=b:253542746
TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22 22:28:32 +00:00
Derek Huang
3d2df35c6e mb/google/brya: Enable SaGv for brask variants
SaGv is enabled for all brya variants, so it should be harmless
to enable it for brask variants to save some power.

BUG=254374912
TEST=Build and boot to Chrome OS

Signed-off-by: Derek Huang <derekhuang@google.com>
Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-22 22:27:51 +00:00
Frank Wu
c9043411b3 mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ
The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects.
Therefore, update the gpio.c to be consistent with the configuration.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-22 17:12:32 +00:00
Sean Rhodes
7bbc9a512a payloads/edk2: Disable the CPU Timer Lib unless supported
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp
Counter Frequence. For CPUs that do not support this instruction, EDK2
must include a different library which is the reason why this must be
configured at build time.

If this is enabled, and the CPU doesn't support 0x15, it will fail to
boot. If is not enabled, and the CPU does support 0x15, it will still
boot but without support for the leaf. Consequently, disabled it by
default.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 17:11:25 +00:00
Sean Rhodes
27c8bf0cc9 payloads/edk2: Add the recipes to assemble UniversalPayload
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 16:48:00 +00:00
Arthur Heymans
c37fd87d85 soc/intel/systemagent: Rewrite using new resource API
Working with resources in KB is tedious and the base_k / size_k variable
naming was simply wrong in one case.

Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 16:46:40 +00:00
Arthur Heymans
9c2f3cc9d9 soc/intel/systemagent.c: Fix memory type reporting
TOLUD stands for top of lower usable dram. Memory between cbmem_top and
TOLUD, even if stolen for another device/purpose can still be marked WB
cacheable. This will result in a cleaner MTRR setup.

Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-22 16:45:29 +00:00
Werner Zeh
6537216b7a mb/siemens/mc_ehl: Add FIVR config to devicetree for all variants
Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2
variants in order to provide the real delay value for the VCC supply
rail. This delay is needed to enable proper switching between different
VCC levels based on current system state.

Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 16:42:22 +00:00
Matei Dibu
516eff01e6 arch/x86/include/arch: fix assembly clobber for 64bit
the "x86 PIC code ebx" workaround done previously
by commit 689e31d18b ("Make cpuid functions usable
when compiled with PIC") does not work for x86_64
(the upper dword of rbx is set to 0)

the GCC bug that needed the workaround was fixed
in version 5 (see GCC bug 54232)

Change-Id: Iff1dd72c7423a3b385a000457bcd065cf7ed6b95
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66345
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-22 16:40:42 +00:00
Angel Pons
436f1c471a mb/siemens/mc_apl*: Enable early PCI bridge before FSP-M
Apollo Lake seems to start with PCIe root ports unusable/uninitialized
before FspMemoryInit() is called and FSP-M properly initializes these
root ports.

However, we need the root ports accessible before FspMemoryInit() in
certain cases, such as emitting POST codes through a PCIe device.

For the initialization to happen properly, certain register writes
specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter
3.3.1 have to be done.

BUG=none
TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check
that the POST codes are emitted before FspMemoryInit().

Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 16:39:05 +00:00
V Sowmya
036b16b884 soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control
Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-10-22 16:36:02 +00:00
Elyes Haouas
901566597e nb/intel/i945/raminit: Use 'bool' for do_reset
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:14:35 +00:00
Elyes Haouas
d9dade3cb9 nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:14:11 +00:00
Elyes Haouas
5bbdb0c948 smbios.h: Add High Bandwidth Memory Generation 3
Add HBM3 according to SMBIOS 3.6.0:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

Change-Id: Id8473e8c4b5006b53b5ff9de7825d15595f2a616
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 05:13:27 +00:00
Elyes Haouas
26fc2a40ae nb/intel/i945/raminit: Use 'size_t' for banksize[]
Change-Id: I4fb845bb4145d47aea39d7e5493d854d00e289aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 05:12:22 +00:00
Martin Roth
f690c93f25 vc/amd/fsp: Get rid of last "sabrina" reference
We still had a lingering reference to the old sabrina codename in the
vendorcode directory.  Searching through the code now, the only places
the sabrina codename is seen is in the release notes, as is proper.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41762880b45a85ce7cd4210b8ce623076d874c06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-22 01:59:17 +00:00
Fred Reitberger
81b5631258 soc/amd/*/i2c.h: Make definition more accurate
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL
definitions instead of BIT(x).

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 01:59:00 +00:00
Reka Norman
ec929142c6 mb/google/nissa: Disable SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.

Before:
Total Time: 1,205,840

After:
Total Time: 995,300

BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.

Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 01:53:57 +00:00
Elyes Haouas
73fec24319 mb/lenovo/*/mainboard.c: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I406f21c0c05e6af357e45e718422be94c6fd5408
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-22 01:53:36 +00:00
Matt DeVillier
f0f73bdb1d mb/google/kahlee: Fix audio ACPI inclusion
Not all kahlee variants use the RT5682 audio codec, so split the
baseboard audio ACPI into two parts and only include the asl for
the codec(s) actually needed for a given variant.

TEST=build/boot aleena, liara variants and verify no ACPI present
for RT5682 codec (which is not present on the boards).

Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-22 01:53:11 +00:00
Shaik Shahina
16ae1cf233 vc/intel/fsp: Update ADL N FSP headers from v3301.00 to v3343.04
Update generated FSP headers for Alder Lake N from v3301.00 to v3343.04.

Changes include:
- FspsUpd.h: 1. Add PchFivrVccstIccMaxControl UPD

BUG=b:254374913
BRANCH=None
TEST=Build using "emerge-nissa intel-adlnfsp" and boot Nissa.

Change-Id: I20b13d3dff2951e6ec3aa754c8954989a3b4e176
Signed-off-by: Shaik Shahina <shahina.shaik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68424
Reviewed-by: Reka Norman <rekanorman@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-22 01:52:35 +00:00
Frank Wu
b56a8d0272 mb/google/skyrim: Enable genesyslogic gl9755 for frostflow
Enable DRIVERS_GENESYSLOGIC_GL9755 support for frostflow

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-21 22:06:35 +00:00
Fred Reitberger
460ea9d5d2 soc/amd/*/smi.h: Use BIT() for clarity
Use the BIT() macro for single-bit constants.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I490f0093d55813260fcdb7303a94accfa90e75e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-21 21:42:00 +00:00
Arthur Heymans
1cffc55d35 util/amdfwutil: Fix adding microcode binaries
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 21:40:08 +00:00
Felix Held
3adfeec58f soc/amd/*/uart: cleanup includes
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-21 21:03:33 +00:00
Angel Pons
669a767635 mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2
Built from a mixture of autoport output, other variants, schematics and
expert guesswork. I don't have this board, but the code has been tested
by someone else and boots successfully (first try) with TianoCore. It's
reasonable to assume most things work, as this board is very similar to
the already-supported variants.

Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 19:05:40 +00:00
Martin Roth
66f1a98e7f arch/x86/include: Split msr access into separate file
To allow testing of code that uses msr calls, separate the actual
calls into a separate header file,  This allows the tests to emulate
the msr access without replacing the rest of the msr.h definitions.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 15:01:00 +00:00
Sean Rhodes
88058a26f0 MAINTAINERS: Remove Andrey Petrov from Apollo Lake
Andrey doesn't seem to have interacted with APL or coreboot
2+ years, so remove him and mark Apollo Lake as orphaned.

Add myself for Odd Fixes.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6cb2f2da63dda3cb841786d53f89b583a9df9791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:57:53 +00:00
Elyes Haouas
d0a5688a93 mb/lenovo/t{410,60}/dock.h: Fix header guards
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7b279cf2c69f62b47ef497edd372034f148fff03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:57:32 +00:00
Rex-BC Chen
a6cd1bd6a8 soc/mediatek: Unify PLL function names
For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().

BUG=none
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:57:09 +00:00
Sen Chu
08248c0ce8 mb/google/corsola: Initialize MT6315 for MT8186T
Initialize MT6315 for powering on big cores on MT8186T.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:56:44 +00:00
Sen Chu
122b45be6e soc/mediatek/mt8186: Add support for PMIC MT6315
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:56:32 +00:00
Sen Chu
28dceaec71 soc/mediatek: Move SPMI interface configuration to SoC folder
The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
  fix this.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:53 +00:00
Rex-BC Chen
1543252e5f soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't
need to configure PMIF SPMI IO pins. Add a config to control that.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:53:02 +00:00
Rex-BC Chen
6d449e005c soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option
On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other
MediaTek SoCs support PMIF_SPMI and PMIF_SPI.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:52:42 +00:00
Rex-BC Chen
6ad80f1b81 soc/mediatek/mt8186: Add support for reading CPU ID
MT8186 has two slightly different versions: MT8186G and MT8186T
(turbo version). Add get_cpu_id() to identify different CPUs.

BUG=b:249436110
TEST=cpu id is correct.
BRANCH=corsola

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21 14:52:17 +00:00
Elyes Haouas
e8df32775d mb/lenovo/s230u/mainboard.c: Replace comma with semicolon
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:51:56 +00:00
Elyes Haouas
000490a221 arm64/armv8: Use 'enum cb_err'
Change-Id: Ic4ce44865544c94c39e8582780a7eca7876f5c38
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-21 14:51:27 +00:00
Fred Reitberger
d91f73b1d3 soc/amd/morgana/aoac: Remove to-do after review
Reviewed files and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6772b21110f74a77eef285da3e1f313ec6326cc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:50:15 +00:00
Fred Reitberger
0d98cc4844 soc/amd/morgana/i2c: Remove to-do after review
Reviewed files and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9d058b0f61b4784a1d83289e75705a6415405d0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:48:42 +00:00
Fred Reitberger
164b93bd9c soc/amd/morgana/include/soc/iomap.h: Remove to-do after review
Reviewed file and values match morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8f914432e0f55aa8050728e8cf41a3dee20990e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 14:47:48 +00:00
Jason Nien
29f1580086 mb/google/skyrim/port_descriptors: update DDI for MDN and Chausie
Add two new types for MDN DDI descriptor

BUG=b:228284940
TEST=Normal boot and S0i3 cycles

Signed-off-by: Jason Nien <finaljason@gmail.com>
Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-10-21 14:45:11 +00:00
Elyes Haouas
4c0299fbc8 nb/x4x/dq_dqs.c: Use 'enum cb_err'
Change-Id: I94dd6b1bb81bbc38ac5f89469b3ed7c83ca2a498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:35:26 +00:00
Elyes Haouas
6f9786bbcc nb/intel/x4x/raminit.c: Use 'enum cb_err'
Change-Id: I22d7e724e69b41c9fabdef785276dc428be2b400
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:32:40 +00:00
Matt DeVillier
6c8826de8f soc/intel/apollolake: Skip SMI lockdown on Apollolake
Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks
SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly.

TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional.

Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:31:21 +00:00
Martin Roth
95b5b025a0 util/lint: Fix linting outside of git repos
If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find.  This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:30:42 +00:00
Elyes Haouas
60bdb327c6 nb/intel/i945/rcven.c: Use read32p()
Tested on unsupported mainboard (945g-m4).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1935308cc50abd651b52d6290d66180905c6a521
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68087
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-21 14:30:01 +00:00
Kevin Chiu
52163149b4 mb/google/brya: Create gladios ADL variant
Create the gladios variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:239513596
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_gladios

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I3dc99d97d8e30d9641f56616222dd68e3a0d548d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 23:56:10 +00:00
Fred Reitberger
e1b3864f0e soc/amd/morgana/smi: Update smi definitions for morgana
Update the SMI definitions for morgana per PPR #57396, rev 1.52

Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile
errors.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 21:40:15 +00:00
Martin Roth
d282ae3889 Docs/releases: Finalize relnotes for the 4.18 release
The coreboot 4.18 release has been tagged, so the release notes can
now be finalized.

Updated with known issues.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I77676ddc42488e9635f1e6f995386490dca441c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68467
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-20 20:33:20 +00:00
Elyes Haouas
72c2e11beb nb/intel/i945/i945.h: Drop useless guard
i945.h file is not used to generate asl files.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 19:39:53 +00:00
Martin Roth
568670f94d arch/x86/include: Split CPUID access into separate file
To allow testing of code that uses CPUID calls, separate the actual
calls into a separate header file,  This allows the tests to emulate
the cpuid access without replacing the rest of the cpu.h definitions.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:55:03 +00:00
Martin Roth
9c64c08b18 soc/amd/morgana: Add TODOs for common code to Kconfig
This allows us to see which of the common code blocks have been verified
and which have not.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:31:50 +00:00
Elyes Haouas
1a847a11be nb/intel/i945: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 17:29:48 +00:00
Elyes Haouas
4944609bd0 intel/i945: Use 'bool' for dual_channel and interleaved
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 17:29:15 +00:00
Matt DeVillier
411023af72 drivers/tpm: Move TPM init to end of device init phase
Boards which use an I2C TPM and do not use vboot will not have the
I2C bus initialized/ready at the start of the device init phase.
If TPM init is called before the bus, init will fail with I2C
transfer timeouts and a significantly lengthened boot time.

Resolves: https://ticket.coreboot.org/issues/429

TEST=build/boot google/reef w/o vboot, verify successful TPM init.

Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68550
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 17:22:57 +00:00
Martin Roth
3d242755ef mb/google/(guybrush|skyrim): Use a variable for APCB filename
We use the name of the APCB file repeatedly, so put it into a variable
so that it's easier to update.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I8684db2f7b2d68f0354e37bd8cdfc4f9cab44b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-20 17:19:51 +00:00
Wonkyu Kim
6a342360da mb/google/rex: Skip sending the MBP HOB to save boot time
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40 ms.

Boot time data
Before:
* 955:returning from FspSiliconInit 1,656,985 (274,416)
After:
* 955:returning from FspSiliconInit 1,593,036 (233,286)

BUG=b:252410202
TEST=Verified that boot time is reduced by ~40 msec.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20 17:19:03 +00:00
Wonkyu Kim
e5f6ff88c4 soc/intel/meteorlake: Add support to skip the MBP HOB
This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Porting the feature from commit 2bc54e7c00
("soc/intel/alderlake: Add support to skip the MBP HOB")

TEST=Build and boot to verify that the right value has been passed to
the FSP.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20 17:18:45 +00:00
Felix Held
97e612586a soc/amd/*/uart: commonize UART code and MMIO device driver
Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:47:35 +00:00
Felix Held
8ebdbbc3cb soc/amd: move set_uart_config prototype to common UART header
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:47:11 +00:00
Felix Held
ba35f3582e soc/amd: move all AOAC function prototypes to amdblocks/aoac.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:46:31 +00:00
Felix Held
880364040a soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:48 +00:00
Felix Held
957e232277 soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:17 +00:00
Felix Held
ceab0fbc59 soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cfea274f4c9e908c11429199479aec037a00097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:45:08 +00:00
Felix Held
9fde88973a soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:44:16 +00:00
Felix Held
6101dcf670 soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_info
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:44:09 +00:00
Felix Held
f1a03b1d6d soc/amd/stoneyridge: initialize GPIOs for serial console
Initialize the two GPIOs of the SoC UART if it's used for serial console
to be sure that the I/O mux is configured correctly without having to
rely on the bootblock_mainboard_early_init call to do this. This brings
Stoneyridge more in line with the other AMD SoCs. Since this code will
be factored out to the common AMD SoC code in a follow-up patch, the
function prototype is added to southbridge.h instead of creating a new
uart.h header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:41:53 +00:00
Felix Held
c6e4cc8873 soc/amd/*/uart: add missing soc/iomap.h include
soc/iomap.h provides the UART base address information used in the
uart_info struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:40:59 +00:00
Felix Held
acd98d8772 soc/amd/stoneyridge/uart: add and use uart_info array
Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge
with the other AMD SoCs in order to allow commonization of the AMD SoC
UART code. Since the current Stoneyridge code doesn't provide or use
UART MMIO device operations, only the base addresses of the UART
controllers from this array are used for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:40:45 +00:00
Felix Held
d2ebe16cb4 soc/amd: introduce and use common soc_uart_ctrlr_info struct
The SoC's uart_info structs all use the same anonymous uart_info struct
definition, so create a named struct for this in the common AMD SoC UART
header and use it in the SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:39:24 +00:00
Felix Held
fb8c78b2ec soc/amd/morgana/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib893720911114d61ee6b3fbbf1a2a3594500bcfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:57 +00:00
Felix Held
f3976b67e0 soc/amd/mendocino/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5077681b64dd68351340bd179838a174d8df1701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:48 +00:00
Felix Held
d85f25fbb9 soc/amd/cezanne/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e585370a0de56787340788acfecc7931820566d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20 16:38:19 +00:00
Felix Held
6c6c35f20c soc/amd/picasso/uart: separate data and code
The goal of this is to be able to move most of the code over to the
common AMD blocks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia496a4b29b25d4438ed8fc09bfe6f83e3fb768d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-10-20 16:38:13 +00:00
Shelley Chen
1b07797a7b soc/qualcomm/sc7280: Remove NVMe init
We are required to boot with eMMC enabled in the BIOS to store modem
calibration data.  Thus, it doesn't make sense to enable NVMe at boot
time since we will never boot from NVMe w/o eMMC.  We may as well take
the boot time reduction (~100ms) by eliminating NVMe initialization.

BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after disabling NVMe and make sure that it still boots
     Note that we are able to see a little over 100ms in boot time
     savings with this change.
     Before: 40:device configuration 824,021 (102,701)
     After:  40:device configuration 717,402 (44)

Cq-Depend: chromium:3964185
Change-Id: I94f614ba0369c073617949285c0781aef5c6263f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20 16:34:01 +00:00
Shelley Chen
d164feb726 mb/google/herobrine: Remove NVMe from device tree
We need to boot eMMC for modem calibration, there is not need for BIOS
to initialize NVMe anymore as the kernel will do so.  Removing the pci
device from the device tree as a first step.

BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after removing from the herobrine device tree.

Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-20 16:33:18 +00:00
Frank Wu
6d87ac57e2 mb/google/skyrim/var/frostflow: Update GPIO settings
Configure GPIOs based on GPIO_20221014.xlsx of frostflow.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I02272801c85a7c30d24c834a840e026225956fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 16:25:22 +00:00
Frank Wu
a6065ec328 mb/google/skyrim/var/frostflow: Generate RAM IDs for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
H9JCNNNBK3MLYR-N6E             0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)
H9JCNNNCP3MLYR-N6E             1 (0001)
MT62F2G32D8DR-031 WT:B         2 (0010)
H9JCNNNFA5MLYR-N6E             3 (0011)

BUG=b:250470704, b:247683159
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I34584092c938539c91d65501ebe34b00212b34d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-20 16:24:41 +00:00
Frank Wu
afd2f6ed62 spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E
Add Hynix H9JCNNNFA5MLYR-N6E in the memory_parts.json and re-generate
the SPD.

BUG=b:250470704
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
2022-10-20 16:24:06 +00:00
Sumeet Pawnikar
4dba71fd25 Revert "drivers/intel/dptf: Add multiple fan support under dptf"
This reverts commit 672bd9bee5.

Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.

BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.

Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-10-20 14:54:09 +00:00
Tyler Wang
58a38af117 mb/google/nissa/var/craask: Remove redundant ELAN Touchscreen
Remove redundant touchscreen "ELAN6915".

BUG=b:254328657
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I8f90b071b053858cf720de5ac2a71031fe623d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:53:16 +00:00
Victor Ding
690705529d mb/google/nissa/var/craask: Remove SAR Proximity Sensor
Craask does not have a SAR proximity sensor.

BUG=b:253387689
TEST=Dump ACPI SSDT and verify SX9324 related entries are not present.

Change-Id: Ia0e3eb6dba82594ca27040d6ab0197da6095f510
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68564
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:52:55 +00:00
Martin Roth
5962b8a91b src/vendorcode: Add a README.md file
This README.md file specifies the expectations and agreements implied by
contributing code to the coreboot src/vendorcode directory.

Licenses, structure, formatting and the like are all the responsibility
of the contributors, however as the code is a part of the coreboot
codebase, members of the coreboot community are allowed to modify the
code to the extent deemed necessary.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7e2aedce9383158d03be342cb10ae18d85146ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:52:41 +00:00
Matt DeVillier
1e56b0fe6f mb/google/drallion/hda_verb: add verbs for GPU HDMI audio
Test: cbmem reports verb table loaded for codec #2

Change-Id: I4db044535c95ccd3e81a67bb5e58e6f04ee8d12f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:51:15 +00:00
Matt DeVillier
4afd0915a6 mb/google/drallion: Add default FMAP for non-ChromeOS builds
Test: build/boot google/drallion with non-ChromeOS build, Tianocore
payload. Windows 10, Linux 5.10.x booted successfully

Change-Id: I6358b1d5c71eee065fed96b7bca31e37f30d3a8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:50:52 +00:00
Jonathon Hall
aeb8b3d4d6 purism/librem_cnl: Add Kconfig to enable Mini UART
Librem Mini has a UART (accessible with soldering), which is very
useful for work on coreboot.  It can be used for coreboot/SeaBIOS/Linux
boot logs, or as a general purpose UART.

Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68551
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:50:15 +00:00
Arthur Heymans
f5575315fd mb/prodrive/hermes: Allow using the Intel iGPU as primary
Configure the Intel iGPU as primary video adapter if enabled according
to EEPROM settings. The default is to use the ASPEED BMC as primary
video adapter, which only has a VGA output and the remote KVM output.

For now, use the FSP GOP driver to light up the iGPU. There are several
issues with libgfxinit on the Hermes, probably due to the unusual setup
of the iGPU's display outputs. They are routed to a mezzanine connector
for a piggy-back sub-board, of which there are two models. The Poseidon
piggy-back has two DisplayPort outputs and an HDMI output coming from a
MegaChips LSPCON. The Avalanche piggy-back routes all three DisplayPort
outputs from the iGPU into a FPGA, which acts as a DisplayPort sink.

Note that the FSP GOP only initializes at most 2 iGPU display outputs.
However, all three outputs function properly once OS (Windows, Linux)
graphics drivers take over.

Additionally, update the config file that Prodrive uses to build
coreboot images so that the iGPU can be used as primary.

TEST=Verify that the iGPU's outputs work properly in pre-OS, Windows and
     Linux, on both the Poseidon and Avalanche piggy-backs.

Change-Id: I24d9ebc2055dc246e7f257aa2f3853b22c8af370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62649
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:49:36 +00:00
Subrata Banik
bf71c7292a vc/intel/fsp/mtl: Update header files from 2344_00 to 2364_00
Update header files for FSP for Meteor Lake platform to
version 2364_00, previous version being 2344_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

BUG=b:251733481
TEST=emerge-rex intel-mtlfsp

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:48:52 +00:00
Arthur Heymans
e146fbd60c Kconfig: Allow x86 to compress pre-ram stages if not run XIP
On the intel/glkrvp
compressed:
- romstage: 29659
- verstage: 31303
non compressed:
- romstage: 46244
- verstage: 47012

On qemu (with some additional patch to not run XIP)
compressed:
- romstage: 11203
non compressed:
- romstage: 13924

Even with a small romstage the size improvements are substantial,
which should result in a speedup when loading the stage. On the
up/squared loading romstage is sped up by 9ms.

TESTED: successfully boot the up/squared & google/vilboz.

Change-Id: I6906c8b6df45f2433d92d2ff1d1748cc4926c73a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-20 14:48:05 +00:00
Arthur Heymans
9efb0c0825 arch/x86: Only use .bss from car.ld when running XIP
Some platform run early stages like romstage and verstage from CAR
instead of XIP. This allows to link them like other arch inside the
_program region. This make in place LZ4 decompression possible as it
needs a bit of extra place to extract the code which is now provided by
the .bss.

Tested on up/squared (Intel APL).

Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-10-20 14:43:40 +00:00
Subrata Banik
1915ec1fe7 soc/intel/alderlake: Drop local ufs.asl
This patch drops `ufs.asl` from the local SoC directory.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20 14:40:30 +00:00
Subrata Banik
2e438c9a6b soc/intel/alderlake: Use ufs.asl from common code acpi block
This patch includes UFS ASL entry from common block ACPI code.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20 14:40:18 +00:00
Subrata Banik
29ad9f7640 soc/intel/cmn/block/acpi: Create common ASL entry for UFS
This patch migrates UFS ASL entry from Alder Lake SoC to common
block ACPI code to be able to be utilized across different IA SoCs.

Additionally, migrate to ASL2.0.

BUG=none
TEST=Able to build and boot Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2022-10-20 14:40:00 +00:00
Matt DeVillier
45ad511a8a mb/google/reef: Demote NHLT log messages from error to info
Change-Id: I1c00322d2b22e1fafffd6ebd66f2df14bcedbd89
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:39:37 +00:00
Matt DeVillier
1b302934a9 ec/google/wilco/acpi: Hide CrOS-specific devices from OS
Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing
as missing drivers under Windows.

Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-20 14:39:00 +00:00
Matt DeVillier
adf21da264 mb/google/volteer: add VBTs for lindar variant
Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.

TEST=build/boot lindar variant with FSP/GOP display init, edk2 payload

Change-Id: I81022670fabda7994e292d333c999b508e61b469
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:35:26 +00:00
Matt DeVillier
6b650811e5 mb/google/dedede: add VBTs for drawcia, mangolor variants
Add VBT data files, ensure secondary VBTs compiled in as needed,
select INTEL_GMA_HAVE_VBT.

TEST=build/boot drawcia, mangolor variants with FSP/GOP display
init and edk2 payload

Change-Id: I58a2ed59bd858ce772e92f6659d341036823b11a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 14:35:02 +00:00
Reka Norman
897f72a111 mb/google/nissa/var/nivviks: Change ISH name to adl_ish_lite.bin
The ISH build target used for nissa is called adl_ish_lite: CL:3925007,
and by default the binary is installed as
/lib/firmware/intel/adl_ish_lite.bin

We could change the installed name, but it's nicer to keep it consistent
with the build target, so change the name in coreboot instead.

BUG=b:234776154
TEST=Build and boot nirwen, check firmware name is updated in SSDT

Change-Id: I983a38d08e758cf5a12a3f91a601c7e57d42c0cb
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-10-20 14:34:48 +00:00
David Wu
6fb95d8558 mb/google/brask/var/kuldax: Set PL and PsysPL
1. Set the PL1, PL2 and PL4.
2. Set PsysPL2 and PsysPmax.

BUG=b:253380352 b:253542746
TEST=Compare the measured power from adapter with the value of 'psys'
     from the command 'dump_intel_rapl_consumption'.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0a7ff64689b39e7754e0aed2f6869881a682fc93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68437
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-19 09:35:50 +00:00
Zanxi Chen
55d47bd1bf mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4
This change disables unused PCIE RP8 and CLKSRC4. Without this change
storo cannot enter into s0ix properly.

BUG=b:219376808
TEST=Built and verified in storo

Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
2022-10-18 23:10:37 +00:00
Felix Held
164c5eda27 soc/amd: factor out writing extended PM registers in FADT
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59985f283f1694beeacb0999340111146fa3f39b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-18 23:07:37 +00:00
Fred Reitberger
13831223be soc/amd/*/i2c: Move reset_i2c_peripherals to i2c.c
Move i2c SoC related code from early_fch.c to i2c.c

TEST=build boards for each SoC

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-18 16:09:44 +00:00
Fred Reitberger
f2b36036c7 soc/amd/morgana/gpio: Update gpio definitions for morgana
Update the GPIO definitions for morgana per PPR #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fa4aaf81b5487f7548f430cb35630aca8be732f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-18 16:08:45 +00:00
Gwendal Grignou
4ee037e8f0 mainboard/google: Remove ACPI ALS device
Remove the ACPI ALS device from the EC configuration for newer devices,
because some do not have light sensors, and those who do have their ALS
presented through the new EC sensor interface already.

Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device")

BUG=b:253967865
BRANCH=none
TEST=Boot a device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.

Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 16:08:10 +00:00
Teddy Shih
630fb54886 mb/google/dedede/var/beadrix: Update SoC gpio pin of USB camera
Update SoC GPIO setting of camera according to beadrix schematics.

GPP_D13 : NC -> PLTRST (EN_PP2800_CAMERA)

BRANCH=dedede
BUG=b:247178737,b:244120730
TEST=on beadrix, validated by beadrix seconds_system_resume < 500 ms.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Id00cb85cdad900c03842ad69707966aa62410efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-10-18 13:13:25 +00:00
Matt DeVillier
10817c7d5a mb/google/glados: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build glados w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: Id8abf68ed2e9720b5580f7965208dbe36460af07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:12:34 +00:00
Matt DeVillier
ad60b7fb56 mb/google/reef: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build reef w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: I4fe3092e620bcbc33b0411ea69e55154fc118aa4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:12:00 +00:00
Matt DeVillier
856a3f4a3c mb/google/sarien: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).

TEST=build sarien w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.

Change-Id: I424033e087bc37c651a922273718fc229b720448
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-18 13:11:50 +00:00
Amanda Huang
c586e9a0a3 mb/google/skyrim/var/skyrim: Add supported memory parts
Add two memory parts and generate the associated DRAM part ID.

1) Hynix H58G66AK6BX070
2) Micron MT62F1G32D2DS-026 WT:B

BUG=b:251363645
TEST=none

Change-Id: Iceb31576533a5b29c5957170473152014fc7e9c8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-18 03:23:09 +00:00
Yu-Ping Wu
3a1333da36 mb/google/corsola: Configure TPM IRQ as EDGE_FALLING
When the GSC is ready for the next transaction, it triggers a
GSC_AP_INT_ODL (active low) pulse with 100us duration to notify the AP.
Currently the TPM IRQ is configured as EDGE_RISING. Changing it to
EDGE_FALLING would speed up each register access by 100us. On Kingler,
this saves 20ms for the boot time (0.93s -> 0.91s).

BUG=b:235185547
TEST=emerge-corsola coreboot
TEST=Kingler booted without TPM errors
BRANCH=none

Change-Id: Id282e0f35694bd151781845cbd5aa4b389a30ddc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-10-18 03:01:16 +00:00
Martin Roth
a2efadd1b4 MAINTAINERS: Create release team
To help make sure that future releases are done correctly and on time,
we are setting up a team with the shared responsibility for doing the
releases and maintaining the release notes, scripts, and documentation.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5ef5b10fce9b16241de548df225fd12c9a7e199f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-17 23:07:03 +00:00
Matt DeVillier
6cb30195ad mb/google/brya: Guard FMD selection with CHROMEOS
Allows brya boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.

TEST=build/boot brya/banshee with edk2 payload, non-ChromeOS build

Change-Id: I21c2247c034d9bdc49f66771a93abad542a1e1fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 22:15:18 +00:00
Matt DeVillier
961f94d84e mb/google/dedede: Guard FMD selection with CHROMEOS
Allows dedede boards to use coreboot-generated FMAP layout
when building for non-ChromeOS target.

TEST=build/boot dedede with edk2 payload, non-ChromeOS build

Change-Id: Icb975455cde0d75a5af9130ba3e82a4fb0df5613
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 22:15:06 +00:00
Christian Walter
a8c10c8298 Makefile: Add targets to add and remove symlinks
When "make symlink" is run, it looks for symlink.txt files recursively
under site-local directory, and make symbolic links accordingly.

"make clean-symlink" removes the symbolic links made.

One application is for development of support for new processors and/or
new mainboards, where new directories are added, along with some common
code changes.

Change-Id: I3fa119675ecca1626d70375a61e8a71abec6a53b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-17 14:00:46 +00:00
Michał Żygowski
ccbb98880b Documentation/drivers/cbfs_smbios.md: Describe CBFS serial number
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6f0963417c7c580f903922ac88c95569c8782bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-17 13:58:23 +00:00
Arthur Heymans
d0b2aa1c5d nb/amd/agesa/fam16kb: Remove dead code
Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.

Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.

Change-Id: I7edf19f71095fb38161f19d511997cdc2fe0d76c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:48:00 +00:00
Arthur Heymans
6fa6e11d78 nb/amd/agesa/fam15tn: Remove dead code
Setting up HT resource seems to be copied from the old native family10
code. It is however not used as no device has a child device below 18.0
in any of the fam15tn board device trees.

Setting up HT resources is therefore done by AGESA and resource
allocation mostly happens to work.

Change-Id: Id95e2dec4a6f3e70234fff1df67ee61e08731400
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68411
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:47:48 +00:00
Zhixing Ma
42bb7df28c arch/x86/smbios.c: Fix Upgrade processor information in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements upgrade function.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf

BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor upgrade value is correct.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I5796d31fa2d31b17afa5eddde0799b0f68d69909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68024
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-17 13:44:58 +00:00
Bill XIE
854c897eb8 mb/supermicro/x9sae: Add full NCT6776 support
X9SAE has a PS/2 controller for keyboard and mouse but its definition
in ACPI used to be missing, and X9SAE used to use a generic SuperIO
support initially generated by autoport, so the full NCT6776 support
is added here like x9scl.

Test result:
Log lines like

    i8042: PNP: No PS/2 controller found.
    i8042: Probing ports directly.
    serio: i8042 KBD port at 0x60,0x64 irq 1
    serio: i8042 AUX port at 0x60,0x64 irq 12
    mousedev: PS/2 mouse device common for all mice

become

    i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at
        0x60,0x64 irq 1,12
    serio: i8042 KBD port at 0x60,0x64 irq 1
    serio: i8042 AUX port at 0x60,0x64 irq 12
    mousedev: PS/2 mouse device common for all mice

and more sub-devices within SuperIO is handled by the PNP driver.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie5e73e8c3fc4e57c6683d7a7ca70e96c64dd9366
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-17 13:43:50 +00:00
Felix Held
de10d5bf4d soc/amd: factor out common noncar bootblock
This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d80 ("soc/amd/picasso: Clean up
includes").

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-17 13:43:25 +00:00
Fred Reitberger
f73a3a5e08 soc/amd/*/smihandler: Make fch_apmc_smi_handler common
Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and
add the fch_apmc_smi_handler function.
Remove the duplicated function from picasso, cezanne, mendocino, and
morgana SoC.

The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so
give the handler a unique name that does not conflict with the common
handler name.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-17 13:42:46 +00:00
Elyes Haouas
9efe34a396 mb/ocp/deltalake: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If68ce4fef69a2466e76fc7fc504c00ee915e3e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-10-17 13:42:01 +00:00
Fred Reitberger
bc4b85f371 MAINTAINERS: Add AMD Morgana SoC and birman board
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iae811c97aba15dd6c9c740aedd7c802e14f53788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-17 13:41:33 +00:00
FrankChu
666f886ce7 mb/google/dedede/var/pirika: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:244620955
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia6cb56e76bc4e245a32f29b19226fa4fae330c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
2022-10-17 13:41:15 +00:00
Elyes Haouas
c35f281934 mb/*/*/gpio.h: Remove unused <soc/gpe.h>
Change-Id: I9b03ccc1100307e3c24393903600d18f6cc9abdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68378
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2022-10-17 13:40:55 +00:00
6607 changed files with 71260 additions and 774777 deletions

34
.gitmodules vendored
View File

@@ -1,67 +1,67 @@
[submodule "3rdparty/blobs"]
path = 3rdparty/blobs
url = ../blobs.git
url = https://review.coreboot.org/blobs.git
update = none
ignore = dirty
[submodule "util/nvidia-cbootimage"]
path = util/nvidia/cbootimage
url = ../nvidia-cbootimage.git
url = https://review.coreboot.org/nvidia-cbootimage.git
[submodule "vboot"]
path = 3rdparty/vboot
url = ../vboot.git
url = https://review.coreboot.org/vboot.git
branch = main
[submodule "arm-trusted-firmware"]
path = 3rdparty/arm-trusted-firmware
url = ../arm-trusted-firmware.git
url = https://review.coreboot.org/arm-trusted-firmware.git
[submodule "3rdparty/chromeec"]
path = 3rdparty/chromeec
url = ../chrome-ec.git
url = https://review.coreboot.org/chrome-ec.git
[submodule "libhwbase"]
path = 3rdparty/libhwbase
url = ../libhwbase.git
url = https://review.coreboot.org/libhwbase.git
[submodule "libgfxinit"]
path = 3rdparty/libgfxinit
url = ../libgfxinit.git
url = https://review.coreboot.org/libgfxinit.git
[submodule "3rdparty/fsp"]
path = 3rdparty/fsp
url = ../fsp.git
url = https://review.coreboot.org/fsp.git
update = none
ignore = dirty
[submodule "opensbi"]
path = 3rdparty/opensbi
url = ../opensbi.git
url = https://review.coreboot.org/opensbi.git
[submodule "intel-microcode"]
path = 3rdparty/intel-microcode
url = ../intel-microcode.git
url = https://review.coreboot.org/intel-microcode.git
update = none
ignore = dirty
branch = main
[submodule "3rdparty/ffs"]
path = 3rdparty/ffs
url = ../ffs.git
url = https://review.coreboot.org/ffs.git
[submodule "3rdparty/amd_blobs"]
path = 3rdparty/amd_blobs
url = ../amd_blobs
url = https://review.coreboot.org/amd_blobs
update = none
ignore = dirty
[submodule "3rdparty/cmocka"]
path = 3rdparty/cmocka
url = ../cmocka.git
url = https://review.coreboot.org/cmocka.git
update = none
branch = stable-1.1
[submodule "3rdparty/qc_blobs"]
path = 3rdparty/qc_blobs
url = ../qc_blobs.git
url = https://review.coreboot.org/qc_blobs.git
update = none
ignore = dirty
[submodule "3rdparty/intel-sec-tools"]
path = 3rdparty/intel-sec-tools
url = ../9esec-security-tooling.git
url = https://review.coreboot.org/9esec-security-tooling.git
[submodule "3rdparty/stm"]
path = 3rdparty/stm
url = ../STM
url = https://review.coreboot.org/STM
branch = stmpe
[submodule "util/goswid"]
path = util/goswid
url = ../goswid
url = https://review.coreboot.org/goswid.git
branch = trunk

2
3rdparty/blobs vendored

2
3rdparty/fsp vendored

2
3rdparty/vboot vendored

View File

@@ -1,3 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for coreboot paper.
# hacked together by Stefan Reinauer <stepan@openbios.org>

View File

@@ -1,3 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
# Makefile for Sphinx documentation
#

View File

@@ -11,6 +11,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
`acpihelp _XXX`
* 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)
* 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space.
Better abbreviated as 4GiB
* 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)
## A
@@ -45,6 +46,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* ALIB - AMD: ACPI-ASL Library
* ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor)
* ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit)
* AMBA - ARM: [**Advanced Microcontroller Bus
Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture):
An open standard to connect and manage functional blocks in an SoC
(System on a Chip)
* AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
SBI: Sideband Interface
@@ -53,8 +58,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* AOAC - AMD: Always On, Always Connected
* AP - Application processor - The main processor on the board (as
opposed to the embedded controller or other processors that may be on
the system), any cores in processor chip that isnt the BSP - Boot
Strap Processor.
the system), any cores in the processor chip that aren't the BSP (Boot
Strap Processor).
* APCB - AMD: AMD PSP Customization Block
* API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
* APIC - [**Advanced Programmable Interrupt
@@ -123,6 +128,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
stored as a single object, this was co-opted by the open source
communities to mean any proprietary binary file that is not available
as source code.
* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering)
* BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management_Interface#Baseboard_management_controller)
* BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format)
* BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials)
@@ -165,7 +171,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity)
* CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim)
* CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)
* CL - Change List - A git patch in gerrit
* CL - ChangeList - Another name for a patch or commit. This seems to be
Perforce notation.
* CLK - Clock - Used when there isn't enough room for 2 additional
characters - similar to RST, for people who hate vowels.
* CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake)
@@ -180,6 +187,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
* CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device)
* CPPC - AMD: Collaborative Processor Performance Controls
* CPS - Characters Per Second
* CPU - [**Central Processing
Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
@@ -196,12 +204,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* CSI - MIPI: [**Camera Serial
Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface)
* CSME - Intel: Converged Security and Management Engine
* CTLE - Intel: Continuous Time Linear Equalization
* CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
* CZN - AMD: Cezanne - CPU Family 19h, Model 50h
* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
## D
* D$ - Data Cache
* D-States - [**ACPI Device power
states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface#Device_states)
D0-D3 - These are device specific power states, with each higher
@@ -223,6 +233,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel)
* DDI - Intel: Digital Display Interface
* DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
* DEVAPC - Mediatek: Device Access Permission Control
* DFP - USB: Downstream Facing port
* DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
* DID - Device Identifier
* DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
@@ -235,6 +247,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Graphics Card, Sound Card. DMA is an essential feature of all modern
computers, as it allows devices of different speeds to communicate
without subjecting the CPU to a massive interrupt load.
* DMI - Direct Media Interface is a link/bus between CPU and PCH.
* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
* DMIC - Digital Microphone
* DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
@@ -243,6 +256,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton)
* DOS - Disk Operating System
* DP - DisplayPort
* DPM - Mediatek: DRAM Power Manager
* DPTF - Intel: Dynamic Power and Thermal Framework
* DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
* DRTM - Dynamic Root of Trust for Measurement
@@ -250,7 +264,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
data-in pin is generally referred to as D, and the data-out pin is Q,
thus the IO Data signal lines are referred to as DQ lines.
* DQS - Memory: Data Q Strobe - Data valid signal for DDR memory.
* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
* DRM - [**Digital Rights
Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or
an Upstream Facing (UFP).
* DRQ - DMA Request
* DRTU - Intel: Diagnostics and Regulatory Testing Utility
* DSDT - The [**Differentiated System Descriptor
@@ -262,12 +279,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line)
* DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor)
* DTB - U-Boot: Device Tree Binary
* dTPM - Discrete Trusted Platform Module
* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
vs Integrated TPMs or fTPMs (Firmware TPMs).
* DTS - U-Boot: Device Tree Source
* DVFS - ARM: Dynamic Voltage and Frequency Scaling
* DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
* DVT - Production Timeline: Design Validation Test
* DW - DesignWare
* DW - DesignWare: A portfolio of silicon IP blocks for sale by the
Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA,
I2c, memory controllers and more.
* DXE - UEFI: [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface#DXE_%E2%80%93_Driver_Execution_Environment_)
* DXIO - AMD: Distributed CrossBar I/O
@@ -283,7 +303,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
- A DRAM standard introduced in 1994 that improved upon, but was
backwards compatible with FPM (Fast Page Mode) memory.
* EDP - [**Embedded DisplayPort**](DisplayPort)
* eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP)
* EDS - Intel: External Design Specification
* EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
electrical erasable programmable ROM).
@@ -340,7 +360,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
* FSP - Intel: Firmware Support Package
* FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
* FTPM - Firmware TPM
* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is
based in firmware instead of actual hardware. It typically runs in
some sort of TEE (Trusted Execution Environment).
## G
@@ -356,6 +378,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Real Time Clock, and maybe a few other registers running.
* GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
* GATT - Graphics Aperture Translation Table
* GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table)
* GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake)
* GMA - Intel: [**Graphics Media
Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
@@ -407,6 +430,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
## I
* I$ - Instruction Cache
* I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for
communication generally between different ICs on a circuit board.
* [https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html](https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html)
@@ -428,6 +452,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI
slot has a signal called IDSEL. It is used to differentiate between
the different slots.
* IDT - [Interrupt Descriptor Table](https://en.wikipedia.org/wiki/Interrupt_descriptor_table)
* IF - AMD: [**Infinity
Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
is a superset of AMD's earlier Hypertransport interconnect.
@@ -539,7 +564,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MCU - Memory Control Unit
* MCU - [**MicroController
Unit**](https://en.wikipedia.org/wiki/Microcontroller)
* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
* MDFIO - Intel: Multi-Die Fabric IO
* MDN - AMD: Mendocino
* ME - Intel: Management Engine
* MEI - Intel: ME Interface (Previously known as HECI)
* Memory training - the process of finding the best speeds, voltages,
@@ -578,9 +605,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
OS software writers to produce SMP-capable machines and OSes in a
vendor-independent manner. Version 1.1 of the spec was released in
1994, and the 1.4 version was released in 1995. This has been
generally been
https://en.wikipedia.org/wiki/MultiProcessor_Specification by the ACPI
tables.
generally superseded by the ACPI tables.
* MRC - Intel: Memory Reference Code
* MSB - Most Significant Bit
* MSI - Message Signaled Interrupt
@@ -588,8 +613,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* MT/s - MegaTransfers per second
* MTL - Intel: Meteor Lake
* MTL - ARM: MHU Transport Layer
* MTRR - [**Memory Type and Range
Register**](http://en.wikipedia.org/wiki/MTRR)
* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
allows to set the cache behaviour on memory access in x86. Basically,
it tells the CPU how to cache certain ranges of memory
(e.g. write-through, write-combining, write-back...). Memory ranges
are specified over physical address ranges. In Linux, they are visible
over `/proc/mtrr` and they can be modified there. For further
information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
## N
@@ -621,8 +651,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state
* ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state.
* ODM - Original Design Manufacturer
* OEM - Original Equipment Manufacturer
* ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer)
* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufacturer)
* OHCI - [**Open Host Controller
Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB%29)
- non-proprietary USB Host controller for USB 1.1 (May also refer to
@@ -643,7 +673,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* PAT - [**Page Attribute
Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can
be used independently or in combination with MTRR to setup memory type
access ranges. Allows more finely-grained control than MTRR.
access ranges. Allows more finely-grained control than MTRR. Compared to MTRR,
which sets memory types by physical address ranges, PAT sets them at Page
level.
* PAT - Intel: [**Performance Acceleration
Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_technology)
* PATA - Parallel Advanced Technology Attachment - A renaming of ATA
@@ -669,7 +701,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
function's configuration space from 256 bytes to 4K.
* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
* PCMCIA: Personal Computer Memory Card International Association
* PCO - AMD: Picasso
* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
* PCR: TPM: Platform Configuration Register
* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage. Setting it low drives it to ground through a resistor.
* PD - Power Delivery - This is a specification for communicating power
@@ -837,6 +869,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
Memory)
* SEV - AMD: Secure Encrypted Virtualization
* SF - Snoop Filter
* Shadow RAM - RAM which content is copied from ROM residing at the same
address for speedup purposes.
* Shim - A small piece of code whose only purpose is to act as an
@@ -873,6 +906,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* SPI - [**Serial Peripheral
Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface)
* SPL - AMD: Security Patch Level
* SPM - Mediatek: System Power Manager
* SPMI - MIPI: System Power Management Interface
* SRAM - Static Random Access Memory
* SSD - Solid State Drive
@@ -889,7 +923,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
* SSI-TEB - Physical board format: [**SSI Thin Electronics
Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
* STAPM - AMD: Skin Temperature Aware Power Management
* STB - AMD: Smart Trace Buffer
* SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
(SIO) device provides a system with any of a number of different
peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT
@@ -909,7 +945,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* TDMA - Time-Division Multiple Access
* TDP - [**Thermal Design
Power**](https://en.wikipedia.org/wiki/Thermal_design_power)
* TEE - Trusted Execution Environment
* TEE - [**Trusted Execution
Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment)
* TFTP - Network Protocol: Trivial File Transfer Protocol
* TGL - Intel: Tigerlake
* THC - Touch Host Controller
@@ -919,6 +956,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* TLA - Three Letter Acronym
* TLB - [**Translation Lookside
Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer)
* TME - Intel: Total Memory Encryption
* TOCTOU - Time-Of-Check to Time-Of-Use
* TOLUM - Top of Low Usable Memory
* ToM - Top of Memory
@@ -927,6 +965,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* TSC - [**Time Stamp
Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
* TSEG - TOM (Top of Memory) Segment
* TSR - Temperature Sensor
* TWAIN - Technology without an interesting name.
* TX - Transmit
* TXE - Intel: Trusted eXecution Engine
@@ -940,6 +979,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
* UDK - UEFI: UEFI Development Kit
* UDP - User Datagram Protocol
* UEFI - Unified Extensible Firmware Interface
* UFP - USB: Upstream Facing Port
* UFS - Universal Flash storage
* UHCI - USB: [**Universal Host Controller
Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29%23UHCI)
@@ -989,6 +1029,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
tablets, it's on the the side away from the screen.
* WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
* WLAN - Wireless LAN (Local Area Network)
* WWAN - Telecommunication: Wireless WAN (Wide Area Network)
* WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
* WO - Write-only
* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)

View File

@@ -66,7 +66,7 @@ case 'm':
case 'K':
case 'k':
mem <<= 10;
/* fall through */
__fallthrough;
default:
break;
}
@@ -818,9 +818,9 @@ Function return values and names
Functions can return values of many different kinds, and one of the most
common is a value indicating whether the function succeeded or failed.
Such a value can be represented as an error-code integer (-Exxx =
failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
= success).
Such a value can be represented as an error-code integer (`CB_ERR_xxx`
(negative number) = failure, `CB_SUCCESS` (0) = success) or a "succeeded"
boolean (0 = failure, non-zero = success).
Mixing up these two sorts of representations is a fertile source of
difficult-to-find bugs. If the C language included a strong distinction
@@ -832,21 +832,84 @@ If the name of a function is an action or an imperative command,
the function should return an error-code integer.  If the name
is a predicate, the function should return a "succeeded" boolean.
For example, "add work" is a command, and the add_work() function
returns 0 for success or -EBUSY for failure. In the same way, "PCI
device present" is a predicate, and the pci_dev_present() function
For example, "add work" is a command, and the `add_work()` function
returns 0 for success or `CB_ERR` for failure. In the same way, "PCI
device present" is a predicate, and the `pci_dev_present()` function
returns 1 if it succeeds in finding a matching device or 0 if it
doesn't.
All EXPORTed functions must respect this convention, and so should all
public functions. Private (static) functions need not, but it is
recommended that they do.
Functions whose return value is the actual result of a computation,
rather than an indication of whether the computation succeeded, are not
subject to this rule. Generally they indicate failure by returning some
out-of-range result. Typical examples would be functions that return
pointers; they use NULL or the ERR_PTR mechanism to report failure.
pointers; they use NULL to report failure.
Error handling, assertions and die()
-----------------------------
As firmware, coreboot has no means to let the user interactively fix things when
something goes wrong. We either succeed to boot or the device becomes a brick
that must be recovered through complicated external means (e.g. a flash
programmer). Therefore, coreboot code should strive to continue booting
wherever possible.
In most cases, errors should be handled by logging a message of at least
`BIOS_ERR` level, returning out of the function stack for the failed feature,
and then continuing execution. For example, if a function reading the EDID of an
eDP display panel encounters an I2C error, it should print a "cannot read EDID"
message and return an error code. The calling display initialization function
knows that without the EDID there is no way to initialize the display correctly,
so it will also immediately return with an error code without running its
remaining code that would initialize the SoC's display controller. Exeuction
returns further up the function stack to the mainboard initialization code
which continues booting despite the failed display initialization, since
display functionality is non-essential to the system. (Code is encouraged but
not required to use `enum cb_err` error codes to return these errors.)
coreboot also has the `die()` function that completely halts execution. `die()`
should only be used as a last resort, since it results in the worst user
experience (bricked system). It is generally preferrable to continue executing
even after a problem was encountered that might be fatal (e.g. SPI clock
couldn't be configured correctly), because a slight chance of successfully
booting is still better than not booting at all. The only cases where `die()`
should be used are:
1. There is no (simple) way to continue executing. For example, when loading the
next stage from SPI flash fails, we don't have any more code to execute. When
memory initialization fails, we have no space to load the ramstage into.
2. Continuing execution would pose a security risk. All security features in
coreboot are optional, but when they are configured in the user must be able
to rely on them. For example, if CBFS verification is enabled and the file
hash when loading the romstage doesn't match what it should be, it is better
to stop execution than to jump to potentially malicious code.
In addition to normal error logging with `printk()`, coreboot also offers the
`assert()` macro. `assert()` should be used judiciously to confirm that
conditions are true which the programmer _knows_ to be true, in order to catch
programming errors and incorrect assumptions. It is therefore different from a
normal `if ()`-check that is used to actually test for things which may turn
out to be true or false based on external conditions. For example, anything
that involves communicating with hardware, such as whether an attempt to read
from SPI flash succeeded, should _not_ use `assert()` and should instead just
be checked with a normal `if ()` and subsequent manual error handling. Hardware
can always fail for various reasons and the programmer can never 100% assume in
advance that it will work as expected. On the other hand, if a function takes a
pointer parameter `ctx` and the contract for that function (as documented in a
comment above its declaration) specifies that this parameter should point to a
valid context structure, then adding an `assert(ctx)` line to that function may
be a good idea. The programmer knows that this function should never be called
with a NULL pointer (because that's how it is specified), and if it was actually
called with a NULL pointer that would indicate a programming error on account of
the caller.
`assert()` can be configured to either just print an error message and continue
execution (default), or call `die()` (when `CONFIG_FATAL_ASSERTS` is set).
Developers are encouraged to always test their code with this option enabled to
make assertion errors (and therefore bugs) more easy to notice. Since assertions
thus do not always stop execution, they should never be relied upon to be the
sole guard against conditions that really _need_ to stop execution (e.g.
security guarantees should never be enforced only by `assert()`).
Headers and includes
---------------

View File

@@ -3,6 +3,84 @@
The document describes the coreboot options how to make CBFS files populate
platform-unique SMBIOS data.
## SMBIOS Serial Number
The [DMTF SMBIOS specification] defines a field in the type 1 System
Information and type 2 Baseboard Information called Serial Number. It
is a null-terminated string field assumed to be unique per platform. Certain
mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
provide an option to populate the Serial Numbers from CBFS for boards that
can't generate the it from any source.
### Usage
In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
and select an option `Serial number in CBFS`. The Kconfig system will enable
`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
coreboot image.
After the coreboot build for your board completes, use the cbfstool to include
the file containing the serial number:
```shell
./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
```
Where `serial_file.txt` is the unterminated string representation of the SMBIOS
type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
partitions you will have to specify the RW regions where the file is going to
be added too. By default the RW CBFS partitions are truncated, so the files
would probably not fit, one needs to expand them first.
```shell
./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-f /path/to/serial_file.txt -r FW_MAIN_A
./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-f /path/to/serial_file.txt -r FW_MAIN_B
./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
```
By default cbfstool adds files to COREBOOT region only, so when vboot is
enabled and the platform is booting from RW partition, the file would not be
picked up by the driver.
One may retrieve the Serial Number from running system (if it exists) using one
of the following commands:
```shell
# Type 1
echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
# OR Type 2
echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
```
Ensure the file does not end with whitespaces like LF and/or CR. The above
commands will not add any whitespaces. The driver automatically terminates the
Serial Number with the NULL character. If the CBFS file is not present, the
driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
option.
Please note that this driver provides `smbios_mainboard_serial_number` hook
overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
build option. If you wish to populate only type 2 Serial Number field your
board code needs to implement `smbios_system_serial_number`, otherwise the weak
implementation of `smbios_system_serial_number` will call
`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
if the board does not implement its own `smbios_system_serial_number`.
There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
implementation (returns empty string). If you wish to populate type 3 Serial
Number, your board code should override the default
`smbios_chassis_serial_number` weak implementation.
## SMBIOS System UUID
The [DMTF SMBIOS specification] defines a field in the type 1 System

View File

@@ -8,7 +8,7 @@ device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
register "detect" = "1"
register "wake" = "GPE0_DW0_21"
device i2c 15 on end
@@ -39,7 +39,7 @@ Scope (\_SB.PCI0.I2C0)
I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
AddressingMode7Bit, "\\_SB.PCI0.I2C0",
0x00, ResourceConsumer, , Exclusive, )
Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
{
0x0000002D,
}
@@ -54,7 +54,7 @@ Scope (\_SB.PCI0.I2C0)
}
```
You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
names/methods in the Device's scope.
## Utilizing a device driver
@@ -88,7 +88,7 @@ be included in the ACPI table.
register "hid" = ""ELAN0000""
```
This corresponds to **const char *hid** in the struct. In the ACPI ASL, it
This corresponds to **const char \*hid** in the struct. In the ACPI ASL, it
translates to:
```
@@ -104,7 +104,7 @@ during enumeration in the OS.**
register "desc" = ""ELAN Touchpad""
```
corresponds to **const char *desc** and in ASL:
corresponds to **const char \*desc** and in ASL:
```
Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
@@ -115,7 +115,7 @@ corresponds to **const char *desc** and in ASL:
It also adds the interrupt,
```
Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
{
0x0000002D,
}
@@ -124,23 +124,30 @@ It also adds the interrupt,
which comes from:
```
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
```
The GPIO pin IRQ settings control the "Level", "ActiveLow", and
"ExclusiveAndWake" settings seen above (level means it is a level-triggered
interrupt as opposed to edge-triggered; active low means the interrupt is
triggered when the signal is low).
The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
means it is a level-triggered interrupt as opposed to
edge-triggered; active low means the interrupt is triggered when the signal is
low).
Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
source. Also note that the IRQ names are SoC-specific, and you will need to
Also note that the IRQ names are SoC-specific, and you will need to
find the names in your SoC's header file. The ACPI_* macros are defined in
``src/arch/x86/include/acpi/acpi_device.h``.
Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
This is often done in a mainboard-specific file named ``gpio.c``.
AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
GPIO controller needs to be used directly. You can do this by setting the
`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
i.e.,
```
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
```
### detect
The next register is:
@@ -162,9 +169,10 @@ I2C audio devices should also work without issue.
Touchscreens can use this feature as well, but special care is needed to
implement the proper power sequencing for the device to be detected. Generally,
this means driving the enable GPIO high and holding the reset GPIO low in early
GPIO init (bootblock/romstage), then releasing reset in ramstage. While no
boards in the tree currently implement this, it has been used in downstream
forks without issue for some time now.
GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
mainboards in the tree to implement this are google/skyrim and google/guybrush.
This feature has also been used in downstream forks without issue for some time
now on several other boards.
### wake
@@ -179,6 +187,8 @@ through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
this example. The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
elsewhere in the devicetree.
### device
The last bit of the definition of that device includes:
```
@@ -192,6 +202,65 @@ found on. In this example, this is I2C bus 0. This also determines the ACPI
"Scope" that the device names and methods will live under, in this case
"\_SB.PCI0.I2C0".
## Wake sources
The ACPI spec defines two methods to describe how a device can wake the system.
Only one of these methods should be used, otherwise duplicate wake events will
be generated.
### Using GPEs as a wake source
The `wake` property specified above is used to tell the ACPI subsystem that the
device can use a GPE to wake the system. The OS can control whether to enable
or disable the wake source by unmasking/masking off the GPE.
The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
generally done by a mainboard specific `gpio.c` file that defines the GPIO
using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
GPEs (the rest are available as `tier-2` GPEs).
Windows has a large caveat when using this method. If you use the `gpio_irq`
property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
to define a `GPE`, Windows will
[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
complaining about an invalid ACPI configuration.
> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
In order to avoid this error, you should use the `irq` property instead. AMD
platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
feasible. The other option is to use a wake capable GPIO as described below.
### Using GPIO interrupts as a wake source
The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
This method has a few caveats:
* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
system. Instead you need to use the `gpio_irq` property, or a `GPE` as
described above.
* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
means the platform specific GPIO controller driver must implement the
`irq_set_wake` callback. For AMD systems this wasn't
[implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
until linux v5.15. If the controller doesn't define this callback, it's
possible for the firmware to manually set the `wake` bit on the GPIO. This is
often done in a mainboard-specific file named `gpio.c`. This is not
recommended because then it's not possible for the OS to disable the wake
source.
* As of
[linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
the ACPI subsystem doesn't take the interrupt `wake` bit into account when
deciding on which power state to put the device in before suspending the
system. This means that if you define a power resource for a device via
`has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
device into D3Cold. i.e., power off the device.
## Other auto-generated names
(see [ACPI specification
@@ -199,17 +268,19 @@ found on. In this example, this is I2C bus 0. This also determines the ACPI
for more details on ACPI methods)
### _S0W (S0 Device Wake State)
_S0W indicates the deepest S0 sleep state this device can wake itself from,
which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
\_S0W indicates the deepest S0 sleep state this device can wake itself from,
which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
D3Hot means the `PR3` power resources are still on and the device is still
responsive on the bus. For i2c devices this is generally the same state as `D0`.
### _PRW (Power Resources for Wake)
_PRW indicates the power resources and events required for wake. There are no
### \_PRW (Power Resources for Wake)
\_PRW indicates the power resources and events required for wake. There are no
dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
as well as the deepest sleep state supporting waking the system (3), which is
S3.
### _STA (Status)
The _STA method is generated automatically, and its values, 0xF, indicates the
### \_STA (Status)
The \_STA method is generated automatically, and its values, 0xF, indicates the
following:
Bit [0] Set if the device is present.
@@ -217,8 +288,8 @@ following:
Bit [2] Set if the device should be shown in the UI.
Bit [3] Set if the device is functioning properly (cleared if device failed its diagnostics).
### _CRS (Current resource settings)
The _CRS method is generated automatically, as the driver knows it is an I2C
### \_CRS (Current resource settings)
The \_CRS method is generated automatically, as the driver knows it is an I2C
controller, and so specifies how to configure the controller for proper
operation with the touchpad.

View File

@@ -0,0 +1,114 @@
# External Resources
This is a list of resources that could be useful to coreboot developers.
These are not endorsed or officially recommended by the coreboot project,
but simply listed here in the hopes that someone will find something
useful.
Please add any helpful or informational links and sections as you see fit.
## Articles
* External Interrupts in the x86 system.
* [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
* [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
* [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
* System address map initialization in x86/x64 architecture.
* [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
* [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
* [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
## General Information
* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
* [Interface BUS](http://www.interfacebus.com/)
* Open course material for a variety of topics such as assembly, firmware,
security, debugging, and more.
* [Open Security Training](https://opensecuritytraining.info/Training.html),
* [Open Security Training 2](https://p.ost2.fyi/)
## Firmware Specifications & Information
* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
### ACPI
* [ACPI Specs](https://uefi.org/acpi/specs)
* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
### Security
* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
## Hardware information
* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
* [Sandpile](https://www.sandpile.org/)
* [CPU-World](https://www.cpu-world.com/index.html)
* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
### Hardware Specifications & Standards
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
[Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED)
* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
* [USB](https://www.usb.org/documents) - USB Implementers Forum
* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
### Chip Vendor Documentation
* AMD
* [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
* [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
* ARM
* [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
* Intel
* [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
* [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
* [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
* [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
* Rockchip
* [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
## Software
* [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
* [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
* [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
* [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
* [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
* [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
## Infrastructure software
* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
* [GNU Make](https://www.gnu.org/software/make/manual/)

View File

@@ -197,4 +197,5 @@ Contents:
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
* [Release notes](releases/index.md)
* [Acronyms & Definitions](acronyms.md)
* [External Resources](external_docs.md)
* [Documentation License](documentation_license.md)

View File

@@ -383,7 +383,7 @@ training. This example expects that the default value of this `register` is set
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
mupd->ExampleFeature = false;
}
```

View File

@@ -85,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
## Intel
- [DG43GT](intel/dg43gt.md)
- [IceLake RVP](intel/icelake_rvp.md)
- [KBLRVP11](intel/kblrvp11.md)
## Kontron
@@ -185,6 +184,7 @@ The boards in this section are not real mainboards, but emulators.
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarLite Mk IV](starlabs/lite_glkr.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)
- [StarBook Mk VI](starlabs/starbook_adl.md)
- [Flashing devices](starlabs/common/flashing.md)
## Supermicro
@@ -201,16 +201,22 @@ The boards in this section are not real mainboards, but emulators.
- [Bonobo Workstation 14](system76/bonw14.md)
- [Darter Pro 6](system76/darp6.md)
- [Darter Pro 7](system76/darp7.md)
- [Darter Pro 8](system76/darp8.md)
- [Galago Pro 4](system76/galp4.md)
- [Galago Pro 5](system76/galp5.md)
- [Galago Pro 6](system76/galp6.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md)
- [Oryx Pro 5](system76/oryp5.md)
- [Oryx Pro 6](system76/oryp6.md)
- [Oryx Pro 7](system76/oryp7.md)
- [Oryx Pro 8](system76/oryp8.md)
- [Oryx Pro 9](system76/oryp9.md)
- [Oryx Pro 10](system76/oryp10.md)
## Texas Instruments

View File

@@ -1,40 +0,0 @@
# Intel Ice Lake RVP (Reference Validation Platform)
This page describes how to run coreboot on the Intel icelake_rvp board.
Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
```eval_rst
:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
```
## Building coreboot
* Follow build instructions mentioned in Ice Lake document
```eval_rst
:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
```
* The default options for this board should result in a fully working image:
```bash
# echo "CONFIG_VENDOR_INTEL=y" > .config
# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
# make olddefconfig && make
```
## Flashing coreboot
```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Winbond |
+---------------------+------------+
| Size | 32 MiB |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
```

View File

@@ -26,12 +26,12 @@ host up to 4 Delta Lake servers (blades) in one sled.
The Yosemite-V3 system is in mass production. Meta, Intel and partners
jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
OSF solution reached production quality for some use cases in July, 2021.
solution. The OSF solution reached production quality for some use cases
in July, 2021.
## How to build
OSF code base is public at
OSF code base is publicly available at
https://github.com/opencomputeproject/OpenSystemFirmware
Run following commands to build Delta Lake OSF image from scratch:
@@ -42,19 +42,21 @@ The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
Linux kernel and u-root code from their upstream repo, and sync down needed
binary blobs. [osf-builder] also provides the top level build system.
Delta Lake server OSF solution requires following binary blobs:
- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
coreboot.org mirrors this repo and by default the correct binary is included.
- ME binary: Ignition binary can be downloaded from
Besides coreboot, the Delta Lake OSF solution includes following components:
- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
- ME ignition binary: downloaded from
https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
- ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
- Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
U-root as initramfs, is used in the joint development. It can be built
U-root as initramfs, is used in the joint development. It is built
following [All about u-root].
## Flashing coreboot
The Delta Lake OSF solution is updated periodically to newer versions of
upstream coreboot code base and other components.
## How to verify Delta Lake OSF image
To do in-band FW image update, use [flashrom]:
flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
@@ -70,6 +72,21 @@ To power off/on the host:
To connect to console through SOL (Serial Over Lan):
sol-util slotx
## How to work on coreboot for Delta Lake
After the OSF image for Delta Lake is built and verified, under
OpenSystemFirmware/Wiwynn/deltalake directory:
cd src/osf-builder/projects/craterlake/coreboot
Run "git remote -v" to confirm the origin is from coreboot upstream repo.
Run "git branch -v" to know the confirmed working coreboot commit ID for the
Delta Lake OSF solution.
Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
image for Delta Lake, verify that it works.
Now you are in a familiar coreboot environment, happy coding!
## Firmware configurations
[ChromeOS VPD] is used to store most of the firmware configurations.
RO_VPD region holds default values, while RW_VPD region holds customized

View File

@@ -0,0 +1,30 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
#### StarBook series:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
#### StarLite series:
* Intel Flash Descriptor file (descriptor.bin)
* IFWI Image (ifwi.rom)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image, where the last two words represent the
series and processor i.e. `lite_glkr`:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
make
```

View File

@@ -41,27 +41,7 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
make
```
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
## Flashing coreboot

View File

@@ -38,26 +38,7 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
The below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
make
```
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
## Flashing coreboot

View File

@@ -37,27 +37,7 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
make
```
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
## Flashing coreboot

View File

@@ -37,26 +37,7 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* IFWI Image (ifwi.rom)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
make
```
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
## Flashing coreboot

View File

@@ -0,0 +1,88 @@
# StarBook Mk V
## Specs
- CPU (full processor specs available at https://ark.intel.com)
- Intel i7-1260P (Alder Lake)
- Intel i3-1220P (Alder Lake)
- EC
- ITE IT5570E
- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend / resume
- GPU
- Intel® Iris® Xe Graphics
- GOP driver is recommended, VBT is provided
- eDP 14-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- 2 x DDR4 SODIMM
- Networking
- AX210 2230 WiFi / Bluetooth
- Sound
- Realtek ALC269-VB6
- Internal speakers
- Internal microphone
- Combined headphone / microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 PCIe SSD
- RTS5129 MicroSD card reader
- USB
- 1920x1080 CCD camera
- USB 3.1 Gen 2 (left)
- USB 3.1 Gen 2 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)
- USB 2.0 Type-A (right)
## Building coreboot
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
make
```
## Flashing coreboot
```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Winbond |
+---------------------+------------+
| Model | W25Q256.V |
+---------------------+------------+
| Size | 32 MiB |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

View File

@@ -40,27 +40,7 @@
## Building coreboot
### Preliminaries
Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* Intel Management Engine firmware (me.bin)
* ITE Embedded Controller firmware (ec.bin)
The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
### Build
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
make
```
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
## Flashing coreboot

View File

@@ -0,0 +1,82 @@
# Syste76 Darter Pro 8 (darp8)
## Specs
- CPU
- Intel Core i5-1240P
- Intel Core i7-1260P
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 15.6" 1920x1080@60Hz LCD
- 1x HDMI
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (OZ711LV2)
- USB
- 1x USB-C Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 1x USB 3.2 (Gen 2) Type-A
- 1x USB 2.0 Type-A
- Dimensions
- 35.7cm x 22.05cm x 1.99cm, 1.74kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Winbond |
+---------------------+---------------------+
| Model | W25Q256.V |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U19) is above the left DIMM slot.

View File

@@ -0,0 +1,61 @@
# System76 Galago Pro 6 (galp6)
## Specs
- CPU
- Intel Core i5-1240P
- Intel Core i7-1260P
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
- USB-C charging, compatible with 90W+ chargers
- 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (OZ711LV2)
- USB
- 1x USB-C Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 32.49cm x 22.5cm x 1.82cm, 1.45kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U43) is left of the wireless card.

View File

@@ -0,0 +1,65 @@
# System76 Gazelle 17 (gaze17)
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
## Specs
- CPU
- Intel Core i5-12500H
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 3050
- NVIDIA GeForce RTX 3050 Ti
- NVIDIA GeForce RTX 3060
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
- Networking
- Gigabit Ethernet
- 3050: Realtek RTL8111H controller
- 3060: Onboard Intel I219-V
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX201
- Power
- 3050: 150W (20V, 7.5A) AC barrel adapter
- 3060: 180W (20V, 9A) AC barrel adapter
- Lite-On PA-1181-76, using a C5 power cord
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The position of the flash chip depends on the variant:
- 3050: U24, below the bottom DIMM slot.
- 3060: U55, left of the PCIe 4.0 M.2 slot.

View File

@@ -0,0 +1,62 @@
# System76 Lemur Pro 11 (lemp11)
## Specs
- CPU
- Intel Core i5-1235U
- Intel Core i7-1255U
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- Intel Iris Xe Graphics
- eDP 14.0" 1920x1080@60Hz LCD
- 1x HDMI 2.1
- 1x DisplayPort 1.4 over USB-C
- Memory
- Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
- Networking
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
- USB-C charging, compatible with 65W+ chargers
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5 mm headphone/microphone jack
- HDMI, USB-C DisplayPort audio
- Storage
- M.2 PCIe NVMe Gen 4 SSD
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-A
- 1x USB 3.2 (Gen 1) Type-A
- Dimensions
- 1.65cm x 32.2cm x 21.68cm, 1.15kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U41) is left of the DIMM slot.

View File

@@ -0,0 +1,69 @@
# System76 Oryx Pro 10 (oryp10)
## Specs
- CPU
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
- eDP options:
- 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
- 80Wh 6-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- Realtek ALC1306 smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
- 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the DIMM slots.

View File

@@ -0,0 +1,67 @@
# System76 Oryx Pro 9 (oryp9)
## Specs
- CPU
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options:
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
- eDP options:
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
- 1x HDMI 2.1
- 1x Mini DisplayPort 1.4
- 1x DisplayPort 1.4 over USB-C
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
- Networking
- Gigabit Ethernet
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
- Power
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
- 80Wh 6-cell Lithium-ion battery
- Sound
- Realtek ALC1220 codec
- TI TAS5825M smart amp
- Internal speakers and microphone
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack
- HDMI, mDP, USB-C DP audio
- Storage
- 2x M.2 PCIe NVMe Gen 4 SSD
- MicroSD card reader (RTS5227S)
- USB
- 1x USB Type-C with Thunderbolt 4
- 1x USB 3.2 (Gen 2) Type-C
- 2x USB 3.2 (Gen 1) Type-A
- Dimensions
- 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
- 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | Macronix |
+---------------------+---------------------+
| Model | MX25L25673G |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The flash chip (U61) is left of the DIMM slots.

View File

@@ -12,16 +12,59 @@ desired.
Currently, [jenkins](https://qa.coreboot.org), our continuous
integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
and 4.16 branches. Builders for other branches can be created on
4.16, and 4.18 branches. Builders for other branches can be created on
request. Likewise, some releases are only marked with tags, and
branches would need to be created to push new code to. These branches
can also be created on request.
Patches can be backported from the master branch to any of these other
branches as needed. The coreboot project will take care of backporting
branches as needed. The coreboot project may take care of backporting
critical security fixes, but other patches will need to handled by
anyone using that release.
## [4.18 Release](coreboot-4.18-relnotes.md)
Branch created, builder configured
```eval_rst
+-------------------------------+------------------------+------------+-----------+
| Vendor/Board | Processor | Date added | Brd type |
+===============================+========================+============+===========+
| amd/inagua | AMD_FAMILY14 | 2011-02-14 | eval |
| amd/olivehill | AMD_FAMILY16_KB | 2013-08-05 | eval |
| amd/parmer | AMD_FAMILY15_TN | 2012-07-22 | eval |
| amd/persimmon | AMD_FAMILY14 | 2011-02-14 | eval |
| amd/south_station | AMD_FAMILY14 | 2011-11-18 | eval |
| amd/thatcher | AMD_FAMILY15_TN | 2012-08-02 | eval |
| amd/union_station | AMD_FAMILY14 | 2011-11-18 | eval |
| asrock/e350m1 | AMD_FAMILY14 | 2011-02-24 | mini |
| asrock/imb-a180 | AMD_FAMILY16_KB | 2013-08-27 | mini |
| asus/a88xm-e | AMD_FAMILY15_TN | 2020-08-13 | desktop |
| asus/am1i-a | AMD_FAMILY16_KB | 2018-01-14 | mini |
| asus/f2a85-m | AMD_FAMILY15_TN | 2013-03-22 | desktop |
| bap/ode_e20XX | AMD_FAMILY16_KB | 2015-05-27 | eval |
| biostar/a68n_5200 | AMD_FAMILY16_KB | 2017-10-14 | eval |
| biostar/am1ml | AMD_FAMILY16_KB | 2015-04-10 | mini |
| elmex/pcm205400 | AMD_FAMILY14 | 2016-09-29 | sbc |
| gizmosphere/gizmo2 | AMD_FAMILY16_KB | 2014-12-09 | eval |
| gizmosphere/gizmo | AMD_FAMILY14 | 2014-01-03 | half |
| hp/abm | AMD_FAMILY16_KB | 2015-01-05 | mini |
| hp/pavilion_m6_1035dx | AMD_FAMILY15_TN | 2014-03-28 | laptop |
| jetway/nf81-t56n-lf | AMD_FAMILY14 | 2014-02-16 | mini |
| lenovo/g505s | AMD_FAMILY15_TN | 2014-11-27 | laptop |
| lippert/frontrunner-af | AMD_FAMILY14 | 2013-03-02 | half |
| msi/ms7721 | AMD_FAMILY15_TN | 2016-11-22 | desktop |
| pcengines/apu1 | AMD_FAMILY14 | 2015-02-23 | half |
+-------------------------------+------------------------+------------+-----------+
```
## [4.17 Release](coreboot-4.17-relnotes.md)
No Branch or builder
* No platforms maintained on this release
## [4.16 Release](coreboot-4.16-relnotes.md)
Branch created, builder configured

View File

@@ -4,56 +4,73 @@
# coreboot Release Process
This document describes our release process and all prerequisites to implement
it successfully.
This document describes our release process and all prerequisites to
implement it successfully.
## Purpose of coreboot releases
Our releases aren't primarily a vehicle for code that is stable across all
boards: The logistics of testing the more than 100 boards that are spread out
all continents (except Antarctica, probably) on a given tree state are
prohibitive for project of our size.
Our releases aren't primarily a vehicle for code that is stable across
all boards: The logistics of testing the more than 100 boards that are
spread out all continents (except Antarctica, probably) on a given tree
state are prohibitive for project of our size.
Instead, the releases are regular breakpoints that serve multiple purposes:
They support cooperation between multiple groups (corporations or otherwise)
in that it's easier to keep source trees synchronized based on a limited set
of commits. They allow a quick assessment of the age of any given build or
source tree based on its git version (4.8-1234 was merged into master a few
months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
guess).
Instead, the releases are regular breakpoints that serve multiple
purposes: They support cooperation between multiple groups (corporations
or otherwise) in that it's easier to keep source trees synchronized
based on a limited set of commits. They allow a quick assessment of the
age of any given build or source tree based on its git version (4.8-1234
was merged into master a few months after 4.8, which came out in April
of 2018. 4.0-21718's age is harder to guess).
And finally we use releases to as points in time where we remove old code:
Once we decide that a certain part of coreboot gets in the way of future
development, we announce on the next release that we intend to remove that
part - and everything that depends on it - after the following release.
So removing feature FOO will be announced in release X for release
X+1. The first commit after X+1 is fair game for such removal.
And finally we use releases to as points in time where we remove old
code: Once we decide that a certain part of coreboot gets in the way of
future development, we announce on the next release that we intend to
remove that part - and everything that depends on it - after the
following release. So removing feature FOO will be announced in release
X for release X+1. The first commit after X+1 is fair game for such
removal.
Together with our 6 months release horizon, this provides time to plan
Together with our 3 months release horizon, this provides time to plan
any migrations necessary to keep older boards in the tree by bringing
them up to current standards.
## coreboot release team
To avoid issues of blocking the release on a single person, a release
team has been formed. Please see the `COREBOOT RELEASES` section of the
MAINTAINERS file for the current members.
These individuals work together to make sure releases are done on time,
follow the steps of this document, and update the release processes and
scripts.
## Needed credentials & authorizations
### coreboot admins only
* Website access is required to post the release files to the website.
* IRC admin access is required to update the topic.
### All release team members
* IRC topic access is required to update the topic.
* Git access rights are needed to post the tag.
* Blog post access is needed to do the blog post.
* A PGP key is required to sign the release tarballs and git tag.
This set of required credentials implies that releases can only be done
by a coreboot admin.
Most of the steps in the release process can be done by anyone on the
release team. Only adding the files to the website needs to be done
by a coreboot administrator.
## When to release
Releases are done roughly on a 6-month schedule, ideally around end
of April and end of October (can be a bit earlier or delay into May
or November).
Releases are done roughly on a 3-month schedule. If a release is
delayed, the next release will still be 3 months after the last release.
We initially followed a 3 month release schedule, but we found that to
be more frequent than was needed, so we scaled it back to twice a year.
## Checklist
### ~2 weeks prior to release
- [ ] Announce upcoming release to mailing list, ask people to test and
to update release notes.
- [ ] Start marking patches that should to go into the release with a
tag "coreboot_release_X.yy"
### ~1 week prior to release
- [ ] Send reminder email to mailing list, ask for people to test,
@@ -66,28 +83,53 @@ be more frequent than was needed, so we scaled it back to twice a year.
- [ ] Finalize release notes as much as possible
- [ ] Prepare release notes template for following release
- [ ] Update `Documentation/releases/index.md`
- [ ] Check which branches need to be released. Any branch with changes
should get a new release. Announce these branch releases and
prepare release notes.
### Day before release
- [ ] Make sure patches with tags for the release are merged.
- [ ] Announce to IRC that the release will be tomorrow and ask for
testing.
- [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
boards supported by vboot.
### Day of release
- [ ] Select a commit ID to base the release upon, announce to IRC,
ask for testing.
- [ ] Review the full documentation about doing the release below.
- [ ] Select a commit ID to base the release upon.
- [ ] Test the commit selected for release.
- [ ] Submit release notes
- [ ] Create new release notes doc template for the next version.
- [ ] Fill in the release date, remove "Upcoming release" and other filler
from the current release notes.
- [ ] Run release script.
- [ ] Submit last pre-release release notes.
- [ ] Run the release script.
- [ ] Test the release from the actual release tarballs.
- [ ] Push signed Tag to repo.
- [ ] Push signed Tag to repo. *This is the actual release step.*
Once this patch is pushed, the release itself has been done.
everything after this step is packaging and delivering the
release.
- [ ] Announce that the release tag is done on IRC.
- [ ] Upload release files to web server.
- [ ] Also extract the release notes and place them on the web server.
- [ ] Upload crossgcc sources to web server.
- [ ] Update download page to point to files, push to repo.
- [ ] Write and publish blog post with release notes.
- [ ] Update the topic in the IRC channel that the release is done.
- [ ] Announce the release to the mailing list.
- [ ] Do the final release notes - Fill in the release date, remove
"Upcoming release" and other filler from the current release
notes.
- [ ] ADMIN: Upload release files to web server.
- [ ] ADMIN: Upload the final release notes to the web server.
- [ ] ADMIN: Upload crossgcc sources to web server.
- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images
based on the release ID and push them to dockerhub. These
can be used as release builders.
### Week following the release
- [ ] Update download page to point to files, push to repo.
- [ ] Write and publish blog post with release final notes. Branch
releases notes should be included in the same post.
- [ ] Remove code that was announced it was going to be removed.
- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
### Creating a branch
- [ ] Branches are named 4.xx_branch to differentiate from the tags.
Instructions on creating branches are listed below.
## Pre-Release tasks
Announce the upcoming release to the mailing list release 2 weeks ahead
@@ -102,29 +144,30 @@ People should be encouraged to provide additions to the release notes.
The final release notes will reside in coreboot's Documentation/releases
directory, so asking for additions to that through the regular Gerrit
process works as well. Note that git requires lots of conflict resolution
on heavily edited text files though.
process works as well. Note that git requires lots of conflict
resolution on heavily edited text files though.
Frequently, we will want to wait until particular things are in the
release. Once those are in, you can select the commit ID that you want
to use for your release. For the 4.6 release, we waited until we had
release. Once those are in, you can select the commit ID that you want
to use for your release. For the 4.6 release, we waited until we had
time to do the release, then pulled in a few patches that we wanted
to have in the release. The release was based on the final of those
to have in the release. The release was based on the final of those
patches to be pulled in.
When a release candidate has been selected, announce the commit ID to
the #coreboot IRC channel, and request that it get some testing, just
to make sure that everything is sane.
## Generate the release
After the commit for the release has been selected and verified, run the
release script - util/release/build-release. This will download a new
release script - util/release/build-release. This will download a new
tree, checkout the commit that you specified, download the submodules,
create a tag, then generate and sign the tarballs.
Be prepared to type in your PGP keys passphrase.
**Be prepared to type in your PGP keys passphrase.**
````
```text
usage: util/release/build-release <version> [commit id] [username] [gpg key id]
Tags a new coreboot version and creates a tar archive
@@ -132,37 +175,41 @@ version: New version name to tag the tree with
commit id: check out this commit-id after cloning the coreboot tree
username: clone the tree using ssh://USERNAME - defaults to https://
gpg key id: used to tag the version, and generate a gpg signature
````
```
After running the script, you should have a new directory for the release,
along with 4 files - 2 tarballs, and 2 signature files.
After running the script, you should have a new directory for the
release, along with 4 files: 2 tarballs, and 2 signature files.
````
```text
drwxr-xr-x 9 martin martin 4096 Apr 30 19:57 coreboot-4.6
-rw-r--r-- 1 martin martin 29156788 Apr 30 19:58 coreboot-4.6.tar.xz
-rw-r--r-- 1 martin martin 836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
-rw-r--r-- 1 martin martin 5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
-rw-r--r-- 1 martin martin 836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
````
```
Heres the command that was used to generate the 4.6 release:
````
% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
````
```bash
util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
```
## Test the release from the tarballs
* Run “make what-jenkins-does” and verify that everything is building.
* Build and test qemu
````
cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
````
```bash
cp configs/config.emulation_qemu_x86_i440fx .config
make olddefconfig
make
qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
```
* Build and test any other platforms you can.
* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
* Compare the directory from the tarballs to the coreboot repo to make
sure nothing went wrong.
* Push the tag to git
A good tag will look like this:
````
````text
% git show 4.6
tag 4.6
Tagger: Martin Roth <martinroth@google.com>
@@ -183,33 +230,44 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
...
````
When you used the script to generate the release, a signed tag was generated in the
tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
In case you pushed the wrong tag already, you have to force push the new one.
When you used the script to generate the release, a signed tag was
generated in the tree that was downloaded. From the coreboot-X.Y tree,
just run: `git push origin X.Y`. In case you pushed the wrong tag
already, you have to force push the new one.
You will need write access for tags to the coreboot git repo to do this.
## After the release is tagged in git
Announce that the release has been tagged - this lets people know that
they should update their trees to grab the new tag. Until they do this,
they should update their trees to grab the new tag. Until they do this,
the version number in build.h will still be based on the previous tag.
Copy the tarballs and .sig files generated by the script to
the coreboot server, and put them in the release directory at
`/srv/docker/www.coreboot.org-staticfiles/releases/`
````
% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
% mv sha256suma.txt sha256sum.txt
````bash
# Update the sha256sum file
sha256sum -b coreboot-*.tar.xz > sha256suma.txt
# make sure the two new files are present (and nothing else has changed)
diff sha256sum.txt sha256suma.txt
mv sha256suma.txt sha256sum.txt
````
People can now see the release tarballs on the website at
<https://www.coreboot.org/releases/>
The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
The downloads page is the official place to download the releases from,
and it needs to be updated with links to the new release tarballs and
.sig files. It can be found at:
<https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
Here is an example commit to change it:
<https://review.coreboot.org/c/homepage/+/19515>
Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
## Upload crossgcc sources
Sometimes the source files for older revisions of
@@ -219,24 +277,32 @@ sources used by the crossgcc scripts that are part of coreboot releases.
Run
````
% util/crossgcc/buildgcc -u
````bash
util/crossgcc/buildgcc -u
````
This will output the set of URLs that the script uses to download the
sources. Download them yourself and copy them into the crossgcc-sources
directory on the server.
## After the release is complete
Post the release notes on <https://blogs.coreboot.org>
Post the final release notes on <https://blogs.coreboot.org>
## Making a branch
At times we will need to create a branch, generally for patch fixes.
When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git cant tell whether you want the tag or the branch.
Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
When making a branch, do NOT name it the same as the release tag: X.Y -
this creates trouble when trying to check it out, as git cant tell
whether you want the tag or the branch. Instead, name it X.Y\_branch:
```bash
git checkout 4.8
git checkout -b 4.8_branch
git push origin 4.8_branch
```
You can then cherry-pick changes and push them up to the branch:
````
````bash
git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
git push origin HEAD:refs/for/4.8_branch
````

View File

@@ -296,6 +296,36 @@ noting, but not needing a full description.
* sandybridge & gm45: Support setting PCI bars above 4G
Plans to move platform support to a branch:
-------------------------------------------
After the 4.18 release in November 2022, we plan to move support for any
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
introduced more than a year ago and with minor changes most platforms
were able to work just fine with it. A major difference is that V3 uses
just one continuous region below 4G to allocate all PCI memory BAR's. V4
uses all available space below 4G and if asked to, also above 4G too.
This makes it important that SoC code properly reports all fixed
resources.
Currently only AGESA platforms have issues with it. On Gerrit both
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
inside the V4 allocator have been proposed, but both efforts seem
stalled. See the (not yet merged) documentation
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
details. It looks like properly reporting all fixed resources is the
issue.
At this point, we are not specifying which platforms this will include
as there are a number of patches to fix these issues in flight.
Hopefully, all platforms will end up being migrated to the V4 resource
allocator so that none of the platforms need to be supported on the
branch.
Additionally, even if the support for the platform is moved to a branch,
it can be brought back to ToT if they're fixed to support the V4
allocator.
Plans for Code Deprecation
--------------------------

View File

@@ -1,11 +1,11 @@
Upcoming release - coreboot 4.18 release
coreboot 4.18 release
========================================================================
The 4.18 release is quite late, but is now planned for October 16, 2022.
The 4.18 release was quite late, but was completed on October 16, 2022.
In the past 4 months since the 4.17 release, the coreboot project has
merged more than 1800 commits from over 200 different authors. Over 50
of those authors submitted their first patches.
In the 4 months since the 4.17 release, the coreboot project has merged
more than 1800 commits from over 200 different authors. Over 50 of those
authors submitted their first patches.
Welcome and thank you to all of our new contributors, and of course the
work of all of the seasoned contributors is greatly appreciated.
@@ -195,6 +195,36 @@ the same increases maintenance burden on the community a lot, while also
being rather confusing.
Plans to move platform support to a branch:
-------------------------------------------
After the 4.18 release in November 2022, we plan to move support for any
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
introduced more than a year ago and with minor changes most platforms
were able to work just fine with it. A major difference is that V3 uses
just one continuous region below 4G to allocate all PCI memory BAR's. V4
uses all available space below 4G and if asked to, also above 4G too.
This makes it important that SoC code properly reports all fixed
resources.
Currently only AGESA platforms have issues with it. On Gerrit both
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
inside the V4 allocator have been proposed, but both efforts seem
stalled. See the (not yet merged) documentation
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
details. It looks like properly reporting all fixed resources is the
issue.
At this point, we are not specifying which platforms this will include
as there are a number of patches to fix these issues in flight.
Hopefully, all platforms will end up being migrated to the v4 resource
allocator so that none of the platforms need to be supported on the
branch.
Additionally, even if the support for the platform is moved to a branch,
it can be brought back to ToT if they're fixed to support the v4
allocator.
### Intel Icelake SoC & Icelake RVP mainboard
Intel Icelake is unmaintained. Also, the only user of this platform ever
@@ -222,15 +252,37 @@ be maintained on the release 4.20 branch.
* Intel Galileo mainboard
Statistics
----------
Statistics from commit d2d9021543 to f4c97ea131
-----------------------------------------------
- Total Commits: 1819
- Average Commits per day: 13.44
- Total lines added: 150195
- Average lines added per commit: 82.57
- Number of patches adding more than 100 lines: 127
- Average lines added per small commit: 38.38
- Total lines removed: 33788
- Total Commits: 1822
- Average Commits per day: 13.38
- Total lines added: 150578
- Average lines added per commit: 82.64
- Number of patches adding more than 100 lines: 128
- Average lines added per small commit: 38.44
- Total lines removed: 33849
- Average lines removed per commit: 18.58
- Total difference between added and removed: 116407
- Total difference between added and removed: 116729
- Total authors: 202
- New authors: 52
Known Issues
------------
A couple of issues were discovered immediately following the release
that will be fixed in a follow-on point release in the upcoming weeks.
A pair of changes ([CB:67754](https://review.coreboot.org/67754) and
[CB:67662](https://review.coreboot.org/67662)) which merged shortly
before the 4.18 release have created an issue on Intel Apollo Lake
platform boards which prevents SMM/SMI from functioning; this affects
only Apollo Lake (but not Gemini Lake) devices.
See [CB:68599](https://review.coreboot.org/68599) for the fix.
Another issue applies to all Intel-based boards with onboard I2C TPMs
when verified boot is not enabled. The I2C buses dont get initialized
until after the TPM, causing timeouts, TPM initialization failures, and
long boot times. See [CB:68550](https://review.coreboot.org/68550) for
the fix.

View File

@@ -1,51 +1,187 @@
Upcoming release - coreboot 4.19
========================================================================
The 4.19 release is planned for January 2023.
The 4.19 release is planned for the 16th of January 2023.
Update this document with changes that should be in the release notes.
Since the last release, the coreboot project has merged over 1600
commits from over 150 authors. Of those authors, around 25 were
first-time committers to the coreboot project.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
As always, we are very grateful to all of the contributors for helping
to keep the project going. The coreboot project is different from many
open source projects in that we need to keep constantly updating the
codebase to stay relevant with the latest processors and technologies.
It takes constant effort to just stay afloat, let alone improve the
codebase. Thank you very much to everyone who has contributed, both in
this release and in previous times.
Significant changes
-------------------
The 4.20 release is planned for the 20th of April, 2023.
### Add significant changes here
Significant or interesting changes
----------------------------------
### Show all Kconfig options in saved config file; compress same
The coreboot build system automatically adds a 'config' file to CBFS
that lists the exact Kconfig configuration that the image was built
with. This is useful to reproduce a build after the fact or to check
whether support for a specific feature is enabled in the image.
This file has been generated using the 'savedefconfig' Kconfig command,
which generates the minimal .config file that is needed to produce the
required config in a coreboot build. This is fine for reproduction, but
bad when you want to check if a certain config was enabled, since many
options get enabled by default or pulled in through another option's
'select' statement and thus don't show up in the defconfig.
Instead coreboot now includes a larger .config instead. In order to save
some space, all of the comments disabling options are removed from the
file, except for those included in the defconfig.
We can also LZMA compress the file since it is never read by firmware
itself and only intended for later re-extraction via cbfstool, which
always has LZMA support included.
### Toolchain updates
* Upgrade LLVM from 15.0.0 to 15.0.6
* Upgrade CMake from 3.24.2 to 3.25.0
* Upgrade IASL from 20220331 to 20221020
* Upgrade MPFR from 4.1.0 to 4.1.1
### Finished the conversion to ASL 2.0 syntax
Until recently, coreboot still contained lots of code using the legacy
ASL syntax. However, all ASL code was ported over to make use of the ASL
2.0 syntax and from this point on new ASL code should make use of it.
Additional coreboot changes
---------------------------
* One or two line change comments go here
* Significant work was done to enable and build-test clang builds.
* Added touchscreen power sequencing and runtime detection.
* A number of patches were added to clean up and improve SMBIOS.
* Work is in progress to unify and extend coreboot post codes.
* Clean up for header includes is in progress with help from IWYU.
* IOAPIC code has been reworked.
* Support was added to superiotool for the NCT6687D-W chip.
* Work is progressing to switch return values to enum cb_err instead of
bool or other pass/fail indicators.
* Clang builds are now working for most boards and are being
build-tested.
* 64-bit coreboot support is in progress and is working on a number of
platforms.
* A driver for EC used on various Clevo laptops was added.
* Native Intel Lynxpoint code was added to replace the MRC.bin.
* Work continued for the process of adding ops structures to the
devicetree.
* The crossgcc tool can now download the source packages, which are
needed to build the coreboot toolchain, from coreboots own mirror if
desired.
* A document with useful external resources related to firmware
development was added at Documentation/external_docs.md.
New Mainboards
--------------
* AMD: Mayan for Phoenix SoC
* GIGABYTE: GA-H61M-DS2
* Google: Crystaldrift
* Google: Gladios
* Google: Dibbi
* Google: Gaelin
* Google: Marasov
* Google: Markarth
* Google: Omnigul
* Google: Voltorb
* Intel: Meteorlake-P RVP
* MSI: PRO Z690-A (WIFI)
* Siemens: MC_EHL3
* Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
* System76: darp8
* System76: galp6
Removed Mainboards
------------------
* AMD: Inagua
* AMD: Olive Hill
* AMD: Parmer
* AMD: Persimmon
* AMD: Southstation
* AMD: Thatcher
* AMD: Unionstation
* ASROCK: E350M1
* ASROCK: IMB-A180
* ASUS: A88XM-E
* ASUS: AM1I-A
* ASUS: F2A85-M
* ASUS: F2A85-M LE
* ASUS: F2A85-M PRO
* BAP: ODE_e20xx
* Biostar: A68N-5200
* Biostar: AM1ML
* ELMEX: pcm205400
* ELMEX: pcm205401
* GizmoSphere: Gizmo
* GizmoSphere: Gizmo2
* Google: Morthal
* HP: ABM
* HP: Pavilion m6 1035dx
* Jetway: NF81_T56N_LF
* Lenovo: AMD G505s
* LiPPERT: FrontRunner-AF aka ADLINK CoreModule2-GF
* LiPPERT: Toucan-AF aka cExpress-GFR (+W83627DHG SIO)
* MSI: MS-7721 (FM2-A75MA-E35)
* PC Engines: APU1
Updated SoCs
------------
* Added soc/amd/glinda
* Renamed soc/amd/morgana to soc/amd/phoenix
* Removed cpu/amd/agesa/family14
* Removed cpu/amd/agesa/family15tn
* Removed cpu/amd/agesa/family16kb
Updated Chipsets
----------------
* Removed northbridge/amd/agesa/family14
* Removed northbridge/amd/agesa/family15tn
* Removed northbridge/amd/agesa/family16kb
* Removed southbridge/amd/agesa/hudson
* Removed southbridge/amd/cimx/sb800
Payloads
--------
### Payload changes go here
* Updated GRUB from 2.04 to 2.06
* Updated SeaBIOS 1.16.0 to 1.16.1
Plans for Code Deprecation
--------------------------
Plans to move platform support to a branch
------------------------------------------
### Intel Icelake SoC & Icelake RVP mainboard
Intel Icelake is unmaintained. Also, the only user of this platform ever
was the Intel CRB (Customer Reference Board). From the looks of it the
code was never ready for production as only engineering sample CPUIDs
are supported. This reduces the maintanence overhead for the coreboot
project.
Intel Icelake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). From the looks of the
code, it was never ready for production as only engineering sample
CPUIDs are supported.
Intel Icelake code will be removed with release 4.19 and any maintenence
Intel Icelake code will be removed following 4.19 and any maintenance
will be done on the 4.19 branch. This consists of the Intel Icelake SoC
and Intel Icelake RVP mainboard.
@@ -53,12 +189,45 @@ and Intel Icelake RVP mainboard.
### Intel Quark SoC & Galileo mainboard
The SoC Intel Quark is unmaintained and different efforts to revive it
failed. Also, the only user of this platform ever was the Galileo
failed. Also, the only user of this platform ever was the Galileo
board.
Thus, to reduce the maintanence overhead for the community, support for
Thus, to reduce the maintenance overhead for the community, support for
the following components will be removed from the master branch and will
be maintained on the release 4.20 branch.
* Intel Quark SoC
* Intel Galileo mainboard
Statistics from the 4.18 to the 4.19 release
--------------------------------------------
- Total Commits: 1608
- Average Commits per day: 17.39
- Total lines added: 93786
- Average lines added per commit: 58.32
- Number of patches adding more than 100 lines: 80
- Average lines added per small commit: 38.54
- Total lines removed: 768014
- Total difference between added and removed: -674228
Significant Known and Open Issues
---------------------------------
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
| # | Subject |
|-----|-----------------------------------------------------------------|
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
| 448 | Thinkpad T440P ACPI Battery Value Issues |
| 446 | Optiplex 9010 No Post |
| 445 | Thinkpad X200 wifi issue |
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
| 427 | x200: Two battery charging issues |
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
| 412 | x230 reboots on suspend |
| 393 | T500 restarts rather than waking up from suspend |
| 350 | I225 PCIe device not detected on Harcuvar |
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |

View File

@@ -0,0 +1,67 @@
Upcoming release - coreboot 4.20
========================================================================
The 4.20 release is planned for the 20th of April 2023.
The 4.21 release is planned for around the 17th of July, 2023
Update this document with changes that should be in the release notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
* Note that all changes before the release are done are marked upcoming.
A final version of the notes are done after the release.
* This document may also be edited at the google doc copy:
https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
Significant or interesting changes
----------------------------------
### Add changes that need a full description here
Additional coreboot changes
---------------------------
The following are changes across a number of patches, or changes worth
noting, but not needing a full description.
* Changes that only need a line or two of description go here.
Plans to move platform support to a branch
------------------------------------------
### Intel Quark SoC & Galileo mainboard
The SoC Intel Quark is unmaintained and different efforts to revive it
have so far failed. The only user of this SoC ever was the Galileo
board.
Thus, to reduce the maintanence overhead for the community, support for
the following components will be removed from the master branch and will
be maintained on the release 4.20 branch.
* Intel Quark SoC
* Intel Galileo mainboard
Statistics from the 4.19 to the 4.20 release
--------------------------------------------
* To be filled in immediately before the release by the release team
Significant Known and Open Issues
---------------------------------
* To be filled in immediately before the release by the release team

View File

@@ -3,7 +3,7 @@
## Upcoming release
Please add to the release notes as changes are added:
* [4.19 - Jan 2023](coreboot-4.19-relnotes.md)
* [4.20 - April 2023](coreboot-4.20-relnotes.md)
The [checklist] contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
@@ -15,9 +15,10 @@ important is taken care of.
## Previous releases
* [4.18 - Oct 2022](coreboot-4.18-relnotes.md)
* [4.19 - January 2023](coreboot-4.19-relnotes.md)
* [4.18 - October 2022](coreboot-4.18-relnotes.md)
* [4.17 - May 2022](coreboot-4.17-relnotes.md)
* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
* [4.16 - February 2022](coreboot-4.16-relnotes.md)
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)

View File

@@ -1,9 +1,11 @@
# vboot-enabled devices
## AMD
- Birman
- Birman for Phoenix SoC
- Birman for Glinda SoC
- Chausie
- Majolica
- Mayan for Phoenix SoC
## Clevo
- N130WU / N131WU
@@ -64,16 +66,20 @@
- Joxer
- Pujjo
- Xivu
- Gaelin4ADL
- Gaelin
- Yaviks
- Lisbon
- Zydron
- Gladios
- Marasov
- Omnigul
- Butterfly (HP Pavilion Chromebook 14)
- Cherry
- Dojo
- Tomato
- Kingler
- Steelix
- Voltorb
- Krabby
- Tentacruel
- Magikarp
@@ -191,22 +197,6 @@
- Puff
- Scout
- Wyvern (CTL Chromebox CBx2)
- Banjo (Acer Chromebook 15 (CB3-531))
- Candy (Dell Chromebook 11 3120)
- Clapper (Lenovo N20 Chromebook)
- Enguarde
- Glimmer (Lenovo ThinkPad 11e Chromebook)
- Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735))
- Heli (Haier Chromebook G2)
- Kip (HP Chromebook 11 G3 / G4 / G4 EE)
- Ninja (AOpen Chromebox Commercial)
- Orco (Lenovo 100S Chromebook)
- Quawks (ASUS Chromebook C300)
- Squawks (ASUS Chromebook C200)
- Rambi
- Sumo (AOpen Chromebase Commercial)
- Swanky (Toshiba Chromebook 2)
- Winky (Samsung Chromebook 2 (XE500C12))
- Reef/Electro (Acer Chromebook Spin 11 R751T)
- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
- Sand (Acer Chromebook 15 CB515-1HT/1H)
@@ -217,8 +207,9 @@
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
- Skyrim
- Winterhold
- Morthal
- Frostflow
- Crystaldrift
- Markarth
- Falco (HP Chromebook 14)
- Leon (Toshiba Chromebook)
- Peppy (Acer C720/C720P Chromebook)
@@ -299,8 +290,6 @@
- Emerald Lake 2 CRB
- Galileo
- Glkrvp
- Icelake U DDR4/LPDDR4 RVP
- Icelake Y LPDDR4 RVP
- Jasperlake DDR4/LPDDR4 RVP
- Jasperlake DDR4/LPDDR4 RVP with Chrome EC
- Kabylake LPDDR3 RVP3
@@ -308,6 +297,8 @@
- Kabylake DDR4 RVP8
- Kabylake DDR4 RVP11
- Kunimitsu
- Meteorlake-P RVP
- Meteorlake-P RVP with Chrome EC
- shadowmountain
- Strago
- Tigerlake UP3 RVP
@@ -346,7 +337,8 @@
- ThinkPad X60 / X60s / X60t
## MSI
- PRO Z690-A WIFI DDR4
- PRO Z690-A (WIFI) DDR4
- PRO Z690-A (WIFI)
## OpenCellular
- Elgon (GBCv2)

View File

@@ -1,67 +0,0 @@
# Intel Ice Lake coreboot development
## Introduction
This document captures the coreboot development strategy for Intel SoC named Ice lake.
The Ice Lake processor family is the next generation Intel® Core processor family.
These processors are built using Intel's 10 nm+ process.
* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html)
## Development Strategy
Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
1. Intel develops initial Firmware code for Ice Lake SoC.
2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
```eval_rst
:doc:`../../../mainboard/intel/icelake_rvp`
```
### Summary:
* SoC is Ice Lake.
* Reference platform is icelake_rvp.
* OEM board is Dragonegg.
## Create coreboot Image
1. Clone latest coreboot code as below
```bash
$ git clone https://review.coreboot.org/coreboot.git
```
2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
Note:
Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
After product launch, FSP binary will be available externally as any other program.
3. Create coreboot .config
4. Build toolchain
```bash
CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl
```
5. Build image
```bash
$ make # the image is generated as build/coreboot.rom
```
## Flashing coreboot
Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
* Make use of dediprog while flashing coreboot image on Intel-RVP
* For Chromebook related platform like dragonegg, one can flash via servo:
```bash
$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
$ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
$ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
```
### References
* [flashrom](https://flashrom.org/Flashrom)
* [Servo](https://www.chromium.org/chromium-os/servo)

View File

@@ -1,7 +0,0 @@
# Intel Ice Lake SOC-specific documentation
This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
## Ice Lake coreboot development
- [Ice Lake coreboot development](iceLake_coreboot_development.md)

View File

@@ -7,7 +7,6 @@ This section contains documentation about coreboot on specific Intel SOCs.
- [Common code development strategy](code_development_model/code_development_model.md)
- [FSP](fsp/index.md)
- [Broadwell](broadwell/index.md)
- [Ice Lake/9th Gen Core-i series](icelake/index.md)
- [MP Initialization](mp_init/mp_init.md)
- [Microcode Updates](microcode.md)
- [Firmware Interface Table](fit.md)

View File

@@ -14,27 +14,17 @@ Please try to follow the guidelines below. This will make things
easier on the maintainers. Not all of these guidelines matter for every
trivial patch so apply some common sense.
1. Always _test_ your changes, however small, on at least 1 or
2 people, preferably many more.
2. Try to release a few ALPHA test versions to gerrit. Announce
them onto the coreboot mailing list and IRC channel and await
results. This is especially important on coreboot core changes,
but also for device drivers, because often that's the only way
you will find things like the fact revision 3 chipset needs
a magic fix you didn't know about, or some clown changed the
chips on a board and not its name. (Don't laugh!)
1. Make sure your changes compile correctly in multiple configurations. In
particular check that changes work for various boards in the tree that
it affects:
3. Make sure your changes compile correctly in multiple
configurations. In particular check that changes work for all
boards in the tree (use abuild!)
Test with: `util/abuild/abuild -c $(nproc) -t vendor/boardname`
4. When you are happy with a change make it generally available for
2. When you are happy with a change make it generally available for
testing in gerrit and await feedback.
5. Make your patch available through coreboot's gerrit code review
system, and add the relevant maintainer from this list as a code
reviewer. Be prepared to get your changes sent back with seemingly
3. Be prepared to get your changes sent back with seemingly
silly requests about formatting and variable names. These aren't
as silly as they seem. One job the maintainers do is to keep
things looking the same. Sometimes this means that the clever
@@ -45,36 +35,27 @@ trivial patch so apply some common sense.
(util/lint/checkpatch.pl) to catch trival style violations.
See https://www.coreboot.org/Coding_Style for guidance here.
PLEASE add the maintainers that are generated by
util/scripts/get_maintainer.pl as reviewers. The results returned
by the script will be best if you have git installed and are
making your changes in a branch derived from coreboot.org's latest
git tree.
PLEASE try to include any credit lines you want added with the
patch. It avoids people being missed off by mistake and makes
it easier to know who wants adding and who doesn't.
PLEASE document known bugs. If it doesn't work for everything
or does something very odd once a month document it.
PLEASE remember that submissions must be made under the terms
ALWAYS remember that submissions are made under the terms
of the OSDL certificate of contribution and should include a
Signed-off-by: line. The current version of this "Developer's
Certificate of Origin" (DCO) is listed at
https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
6. Make sure you have the right to send any changes you make. If you
4. Make sure you have the right to send any changes you make. If you
do changes at work you may find your employer owns the patch
not you.
7. Happy hacking.
5. Happy hacking.
Descriptions of section entries:
M: Maintainer: FullName <address@domain>
Must be registered to Gerrit (https://review.coreboot.org/).
Should have experience with upstream coreboot development.
Should have experience with upstream coreboot development and
+2 rights.
R: Designated reviewer: FullName <address@domain>
These reviewers should be CCed on patches.
L: Mailing list that is relevant to this area
@@ -137,6 +118,24 @@ Maintainers List (try to look for most precise areas first)
# Mainboards
################################################################################
51NB MAINBOARDS
S: Orphan
F: src/mainboard/51nb/
ACER MAINBOARDS
S: Orphan
F: src/mainboard/acer/
ADLINK MAINBOARDS
S: Orphan
F: src/mainboard/adlink/
AMD family 17h and 19h reference boards
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
@@ -144,11 +143,14 @@ M: Fred Reitberger <reitbergerfred@gmail.com>
L: amd_coreboot_org_changes@googlegroups.com
S: Maintained
F: src/mainboard/amd/bilby/
F: src/mainboard/amd/birman/
F: src/mainboard/amd/chausie/
F: src/mainboard/amd/majolica/
F: src/mainboard/amd/mandolin/
F: src/mainboard/amd/mayan/
AMD reference boards outside of family 17h and 19h
S: Odd Fixes
L: amd_coreboot_org_changes@googlegroups.com
F: src/mainboard/amd/gardenia/
F: src/mainboard/amd/inagua/
@@ -162,6 +164,12 @@ F: src/mainboard/amd/union_station/
AOPEN MAINBOARDS
S: Orphan
F: src/mainboard/aopen/
APPLE MAINBOARDS
M: Evgeny Zinoviev <me@ch1p.io>
S: Maintained
@@ -179,11 +187,6 @@ M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/asrock/g41c-gs/
ASROCK H81M-HDS MAINBOARD
M: Tristan Corrick <tristan@corrick.kiwi>
S: Maintained
F: src/mainboard/asrock/h81m-hds/
ASUS A88XM-E MAINBOARD
@@ -198,15 +201,9 @@ F: src/mainboard/asus/am1i-a/
ASUS H61 SERIES MAINBOARDS
M: Angel Pons <th3fanbus@gmail.com>
M: Tristan Corrick <tristan@corrick.kiwi>
S: Maintained
F: src/mainboard/asus/h61-series/
ASUS MAXIMUS IV GENE-Z MAINBOARD
M: Tristan Corrick <tristan@corrick.kiwi>
S: Maintained
F: src/mainboard/asus/maximus_iv_gene-z/
ASUS P5QC PRO MAINBOARD & VARIANTS
M: Angel Pons <th3fanbus@gmail.com>
R: Stefan Ott <coreboot@desire.ch>
@@ -226,6 +223,30 @@ F: src/mainboard/asus/p8z77-series/
BAP MAINBOARDS
S: Orphan
F: src/mainboard/bap/
BIOSTAR MAINBOARDS
S: Orphan
F: src/mainboard/biostar/
BOSTENTECH MAINBOARDS
S: Orphan
F: src/mainboard/bostentech/
CAVIUM MAINBOARDS
S: Orphan
F: src/mainboard/cavium/
CLEVO MAINBOARDS
M: Felix Singer <felixsinger@posteo.net>
M: Michael Niewöhner <foss@mniewoehner.de>
@@ -234,6 +255,36 @@ F: src/mainboard/clevo/
COMPULAB MAINBOARDS
S: Orphan
F: src/mainboard/compulab/
DELL MAINBOARDS
S: Orphan
F: src/mainboard/dell/
ELMEX MAINBOARDS
S: Orphan
F: src/mainboard/elmex/
EMULATION MAINBOARDS
S: Orphan
F: src/mainboard/emulation/
EXAMPLE MAINBOARDS
S: Orphan
F: src/mainboard/example/
FACEBOOK FBG1701 MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
@@ -248,21 +299,36 @@ F: src/mainboard/facebook/monolith/
FOXCONN MAINBOARDS
S: Orphan
F: src/mainboard/foxconn/
GETAC MAINBOARDS
S: Orphan
F: src/mainboard/getac/
GIGABYTE GA-D510UD MAINBOARD
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/gigabyte/ga-d510ud/
GIGABYTE GA-G41M-ES2L MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/gigabyte/ga-g41m-es2l/
GIGABYTE GA-H61M SERIES MAINBOARDS
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/gigabyte/ga-h61m-series/
GIZMOSPHERE MAINBOARDS
S: Orphan
F: src/mainboard/gizmosphere/
GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
@@ -280,11 +346,6 @@ M: Tarun Tuli <taruntuli@google.com>
S: Maintained
F: src/mainboard/google/hatch/
GOOGLE PANTHER MAINBOARD
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
S: Supported
F: src/mainboard/google/panther/
GOOGLE VOLTEER MAINBOARDS
M: Nick Vaccaro <nvaccaro@chromium.org>
S: Maintained
@@ -315,6 +376,7 @@ F: src/mainboard/google/guybrush/
F: src/mainboard/google/skyrim/
HP 280 G2 MAINBOARD
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
@@ -322,23 +384,23 @@ F: src/mainboard/hp/280_g2/
INTEL D510MO MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/intel/d510mo/
IBASE MAINBOARDS
S: Orphan
F: src/mainboard/ibase/
INTEL HARCUVAR_CRB MAINBOARD
M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/mainboard/intel/harcuvar/
INTEL STRAGO MAINBOARD
M: Hannah Williams <hannah.williams@intel.com>
S: Supported
F: /src/mainboard/intel/strago/
JETWAY MAINBOARDS
S: Orphan
F: src/mainboard/jetway/
@@ -378,6 +440,7 @@ S: Maintained
F: src/mainboard/lenovo/x201/
LIBRETREND LT1000 MAINBOARD
M: Piotr Król <piotr.krol@3mdeb.com>
M: Michał Żygowski <michal.zygowski@3mdeb.com>
@@ -386,6 +449,12 @@ F: src/mainboard/libretrend/lt1000/
LIPPERT MAINBOARDS (acquired by Adlink)
S: Orphan
F: src/mainboard/lippert/
MSI H81M-P33 MAINBOARD
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
@@ -397,6 +466,8 @@ M: Michał Kopeć <michal.kopec@3mdeb.com>
S: Maintained
F: src/mainboard/msi/ms7d25/
OCP DELTALAKE MAINBOARD
M: Arthur Heymans <arthur@aheymans.xyz>
M: Christian Walter <christian.walter@9elements.com>
@@ -408,7 +479,6 @@ F: src/mainboard/ocp/deltalake/
OCP TIOGAPASS MAINBOARD
M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
@@ -434,6 +504,12 @@ F: src/mainboard/pcengines/
PINE64 MAINBOARDS
S: Orphan
F: src/mainboard/pine64/
PORTWELL PQ-M107 MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Erik van den Bogaert <ebogaert@eltan.com>
@@ -472,6 +548,18 @@ F: src/mainboard/purism/
RAZER MAINBOARDS
S: Orphan
F: src/mainboard/razer/
RODA MAINBOARDS
S: Orphan
F: src/mainboard/roda/
SAMSUNG CHROMEOS MAINBOARDS
M: Matt DeVillier <MrChromebox@gmail.com>
S: Maintained
@@ -480,6 +568,18 @@ F: src/mainboard/samsung/stumpy/
SAPPHIRE MAINBOARDS
S: Orphan
F: src/mainboard/sapphire/
SCALEWAY MAINBOARDS
S: Orphan
F: src/mainboard/scaleway/
SIEMENS CHILI MAINBAORD
M: Felix Singer <felixsinger@posteo.net>
M: Nico Huber <nico.h@gmx.de>
@@ -494,6 +594,12 @@ F: src/mainboard/siemens/mc_ehl/
SIFIVE MAINBOARDS
S: Orphan
F: src/mainboard/sifive/
STAR LABS MAINBOARDS
M: Sean Rhodes <sean@starlabs.systems>
S: Maintained
@@ -501,6 +607,13 @@ F: src/mainboard/starlabs/
SUPERMICRO X11-LGA1151-SERIES
M: Michael Niewöhner <foss@mniewoehner.de>
S: Maintained
F: src/mainboard/supermicro/x11-lga1151-series/
SYSTEM76 MAINBOARDS
M: Jeremy Soller <jeremy@system76.com>
M: Tim Crawford <tcrawford@system76.com>
@@ -509,15 +622,15 @@ F: src/mainboard/system76/
SUPERMICRO X10SLM+-F MAINBOARD
M: Tristan Corrick <tristan@corrick.kiwi>
S: Maintained
F: src/mainboard/supermicro/x10slm-f/
TI MAINBOARDS
S: Orphan
F: src/mainboard/ti/
SUPERMICRO X11-LGA1151-SERIES
M: Michael Niewöhner <foss@mniewoehner.de>
S: Maintained
F: src/mainboard/supermicro/x11-lga1151-series/
UP MAINBOARDS
S: Orphan
F: src/mainboard/up/
################################################################################
# Architectures
@@ -553,6 +666,7 @@ F: src/mainboard/sifive/
F: util/riscv/
X86 ARCHITECTURE
S: MAINTAINED
F: src/arch/x86/
F: src/cpu/x86/
F: src/drivers/pc80/
@@ -567,7 +681,7 @@ CHROME EC
M: Boris Mittelberg <bmbm@google.com>
M: Caveh Jalali <caveh@chromium.org>
S: Maintained
F: src/ec/google/chromeec/
F: src/ec/google/
LENOVO EC
M: Alexander Couzens <lynxis@fe80.eu>
@@ -585,6 +699,19 @@ M: Tim Crawford <tcrawford@system76.com>
S: Maintained
F: src/ec/system76/
ORPHANED ECS
S: Orphan
F: src/ec/51nb/
F: src/ec/acpi/
F: src/ec/apple/
F: src/ec/compal/
F: src/ec/hp/
F: src/ec/kontron/
F: src/ec/purism/
F: src/ec/quanta/
F: src/ec/roda/
F: src/ec/smsc/
################################################################################
# Northbridges
################################################################################
@@ -595,7 +722,6 @@ S: Maintained
F: src/northbridge/intel/haswell/
INTEL PINEVIEW CHIPSET
M: Damien Zammit <damien@zamaudio.com>
M: Angel Pons <th3fanbus@gmail.com>
S: Odd Fixes
F: src/northbridge/intel/pineview/
@@ -606,7 +732,6 @@ S: Maintained
F: src/northbridge/intel/sandybridge/
INTEL X4X CHIPSET
M: Damien Zammit <damien@zamaudio.com>
M: Angel Pons <th3fanbus@gmail.com>
S: Odd Fixes
F: src/northbridge/intel/x4x/
@@ -617,6 +742,7 @@ F: src/northbridge/intel/x4x/
AMD SUPPORT
L: amd_coreboot_org_changes@googlegroups.com
S: Odd Fixes
F: src/vendorcode/amd/
F: src/cpu/amd/
F: src/northbridge/amd/
@@ -634,9 +760,7 @@ F: src/drivers/intel/
F: src/include/cpu/intel/
INTEL FSP 1.1
M: Lee Leahy <leroy.p.leahy@intel.com>
M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported
F: src/drivers/intel/fsp1_1/
@@ -691,6 +815,16 @@ S: Supported
F: src/soc/amd/mendocino/
F: src/vendorcode/amd/fsp/mendocino/
AMD Phoenix
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
L: amd_coreboot_org_changes@googlegroups.com
S: Supported
F: src/soc/amd/phoenix/
F: src/vendorcode/amd/fsp/phoenix/
AMD Stoneyridge
M: Felix Held <felix-coreboot@felixheld.de>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
@@ -712,8 +846,8 @@ S: Maintained
F: src/soc/intel/alderlake/
INTEL APOLLOLAKE_SOC
M: Andrey Petrov <andrey.petrov@gmail.com>
S: Maintained
M: Sean Rhodes <sean@starlabs.systems>
S: Odd Fixes
F: src/soc/intel/apollolake/
INTEL BRASWELL SOC
@@ -727,8 +861,6 @@ F: /src/vendorcode/intel/fsp/fsp1_1/braswell/
INTEL DENVERTON-NS SOC
M: Jeff Daly <jeffd@silicom-usa.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/soc/intel/denverton_ns/
@@ -746,7 +878,6 @@ F: src/soc/intel/tigerlake/
INTEL Xeon Sacalable Processor Family
M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Tim Chu <Tim.Chu@quantatw.com>
M: Arthur Heymans <arthur@aheymans.xyz>
@@ -768,7 +899,7 @@ F: src/soc/mediatek/mt8192/
F: src/vendorcode/mediatek/mt8192/
ORPHANED ARM SOCS
S: Orphaned
S: Orphan
F: src/cpu/armltd/
F: src/soc/ti/
F: src/soc/qualcomm/
@@ -825,6 +956,10 @@ F: util/xcompile/
F: util/genbuild_h/
TOOLCHAIN
M: Martin Roth <gaumless@gmail.com>
M: Felix Singer <felixsinger@posteo.net>
M: Elyes Haouas <ehaouas@noos.fr>
S: Supported
F: util/crossgcc/
DOCKER
@@ -976,6 +1111,16 @@ S: Maintained
F: tests/
F: payloads/libpayload/tests/
COREBOOT RELEASES
M: Felix Singer <felixsinger@posteo.net>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Angel Pons <th3fanbus@gmail.com>
M: Martin Roth <gaumless@gmail.com>
M: Matt DeVillier <MrChromebox@gmail.com>
S: Maintained
F: Documentation/releases/
F: util/release/
MISSING: TIMERS / DELAYS
MISSING: TIMESTAMPS
@@ -1012,7 +1157,7 @@ MISSING: SPI
CODE OF CONDUCT
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Ronald Minnich <rminnich@coreboot.org>
M: Ronald Minnich <rminnich@gmail.com>
M: Martin Roth <martin@coreboot.org>
S: Maintained
F: Documentation/community/code_of_conduct.md

View File

@@ -38,6 +38,11 @@ COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
# Make does not offer a recursive wildcard function, so here's one:
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
SYMLINK_LIST = $(call rwildcard,site-local/,symlink.txt)
# directory containing the toplevel Makefile.inc
TOPLEVEL := .
@@ -64,6 +69,9 @@ endif
HOSTCFLAGS := -g
HOSTCXXFLAGS := -g
HOSTPKG_CONFIG ?= pkg-config
COREBOOT_EXPORTS += HOSTPKG_CONFIG
PREPROCESS_ONLY := -E -P -x assembler-with-cpp -undef -I .
export $(COREBOOT_EXPORTS)
@@ -143,13 +151,14 @@ include $(TOPLEVEL)/payloads/Makefile.inc
include $(TOPLEVEL)/util/testing/Makefile.inc
-include $(TOPLEVEL)/site-local/Makefile.inc
include $(TOPLEVEL)/tests/Makefile.inc
real-all:
printall real-all:
@echo "Error: Trying to build, but NOCOMPILE is set." >&2
@echo " Please file a bug with the following information:"
@echo "- MAKECMDGOALS: $(MAKECMDGOALS)" >&2
@echo "- HAVE_DOTCONFIG: $(HAVE_DOTCONFIG)" >&2
@echo "- HAVE_KCONFIG_MAKEFILE_REAL: $(HAVE_KCONFIG_MAKEFILE_REAL)" >&2
@exit 1
else
ifneq ($(UNIT_TEST),1)
@@ -307,6 +316,9 @@ $(eval $(postinclude-hooks))
$(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
# Build Kconfig .ads if necessary
ifeq ($(CONFIG_ROMSTAGE_ADA),y)
romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
endif
ifeq ($(CONFIG_RAMSTAGE_ADA),y)
ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS))
endif
@@ -455,6 +467,29 @@ sphinx:
sphinx-lint:
$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
symlink:
@echo "Creating Symbolic Links.."; \
for link in $(SYMLINK_LIST); do \
SYMLINK=`cat $$link`; \
REALPATH=`realpath $$link`; \
if [ -L "$$SYMLINK" ]; then \
continue; \
elif [ ! -e "$$SYMLINK" ]; then \
echo -e "\tLINK $$SYMLINK -> $$(dirname $$REALPATH)"; \
ln -s $$(dirname $$REALPATH) $$SYMLINK; \
else \
echo -e "\tFAILED: $$SYMLINK exists"; \
fi \
done
clean-symlink:
@echo "Deleting symbolic link";\
EXISTING_SYMLINKS=`find -L ./src -xtype l | grep -v 3rdparty`; \
for link in $$EXISTING_SYMLINKS; do \
echo -e "\tUNLINK $$link"; \
rm "$$link"; \
done
clean-for-update:
rm -rf $(obj) .xcompile
@@ -482,4 +517,4 @@ distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
rm -f abuild*.xml junit.xml* util/lint/junit.xml
.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean sphinx sphinx-lint
.PHONY: ctags-project cscope-project clean-ctags
.PHONY: ctags-project cscope-project clean-ctags symlink clean-symlink

View File

@@ -80,6 +80,7 @@ PHONY+= clean-abuild coreboot check-style build_complete
#######################################################################
# root source directories of coreboot
subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
subdirs-y += $(wildcard src/northbridge/*/*)
@@ -265,26 +266,9 @@ endef
# ResourceTemplate is the correct code.
# As it's valid ASL, disable the warning.
EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
# 1) If _PRS is present, must have _CRS and _SRS
# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
# 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
# 4) If _SRS is present, probably should have a _DIS (Remark only)
# A warning will be issued for each of these cases.
# For existing ASL code, ignore this warnings
IASL_MISSING_DEPENDENCY = 3141
IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING)
ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
build_complete::
printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n"
printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
endif
IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
define asl_template
@@ -322,18 +306,20 @@ cbfs-files-processor-nvramtool= \
mv $(2).tmp $(2))
#######################################################################
# Reduce a .config file to its minimal representation
# Reduce a .config file by removing lines about default unset booleans
# arg1: input
# arg2: output
define cbfs-files-processor-defconfig
$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
define cbfs-files-processor-config
$(eval $(2): $(1) $(obj)/build.h; \
+printf " CREATE $(2) (from $(1))\n"; \
printf "# This image was built using coreboot " > $(2).tmp && \
grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
$(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \
cat $(2).tmp2 >> $(2).tmp && \
printf "# End of defconfig. Derivable values start here.\n" >> $(2).tmp && \
grep "^CONFIG" $(1) | grep -F -v -f $(2).tmp2 >> $(2).tmp && \
rm -f $(2).tmp2 && \
\mv -f $(2).tmp $(2))
mv -f $(2).tmp $(2))
endef
#######################################################################
@@ -386,9 +372,12 @@ cbfs-files-handler= \
#######################################################################
# a variety of flags for our build
CBFS_COMPRESS_FLAG:=none
ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y)
ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y)
CBFS_COMPRESS_FLAG:=LZMA
endif
ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZ4),y)
CBFS_COMPRESS_FLAG:=LZ4
endif
CBFS_PAYLOAD_COMPRESS_FLAG:=none
ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
@@ -433,7 +422,7 @@ endif
CFLAGS_common += -pipe -g -nostdinc -std=gnu11
CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
CFLAGS_common += -Wdangling-else
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
@@ -600,6 +589,7 @@ BINCFG:=$(objutil)/bincfg/bincfg
IFDTOOL:=$(objutil)/ifdtool/ifdtool
AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
AMDFWREAD:=$(objutil)/amdfwtool/amdfwread
APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
@@ -701,7 +691,7 @@ install-git-commit-clangfmt:
include util/crossgcc/Makefile.inc
.PHONY: tools
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER)
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD)
###########################################################################
# Common recipes for all stages
@@ -1228,8 +1218,9 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
vgaroms/seavgabios.bin-type := raw
cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config
config-file := $(DOTCONFIG):defconfig
config-file := $(DOTCONFIG):config
config-type := raw
config-compression := LZMA
cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision
revision-file := $(obj)/build.h

209
README.md
View File

@@ -1,21 +1,41 @@
coreboot README
===============
coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers. coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.
coreboot is a Free Software project aimed at replacing the proprietary
firmware (BIOS/UEFI) found in most computers. coreboot performs the
required hardware initialization to configure the system, then passes
control to a different executable, referred to in coreboot as the
payload. Most often, the primary function of the payload is to boot the
operating system (OS).
With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.
coreboot is perfect for a wide variety of situations. It can be used
for specialized applications that run directly in the firmware, running
operating systems from flash, loading custom bootloaders, or
implementing firmware standards, like PC BIOS services or UEFI. This
flexibility allows coreboot systems to include only the features
necessary in the target application, reducing the amount of code and
flash space required.
coreboot was formerly known as LinuxBIOS.
Source code
-----------
All source code for coreboot is stored in git. It is downloaded with
the command:
`git clone https://review.coreboot.org/coreboot.git`.
Code reviews are done in [the project's Gerrit
instance](https://review.coreboot.org/).
The code may be browsed via [coreboot's Gitiles
instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master).
The coreboot project also maintains a
[mirror](https://github.com/coreboot/coreboot) of the project on github.
This is read-only, as coreboot does not accept github pull requests,
but allows browsing and downloading the coreboot source.
Payloads
--------
@@ -23,81 +43,156 @@ Payloads
After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.
See <https://www.coreboot.org/Payloads> for a list of supported payloads.
See <https://doc.coreboot.org/payloads.html> for a list of some of
coreboot's supported payloads.
Supported Hardware
------------------
coreboot supports a wide range of chipsets, devices, and mainboards.
The coreboot project supports a wide range of architectures, chipsets,
devices, and mainboards. While not all of these are documented, you can
find some information in the [Architecture-specific
documentation](https://doc.coreboot.org/arch/index.html) or the
[SOC-specific documentation](https://doc.coreboot.org/soc/index.html).
For details please consult:
* <https://www.coreboot.org/Supported_Motherboards>
For details about the specific mainboard devices that coreboot supports,
please consult the [Mainboard-specific
documentation](https://doc.coreboot.org/mainboard/index.html) or the
[Board Status](https://coreboot.org/status/board-status.html) pages.
Build Requirements
------------------
Releases
--------
* make
* gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
`ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this
case).
* iasl (for targets with ACPI support)
* pkg-config
* libssl-dev (openssl)
Releases are currently done by coreboot every quarter. The
release archives contain the entire coreboot codebase from the time of
the release, along with any external submodules. The submodules
containing binaries are separated from the general release archives. All
of the packages required to build the coreboot toolchains are also kept
at coreboot.org in case the websites change, or those specific packages
become unavailable in the future.
Optional:
All releases are available on the [coreboot
download](https://coreboot.org/downloads.html) page.
* gdb (for better debugging facilities on some targets)
* ncurses (for `make menuconfig` and `make nconfig`)
* flex and bison (for regenerating parsers)
Please note that the coreboot releases are best considered as snapshots
of the codebase, and do not currently guarantee any sort of extra
stability.
Build Requirements and building coreboot
----------------------------------------
Building coreboot
-----------------
The coreboot build, associated utilities and payloads require many
additional tools and packages to build. The actual coreboot binary is
typically built using a coreboot-controlled toolchain to provide
reproducibility across various platforms. It is also possible, though
not recommended, to make it directly with your system toolchain.
Operating systems and distributions come with an unknown variety of
system tools and utilities installed. Because of this, it isn't
reasonable to list all the required packages to do a build, but the
documentation lists the requirements for a few different Linux
distributions.
Please consult <https://www.coreboot.org/Build_HOWTO> for details.
To see the list of tools and libraries, along with a list of
instructions to get started building coreboot, go to the [Starting from
scratch](https://doc.coreboot.org/tutorial/part1.html) tutorial page.
Testing coreboot Without Modifying Your Hardware
------------------------------------------------
If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.
Please see <https://www.coreboot.org/QEMU> for details.
That same page goes through how to use QEMU to boot the build and see
the output.
Website and Mailing List
------------------------
Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:
Further details on the project, as well as links to documentation and
more can be found on the coreboot website:
<https://www.coreboot.org>
You can contact us directly on the coreboot mailing list:
<https://www.coreboot.org/Mailinglist>
<https://doc.coreboot.org/community/forums.html>
Copyright and License
Copyrights and Licenses
---------------------
### Uncopyrightable files
There are many files in the coreboot tree that we feel are not
copyrightable due to a lack of creative content.
"In order to qualify for copyright protection in the United States, a
work must satisfy the originality requirement, which has two parts. The
work must have “at least a modicum” of creativity, and it must be the
independent creation of its author."
<https://guides.lib.umich.edu/copyrightbasics/copyrightability>
Similar terms apply to other locations.
These uncopyrightable files include:
- Empty files or files with only a comment explaining their existence.
These may be required to exist as part of the build process but are
not needed for the particular project.
- Configuration files either in binary or text form. Examples would be
files such as .vbt files describing graphics configuration, spd files
as binary .spd or text \*spd\*.hex representing memory chip
configuration.
- Machine-generated files containing version numbers, dates, hash
values or other "non-creative" content.
As non-creative content, these files are in the public domain by
default. As such, the coreboot project excludes them from the project's
general license even though they may be included in a final binary.
If there are questions or concerns about this policy, please get in
touch with the coreboot project via the mailing list.
### Copyrights
The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.
developers and companies. A list of companies and individuals with known
copyright claims is present at the top level of the coreboot source tree
in the 'AUTHORS' file. Please check the git history of each of the
source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.
### Licenses
Because of the way coreboot began, using a significant amount of source
code from the Linux kernel, it's licensed the same way as the Linux
Kernel, with GNU General Public License (GPL) Version 2. Individual
files are licensed under various licenses, though all are compatible
with GPLv2. The resulting coreboot image is licensed under the GPL,
version 2. All source files should have an SPDX license identifier at
the top for clarification.
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms.
As an exception, files under Documentation/ with a history older than
2017-05-24 might be under different licenses.
Files in the coreboot/src/commonlib/bsd directory are all licensed with
the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or
GPL-2.0-or-later. These files are intended to be shared with libpayload
or other BSD licensed projects.
The libpayload project contained in coreboot/payloads/libpayload may be
licensed as BSD or GPL, depending on the code pulled in during the build
process. All GPL source code should be excluded unless the Kconfig
option to include it is set.
The Software Freedom Conservancy
--------------------------------
Since 2017, coreboot has been a member of [The Software Freedom
Conservancy](https://sfconservancy.org/), a nonprofit organization
devoted to ethical technology and driving initiatives to make technology
more inclusive. The conservancy acts as coreboot's fiscal sponsor and
legal advisor.

View File

@@ -0,0 +1,5 @@
# Configuration used to build-test native raminit
CONFIG_VENDOR_ASROCK=y
CONFIG_BOARD_ASROCK_B85M_PRO4=y
CONFIG_USE_NATIVE_RAMINIT=y
CONFIG_DEBUG_RAM_SETUP=y

View File

@@ -0,0 +1,29 @@
CONFIG_USE_AMD_BLOBS=y
CONFIG_VENDOR_GOOGLE=y
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_AMD_FWM_POSITION_INDEX=4
CONFIG_VBOOT=y
CONFIG_VBOOT_SLOTS_RW_A=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_BOARD_GOOGLE_SKYRIM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000
CONFIG_VBOOT_FWID_MODEL="Google_$(CONFIG_MAINBOARD_PART_NUMBER)"
# CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK is not set
CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_ASYNC_FILE_LOADING=y
# CONFIG_ACPI_BERT is not set
# CONFIG_ACPI_SSDT_PSD_INDEPENDENT is not set
CONFIG_AMD_STB_SIZE_IN_MB=3
CONFIG_NO_GFX_INIT=y
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_VPD=y
CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50
CONFIG_GBB_FLAG_DEV_SCREEN_SHORT_DELAY=y
CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
CONFIG_VBOOT_KEYBLOCK_VERSION=1
CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_POST_IO_PORT=0x80
CONFIG_SEABIOS_DEBUG_LEVEL=-1

View File

@@ -0,0 +1,31 @@
CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_USE_AMD_BLOBS=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_VGA_BIOS_ID="1002,1506"
CONFIG_AMD_FWM_POSITION_INDEX=3
CONFIG_VGA_BIOS=y
CONFIG_CONSOLE_POST=y
CONFIG_BOARD_GOOGLE_SKYRIM=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin"
CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin"
CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
CONFIG_ASYNC_FILE_LOADING=y
CONFIG_PSP_SOFTFUSE_BITS="34 28"
CONFIG_UART_PCI_ADDR=0x0
CONFIG_RUN_FSP_GOP=y
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_DISPLAY_HOBS=y
CONFIG_DISPLAY_UPD_DATA=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_NONE=y
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_FATAL_ASSERTS=y
CONFIG_DEBUG_SMI=y
CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y
CONFIG_ADD_POSTCODES_TO_STB=y

View File

@@ -0,0 +1,3 @@
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_VILBOZ=y
CONFIG_USE_EXP_X86_64_SUPPORT=y

View File

@@ -4,7 +4,6 @@ CONFIG_CBFS_SIZE=0x800000
CONFIG_BOARD_INTEL_HARCUVAR=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_ENABLE_HSUART=y
CONFIG_UART_PCI_ADDR=0x8000d000
#Sample settings for Denverton-NS FSP.
#CONFIG_ADD_FSP_BINARIES=y

View File

@@ -10,3 +10,4 @@ CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_SPI_FLASH=y
CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y
CONFIG_USE_EXP_X86_64_SUPPORT=y

View File

@@ -0,0 +1,21 @@
CONFIG_VENDOR_MSI=y
CONFIG_CBFS_SIZE=0x1000000
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EDK2_BOOT_TIMEOUT=3
CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_POST_DEVICE_PCI_PCIE=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git"
CONFIG_EDK2_TAG_OR_REV="origin/dasharo"
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
CONFIG_EDK2_SD_MMC_TIMEOUT=1000
CONFIG_TPM2=y
CONFIG_TPM_MEASURED_BOOT=y
CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
CONFIG_DRIVERS_GENERIC_CBFS_UUID=y

View File

@@ -13,3 +13,4 @@ CONFIG_POST_DEVICE_LPC=y
CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
CONFIG_RUN_FSP_GOP=y

View File

@@ -0,0 +1,17 @@
# Settings used by Prodrive to build coreboot for the Hermes but with x86_64 enabled
CONFIG_VENDOR_PRODRIVE=y
CONFIG_BOARD_PRODRIVE_HERMES=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Technologies B.V."
CONFIG_POST_IO=y
CONFIG_USE_LEGACY_8254_TIMER=y
CONFIG_HERMES_USES_SPS_FIRMWARE=y
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_SMMSTORE=y
CONFIG_SMMSTORE_V2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
CONFIG_POST_DEVICE_LPC=y
CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
CONFIG_RUN_FSP_GOP=y
CONFIG_USE_EXP_X86_64_SUPPORT=y

View File

@@ -1,15 +1,8 @@
menu "Payload"
config NO_DEFAULT_PAYLOAD
bool
choice
prompt "Add a payload"
default PAYLOAD_NONE if NO_DEFAULT_PAYLOAD || !ARCH_X86
default PAYLOAD_SEABIOS if ARCH_X86
config PAYLOAD_NONE
bool "None"
bool "Don't add a payload"
default y if !ARCH_X86
help
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
@@ -18,6 +11,11 @@ config PAYLOAD_NONE
For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.
if !PAYLOAD_NONE
choice
prompt "Payload to add"
default PAYLOAD_SEABIOS if ARCH_X86
config PAYLOAD_ELF
bool "An ELF executable payload"
help
@@ -58,7 +56,7 @@ choice
prompt "Payload compression algorithm"
default COMPRESSED_PAYLOAD_LZMA
default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT
depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
depends on !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
help
Choose the compression algorithm for the chosen payloads.
You can choose between None, LZMA, or LZ4.
@@ -178,4 +176,7 @@ config COREDOOM_SECONDARY_PAYLOAD
source "payloads/external/*/Kconfig.secondary"
endmenu # "Secondary Payloads"
endif # !PAYLOAD_NONE
endmenu

View File

@@ -6,4 +6,4 @@ config PAYLOAD_FILO
with a FILO payload. If you don't know what this is
about, just leave it enabled.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -15,7 +15,7 @@ choice
default GRUB2_STABLE
config GRUB2_STABLE
bool "2.04"
bool "2.06"
help
Stable GRUB2 version

View File

@@ -7,7 +7,7 @@ config PAYLOAD_GRUB2
with a GRUB2 payload. If you don't know what this is
about, just leave it enabled.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.
config PAYLOAD_SEAGRUB
bool "GRUB2 atop SeaBIOS"
@@ -19,4 +19,4 @@ config PAYLOAD_SEAGRUB
with a GRUB2 payload running atop SeaBIOS to improve its
hardware compatibility.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -1,9 +1,9 @@
TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD
TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.06
NAME-$(CONFIG_GRUB2_MASTER)=HEAD
NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
NAME-$(CONFIG_GRUB2_STABLE)=2.04
NAME-$(CONFIG_GRUB2_STABLE)=2.06
project_git_repo=https://git.savannah.gnu.org/git/grub.git/
project_dir=grub2
@@ -34,7 +34,7 @@ grub2/build/config.h: $(CONFIG_DEP) | checkout
cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \
FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \
TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \
CFLAGS=-O2 TARGET_CFLAGS=-Os \
CFLAGS=-O2 TARGET_CFLAGS="-Os -fno-reorder-functions" \
--with-platform=coreboot --enable-boot-time --disable-werror
config: grub2/build/config.h checkout

View File

@@ -8,4 +8,4 @@ config PAYLOAD_LINUXBOOT
with a LinuxBoot payload. If you don't know what this is
about, just leave it enabled.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -45,6 +45,8 @@ else ifeq ($(findstring x4.,x$(kernel_version)),x4.)
kernel_mirror_path := $(kernel_mirror)/v4.x
else ifeq ($(findstring x5.,x$(kernel_version)),x5.)
kernel_mirror_path := $(kernel_mirror)/v5.x
else ifeq ($(findstring x6.,x$(kernel_version)),x6.)
kernel_mirror_path := $(kernel_mirror)/v6.x
endif
all: kernel

View File

@@ -164,6 +164,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
@@ -182,6 +183,48 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
GCC_CC_arm64=$(GCC_CC_arm64) \
OBJCOPY_x86_32=$(OBJCOPY_x86_32) \
OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
OBJCOPY_arm=$(OBJCOPY_arm) \
OBJCOPY_arm64=$(OBJCOPY_arm64) \
MFLAGS= MAKEFLAGS=
$(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
$(MAKE) -C payloads/external/edk2 UniversalPayload \
HOSTCC="$(HOSTCC)" \
CC="$(HOSTCC)" \
CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \
CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \
CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \
CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \
CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \
CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \
CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \

View File

@@ -15,7 +15,7 @@ choice
default SEABIOS_STABLE
config SEABIOS_STABLE
bool "1.16.0"
bool "1.16.1"
help
Stable SeaBIOS version
config SEABIOS_MASTER

View File

@@ -7,4 +7,4 @@ config PAYLOAD_SEABIOS
with a SeaBIOS payload. If you don't know what this is
about, just leave it enabled.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=d239552ce7220e448ae81f41515138f7b9e3c4db
TAG-$(CONFIG_SEABIOS_STABLE)=3208b098f51a9ef96d0dfa71d5ec3a3eaec88f0a
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
project_git_repo=https://review.coreboot.org/seabios.git

View File

@@ -5,6 +5,6 @@ config PAYLOAD_UBOOT
Select this option if you want to build a coreboot image
with a U-Boot payload.
See https://coreboot.org/Payloads and U-Boot's documentation
See https://doc.coreboot.org/payloads.html and U-Boot's documentation
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
for more information.

View File

@@ -5,4 +5,4 @@ config PAYLOAD_DEPTHCHARGE
Select this option if you want to build a coreboot image
with a depthcharge payload.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -155,6 +155,20 @@ config EDK2_CBMEM_LOGGING
this option, especially if using a debug (vs release) build.
Selecting this option will increase the payload size in CBFS by 0x10000.
config EDK2_CPU_TIMER_LIB
bool
default n
help
For recent Intel and AMD CPUs, the 0x15 CPUID instruction will return Time
Stamp Counter Frequence. For CPUs that do not support this instruction,
EDK2 must include a different library which is the reason why this must be
configured at build time.
If this is enabled, and the CPU doesn't support 0x15, it will fail to
boot. If it is not enabled, and the CPU does support 0x15, it will still
boot but without support for the leaf. Consequently, it is disabled by
default.
config EDK2_FOLLOW_BGRT_SPEC
bool "Center logo 38.2% from the top of screen"
default n

View File

@@ -6,4 +6,4 @@ config PAYLOAD_EDK2
with a edk2 payload. If you don't know what this is
about, just leave it enabled.
See https://coreboot.org/Payloads for more information.
See https://doc.coreboot.org/payloads.html for more information.

View File

@@ -8,6 +8,8 @@ export WORKSPACE := $(CURDIR)/workspace
export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
export PACKAGES_PATH := $(EDK2_PATH)
OBJCOPY = $(GCC_PREFIX)objcopy
ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc
endif
@@ -44,6 +46,12 @@ RELEASE_STR = DEBUG
else
RELEASE_STR = RELEASE
endif
# CPU_TIMER_LIB_ENABLE = TRUE
ifneq ($(CONFIG_EDK2_CPU_TIMER_LIB),y)
BUILD_STR += -D CPU_TIMER_LIB_ENABLE=FALSE
else
BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency=$(CONFIG_CPU_XTAL_HZ)
endif
# DISABLE_SERIAL_TERMINAL = FALSE
ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
@@ -229,10 +237,14 @@ UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/
mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \
../../../build/UEFIPAYLOAD.fd
UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll
mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \
../../../build/ShimmedUniversalPayload.elf
clean:
test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
distclean:
rm -rf $(WORKSPACE)
.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg clean distclean
.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean

View File

@@ -93,7 +93,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
media->context = (void*)romsize;
#if CONFIG(LP_ROM_SIZE)
if (CONFIG_LP_ROM_SIZE != romsize)
printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
printk(BIOS_WARNING, "rom size unmatch (%d/%d)\n",
CONFIG_LP_ROM_SIZE, romsize);
#endif
}

View File

@@ -72,9 +72,9 @@ static void serial_write_reg(uint8_t val, int offset)
static void serial_hardware_init(int speed, int word_bits,
int parity, int stop_bits)
{
#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
unsigned char reg;
#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
/* Disable interrupts. */
serial_write_reg(0, 0x01);

View File

@@ -502,7 +502,7 @@ static void complete_ep_transfer(struct usbdev_ctrl *this, int endpoint,
}
SIMPLEQ_REMOVE_HEAD(&p->eps[endpoint][in_dir].job_queue, queue);
usb_debug("%d-%d: scheduled %zd, now %d bytes\n", endpoint, in_dir,
usb_debug("%d-%d: scheduled %zd, now %zd bytes\n", endpoint, in_dir,
job->length, job->xfered_length);
if (this->current_config &&

View File

@@ -191,14 +191,6 @@ struct cb_serial {
* decisions as to which dividers to select and their values
* to eventually arrive at the desired console baud-rate. */
u32 input_hertz;
/* UART PCI address: bus, device, function
* 1 << 31 - Valid bit, PCI UART in use
* Bus << 20
* Device << 15
* Function << 12
*/
u32 uart_pci_addr;
};
struct cb_console {

View File

@@ -206,7 +206,7 @@
},
{
// Datasheet Revision: Rev. 1.0 Dec. 2021
"name": "H5AG36EXNDX019",
"name": "H5AG36EXNDX017",
"attribs": {
"speedMTps": 3200,
"CL_nRCD_nRP": 22,

View File

@@ -17,7 +17,7 @@ H5AN8G6NCJR-XNC,spd-1.hex
K4AAG165WA-BCTD,spd-8.hex
H5ANAG6NDMR-XNC,spd-2.hex
H5ANAG6NCJR-XNC,spd-9.hex
H5AG36EXNDX019,spd-1.hex
H5AG36EXNDX017,spd-1.hex
K4AAG165WB-BCWE,spd-9.hex
MT40A1G16RC-062E:B,spd-9.hex
MT40A512M16TB-062E:R,spd-1.hex

View File

@@ -175,6 +175,16 @@
"speedMbps": 7500,
"lp5x": true
}
},
{
"name": "H9JCNNNFA5MLYR-N6E",
"attribs": {
"densityPerDieGb": 8,
"diesPerPackage": 8,
"bitWidthPerChannel": 8,
"ranksPerChannel": 2,
"speedMbps": 6400
}
}
]
}

View File

@@ -18,3 +18,4 @@ K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
H9JCNNNFA5MLYR-N6E,spd-4.hex

32
spd/lp5/set-0/spd-9.hex Normal file
View File

@@ -0,0 +1,32 @@
23 10 13 0E 15 1A F9 08 00 00 00 00 0A 01 00 00
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

View File

@@ -18,3 +18,4 @@ K3KL8L80CM-MGCT,spd-7.hex
K3KL9L90CM-MGCT,spd-8.hex
H58G66BK7BX067,spd-8.hex
H58G56BK7BX068,spd-7.hex
H9JCNNNFA5MLYR-N6E,spd-4.hex

View File

@@ -1,4 +1,4 @@
23 11 15 0E 86 21 95 18 00 40 00 00 02 02 00 00
23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

View File

@@ -1,4 +1,4 @@
23 11 15 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
spd/lp5/set-1/spd-9.hex Normal file
View File

@@ -0,0 +1,32 @@
23 11 13 0E 85 19 F9 18 00 40 00 00 0A 02 00 00
00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

View File

@@ -170,23 +170,47 @@ config STATIC_OPTION_TABLE
every boot. Use this if you want the NVRAM configuration to
never be modified from its default values.
config COMPRESS_RAMSTAGE
bool "Compress ramstage with LZMA"
depends on HAVE_RAMSTAGE
# Default value set at the end of the file
config MB_COMPRESS_RAMSTAGE_LZ4
bool
help
Compress ramstage to save memory in the flash image.
Select this in a mainboard to use LZ4 compression by default
choice
prompt "Ramstage compression"
depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
default COMPRESS_RAMSTAGE_LZMA
config COMPRESS_RAMSTAGE_LZMA
bool "Compress ramstage with LZMA"
help
Compress ramstage with LZMA to save memory in the flash image.
config COMPRESS_RAMSTAGE_LZ4
bool "Compress ramstage with LZ4"
help
LZ4 doesn't give as good compression as LZMA, but decompresses much
faster. For large binaries such as ramstage, it's typically best to
use LZMA, but there can be cases where the faster decompression of
LZ4 can lead to a faster boot time. Testing on each individual board
is typically going to be needed due to the large number of factors
that can influence the decision. Binary size, CPU speed, ROM read
speed, cache, and other factors all play a part.
If you're not sure, stick with LZMA.
endchoice
config COMPRESS_PRERAM_STAGES
bool "Compress romstage and verstage with LZ4"
depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
# Default value set at the end of the file
help
Compress romstage and (if it exists) verstage with LZ4 to save flash
space and speed up boot, since the time for reading the image from SPI
(and in the vboot case verifying it) is usually much greater than the
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
time spent decompressing. Doesn't work for XIP stages for obvious
reasons.
config COMPRESS_BOOTBLOCK
bool
@@ -211,9 +235,9 @@ config INCLUDE_CONFIG_FILE
Saying Y here will increase the image size by 2-3KB.
You can use the following command to easily list the options:
You can then use cbfstool to extract the config from a final image:
grep -a CONFIG_ coreboot.rom
cbfstool coreboot.rom extract -n config -f <output file path>
Alternatively, you can also use cbfstool to print the image
contents (including the raw 'config' item we're looking for).
@@ -347,7 +371,7 @@ endif
choice
prompt "Stage Cache for ACPI S3 resume"
default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE
default TSEG_STAGE_CACHE if SMM_TSEG
config NO_STAGE_CACHE
@@ -380,6 +404,13 @@ config CBMEM_STAGE_CACHE
endchoice
config MAINBOARD_DISABLE_STAGE_CACHE
bool
help
Selected by mainboards which wish to disable the stage cache.
E.g. mainboards which don't use S3 resume in the field may wish to
disable it to save boot time at the cost of increasing S3 resume time.
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
help
@@ -715,7 +746,7 @@ config TIMER_QUEUE
config COOP_MULTITASKING
def_bool n
select TIMER_QUEUE
depends on ARCH_X86 && CPU_INFO_V2
depends on ARCH_X86
help
Cooperative multitasking allows callbacks to be multiplexed on the
main thread. With this enabled it allows for multiple execution paths
@@ -795,9 +826,9 @@ config ACPI_NHLT
menu "System tables"
config GENERATE_MP_TABLE
prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
prompt "Generate an MP table" if HAVE_MP_TABLE
bool
default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
default HAVE_MP_TABLE
help
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.
@@ -1372,11 +1403,8 @@ config MEMLAYOUT_LD_FILE
# Set default values for symbols created before mainboards. This allows the
# option to be displayed in the general menu, but the default to be loaded in
# the mainboard if desired.
config COMPRESS_RAMSTAGE
default y if !UNCOMPRESSED_RAMSTAGE
config COMPRESS_PRERAM_STAGES
depends on !ARCH_X86
depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
default y
config INCLUDE_CONFIG_FILE

View File

@@ -8,7 +8,7 @@ config ACPI_AMD_HARDWARE_SLEEP_VALUES
config ACPI_CPU_STRING
string
default "\\_SB.CP%02d"
default "\\_SB.CP%02X"
depends on HAVE_ACPI_TABLES
help
Sets the ACPI name string in the processor scope as written by
@@ -30,6 +30,11 @@ config ACPI_SOC_NVS
Set to indicate <soc/nvs.h> exists for the platform with a definition
for global_nvs.
config ACPI_NO_MADT
bool
help
Selected by platforms that don't expose a useful MADT.
config ACPI_NO_PCAT_8259
bool
help

View File

@@ -30,6 +30,10 @@
#include <types.h>
#include <version.h>
#if ENV_X86
#include <arch/ioapic.h>
#endif
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp);
u8 acpi_checksum(u8 *table, u32 length)
@@ -180,6 +184,22 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
return ioapic->length;
}
#if ENV_X86
/* For a system with multiple I/O APICs it's required that the one potentially
routing i8259 via ExtNMI delivery calls this first to get GSI #0. */
int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr)
{
static u32 gsi_base;
u32 my_base;
u8 id = get_ioapic_id((void *)(uintptr_t)addr);
u8 count = ioapic_get_max_vectors((void *)(uintptr_t)addr);
my_base = gsi_base;
gsi_base += count;
return acpi_create_madt_ioapic(ioapic, id, addr, my_base);
}
#endif
int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
u8 bus, u8 source, u32 gsirq, u16 flags)
{
@@ -220,6 +240,24 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
return lapic_nmi->length;
}
unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current)
{
const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH;
current = acpi_create_madt_lapics(current);
/* 1: LINT1 connect to NMI */
/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1);
if (!CONFIG(XAPIC_ONLY))
current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current,
ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1);
return current;
}
void acpi_create_madt(acpi_madt_t *madt)
{
acpi_header_t *header = &(madt->header);
@@ -244,7 +282,8 @@ void acpi_create_madt(acpi_madt_t *madt)
if (CONFIG(ACPI_HAVE_PCAT_8259))
madt->flags |= 1;
current = acpi_fill_madt(current);
if (!CONFIG(ACPI_NO_MADT))
current = acpi_fill_madt(current);
/* (Re)calculate length and checksum. */
header->length = current - (unsigned long)madt;
@@ -341,7 +380,7 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa)
tcpa->platform_class = 0;
tcpa->laml = tcpa_log_len;
tcpa->lasa = (uintptr_t) lasa;
tcpa->lasa = (uintptr_t)lasa;
/* Calculate checksum. */
header->checksum = acpi_checksum((void *)tcpa, header->length);
@@ -416,7 +455,7 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2)
/* Fill the log area size and start address fields. */
tpm2->laml = tpm2_log_len;
tpm2->lasa = (uintptr_t) lasa;
tpm2->lasa = (uintptr_t)lasa;
/* Calculate checksum. */
header->checksum = acpi_checksum((void *)tpm2, header->length);
@@ -460,7 +499,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
ssdt->asl_compiler_revision = asl_revision;
ssdt->length = sizeof(acpi_header_t);
acpigen_set_current((char *) current);
acpigen_set_current((char *)current);
/* Write object to declare coreboot tables */
acpi_ssdt_write_cbtable();
@@ -470,7 +509,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
for (dev = all_devices; dev; dev = dev->next)
if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt)
dev->ops->acpi_fill_ssdt(dev);
current = (unsigned long) acpigen_get_current();
current = (unsigned long)acpigen_get_current();
}
/* (Re)calculate length and checksum. */
@@ -555,6 +594,90 @@ void acpi_create_srat(acpi_srat_t *srat,
header->checksum = acpi_checksum((void *)srat, header->length);
}
int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base)
{
memset((void *)chbs, 0, sizeof(acpi_cedt_chbs_t));
chbs->type = ACPI_CEDT_STRUCTURE_CHBS;
chbs->length = sizeof(acpi_cedt_chbs_t);
chbs->uid = uid;
chbs->cxl_ver = cxl_ver;
chbs->base = base;
/*
* CXL spec 2.0 section 9.14.1.2 "CXL CHBS"
* CXL 1.1 spec compliant host bridge: 8KB
* CXL 2.0 spec compliant host bridge: 64KB
*/
if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_1_1)
chbs->len = 8 * KiB;
else if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_2_0)
chbs->len = 64 * KiB;
else
printk(BIOS_ERR, "ACPI(%s:%s): Incorrect CXL version:%d\n", __FILE__, __func__,
cxl_ver);
return chbs->length;
}
int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw,
u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target)
{
memset((void *)cfmws, 0, sizeof(acpi_cedt_cfmws_t));
cfmws->type = ACPI_CEDT_STRUCTURE_CFMWS;
u8 niw = 0;
if (eniw >= 8)
printk(BIOS_ERR, "ACPI(%s:%s): Incorrect eniw::%d\n", __FILE__, __func__, eniw);
else
/* NIW = 2 ** ENIW */
niw = 0x1 << eniw;
/* 36 + 4 * NIW */
cfmws->length = sizeof(acpi_cedt_cfmws_t) + 4 * niw;
cfmws->base_hpa = base_hpa;
cfmws->window_size = window_size;
cfmws->eniw = eniw;
// 0: Standard Modulo Arithmetic. Other values reserved.
cfmws->interleave_arithmetic = 0;
cfmws->hbig = hbig;
cfmws->restriction = restriction;
cfmws->qtg_id = qtg_id;
memcpy(&cfmws->interleave_target, interleave_target, 4 * niw);
return cfmws->length;
}
void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt)(unsigned long current))
{
acpi_header_t *header = &(cedt->header);
unsigned long current = (unsigned long)cedt + sizeof(acpi_cedt_t);
memset((void *)cedt, 0, sizeof(acpi_cedt_t));
if (!header)
return;
/* Fill out header fields. */
memcpy(header->signature, "CEDT", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = asl_revision;
header->length = sizeof(acpi_cedt_t);
header->revision = get_acpi_table_revision(CEDT);
current = acpi_fill_cedt(current);
/* (Re)calculate length and checksum. */
header->length = current - (unsigned long)cedt;
header->checksum = acpi_checksum((void *)cedt, header->length);
}
int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory)
{
memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t));
@@ -775,6 +898,14 @@ unsigned long acpi_create_dmar_ds_ioapic(unsigned long current,
SCOPE_IOAPIC, enumeration_id, bus, dev, fn);
}
unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current,
u32 addr, u8 bus, u8 dev, u8 fn)
{
u8 enumeration_id = get_ioapic_id((void *)(uintptr_t)addr);
return acpi_create_dmar_ds(current,
SCOPE_IOAPIC, enumeration_id, bus, dev, fn);
}
unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current,
u8 enumeration_id, u8 bus, u8 dev, u8 fn)
{
@@ -868,7 +999,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
printk(BIOS_DEBUG, "%s einj_smi = %p\n", __func__, einj_smi);
memset(einj_smi, 0, sizeof(acpi_einj_smi_t));
tat = (acpi_einj_trigger_table_t *)(einj_smi + sizeof(acpi_einj_smi_t));
tat = (acpi_einj_trigger_table_t *)((uint8_t *)einj_smi + sizeof(acpi_einj_smi_t));
tat->header_size = 16;
tat->revision = 0;
tat->table_size = sizeof(acpi_einj_trigger_table_t) +
@@ -966,7 +1097,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
};
einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP;
einj_smi->trigger_action_table = (u64) (uintptr_t)tat;
einj_smi->trigger_action_table = (u64)(uintptr_t)tat;
for (i = 0; i < ACTION_COUNT; i++)
printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i,
@@ -1144,7 +1275,7 @@ unsigned long acpi_write_hpet(const struct device *device, unsigned long current
*/
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
hpet = (acpi_hpet_t *)current;
current += sizeof(acpi_hpet_t);
current = ALIGN_UP(current, 16);
acpi_create_hpet(hpet);
@@ -1390,7 +1521,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
case 0: /* MCE */
break;
case 1: /* CMC */
hen = (acpi_hest_hen_t *) (pos);
hen = (acpi_hest_hen_t *)(pos);
memset(pos, 0, sizeof(acpi_hest_hen_t));
hen->type = 3; /* SCI? */
hen->length = sizeof(acpi_hest_hen_t);
@@ -1483,7 +1614,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
if (!header)
return;
@@ -1497,11 +1628,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
header->asl_compiler_revision = asl_revision;
fadt->FADT_MinorVersion = get_acpi_fadt_minor_version();
fadt->firmware_ctrl = (unsigned long) facs;
fadt->firmware_ctrl = (unsigned long)facs;
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0;
fadt->dsdt = (unsigned long) dsdt;
fadt->dsdt = (unsigned long)dsdt;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0;
@@ -1521,7 +1652,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
mainboard_fill_fadt(fadt);
header->checksum =
acpi_checksum((void *) fadt, header->length);
acpi_checksum((void *)fadt, header->length);
}
void acpi_create_lpit(acpi_lpit_t *lpit)
@@ -1642,7 +1773,7 @@ unsigned long write_acpi_tables(unsigned long start)
ssdt->asl_compiler_revision = asl_revision;
ssdt->length = sizeof(acpi_header_t);
acpigen_set_current((char *) current);
acpigen_set_current((char *)current);
/* Write object to declare coreboot tables */
acpi_ssdt_write_cbtable();
@@ -1691,19 +1822,19 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
rsdp = (acpi_rsdp_t *)current;
coreboot_rsdp = (uintptr_t)rsdp;
current += sizeof(acpi_rsdp_t);
current = acpi_align_current(current);
rsdt = (acpi_rsdt_t *) current;
rsdt = (acpi_rsdt_t *)current;
current += sizeof(acpi_rsdt_t);
current = acpi_align_current(current);
xsdt = (acpi_xsdt_t *) current;
xsdt = (acpi_xsdt_t *)current;
current += sizeof(acpi_xsdt_t);
current = acpi_align_current(current);
/* clear all table memory */
memset((void *) start, 0, current - start);
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id);
acpi_write_rsdt(rsdt, oem_id, oem_table_id);
@@ -1711,18 +1842,18 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "ACPI: * FACS\n");
current = ALIGN_UP(current, 64);
facs = (acpi_facs_t *) current;
facs = (acpi_facs_t *)current;
current += sizeof(acpi_facs_t);
current = acpi_align_current(current);
acpi_create_facs(facs);
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *) current;
dsdt = (acpi_header_t *)current;
memcpy(dsdt, dsdt_file, sizeof(acpi_header_t));
if (dsdt->length >= sizeof(acpi_header_t)) {
current += sizeof(acpi_header_t);
acpigen_set_current((char *) current);
acpigen_set_current((char *)current);
if (CONFIG(ACPI_SOC_NVS))
acpi_fill_gnvs();
@@ -1732,7 +1863,7 @@ unsigned long write_acpi_tables(unsigned long start)
for (dev = all_devices; dev; dev = dev->next)
if (dev->ops && dev->ops->acpi_inject_dsdt)
dev->ops->acpi_inject_dsdt(dev);
current = (unsigned long) acpigen_get_current();
current = (unsigned long)acpigen_get_current();
memcpy((char *)current,
(char *)dsdt_file + sizeof(acpi_header_t),
dsdt->length - sizeof(acpi_header_t));
@@ -1747,7 +1878,7 @@ unsigned long write_acpi_tables(unsigned long start)
current = acpi_align_current(current);
printk(BIOS_DEBUG, "ACPI: * FADT\n");
fadt = (acpi_fadt_t *) current;
fadt = (acpi_fadt_t *)current;
current += sizeof(acpi_fadt_t);
current = acpi_align_current(current);
@@ -1773,7 +1904,7 @@ unsigned long write_acpi_tables(unsigned long start)
}
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
mcfg = (acpi_mcfg_t *) current;
mcfg = (acpi_mcfg_t *)current;
acpi_create_mcfg(mcfg);
if (mcfg->header.length > sizeof(acpi_mcfg_t)) {
current += mcfg->header.length;
@@ -1783,7 +1914,7 @@ unsigned long write_acpi_tables(unsigned long start)
if (CONFIG(TPM1)) {
printk(BIOS_DEBUG, "ACPI: * TCPA\n");
tcpa = (acpi_tcpa_t *) current;
tcpa = (acpi_tcpa_t *)current;
acpi_create_tcpa(tcpa);
if (tcpa->header.length >= sizeof(acpi_tcpa_t)) {
current += tcpa->header.length;
@@ -1794,7 +1925,7 @@ unsigned long write_acpi_tables(unsigned long start)
if (CONFIG(TPM2)) {
printk(BIOS_DEBUG, "ACPI: * TPM2\n");
tpm2 = (acpi_tpm2_t *) current;
tpm2 = (acpi_tpm2_t *)current;
acpi_create_tpm2(tpm2);
if (tpm2->header.length >= sizeof(acpi_tpm2_t)) {
current += tpm2->header.length;
@@ -1817,7 +1948,7 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
madt = (acpi_madt_t *)current;
acpi_create_madt(madt);
if (madt->header.length > sizeof(acpi_madt_t)) {
current += madt->header.length;
@@ -1829,7 +1960,7 @@ unsigned long write_acpi_tables(unsigned long start)
if (CONFIG(ACPI_BERT)) {
void *region;
size_t size;
bert = (acpi_bert_t *) current;
bert = (acpi_bert_t *)current;
if (acpi_soc_get_bert_region(&region, &size) == CB_SUCCESS) {
printk(BIOS_DEBUG, "ACPI: * BERT\n");
acpi_write_bert(bert, (uintptr_t)region, size);
@@ -1962,8 +2093,8 @@ int get_acpi_table_revision(enum acpi_tables table)
return 4;
case SSDT: /* ACPI 3.0 up to 6.3: 2 */
return 2;
case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */
return 1; /* TODO Should probably be upgraded to 2 */
case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.4: 3 */
return 3;
case HMAT: /* ACPI 6.4: 2 */
return 2;
case DMAR:
@@ -1996,6 +2127,8 @@ int get_acpi_table_revision(enum acpi_tables table)
return 5;
case BERT:
return 1;
case CEDT: /* CXL 3.0 section 9.17.1 */
return 1;
case CRAT:
return 1;
case LPIT: /* ACPI 5.1 up to 6.3: 0 */

View File

@@ -256,7 +256,7 @@ static void acpigen_emit_multi_namestring(const char *name)
unsigned char *pathlen;
acpigen_emit_byte(MULTI_NAME_PREFIX);
acpigen_emit_byte(ZERO_OP);
pathlen = ((unsigned char *) acpigen_get_current()) - 1;
pathlen = ((unsigned char *)acpigen_get_current()) - 1;
while (name[0] != '\0') {
acpigen_emit_simple_namestring(name);
@@ -399,7 +399,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
acpigen_write_len_f();
snprintf(pscope, sizeof(pscope),
CONFIG_ACPI_CPU_STRING, (unsigned int) cpuindex);
CONFIG_ACPI_CPU_STRING, (unsigned int)cpuindex);
acpigen_emit_namestring(pscope);
acpigen_emit_byte(cpuindex);
acpigen_emit_dword(pblock_addr);
@@ -532,7 +532,7 @@ static void acpigen_write_field_offset(uint32_t offset, uint32_t current_bit_pos
acpigen_write_field_length(diff_bits);
}
static void acpigen_write_field_name(const char *name, uint32_t size)
void acpigen_write_field_name(const char *name, uint32_t size)
{
acpigen_emit_simple_namestring(name);
acpigen_write_field_length(size);

View File

@@ -62,8 +62,6 @@ static const char *namestring_of(enum dptf_participant participant)
return "TCHG";
case DPTF_FAN:
return "TFN1";
case DPTF_FAN_2:
return "TFN2";
case DPTF_TEMP_SENSOR_0:
return "TSR0";
case DPTF_TEMP_SENSOR_1:
@@ -125,7 +123,7 @@ void dptf_write_scope(enum dptf_participant participant)
* are used to increase the speed of the fan in order to speed up cooling.
*/
static void write_active_relationship_table(const struct dptf_active_policy *policies,
int max_count, bool dptf_multifan_support)
int max_count)
{
char *pkg_count;
int i, j;
@@ -156,11 +154,7 @@ static void write_active_relationship_table(const struct dptf_active_policy *pol
/* Source, Target, Percent, Fan % for each of _AC0 ... _AC9 */
acpigen_write_package(13);
if (dptf_multifan_support)
acpigen_emit_namestring(path_of(policies[i].source));
else
acpigen_emit_namestring(path_of(DPTF_FAN));
acpigen_emit_namestring(path_of(DPTF_FAN));
acpigen_emit_namestring(path_of(policies[i].target));
acpigen_write_integer(DEFAULT_IF_0(policies[i].weight, DEFAULT_WEIGHT));
@@ -211,10 +205,9 @@ static void write_active_cooling_methods(const struct dptf_active_policy *polici
}
}
void dptf_write_active_policies(const struct dptf_active_policy *policies,
int max_count, bool dptf_multifan_support)
void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count)
{
write_active_relationship_table(policies, max_count, dptf_multifan_support);
write_active_relationship_table(policies, max_count);
write_active_cooling_methods(policies, max_count);
}
@@ -359,29 +352,7 @@ void dptf_write_charger_perf(const struct dptf_charger_perf *states, int max_cou
acpigen_pop_len(); /* Scope */
}
int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed,
uint16_t noise_level)
{
/*
* Some _FPS tables do include a last entry where Percent is 0, but Power is
* called out, so this table is finished when both are zero.
*/
if (!percent && !power)
return 1;
acpigen_write_package(5);
acpigen_write_integer(percent);
acpigen_write_integer(DEFAULT_TRIP_POINT);
acpigen_write_integer(speed);
acpigen_write_integer(noise_level);
acpigen_write_integer(power);
acpigen_pop_len(); /* inner Package */
return 0;
}
void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
enum dptf_participant participant)
void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count)
{
char *pkg_count;
int i;
@@ -389,48 +360,29 @@ void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
if (!max_count || !states[0].percent)
return;
dptf_write_scope(participant);
dptf_write_scope(DPTF_FAN);
/* _FPS - Fan Performance States */
acpigen_write_name("_FPS");
pkg_count = acpigen_write_package(1); /* 1 for Revision */
acpigen_write_integer(FPS_REVISION); /* revision */
for (i = 0; i < max_count; ++i) {
(*pkg_count)++;
if (dptf_write_fan_perf_fps(states[i].percent, states[i].power,
states[i].speed, states[i].noise_level))
/*
* Some _FPS tables do include a last entry where Percent is 0, but Power is
* called out, so this table is finished when both are zero.
*/
if (!states[i].percent && !states[i].power)
break;
}
acpigen_pop_len(); /* Package */
acpigen_pop_len(); /* Scope */
}
void dptf_write_multifan_perf(
const struct dptf_multifan_perf (*states)[DPTF_MAX_FAN_PERF_STATES],
int max_count, enum dptf_participant participant, int fan_num)
{
char *pkg_count;
int i;
if (!max_count || !states[fan_num][0].percent)
return;
dptf_write_scope(participant);
/* _FPS - Fan Performance States */
acpigen_write_name("_FPS");
pkg_count = acpigen_write_package(1); /* 1 for Revision */
acpigen_write_integer(FPS_REVISION); /* revision */
for (i = 0; i < max_count; ++i) {
(*pkg_count)++;
if (dptf_write_fan_perf_fps(states[fan_num][i].percent, states[fan_num][i].power,
states[fan_num][i].speed, states[fan_num][i].noise_level))
break;
acpigen_write_package(5);
acpigen_write_integer(states[i].percent);
acpigen_write_integer(DEFAULT_TRIP_POINT);
acpigen_write_integer(states[i].speed);
acpigen_write_integer(states[i].noise_level);
acpigen_write_integer(states[i].power);
acpigen_pop_len(); /* inner Package */
}
acpigen_pop_len(); /* Package */

View File

@@ -47,3 +47,26 @@ void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config)
}
/* ------------------- End: I2C HID DSM ------------------------- */
#define USB_DSM_UUID "CE2EE385-00E6-48CB-9F05-2EDB927C4899"
static void usb_dsm_func5_cb(void *arg)
{
struct dsm_usb_config *config = arg;
acpigen_write_return_byte(config->usb_lpm_incapable);
}
static void (*usb_dsm_callbacks[6])(void *) = {
NULL,
NULL,
NULL,
NULL,
NULL,
usb_dsm_func5_cb,
};
void acpigen_write_dsm_usb(struct dsm_usb_config *config)
{
acpigen_write_dsm(USB_DSM_UUID, usb_dsm_callbacks,
ARRAY_SIZE(usb_dsm_callbacks), config);
}

View File

@@ -19,6 +19,27 @@
#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301"
#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b"
/*
* Below properties are defined at
* https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
*/
#define ACPI_DSD_EXTERNAL_FACING_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389"
#define ACPI_DSD_EXTERNAL_FACING_PORT_NAME "ExternalFacingPort"
#define ACPI_DSD_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"
#define ACPI_DSD_HOTPLUG_IN_D3_NAME "HotPlugSupportInD3"
/* ID for the DmaProperty _DSD */
#define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865"
#define ACPI_DSD_DMA_PROPERTY_NAME "DmaProperty"
/*
* Below properties are defined at
* https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro
*/
#define ACPI_DSD_STORAGE_D3_UUID "5025030F-842F-4AB4-A561-99A5189762D0"
#define ACPI_DSD_STORAGE_D3_NAME "StorageD3Enable"
/* Write empty word value and return pointer to it */
static void *acpi_device_write_zero_len(void)
{
@@ -1183,3 +1204,64 @@ void acpi_device_write_pci_dev(const struct device *dev)
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
}
/*
* Helper function to add given integer property with an UUID to _DSD in the current scope.
*
* dsd - Pointer to a _DSD object.
* Append to existing _DSD object if not NULL.
* Create new _DSD object and flush it if NULL.
* uuid - Pointer to the UUID string.
* name - Pointer to the property name string.
* value - Value of the integer property.
*/
static void acpi_device_add_integer_property_with_uuid(struct acpi_dp *dsd,
const char *uuid,
const char *name,
uint64_t value)
{
struct acpi_dp *prev_dsd = dsd, *pkg;
if (prev_dsd == NULL)
dsd = acpi_dp_new_table("_DSD");
pkg = acpi_dp_new_table(uuid);
acpi_dp_add_integer(pkg, name, value);
acpi_dp_add_package(dsd, pkg);
if (prev_dsd == NULL)
acpi_dp_write(dsd);
}
/* _DSD with ExternalFacingPort */
void acpi_device_add_external_facing_port(struct acpi_dp *dsd)
{
acpi_device_add_integer_property_with_uuid(dsd,
ACPI_DSD_EXTERNAL_FACING_PORT_UUID,
ACPI_DSD_EXTERNAL_FACING_PORT_NAME,
1);
}
/* _DSD with HotPlugSupportInD3 */
void acpi_device_add_hotplug_support_in_d3(struct acpi_dp *dsd)
{
acpi_device_add_integer_property_with_uuid(dsd,
ACPI_DSD_HOTPLUG_IN_D3_UUID,
ACPI_DSD_HOTPLUG_IN_D3_NAME,
1);
}
/* _DSD with DmaProperty */
void acpi_device_add_dma_property(struct acpi_dp *dsd)
{
acpi_device_add_integer_property_with_uuid(dsd,
ACPI_DSD_DMA_PROPERTY_UUID,
ACPI_DSD_DMA_PROPERTY_NAME,
1);
}
/* _DSD with StorageD3Enable */
void acpi_device_add_storage_d3_enable(struct acpi_dp *dsd)
{
acpi_device_add_integer_property_with_uuid(dsd,
ACPI_DSD_STORAGE_D3_UUID,
ACPI_DSD_STORAGE_D3_NAME,
1);
}

View File

@@ -10,11 +10,11 @@
/* Operating system enumeration. */
Name (OSYS, 0)
/* Zero => PIC mode, One => APIC Mode */
Name (PICM, Zero)
/* 0 => PIC mode, 1 => APIC Mode */
Name (PICM, 0)
/* Power state (AC = 1) */
Name (PWRS, One)
Name (PWRS, 1)
/*
* The _PIC method is called by the OS to choose between interrupt

View File

@@ -5,7 +5,17 @@ armv7-a_flags = -march=armv7-a $(armv7_flags) -D__COREBOOT_ARM_V7_A__
armv7-m_flags = -march=armv7-m $(armv7_flags) -D__COREBOOT_ARM_V7_M__
armv7-r_flags = -march=armv7-r $(armv7_flags) -D__COREBOOT_ARM_V7_R__
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always
ifeq ($(CONFIG_COMPILER_GCC),y)
armv7_asm_flags += -Wa,-mno-warn-deprecated
else # CLANG
armv7_flags += -mfpu=none
bootblock-ld-ccopts += -target arm-eabi
verstage-ld-ccopts += -target arm-eabi
romstage-ld-ccopts += -target arm-eabi
ramstage-ld-ccopts += -target arm-eabi
rmodule_arm-ld-ccopts += -target arm-eabi
endif
armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags)
###############################################################################

View File

@@ -23,14 +23,37 @@ void __aeabi_unwind_cpp_pr1(void)
{
}
/* Support the alias for the __aeabi_memcpy which may
assume memory alignment. */
void __aeabi_memcpy4(void *dest, const void *src, size_t n)
__attribute((alias("__aeabi_memcpy")));
void __aeabi_memcpy8(void *dest, const void *src, size_t n)
__attribute((alias("__aeabi_memcpy")));
void __aeabi_memcpy(void *dest, const void *src, size_t n);
void __aeabi_memcpy(void *dest, const void *src, size_t n)
{
(void) memcpy(dest, src, n);
(void)memcpy(dest, src, n);
}
void __aeabi_memset(void *dest, size_t n, int c);
void __aeabi_memset(void *dest, size_t n, int c)
{
(void) memset(dest, c, n);
(void)memset(dest, c, n);
}
/* Support the alias for the __aeabi_memclr which may
assume memory alignment. */
void __aeabi_memclr4(void *dest, size_t n)
__attribute((alias("__aeabi_memclr")));
void __aeabi_memclr8(void *dest, size_t n)
__attribute((alias("__aeabi_memclr")));
/* Support the routine __aeabi_memclr. */
void __aeabi_memclr(void *dest, size_t n);
void __aeabi_memclr(void *dest, size_t n)
{
__aeabi_memset(dest, n, 0);
}

View File

@@ -8,6 +8,8 @@
#include <arch/asm.h>
.syntax unified
.macro ARM_DIV_BODY dividend, divisor, result, curbit
#if __COREBOOT_ARM_ARCH__ >= 5
@@ -67,7 +69,7 @@
subhs \dividend, \dividend, \divisor, lsr #3
orrhs \result, \result, \curbit, lsr #3
cmp \dividend, #0 @ Early termination?
movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
movne \divisor, \divisor, lsr #4
bne 1b
@@ -153,7 +155,7 @@
subhs \dividend, \dividend, \divisor, lsr #3
cmp \dividend, #1
mov \divisor, \divisor, lsr #4
subges \order, \order, #4
subsge \order, \order, #4
bge 1b
tst \order, #3

Some files were not shown because too many files have changed in this diff Show More