Compare commits
1838 Commits
4.18
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2023-03-22
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34
.gitmodules
vendored
34
.gitmodules
vendored
@@ -1,67 +1,67 @@
|
||||
[submodule "3rdparty/blobs"]
|
||||
path = 3rdparty/blobs
|
||||
url = ../blobs.git
|
||||
url = https://review.coreboot.org/blobs.git
|
||||
update = none
|
||||
ignore = dirty
|
||||
[submodule "util/nvidia-cbootimage"]
|
||||
path = util/nvidia/cbootimage
|
||||
url = ../nvidia-cbootimage.git
|
||||
url = https://review.coreboot.org/nvidia-cbootimage.git
|
||||
[submodule "vboot"]
|
||||
path = 3rdparty/vboot
|
||||
url = ../vboot.git
|
||||
url = https://review.coreboot.org/vboot.git
|
||||
branch = main
|
||||
[submodule "arm-trusted-firmware"]
|
||||
path = 3rdparty/arm-trusted-firmware
|
||||
url = ../arm-trusted-firmware.git
|
||||
url = https://review.coreboot.org/arm-trusted-firmware.git
|
||||
[submodule "3rdparty/chromeec"]
|
||||
path = 3rdparty/chromeec
|
||||
url = ../chrome-ec.git
|
||||
url = https://review.coreboot.org/chrome-ec.git
|
||||
[submodule "libhwbase"]
|
||||
path = 3rdparty/libhwbase
|
||||
url = ../libhwbase.git
|
||||
url = https://review.coreboot.org/libhwbase.git
|
||||
[submodule "libgfxinit"]
|
||||
path = 3rdparty/libgfxinit
|
||||
url = ../libgfxinit.git
|
||||
url = https://review.coreboot.org/libgfxinit.git
|
||||
[submodule "3rdparty/fsp"]
|
||||
path = 3rdparty/fsp
|
||||
url = ../fsp.git
|
||||
url = https://review.coreboot.org/fsp.git
|
||||
update = none
|
||||
ignore = dirty
|
||||
[submodule "opensbi"]
|
||||
path = 3rdparty/opensbi
|
||||
url = ../opensbi.git
|
||||
url = https://review.coreboot.org/opensbi.git
|
||||
[submodule "intel-microcode"]
|
||||
path = 3rdparty/intel-microcode
|
||||
url = ../intel-microcode.git
|
||||
url = https://review.coreboot.org/intel-microcode.git
|
||||
update = none
|
||||
ignore = dirty
|
||||
branch = main
|
||||
[submodule "3rdparty/ffs"]
|
||||
path = 3rdparty/ffs
|
||||
url = ../ffs.git
|
||||
url = https://review.coreboot.org/ffs.git
|
||||
[submodule "3rdparty/amd_blobs"]
|
||||
path = 3rdparty/amd_blobs
|
||||
url = ../amd_blobs
|
||||
url = https://review.coreboot.org/amd_blobs
|
||||
update = none
|
||||
ignore = dirty
|
||||
[submodule "3rdparty/cmocka"]
|
||||
path = 3rdparty/cmocka
|
||||
url = ../cmocka.git
|
||||
url = https://review.coreboot.org/cmocka.git
|
||||
update = none
|
||||
branch = stable-1.1
|
||||
[submodule "3rdparty/qc_blobs"]
|
||||
path = 3rdparty/qc_blobs
|
||||
url = ../qc_blobs.git
|
||||
url = https://review.coreboot.org/qc_blobs.git
|
||||
update = none
|
||||
ignore = dirty
|
||||
[submodule "3rdparty/intel-sec-tools"]
|
||||
path = 3rdparty/intel-sec-tools
|
||||
url = ../9esec-security-tooling.git
|
||||
url = https://review.coreboot.org/9esec-security-tooling.git
|
||||
[submodule "3rdparty/stm"]
|
||||
path = 3rdparty/stm
|
||||
url = ../STM
|
||||
url = https://review.coreboot.org/STM
|
||||
branch = stmpe
|
||||
[submodule "util/goswid"]
|
||||
path = util/goswid
|
||||
url = ../goswid
|
||||
url = https://review.coreboot.org/goswid.git
|
||||
branch = trunk
|
||||
|
2
3rdparty/amd_blobs
vendored
2
3rdparty/amd_blobs
vendored
Submodule 3rdparty/amd_blobs updated: 234dc70670...acf7395452
2
3rdparty/arm-trusted-firmware
vendored
2
3rdparty/arm-trusted-firmware
vendored
Submodule 3rdparty/arm-trusted-firmware updated: c45d2febb9...9881bb93a3
2
3rdparty/blobs
vendored
2
3rdparty/blobs
vendored
Submodule 3rdparty/blobs updated: 5a19332deb...01ba15667f
2
3rdparty/fsp
vendored
2
3rdparty/fsp
vendored
Submodule 3rdparty/fsp updated: 12160fe64b...6f2f17f3d3
2
3rdparty/intel-microcode
vendored
2
3rdparty/intel-microcode
vendored
Submodule 3rdparty/intel-microcode updated: 6c0c4691e5...2be47edc99
2
3rdparty/libgfxinit
vendored
2
3rdparty/libgfxinit
vendored
Submodule 3rdparty/libgfxinit updated: 1b04c517b3...066e52eeaa
2
3rdparty/libhwbase
vendored
2
3rdparty/libhwbase
vendored
Submodule 3rdparty/libhwbase updated: fc2102f560...8be5a82b85
2
3rdparty/qc_blobs
vendored
2
3rdparty/qc_blobs
vendored
Submodule 3rdparty/qc_blobs updated: e8efa5d98d...33cc4f2fd8
2
3rdparty/vboot
vendored
2
3rdparty/vboot
vendored
Submodule 3rdparty/vboot updated: b827ddb9b0...a09b792e6a
@@ -1,3 +1,4 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Makefile for coreboot paper.
|
||||
# hacked together by Stefan Reinauer <stepan@openbios.org>
|
||||
|
@@ -1,3 +1,4 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
# Makefile for Sphinx documentation
|
||||
#
|
||||
|
||||
|
@@ -11,6 +11,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
`acpihelp _XXX`
|
||||
* 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)
|
||||
* 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space.
|
||||
Better abbreviated as 4GiB
|
||||
* 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)
|
||||
|
||||
## A
|
||||
@@ -45,6 +46,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* ALIB - AMD: ACPI-ASL Library
|
||||
* ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor)
|
||||
* ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit)
|
||||
* AMBA - ARM: [**Advanced Microcontroller Bus
|
||||
Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture):
|
||||
An open standard to connect and manage functional blocks in an SoC
|
||||
(System on a Chip)
|
||||
* AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
|
||||
* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
|
||||
SBI: Sideband Interface
|
||||
@@ -53,8 +58,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* AOAC - AMD: Always On, Always Connected
|
||||
* AP - Application processor - The main processor on the board (as
|
||||
opposed to the embedded controller or other processors that may be on
|
||||
the system), any cores in processor chip that isn’t the BSP - Boot
|
||||
Strap Processor.
|
||||
the system), any cores in the processor chip that aren't the BSP (Boot
|
||||
Strap Processor).
|
||||
* APCB - AMD: AMD PSP Customization Block
|
||||
* API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
|
||||
* APIC - [**Advanced Programmable Interrupt
|
||||
@@ -123,6 +128,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
stored as a single object, this was co-opted by the open source
|
||||
communities to mean any proprietary binary file that is not available
|
||||
as source code.
|
||||
* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering)
|
||||
* BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management_Interface#Baseboard_management_controller)
|
||||
* BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format)
|
||||
* BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials)
|
||||
@@ -165,7 +171,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity)
|
||||
* CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim)
|
||||
* CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)
|
||||
* CL - Change List - A git patch in gerrit
|
||||
* CL - ChangeList - Another name for a patch or commit. This seems to be
|
||||
Perforce notation.
|
||||
* CLK - Clock - Used when there isn't enough room for 2 additional
|
||||
characters - similar to RST, for people who hate vowels.
|
||||
* CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake)
|
||||
@@ -180,6 +187,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
|
||||
* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
|
||||
* CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device)
|
||||
* CPPC - AMD: Collaborative Processor Performance Controls
|
||||
* CPS - Characters Per Second
|
||||
* CPU - [**Central Processing
|
||||
Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
|
||||
@@ -196,12 +204,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* CSI - MIPI: [**Camera Serial
|
||||
Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface)
|
||||
* CSME - Intel: Converged Security and Management Engine
|
||||
* CTLE - Intel: Continuous Time Linear Equalization
|
||||
* CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
|
||||
* CZN - AMD: Cezanne - CPU Family 19h, Model 50h
|
||||
* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
|
||||
|
||||
|
||||
## D
|
||||
|
||||
* D$ - Data Cache
|
||||
* D-States - [**ACPI Device power
|
||||
states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface#Device_states)
|
||||
D0-D3 - These are device specific power states, with each higher
|
||||
@@ -223,6 +233,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel)
|
||||
* DDI - Intel: Digital Display Interface
|
||||
* DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
|
||||
* DEVAPC - Mediatek: Device Access Permission Control
|
||||
* DFP - USB: Downstream Facing port
|
||||
* DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
|
||||
* DID - Device Identifier
|
||||
* DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
|
||||
@@ -235,6 +247,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
Graphics Card, Sound Card. DMA is an essential feature of all modern
|
||||
computers, as it allows devices of different speeds to communicate
|
||||
without subjecting the CPU to a massive interrupt load.
|
||||
* DMI - Direct Media Interface is a link/bus between CPU and PCH.
|
||||
* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
|
||||
* DMIC - Digital Microphone
|
||||
* DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
|
||||
@@ -243,6 +256,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton)
|
||||
* DOS - Disk Operating System
|
||||
* DP - DisplayPort
|
||||
* DPM - Mediatek: DRAM Power Manager
|
||||
* DPTF - Intel: Dynamic Power and Thermal Framework
|
||||
* DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
|
||||
* DRTM - Dynamic Root of Trust for Measurement
|
||||
@@ -250,7 +264,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
data-in pin is generally referred to as D, and the data-out pin is Q,
|
||||
thus the IO Data signal lines are referred to as DQ lines.
|
||||
* DQS - Memory: Data Q Strobe - Data valid signal for DDR memory.
|
||||
* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
|
||||
* DRM - [**Digital Rights
|
||||
Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
|
||||
* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or
|
||||
an Upstream Facing (UFP).
|
||||
* DRQ - DMA Request
|
||||
* DRTU - Intel: Diagnostics and Regulatory Testing Utility
|
||||
* DSDT - The [**Differentiated System Descriptor
|
||||
@@ -262,12 +279,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line)
|
||||
* DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor)
|
||||
* DTB - U-Boot: Device Tree Binary
|
||||
* dTPM - Discrete Trusted Platform Module
|
||||
* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
|
||||
vs Integrated TPMs or fTPMs (Firmware TPMs).
|
||||
* DTS - U-Boot: Device Tree Source
|
||||
* DVFS - ARM: Dynamic Voltage and Frequency Scaling
|
||||
* DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
|
||||
* DVT - Production Timeline: Design Validation Test
|
||||
* DW - DesignWare
|
||||
* DW - DesignWare: A portfolio of silicon IP blocks for sale by the
|
||||
Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA,
|
||||
I2c, memory controllers and more.
|
||||
* DXE - UEFI: [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface#DXE_%E2%80%93_Driver_Execution_Environment_)
|
||||
* DXIO - AMD: Distributed CrossBar I/O
|
||||
|
||||
@@ -283,7 +303,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
|
||||
- A DRAM standard introduced in 1994 that improved upon, but was
|
||||
backwards compatible with FPM (Fast Page Mode) memory.
|
||||
* EDP - [**Embedded DisplayPort**](DisplayPort)
|
||||
* eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP)
|
||||
* EDS - Intel: External Design Specification
|
||||
* EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
|
||||
electrical erasable programmable ROM).
|
||||
@@ -340,7 +360,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
|
||||
* FSP - Intel: Firmware Support Package
|
||||
* FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
|
||||
* FTPM - Firmware TPM
|
||||
* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is
|
||||
based in firmware instead of actual hardware. It typically runs in
|
||||
some sort of TEE (Trusted Execution Environment).
|
||||
|
||||
|
||||
## G
|
||||
@@ -356,6 +378,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
Real Time Clock, and maybe a few other registers running.
|
||||
* GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
|
||||
* GATT - Graphics Aperture Translation Table
|
||||
* GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table)
|
||||
* GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake)
|
||||
* GMA - Intel: [**Graphics Media
|
||||
Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
|
||||
@@ -407,6 +430,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
|
||||
## I
|
||||
|
||||
* I$ - Instruction Cache
|
||||
* I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for
|
||||
communication generally between different ICs on a circuit board.
|
||||
* [https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html](https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html)
|
||||
@@ -428,6 +452,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI
|
||||
slot has a signal called IDSEL. It is used to differentiate between
|
||||
the different slots.
|
||||
* IDT - [Interrupt Descriptor Table](https://en.wikipedia.org/wiki/Interrupt_descriptor_table)
|
||||
* IF - AMD: [**Infinity
|
||||
Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
|
||||
is a superset of AMD's earlier Hypertransport interconnect.
|
||||
@@ -539,7 +564,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* MCU - Memory Control Unit
|
||||
* MCU - [**MicroController
|
||||
Unit**](https://en.wikipedia.org/wiki/Microcontroller)
|
||||
* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
|
||||
* MDFIO - Intel: Multi-Die Fabric IO
|
||||
* MDN - AMD: Mendocino
|
||||
* ME - Intel: Management Engine
|
||||
* MEI - Intel: ME Interface (Previously known as HECI)
|
||||
* Memory training - the process of finding the best speeds, voltages,
|
||||
@@ -578,9 +605,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
OS software writers to produce SMP-capable machines and OSes in a
|
||||
vendor-independent manner. Version 1.1 of the spec was released in
|
||||
1994, and the 1.4 version was released in 1995. This has been
|
||||
generally been
|
||||
https://en.wikipedia.org/wiki/MultiProcessor_Specification by the ACPI
|
||||
tables.
|
||||
generally superseded by the ACPI tables.
|
||||
* MRC - Intel: Memory Reference Code
|
||||
* MSB - Most Significant Bit
|
||||
* MSI - Message Signaled Interrupt
|
||||
@@ -588,8 +613,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* MT/s - MegaTransfers per second
|
||||
* MTL - Intel: Meteor Lake
|
||||
* MTL - ARM: MHU Transport Layer
|
||||
* MTRR - [**Memory Type and Range
|
||||
Register**](http://en.wikipedia.org/wiki/MTRR)
|
||||
* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
|
||||
allows to set the cache behaviour on memory access in x86. Basically,
|
||||
it tells the CPU how to cache certain ranges of memory
|
||||
(e.g. write-through, write-combining, write-back...). Memory ranges
|
||||
are specified over physical address ranges. In Linux, they are visible
|
||||
over `/proc/mtrr` and they can be modified there. For further
|
||||
information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
|
||||
|
||||
|
||||
## N
|
||||
@@ -621,8 +651,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
|
||||
* ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state
|
||||
* ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state.
|
||||
* ODM - Original Design Manufacturer
|
||||
* OEM - Original Equipment Manufacturer
|
||||
* ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer)
|
||||
* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufacturer)
|
||||
* OHCI - [**Open Host Controller
|
||||
Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB%29)
|
||||
- non-proprietary USB Host controller for USB 1.1 (May also refer to
|
||||
@@ -643,7 +673,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* PAT - [**Page Attribute
|
||||
Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can
|
||||
be used independently or in combination with MTRR to setup memory type
|
||||
access ranges. Allows more finely-grained control than MTRR.
|
||||
access ranges. Allows more finely-grained control than MTRR. Compared to MTRR,
|
||||
which sets memory types by physical address ranges, PAT sets them at Page
|
||||
level.
|
||||
* PAT - Intel: [**Performance Acceleration
|
||||
Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_technology)
|
||||
* PATA - Parallel Advanced Technology Attachment - A renaming of ATA
|
||||
@@ -669,7 +701,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
function's configuration space from 256 bytes to 4K.
|
||||
* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
|
||||
* PCMCIA: Personal Computer Memory Card International Association
|
||||
* PCO - AMD: Picasso
|
||||
* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
|
||||
* PCR: TPM: Platform Configuration Register
|
||||
* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage. Setting it low drives it to ground through a resistor.
|
||||
* PD - Power Delivery - This is a specification for communicating power
|
||||
@@ -837,6 +869,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
|
||||
Memory)
|
||||
* SEV - AMD: Secure Encrypted Virtualization
|
||||
* SF - Snoop Filter
|
||||
* Shadow RAM - RAM which content is copied from ROM residing at the same
|
||||
address for speedup purposes.
|
||||
* Shim - A small piece of code whose only purpose is to act as an
|
||||
@@ -873,6 +906,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* SPI - [**Serial Peripheral
|
||||
Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface)
|
||||
* SPL - AMD: Security Patch Level
|
||||
* SPM - Mediatek: System Power Manager
|
||||
* SPMI - MIPI: System Power Management Interface
|
||||
* SRAM - Static Random Access Memory
|
||||
* SSD - Solid State Drive
|
||||
@@ -889,7 +923,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
|
||||
* SSI-TEB - Physical board format: [**SSI Thin Electronics
|
||||
Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
|
||||
* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
|
||||
* STAPM - AMD: Skin Temperature Aware Power Management
|
||||
* STB - AMD: Smart Trace Buffer
|
||||
* SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
|
||||
(SIO) device provides a system with any of a number of different
|
||||
peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT
|
||||
@@ -909,7 +945,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* TDMA - Time-Division Multiple Access
|
||||
* TDP - [**Thermal Design
|
||||
Power**](https://en.wikipedia.org/wiki/Thermal_design_power)
|
||||
* TEE - Trusted Execution Environment
|
||||
* TEE - [**Trusted Execution
|
||||
Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment)
|
||||
* TFTP - Network Protocol: Trivial File Transfer Protocol
|
||||
* TGL - Intel: Tigerlake
|
||||
* THC - Touch Host Controller
|
||||
@@ -919,6 +956,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* TLA - Three Letter Acronym
|
||||
* TLB - [**Translation Lookside
|
||||
Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer)
|
||||
* TME - Intel: Total Memory Encryption
|
||||
* TOCTOU - Time-Of-Check to Time-Of-Use
|
||||
* TOLUM - Top of Low Usable Memory
|
||||
* ToM - Top of Memory
|
||||
@@ -927,6 +965,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* TSC - [**Time Stamp
|
||||
Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
|
||||
* TSEG - TOM (Top of Memory) Segment
|
||||
* TSR - Temperature Sensor
|
||||
* TWAIN - Technology without an interesting name.
|
||||
* TX - Transmit
|
||||
* TXE - Intel: Trusted eXecution Engine
|
||||
@@ -940,6 +979,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
* UDK - UEFI: UEFI Development Kit
|
||||
* UDP - User Datagram Protocol
|
||||
* UEFI - Unified Extensible Firmware Interface
|
||||
* UFP - USB: Upstream Facing Port
|
||||
* UFS - Universal Flash storage
|
||||
* UHCI - USB: [**Universal Host Controller
|
||||
Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29%23UHCI)
|
||||
@@ -989,6 +1029,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
|
||||
tablets, it's on the the side away from the screen.
|
||||
* WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
|
||||
* WLAN - Wireless LAN (Local Area Network)
|
||||
* WWAN - Telecommunication: Wireless WAN (Wide Area Network)
|
||||
* WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
|
||||
* WO - Write-only
|
||||
* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
|
||||
|
@@ -66,7 +66,7 @@ case 'm':
|
||||
case 'K':
|
||||
case 'k':
|
||||
mem <<= 10;
|
||||
/* fall through */
|
||||
__fallthrough;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -818,9 +818,9 @@ Function return values and names
|
||||
|
||||
Functions can return values of many different kinds, and one of the most
|
||||
common is a value indicating whether the function succeeded or failed.
|
||||
Such a value can be represented as an error-code integer (-Exxx =
|
||||
failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
|
||||
= success).
|
||||
Such a value can be represented as an error-code integer (`CB_ERR_xxx`
|
||||
(negative number) = failure, `CB_SUCCESS` (0) = success) or a "succeeded"
|
||||
boolean (0 = failure, non-zero = success).
|
||||
|
||||
Mixing up these two sorts of representations is a fertile source of
|
||||
difficult-to-find bugs. If the C language included a strong distinction
|
||||
@@ -832,21 +832,84 @@ If the name of a function is an action or an imperative command,
|
||||
the function should return an error-code integer. If the name
|
||||
is a predicate, the function should return a "succeeded" boolean.
|
||||
|
||||
For example, "add work" is a command, and the add_work() function
|
||||
returns 0 for success or -EBUSY for failure. In the same way, "PCI
|
||||
device present" is a predicate, and the pci_dev_present() function
|
||||
For example, "add work" is a command, and the `add_work()` function
|
||||
returns 0 for success or `CB_ERR` for failure. In the same way, "PCI
|
||||
device present" is a predicate, and the `pci_dev_present()` function
|
||||
returns 1 if it succeeds in finding a matching device or 0 if it
|
||||
doesn't.
|
||||
|
||||
All EXPORTed functions must respect this convention, and so should all
|
||||
public functions. Private (static) functions need not, but it is
|
||||
recommended that they do.
|
||||
|
||||
Functions whose return value is the actual result of a computation,
|
||||
rather than an indication of whether the computation succeeded, are not
|
||||
subject to this rule. Generally they indicate failure by returning some
|
||||
out-of-range result. Typical examples would be functions that return
|
||||
pointers; they use NULL or the ERR_PTR mechanism to report failure.
|
||||
pointers; they use NULL to report failure.
|
||||
|
||||
Error handling, assertions and die()
|
||||
-----------------------------
|
||||
|
||||
As firmware, coreboot has no means to let the user interactively fix things when
|
||||
something goes wrong. We either succeed to boot or the device becomes a brick
|
||||
that must be recovered through complicated external means (e.g. a flash
|
||||
programmer). Therefore, coreboot code should strive to continue booting
|
||||
wherever possible.
|
||||
|
||||
In most cases, errors should be handled by logging a message of at least
|
||||
`BIOS_ERR` level, returning out of the function stack for the failed feature,
|
||||
and then continuing execution. For example, if a function reading the EDID of an
|
||||
eDP display panel encounters an I2C error, it should print a "cannot read EDID"
|
||||
message and return an error code. The calling display initialization function
|
||||
knows that without the EDID there is no way to initialize the display correctly,
|
||||
so it will also immediately return with an error code without running its
|
||||
remaining code that would initialize the SoC's display controller. Exeuction
|
||||
returns further up the function stack to the mainboard initialization code
|
||||
which continues booting despite the failed display initialization, since
|
||||
display functionality is non-essential to the system. (Code is encouraged but
|
||||
not required to use `enum cb_err` error codes to return these errors.)
|
||||
|
||||
coreboot also has the `die()` function that completely halts execution. `die()`
|
||||
should only be used as a last resort, since it results in the worst user
|
||||
experience (bricked system). It is generally preferrable to continue executing
|
||||
even after a problem was encountered that might be fatal (e.g. SPI clock
|
||||
couldn't be configured correctly), because a slight chance of successfully
|
||||
booting is still better than not booting at all. The only cases where `die()`
|
||||
should be used are:
|
||||
|
||||
1. There is no (simple) way to continue executing. For example, when loading the
|
||||
next stage from SPI flash fails, we don't have any more code to execute. When
|
||||
memory initialization fails, we have no space to load the ramstage into.
|
||||
|
||||
2. Continuing execution would pose a security risk. All security features in
|
||||
coreboot are optional, but when they are configured in the user must be able
|
||||
to rely on them. For example, if CBFS verification is enabled and the file
|
||||
hash when loading the romstage doesn't match what it should be, it is better
|
||||
to stop execution than to jump to potentially malicious code.
|
||||
|
||||
In addition to normal error logging with `printk()`, coreboot also offers the
|
||||
`assert()` macro. `assert()` should be used judiciously to confirm that
|
||||
conditions are true which the programmer _knows_ to be true, in order to catch
|
||||
programming errors and incorrect assumptions. It is therefore different from a
|
||||
normal `if ()`-check that is used to actually test for things which may turn
|
||||
out to be true or false based on external conditions. For example, anything
|
||||
that involves communicating with hardware, such as whether an attempt to read
|
||||
from SPI flash succeeded, should _not_ use `assert()` and should instead just
|
||||
be checked with a normal `if ()` and subsequent manual error handling. Hardware
|
||||
can always fail for various reasons and the programmer can never 100% assume in
|
||||
advance that it will work as expected. On the other hand, if a function takes a
|
||||
pointer parameter `ctx` and the contract for that function (as documented in a
|
||||
comment above its declaration) specifies that this parameter should point to a
|
||||
valid context structure, then adding an `assert(ctx)` line to that function may
|
||||
be a good idea. The programmer knows that this function should never be called
|
||||
with a NULL pointer (because that's how it is specified), and if it was actually
|
||||
called with a NULL pointer that would indicate a programming error on account of
|
||||
the caller.
|
||||
|
||||
`assert()` can be configured to either just print an error message and continue
|
||||
execution (default), or call `die()` (when `CONFIG_FATAL_ASSERTS` is set).
|
||||
Developers are encouraged to always test their code with this option enabled to
|
||||
make assertion errors (and therefore bugs) more easy to notice. Since assertions
|
||||
thus do not always stop execution, they should never be relied upon to be the
|
||||
sole guard against conditions that really _need_ to stop execution (e.g.
|
||||
security guarantees should never be enforced only by `assert()`).
|
||||
|
||||
Headers and includes
|
||||
---------------
|
||||
|
@@ -3,6 +3,84 @@
|
||||
The document describes the coreboot options how to make CBFS files populate
|
||||
platform-unique SMBIOS data.
|
||||
|
||||
## SMBIOS Serial Number
|
||||
|
||||
The [DMTF SMBIOS specification] defines a field in the type 1 System
|
||||
Information and type 2 Baseboard Information called Serial Number. It
|
||||
is a null-terminated string field assumed to be unique per platform. Certain
|
||||
mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
|
||||
data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
|
||||
provide an option to populate the Serial Numbers from CBFS for boards that
|
||||
can't generate the it from any source.
|
||||
|
||||
### Usage
|
||||
|
||||
In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
|
||||
and select an option `Serial number in CBFS`. The Kconfig system will enable
|
||||
`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
|
||||
coreboot image.
|
||||
|
||||
After the coreboot build for your board completes, use the cbfstool to include
|
||||
the file containing the serial number:
|
||||
|
||||
```shell
|
||||
./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
|
||||
```
|
||||
|
||||
Where `serial_file.txt` is the unterminated string representation of the SMBIOS
|
||||
type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
|
||||
partitions you will have to specify the RW regions where the file is going to
|
||||
be added too. By default the RW CBFS partitions are truncated, so the files
|
||||
would probably not fit, one needs to expand them first.
|
||||
|
||||
```shell
|
||||
./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
|
||||
./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
|
||||
-f /path/to/serial_file.txt -r FW_MAIN_A
|
||||
./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
|
||||
|
||||
./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
|
||||
./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
|
||||
-f /path/to/serial_file.txt -r FW_MAIN_B
|
||||
./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
|
||||
```
|
||||
|
||||
By default cbfstool adds files to COREBOOT region only, so when vboot is
|
||||
enabled and the platform is booting from RW partition, the file would not be
|
||||
picked up by the driver.
|
||||
|
||||
One may retrieve the Serial Number from running system (if it exists) using one
|
||||
of the following commands:
|
||||
|
||||
```shell
|
||||
# Type 1
|
||||
echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
|
||||
# OR Type 2
|
||||
echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
|
||||
```
|
||||
|
||||
Ensure the file does not end with whitespaces like LF and/or CR. The above
|
||||
commands will not add any whitespaces. The driver automatically terminates the
|
||||
Serial Number with the NULL character. If the CBFS file is not present, the
|
||||
driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
|
||||
option.
|
||||
|
||||
Please note that this driver provides `smbios_mainboard_serial_number` hook
|
||||
overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
|
||||
build option. If you wish to populate only type 2 Serial Number field your
|
||||
board code needs to implement `smbios_system_serial_number`, otherwise the weak
|
||||
implementation of `smbios_system_serial_number` will call
|
||||
`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
|
||||
implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
|
||||
has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
|
||||
if the board does not implement its own `smbios_system_serial_number`.
|
||||
|
||||
There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
|
||||
populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
|
||||
implementation (returns empty string). If you wish to populate type 3 Serial
|
||||
Number, your board code should override the default
|
||||
`smbios_chassis_serial_number` weak implementation.
|
||||
|
||||
## SMBIOS System UUID
|
||||
|
||||
The [DMTF SMBIOS specification] defines a field in the type 1 System
|
||||
|
@@ -8,7 +8,7 @@ device pci 15.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
|
||||
register "detect" = "1"
|
||||
register "wake" = "GPE0_DW0_21"
|
||||
device i2c 15 on end
|
||||
@@ -39,7 +39,7 @@ Scope (\_SB.PCI0.I2C0)
|
||||
I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
|
||||
AddressingMode7Bit, "\\_SB.PCI0.I2C0",
|
||||
0x00, ResourceConsumer, , Exclusive, )
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
|
||||
{
|
||||
0x0000002D,
|
||||
}
|
||||
@@ -54,7 +54,7 @@ Scope (\_SB.PCI0.I2C0)
|
||||
}
|
||||
```
|
||||
|
||||
You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
|
||||
You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
|
||||
names/methods in the Device's scope.
|
||||
|
||||
## Utilizing a device driver
|
||||
@@ -88,7 +88,7 @@ be included in the ACPI table.
|
||||
register "hid" = ""ELAN0000""
|
||||
```
|
||||
|
||||
This corresponds to **const char *hid** in the struct. In the ACPI ASL, it
|
||||
This corresponds to **const char \*hid** in the struct. In the ACPI ASL, it
|
||||
translates to:
|
||||
|
||||
```
|
||||
@@ -104,7 +104,7 @@ during enumeration in the OS.**
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
```
|
||||
|
||||
corresponds to **const char *desc** and in ASL:
|
||||
corresponds to **const char \*desc** and in ASL:
|
||||
|
||||
```
|
||||
Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
|
||||
@@ -115,7 +115,7 @@ corresponds to **const char *desc** and in ASL:
|
||||
It also adds the interrupt,
|
||||
|
||||
```
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
|
||||
{
|
||||
0x0000002D,
|
||||
}
|
||||
@@ -124,23 +124,30 @@ It also adds the interrupt,
|
||||
which comes from:
|
||||
|
||||
```
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
|
||||
```
|
||||
|
||||
The GPIO pin IRQ settings control the "Level", "ActiveLow", and
|
||||
"ExclusiveAndWake" settings seen above (level means it is a level-triggered
|
||||
interrupt as opposed to edge-triggered; active low means the interrupt is
|
||||
triggered when the signal is low).
|
||||
The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
|
||||
means it is a level-triggered interrupt as opposed to
|
||||
edge-triggered; active low means the interrupt is triggered when the signal is
|
||||
low).
|
||||
|
||||
Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
|
||||
will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
|
||||
source. Also note that the IRQ names are SoC-specific, and you will need to
|
||||
Also note that the IRQ names are SoC-specific, and you will need to
|
||||
find the names in your SoC's header file. The ACPI_* macros are defined in
|
||||
``src/arch/x86/include/acpi/acpi_device.h``.
|
||||
|
||||
Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
|
||||
This is often done in a mainboard-specific file named ``gpio.c``.
|
||||
|
||||
AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
|
||||
GPIO controller needs to be used directly. You can do this by setting the
|
||||
`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
|
||||
|
||||
i.e.,
|
||||
```
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
|
||||
```
|
||||
|
||||
### detect
|
||||
|
||||
The next register is:
|
||||
@@ -162,9 +169,10 @@ I2C audio devices should also work without issue.
|
||||
Touchscreens can use this feature as well, but special care is needed to
|
||||
implement the proper power sequencing for the device to be detected. Generally,
|
||||
this means driving the enable GPIO high and holding the reset GPIO low in early
|
||||
GPIO init (bootblock/romstage), then releasing reset in ramstage. While no
|
||||
boards in the tree currently implement this, it has been used in downstream
|
||||
forks without issue for some time now.
|
||||
GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
|
||||
mainboards in the tree to implement this are google/skyrim and google/guybrush.
|
||||
This feature has also been used in downstream forks without issue for some time
|
||||
now on several other boards.
|
||||
|
||||
### wake
|
||||
|
||||
@@ -179,6 +187,8 @@ through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
|
||||
this example. The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
|
||||
elsewhere in the devicetree.
|
||||
|
||||
### device
|
||||
|
||||
The last bit of the definition of that device includes:
|
||||
|
||||
```
|
||||
@@ -192,6 +202,65 @@ found on. In this example, this is I2C bus 0. This also determines the ACPI
|
||||
"Scope" that the device names and methods will live under, in this case
|
||||
"\_SB.PCI0.I2C0".
|
||||
|
||||
## Wake sources
|
||||
|
||||
The ACPI spec defines two methods to describe how a device can wake the system.
|
||||
Only one of these methods should be used, otherwise duplicate wake events will
|
||||
be generated.
|
||||
|
||||
### Using GPEs as a wake source
|
||||
|
||||
The `wake` property specified above is used to tell the ACPI subsystem that the
|
||||
device can use a GPE to wake the system. The OS can control whether to enable
|
||||
or disable the wake source by unmasking/masking off the GPE.
|
||||
|
||||
The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
|
||||
generally done by a mainboard specific `gpio.c` file that defines the GPIO
|
||||
using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
|
||||
`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
|
||||
file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
|
||||
`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
|
||||
GPEs (the rest are available as `tier-2` GPEs).
|
||||
|
||||
Windows has a large caveat when using this method. If you use the `gpio_irq`
|
||||
property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
|
||||
to define a `GPE`, Windows will
|
||||
[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
|
||||
complaining about an invalid ACPI configuration.
|
||||
> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
|
||||
|
||||
In order to avoid this error, you should use the `irq` property instead. AMD
|
||||
platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
|
||||
feasible. The other option is to use a wake capable GPIO as described below.
|
||||
|
||||
### Using GPIO interrupts as a wake source
|
||||
|
||||
The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
|
||||
`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
|
||||
`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
|
||||
|
||||
This method has a few caveats:
|
||||
* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
|
||||
the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
|
||||
system. Instead you need to use the `gpio_irq` property, or a `GPE` as
|
||||
described above.
|
||||
* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
|
||||
means the platform specific GPIO controller driver must implement the
|
||||
`irq_set_wake` callback. For AMD systems this wasn't
|
||||
[implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
|
||||
until linux v5.15. If the controller doesn't define this callback, it's
|
||||
possible for the firmware to manually set the `wake` bit on the GPIO. This is
|
||||
often done in a mainboard-specific file named `gpio.c`. This is not
|
||||
recommended because then it's not possible for the OS to disable the wake
|
||||
source.
|
||||
* As of
|
||||
[linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
|
||||
the ACPI subsystem doesn't take the interrupt `wake` bit into account when
|
||||
deciding on which power state to put the device in before suspending the
|
||||
system. This means that if you define a power resource for a device via
|
||||
`has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
|
||||
device into D3Cold. i.e., power off the device.
|
||||
|
||||
## Other auto-generated names
|
||||
|
||||
(see [ACPI specification
|
||||
@@ -199,17 +268,19 @@ found on. In this example, this is I2C bus 0. This also determines the ACPI
|
||||
for more details on ACPI methods)
|
||||
|
||||
### _S0W (S0 Device Wake State)
|
||||
_S0W indicates the deepest S0 sleep state this device can wake itself from,
|
||||
which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
|
||||
\_S0W indicates the deepest S0 sleep state this device can wake itself from,
|
||||
which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
|
||||
D3Hot means the `PR3` power resources are still on and the device is still
|
||||
responsive on the bus. For i2c devices this is generally the same state as `D0`.
|
||||
|
||||
### _PRW (Power Resources for Wake)
|
||||
_PRW indicates the power resources and events required for wake. There are no
|
||||
### \_PRW (Power Resources for Wake)
|
||||
\_PRW indicates the power resources and events required for wake. There are no
|
||||
dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
|
||||
as well as the deepest sleep state supporting waking the system (3), which is
|
||||
S3.
|
||||
|
||||
### _STA (Status)
|
||||
The _STA method is generated automatically, and its values, 0xF, indicates the
|
||||
### \_STA (Status)
|
||||
The \_STA method is generated automatically, and its values, 0xF, indicates the
|
||||
following:
|
||||
|
||||
Bit [0] – Set if the device is present.
|
||||
@@ -217,8 +288,8 @@ following:
|
||||
Bit [2] – Set if the device should be shown in the UI.
|
||||
Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
|
||||
|
||||
### _CRS (Current resource settings)
|
||||
The _CRS method is generated automatically, as the driver knows it is an I2C
|
||||
### \_CRS (Current resource settings)
|
||||
The \_CRS method is generated automatically, as the driver knows it is an I2C
|
||||
controller, and so specifies how to configure the controller for proper
|
||||
operation with the touchpad.
|
||||
|
||||
|
114
Documentation/external_docs.md
Normal file
114
Documentation/external_docs.md
Normal file
@@ -0,0 +1,114 @@
|
||||
# External Resources
|
||||
|
||||
This is a list of resources that could be useful to coreboot developers.
|
||||
These are not endorsed or officially recommended by the coreboot project,
|
||||
but simply listed here in the hopes that someone will find something
|
||||
useful.
|
||||
|
||||
Please add any helpful or informational links and sections as you see fit.
|
||||
|
||||
## Articles
|
||||
|
||||
* External Interrupts in the x86 system.
|
||||
* [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
|
||||
* [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
|
||||
* [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
|
||||
* System address map initialization in x86/x64 architecture.
|
||||
* [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
|
||||
* [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
|
||||
* [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
|
||||
* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
|
||||
|
||||
|
||||
## General Information
|
||||
|
||||
* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
|
||||
* [Interface BUS](http://www.interfacebus.com/)
|
||||
* Open course material for a variety of topics such as assembly, firmware,
|
||||
security, debugging, and more.
|
||||
* [Open Security Training](https://opensecuritytraining.info/Training.html),
|
||||
* [Open Security Training 2](https://p.ost2.fyi/)
|
||||
|
||||
|
||||
## Firmware Specifications & Information
|
||||
|
||||
* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
|
||||
* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
|
||||
* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
|
||||
|
||||
|
||||
### ACPI
|
||||
|
||||
* [ACPI Specs](https://uefi.org/acpi/specs)
|
||||
* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
|
||||
* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
|
||||
* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
|
||||
|
||||
|
||||
### Security
|
||||
|
||||
* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
|
||||
|
||||
|
||||
## Hardware information
|
||||
|
||||
* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
|
||||
* [Sandpile](https://www.sandpile.org/)
|
||||
* [CPU-World](https://www.cpu-world.com/index.html)
|
||||
* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
|
||||
|
||||
|
||||
### Hardware Specifications & Standards
|
||||
|
||||
* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
|
||||
* [eMMC](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
|
||||
* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
|
||||
* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
|
||||
[Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
|
||||
* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
|
||||
* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
|
||||
* [Memory](https://www.jedec.org/) - JEDEC - (LOGIN REQUIRED)
|
||||
* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
|
||||
* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
|
||||
* [PCI / PCIe / M.2](https://pcisig.com/specifications) - PCI-SIG - (LOGIN REQUIRED)
|
||||
* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
|
||||
* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
|
||||
* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
|
||||
* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
|
||||
* [USB](https://www.usb.org/documents) - USB Implementers Forum
|
||||
* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
|
||||
|
||||
|
||||
### Chip Vendor Documentation
|
||||
|
||||
* AMD
|
||||
* [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
|
||||
* [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
|
||||
* ARM
|
||||
* [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
|
||||
* Intel
|
||||
* [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
|
||||
* [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
|
||||
* [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
|
||||
* [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
|
||||
|
||||
* Rockchip
|
||||
* [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
|
||||
|
||||
|
||||
## Software
|
||||
|
||||
* [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
|
||||
* [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
|
||||
* [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
|
||||
* [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
|
||||
* [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
|
||||
* [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
|
||||
* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
|
||||
* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
|
||||
|
||||
|
||||
## Infrastructure software
|
||||
|
||||
* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
|
||||
* [GNU Make](https://www.gnu.org/software/make/manual/)
|
@@ -197,4 +197,5 @@ Contents:
|
||||
* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
|
||||
* [Release notes](releases/index.md)
|
||||
* [Acronyms & Definitions](acronyms.md)
|
||||
* [External Resources](external_docs.md)
|
||||
* [Documentation License](documentation_license.md)
|
||||
|
@@ -383,7 +383,7 @@ training. This example expects that the default value of this `register` is set
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
|
||||
if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
|
||||
mupd->ExampleFeature = false;
|
||||
}
|
||||
```
|
||||
|
@@ -85,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
|
||||
## Intel
|
||||
|
||||
- [DG43GT](intel/dg43gt.md)
|
||||
- [IceLake RVP](intel/icelake_rvp.md)
|
||||
- [KBLRVP11](intel/kblrvp11.md)
|
||||
|
||||
## Kontron
|
||||
@@ -185,6 +184,7 @@ The boards in this section are not real mainboards, but emulators.
|
||||
- [StarLite Mk III](starlabs/lite_glk.md)
|
||||
- [StarLite Mk IV](starlabs/lite_glkr.md)
|
||||
- [StarBook Mk V](starlabs/starbook_tgl.md)
|
||||
- [StarBook Mk VI](starlabs/starbook_adl.md)
|
||||
- [Flashing devices](starlabs/common/flashing.md)
|
||||
|
||||
## Supermicro
|
||||
@@ -201,16 +201,22 @@ The boards in this section are not real mainboards, but emulators.
|
||||
- [Bonobo Workstation 14](system76/bonw14.md)
|
||||
- [Darter Pro 6](system76/darp6.md)
|
||||
- [Darter Pro 7](system76/darp7.md)
|
||||
- [Darter Pro 8](system76/darp8.md)
|
||||
- [Galago Pro 4](system76/galp4.md)
|
||||
- [Galago Pro 5](system76/galp5.md)
|
||||
- [Galago Pro 6](system76/galp6.md)
|
||||
- [Gazelle 15](system76/gaze15.md)
|
||||
- [Gazelle 16](system76/gaze16.md)
|
||||
- [Gazelle 17](system76/gaze17.md)
|
||||
- [Lemur Pro 9](system76/lemp9.md)
|
||||
- [Lemur Pro 10](system76/lemp10.md)
|
||||
- [Lemur Pro 11](system76/lemp11.md)
|
||||
- [Oryx Pro 5](system76/oryp5.md)
|
||||
- [Oryx Pro 6](system76/oryp6.md)
|
||||
- [Oryx Pro 7](system76/oryp7.md)
|
||||
- [Oryx Pro 8](system76/oryp8.md)
|
||||
- [Oryx Pro 9](system76/oryp9.md)
|
||||
- [Oryx Pro 10](system76/oryp10.md)
|
||||
|
||||
## Texas Instruments
|
||||
|
||||
|
@@ -1,40 +0,0 @@
|
||||
# Intel Ice Lake RVP (Reference Validation Platform)
|
||||
|
||||
This page describes how to run coreboot on the Intel icelake_rvp board.
|
||||
|
||||
Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
|
||||
```eval_rst
|
||||
:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
|
||||
```
|
||||
|
||||
## Building coreboot
|
||||
|
||||
* Follow build instructions mentioned in Ice Lake document
|
||||
```eval_rst
|
||||
:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
|
||||
```
|
||||
|
||||
* The default options for this board should result in a fully working image:
|
||||
```bash
|
||||
# echo "CONFIG_VENDOR_INTEL=y" > .config
|
||||
# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
|
||||
# make olddefconfig && make
|
||||
```
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
| Socketed flash | no |
|
||||
+---------------------+------------+
|
||||
| Vendor | Winbond |
|
||||
+---------------------+------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+------------+
|
||||
```
|
@@ -26,12 +26,12 @@ host up to 4 Delta Lake servers (blades) in one sled.
|
||||
|
||||
The Yosemite-V3 system is in mass production. Meta, Intel and partners
|
||||
jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
|
||||
solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
|
||||
OSF solution reached production quality for some use cases in July, 2021.
|
||||
solution. The OSF solution reached production quality for some use cases
|
||||
in July, 2021.
|
||||
|
||||
## How to build
|
||||
|
||||
OSF code base is public at
|
||||
OSF code base is publicly available at
|
||||
https://github.com/opencomputeproject/OpenSystemFirmware
|
||||
|
||||
Run following commands to build Delta Lake OSF image from scratch:
|
||||
@@ -42,19 +42,21 @@ The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
|
||||
Linux kernel and u-root code from their upstream repo, and sync down needed
|
||||
binary blobs. [osf-builder] also provides the top level build system.
|
||||
|
||||
Delta Lake server OSF solution requires following binary blobs:
|
||||
- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
|
||||
can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
|
||||
- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
|
||||
coreboot.org mirrors this repo and by default the correct binary is included.
|
||||
- ME binary: Ignition binary can be downloaded from
|
||||
Besides coreboot, the Delta Lake OSF solution includes following components:
|
||||
- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
|
||||
is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
|
||||
- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
|
||||
- ME ignition binary: downloaded from
|
||||
https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
|
||||
- ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
|
||||
- Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
|
||||
U-root as initramfs, is used in the joint development. It can be built
|
||||
U-root as initramfs, is used in the joint development. It is built
|
||||
following [All about u-root].
|
||||
|
||||
## Flashing coreboot
|
||||
The Delta Lake OSF solution is updated periodically to newer versions of
|
||||
upstream coreboot code base and other components.
|
||||
|
||||
## How to verify Delta Lake OSF image
|
||||
|
||||
To do in-band FW image update, use [flashrom]:
|
||||
flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
|
||||
@@ -70,6 +72,21 @@ To power off/on the host:
|
||||
To connect to console through SOL (Serial Over Lan):
|
||||
sol-util slotx
|
||||
|
||||
## How to work on coreboot for Delta Lake
|
||||
After the OSF image for Delta Lake is built and verified, under
|
||||
OpenSystemFirmware/Wiwynn/deltalake directory:
|
||||
cd src/osf-builder/projects/craterlake/coreboot
|
||||
|
||||
Run "git remote -v" to confirm the origin is from coreboot upstream repo.
|
||||
|
||||
Run "git branch -v" to know the confirmed working coreboot commit ID for the
|
||||
Delta Lake OSF solution.
|
||||
|
||||
Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
|
||||
image for Delta Lake, verify that it works.
|
||||
|
||||
Now you are in a familiar coreboot environment, happy coding!
|
||||
|
||||
## Firmware configurations
|
||||
[ChromeOS VPD] is used to store most of the firmware configurations.
|
||||
RO_VPD region holds default values, while RW_VPD region holds customized
|
||||
|
30
Documentation/mainboard/starlabs/common/building.md
Normal file
30
Documentation/mainboard/starlabs/common/building.md
Normal file
@@ -0,0 +1,30 @@
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
|
||||
#### StarBook series:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
* ITE Embedded Controller firmware (ec.bin)
|
||||
|
||||
#### StarLite series:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* IFWI Image (ifwi.rom)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image, where the last two words represent the
|
||||
series and processor i.e. `lite_glkr`:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
|
||||
make
|
||||
```
|
@@ -41,27 +41,7 @@
|
||||
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
* ITE Embedded Controller firmware (ec.bin)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
|
||||
make
|
||||
```
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
|
@@ -38,26 +38,7 @@
|
||||
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
|
||||
The below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
|
||||
make
|
||||
```
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
|
@@ -37,27 +37,7 @@
|
||||
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
* ITE Embedded Controller firmware (ec.bin)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
|
||||
make
|
||||
```
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
|
@@ -37,26 +37,7 @@
|
||||
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* IFWI Image (ifwi.rom)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
|
||||
make
|
||||
```
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
|
88
Documentation/mainboard/starlabs/starbook_adl.md
Normal file
88
Documentation/mainboard/starlabs/starbook_adl.md
Normal file
@@ -0,0 +1,88 @@
|
||||
# StarBook Mk V
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU (full processor specs available at https://ark.intel.com)
|
||||
- Intel i7-1260P (Alder Lake)
|
||||
- Intel i3-1220P (Alder Lake)
|
||||
- EC
|
||||
- ITE IT5570E
|
||||
- Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
|
||||
- Battery
|
||||
- Charger, using AC adapter or USB-C PD
|
||||
- Suspend / resume
|
||||
- GPU
|
||||
- Intel® Iris® Xe Graphics
|
||||
- GOP driver is recommended, VBT is provided
|
||||
- eDP 14-inch 1920x1080 LCD
|
||||
- HDMI video
|
||||
- USB-C DisplayPort video
|
||||
- Memory
|
||||
- 2 x DDR4 SODIMM
|
||||
- Networking
|
||||
- AX210 2230 WiFi / Bluetooth
|
||||
- Sound
|
||||
- Realtek ALC269-VB6
|
||||
- Internal speakers
|
||||
- Internal microphone
|
||||
- Combined headphone / microphone 3.5-mm jack
|
||||
- HDMI audio
|
||||
- USB-C DisplayPort audio
|
||||
- Storage
|
||||
- M.2 PCIe SSD
|
||||
- RTS5129 MicroSD card reader
|
||||
- USB
|
||||
- 1920x1080 CCD camera
|
||||
- USB 3.1 Gen 2 (left)
|
||||
- USB 3.1 Gen 2 Type-A (left)
|
||||
- USB 3.1 Gen 1 Type-A (right)
|
||||
- USB 2.0 Type-A (right)
|
||||
|
||||
## Building coreboot
|
||||
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
* ITE Embedded Controller firmware (ec.bin)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
|
||||
make
|
||||
```
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+------------+
|
||||
| Type | Value |
|
||||
+=====================+============+
|
||||
| Socketed flash | no |
|
||||
+---------------------+------------+
|
||||
| Vendor | Winbond |
|
||||
+---------------------+------------+
|
||||
| Model | W25Q256.V |
|
||||
+---------------------+------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+------------+
|
||||
| Package | SOIC-8 |
|
||||
+---------------------+------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+------------+
|
||||
|
||||
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
|
@@ -40,27 +40,7 @@
|
||||
|
||||
## Building coreboot
|
||||
|
||||
### Preliminaries
|
||||
|
||||
Prior to building coreboot the following files are required:
|
||||
* Intel Flash Descriptor file (descriptor.bin)
|
||||
* Intel Management Engine firmware (me.bin)
|
||||
* ITE Embedded Controller firmware (ec.bin)
|
||||
|
||||
The files listed below are optional:
|
||||
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
|
||||
|
||||
These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
|
||||
|
||||
### Build
|
||||
|
||||
The following commands will build a working image:
|
||||
|
||||
```bash
|
||||
make distclean
|
||||
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
|
||||
make
|
||||
```
|
||||
Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
|
82
Documentation/mainboard/system76/darp8.md
Normal file
82
Documentation/mainboard/system76/darp8.md
Normal file
@@ -0,0 +1,82 @@
|
||||
# Syste76 Darter Pro 8 (darp8)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i5-1240P
|
||||
- Intel Core i7-1260P
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- Intel Iris Xe Graphics
|
||||
- eDP 15.6" 1920x1080@60Hz LCD
|
||||
- 1x HDMI
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
|
||||
- Networking
|
||||
- Gigabit Ethernet
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
|
||||
- Power
|
||||
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
|
||||
- USB-C charging, compatible with 65W+ chargers
|
||||
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
|
||||
- Sound
|
||||
- Realtek ALC256 codec
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone/microphone jack
|
||||
- HDMI, USB-C DisplayPort audio
|
||||
- Storage
|
||||
- M.2 PCIe NVMe Gen 4 SSD
|
||||
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
|
||||
- MicroSD card reader (OZ711LV2)
|
||||
- USB
|
||||
- 1x USB-C Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 (Gen 2) Type-C
|
||||
- 1x USB 3.2 (Gen 2) Type-A
|
||||
- 1x USB 2.0 Type-A
|
||||
- Dimensions
|
||||
- 35.7cm x 22.05cm x 1.99cm, 1.74kg
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | GigaDevice |
|
||||
+---------------------+---------------------+
|
||||
| Model | GD25B256E |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | Winbond |
|
||||
+---------------------+---------------------+
|
||||
| Model | W25Q256.V |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U19) is above the left DIMM slot.
|
61
Documentation/mainboard/system76/galp6.md
Normal file
61
Documentation/mainboard/system76/galp6.md
Normal file
@@ -0,0 +1,61 @@
|
||||
# System76 Galago Pro 6 (galp6)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i5-1240P
|
||||
- Intel Core i7-1260P
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- Intel Iris Xe Graphics
|
||||
- eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
|
||||
- 1x HDMI 2.1
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
|
||||
- Networking
|
||||
- Gigabit Ethernet
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
|
||||
- Power
|
||||
- 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
|
||||
- USB-C charging, compatible with 90W+ chargers
|
||||
- 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
|
||||
- Sound
|
||||
- Realtek ALC256 codec
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone/microphone jack
|
||||
- HDMI, USB-C DisplayPort audio
|
||||
- Storage
|
||||
- M.2 PCIe NVMe Gen 4 SSD
|
||||
- MicroSD card reader (OZ711LV2)
|
||||
- USB
|
||||
- 1x USB-C Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 (Gen 2) Type-C
|
||||
- 2x USB 3.2 (Gen 1) Type-A
|
||||
- Dimensions
|
||||
- 32.49cm x 22.5cm x 1.82cm, 1.45kg
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | Macronix |
|
||||
+---------------------+---------------------+
|
||||
| Model | MX25L25673G |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U43) is left of the wireless card.
|
65
Documentation/mainboard/system76/gaze17.md
Normal file
65
Documentation/mainboard/system76/gaze17.md
Normal file
@@ -0,0 +1,65 @@
|
||||
# System76 Gazelle 17 (gaze17)
|
||||
|
||||
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i5-12500H
|
||||
- Intel Core i7-12700H
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- dGPU options
|
||||
- NVIDIA GeForce RTX 3050
|
||||
- NVIDIA GeForce RTX 3050 Ti
|
||||
- NVIDIA GeForce RTX 3060
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
|
||||
- Networking
|
||||
- Gigabit Ethernet
|
||||
- 3050: Realtek RTL8111H controller
|
||||
- 3060: Onboard Intel I219-V
|
||||
- M.2 PCIe/CNVi WiFi/Bluetooth
|
||||
- Intel Wi-Fi 6 AX201
|
||||
- Power
|
||||
- 3050: 150W (20V, 7.5A) AC barrel adapter
|
||||
- 3060: 180W (20V, 9A) AC barrel adapter
|
||||
- Lite-On PA-1181-76, using a C5 power cord
|
||||
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
|
||||
- Sound
|
||||
- Realtek ALC256 codec
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone/microphone jack
|
||||
- Dedicated 3.5mm microphone jack
|
||||
- Storage
|
||||
- 1x M.2 PCIe NVMe Gen 4 SSD
|
||||
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
|
||||
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | GigaDevice |
|
||||
+---------------------+---------------------+
|
||||
| Model | GD25B256E |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The position of the flash chip depends on the variant:
|
||||
|
||||
- 3050: U24, below the bottom DIMM slot.
|
||||
- 3060: U55, left of the PCIe 4.0 M.2 slot.
|
62
Documentation/mainboard/system76/lemp11.md
Normal file
62
Documentation/mainboard/system76/lemp11.md
Normal file
@@ -0,0 +1,62 @@
|
||||
# System76 Lemur Pro 11 (lemp11)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i5-1235U
|
||||
- Intel Core i7-1255U
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- Intel Iris Xe Graphics
|
||||
- eDP 14.0" 1920x1080@60Hz LCD
|
||||
- 1x HDMI 2.1
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
|
||||
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
|
||||
- Networking
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
|
||||
- Power
|
||||
- 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
|
||||
- USB-C charging, compatible with 65W+ chargers
|
||||
- 73Wh 4-cell Lithium-ion battery (L140BAT-4)
|
||||
- Sound
|
||||
- Realtek ALC256 codec
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5 mm headphone/microphone jack
|
||||
- HDMI, USB-C DisplayPort audio
|
||||
- Storage
|
||||
- M.2 PCIe NVMe Gen 4 SSD
|
||||
- M.2 PCIe NVMe Gen 3 or SATA 3 SSD
|
||||
- MicroSD card reader (RTS5227S)
|
||||
- USB
|
||||
- 1x USB Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 (Gen 2) Type-A
|
||||
- 1x USB 3.2 (Gen 1) Type-A
|
||||
- Dimensions
|
||||
- 1.65cm x 32.2cm x 21.68cm, 1.15kg
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | Macronix |
|
||||
+---------------------+---------------------+
|
||||
| Model | MX25L25673G |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U41) is left of the DIMM slot.
|
69
Documentation/mainboard/system76/oryp10.md
Normal file
69
Documentation/mainboard/system76/oryp10.md
Normal file
@@ -0,0 +1,69 @@
|
||||
# System76 Oryx Pro 10 (oryp10)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i7-12700H
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- dGPU options:
|
||||
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
|
||||
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
|
||||
- eDP options:
|
||||
- 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
|
||||
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
|
||||
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
|
||||
- 1x HDMI 2.1
|
||||
- 1x Mini DisplayPort 1.4
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
|
||||
- Networking
|
||||
- Gigabit Ethernet
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
|
||||
- Power
|
||||
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
|
||||
- 80Wh 6-cell Lithium-ion battery
|
||||
- Sound
|
||||
- Realtek ALC1220 codec
|
||||
- Realtek ALC1306 smart amp
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone & microphone jack
|
||||
- Combined 3.5mm microphone & S/PDIF jack
|
||||
- HDMI, mDP, USB-C DP audio
|
||||
- Storage
|
||||
- 2x M.2 PCIe NVMe Gen 4 SSD
|
||||
- MicroSD card reader (RTS5227S)
|
||||
- USB
|
||||
- 1x USB Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 (Gen 2) Type-C
|
||||
- 2x USB 3.2 (Gen 1) Type-A
|
||||
- Dimensions
|
||||
- 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
|
||||
- 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
|
||||
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | Macronix |
|
||||
+---------------------+---------------------+
|
||||
| Model | MX25L25673G |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U61) is left of the DIMM slots.
|
67
Documentation/mainboard/system76/oryp9.md
Normal file
67
Documentation/mainboard/system76/oryp9.md
Normal file
@@ -0,0 +1,67 @@
|
||||
# System76 Oryx Pro 9 (oryp9)
|
||||
|
||||
## Specs
|
||||
|
||||
- CPU
|
||||
- Intel Core i7-12700H
|
||||
- EC
|
||||
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
|
||||
- Graphics
|
||||
- dGPU options:
|
||||
- NVIDIA GeForce RTX 3070 Ti (Max-Q)
|
||||
- NVIDIA GeForce RTX 3080 Ti (Max-Q)
|
||||
- eDP options:
|
||||
- 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
|
||||
- 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
|
||||
- 1x HDMI 2.1
|
||||
- 1x Mini DisplayPort 1.4
|
||||
- 1x DisplayPort 1.4 over USB-C
|
||||
- Memory
|
||||
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
|
||||
- Networking
|
||||
- Gigabit Ethernet
|
||||
- M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
|
||||
- Power
|
||||
- 230W (20V, 11.5A) AC barrel adapter (Lite-On PA-1231-26)
|
||||
- 80Wh 6-cell Lithium-ion battery
|
||||
- Sound
|
||||
- Realtek ALC1220 codec
|
||||
- TI TAS5825M smart amp
|
||||
- Internal speakers and microphone
|
||||
- Combined 3.5mm headphone & microphone jack
|
||||
- Combined 3.5mm microphone & S/PDIF jack
|
||||
- HDMI, mDP, USB-C DP audio
|
||||
- Storage
|
||||
- 2x M.2 PCIe NVMe Gen 4 SSD
|
||||
- MicroSD card reader (RTS5227S)
|
||||
- USB
|
||||
- 1x USB Type-C with Thunderbolt 4
|
||||
- 1x USB 3.2 (Gen 2) Type-C
|
||||
- 2x USB 3.2 (Gen 1) Type-A
|
||||
- Dimensions
|
||||
- 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
|
||||
- 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+---------------------+---------------------+
|
||||
| Type | Value |
|
||||
+=====================+=====================+
|
||||
| Socketed flash | no |
|
||||
+---------------------+---------------------+
|
||||
| Vendor | Macronix |
|
||||
+---------------------+---------------------+
|
||||
| Model | MX25L25673G |
|
||||
+---------------------+---------------------+
|
||||
| Size | 32 MiB |
|
||||
+---------------------+---------------------+
|
||||
| Package | WSON-8 |
|
||||
+---------------------+---------------------+
|
||||
| Internal flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
| External flashing | yes |
|
||||
+---------------------+---------------------+
|
||||
```
|
||||
|
||||
The flash chip (U61) is left of the DIMM slots.
|
@@ -12,16 +12,59 @@ desired.
|
||||
|
||||
Currently, [jenkins](https://qa.coreboot.org), our continuous
|
||||
integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
|
||||
and 4.16 branches. Builders for other branches can be created on
|
||||
4.16, and 4.18 branches. Builders for other branches can be created on
|
||||
request. Likewise, some releases are only marked with tags, and
|
||||
branches would need to be created to push new code to. These branches
|
||||
can also be created on request.
|
||||
|
||||
Patches can be backported from the master branch to any of these other
|
||||
branches as needed. The coreboot project will take care of backporting
|
||||
branches as needed. The coreboot project may take care of backporting
|
||||
critical security fixes, but other patches will need to handled by
|
||||
anyone using that release.
|
||||
|
||||
|
||||
## [4.18 Release](coreboot-4.18-relnotes.md)
|
||||
Branch created, builder configured
|
||||
|
||||
```eval_rst
|
||||
+-------------------------------+------------------------+------------+-----------+
|
||||
| Vendor/Board | Processor | Date added | Brd type |
|
||||
+===============================+========================+============+===========+
|
||||
| amd/inagua | AMD_FAMILY14 | 2011-02-14 | eval |
|
||||
| amd/olivehill | AMD_FAMILY16_KB | 2013-08-05 | eval |
|
||||
| amd/parmer | AMD_FAMILY15_TN | 2012-07-22 | eval |
|
||||
| amd/persimmon | AMD_FAMILY14 | 2011-02-14 | eval |
|
||||
| amd/south_station | AMD_FAMILY14 | 2011-11-18 | eval |
|
||||
| amd/thatcher | AMD_FAMILY15_TN | 2012-08-02 | eval |
|
||||
| amd/union_station | AMD_FAMILY14 | 2011-11-18 | eval |
|
||||
| asrock/e350m1 | AMD_FAMILY14 | 2011-02-24 | mini |
|
||||
| asrock/imb-a180 | AMD_FAMILY16_KB | 2013-08-27 | mini |
|
||||
| asus/a88xm-e | AMD_FAMILY15_TN | 2020-08-13 | desktop |
|
||||
| asus/am1i-a | AMD_FAMILY16_KB | 2018-01-14 | mini |
|
||||
| asus/f2a85-m | AMD_FAMILY15_TN | 2013-03-22 | desktop |
|
||||
| bap/ode_e20XX | AMD_FAMILY16_KB | 2015-05-27 | eval |
|
||||
| biostar/a68n_5200 | AMD_FAMILY16_KB | 2017-10-14 | eval |
|
||||
| biostar/am1ml | AMD_FAMILY16_KB | 2015-04-10 | mini |
|
||||
| elmex/pcm205400 | AMD_FAMILY14 | 2016-09-29 | sbc |
|
||||
| gizmosphere/gizmo2 | AMD_FAMILY16_KB | 2014-12-09 | eval |
|
||||
| gizmosphere/gizmo | AMD_FAMILY14 | 2014-01-03 | half |
|
||||
| hp/abm | AMD_FAMILY16_KB | 2015-01-05 | mini |
|
||||
| hp/pavilion_m6_1035dx | AMD_FAMILY15_TN | 2014-03-28 | laptop |
|
||||
| jetway/nf81-t56n-lf | AMD_FAMILY14 | 2014-02-16 | mini |
|
||||
| lenovo/g505s | AMD_FAMILY15_TN | 2014-11-27 | laptop |
|
||||
| lippert/frontrunner-af | AMD_FAMILY14 | 2013-03-02 | half |
|
||||
| msi/ms7721 | AMD_FAMILY15_TN | 2016-11-22 | desktop |
|
||||
| pcengines/apu1 | AMD_FAMILY14 | 2015-02-23 | half |
|
||||
+-------------------------------+------------------------+------------+-----------+
|
||||
```
|
||||
|
||||
|
||||
## [4.17 Release](coreboot-4.17-relnotes.md)
|
||||
No Branch or builder
|
||||
|
||||
* No platforms maintained on this release
|
||||
|
||||
|
||||
## [4.16 Release](coreboot-4.16-relnotes.md)
|
||||
Branch created, builder configured
|
||||
|
||||
|
@@ -4,56 +4,73 @@
|
||||
|
||||
# coreboot Release Process
|
||||
|
||||
This document describes our release process and all prerequisites to implement
|
||||
it successfully.
|
||||
This document describes our release process and all prerequisites to
|
||||
implement it successfully.
|
||||
|
||||
|
||||
## Purpose of coreboot releases
|
||||
Our releases aren't primarily a vehicle for code that is stable across all
|
||||
boards: The logistics of testing the more than 100 boards that are spread out
|
||||
all continents (except Antarctica, probably) on a given tree state are
|
||||
prohibitive for project of our size.
|
||||
Our releases aren't primarily a vehicle for code that is stable across
|
||||
all boards: The logistics of testing the more than 100 boards that are
|
||||
spread out all continents (except Antarctica, probably) on a given tree
|
||||
state are prohibitive for project of our size.
|
||||
|
||||
Instead, the releases are regular breakpoints that serve multiple purposes:
|
||||
They support cooperation between multiple groups (corporations or otherwise)
|
||||
in that it's easier to keep source trees synchronized based on a limited set
|
||||
of commits. They allow a quick assessment of the age of any given build or
|
||||
source tree based on its git version (4.8-1234 was merged into master a few
|
||||
months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
|
||||
guess).
|
||||
Instead, the releases are regular breakpoints that serve multiple
|
||||
purposes: They support cooperation between multiple groups (corporations
|
||||
or otherwise) in that it's easier to keep source trees synchronized
|
||||
based on a limited set of commits. They allow a quick assessment of the
|
||||
age of any given build or source tree based on its git version (4.8-1234
|
||||
was merged into master a few months after 4.8, which came out in April
|
||||
of 2018. 4.0-21718's age is harder to guess).
|
||||
|
||||
And finally we use releases to as points in time where we remove old code:
|
||||
Once we decide that a certain part of coreboot gets in the way of future
|
||||
development, we announce on the next release that we intend to remove that
|
||||
part - and everything that depends on it - after the following release.
|
||||
So removing feature FOO will be announced in release X for release
|
||||
X+1. The first commit after X+1 is fair game for such removal.
|
||||
And finally we use releases to as points in time where we remove old
|
||||
code: Once we decide that a certain part of coreboot gets in the way of
|
||||
future development, we announce on the next release that we intend to
|
||||
remove that part - and everything that depends on it - after the
|
||||
following release. So removing feature FOO will be announced in release
|
||||
X for release X+1. The first commit after X+1 is fair game for such
|
||||
removal.
|
||||
|
||||
Together with our 6 months release horizon, this provides time to plan
|
||||
Together with our 3 months release horizon, this provides time to plan
|
||||
any migrations necessary to keep older boards in the tree by bringing
|
||||
them up to current standards.
|
||||
|
||||
## coreboot release team
|
||||
To avoid issues of blocking the release on a single person, a release
|
||||
team has been formed. Please see the `COREBOOT RELEASES` section of the
|
||||
MAINTAINERS file for the current members.
|
||||
|
||||
These individuals work together to make sure releases are done on time,
|
||||
follow the steps of this document, and update the release processes and
|
||||
scripts.
|
||||
|
||||
|
||||
## Needed credentials & authorizations
|
||||
|
||||
### coreboot admins only
|
||||
* Website access is required to post the release files to the website.
|
||||
* IRC admin access is required to update the topic.
|
||||
|
||||
### All release team members
|
||||
* IRC topic access is required to update the topic.
|
||||
* Git access rights are needed to post the tag.
|
||||
* Blog post access is needed to do the blog post.
|
||||
* A PGP key is required to sign the release tarballs and git tag.
|
||||
|
||||
This set of required credentials implies that releases can only be done
|
||||
by a coreboot admin.
|
||||
Most of the steps in the release process can be done by anyone on the
|
||||
release team. Only adding the files to the website needs to be done
|
||||
by a coreboot administrator.
|
||||
|
||||
## When to release
|
||||
Releases are done roughly on a 6-month schedule, ideally around end
|
||||
of April and end of October (can be a bit earlier or delay into May
|
||||
or November).
|
||||
Releases are done roughly on a 3-month schedule. If a release is
|
||||
delayed, the next release will still be 3 months after the last release.
|
||||
|
||||
We initially followed a 3 month release schedule, but we found that to
|
||||
be more frequent than was needed, so we scaled it back to twice a year.
|
||||
|
||||
## Checklist
|
||||
|
||||
### ~2 weeks prior to release
|
||||
- [ ] Announce upcoming release to mailing list, ask people to test and
|
||||
to update release notes.
|
||||
- [ ] Start marking patches that should to go into the release with a
|
||||
tag "coreboot_release_X.yy"
|
||||
|
||||
### ~1 week prior to release
|
||||
- [ ] Send reminder email to mailing list, ask for people to test,
|
||||
@@ -66,28 +83,53 @@ be more frequent than was needed, so we scaled it back to twice a year.
|
||||
- [ ] Finalize release notes as much as possible
|
||||
- [ ] Prepare release notes template for following release
|
||||
- [ ] Update `Documentation/releases/index.md`
|
||||
- [ ] Check which branches need to be released. Any branch with changes
|
||||
should get a new release. Announce these branch releases and
|
||||
prepare release notes.
|
||||
|
||||
### Day before release
|
||||
- [ ] Make sure patches with tags for the release are merged.
|
||||
- [ ] Announce to IRC that the release will be tomorrow and ask for
|
||||
testing.
|
||||
- [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
|
||||
boards supported by vboot.
|
||||
|
||||
### Day of release
|
||||
- [ ] Select a commit ID to base the release upon, announce to IRC,
|
||||
ask for testing.
|
||||
- [ ] Review the full documentation about doing the release below.
|
||||
- [ ] Select a commit ID to base the release upon.
|
||||
- [ ] Test the commit selected for release.
|
||||
- [ ] Submit release notes
|
||||
- [ ] Create new release notes doc template for the next version.
|
||||
- [ ] Fill in the release date, remove "Upcoming release" and other filler
|
||||
from the current release notes.
|
||||
- [ ] Run release script.
|
||||
- [ ] Submit last pre-release release notes.
|
||||
- [ ] Run the release script.
|
||||
- [ ] Test the release from the actual release tarballs.
|
||||
- [ ] Push signed Tag to repo.
|
||||
- [ ] Push signed Tag to repo. *This is the actual release step.*
|
||||
Once this patch is pushed, the release itself has been done.
|
||||
everything after this step is packaging and delivering the
|
||||
release.
|
||||
|
||||
- [ ] Announce that the release tag is done on IRC.
|
||||
- [ ] Upload release files to web server.
|
||||
- [ ] Also extract the release notes and place them on the web server.
|
||||
- [ ] Upload crossgcc sources to web server.
|
||||
- [ ] Update download page to point to files, push to repo.
|
||||
- [ ] Write and publish blog post with release notes.
|
||||
- [ ] Update the topic in the IRC channel that the release is done.
|
||||
- [ ] Announce the release to the mailing list.
|
||||
|
||||
- [ ] Do the final release notes - Fill in the release date, remove
|
||||
"Upcoming release" and other filler from the current release
|
||||
notes.
|
||||
- [ ] ADMIN: Upload release files to web server.
|
||||
- [ ] ADMIN: Upload the final release notes to the web server.
|
||||
- [ ] ADMIN: Upload crossgcc sources to web server.
|
||||
- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images
|
||||
based on the release ID and push them to dockerhub. These
|
||||
can be used as release builders.
|
||||
|
||||
### Week following the release
|
||||
- [ ] Update download page to point to files, push to repo.
|
||||
- [ ] Write and publish blog post with release final notes. Branch
|
||||
releases notes should be included in the same post.
|
||||
- [ ] Remove code that was announced it was going to be removed.
|
||||
- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
|
||||
|
||||
### Creating a branch
|
||||
- [ ] Branches are named 4.xx_branch to differentiate from the tags.
|
||||
Instructions on creating branches are listed below.
|
||||
|
||||
|
||||
## Pre-Release tasks
|
||||
Announce the upcoming release to the mailing list release 2 weeks ahead
|
||||
@@ -102,29 +144,30 @@ People should be encouraged to provide additions to the release notes.
|
||||
|
||||
The final release notes will reside in coreboot's Documentation/releases
|
||||
directory, so asking for additions to that through the regular Gerrit
|
||||
process works as well. Note that git requires lots of conflict resolution
|
||||
on heavily edited text files though.
|
||||
process works as well. Note that git requires lots of conflict
|
||||
resolution on heavily edited text files though.
|
||||
|
||||
Frequently, we will want to wait until particular things are in the
|
||||
release. Once those are in, you can select the commit ID that you want
|
||||
to use for your release. For the 4.6 release, we waited until we had
|
||||
release. Once those are in, you can select the commit ID that you want
|
||||
to use for your release. For the 4.6 release, we waited until we had
|
||||
time to do the release, then pulled in a few patches that we wanted
|
||||
to have in the release. The release was based on the final of those
|
||||
to have in the release. The release was based on the final of those
|
||||
patches to be pulled in.
|
||||
|
||||
When a release candidate has been selected, announce the commit ID to
|
||||
the #coreboot IRC channel, and request that it get some testing, just
|
||||
to make sure that everything is sane.
|
||||
|
||||
|
||||
## Generate the release
|
||||
After the commit for the release has been selected and verified, run the
|
||||
release script - util/release/build-release. This will download a new
|
||||
release script - util/release/build-release. This will download a new
|
||||
tree, checkout the commit that you specified, download the submodules,
|
||||
create a tag, then generate and sign the tarballs.
|
||||
|
||||
Be prepared to type in your PGP key’s passphrase.
|
||||
**Be prepared to type in your PGP key’s passphrase.**
|
||||
|
||||
````
|
||||
```text
|
||||
usage: util/release/build-release <version> [commit id] [username] [gpg key id]
|
||||
Tags a new coreboot version and creates a tar archive
|
||||
|
||||
@@ -132,37 +175,41 @@ version: New version name to tag the tree with
|
||||
commit id: check out this commit-id after cloning the coreboot tree
|
||||
username: clone the tree using ssh://USERNAME - defaults to https://
|
||||
gpg key id: used to tag the version, and generate a gpg signature
|
||||
````
|
||||
```
|
||||
|
||||
After running the script, you should have a new directory for the release,
|
||||
along with 4 files - 2 tarballs, and 2 signature files.
|
||||
After running the script, you should have a new directory for the
|
||||
release, along with 4 files: 2 tarballs, and 2 signature files.
|
||||
|
||||
````
|
||||
```text
|
||||
drwxr-xr-x 9 martin martin 4096 Apr 30 19:57 coreboot-4.6
|
||||
-rw-r--r-- 1 martin martin 29156788 Apr 30 19:58 coreboot-4.6.tar.xz
|
||||
-rw-r--r-- 1 martin martin 836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
|
||||
-rw-r--r-- 1 martin martin 5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
|
||||
-rw-r--r-- 1 martin martin 836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
|
||||
````
|
||||
```
|
||||
|
||||
Here’s the command that was used to generate the 4.6 release:
|
||||
````
|
||||
% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
|
||||
````
|
||||
```bash
|
||||
util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
|
||||
```
|
||||
|
||||
|
||||
## Test the release from the tarballs
|
||||
* Run “make what-jenkins-does” and verify that everything is building.
|
||||
* Build and test qemu
|
||||
````
|
||||
cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
|
||||
qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
|
||||
````
|
||||
```bash
|
||||
cp configs/config.emulation_qemu_x86_i440fx .config
|
||||
make olddefconfig
|
||||
make
|
||||
qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
|
||||
```
|
||||
* Build and test any other platforms you can.
|
||||
* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
|
||||
* Compare the directory from the tarballs to the coreboot repo to make
|
||||
sure nothing went wrong.
|
||||
* Push the tag to git
|
||||
|
||||
A good tag will look like this:
|
||||
````
|
||||
````text
|
||||
% git show 4.6
|
||||
tag 4.6
|
||||
Tagger: Martin Roth <martinroth@google.com>
|
||||
@@ -183,33 +230,44 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
|
||||
...
|
||||
````
|
||||
|
||||
When you used the script to generate the release, a signed tag was generated in the
|
||||
tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
|
||||
In case you pushed the wrong tag already, you have to force push the new one.
|
||||
When you used the script to generate the release, a signed tag was
|
||||
generated in the tree that was downloaded. From the coreboot-X.Y tree,
|
||||
just run: `git push origin X.Y`. In case you pushed the wrong tag
|
||||
already, you have to force push the new one.
|
||||
|
||||
You will need write access for tags to the coreboot git repo to do this.
|
||||
|
||||
|
||||
## After the release is tagged in git
|
||||
Announce that the release has been tagged - this lets people know that
|
||||
they should update their trees to grab the new tag. Until they do this,
|
||||
they should update their trees to grab the new tag. Until they do this,
|
||||
the version number in build.h will still be based on the previous tag.
|
||||
|
||||
Copy the tarballs and .sig files generated by the script to
|
||||
the coreboot server, and put them in the release directory at
|
||||
`/srv/docker/www.coreboot.org-staticfiles/releases/`
|
||||
|
||||
````
|
||||
% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
|
||||
% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
|
||||
% mv sha256suma.txt sha256sum.txt
|
||||
````bash
|
||||
# Update the sha256sum file
|
||||
sha256sum -b coreboot-*.tar.xz > sha256suma.txt
|
||||
|
||||
# make sure the two new files are present (and nothing else has changed)
|
||||
diff sha256sum.txt sha256suma.txt
|
||||
|
||||
mv sha256suma.txt sha256sum.txt
|
||||
````
|
||||
|
||||
People can now see the release tarballs on the website at
|
||||
<https://www.coreboot.org/releases/>
|
||||
|
||||
The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
|
||||
The downloads page is the official place to download the releases from,
|
||||
and it needs to be updated with links to the new release tarballs and
|
||||
.sig files. It can be found at:
|
||||
<https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
|
||||
|
||||
Here is an example commit to change it:
|
||||
<https://review.coreboot.org/c/homepage/+/19515>
|
||||
|
||||
Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
|
||||
|
||||
## Upload crossgcc sources
|
||||
Sometimes the source files for older revisions of
|
||||
@@ -219,24 +277,32 @@ sources used by the crossgcc scripts that are part of coreboot releases.
|
||||
|
||||
Run
|
||||
|
||||
````
|
||||
% util/crossgcc/buildgcc -u
|
||||
````bash
|
||||
util/crossgcc/buildgcc -u
|
||||
````
|
||||
|
||||
This will output the set of URLs that the script uses to download the
|
||||
sources. Download them yourself and copy them into the crossgcc-sources
|
||||
directory on the server.
|
||||
|
||||
|
||||
## After the release is complete
|
||||
Post the release notes on <https://blogs.coreboot.org>
|
||||
Post the final release notes on <https://blogs.coreboot.org>
|
||||
|
||||
|
||||
## Making a branch
|
||||
At times we will need to create a branch, generally for patch fixes.
|
||||
When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git can’t tell whether you want the tag or the branch.
|
||||
Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
|
||||
When making a branch, do NOT name it the same as the release tag: X.Y -
|
||||
this creates trouble when trying to check it out, as git can’t tell
|
||||
whether you want the tag or the branch. Instead, name it X.Y\_branch:
|
||||
```bash
|
||||
git checkout 4.8
|
||||
git checkout -b 4.8_branch
|
||||
git push origin 4.8_branch
|
||||
```
|
||||
|
||||
You can then cherry-pick changes and push them up to the branch:
|
||||
````
|
||||
````bash
|
||||
git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
|
||||
git push origin HEAD:refs/for/4.8_branch
|
||||
````
|
||||
|
@@ -296,6 +296,36 @@ noting, but not needing a full description.
|
||||
* sandybridge & gm45: Support setting PCI bars above 4G
|
||||
|
||||
|
||||
Plans to move platform support to a branch:
|
||||
-------------------------------------------
|
||||
After the 4.18 release in November 2022, we plan to move support for any
|
||||
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
|
||||
introduced more than a year ago and with minor changes most platforms
|
||||
were able to work just fine with it. A major difference is that V3 uses
|
||||
just one continuous region below 4G to allocate all PCI memory BAR's. V4
|
||||
uses all available space below 4G and if asked to, also above 4G too.
|
||||
This makes it important that SoC code properly reports all fixed
|
||||
resources.
|
||||
|
||||
Currently only AGESA platforms have issues with it. On Gerrit both
|
||||
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
|
||||
inside the V4 allocator have been proposed, but both efforts seem
|
||||
stalled. See the (not yet merged) documentation
|
||||
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
|
||||
details. It looks like properly reporting all fixed resources is the
|
||||
issue.
|
||||
|
||||
At this point, we are not specifying which platforms this will include
|
||||
as there are a number of patches to fix these issues in flight.
|
||||
Hopefully, all platforms will end up being migrated to the V4 resource
|
||||
allocator so that none of the platforms need to be supported on the
|
||||
branch.
|
||||
|
||||
Additionally, even if the support for the platform is moved to a branch,
|
||||
it can be brought back to ToT if they're fixed to support the V4
|
||||
allocator.
|
||||
|
||||
|
||||
Plans for Code Deprecation
|
||||
--------------------------
|
||||
|
||||
|
@@ -1,11 +1,11 @@
|
||||
Upcoming release - coreboot 4.18 release
|
||||
coreboot 4.18 release
|
||||
========================================================================
|
||||
|
||||
The 4.18 release is quite late, but is now planned for October 16, 2022.
|
||||
The 4.18 release was quite late, but was completed on October 16, 2022.
|
||||
|
||||
In the past 4 months since the 4.17 release, the coreboot project has
|
||||
merged more than 1800 commits from over 200 different authors. Over 50
|
||||
of those authors submitted their first patches.
|
||||
In the 4 months since the 4.17 release, the coreboot project has merged
|
||||
more than 1800 commits from over 200 different authors. Over 50 of those
|
||||
authors submitted their first patches.
|
||||
|
||||
Welcome and thank you to all of our new contributors, and of course the
|
||||
work of all of the seasoned contributors is greatly appreciated.
|
||||
@@ -195,6 +195,36 @@ the same increases maintenance burden on the community a lot, while also
|
||||
being rather confusing.
|
||||
|
||||
|
||||
Plans to move platform support to a branch:
|
||||
-------------------------------------------
|
||||
After the 4.18 release in November 2022, we plan to move support for any
|
||||
boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch. V4 was
|
||||
introduced more than a year ago and with minor changes most platforms
|
||||
were able to work just fine with it. A major difference is that V3 uses
|
||||
just one continuous region below 4G to allocate all PCI memory BAR's. V4
|
||||
uses all available space below 4G and if asked to, also above 4G too.
|
||||
This makes it important that SoC code properly reports all fixed
|
||||
resources.
|
||||
|
||||
Currently only AGESA platforms have issues with it. On Gerrit both
|
||||
attempts to fix AMD AGESA codebases to use V4 and compatibility modes
|
||||
inside the V4 allocator have been proposed, but both efforts seem
|
||||
stalled. See the (not yet merged) documentation
|
||||
[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
|
||||
details. It looks like properly reporting all fixed resources is the
|
||||
issue.
|
||||
|
||||
At this point, we are not specifying which platforms this will include
|
||||
as there are a number of patches to fix these issues in flight.
|
||||
Hopefully, all platforms will end up being migrated to the v4 resource
|
||||
allocator so that none of the platforms need to be supported on the
|
||||
branch.
|
||||
|
||||
Additionally, even if the support for the platform is moved to a branch,
|
||||
it can be brought back to ToT if they're fixed to support the v4
|
||||
allocator.
|
||||
|
||||
|
||||
### Intel Icelake SoC & Icelake RVP mainboard
|
||||
|
||||
Intel Icelake is unmaintained. Also, the only user of this platform ever
|
||||
@@ -222,15 +252,37 @@ be maintained on the release 4.20 branch.
|
||||
* Intel Galileo mainboard
|
||||
|
||||
|
||||
Statistics
|
||||
----------
|
||||
Statistics from commit d2d9021543 to f4c97ea131
|
||||
-----------------------------------------------
|
||||
|
||||
- Total Commits: 1819
|
||||
- Average Commits per day: 13.44
|
||||
- Total lines added: 150195
|
||||
- Average lines added per commit: 82.57
|
||||
- Number of patches adding more than 100 lines: 127
|
||||
- Average lines added per small commit: 38.38
|
||||
- Total lines removed: 33788
|
||||
- Total Commits: 1822
|
||||
- Average Commits per day: 13.38
|
||||
- Total lines added: 150578
|
||||
- Average lines added per commit: 82.64
|
||||
- Number of patches adding more than 100 lines: 128
|
||||
- Average lines added per small commit: 38.44
|
||||
- Total lines removed: 33849
|
||||
- Average lines removed per commit: 18.58
|
||||
- Total difference between added and removed: 116407
|
||||
- Total difference between added and removed: 116729
|
||||
- Total authors: 202
|
||||
- New authors: 52
|
||||
|
||||
|
||||
Known Issues
|
||||
------------
|
||||
|
||||
A couple of issues were discovered immediately following the release
|
||||
that will be fixed in a follow-on point release in the upcoming weeks.
|
||||
|
||||
A pair of changes ([CB:67754](https://review.coreboot.org/67754) and
|
||||
[CB:67662](https://review.coreboot.org/67662)) which merged shortly
|
||||
before the 4.18 release have created an issue on Intel Apollo Lake
|
||||
platform boards which prevents SMM/SMI from functioning; this affects
|
||||
only Apollo Lake (but not Gemini Lake) devices.
|
||||
See [CB:68599](https://review.coreboot.org/68599) for the fix.
|
||||
|
||||
Another issue applies to all Intel-based boards with onboard I2C TPMs
|
||||
when verified boot is not enabled. The I2C buses don’t get initialized
|
||||
until after the TPM, causing timeouts, TPM initialization failures, and
|
||||
long boot times. See [CB:68550](https://review.coreboot.org/68550) for
|
||||
the fix.
|
||||
|
@@ -1,51 +1,187 @@
|
||||
Upcoming release - coreboot 4.19
|
||||
========================================================================
|
||||
|
||||
The 4.19 release is planned for January 2023.
|
||||
The 4.19 release is planned for the 16th of January 2023.
|
||||
|
||||
Update this document with changes that should be in the release notes.
|
||||
Since the last release, the coreboot project has merged over 1600
|
||||
commits from over 150 authors. Of those authors, around 25 were
|
||||
first-time committers to the coreboot project.
|
||||
|
||||
* Please use Markdown.
|
||||
* See the past few release notes for the general format.
|
||||
* The chip and board additions and removals will be updated right
|
||||
before the release, so those do not need to be added.
|
||||
* Note that all changes before the release are done are marked upcoming.
|
||||
A final version of the notes are done after the release.
|
||||
As always, we are very grateful to all of the contributors for helping
|
||||
to keep the project going. The coreboot project is different from many
|
||||
open source projects in that we need to keep constantly updating the
|
||||
codebase to stay relevant with the latest processors and technologies.
|
||||
It takes constant effort to just stay afloat, let alone improve the
|
||||
codebase. Thank you very much to everyone who has contributed, both in
|
||||
this release and in previous times.
|
||||
|
||||
Significant changes
|
||||
-------------------
|
||||
The 4.20 release is planned for the 20th of April, 2023.
|
||||
|
||||
### Add significant changes here
|
||||
|
||||
Significant or interesting changes
|
||||
----------------------------------
|
||||
|
||||
|
||||
### Show all Kconfig options in saved config file; compress same
|
||||
|
||||
The coreboot build system automatically adds a 'config' file to CBFS
|
||||
that lists the exact Kconfig configuration that the image was built
|
||||
with. This is useful to reproduce a build after the fact or to check
|
||||
whether support for a specific feature is enabled in the image.
|
||||
|
||||
This file has been generated using the 'savedefconfig' Kconfig command,
|
||||
which generates the minimal .config file that is needed to produce the
|
||||
required config in a coreboot build. This is fine for reproduction, but
|
||||
bad when you want to check if a certain config was enabled, since many
|
||||
options get enabled by default or pulled in through another option's
|
||||
'select' statement and thus don't show up in the defconfig.
|
||||
|
||||
Instead coreboot now includes a larger .config instead. In order to save
|
||||
some space, all of the comments disabling options are removed from the
|
||||
file, except for those included in the defconfig.
|
||||
|
||||
We can also LZMA compress the file since it is never read by firmware
|
||||
itself and only intended for later re-extraction via cbfstool, which
|
||||
always has LZMA support included.
|
||||
|
||||
|
||||
### Toolchain updates
|
||||
|
||||
* Upgrade LLVM from 15.0.0 to 15.0.6
|
||||
* Upgrade CMake from 3.24.2 to 3.25.0
|
||||
* Upgrade IASL from 20220331 to 20221020
|
||||
* Upgrade MPFR from 4.1.0 to 4.1.1
|
||||
|
||||
|
||||
### Finished the conversion to ASL 2.0 syntax
|
||||
|
||||
Until recently, coreboot still contained lots of code using the legacy
|
||||
ASL syntax. However, all ASL code was ported over to make use of the ASL
|
||||
2.0 syntax and from this point on new ASL code should make use of it.
|
||||
|
||||
|
||||
Additional coreboot changes
|
||||
---------------------------
|
||||
|
||||
* One or two line change comments go here
|
||||
* Significant work was done to enable and build-test clang builds.
|
||||
* Added touchscreen power sequencing and runtime detection.
|
||||
* A number of patches were added to clean up and improve SMBIOS.
|
||||
* Work is in progress to unify and extend coreboot post codes.
|
||||
* Clean up for header includes is in progress with help from IWYU.
|
||||
* IOAPIC code has been reworked.
|
||||
* Support was added to superiotool for the NCT6687D-W chip.
|
||||
* Work is progressing to switch return values to enum cb_err instead of
|
||||
bool or other pass/fail indicators.
|
||||
* Clang builds are now working for most boards and are being
|
||||
build-tested.
|
||||
* 64-bit coreboot support is in progress and is working on a number of
|
||||
platforms.
|
||||
* A driver for EC used on various Clevo laptops was added.
|
||||
* Native Intel Lynxpoint code was added to replace the MRC.bin.
|
||||
* Work continued for the process of adding ops structures to the
|
||||
devicetree.
|
||||
* The crossgcc tool can now download the source packages, which are
|
||||
needed to build the coreboot toolchain, from coreboot’s own mirror if
|
||||
desired.
|
||||
* A document with useful external resources related to firmware
|
||||
development was added at Documentation/external_docs.md.
|
||||
|
||||
|
||||
New Mainboards
|
||||
--------------
|
||||
|
||||
* AMD: Mayan for Phoenix SoC
|
||||
* GIGABYTE: GA-H61M-DS2
|
||||
* Google: Crystaldrift
|
||||
* Google: Gladios
|
||||
* Google: Dibbi
|
||||
* Google: Gaelin
|
||||
* Google: Marasov
|
||||
* Google: Markarth
|
||||
* Google: Omnigul
|
||||
* Google: Voltorb
|
||||
* Intel: Meteorlake-P RVP
|
||||
* MSI: PRO Z690-A (WIFI)
|
||||
* Siemens: MC_EHL3
|
||||
* Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
|
||||
* System76: darp8
|
||||
* System76: galp6
|
||||
|
||||
|
||||
Removed Mainboards
|
||||
------------------
|
||||
|
||||
* AMD: Inagua
|
||||
* AMD: Olive Hill
|
||||
* AMD: Parmer
|
||||
* AMD: Persimmon
|
||||
* AMD: Southstation
|
||||
* AMD: Thatcher
|
||||
* AMD: Unionstation
|
||||
* ASROCK: E350M1
|
||||
* ASROCK: IMB-A180
|
||||
* ASUS: A88XM-E
|
||||
* ASUS: AM1I-A
|
||||
* ASUS: F2A85-M
|
||||
* ASUS: F2A85-M LE
|
||||
* ASUS: F2A85-M PRO
|
||||
* BAP: ODE_e20xx
|
||||
* Biostar: A68N-5200
|
||||
* Biostar: AM1ML
|
||||
* ELMEX: pcm205400
|
||||
* ELMEX: pcm205401
|
||||
* GizmoSphere: Gizmo
|
||||
* GizmoSphere: Gizmo2
|
||||
* Google: Morthal
|
||||
* HP: ABM
|
||||
* HP: Pavilion m6 1035dx
|
||||
* Jetway: NF81_T56N_LF
|
||||
* Lenovo: AMD G505s
|
||||
* LiPPERT: FrontRunner-AF aka ADLINK CoreModule2-GF
|
||||
* LiPPERT: Toucan-AF aka cExpress-GFR (+W83627DHG SIO)
|
||||
* MSI: MS-7721 (FM2-A75MA-E35)
|
||||
* PC Engines: APU1
|
||||
|
||||
|
||||
Updated SoCs
|
||||
------------
|
||||
|
||||
* Added soc/amd/glinda
|
||||
* Renamed soc/amd/morgana to soc/amd/phoenix
|
||||
* Removed cpu/amd/agesa/family14
|
||||
* Removed cpu/amd/agesa/family15tn
|
||||
* Removed cpu/amd/agesa/family16kb
|
||||
|
||||
|
||||
Updated Chipsets
|
||||
----------------
|
||||
|
||||
* Removed northbridge/amd/agesa/family14
|
||||
* Removed northbridge/amd/agesa/family15tn
|
||||
* Removed northbridge/amd/agesa/family16kb
|
||||
* Removed southbridge/amd/agesa/hudson
|
||||
* Removed southbridge/amd/cimx/sb800
|
||||
|
||||
|
||||
Payloads
|
||||
--------
|
||||
|
||||
### Payload changes go here
|
||||
* Updated GRUB from 2.04 to 2.06
|
||||
* Updated SeaBIOS 1.16.0 to 1.16.1
|
||||
|
||||
|
||||
|
||||
Plans for Code Deprecation
|
||||
--------------------------
|
||||
Plans to move platform support to a branch
|
||||
------------------------------------------
|
||||
|
||||
|
||||
### Intel Icelake SoC & Icelake RVP mainboard
|
||||
|
||||
Intel Icelake is unmaintained. Also, the only user of this platform ever
|
||||
was the Intel CRB (Customer Reference Board). From the looks of it the
|
||||
code was never ready for production as only engineering sample CPUIDs
|
||||
are supported. This reduces the maintanence overhead for the coreboot
|
||||
project.
|
||||
Intel Icelake is unmaintained and the only user of this platform ever
|
||||
was the Intel CRB (Customer Reference Board). From the looks of the
|
||||
code, it was never ready for production as only engineering sample
|
||||
CPUIDs are supported.
|
||||
|
||||
Intel Icelake code will be removed with release 4.19 and any maintenence
|
||||
Intel Icelake code will be removed following 4.19 and any maintenance
|
||||
will be done on the 4.19 branch. This consists of the Intel Icelake SoC
|
||||
and Intel Icelake RVP mainboard.
|
||||
|
||||
@@ -53,12 +189,45 @@ and Intel Icelake RVP mainboard.
|
||||
### Intel Quark SoC & Galileo mainboard
|
||||
|
||||
The SoC Intel Quark is unmaintained and different efforts to revive it
|
||||
failed. Also, the only user of this platform ever was the Galileo
|
||||
failed. Also, the only user of this platform ever was the Galileo
|
||||
board.
|
||||
|
||||
Thus, to reduce the maintanence overhead for the community, support for
|
||||
Thus, to reduce the maintenance overhead for the community, support for
|
||||
the following components will be removed from the master branch and will
|
||||
be maintained on the release 4.20 branch.
|
||||
|
||||
* Intel Quark SoC
|
||||
* Intel Galileo mainboard
|
||||
|
||||
|
||||
Statistics from the 4.18 to the 4.19 release
|
||||
--------------------------------------------
|
||||
|
||||
- Total Commits: 1608
|
||||
- Average Commits per day: 17.39
|
||||
- Total lines added: 93786
|
||||
- Average lines added per commit: 58.32
|
||||
- Number of patches adding more than 100 lines: 80
|
||||
- Average lines added per small commit: 38.54
|
||||
- Total lines removed: 768014
|
||||
- Total difference between added and removed: -674228
|
||||
|
||||
|
||||
Significant Known and Open Issues
|
||||
---------------------------------
|
||||
|
||||
Issues from the coreboot bugtracker: https://ticket.coreboot.org/
|
||||
|
||||
| # | Subject |
|
||||
|-----|-----------------------------------------------------------------|
|
||||
| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
|
||||
| 448 | Thinkpad T440P ACPI Battery Value Issues |
|
||||
| 446 | Optiplex 9010 No Post |
|
||||
| 445 | Thinkpad X200 wifi issue |
|
||||
| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz) |
|
||||
| 427 | x200: Two battery charging issues |
|
||||
| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
|
||||
| 412 | x230 reboots on suspend |
|
||||
| 393 | T500 restarts rather than waking up from suspend |
|
||||
| 350 | I225 PCIe device not detected on Harcuvar |
|
||||
| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD |
|
||||
|
67
Documentation/releases/coreboot-4.20-relnotes.md
Normal file
67
Documentation/releases/coreboot-4.20-relnotes.md
Normal file
@@ -0,0 +1,67 @@
|
||||
Upcoming release - coreboot 4.20
|
||||
========================================================================
|
||||
|
||||
The 4.20 release is planned for the 20th of April 2023.
|
||||
|
||||
|
||||
The 4.21 release is planned for around the 17th of July, 2023
|
||||
|
||||
|
||||
Update this document with changes that should be in the release notes.
|
||||
|
||||
* Please use Markdown.
|
||||
* See the past few release notes for the general format.
|
||||
* The chip and board additions and removals will be updated right
|
||||
before the release, so those do not need to be added.
|
||||
* Note that all changes before the release are done are marked upcoming.
|
||||
A final version of the notes are done after the release.
|
||||
|
||||
* This document may also be edited at the google doc copy:
|
||||
https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
|
||||
|
||||
Significant or interesting changes
|
||||
----------------------------------
|
||||
|
||||
### Add changes that need a full description here
|
||||
|
||||
|
||||
|
||||
Additional coreboot changes
|
||||
---------------------------
|
||||
|
||||
The following are changes across a number of patches, or changes worth
|
||||
noting, but not needing a full description.
|
||||
|
||||
* Changes that only need a line or two of description go here.
|
||||
|
||||
|
||||
|
||||
|
||||
Plans to move platform support to a branch
|
||||
------------------------------------------
|
||||
|
||||
### Intel Quark SoC & Galileo mainboard
|
||||
|
||||
The SoC Intel Quark is unmaintained and different efforts to revive it
|
||||
have so far failed. The only user of this SoC ever was the Galileo
|
||||
board.
|
||||
|
||||
Thus, to reduce the maintanence overhead for the community, support for
|
||||
the following components will be removed from the master branch and will
|
||||
be maintained on the release 4.20 branch.
|
||||
|
||||
* Intel Quark SoC
|
||||
* Intel Galileo mainboard
|
||||
|
||||
|
||||
Statistics from the 4.19 to the 4.20 release
|
||||
--------------------------------------------
|
||||
|
||||
* To be filled in immediately before the release by the release team
|
||||
|
||||
|
||||
Significant Known and Open Issues
|
||||
---------------------------------
|
||||
|
||||
* To be filled in immediately before the release by the release team
|
||||
|
@@ -3,7 +3,7 @@
|
||||
## Upcoming release
|
||||
|
||||
Please add to the release notes as changes are added:
|
||||
* [4.19 - Jan 2023](coreboot-4.19-relnotes.md)
|
||||
* [4.20 - April 2023](coreboot-4.20-relnotes.md)
|
||||
|
||||
The [checklist] contains instructions to ensure that a release covers all
|
||||
important things and provides a reliable format for tarballs, branch
|
||||
@@ -15,9 +15,10 @@ important is taken care of.
|
||||
|
||||
## Previous releases
|
||||
|
||||
* [4.18 - Oct 2022](coreboot-4.18-relnotes.md)
|
||||
* [4.19 - January 2023](coreboot-4.19-relnotes.md)
|
||||
* [4.18 - October 2022](coreboot-4.18-relnotes.md)
|
||||
* [4.17 - May 2022](coreboot-4.17-relnotes.md)
|
||||
* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
|
||||
* [4.16 - February 2022](coreboot-4.16-relnotes.md)
|
||||
* [4.15 - November 2021](coreboot-4.15-relnotes.md)
|
||||
* [4.14 - May 2021](coreboot-4.14-relnotes.md)
|
||||
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
|
||||
|
@@ -1,9 +1,11 @@
|
||||
# vboot-enabled devices
|
||||
|
||||
## AMD
|
||||
- Birman
|
||||
- Birman for Phoenix SoC
|
||||
- Birman for Glinda SoC
|
||||
- Chausie
|
||||
- Majolica
|
||||
- Mayan for Phoenix SoC
|
||||
|
||||
## Clevo
|
||||
- N130WU / N131WU
|
||||
@@ -64,16 +66,20 @@
|
||||
- Joxer
|
||||
- Pujjo
|
||||
- Xivu
|
||||
- Gaelin4ADL
|
||||
- Gaelin
|
||||
- Yaviks
|
||||
- Lisbon
|
||||
- Zydron
|
||||
- Gladios
|
||||
- Marasov
|
||||
- Omnigul
|
||||
- Butterfly (HP Pavilion Chromebook 14)
|
||||
- Cherry
|
||||
- Dojo
|
||||
- Tomato
|
||||
- Kingler
|
||||
- Steelix
|
||||
- Voltorb
|
||||
- Krabby
|
||||
- Tentacruel
|
||||
- Magikarp
|
||||
@@ -191,22 +197,6 @@
|
||||
- Puff
|
||||
- Scout
|
||||
- Wyvern (CTL Chromebox CBx2)
|
||||
- Banjo (Acer Chromebook 15 (CB3-531))
|
||||
- Candy (Dell Chromebook 11 3120)
|
||||
- Clapper (Lenovo N20 Chromebook)
|
||||
- Enguarde
|
||||
- Glimmer (Lenovo ThinkPad 11e Chromebook)
|
||||
- Gnawty (Acer Chromebook 11 (CB3-111/131,C730/C730E/C735))
|
||||
- Heli (Haier Chromebook G2)
|
||||
- Kip (HP Chromebook 11 G3 / G4 / G4 EE)
|
||||
- Ninja (AOpen Chromebox Commercial)
|
||||
- Orco (Lenovo 100S Chromebook)
|
||||
- Quawks (ASUS Chromebook C300)
|
||||
- Squawks (ASUS Chromebook C200)
|
||||
- Rambi
|
||||
- Sumo (AOpen Chromebase Commercial)
|
||||
- Swanky (Toshiba Chromebook 2)
|
||||
- Winky (Samsung Chromebook 2 (XE500C12))
|
||||
- Reef/Electro (Acer Chromebook Spin 11 R751T)
|
||||
- Pyro (Lenovo Thinkpad (Yoga) 11e Chromebook)
|
||||
- Sand (Acer Chromebook 15 CB515-1HT/1H)
|
||||
@@ -217,8 +207,9 @@
|
||||
- Sarien (Dell Latitude 5400 Chromebook Enterprise)
|
||||
- Skyrim
|
||||
- Winterhold
|
||||
- Morthal
|
||||
- Frostflow
|
||||
- Crystaldrift
|
||||
- Markarth
|
||||
- Falco (HP Chromebook 14)
|
||||
- Leon (Toshiba Chromebook)
|
||||
- Peppy (Acer C720/C720P Chromebook)
|
||||
@@ -299,8 +290,6 @@
|
||||
- Emerald Lake 2 CRB
|
||||
- Galileo
|
||||
- Glkrvp
|
||||
- Icelake U DDR4/LPDDR4 RVP
|
||||
- Icelake Y LPDDR4 RVP
|
||||
- Jasperlake DDR4/LPDDR4 RVP
|
||||
- Jasperlake DDR4/LPDDR4 RVP with Chrome EC
|
||||
- Kabylake LPDDR3 RVP3
|
||||
@@ -308,6 +297,8 @@
|
||||
- Kabylake DDR4 RVP8
|
||||
- Kabylake DDR4 RVP11
|
||||
- Kunimitsu
|
||||
- Meteorlake-P RVP
|
||||
- Meteorlake-P RVP with Chrome EC
|
||||
- shadowmountain
|
||||
- Strago
|
||||
- Tigerlake UP3 RVP
|
||||
@@ -346,7 +337,8 @@
|
||||
- ThinkPad X60 / X60s / X60t
|
||||
|
||||
## MSI
|
||||
- PRO Z690-A WIFI DDR4
|
||||
- PRO Z690-A (WIFI) DDR4
|
||||
- PRO Z690-A (WIFI)
|
||||
|
||||
## OpenCellular
|
||||
- Elgon (GBCv2)
|
||||
|
@@ -1,67 +0,0 @@
|
||||
# Intel Ice Lake coreboot development
|
||||
|
||||
## Introduction
|
||||
|
||||
This document captures the coreboot development strategy for Intel SoC named Ice lake.
|
||||
|
||||
The Ice Lake processor family is the next generation Intel® Core processor family.
|
||||
These processors are built using Intel's 10 nm+ process.
|
||||
|
||||
* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html)
|
||||
|
||||
## Development Strategy
|
||||
|
||||
Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
|
||||
|
||||
1. Intel develops initial Firmware code for Ice Lake SoC.
|
||||
|
||||
2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
|
||||
```eval_rst
|
||||
:doc:`../../../mainboard/intel/icelake_rvp`
|
||||
```
|
||||
|
||||
### Summary:
|
||||
* SoC is Ice Lake.
|
||||
* Reference platform is icelake_rvp.
|
||||
* OEM board is Dragonegg.
|
||||
|
||||
## Create coreboot Image
|
||||
|
||||
1. Clone latest coreboot code as below
|
||||
```bash
|
||||
$ git clone https://review.coreboot.org/coreboot.git
|
||||
```
|
||||
|
||||
2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
|
||||
|
||||
Note:
|
||||
Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
|
||||
After product launch, FSP binary will be available externally as any other program.
|
||||
|
||||
3. Create coreboot .config
|
||||
|
||||
4. Build toolchain
|
||||
```bash
|
||||
CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl
|
||||
```
|
||||
|
||||
5. Build image
|
||||
```bash
|
||||
$ make # the image is generated as build/coreboot.rom
|
||||
```
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
|
||||
|
||||
* Make use of dediprog while flashing coreboot image on Intel-RVP
|
||||
* For Chromebook related platform like dragonegg, one can flash via servo:
|
||||
|
||||
```bash
|
||||
$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
|
||||
$ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
|
||||
$ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
|
||||
```
|
||||
### References
|
||||
* [flashrom](https://flashrom.org/Flashrom)
|
||||
* [Servo](https://www.chromium.org/chromium-os/servo)
|
@@ -1,7 +0,0 @@
|
||||
# Intel Ice Lake SOC-specific documentation
|
||||
|
||||
This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
|
||||
|
||||
## Ice Lake coreboot development
|
||||
|
||||
- [Ice Lake coreboot development](iceLake_coreboot_development.md)
|
@@ -7,7 +7,6 @@ This section contains documentation about coreboot on specific Intel SOCs.
|
||||
- [Common code development strategy](code_development_model/code_development_model.md)
|
||||
- [FSP](fsp/index.md)
|
||||
- [Broadwell](broadwell/index.md)
|
||||
- [Ice Lake/9th Gen Core-i series](icelake/index.md)
|
||||
- [MP Initialization](mp_init/mp_init.md)
|
||||
- [Microcode Updates](microcode.md)
|
||||
- [Firmware Interface Table](fit.md)
|
||||
|
309
MAINTAINERS
309
MAINTAINERS
@@ -14,27 +14,17 @@ Please try to follow the guidelines below. This will make things
|
||||
easier on the maintainers. Not all of these guidelines matter for every
|
||||
trivial patch so apply some common sense.
|
||||
|
||||
1. Always _test_ your changes, however small, on at least 1 or
|
||||
2 people, preferably many more.
|
||||
|
||||
2. Try to release a few ALPHA test versions to gerrit. Announce
|
||||
them onto the coreboot mailing list and IRC channel and await
|
||||
results. This is especially important on coreboot core changes,
|
||||
but also for device drivers, because often that's the only way
|
||||
you will find things like the fact revision 3 chipset needs
|
||||
a magic fix you didn't know about, or some clown changed the
|
||||
chips on a board and not its name. (Don't laugh!)
|
||||
1. Make sure your changes compile correctly in multiple configurations. In
|
||||
particular check that changes work for various boards in the tree that
|
||||
it affects:
|
||||
|
||||
3. Make sure your changes compile correctly in multiple
|
||||
configurations. In particular check that changes work for all
|
||||
boards in the tree (use abuild!)
|
||||
Test with: `util/abuild/abuild -c $(nproc) -t vendor/boardname`
|
||||
|
||||
4. When you are happy with a change make it generally available for
|
||||
2. When you are happy with a change make it generally available for
|
||||
testing in gerrit and await feedback.
|
||||
|
||||
5. Make your patch available through coreboot's gerrit code review
|
||||
system, and add the relevant maintainer from this list as a code
|
||||
reviewer. Be prepared to get your changes sent back with seemingly
|
||||
3. Be prepared to get your changes sent back with seemingly
|
||||
silly requests about formatting and variable names. These aren't
|
||||
as silly as they seem. One job the maintainers do is to keep
|
||||
things looking the same. Sometimes this means that the clever
|
||||
@@ -45,36 +35,27 @@ trivial patch so apply some common sense.
|
||||
(util/lint/checkpatch.pl) to catch trival style violations.
|
||||
See https://www.coreboot.org/Coding_Style for guidance here.
|
||||
|
||||
PLEASE add the maintainers that are generated by
|
||||
util/scripts/get_maintainer.pl as reviewers. The results returned
|
||||
by the script will be best if you have git installed and are
|
||||
making your changes in a branch derived from coreboot.org's latest
|
||||
git tree.
|
||||
|
||||
PLEASE try to include any credit lines you want added with the
|
||||
patch. It avoids people being missed off by mistake and makes
|
||||
it easier to know who wants adding and who doesn't.
|
||||
|
||||
PLEASE document known bugs. If it doesn't work for everything
|
||||
or does something very odd once a month document it.
|
||||
|
||||
PLEASE remember that submissions must be made under the terms
|
||||
ALWAYS remember that submissions are made under the terms
|
||||
of the OSDL certificate of contribution and should include a
|
||||
Signed-off-by: line. The current version of this "Developer's
|
||||
Certificate of Origin" (DCO) is listed at
|
||||
https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
|
||||
|
||||
6. Make sure you have the right to send any changes you make. If you
|
||||
4. Make sure you have the right to send any changes you make. If you
|
||||
do changes at work you may find your employer owns the patch
|
||||
not you.
|
||||
|
||||
7. Happy hacking.
|
||||
5. Happy hacking.
|
||||
|
||||
Descriptions of section entries:
|
||||
|
||||
M: Maintainer: FullName <address@domain>
|
||||
Must be registered to Gerrit (https://review.coreboot.org/).
|
||||
Should have experience with upstream coreboot development.
|
||||
Should have experience with upstream coreboot development and
|
||||
+2 rights.
|
||||
R: Designated reviewer: FullName <address@domain>
|
||||
These reviewers should be CCed on patches.
|
||||
L: Mailing list that is relevant to this area
|
||||
@@ -137,6 +118,24 @@ Maintainers List (try to look for most precise areas first)
|
||||
# Mainboards
|
||||
################################################################################
|
||||
|
||||
51NB MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/51nb/
|
||||
|
||||
|
||||
|
||||
ACER MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/acer/
|
||||
|
||||
|
||||
|
||||
ADLINK MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/adlink/
|
||||
|
||||
|
||||
|
||||
AMD family 17h and 19h reference boards
|
||||
M: Felix Held <felix-coreboot@felixheld.de>
|
||||
M: Jason Glenesk <jason.glenesk@gmail.com>
|
||||
@@ -144,11 +143,14 @@ M: Fred Reitberger <reitbergerfred@gmail.com>
|
||||
L: amd_coreboot_org_changes@googlegroups.com
|
||||
S: Maintained
|
||||
F: src/mainboard/amd/bilby/
|
||||
F: src/mainboard/amd/birman/
|
||||
F: src/mainboard/amd/chausie/
|
||||
F: src/mainboard/amd/majolica/
|
||||
F: src/mainboard/amd/mandolin/
|
||||
F: src/mainboard/amd/mayan/
|
||||
|
||||
AMD reference boards outside of family 17h and 19h
|
||||
S: Odd Fixes
|
||||
L: amd_coreboot_org_changes@googlegroups.com
|
||||
F: src/mainboard/amd/gardenia/
|
||||
F: src/mainboard/amd/inagua/
|
||||
@@ -162,6 +164,12 @@ F: src/mainboard/amd/union_station/
|
||||
|
||||
|
||||
|
||||
AOPEN MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/aopen/
|
||||
|
||||
|
||||
|
||||
APPLE MAINBOARDS
|
||||
M: Evgeny Zinoviev <me@ch1p.io>
|
||||
S: Maintained
|
||||
@@ -179,11 +187,6 @@ M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/asrock/g41c-gs/
|
||||
|
||||
ASROCK H81M-HDS MAINBOARD
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
S: Maintained
|
||||
F: src/mainboard/asrock/h81m-hds/
|
||||
|
||||
|
||||
|
||||
ASUS A88XM-E MAINBOARD
|
||||
@@ -198,15 +201,9 @@ F: src/mainboard/asus/am1i-a/
|
||||
|
||||
ASUS H61 SERIES MAINBOARDS
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
S: Maintained
|
||||
F: src/mainboard/asus/h61-series/
|
||||
|
||||
ASUS MAXIMUS IV GENE-Z MAINBOARD
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
S: Maintained
|
||||
F: src/mainboard/asus/maximus_iv_gene-z/
|
||||
|
||||
ASUS P5QC PRO MAINBOARD & VARIANTS
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
R: Stefan Ott <coreboot@desire.ch>
|
||||
@@ -226,6 +223,30 @@ F: src/mainboard/asus/p8z77-series/
|
||||
|
||||
|
||||
|
||||
BAP MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/bap/
|
||||
|
||||
|
||||
|
||||
BIOSTAR MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/biostar/
|
||||
|
||||
|
||||
|
||||
BOSTENTECH MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/bostentech/
|
||||
|
||||
|
||||
|
||||
CAVIUM MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/cavium/
|
||||
|
||||
|
||||
|
||||
CLEVO MAINBOARDS
|
||||
M: Felix Singer <felixsinger@posteo.net>
|
||||
M: Michael Niewöhner <foss@mniewoehner.de>
|
||||
@@ -234,6 +255,36 @@ F: src/mainboard/clevo/
|
||||
|
||||
|
||||
|
||||
COMPULAB MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/compulab/
|
||||
|
||||
|
||||
|
||||
DELL MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/dell/
|
||||
|
||||
|
||||
|
||||
ELMEX MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/elmex/
|
||||
|
||||
|
||||
|
||||
EMULATION MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/emulation/
|
||||
|
||||
|
||||
|
||||
EXAMPLE MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/example/
|
||||
|
||||
|
||||
|
||||
FACEBOOK FBG1701 MAINBOARD
|
||||
M: Frans Hendriks <fhendriks@eltan.com>
|
||||
M: Erik van den Bogaert <ebogaert@eltan.com>
|
||||
@@ -248,21 +299,36 @@ F: src/mainboard/facebook/monolith/
|
||||
|
||||
|
||||
|
||||
FOXCONN MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/foxconn/
|
||||
|
||||
|
||||
|
||||
GETAC MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/getac/
|
||||
|
||||
|
||||
|
||||
GIGABYTE GA-D510UD MAINBOARD
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/gigabyte/ga-d510ud/
|
||||
|
||||
GIGABYTE GA-G41M-ES2L MAINBOARD
|
||||
M: Damien Zammit <damien@zamaudio.com>
|
||||
S: Odd Fixes
|
||||
F: src/mainboard/gigabyte/ga-g41m-es2l/
|
||||
|
||||
GIGABYTE GA-H61M SERIES MAINBOARDS
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/gigabyte/ga-h61m-series/
|
||||
|
||||
|
||||
|
||||
GIZMOSPHERE MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/gizmosphere/
|
||||
|
||||
|
||||
|
||||
GOOGLE REX MAINBOARDS
|
||||
M: Subrata Banik <subratabanik@google.com>
|
||||
M: Tarun Tuli <taruntuli@google.com>
|
||||
@@ -280,11 +346,6 @@ M: Tarun Tuli <taruntuli@google.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/google/hatch/
|
||||
|
||||
GOOGLE PANTHER MAINBOARD
|
||||
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
||||
S: Supported
|
||||
F: src/mainboard/google/panther/
|
||||
|
||||
GOOGLE VOLTEER MAINBOARDS
|
||||
M: Nick Vaccaro <nvaccaro@chromium.org>
|
||||
S: Maintained
|
||||
@@ -315,6 +376,7 @@ F: src/mainboard/google/guybrush/
|
||||
F: src/mainboard/google/skyrim/
|
||||
|
||||
|
||||
|
||||
HP 280 G2 MAINBOARD
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Maintained
|
||||
@@ -322,23 +384,23 @@ F: src/mainboard/hp/280_g2/
|
||||
|
||||
|
||||
|
||||
INTEL D510MO MAINBOARD
|
||||
M: Damien Zammit <damien@zamaudio.com>
|
||||
S: Odd Fixes
|
||||
F: src/mainboard/intel/d510mo/
|
||||
IBASE MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/ibase/
|
||||
|
||||
|
||||
|
||||
INTEL HARCUVAR_CRB MAINBOARD
|
||||
M: Jeff Daly <jeffd@silicom-usa.com>
|
||||
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
|
||||
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
|
||||
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/intel/harcuvar/
|
||||
|
||||
INTEL STRAGO MAINBOARD
|
||||
M: Hannah Williams <hannah.williams@intel.com>
|
||||
S: Supported
|
||||
F: /src/mainboard/intel/strago/
|
||||
|
||||
|
||||
JETWAY MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/jetway/
|
||||
|
||||
|
||||
|
||||
@@ -378,6 +440,7 @@ S: Maintained
|
||||
F: src/mainboard/lenovo/x201/
|
||||
|
||||
|
||||
|
||||
LIBRETREND LT1000 MAINBOARD
|
||||
M: Piotr Król <piotr.krol@3mdeb.com>
|
||||
M: Michał Żygowski <michal.zygowski@3mdeb.com>
|
||||
@@ -386,6 +449,12 @@ F: src/mainboard/libretrend/lt1000/
|
||||
|
||||
|
||||
|
||||
LIPPERT MAINBOARDS (acquired by Adlink)
|
||||
S: Orphan
|
||||
F: src/mainboard/lippert/
|
||||
|
||||
|
||||
|
||||
MSI H81M-P33 MAINBOARD
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Maintained
|
||||
@@ -397,6 +466,8 @@ M: Michał Kopeć <michal.kopec@3mdeb.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/msi/ms7d25/
|
||||
|
||||
|
||||
|
||||
OCP DELTALAKE MAINBOARD
|
||||
M: Arthur Heymans <arthur@aheymans.xyz>
|
||||
M: Christian Walter <christian.walter@9elements.com>
|
||||
@@ -408,7 +479,6 @@ F: src/mainboard/ocp/deltalake/
|
||||
|
||||
OCP TIOGAPASS MAINBOARD
|
||||
M: Jonathan Zhang <jonzhang@fb.com>
|
||||
M: Reddy Chagam <anjaneya.chagam@intel.com>
|
||||
M: Johnny Lin <Johnny_Lin@wiwynn.com>
|
||||
M: Morgan Jang <Morgan_Jang@wiwynn.com>
|
||||
M: Ryback Hung <<Ryback.Hung@quantatw.com>
|
||||
@@ -434,6 +504,12 @@ F: src/mainboard/pcengines/
|
||||
|
||||
|
||||
|
||||
PINE64 MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/pine64/
|
||||
|
||||
|
||||
|
||||
PORTWELL PQ-M107 MAINBOARD
|
||||
M: Frans Hendriks <fhendriks@eltan.com>
|
||||
M: Erik van den Bogaert <ebogaert@eltan.com>
|
||||
@@ -472,6 +548,18 @@ F: src/mainboard/purism/
|
||||
|
||||
|
||||
|
||||
RAZER MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/razer/
|
||||
|
||||
|
||||
|
||||
RODA MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/roda/
|
||||
|
||||
|
||||
|
||||
SAMSUNG CHROMEOS MAINBOARDS
|
||||
M: Matt DeVillier <MrChromebox@gmail.com>
|
||||
S: Maintained
|
||||
@@ -480,6 +568,18 @@ F: src/mainboard/samsung/stumpy/
|
||||
|
||||
|
||||
|
||||
SAPPHIRE MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/sapphire/
|
||||
|
||||
|
||||
|
||||
SCALEWAY MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/scaleway/
|
||||
|
||||
|
||||
|
||||
SIEMENS CHILI MAINBAORD
|
||||
M: Felix Singer <felixsinger@posteo.net>
|
||||
M: Nico Huber <nico.h@gmx.de>
|
||||
@@ -494,6 +594,12 @@ F: src/mainboard/siemens/mc_ehl/
|
||||
|
||||
|
||||
|
||||
SIFIVE MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/sifive/
|
||||
|
||||
|
||||
|
||||
STAR LABS MAINBOARDS
|
||||
M: Sean Rhodes <sean@starlabs.systems>
|
||||
S: Maintained
|
||||
@@ -501,6 +607,13 @@ F: src/mainboard/starlabs/
|
||||
|
||||
|
||||
|
||||
SUPERMICRO X11-LGA1151-SERIES
|
||||
M: Michael Niewöhner <foss@mniewoehner.de>
|
||||
S: Maintained
|
||||
F: src/mainboard/supermicro/x11-lga1151-series/
|
||||
|
||||
|
||||
|
||||
SYSTEM76 MAINBOARDS
|
||||
M: Jeremy Soller <jeremy@system76.com>
|
||||
M: Tim Crawford <tcrawford@system76.com>
|
||||
@@ -509,15 +622,15 @@ F: src/mainboard/system76/
|
||||
|
||||
|
||||
|
||||
SUPERMICRO X10SLM+-F MAINBOARD
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
S: Maintained
|
||||
F: src/mainboard/supermicro/x10slm-f/
|
||||
TI MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/ti/
|
||||
|
||||
SUPERMICRO X11-LGA1151-SERIES
|
||||
M: Michael Niewöhner <foss@mniewoehner.de>
|
||||
S: Maintained
|
||||
F: src/mainboard/supermicro/x11-lga1151-series/
|
||||
|
||||
|
||||
UP MAINBOARDS
|
||||
S: Orphan
|
||||
F: src/mainboard/up/
|
||||
|
||||
################################################################################
|
||||
# Architectures
|
||||
@@ -553,6 +666,7 @@ F: src/mainboard/sifive/
|
||||
F: util/riscv/
|
||||
|
||||
X86 ARCHITECTURE
|
||||
S: MAINTAINED
|
||||
F: src/arch/x86/
|
||||
F: src/cpu/x86/
|
||||
F: src/drivers/pc80/
|
||||
@@ -567,7 +681,7 @@ CHROME EC
|
||||
M: Boris Mittelberg <bmbm@google.com>
|
||||
M: Caveh Jalali <caveh@chromium.org>
|
||||
S: Maintained
|
||||
F: src/ec/google/chromeec/
|
||||
F: src/ec/google/
|
||||
|
||||
LENOVO EC
|
||||
M: Alexander Couzens <lynxis@fe80.eu>
|
||||
@@ -585,6 +699,19 @@ M: Tim Crawford <tcrawford@system76.com>
|
||||
S: Maintained
|
||||
F: src/ec/system76/
|
||||
|
||||
ORPHANED ECS
|
||||
S: Orphan
|
||||
F: src/ec/51nb/
|
||||
F: src/ec/acpi/
|
||||
F: src/ec/apple/
|
||||
F: src/ec/compal/
|
||||
F: src/ec/hp/
|
||||
F: src/ec/kontron/
|
||||
F: src/ec/purism/
|
||||
F: src/ec/quanta/
|
||||
F: src/ec/roda/
|
||||
F: src/ec/smsc/
|
||||
|
||||
################################################################################
|
||||
# Northbridges
|
||||
################################################################################
|
||||
@@ -595,7 +722,6 @@ S: Maintained
|
||||
F: src/northbridge/intel/haswell/
|
||||
|
||||
INTEL PINEVIEW CHIPSET
|
||||
M: Damien Zammit <damien@zamaudio.com>
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Odd Fixes
|
||||
F: src/northbridge/intel/pineview/
|
||||
@@ -606,7 +732,6 @@ S: Maintained
|
||||
F: src/northbridge/intel/sandybridge/
|
||||
|
||||
INTEL X4X CHIPSET
|
||||
M: Damien Zammit <damien@zamaudio.com>
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
S: Odd Fixes
|
||||
F: src/northbridge/intel/x4x/
|
||||
@@ -617,6 +742,7 @@ F: src/northbridge/intel/x4x/
|
||||
|
||||
AMD SUPPORT
|
||||
L: amd_coreboot_org_changes@googlegroups.com
|
||||
S: Odd Fixes
|
||||
F: src/vendorcode/amd/
|
||||
F: src/cpu/amd/
|
||||
F: src/northbridge/amd/
|
||||
@@ -634,9 +760,7 @@ F: src/drivers/intel/
|
||||
F: src/include/cpu/intel/
|
||||
|
||||
INTEL FSP 1.1
|
||||
M: Lee Leahy <leroy.p.leahy@intel.com>
|
||||
M: Huang Jin <huang.jin@intel.com>
|
||||
M: York Yang <york.yang@intel.com>
|
||||
S: Supported
|
||||
F: src/drivers/intel/fsp1_1/
|
||||
|
||||
@@ -691,6 +815,16 @@ S: Supported
|
||||
F: src/soc/amd/mendocino/
|
||||
F: src/vendorcode/amd/fsp/mendocino/
|
||||
|
||||
AMD Phoenix
|
||||
M: Felix Held <felix-coreboot@felixheld.de>
|
||||
M: Jason Glenesk <jason.glenesk@gmail.com>
|
||||
M: Fred Reitberger <reitbergerfred@gmail.com>
|
||||
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
||||
L: amd_coreboot_org_changes@googlegroups.com
|
||||
S: Supported
|
||||
F: src/soc/amd/phoenix/
|
||||
F: src/vendorcode/amd/fsp/phoenix/
|
||||
|
||||
AMD Stoneyridge
|
||||
M: Felix Held <felix-coreboot@felixheld.de>
|
||||
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
||||
@@ -712,8 +846,8 @@ S: Maintained
|
||||
F: src/soc/intel/alderlake/
|
||||
|
||||
INTEL APOLLOLAKE_SOC
|
||||
M: Andrey Petrov <andrey.petrov@gmail.com>
|
||||
S: Maintained
|
||||
M: Sean Rhodes <sean@starlabs.systems>
|
||||
S: Odd Fixes
|
||||
F: src/soc/intel/apollolake/
|
||||
|
||||
INTEL BRASWELL SOC
|
||||
@@ -727,8 +861,6 @@ F: /src/vendorcode/intel/fsp/fsp1_1/braswell/
|
||||
INTEL DENVERTON-NS SOC
|
||||
M: Jeff Daly <jeffd@silicom-usa.com>
|
||||
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
|
||||
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
|
||||
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
|
||||
S: Maintained
|
||||
F: src/soc/intel/denverton_ns/
|
||||
|
||||
@@ -746,7 +878,6 @@ F: src/soc/intel/tigerlake/
|
||||
|
||||
INTEL Xeon Sacalable Processor Family
|
||||
M: Jonathan Zhang <jonzhang@fb.com>
|
||||
M: Reddy Chagam <anjaneya.chagam@intel.com>
|
||||
M: Johnny Lin <Johnny_Lin@wiwynn.com>
|
||||
M: Tim Chu <Tim.Chu@quantatw.com>
|
||||
M: Arthur Heymans <arthur@aheymans.xyz>
|
||||
@@ -768,7 +899,7 @@ F: src/soc/mediatek/mt8192/
|
||||
F: src/vendorcode/mediatek/mt8192/
|
||||
|
||||
ORPHANED ARM SOCS
|
||||
S: Orphaned
|
||||
S: Orphan
|
||||
F: src/cpu/armltd/
|
||||
F: src/soc/ti/
|
||||
F: src/soc/qualcomm/
|
||||
@@ -825,6 +956,10 @@ F: util/xcompile/
|
||||
F: util/genbuild_h/
|
||||
|
||||
TOOLCHAIN
|
||||
M: Martin Roth <gaumless@gmail.com>
|
||||
M: Felix Singer <felixsinger@posteo.net>
|
||||
M: Elyes Haouas <ehaouas@noos.fr>
|
||||
S: Supported
|
||||
F: util/crossgcc/
|
||||
|
||||
DOCKER
|
||||
@@ -976,6 +1111,16 @@ S: Maintained
|
||||
F: tests/
|
||||
F: payloads/libpayload/tests/
|
||||
|
||||
COREBOOT RELEASES
|
||||
M: Felix Singer <felixsinger@posteo.net>
|
||||
M: Jason Glenesk <jason.glenesk@gmail.com>
|
||||
M: Angel Pons <th3fanbus@gmail.com>
|
||||
M: Martin Roth <gaumless@gmail.com>
|
||||
M: Matt DeVillier <MrChromebox@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/releases/
|
||||
F: util/release/
|
||||
|
||||
MISSING: TIMERS / DELAYS
|
||||
|
||||
MISSING: TIMESTAMPS
|
||||
@@ -1012,7 +1157,7 @@ MISSING: SPI
|
||||
|
||||
CODE OF CONDUCT
|
||||
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
||||
M: Ronald Minnich <rminnich@coreboot.org>
|
||||
M: Ronald Minnich <rminnich@gmail.com>
|
||||
M: Martin Roth <martin@coreboot.org>
|
||||
S: Maintained
|
||||
F: Documentation/community/code_of_conduct.md
|
||||
|
39
Makefile
39
Makefile
@@ -38,6 +38,11 @@ COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
|
||||
COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
|
||||
COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
|
||||
|
||||
# Make does not offer a recursive wildcard function, so here's one:
|
||||
rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
|
||||
SYMLINK_LIST = $(call rwildcard,site-local/,symlink.txt)
|
||||
|
||||
|
||||
# directory containing the toplevel Makefile.inc
|
||||
TOPLEVEL := .
|
||||
|
||||
@@ -64,6 +69,9 @@ endif
|
||||
HOSTCFLAGS := -g
|
||||
HOSTCXXFLAGS := -g
|
||||
|
||||
HOSTPKG_CONFIG ?= pkg-config
|
||||
COREBOOT_EXPORTS += HOSTPKG_CONFIG
|
||||
|
||||
PREPROCESS_ONLY := -E -P -x assembler-with-cpp -undef -I .
|
||||
|
||||
export $(COREBOOT_EXPORTS)
|
||||
@@ -143,13 +151,14 @@ include $(TOPLEVEL)/payloads/Makefile.inc
|
||||
include $(TOPLEVEL)/util/testing/Makefile.inc
|
||||
-include $(TOPLEVEL)/site-local/Makefile.inc
|
||||
include $(TOPLEVEL)/tests/Makefile.inc
|
||||
real-all:
|
||||
printall real-all:
|
||||
@echo "Error: Trying to build, but NOCOMPILE is set." >&2
|
||||
@echo " Please file a bug with the following information:"
|
||||
@echo "- MAKECMDGOALS: $(MAKECMDGOALS)" >&2
|
||||
@echo "- HAVE_DOTCONFIG: $(HAVE_DOTCONFIG)" >&2
|
||||
@echo "- HAVE_KCONFIG_MAKEFILE_REAL: $(HAVE_KCONFIG_MAKEFILE_REAL)" >&2
|
||||
@exit 1
|
||||
|
||||
else
|
||||
|
||||
ifneq ($(UNIT_TEST),1)
|
||||
@@ -307,6 +316,9 @@ $(eval $(postinclude-hooks))
|
||||
$(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
|
||||
|
||||
# Build Kconfig .ads if necessary
|
||||
ifeq ($(CONFIG_ROMSTAGE_ADA),y)
|
||||
romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
|
||||
endif
|
||||
ifeq ($(CONFIG_RAMSTAGE_ADA),y)
|
||||
ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS))
|
||||
endif
|
||||
@@ -455,6 +467,29 @@ sphinx:
|
||||
sphinx-lint:
|
||||
$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
|
||||
|
||||
symlink:
|
||||
@echo "Creating Symbolic Links.."; \
|
||||
for link in $(SYMLINK_LIST); do \
|
||||
SYMLINK=`cat $$link`; \
|
||||
REALPATH=`realpath $$link`; \
|
||||
if [ -L "$$SYMLINK" ]; then \
|
||||
continue; \
|
||||
elif [ ! -e "$$SYMLINK" ]; then \
|
||||
echo -e "\tLINK $$SYMLINK -> $$(dirname $$REALPATH)"; \
|
||||
ln -s $$(dirname $$REALPATH) $$SYMLINK; \
|
||||
else \
|
||||
echo -e "\tFAILED: $$SYMLINK exists"; \
|
||||
fi \
|
||||
done
|
||||
|
||||
clean-symlink:
|
||||
@echo "Deleting symbolic link";\
|
||||
EXISTING_SYMLINKS=`find -L ./src -xtype l | grep -v 3rdparty`; \
|
||||
for link in $$EXISTING_SYMLINKS; do \
|
||||
echo -e "\tUNLINK $$link"; \
|
||||
rm "$$link"; \
|
||||
done
|
||||
|
||||
clean-for-update:
|
||||
rm -rf $(obj) .xcompile
|
||||
|
||||
@@ -482,4 +517,4 @@ distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
|
||||
rm -f abuild*.xml junit.xml* util/lint/junit.xml
|
||||
|
||||
.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean sphinx sphinx-lint
|
||||
.PHONY: ctags-project cscope-project clean-ctags
|
||||
.PHONY: ctags-project cscope-project clean-ctags symlink clean-symlink
|
||||
|
41
Makefile.inc
41
Makefile.inc
@@ -80,6 +80,7 @@ PHONY+= clean-abuild coreboot check-style build_complete
|
||||
#######################################################################
|
||||
# root source directories of coreboot
|
||||
subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
|
||||
subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
|
||||
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
|
||||
subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
|
||||
subdirs-y += $(wildcard src/northbridge/*/*)
|
||||
@@ -265,26 +266,9 @@ endef
|
||||
# ResourceTemplate is the correct code.
|
||||
# As it's valid ASL, disable the warning.
|
||||
EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
|
||||
# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
|
||||
# 1) If _PRS is present, must have _CRS and _SRS
|
||||
# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
|
||||
# 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
|
||||
# 4) If _SRS is present, probably should have a _DIS (Remark only)
|
||||
# A warning will be issued for each of these cases.
|
||||
# For existing ASL code, ignore this warnings
|
||||
IASL_MISSING_DEPENDENCY = 3141
|
||||
|
||||
IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING)
|
||||
|
||||
ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
|
||||
IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
|
||||
build_complete::
|
||||
printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n"
|
||||
printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
|
||||
printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
|
||||
printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
|
||||
endif
|
||||
|
||||
IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
|
||||
|
||||
define asl_template
|
||||
@@ -322,18 +306,20 @@ cbfs-files-processor-nvramtool= \
|
||||
mv $(2).tmp $(2))
|
||||
|
||||
#######################################################################
|
||||
# Reduce a .config file to its minimal representation
|
||||
# Reduce a .config file by removing lines about default unset booleans
|
||||
# arg1: input
|
||||
# arg2: output
|
||||
define cbfs-files-processor-defconfig
|
||||
$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
|
||||
define cbfs-files-processor-config
|
||||
$(eval $(2): $(1) $(obj)/build.h; \
|
||||
+printf " CREATE $(2) (from $(1))\n"; \
|
||||
printf "# This image was built using coreboot " > $(2).tmp && \
|
||||
grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
|
||||
$(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \
|
||||
cat $(2).tmp2 >> $(2).tmp && \
|
||||
printf "# End of defconfig. Derivable values start here.\n" >> $(2).tmp && \
|
||||
grep "^CONFIG" $(1) | grep -F -v -f $(2).tmp2 >> $(2).tmp && \
|
||||
rm -f $(2).tmp2 && \
|
||||
\mv -f $(2).tmp $(2))
|
||||
mv -f $(2).tmp $(2))
|
||||
endef
|
||||
|
||||
#######################################################################
|
||||
@@ -386,9 +372,12 @@ cbfs-files-handler= \
|
||||
#######################################################################
|
||||
# a variety of flags for our build
|
||||
CBFS_COMPRESS_FLAG:=none
|
||||
ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y)
|
||||
ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y)
|
||||
CBFS_COMPRESS_FLAG:=LZMA
|
||||
endif
|
||||
ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZ4),y)
|
||||
CBFS_COMPRESS_FLAG:=LZ4
|
||||
endif
|
||||
|
||||
CBFS_PAYLOAD_COMPRESS_FLAG:=none
|
||||
ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
|
||||
@@ -433,7 +422,7 @@ endif
|
||||
CFLAGS_common += -pipe -g -nostdinc -std=gnu11
|
||||
CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
|
||||
CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
|
||||
CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
|
||||
CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
|
||||
CFLAGS_common += -Wdangling-else
|
||||
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
|
||||
CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
|
||||
@@ -600,6 +589,7 @@ BINCFG:=$(objutil)/bincfg/bincfg
|
||||
IFDTOOL:=$(objutil)/ifdtool/ifdtool
|
||||
|
||||
AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
|
||||
AMDFWREAD:=$(objutil)/amdfwtool/amdfwread
|
||||
|
||||
APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
|
||||
|
||||
@@ -701,7 +691,7 @@ install-git-commit-clangfmt:
|
||||
include util/crossgcc/Makefile.inc
|
||||
|
||||
.PHONY: tools
|
||||
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER)
|
||||
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD)
|
||||
|
||||
###########################################################################
|
||||
# Common recipes for all stages
|
||||
@@ -1228,8 +1218,9 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
|
||||
vgaroms/seavgabios.bin-type := raw
|
||||
|
||||
cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config
|
||||
config-file := $(DOTCONFIG):defconfig
|
||||
config-file := $(DOTCONFIG):config
|
||||
config-type := raw
|
||||
config-compression := LZMA
|
||||
|
||||
cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision
|
||||
revision-file := $(obj)/build.h
|
||||
|
209
README.md
209
README.md
@@ -1,21 +1,41 @@
|
||||
coreboot README
|
||||
===============
|
||||
|
||||
coreboot is a Free Software project aimed at replacing the proprietary BIOS
|
||||
(firmware) found in most computers. coreboot performs a little bit of
|
||||
hardware initialization and then executes additional boot logic, called a
|
||||
payload.
|
||||
coreboot is a Free Software project aimed at replacing the proprietary
|
||||
firmware (BIOS/UEFI) found in most computers. coreboot performs the
|
||||
required hardware initialization to configure the system, then passes
|
||||
control to a different executable, referred to in coreboot as the
|
||||
payload. Most often, the primary function of the payload is to boot the
|
||||
operating system (OS).
|
||||
|
||||
With the separation of hardware initialization and later boot logic,
|
||||
coreboot can scale from specialized applications that run directly
|
||||
firmware, run operating systems in flash, load custom
|
||||
bootloaders, or implement firmware standards, like PC BIOS services or
|
||||
UEFI. This allows for systems to only include the features necessary
|
||||
in the target application, reducing the amount of code and flash space
|
||||
required.
|
||||
coreboot is perfect for a wide variety of situations. It can be used
|
||||
for specialized applications that run directly in the firmware, running
|
||||
operating systems from flash, loading custom bootloaders, or
|
||||
implementing firmware standards, like PC BIOS services or UEFI. This
|
||||
flexibility allows coreboot systems to include only the features
|
||||
necessary in the target application, reducing the amount of code and
|
||||
flash space required.
|
||||
|
||||
coreboot was formerly known as LinuxBIOS.
|
||||
|
||||
Source code
|
||||
-----------
|
||||
|
||||
All source code for coreboot is stored in git. It is downloaded with
|
||||
the command:
|
||||
|
||||
`git clone https://review.coreboot.org/coreboot.git`.
|
||||
|
||||
Code reviews are done in [the project's Gerrit
|
||||
instance](https://review.coreboot.org/).
|
||||
|
||||
The code may be browsed via [coreboot's Gitiles
|
||||
instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master).
|
||||
|
||||
The coreboot project also maintains a
|
||||
[mirror](https://github.com/coreboot/coreboot) of the project on github.
|
||||
This is read-only, as coreboot does not accept github pull requests,
|
||||
but allows browsing and downloading the coreboot source.
|
||||
|
||||
Payloads
|
||||
--------
|
||||
@@ -23,81 +43,156 @@ Payloads
|
||||
After the basic initialization of the hardware has been performed, any
|
||||
desired "payload" can be started by coreboot.
|
||||
|
||||
See <https://www.coreboot.org/Payloads> for a list of supported payloads.
|
||||
See <https://doc.coreboot.org/payloads.html> for a list of some of
|
||||
coreboot's supported payloads.
|
||||
|
||||
|
||||
Supported Hardware
|
||||
------------------
|
||||
|
||||
coreboot supports a wide range of chipsets, devices, and mainboards.
|
||||
The coreboot project supports a wide range of architectures, chipsets,
|
||||
devices, and mainboards. While not all of these are documented, you can
|
||||
find some information in the [Architecture-specific
|
||||
documentation](https://doc.coreboot.org/arch/index.html) or the
|
||||
[SOC-specific documentation](https://doc.coreboot.org/soc/index.html).
|
||||
|
||||
For details please consult:
|
||||
|
||||
* <https://www.coreboot.org/Supported_Motherboards>
|
||||
For details about the specific mainboard devices that coreboot supports,
|
||||
please consult the [Mainboard-specific
|
||||
documentation](https://doc.coreboot.org/mainboard/index.html) or the
|
||||
[Board Status](https://coreboot.org/status/board-status.html) pages.
|
||||
|
||||
|
||||
Build Requirements
|
||||
------------------
|
||||
Releases
|
||||
--------
|
||||
|
||||
* make
|
||||
* gcc / g++
|
||||
Because Linux distribution compilers tend to use lots of patches. coreboot
|
||||
does lots of "unusual" things in its build system, some of which break due
|
||||
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
|
||||
by generating broken object code.
|
||||
Two options: use our toolchain (eg. make crosstools-i386) or enable the
|
||||
`ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this
|
||||
case).
|
||||
* iasl (for targets with ACPI support)
|
||||
* pkg-config
|
||||
* libssl-dev (openssl)
|
||||
Releases are currently done by coreboot every quarter. The
|
||||
release archives contain the entire coreboot codebase from the time of
|
||||
the release, along with any external submodules. The submodules
|
||||
containing binaries are separated from the general release archives. All
|
||||
of the packages required to build the coreboot toolchains are also kept
|
||||
at coreboot.org in case the websites change, or those specific packages
|
||||
become unavailable in the future.
|
||||
|
||||
Optional:
|
||||
All releases are available on the [coreboot
|
||||
download](https://coreboot.org/downloads.html) page.
|
||||
|
||||
* gdb (for better debugging facilities on some targets)
|
||||
* ncurses (for `make menuconfig` and `make nconfig`)
|
||||
* flex and bison (for regenerating parsers)
|
||||
Please note that the coreboot releases are best considered as snapshots
|
||||
of the codebase, and do not currently guarantee any sort of extra
|
||||
stability.
|
||||
|
||||
Build Requirements and building coreboot
|
||||
----------------------------------------
|
||||
|
||||
Building coreboot
|
||||
-----------------
|
||||
The coreboot build, associated utilities and payloads require many
|
||||
additional tools and packages to build. The actual coreboot binary is
|
||||
typically built using a coreboot-controlled toolchain to provide
|
||||
reproducibility across various platforms. It is also possible, though
|
||||
not recommended, to make it directly with your system toolchain.
|
||||
Operating systems and distributions come with an unknown variety of
|
||||
system tools and utilities installed. Because of this, it isn't
|
||||
reasonable to list all the required packages to do a build, but the
|
||||
documentation lists the requirements for a few different Linux
|
||||
distributions.
|
||||
|
||||
Please consult <https://www.coreboot.org/Build_HOWTO> for details.
|
||||
To see the list of tools and libraries, along with a list of
|
||||
instructions to get started building coreboot, go to the [Starting from
|
||||
scratch](https://doc.coreboot.org/tutorial/part1.html) tutorial page.
|
||||
|
||||
|
||||
Testing coreboot Without Modifying Your Hardware
|
||||
------------------------------------------------
|
||||
|
||||
If you want to test coreboot without any risks before you really decide
|
||||
to use it on your hardware, you can use the QEMU system emulator to run
|
||||
coreboot virtually in QEMU.
|
||||
|
||||
Please see <https://www.coreboot.org/QEMU> for details.
|
||||
That same page goes through how to use QEMU to boot the build and see
|
||||
the output.
|
||||
|
||||
|
||||
Website and Mailing List
|
||||
------------------------
|
||||
|
||||
Further details on the project, a FAQ, many HOWTOs, news, development
|
||||
guidelines and more can be found on the coreboot website:
|
||||
Further details on the project, as well as links to documentation and
|
||||
more can be found on the coreboot website:
|
||||
|
||||
<https://www.coreboot.org>
|
||||
|
||||
You can contact us directly on the coreboot mailing list:
|
||||
|
||||
<https://www.coreboot.org/Mailinglist>
|
||||
<https://doc.coreboot.org/community/forums.html>
|
||||
|
||||
|
||||
Copyright and License
|
||||
|
||||
Copyrights and Licenses
|
||||
---------------------
|
||||
|
||||
|
||||
### Uncopyrightable files
|
||||
|
||||
There are many files in the coreboot tree that we feel are not
|
||||
copyrightable due to a lack of creative content.
|
||||
|
||||
"In order to qualify for copyright protection in the United States, a
|
||||
work must satisfy the originality requirement, which has two parts. The
|
||||
work must have “at least a modicum” of creativity, and it must be the
|
||||
independent creation of its author."
|
||||
|
||||
<https://guides.lib.umich.edu/copyrightbasics/copyrightability>
|
||||
|
||||
Similar terms apply to other locations.
|
||||
|
||||
These uncopyrightable files include:
|
||||
|
||||
- Empty files or files with only a comment explaining their existence.
|
||||
These may be required to exist as part of the build process but are
|
||||
not needed for the particular project.
|
||||
- Configuration files either in binary or text form. Examples would be
|
||||
files such as .vbt files describing graphics configuration, spd files
|
||||
as binary .spd or text \*spd\*.hex representing memory chip
|
||||
configuration.
|
||||
- Machine-generated files containing version numbers, dates, hash
|
||||
values or other "non-creative" content.
|
||||
|
||||
As non-creative content, these files are in the public domain by
|
||||
default. As such, the coreboot project excludes them from the project's
|
||||
general license even though they may be included in a final binary.
|
||||
|
||||
If there are questions or concerns about this policy, please get in
|
||||
touch with the coreboot project via the mailing list.
|
||||
|
||||
|
||||
### Copyrights
|
||||
|
||||
The copyright on coreboot is owned by quite a large number of individual
|
||||
developers and companies. Please check the individual source files for details.
|
||||
developers and companies. A list of companies and individuals with known
|
||||
copyright claims is present at the top level of the coreboot source tree
|
||||
in the 'AUTHORS' file. Please check the git history of each of the
|
||||
source files for details.
|
||||
|
||||
coreboot is licensed under the terms of the GNU General Public License (GPL).
|
||||
Some files are licensed under the "GPL (version 2, or any later version)",
|
||||
and some files are licensed under the "GPL, version 2". For some parts, which
|
||||
were derived from other projects, other (GPL-compatible) licenses may apply.
|
||||
Please check the individual source files for details.
|
||||
|
||||
This makes the resulting coreboot images licensed under the GPL, version 2.
|
||||
### Licenses
|
||||
|
||||
Because of the way coreboot began, using a significant amount of source
|
||||
code from the Linux kernel, it's licensed the same way as the Linux
|
||||
Kernel, with GNU General Public License (GPL) Version 2. Individual
|
||||
files are licensed under various licenses, though all are compatible
|
||||
with GPLv2. The resulting coreboot image is licensed under the GPL,
|
||||
version 2. All source files should have an SPDX license identifier at
|
||||
the top for clarification.
|
||||
|
||||
Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms.
|
||||
As an exception, files under Documentation/ with a history older than
|
||||
2017-05-24 might be under different licenses.
|
||||
|
||||
Files in the coreboot/src/commonlib/bsd directory are all licensed with
|
||||
the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or
|
||||
GPL-2.0-or-later. These files are intended to be shared with libpayload
|
||||
or other BSD licensed projects.
|
||||
|
||||
The libpayload project contained in coreboot/payloads/libpayload may be
|
||||
licensed as BSD or GPL, depending on the code pulled in during the build
|
||||
process. All GPL source code should be excluded unless the Kconfig
|
||||
option to include it is set.
|
||||
|
||||
|
||||
The Software Freedom Conservancy
|
||||
--------------------------------
|
||||
|
||||
Since 2017, coreboot has been a member of [The Software Freedom
|
||||
Conservancy](https://sfconservancy.org/), a nonprofit organization
|
||||
devoted to ethical technology and driving initiatives to make technology
|
||||
more inclusive. The conservancy acts as coreboot's fiscal sponsor and
|
||||
legal advisor.
|
||||
|
5
configs/config.asrock_b85m_pro4.native_raminit
Normal file
5
configs/config.asrock_b85m_pro4.native_raminit
Normal file
@@ -0,0 +1,5 @@
|
||||
# Configuration used to build-test native raminit
|
||||
CONFIG_VENDOR_ASROCK=y
|
||||
CONFIG_BOARD_ASROCK_B85M_PRO4=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_DEBUG_RAM_SETUP=y
|
29
configs/config.google_skyrim.no_video
Normal file
29
configs/config.google_skyrim.no_video
Normal file
@@ -0,0 +1,29 @@
|
||||
CONFIG_USE_AMD_BLOBS=y
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
# CONFIG_CONSOLE_SERIAL is not set
|
||||
CONFIG_AMD_FWM_POSITION_INDEX=4
|
||||
CONFIG_VBOOT=y
|
||||
CONFIG_VBOOT_SLOTS_RW_A=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_BOARD_GOOGLE_SKYRIM=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000
|
||||
CONFIG_VBOOT_FWID_MODEL="Google_$(CONFIG_MAINBOARD_PART_NUMBER)"
|
||||
# CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK is not set
|
||||
CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_ASYNC_FILE_LOADING=y
|
||||
# CONFIG_ACPI_BERT is not set
|
||||
# CONFIG_ACPI_SSDT_PSD_INDEPENDENT is not set
|
||||
CONFIG_AMD_STB_SIZE_IN_MB=3
|
||||
CONFIG_NO_GFX_INIT=y
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_VPD=y
|
||||
CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50
|
||||
CONFIG_GBB_FLAG_DEV_SCREEN_SHORT_DELAY=y
|
||||
CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
|
||||
CONFIG_VBOOT_KEYBLOCK_VERSION=1
|
||||
CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_SEABIOS_DEBUG_LEVEL=-1
|
31
configs/config.google_skyrim.with_binaries
Normal file
31
configs/config.google_skyrim.with_binaries
Normal file
@@ -0,0 +1,31 @@
|
||||
CONFIG_TIMESTAMPS_ON_CONSOLE=y
|
||||
CONFIG_USE_AMD_BLOBS=y
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_VGA_BIOS_ID="1002,1506"
|
||||
CONFIG_AMD_FWM_POSITION_INDEX=3
|
||||
CONFIG_VGA_BIOS=y
|
||||
CONFIG_CONSOLE_POST=y
|
||||
CONFIG_BOARD_GOOGLE_SKYRIM=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin"
|
||||
CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin"
|
||||
CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
|
||||
CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
|
||||
CONFIG_ASYNC_FILE_LOADING=y
|
||||
CONFIG_PSP_SOFTFUSE_BITS="34 28"
|
||||
CONFIG_UART_PCI_ADDR=0x0
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_DISPLAY_HOBS=y
|
||||
CONFIG_DISPLAY_UPD_DATA=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
|
||||
CONFIG_DISPLAY_FSP_HEADER=y
|
||||
CONFIG_FATAL_ASSERTS=y
|
||||
CONFIG_DEBUG_SMI=y
|
||||
CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y
|
||||
CONFIG_ADD_POSTCODES_TO_STB=y
|
3
configs/config.google_vilboz.x86_64
Normal file
3
configs/config.google_vilboz.x86_64
Normal file
@@ -0,0 +1,3 @@
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_BOARD_GOOGLE_VILBOZ=y
|
||||
CONFIG_USE_EXP_X86_64_SUPPORT=y
|
@@ -4,7 +4,6 @@ CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_BOARD_INTEL_HARCUVAR=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_ENABLE_HSUART=y
|
||||
CONFIG_UART_PCI_ADDR=0x8000d000
|
||||
|
||||
#Sample settings for Denverton-NS FSP.
|
||||
#CONFIG_ADD_FSP_BINARIES=y
|
||||
|
@@ -10,3 +10,4 @@ CONFIG_DEBUG_MALLOC=y
|
||||
CONFIG_DEBUG_SPI_FLASH=y
|
||||
CONFIG_DEBUG_BOOT_STATE=y
|
||||
CONFIG_DEBUG_ADA_CODE=y
|
||||
CONFIG_USE_EXP_X86_64_SUPPORT=y
|
||||
|
21
configs/config.msi_ms7d25_ddr5
Normal file
21
configs/config.msi_ms7d25_ddr5
Normal file
@@ -0,0 +1,21 @@
|
||||
CONFIG_VENDOR_MSI=y
|
||||
CONFIG_CBFS_SIZE=0x1000000
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_EDK2_BOOT_TIMEOUT=3
|
||||
CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_POST_DEVICE_PCI_PCIE=y
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_PAYLOAD_EDK2=y
|
||||
CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git"
|
||||
CONFIG_EDK2_TAG_OR_REV="origin/dasharo"
|
||||
CONFIG_EDK2_CBMEM_LOGGING=y
|
||||
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
|
||||
CONFIG_EDK2_SD_MMC_TIMEOUT=1000
|
||||
CONFIG_TPM2=y
|
||||
CONFIG_TPM_MEASURED_BOOT=y
|
||||
CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
|
||||
CONFIG_DRIVERS_GENERIC_CBFS_UUID=y
|
@@ -13,3 +13,4 @@ CONFIG_POST_DEVICE_LPC=y
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
|
||||
CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
|
||||
CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
|
17
configs/config.prodrive_hermes.x86_64
Normal file
17
configs/config.prodrive_hermes.x86_64
Normal file
@@ -0,0 +1,17 @@
|
||||
# Settings used by Prodrive to build coreboot for the Hermes but with x86_64 enabled
|
||||
CONFIG_VENDOR_PRODRIVE=y
|
||||
CONFIG_BOARD_PRODRIVE_HERMES=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Technologies B.V."
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
CONFIG_HERMES_USES_SPS_FIRMWARE=y
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_SMMSTORE=y
|
||||
CONFIG_SMMSTORE_V2=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
|
||||
CONFIG_POST_DEVICE_LPC=y
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
|
||||
CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
|
||||
CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_USE_EXP_X86_64_SUPPORT=y
|
@@ -1,15 +1,8 @@
|
||||
menu "Payload"
|
||||
|
||||
config NO_DEFAULT_PAYLOAD
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Add a payload"
|
||||
default PAYLOAD_NONE if NO_DEFAULT_PAYLOAD || !ARCH_X86
|
||||
default PAYLOAD_SEABIOS if ARCH_X86
|
||||
|
||||
config PAYLOAD_NONE
|
||||
bool "None"
|
||||
bool "Don't add a payload"
|
||||
default y if !ARCH_X86
|
||||
help
|
||||
Select this option if you want to create an "empty" coreboot
|
||||
ROM image for a certain mainboard, i.e. a coreboot ROM image
|
||||
@@ -18,6 +11,11 @@ config PAYLOAD_NONE
|
||||
For such an image to be useful, you have to use 'cbfstool'
|
||||
to add a payload to the ROM image later.
|
||||
|
||||
if !PAYLOAD_NONE
|
||||
choice
|
||||
prompt "Payload to add"
|
||||
default PAYLOAD_SEABIOS if ARCH_X86
|
||||
|
||||
config PAYLOAD_ELF
|
||||
bool "An ELF executable payload"
|
||||
help
|
||||
@@ -58,7 +56,7 @@ choice
|
||||
prompt "Payload compression algorithm"
|
||||
default COMPRESSED_PAYLOAD_LZMA
|
||||
default COMPRESSED_PAYLOAD_NONE if PAYLOAD_LINUX || PAYLOAD_LINUXBOOT || PAYLOAD_FIT
|
||||
depends on !PAYLOAD_NONE && !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
|
||||
depends on !PAYLOAD_LINUX && !PAYLOAD_LINUXBOOT && !PAYLOAD_FIT
|
||||
help
|
||||
Choose the compression algorithm for the chosen payloads.
|
||||
You can choose between None, LZMA, or LZ4.
|
||||
@@ -178,4 +176,7 @@ config COREDOOM_SECONDARY_PAYLOAD
|
||||
source "payloads/external/*/Kconfig.secondary"
|
||||
|
||||
endmenu # "Secondary Payloads"
|
||||
|
||||
endif # !PAYLOAD_NONE
|
||||
|
||||
endmenu
|
||||
|
2
payloads/external/FILO/Kconfig.name
vendored
2
payloads/external/FILO/Kconfig.name
vendored
@@ -6,4 +6,4 @@ config PAYLOAD_FILO
|
||||
with a FILO payload. If you don't know what this is
|
||||
about, just leave it enabled.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
2
payloads/external/GRUB2/Kconfig
vendored
2
payloads/external/GRUB2/Kconfig
vendored
@@ -15,7 +15,7 @@ choice
|
||||
default GRUB2_STABLE
|
||||
|
||||
config GRUB2_STABLE
|
||||
bool "2.04"
|
||||
bool "2.06"
|
||||
help
|
||||
Stable GRUB2 version
|
||||
|
||||
|
4
payloads/external/GRUB2/Kconfig.name
vendored
4
payloads/external/GRUB2/Kconfig.name
vendored
@@ -7,7 +7,7 @@ config PAYLOAD_GRUB2
|
||||
with a GRUB2 payload. If you don't know what this is
|
||||
about, just leave it enabled.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
||||
config PAYLOAD_SEAGRUB
|
||||
bool "GRUB2 atop SeaBIOS"
|
||||
@@ -19,4 +19,4 @@ config PAYLOAD_SEAGRUB
|
||||
with a GRUB2 payload running atop SeaBIOS to improve its
|
||||
hardware compatibility.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
6
payloads/external/GRUB2/Makefile
vendored
6
payloads/external/GRUB2/Makefile
vendored
@@ -1,9 +1,9 @@
|
||||
TAG-$(CONFIG_GRUB2_MASTER)=origin/HEAD
|
||||
TAG-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
|
||||
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.04
|
||||
TAG-$(CONFIG_GRUB2_STABLE)=grub-2.06
|
||||
NAME-$(CONFIG_GRUB2_MASTER)=HEAD
|
||||
NAME-$(CONFIG_GRUB2_REVISION)=$(CONFIG_GRUB2_REVISION_ID)
|
||||
NAME-$(CONFIG_GRUB2_STABLE)=2.04
|
||||
NAME-$(CONFIG_GRUB2_STABLE)=2.06
|
||||
|
||||
project_git_repo=https://git.savannah.gnu.org/git/grub.git/
|
||||
project_dir=grub2
|
||||
@@ -34,7 +34,7 @@ grub2/build/config.h: $(CONFIG_DEP) | checkout
|
||||
cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \
|
||||
FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \
|
||||
TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \
|
||||
CFLAGS=-O2 TARGET_CFLAGS=-Os \
|
||||
CFLAGS=-O2 TARGET_CFLAGS="-Os -fno-reorder-functions" \
|
||||
--with-platform=coreboot --enable-boot-time --disable-werror
|
||||
|
||||
config: grub2/build/config.h checkout
|
||||
|
2
payloads/external/LinuxBoot/Kconfig.name
vendored
2
payloads/external/LinuxBoot/Kconfig.name
vendored
@@ -8,4 +8,4 @@ config PAYLOAD_LINUXBOOT
|
||||
with a LinuxBoot payload. If you don't know what this is
|
||||
about, just leave it enabled.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
2
payloads/external/LinuxBoot/targets/linux.mk
vendored
2
payloads/external/LinuxBoot/targets/linux.mk
vendored
@@ -45,6 +45,8 @@ else ifeq ($(findstring x4.,x$(kernel_version)),x4.)
|
||||
kernel_mirror_path := $(kernel_mirror)/v4.x
|
||||
else ifeq ($(findstring x5.,x$(kernel_version)),x5.)
|
||||
kernel_mirror_path := $(kernel_mirror)/v5.x
|
||||
else ifeq ($(findstring x6.,x$(kernel_version)),x6.)
|
||||
kernel_mirror_path := $(kernel_mirror)/v6.x
|
||||
endif
|
||||
|
||||
all: kernel
|
||||
|
43
payloads/external/Makefile.inc
vendored
43
payloads/external/Makefile.inc
vendored
@@ -164,6 +164,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
|
||||
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
|
||||
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
|
||||
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
|
||||
CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \
|
||||
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
|
||||
CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
|
||||
CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
|
||||
@@ -182,6 +183,48 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
|
||||
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
|
||||
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
|
||||
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
|
||||
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
|
||||
GCC_CC_x86_32=$(GCC_CC_x86_32) \
|
||||
GCC_CC_x86_64=$(GCC_CC_x86_64) \
|
||||
GCC_CC_arm=$(GCC_CC_arm) \
|
||||
GCC_CC_arm64=$(GCC_CC_arm64) \
|
||||
OBJCOPY_x86_32=$(OBJCOPY_x86_32) \
|
||||
OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
|
||||
OBJCOPY_arm=$(OBJCOPY_arm) \
|
||||
OBJCOPY_arm64=$(OBJCOPY_arm64) \
|
||||
MFLAGS= MAKEFLAGS=
|
||||
|
||||
$(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
|
||||
$(MAKE) -C payloads/external/edk2 UniversalPayload \
|
||||
HOSTCC="$(HOSTCC)" \
|
||||
CC="$(HOSTCC)" \
|
||||
CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
|
||||
CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
|
||||
CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
|
||||
CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
|
||||
CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
|
||||
CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
|
||||
CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \
|
||||
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
|
||||
CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
|
||||
CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
|
||||
CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
|
||||
CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
|
||||
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
|
||||
CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
|
||||
CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \
|
||||
CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \
|
||||
CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \
|
||||
CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \
|
||||
CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \
|
||||
CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \
|
||||
CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \
|
||||
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
|
||||
CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
|
||||
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
|
||||
CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
|
||||
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
|
||||
GCC_CC_x86_32=$(GCC_CC_x86_32) \
|
||||
GCC_CC_x86_64=$(GCC_CC_x86_64) \
|
||||
|
2
payloads/external/SeaBIOS/Kconfig
vendored
2
payloads/external/SeaBIOS/Kconfig
vendored
@@ -15,7 +15,7 @@ choice
|
||||
default SEABIOS_STABLE
|
||||
|
||||
config SEABIOS_STABLE
|
||||
bool "1.16.0"
|
||||
bool "1.16.1"
|
||||
help
|
||||
Stable SeaBIOS version
|
||||
config SEABIOS_MASTER
|
||||
|
2
payloads/external/SeaBIOS/Kconfig.name
vendored
2
payloads/external/SeaBIOS/Kconfig.name
vendored
@@ -7,4 +7,4 @@ config PAYLOAD_SEABIOS
|
||||
with a SeaBIOS payload. If you don't know what this is
|
||||
about, just leave it enabled.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
2
payloads/external/SeaBIOS/Makefile
vendored
2
payloads/external/SeaBIOS/Makefile
vendored
@@ -1,5 +1,5 @@
|
||||
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
|
||||
TAG-$(CONFIG_SEABIOS_STABLE)=d239552ce7220e448ae81f41515138f7b9e3c4db
|
||||
TAG-$(CONFIG_SEABIOS_STABLE)=3208b098f51a9ef96d0dfa71d5ec3a3eaec88f0a
|
||||
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
|
||||
|
||||
project_git_repo=https://review.coreboot.org/seabios.git
|
||||
|
2
payloads/external/U-Boot/Kconfig.name
vendored
2
payloads/external/U-Boot/Kconfig.name
vendored
@@ -5,6 +5,6 @@ config PAYLOAD_UBOOT
|
||||
Select this option if you want to build a coreboot image
|
||||
with a U-Boot payload.
|
||||
|
||||
See https://coreboot.org/Payloads and U-Boot's documentation
|
||||
See https://doc.coreboot.org/payloads.html and U-Boot's documentation
|
||||
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
|
||||
for more information.
|
||||
|
2
payloads/external/depthcharge/Kconfig.name
vendored
2
payloads/external/depthcharge/Kconfig.name
vendored
@@ -5,4 +5,4 @@ config PAYLOAD_DEPTHCHARGE
|
||||
Select this option if you want to build a coreboot image
|
||||
with a depthcharge payload.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
14
payloads/external/edk2/Kconfig
vendored
14
payloads/external/edk2/Kconfig
vendored
@@ -155,6 +155,20 @@ config EDK2_CBMEM_LOGGING
|
||||
this option, especially if using a debug (vs release) build.
|
||||
Selecting this option will increase the payload size in CBFS by 0x10000.
|
||||
|
||||
config EDK2_CPU_TIMER_LIB
|
||||
bool
|
||||
default n
|
||||
help
|
||||
For recent Intel and AMD CPUs, the 0x15 CPUID instruction will return Time
|
||||
Stamp Counter Frequence. For CPUs that do not support this instruction,
|
||||
EDK2 must include a different library which is the reason why this must be
|
||||
configured at build time.
|
||||
|
||||
If this is enabled, and the CPU doesn't support 0x15, it will fail to
|
||||
boot. If it is not enabled, and the CPU does support 0x15, it will still
|
||||
boot but without support for the leaf. Consequently, it is disabled by
|
||||
default.
|
||||
|
||||
config EDK2_FOLLOW_BGRT_SPEC
|
||||
bool "Center logo 38.2% from the top of screen"
|
||||
default n
|
||||
|
2
payloads/external/edk2/Kconfig.name
vendored
2
payloads/external/edk2/Kconfig.name
vendored
@@ -6,4 +6,4 @@ config PAYLOAD_EDK2
|
||||
with a edk2 payload. If you don't know what this is
|
||||
about, just leave it enabled.
|
||||
|
||||
See https://coreboot.org/Payloads for more information.
|
||||
See https://doc.coreboot.org/payloads.html for more information.
|
||||
|
14
payloads/external/edk2/Makefile
vendored
14
payloads/external/edk2/Makefile
vendored
@@ -8,6 +8,8 @@ export WORKSPACE := $(CURDIR)/workspace
|
||||
export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
|
||||
export PACKAGES_PATH := $(EDK2_PATH)
|
||||
|
||||
OBJCOPY = $(GCC_PREFIX)objcopy
|
||||
|
||||
ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
|
||||
BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc
|
||||
endif
|
||||
@@ -44,6 +46,12 @@ RELEASE_STR = DEBUG
|
||||
else
|
||||
RELEASE_STR = RELEASE
|
||||
endif
|
||||
# CPU_TIMER_LIB_ENABLE = TRUE
|
||||
ifneq ($(CONFIG_EDK2_CPU_TIMER_LIB),y)
|
||||
BUILD_STR += -D CPU_TIMER_LIB_ENABLE=FALSE
|
||||
else
|
||||
BUILD_STR += --pcd gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency=$(CONFIG_CPU_XTAL_HZ)
|
||||
endif
|
||||
# DISABLE_SERIAL_TERMINAL = FALSE
|
||||
ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
|
||||
BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
|
||||
@@ -229,10 +237,14 @@ UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/
|
||||
mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \
|
||||
../../../build/UEFIPAYLOAD.fd
|
||||
|
||||
UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll
|
||||
mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \
|
||||
../../../build/ShimmedUniversalPayload.elf
|
||||
|
||||
clean:
|
||||
test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
|
||||
|
||||
distclean:
|
||||
rm -rf $(WORKSPACE)
|
||||
|
||||
.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg clean distclean
|
||||
.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean
|
||||
|
@@ -93,7 +93,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
|
||||
media->context = (void*)romsize;
|
||||
#if CONFIG(LP_ROM_SIZE)
|
||||
if (CONFIG_LP_ROM_SIZE != romsize)
|
||||
printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
|
||||
printk(BIOS_WARNING, "rom size unmatch (%d/%d)\n",
|
||||
CONFIG_LP_ROM_SIZE, romsize);
|
||||
#endif
|
||||
}
|
||||
|
@@ -72,9 +72,9 @@ static void serial_write_reg(uint8_t val, int offset)
|
||||
static void serial_hardware_init(int speed, int word_bits,
|
||||
int parity, int stop_bits)
|
||||
{
|
||||
#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
|
||||
unsigned char reg;
|
||||
|
||||
#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
|
||||
/* Disable interrupts. */
|
||||
serial_write_reg(0, 0x01);
|
||||
|
||||
|
@@ -502,7 +502,7 @@ static void complete_ep_transfer(struct usbdev_ctrl *this, int endpoint,
|
||||
}
|
||||
SIMPLEQ_REMOVE_HEAD(&p->eps[endpoint][in_dir].job_queue, queue);
|
||||
|
||||
usb_debug("%d-%d: scheduled %zd, now %d bytes\n", endpoint, in_dir,
|
||||
usb_debug("%d-%d: scheduled %zd, now %zd bytes\n", endpoint, in_dir,
|
||||
job->length, job->xfered_length);
|
||||
|
||||
if (this->current_config &&
|
||||
|
@@ -191,14 +191,6 @@ struct cb_serial {
|
||||
* decisions as to which dividers to select and their values
|
||||
* to eventually arrive at the desired console baud-rate. */
|
||||
u32 input_hertz;
|
||||
|
||||
/* UART PCI address: bus, device, function
|
||||
* 1 << 31 - Valid bit, PCI UART in use
|
||||
* Bus << 20
|
||||
* Device << 15
|
||||
* Function << 12
|
||||
*/
|
||||
u32 uart_pci_addr;
|
||||
};
|
||||
|
||||
struct cb_console {
|
||||
|
@@ -206,7 +206,7 @@
|
||||
},
|
||||
{
|
||||
// Datasheet Revision: Rev. 1.0 Dec. 2021
|
||||
"name": "H5AG36EXNDX019",
|
||||
"name": "H5AG36EXNDX017",
|
||||
"attribs": {
|
||||
"speedMTps": 3200,
|
||||
"CL_nRCD_nRP": 22,
|
||||
|
@@ -17,7 +17,7 @@ H5AN8G6NCJR-XNC,spd-1.hex
|
||||
K4AAG165WA-BCTD,spd-8.hex
|
||||
H5ANAG6NDMR-XNC,spd-2.hex
|
||||
H5ANAG6NCJR-XNC,spd-9.hex
|
||||
H5AG36EXNDX019,spd-1.hex
|
||||
H5AG36EXNDX017,spd-1.hex
|
||||
K4AAG165WB-BCWE,spd-9.hex
|
||||
MT40A1G16RC-062E:B,spd-9.hex
|
||||
MT40A512M16TB-062E:R,spd-1.hex
|
||||
|
@@ -175,6 +175,16 @@
|
||||
"speedMbps": 7500,
|
||||
"lp5x": true
|
||||
}
|
||||
},
|
||||
{
|
||||
"name": "H9JCNNNFA5MLYR-N6E",
|
||||
"attribs": {
|
||||
"densityPerDieGb": 8,
|
||||
"diesPerPackage": 8,
|
||||
"bitWidthPerChannel": 8,
|
||||
"ranksPerChannel": 2,
|
||||
"speedMbps": 6400
|
||||
}
|
||||
}
|
||||
]
|
||||
}
|
||||
|
@@ -18,3 +18,4 @@ K3KL8L80CM-MGCT,spd-7.hex
|
||||
K3KL9L90CM-MGCT,spd-8.hex
|
||||
H58G66BK7BX067,spd-8.hex
|
||||
H58G56BK7BX068,spd-7.hex
|
||||
H9JCNNNFA5MLYR-N6E,spd-4.hex
|
||||
|
32
spd/lp5/set-0/spd-9.hex
Normal file
32
spd/lp5/set-0/spd-9.hex
Normal file
@@ -0,0 +1,32 @@
|
||||
23 10 13 0E 15 1A F9 08 00 00 00 00 0A 01 00 00
|
||||
00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
|
||||
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
@@ -18,3 +18,4 @@ K3KL8L80CM-MGCT,spd-7.hex
|
||||
K3KL9L90CM-MGCT,spd-8.hex
|
||||
H58G66BK7BX067,spd-8.hex
|
||||
H58G56BK7BX068,spd-7.hex
|
||||
H9JCNNNFA5MLYR-N6E,spd-4.hex
|
||||
|
@@ -1,4 +1,4 @@
|
||||
23 11 15 0E 86 21 95 18 00 40 00 00 02 02 00 00
|
||||
23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
|
||||
00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
|
||||
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
@@ -1,4 +1,4 @@
|
||||
23 11 15 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
|
||||
23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
|
||||
00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60
|
||||
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
32
spd/lp5/set-1/spd-9.hex
Normal file
32
spd/lp5/set-1/spd-9.hex
Normal file
@@ -0,0 +1,32 @@
|
||||
23 11 13 0E 85 19 F9 18 00 40 00 00 0A 02 00 00
|
||||
00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
|
||||
03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
64
src/Kconfig
64
src/Kconfig
@@ -170,23 +170,47 @@ config STATIC_OPTION_TABLE
|
||||
every boot. Use this if you want the NVRAM configuration to
|
||||
never be modified from its default values.
|
||||
|
||||
config COMPRESS_RAMSTAGE
|
||||
bool "Compress ramstage with LZMA"
|
||||
depends on HAVE_RAMSTAGE
|
||||
# Default value set at the end of the file
|
||||
config MB_COMPRESS_RAMSTAGE_LZ4
|
||||
bool
|
||||
help
|
||||
Compress ramstage to save memory in the flash image.
|
||||
Select this in a mainboard to use LZ4 compression by default
|
||||
|
||||
choice
|
||||
prompt "Ramstage compression"
|
||||
depends on HAVE_RAMSTAGE && !UNCOMPRESSED_RAMSTAGE
|
||||
default COMPRESS_RAMSTAGE_LZ4 if MB_COMPRESS_RAMSTAGE_LZ4
|
||||
default COMPRESS_RAMSTAGE_LZMA
|
||||
|
||||
config COMPRESS_RAMSTAGE_LZMA
|
||||
bool "Compress ramstage with LZMA"
|
||||
help
|
||||
Compress ramstage with LZMA to save memory in the flash image.
|
||||
|
||||
config COMPRESS_RAMSTAGE_LZ4
|
||||
bool "Compress ramstage with LZ4"
|
||||
help
|
||||
LZ4 doesn't give as good compression as LZMA, but decompresses much
|
||||
faster. For large binaries such as ramstage, it's typically best to
|
||||
use LZMA, but there can be cases where the faster decompression of
|
||||
LZ4 can lead to a faster boot time. Testing on each individual board
|
||||
is typically going to be needed due to the large number of factors
|
||||
that can influence the decision. Binary size, CPU speed, ROM read
|
||||
speed, cache, and other factors all play a part.
|
||||
|
||||
If you're not sure, stick with LZMA.
|
||||
|
||||
endchoice
|
||||
|
||||
config COMPRESS_PRERAM_STAGES
|
||||
bool "Compress romstage and verstage with LZ4"
|
||||
depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
|
||||
depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
|
||||
# Default value set at the end of the file
|
||||
help
|
||||
Compress romstage and (if it exists) verstage with LZ4 to save flash
|
||||
space and speed up boot, since the time for reading the image from SPI
|
||||
(and in the vboot case verifying it) is usually much greater than the
|
||||
time spent decompressing. Doesn't work for XIP stages (assume all
|
||||
ARCH_X86 for now) for obvious reasons.
|
||||
time spent decompressing. Doesn't work for XIP stages for obvious
|
||||
reasons.
|
||||
|
||||
config COMPRESS_BOOTBLOCK
|
||||
bool
|
||||
@@ -211,9 +235,9 @@ config INCLUDE_CONFIG_FILE
|
||||
|
||||
Saying Y here will increase the image size by 2-3KB.
|
||||
|
||||
You can use the following command to easily list the options:
|
||||
You can then use cbfstool to extract the config from a final image:
|
||||
|
||||
grep -a CONFIG_ coreboot.rom
|
||||
cbfstool coreboot.rom extract -n config -f <output file path>
|
||||
|
||||
Alternatively, you can also use cbfstool to print the image
|
||||
contents (including the raw 'config' item we're looking for).
|
||||
@@ -347,7 +371,7 @@ endif
|
||||
|
||||
choice
|
||||
prompt "Stage Cache for ACPI S3 resume"
|
||||
default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
|
||||
default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || MAINBOARD_DISABLE_STAGE_CACHE
|
||||
default TSEG_STAGE_CACHE if SMM_TSEG
|
||||
|
||||
config NO_STAGE_CACHE
|
||||
@@ -380,6 +404,13 @@ config CBMEM_STAGE_CACHE
|
||||
|
||||
endchoice
|
||||
|
||||
config MAINBOARD_DISABLE_STAGE_CACHE
|
||||
bool
|
||||
help
|
||||
Selected by mainboards which wish to disable the stage cache.
|
||||
E.g. mainboards which don't use S3 resume in the field may wish to
|
||||
disable it to save boot time at the cost of increasing S3 resume time.
|
||||
|
||||
config UPDATE_IMAGE
|
||||
bool "Update existing coreboot.rom image"
|
||||
help
|
||||
@@ -715,7 +746,7 @@ config TIMER_QUEUE
|
||||
config COOP_MULTITASKING
|
||||
def_bool n
|
||||
select TIMER_QUEUE
|
||||
depends on ARCH_X86 && CPU_INFO_V2
|
||||
depends on ARCH_X86
|
||||
help
|
||||
Cooperative multitasking allows callbacks to be multiplexed on the
|
||||
main thread. With this enabled it allows for multiple execution paths
|
||||
@@ -795,9 +826,9 @@ config ACPI_NHLT
|
||||
menu "System tables"
|
||||
|
||||
config GENERATE_MP_TABLE
|
||||
prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
||||
prompt "Generate an MP table" if HAVE_MP_TABLE
|
||||
bool
|
||||
default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
||||
default HAVE_MP_TABLE
|
||||
help
|
||||
Generate an MP table (conforming to the Intel MultiProcessor
|
||||
specification 1.4) for this board.
|
||||
@@ -1372,11 +1403,8 @@ config MEMLAYOUT_LD_FILE
|
||||
# Set default values for symbols created before mainboards. This allows the
|
||||
# option to be displayed in the general menu, but the default to be loaded in
|
||||
# the mainboard if desired.
|
||||
config COMPRESS_RAMSTAGE
|
||||
default y if !UNCOMPRESSED_RAMSTAGE
|
||||
|
||||
config COMPRESS_PRERAM_STAGES
|
||||
depends on !ARCH_X86
|
||||
depends on (HAVE_ROMSTAGE || HAVE_VERSTAGE) && NO_XIP_EARLY_STAGES
|
||||
default y
|
||||
|
||||
config INCLUDE_CONFIG_FILE
|
||||
|
@@ -8,7 +8,7 @@ config ACPI_AMD_HARDWARE_SLEEP_VALUES
|
||||
|
||||
config ACPI_CPU_STRING
|
||||
string
|
||||
default "\\_SB.CP%02d"
|
||||
default "\\_SB.CP%02X"
|
||||
depends on HAVE_ACPI_TABLES
|
||||
help
|
||||
Sets the ACPI name string in the processor scope as written by
|
||||
@@ -30,6 +30,11 @@ config ACPI_SOC_NVS
|
||||
Set to indicate <soc/nvs.h> exists for the platform with a definition
|
||||
for global_nvs.
|
||||
|
||||
config ACPI_NO_MADT
|
||||
bool
|
||||
help
|
||||
Selected by platforms that don't expose a useful MADT.
|
||||
|
||||
config ACPI_NO_PCAT_8259
|
||||
bool
|
||||
help
|
||||
|
193
src/acpi/acpi.c
193
src/acpi/acpi.c
@@ -30,6 +30,10 @@
|
||||
#include <types.h>
|
||||
#include <version.h>
|
||||
|
||||
#if ENV_X86
|
||||
#include <arch/ioapic.h>
|
||||
#endif
|
||||
|
||||
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp);
|
||||
|
||||
u8 acpi_checksum(u8 *table, u32 length)
|
||||
@@ -180,6 +184,22 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,
|
||||
return ioapic->length;
|
||||
}
|
||||
|
||||
#if ENV_X86
|
||||
/* For a system with multiple I/O APICs it's required that the one potentially
|
||||
routing i8259 via ExtNMI delivery calls this first to get GSI #0. */
|
||||
int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr)
|
||||
{
|
||||
static u32 gsi_base;
|
||||
u32 my_base;
|
||||
u8 id = get_ioapic_id((void *)(uintptr_t)addr);
|
||||
u8 count = ioapic_get_max_vectors((void *)(uintptr_t)addr);
|
||||
|
||||
my_base = gsi_base;
|
||||
gsi_base += count;
|
||||
return acpi_create_madt_ioapic(ioapic, id, addr, my_base);
|
||||
}
|
||||
#endif
|
||||
|
||||
int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
|
||||
u8 bus, u8 source, u32 gsirq, u16 flags)
|
||||
{
|
||||
@@ -220,6 +240,24 @@ int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
|
||||
return lapic_nmi->length;
|
||||
}
|
||||
|
||||
unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current)
|
||||
{
|
||||
const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH;
|
||||
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* 1: LINT1 connect to NMI */
|
||||
/* create all subtables for processors */
|
||||
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
|
||||
ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1);
|
||||
|
||||
if (!CONFIG(XAPIC_ONLY))
|
||||
current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current,
|
||||
ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
void acpi_create_madt(acpi_madt_t *madt)
|
||||
{
|
||||
acpi_header_t *header = &(madt->header);
|
||||
@@ -244,7 +282,8 @@ void acpi_create_madt(acpi_madt_t *madt)
|
||||
if (CONFIG(ACPI_HAVE_PCAT_8259))
|
||||
madt->flags |= 1;
|
||||
|
||||
current = acpi_fill_madt(current);
|
||||
if (!CONFIG(ACPI_NO_MADT))
|
||||
current = acpi_fill_madt(current);
|
||||
|
||||
/* (Re)calculate length and checksum. */
|
||||
header->length = current - (unsigned long)madt;
|
||||
@@ -341,7 +380,7 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa)
|
||||
|
||||
tcpa->platform_class = 0;
|
||||
tcpa->laml = tcpa_log_len;
|
||||
tcpa->lasa = (uintptr_t) lasa;
|
||||
tcpa->lasa = (uintptr_t)lasa;
|
||||
|
||||
/* Calculate checksum. */
|
||||
header->checksum = acpi_checksum((void *)tcpa, header->length);
|
||||
@@ -416,7 +455,7 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2)
|
||||
|
||||
/* Fill the log area size and start address fields. */
|
||||
tpm2->laml = tpm2_log_len;
|
||||
tpm2->lasa = (uintptr_t) lasa;
|
||||
tpm2->lasa = (uintptr_t)lasa;
|
||||
|
||||
/* Calculate checksum. */
|
||||
header->checksum = acpi_checksum((void *)tpm2, header->length);
|
||||
@@ -460,7 +499,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
|
||||
ssdt->asl_compiler_revision = asl_revision;
|
||||
ssdt->length = sizeof(acpi_header_t);
|
||||
|
||||
acpigen_set_current((char *) current);
|
||||
acpigen_set_current((char *)current);
|
||||
|
||||
/* Write object to declare coreboot tables */
|
||||
acpi_ssdt_write_cbtable();
|
||||
@@ -470,7 +509,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
|
||||
for (dev = all_devices; dev; dev = dev->next)
|
||||
if (dev->enabled && dev->ops && dev->ops->acpi_fill_ssdt)
|
||||
dev->ops->acpi_fill_ssdt(dev);
|
||||
current = (unsigned long) acpigen_get_current();
|
||||
current = (unsigned long)acpigen_get_current();
|
||||
}
|
||||
|
||||
/* (Re)calculate length and checksum. */
|
||||
@@ -555,6 +594,90 @@ void acpi_create_srat(acpi_srat_t *srat,
|
||||
header->checksum = acpi_checksum((void *)srat, header->length);
|
||||
}
|
||||
|
||||
int acpi_create_cedt_chbs(acpi_cedt_chbs_t *chbs, u32 uid, u32 cxl_ver, u64 base)
|
||||
{
|
||||
memset((void *)chbs, 0, sizeof(acpi_cedt_chbs_t));
|
||||
|
||||
chbs->type = ACPI_CEDT_STRUCTURE_CHBS;
|
||||
chbs->length = sizeof(acpi_cedt_chbs_t);
|
||||
chbs->uid = uid;
|
||||
chbs->cxl_ver = cxl_ver;
|
||||
chbs->base = base;
|
||||
|
||||
/*
|
||||
* CXL spec 2.0 section 9.14.1.2 "CXL CHBS"
|
||||
* CXL 1.1 spec compliant host bridge: 8KB
|
||||
* CXL 2.0 spec compliant host bridge: 64KB
|
||||
*/
|
||||
if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_1_1)
|
||||
chbs->len = 8 * KiB;
|
||||
else if (cxl_ver == ACPI_CEDT_CHBS_CXL_VER_2_0)
|
||||
chbs->len = 64 * KiB;
|
||||
else
|
||||
printk(BIOS_ERR, "ACPI(%s:%s): Incorrect CXL version:%d\n", __FILE__, __func__,
|
||||
cxl_ver);
|
||||
|
||||
return chbs->length;
|
||||
}
|
||||
|
||||
int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw,
|
||||
u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target)
|
||||
{
|
||||
memset((void *)cfmws, 0, sizeof(acpi_cedt_cfmws_t));
|
||||
|
||||
cfmws->type = ACPI_CEDT_STRUCTURE_CFMWS;
|
||||
|
||||
u8 niw = 0;
|
||||
if (eniw >= 8)
|
||||
printk(BIOS_ERR, "ACPI(%s:%s): Incorrect eniw::%d\n", __FILE__, __func__, eniw);
|
||||
else
|
||||
/* NIW = 2 ** ENIW */
|
||||
niw = 0x1 << eniw;
|
||||
/* 36 + 4 * NIW */
|
||||
cfmws->length = sizeof(acpi_cedt_cfmws_t) + 4 * niw;
|
||||
|
||||
cfmws->base_hpa = base_hpa;
|
||||
cfmws->window_size = window_size;
|
||||
cfmws->eniw = eniw;
|
||||
|
||||
// 0: Standard Modulo Arithmetic. Other values reserved.
|
||||
cfmws->interleave_arithmetic = 0;
|
||||
|
||||
cfmws->hbig = hbig;
|
||||
cfmws->restriction = restriction;
|
||||
cfmws->qtg_id = qtg_id;
|
||||
memcpy(&cfmws->interleave_target, interleave_target, 4 * niw);
|
||||
|
||||
return cfmws->length;
|
||||
}
|
||||
|
||||
void acpi_create_cedt(acpi_cedt_t *cedt, unsigned long (*acpi_fill_cedt)(unsigned long current))
|
||||
{
|
||||
acpi_header_t *header = &(cedt->header);
|
||||
unsigned long current = (unsigned long)cedt + sizeof(acpi_cedt_t);
|
||||
|
||||
memset((void *)cedt, 0, sizeof(acpi_cedt_t));
|
||||
|
||||
if (!header)
|
||||
return;
|
||||
|
||||
/* Fill out header fields. */
|
||||
memcpy(header->signature, "CEDT", 4);
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
|
||||
header->asl_compiler_revision = asl_revision;
|
||||
header->length = sizeof(acpi_cedt_t);
|
||||
header->revision = get_acpi_table_revision(CEDT);
|
||||
|
||||
current = acpi_fill_cedt(current);
|
||||
|
||||
/* (Re)calculate length and checksum. */
|
||||
header->length = current - (unsigned long)cedt;
|
||||
header->checksum = acpi_checksum((void *)cedt, header->length);
|
||||
}
|
||||
|
||||
int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory)
|
||||
{
|
||||
memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t));
|
||||
@@ -775,6 +898,14 @@ unsigned long acpi_create_dmar_ds_ioapic(unsigned long current,
|
||||
SCOPE_IOAPIC, enumeration_id, bus, dev, fn);
|
||||
}
|
||||
|
||||
unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current,
|
||||
u32 addr, u8 bus, u8 dev, u8 fn)
|
||||
{
|
||||
u8 enumeration_id = get_ioapic_id((void *)(uintptr_t)addr);
|
||||
return acpi_create_dmar_ds(current,
|
||||
SCOPE_IOAPIC, enumeration_id, bus, dev, fn);
|
||||
}
|
||||
|
||||
unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current,
|
||||
u8 enumeration_id, u8 bus, u8 dev, u8 fn)
|
||||
{
|
||||
@@ -868,7 +999,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
|
||||
|
||||
printk(BIOS_DEBUG, "%s einj_smi = %p\n", __func__, einj_smi);
|
||||
memset(einj_smi, 0, sizeof(acpi_einj_smi_t));
|
||||
tat = (acpi_einj_trigger_table_t *)(einj_smi + sizeof(acpi_einj_smi_t));
|
||||
tat = (acpi_einj_trigger_table_t *)((uint8_t *)einj_smi + sizeof(acpi_einj_smi_t));
|
||||
tat->header_size = 16;
|
||||
tat->revision = 0;
|
||||
tat->table_size = sizeof(acpi_einj_trigger_table_t) +
|
||||
@@ -966,7 +1097,7 @@ void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions)
|
||||
};
|
||||
|
||||
einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP;
|
||||
einj_smi->trigger_action_table = (u64) (uintptr_t)tat;
|
||||
einj_smi->trigger_action_table = (u64)(uintptr_t)tat;
|
||||
|
||||
for (i = 0; i < ACTION_COUNT; i++)
|
||||
printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i,
|
||||
@@ -1144,7 +1275,7 @@ unsigned long acpi_write_hpet(const struct device *device, unsigned long current
|
||||
*/
|
||||
printk(BIOS_DEBUG, "ACPI: * HPET\n");
|
||||
|
||||
hpet = (acpi_hpet_t *) current;
|
||||
hpet = (acpi_hpet_t *)current;
|
||||
current += sizeof(acpi_hpet_t);
|
||||
current = ALIGN_UP(current, 16);
|
||||
acpi_create_hpet(hpet);
|
||||
@@ -1390,7 +1521,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
|
||||
case 0: /* MCE */
|
||||
break;
|
||||
case 1: /* CMC */
|
||||
hen = (acpi_hest_hen_t *) (pos);
|
||||
hen = (acpi_hest_hen_t *)(pos);
|
||||
memset(pos, 0, sizeof(acpi_hest_hen_t));
|
||||
hen->type = 3; /* SCI? */
|
||||
hen->length = sizeof(acpi_hest_hen_t);
|
||||
@@ -1483,7 +1614,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
|
||||
|
||||
if (!header)
|
||||
return;
|
||||
@@ -1497,11 +1628,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
header->asl_compiler_revision = asl_revision;
|
||||
|
||||
fadt->FADT_MinorVersion = get_acpi_fadt_minor_version();
|
||||
fadt->firmware_ctrl = (unsigned long) facs;
|
||||
fadt->firmware_ctrl = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
|
||||
fadt->dsdt = (unsigned long) dsdt;
|
||||
fadt->dsdt = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
@@ -1521,7 +1652,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
mainboard_fill_fadt(fadt);
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
acpi_checksum((void *)fadt, header->length);
|
||||
}
|
||||
|
||||
void acpi_create_lpit(acpi_lpit_t *lpit)
|
||||
@@ -1642,7 +1773,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
ssdt->asl_compiler_revision = asl_revision;
|
||||
ssdt->length = sizeof(acpi_header_t);
|
||||
|
||||
acpigen_set_current((char *) current);
|
||||
acpigen_set_current((char *)current);
|
||||
|
||||
/* Write object to declare coreboot tables */
|
||||
acpi_ssdt_write_cbtable();
|
||||
@@ -1691,19 +1822,19 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
|
||||
|
||||
/* We need at least an RSDP and an RSDT Table */
|
||||
rsdp = (acpi_rsdp_t *) current;
|
||||
rsdp = (acpi_rsdp_t *)current;
|
||||
coreboot_rsdp = (uintptr_t)rsdp;
|
||||
current += sizeof(acpi_rsdp_t);
|
||||
current = acpi_align_current(current);
|
||||
rsdt = (acpi_rsdt_t *) current;
|
||||
rsdt = (acpi_rsdt_t *)current;
|
||||
current += sizeof(acpi_rsdt_t);
|
||||
current = acpi_align_current(current);
|
||||
xsdt = (acpi_xsdt_t *) current;
|
||||
xsdt = (acpi_xsdt_t *)current;
|
||||
current += sizeof(acpi_xsdt_t);
|
||||
current = acpi_align_current(current);
|
||||
|
||||
/* clear all table memory */
|
||||
memset((void *) start, 0, current - start);
|
||||
memset((void *)start, 0, current - start);
|
||||
|
||||
acpi_write_rsdp(rsdp, rsdt, xsdt, oem_id);
|
||||
acpi_write_rsdt(rsdt, oem_id, oem_table_id);
|
||||
@@ -1711,18 +1842,18 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * FACS\n");
|
||||
current = ALIGN_UP(current, 64);
|
||||
facs = (acpi_facs_t *) current;
|
||||
facs = (acpi_facs_t *)current;
|
||||
current += sizeof(acpi_facs_t);
|
||||
current = acpi_align_current(current);
|
||||
acpi_create_facs(facs);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
|
||||
dsdt = (acpi_header_t *) current;
|
||||
dsdt = (acpi_header_t *)current;
|
||||
memcpy(dsdt, dsdt_file, sizeof(acpi_header_t));
|
||||
if (dsdt->length >= sizeof(acpi_header_t)) {
|
||||
current += sizeof(acpi_header_t);
|
||||
|
||||
acpigen_set_current((char *) current);
|
||||
acpigen_set_current((char *)current);
|
||||
|
||||
if (CONFIG(ACPI_SOC_NVS))
|
||||
acpi_fill_gnvs();
|
||||
@@ -1732,7 +1863,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
for (dev = all_devices; dev; dev = dev->next)
|
||||
if (dev->ops && dev->ops->acpi_inject_dsdt)
|
||||
dev->ops->acpi_inject_dsdt(dev);
|
||||
current = (unsigned long) acpigen_get_current();
|
||||
current = (unsigned long)acpigen_get_current();
|
||||
memcpy((char *)current,
|
||||
(char *)dsdt_file + sizeof(acpi_header_t),
|
||||
dsdt->length - sizeof(acpi_header_t));
|
||||
@@ -1747,7 +1878,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
current = acpi_align_current(current);
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * FADT\n");
|
||||
fadt = (acpi_fadt_t *) current;
|
||||
fadt = (acpi_fadt_t *)current;
|
||||
current += sizeof(acpi_fadt_t);
|
||||
current = acpi_align_current(current);
|
||||
|
||||
@@ -1773,7 +1904,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * MCFG\n");
|
||||
mcfg = (acpi_mcfg_t *) current;
|
||||
mcfg = (acpi_mcfg_t *)current;
|
||||
acpi_create_mcfg(mcfg);
|
||||
if (mcfg->header.length > sizeof(acpi_mcfg_t)) {
|
||||
current += mcfg->header.length;
|
||||
@@ -1783,7 +1914,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
|
||||
if (CONFIG(TPM1)) {
|
||||
printk(BIOS_DEBUG, "ACPI: * TCPA\n");
|
||||
tcpa = (acpi_tcpa_t *) current;
|
||||
tcpa = (acpi_tcpa_t *)current;
|
||||
acpi_create_tcpa(tcpa);
|
||||
if (tcpa->header.length >= sizeof(acpi_tcpa_t)) {
|
||||
current += tcpa->header.length;
|
||||
@@ -1794,7 +1925,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
|
||||
if (CONFIG(TPM2)) {
|
||||
printk(BIOS_DEBUG, "ACPI: * TPM2\n");
|
||||
tpm2 = (acpi_tpm2_t *) current;
|
||||
tpm2 = (acpi_tpm2_t *)current;
|
||||
acpi_create_tpm2(tpm2);
|
||||
if (tpm2->header.length >= sizeof(acpi_tpm2_t)) {
|
||||
current += tpm2->header.length;
|
||||
@@ -1817,7 +1948,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
|
||||
printk(BIOS_DEBUG, "ACPI: * MADT\n");
|
||||
|
||||
madt = (acpi_madt_t *) current;
|
||||
madt = (acpi_madt_t *)current;
|
||||
acpi_create_madt(madt);
|
||||
if (madt->header.length > sizeof(acpi_madt_t)) {
|
||||
current += madt->header.length;
|
||||
@@ -1829,7 +1960,7 @@ unsigned long write_acpi_tables(unsigned long start)
|
||||
if (CONFIG(ACPI_BERT)) {
|
||||
void *region;
|
||||
size_t size;
|
||||
bert = (acpi_bert_t *) current;
|
||||
bert = (acpi_bert_t *)current;
|
||||
if (acpi_soc_get_bert_region(®ion, &size) == CB_SUCCESS) {
|
||||
printk(BIOS_DEBUG, "ACPI: * BERT\n");
|
||||
acpi_write_bert(bert, (uintptr_t)region, size);
|
||||
@@ -1962,8 +2093,8 @@ int get_acpi_table_revision(enum acpi_tables table)
|
||||
return 4;
|
||||
case SSDT: /* ACPI 3.0 up to 6.3: 2 */
|
||||
return 2;
|
||||
case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.3: 3 */
|
||||
return 1; /* TODO Should probably be upgraded to 2 */
|
||||
case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 up to 6.4: 3 */
|
||||
return 3;
|
||||
case HMAT: /* ACPI 6.4: 2 */
|
||||
return 2;
|
||||
case DMAR:
|
||||
@@ -1996,6 +2127,8 @@ int get_acpi_table_revision(enum acpi_tables table)
|
||||
return 5;
|
||||
case BERT:
|
||||
return 1;
|
||||
case CEDT: /* CXL 3.0 section 9.17.1 */
|
||||
return 1;
|
||||
case CRAT:
|
||||
return 1;
|
||||
case LPIT: /* ACPI 5.1 up to 6.3: 0 */
|
||||
|
@@ -256,7 +256,7 @@ static void acpigen_emit_multi_namestring(const char *name)
|
||||
unsigned char *pathlen;
|
||||
acpigen_emit_byte(MULTI_NAME_PREFIX);
|
||||
acpigen_emit_byte(ZERO_OP);
|
||||
pathlen = ((unsigned char *) acpigen_get_current()) - 1;
|
||||
pathlen = ((unsigned char *)acpigen_get_current()) - 1;
|
||||
|
||||
while (name[0] != '\0') {
|
||||
acpigen_emit_simple_namestring(name);
|
||||
@@ -399,7 +399,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
|
||||
acpigen_write_len_f();
|
||||
|
||||
snprintf(pscope, sizeof(pscope),
|
||||
CONFIG_ACPI_CPU_STRING, (unsigned int) cpuindex);
|
||||
CONFIG_ACPI_CPU_STRING, (unsigned int)cpuindex);
|
||||
acpigen_emit_namestring(pscope);
|
||||
acpigen_emit_byte(cpuindex);
|
||||
acpigen_emit_dword(pblock_addr);
|
||||
@@ -532,7 +532,7 @@ static void acpigen_write_field_offset(uint32_t offset, uint32_t current_bit_pos
|
||||
acpigen_write_field_length(diff_bits);
|
||||
}
|
||||
|
||||
static void acpigen_write_field_name(const char *name, uint32_t size)
|
||||
void acpigen_write_field_name(const char *name, uint32_t size)
|
||||
{
|
||||
acpigen_emit_simple_namestring(name);
|
||||
acpigen_write_field_length(size);
|
||||
|
@@ -62,8 +62,6 @@ static const char *namestring_of(enum dptf_participant participant)
|
||||
return "TCHG";
|
||||
case DPTF_FAN:
|
||||
return "TFN1";
|
||||
case DPTF_FAN_2:
|
||||
return "TFN2";
|
||||
case DPTF_TEMP_SENSOR_0:
|
||||
return "TSR0";
|
||||
case DPTF_TEMP_SENSOR_1:
|
||||
@@ -125,7 +123,7 @@ void dptf_write_scope(enum dptf_participant participant)
|
||||
* are used to increase the speed of the fan in order to speed up cooling.
|
||||
*/
|
||||
static void write_active_relationship_table(const struct dptf_active_policy *policies,
|
||||
int max_count, bool dptf_multifan_support)
|
||||
int max_count)
|
||||
{
|
||||
char *pkg_count;
|
||||
int i, j;
|
||||
@@ -156,11 +154,7 @@ static void write_active_relationship_table(const struct dptf_active_policy *pol
|
||||
|
||||
/* Source, Target, Percent, Fan % for each of _AC0 ... _AC9 */
|
||||
acpigen_write_package(13);
|
||||
if (dptf_multifan_support)
|
||||
acpigen_emit_namestring(path_of(policies[i].source));
|
||||
else
|
||||
acpigen_emit_namestring(path_of(DPTF_FAN));
|
||||
|
||||
acpigen_emit_namestring(path_of(DPTF_FAN));
|
||||
acpigen_emit_namestring(path_of(policies[i].target));
|
||||
acpigen_write_integer(DEFAULT_IF_0(policies[i].weight, DEFAULT_WEIGHT));
|
||||
|
||||
@@ -211,10 +205,9 @@ static void write_active_cooling_methods(const struct dptf_active_policy *polici
|
||||
}
|
||||
}
|
||||
|
||||
void dptf_write_active_policies(const struct dptf_active_policy *policies,
|
||||
int max_count, bool dptf_multifan_support)
|
||||
void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count)
|
||||
{
|
||||
write_active_relationship_table(policies, max_count, dptf_multifan_support);
|
||||
write_active_relationship_table(policies, max_count);
|
||||
write_active_cooling_methods(policies, max_count);
|
||||
}
|
||||
|
||||
@@ -359,29 +352,7 @@ void dptf_write_charger_perf(const struct dptf_charger_perf *states, int max_cou
|
||||
acpigen_pop_len(); /* Scope */
|
||||
}
|
||||
|
||||
int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed,
|
||||
uint16_t noise_level)
|
||||
{
|
||||
/*
|
||||
* Some _FPS tables do include a last entry where Percent is 0, but Power is
|
||||
* called out, so this table is finished when both are zero.
|
||||
*/
|
||||
if (!percent && !power)
|
||||
return 1;
|
||||
|
||||
acpigen_write_package(5);
|
||||
acpigen_write_integer(percent);
|
||||
acpigen_write_integer(DEFAULT_TRIP_POINT);
|
||||
acpigen_write_integer(speed);
|
||||
acpigen_write_integer(noise_level);
|
||||
acpigen_write_integer(power);
|
||||
acpigen_pop_len(); /* inner Package */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
|
||||
enum dptf_participant participant)
|
||||
void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count)
|
||||
{
|
||||
char *pkg_count;
|
||||
int i;
|
||||
@@ -389,48 +360,29 @@ void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
|
||||
if (!max_count || !states[0].percent)
|
||||
return;
|
||||
|
||||
dptf_write_scope(participant);
|
||||
dptf_write_scope(DPTF_FAN);
|
||||
|
||||
/* _FPS - Fan Performance States */
|
||||
acpigen_write_name("_FPS");
|
||||
|
||||
pkg_count = acpigen_write_package(1); /* 1 for Revision */
|
||||
acpigen_write_integer(FPS_REVISION); /* revision */
|
||||
|
||||
for (i = 0; i < max_count; ++i) {
|
||||
(*pkg_count)++;
|
||||
if (dptf_write_fan_perf_fps(states[i].percent, states[i].power,
|
||||
states[i].speed, states[i].noise_level))
|
||||
/*
|
||||
* Some _FPS tables do include a last entry where Percent is 0, but Power is
|
||||
* called out, so this table is finished when both are zero.
|
||||
*/
|
||||
if (!states[i].percent && !states[i].power)
|
||||
break;
|
||||
}
|
||||
|
||||
acpigen_pop_len(); /* Package */
|
||||
acpigen_pop_len(); /* Scope */
|
||||
}
|
||||
|
||||
void dptf_write_multifan_perf(
|
||||
const struct dptf_multifan_perf (*states)[DPTF_MAX_FAN_PERF_STATES],
|
||||
int max_count, enum dptf_participant participant, int fan_num)
|
||||
{
|
||||
char *pkg_count;
|
||||
int i;
|
||||
|
||||
if (!max_count || !states[fan_num][0].percent)
|
||||
return;
|
||||
|
||||
dptf_write_scope(participant);
|
||||
|
||||
/* _FPS - Fan Performance States */
|
||||
acpigen_write_name("_FPS");
|
||||
|
||||
pkg_count = acpigen_write_package(1); /* 1 for Revision */
|
||||
acpigen_write_integer(FPS_REVISION); /* revision */
|
||||
|
||||
for (i = 0; i < max_count; ++i) {
|
||||
(*pkg_count)++;
|
||||
if (dptf_write_fan_perf_fps(states[fan_num][i].percent, states[fan_num][i].power,
|
||||
states[fan_num][i].speed, states[fan_num][i].noise_level))
|
||||
break;
|
||||
acpigen_write_package(5);
|
||||
acpigen_write_integer(states[i].percent);
|
||||
acpigen_write_integer(DEFAULT_TRIP_POINT);
|
||||
acpigen_write_integer(states[i].speed);
|
||||
acpigen_write_integer(states[i].noise_level);
|
||||
acpigen_write_integer(states[i].power);
|
||||
acpigen_pop_len(); /* inner Package */
|
||||
}
|
||||
|
||||
acpigen_pop_len(); /* Package */
|
||||
|
@@ -47,3 +47,26 @@ void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config)
|
||||
}
|
||||
|
||||
/* ------------------- End: I2C HID DSM ------------------------- */
|
||||
|
||||
#define USB_DSM_UUID "CE2EE385-00E6-48CB-9F05-2EDB927C4899"
|
||||
|
||||
static void usb_dsm_func5_cb(void *arg)
|
||||
{
|
||||
struct dsm_usb_config *config = arg;
|
||||
acpigen_write_return_byte(config->usb_lpm_incapable);
|
||||
}
|
||||
|
||||
static void (*usb_dsm_callbacks[6])(void *) = {
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
usb_dsm_func5_cb,
|
||||
};
|
||||
|
||||
void acpigen_write_dsm_usb(struct dsm_usb_config *config)
|
||||
{
|
||||
acpigen_write_dsm(USB_DSM_UUID, usb_dsm_callbacks,
|
||||
ARRAY_SIZE(usb_dsm_callbacks), config);
|
||||
}
|
||||
|
@@ -19,6 +19,27 @@
|
||||
#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301"
|
||||
#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b"
|
||||
|
||||
/*
|
||||
* Below properties are defined at
|
||||
* https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
|
||||
*/
|
||||
#define ACPI_DSD_EXTERNAL_FACING_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389"
|
||||
#define ACPI_DSD_EXTERNAL_FACING_PORT_NAME "ExternalFacingPort"
|
||||
|
||||
#define ACPI_DSD_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"
|
||||
#define ACPI_DSD_HOTPLUG_IN_D3_NAME "HotPlugSupportInD3"
|
||||
|
||||
/* ID for the DmaProperty _DSD */
|
||||
#define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865"
|
||||
#define ACPI_DSD_DMA_PROPERTY_NAME "DmaProperty"
|
||||
|
||||
/*
|
||||
* Below properties are defined at
|
||||
* https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro
|
||||
*/
|
||||
#define ACPI_DSD_STORAGE_D3_UUID "5025030F-842F-4AB4-A561-99A5189762D0"
|
||||
#define ACPI_DSD_STORAGE_D3_NAME "StorageD3Enable"
|
||||
|
||||
/* Write empty word value and return pointer to it */
|
||||
static void *acpi_device_write_zero_len(void)
|
||||
{
|
||||
@@ -1183,3 +1204,64 @@ void acpi_device_write_pci_dev(const struct device *dev)
|
||||
acpigen_pop_len(); /* Device */
|
||||
acpigen_pop_len(); /* Scope */
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper function to add given integer property with an UUID to _DSD in the current scope.
|
||||
*
|
||||
* dsd - Pointer to a _DSD object.
|
||||
* Append to existing _DSD object if not NULL.
|
||||
* Create new _DSD object and flush it if NULL.
|
||||
* uuid - Pointer to the UUID string.
|
||||
* name - Pointer to the property name string.
|
||||
* value - Value of the integer property.
|
||||
*/
|
||||
static void acpi_device_add_integer_property_with_uuid(struct acpi_dp *dsd,
|
||||
const char *uuid,
|
||||
const char *name,
|
||||
uint64_t value)
|
||||
{
|
||||
struct acpi_dp *prev_dsd = dsd, *pkg;
|
||||
if (prev_dsd == NULL)
|
||||
dsd = acpi_dp_new_table("_DSD");
|
||||
pkg = acpi_dp_new_table(uuid);
|
||||
acpi_dp_add_integer(pkg, name, value);
|
||||
acpi_dp_add_package(dsd, pkg);
|
||||
if (prev_dsd == NULL)
|
||||
acpi_dp_write(dsd);
|
||||
}
|
||||
|
||||
/* _DSD with ExternalFacingPort */
|
||||
void acpi_device_add_external_facing_port(struct acpi_dp *dsd)
|
||||
{
|
||||
acpi_device_add_integer_property_with_uuid(dsd,
|
||||
ACPI_DSD_EXTERNAL_FACING_PORT_UUID,
|
||||
ACPI_DSD_EXTERNAL_FACING_PORT_NAME,
|
||||
1);
|
||||
}
|
||||
|
||||
/* _DSD with HotPlugSupportInD3 */
|
||||
void acpi_device_add_hotplug_support_in_d3(struct acpi_dp *dsd)
|
||||
{
|
||||
acpi_device_add_integer_property_with_uuid(dsd,
|
||||
ACPI_DSD_HOTPLUG_IN_D3_UUID,
|
||||
ACPI_DSD_HOTPLUG_IN_D3_NAME,
|
||||
1);
|
||||
}
|
||||
|
||||
/* _DSD with DmaProperty */
|
||||
void acpi_device_add_dma_property(struct acpi_dp *dsd)
|
||||
{
|
||||
acpi_device_add_integer_property_with_uuid(dsd,
|
||||
ACPI_DSD_DMA_PROPERTY_UUID,
|
||||
ACPI_DSD_DMA_PROPERTY_NAME,
|
||||
1);
|
||||
}
|
||||
|
||||
/* _DSD with StorageD3Enable */
|
||||
void acpi_device_add_storage_d3_enable(struct acpi_dp *dsd)
|
||||
{
|
||||
acpi_device_add_integer_property_with_uuid(dsd,
|
||||
ACPI_DSD_STORAGE_D3_UUID,
|
||||
ACPI_DSD_STORAGE_D3_NAME,
|
||||
1);
|
||||
}
|
||||
|
@@ -10,11 +10,11 @@
|
||||
/* Operating system enumeration. */
|
||||
Name (OSYS, 0)
|
||||
|
||||
/* Zero => PIC mode, One => APIC Mode */
|
||||
Name (PICM, Zero)
|
||||
/* 0 => PIC mode, 1 => APIC Mode */
|
||||
Name (PICM, 0)
|
||||
|
||||
/* Power state (AC = 1) */
|
||||
Name (PWRS, One)
|
||||
Name (PWRS, 1)
|
||||
|
||||
/*
|
||||
* The _PIC method is called by the OS to choose between interrupt
|
||||
|
@@ -5,7 +5,17 @@ armv7-a_flags = -march=armv7-a $(armv7_flags) -D__COREBOOT_ARM_V7_A__
|
||||
armv7-m_flags = -march=armv7-m $(armv7_flags) -D__COREBOOT_ARM_V7_M__
|
||||
armv7-r_flags = -march=armv7-r $(armv7_flags) -D__COREBOOT_ARM_V7_R__
|
||||
|
||||
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
|
||||
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always
|
||||
ifeq ($(CONFIG_COMPILER_GCC),y)
|
||||
armv7_asm_flags += -Wa,-mno-warn-deprecated
|
||||
else # CLANG
|
||||
armv7_flags += -mfpu=none
|
||||
bootblock-ld-ccopts += -target arm-eabi
|
||||
verstage-ld-ccopts += -target arm-eabi
|
||||
romstage-ld-ccopts += -target arm-eabi
|
||||
ramstage-ld-ccopts += -target arm-eabi
|
||||
rmodule_arm-ld-ccopts += -target arm-eabi
|
||||
endif
|
||||
armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags)
|
||||
|
||||
###############################################################################
|
||||
|
@@ -23,14 +23,37 @@ void __aeabi_unwind_cpp_pr1(void)
|
||||
{
|
||||
}
|
||||
|
||||
/* Support the alias for the __aeabi_memcpy which may
|
||||
assume memory alignment. */
|
||||
void __aeabi_memcpy4(void *dest, const void *src, size_t n)
|
||||
__attribute((alias("__aeabi_memcpy")));
|
||||
|
||||
void __aeabi_memcpy8(void *dest, const void *src, size_t n)
|
||||
__attribute((alias("__aeabi_memcpy")));
|
||||
|
||||
void __aeabi_memcpy(void *dest, const void *src, size_t n);
|
||||
void __aeabi_memcpy(void *dest, const void *src, size_t n)
|
||||
{
|
||||
(void) memcpy(dest, src, n);
|
||||
(void)memcpy(dest, src, n);
|
||||
}
|
||||
|
||||
void __aeabi_memset(void *dest, size_t n, int c);
|
||||
void __aeabi_memset(void *dest, size_t n, int c)
|
||||
{
|
||||
(void) memset(dest, c, n);
|
||||
(void)memset(dest, c, n);
|
||||
}
|
||||
|
||||
/* Support the alias for the __aeabi_memclr which may
|
||||
assume memory alignment. */
|
||||
void __aeabi_memclr4(void *dest, size_t n)
|
||||
__attribute((alias("__aeabi_memclr")));
|
||||
|
||||
void __aeabi_memclr8(void *dest, size_t n)
|
||||
__attribute((alias("__aeabi_memclr")));
|
||||
|
||||
/* Support the routine __aeabi_memclr. */
|
||||
void __aeabi_memclr(void *dest, size_t n);
|
||||
void __aeabi_memclr(void *dest, size_t n)
|
||||
{
|
||||
__aeabi_memset(dest, n, 0);
|
||||
}
|
||||
|
@@ -8,6 +8,8 @@
|
||||
|
||||
#include <arch/asm.h>
|
||||
|
||||
.syntax unified
|
||||
|
||||
.macro ARM_DIV_BODY dividend, divisor, result, curbit
|
||||
|
||||
#if __COREBOOT_ARM_ARCH__ >= 5
|
||||
@@ -67,7 +69,7 @@
|
||||
subhs \dividend, \dividend, \divisor, lsr #3
|
||||
orrhs \result, \result, \curbit, lsr #3
|
||||
cmp \dividend, #0 @ Early termination?
|
||||
movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
|
||||
movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
|
||||
movne \divisor, \divisor, lsr #4
|
||||
bne 1b
|
||||
|
||||
@@ -153,7 +155,7 @@
|
||||
subhs \dividend, \dividend, \divisor, lsr #3
|
||||
cmp \dividend, #1
|
||||
mov \divisor, \divisor, lsr #4
|
||||
subges \order, \order, #4
|
||||
subsge \order, \order, #4
|
||||
bge 1b
|
||||
|
||||
tst \order, #3
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user