src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files

This change updates Intel Copyright License for all header files
under Sapphirerapids dir

Cherry-picked from commit 7e2106627d.

Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Original-Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Original-Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75469
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/Makefile

@@ -4,12 +4,11 @@
 # hacked together by Stefan Reinauer <stepan@openbios.org>
 #
 
-PDFLATEX  = pdflatex -t a4
+PDFLATEX=pdflatex -t a4
-BUILDDIR ?= _build
 
 FIGS=codeflow.pdf hypertransport.pdf
 
-all: sphinx corebootPortingGuide.pdf
+all: corebootPortingGuide.pdf
 
 SVG2PDF=$(shell command -v svg2pdf)
 INKSCAPE=$(shell command -v inkscape)
@@ -33,9 +32,6 @@ else ifneq ($(strip $(CONVERT)),)
 	convert $< $@
 endif
 
-$(BUILDDIR):
-	mkdir -p $(BUILDDIR)
-
 corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 	# 2 times to make sure we have a current toc.
 	$(PDFLATEX) corebootBuildingGuide.tex
@@ -44,11 +40,11 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
 	$(PDFLATEX) corebootBuildingGuide.tex
 
-sphinx: $(BUILDDIR)
+sphinx:
-	$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx html
 
 clean-sphinx:
-	$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx clean
 
 clean: clean-sphinx
 	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -56,25 +52,5 @@ clean: clean-sphinx
 distclean: clean
 	rm -f corebootPortingGuide.pdf
 
-livesphinx: $(BUILDDIR)
+livesphinx:
-	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"
-
-test:
-	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
-
-help:
-	@echo "all            - Builds coreboot porting guide PDF (outdated)"
-	@echo "sphinx         - Builds html documentation in _build directory"
-	@echo "clean          - Cleans intermediate files"
-	@echo "clean-sphinx   - Removes sphinx output files"
-	@echo "distclean      - Removes PDF files as well"
-	@echo "test           - Runs documentation tests"
-	@echo
-	@echo "  Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
-	@echo
-	@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
-
-.phony: help livesphinx sphinx test
-.phony: distclean clean clean-sphinx

Documentation/acpi/index.md

@@ -11,9 +11,6 @@ upwards.
 
 - [GPIO toggling in ACPI AML](gpio.md)
 
-## Windows-specific ACPI documentation
-
-- [Windows-specific documentation](windows.md)
 
 ##  ACPI specification - Useful links
 

Documentation/acpi/windows.md

@@ -1,9 +0,0 @@
-# Testing ACPI changes under Windows
-
-When testing ACPI changes in coreboot against Windows 8 or newer, beware that
-during a normal boot after a clean shutdown, Windows will use the fast startup
-mechanism which results in it not evaluating the changed ACPI code but instead
-using some cached version which won't include the changes that were supposed to
-be tested. In order for Windows to actually use the new ACPI tables, either
-disable the fast startup or just tell Windows to do a reboot which will make it
-read and use the ACPI tables in memory instead of an outdated cached version.

Documentation/acronyms.md

@@ -1,5 +1,7 @@
 # Firmware and Computer Acronyms, Initialisms and Definitions
 
+** Note that this document even more of a work in progress than most **
+** of the coreboot documentation **
 
 ## _0-9
 
@@ -18,25 +20,24 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   initialization that happens from the PSP.  Significantly, Memory
   Initialization.
 * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
-* Ack - Acknowledgment / Acknowledged
+* Ack - Acknowledgment
 * ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
 * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)
 * ACPI - The [**Advanced Configuration and Power
   Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
   is an industry standard for letting the OS control power management.
-  * [https://uefi.org/specifications](https://uefi.org/specifications)
+  * [http://www.acpi.info/](http://www.acpi.info/)
   * [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
 * ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
 * ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
 * AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)
-* AESKL - Intel: AES Key Locker
 * AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
 * AGP - The [**Accelerated Graphics
-  Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
+  Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
   older (1997-2004) point-to-point bus for video cards to communicate
   with the processor.
 * AHCI - The [**Advanced Host Controller
-  Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
+  Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
   is a standard register set for communicating with a SATA controller.
   * [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
   * [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
@@ -50,11 +51,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   An open standard to connect and manage functional blocks in an SoC
   (System on a Chip)
 * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
-* AMD-Vi AMD: The AMD name for their IOMMU implementation
 * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
   SBI: Sideband Interface
 * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
-* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute)
+* ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
 * AOAC - AMD: Always On, Always Connected
 * AP - Application processor - The main processor on the board (as
   opposed to the embedded controller or other processors that may be on
@@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * APCB - AMD: AMD PSP Customization Block
 * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
 * APIC - [**Advanced Programmable Interrupt
-  Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
+  Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
   this is an advanced version of a PIC that can handle interrupts from
   and for multiple CPUs. Modern systems usually have several APICs:
   Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
@@ -98,7 +98,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## B
 
-* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
+* BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
   base address registers in the PCI config space of a PCI device
 * Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
   after Émile Baudot
@@ -117,7 +117,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   the entire 4GiB of the 32-bit address space. Also known as flat mode
   or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
 * BIOS - [**Basic Input/Output
-  System**](https://en.wikipedia.org/wiki/BIOS)
+  System**](http://en.wikipedia.org/wiki/BIOS)
 * BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
   itself when it is first started. Usually, any nonzero value indicates
   that the selftest failed.
@@ -183,7 +183,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   generally used to describe a section of NVRAM (Non-volatile RAM), in
   this case a section battery-backed memory in the RTC (Real Time Clock)
   that is typically used to store BIOS settings.
-  *[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
+  *[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
 * CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
 * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
 * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
@@ -191,14 +191,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CPPC - AMD: Collaborative Processor Performance Controls
 * CPS - Characters Per Second
 * CPU - [**Central Processing
-  Unit**](https://en.wikipedia.org/wiki/Central_processing_unit)
+  Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
 * CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
 * Cr50 - Google: The first generation Google Security Chip (GSC) used on
   ChromeOS devices.
 * CRB - Customer Reference Board
 * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
   (End-of-Line) marker.
-* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
+* crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
 * crt0s - crt0 Source code
 * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
 * CSE - Intel: Converged Security Engine
@@ -207,7 +207,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CSME - Intel: Converged Security and Management Engine
 * CTLE - Intel: Continuous Time Linear Equalization
 * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
-* CXMT - ChangXin Memory Technologies
 * CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
 
 
@@ -226,9 +225,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   still has power.
 * D3 Cold - ACPI Device power state: Power is completely removed from
   the device.
-* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware)
+* DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
 * DB - DaughterBoard
-* DbC - USB: Debug Capability on the USB host controller
 * DC - Electricity: Direct Current
 * DCP - Digital Content Protection
 * DCR - **Decode Control Register** This is a way of identifying the
@@ -244,7 +242,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
 * DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
 * DMA - [**Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows
+  Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
   certain hardware subsystems within a computer to access system memory
   for reading and/or writing independently of the main CPU. Examples of
   systems that use DMA: Hard Disk Controller, Disk Drive Controller,
@@ -252,7 +250,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   computers, as it allows devices of different speeds to communicate
   without subjecting the CPU to a massive interrupt load.
 * DMI - Direct Media Interface is a link/bus between CPU and PCH.
-* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface)
+* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
 * DMIC - Digital Microphone
 * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
 * DMZ - Demilitarized Zone
@@ -261,7 +259,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DOS - Disk Operating System
 * DP - DisplayPort
 * DPM - Mediatek: DRAM Power Manager
-* DPTC - AMD: Dynamic Power and Thermal Control
 * DPTF - Intel: Dynamic Power and Thermal Framework
 * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
 * DRTM - Dynamic Root of Trust for Measurement
@@ -288,7 +285,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   vs Integrated TPMs or fTPMs (Firmware TPMs).
 * DTS - U-Boot: Device Tree Source
 * DUT - Device Under Test
-* DvC - USB: Debug Capability on the USB Device (Device Capability)
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
@@ -301,13 +297,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## E
 
-* EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd-audio-eapd/)
 * EBDA - Extended BIOS Data Area
 * EBG - Intel: Emmitsburg PCH
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* EDK2 - EFI Development Kit 2
+* edk2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was
@@ -329,7 +324,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EOL - End of Life
 * EPP - Intel: Energy-Performance Preference
 * EPROM - Erasable Programmable Read-Only Memory
-* EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS)
 * ESD - Electrostatic discharge
 * eSPI - Enhanced System Peripheral Interface
 * EVT - Production Timeline: Engineering Validation Test
@@ -340,7 +334,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FADT - ACPI Table: Fixed ACPI Description Table
 * FAE - Field Application Engineer
 * FAT - File Allocation Table
-* FBVDDQ - Nvidia Power: Framebuffer Voltage
 * FCH - AMD: Firmware Control Hub
 * FCS - Production Timeline: First Customer Shipment
 * FDD - Floppy Disk Drive
@@ -358,7 +351,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPDT - ACPI: Firmware Performance Data Table
 * FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
 * Framebuffer - The
-  [**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part
+  [**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
   of RAM in a computer which is allocated to hold the graphics
   information for one frame or picture. This information typically
   consists of color values for every pixel on the screen. A framebuffer
@@ -370,15 +363,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990.
 * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
-* FSM - Finite State Machine
 * FSP - Intel: Firmware Support Package
 * FSR - Intel: Firmware Status Register
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
 * fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
   based in firmware instead of actual hardware.  It typically runs in
   some sort of TEE (Trusted Execution Environment).
-* FWCM Intel: firmware Connection Manager
-* FWID - Firmware Identifier
 
 
 ## G
@@ -399,7 +389,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GMA - Intel: [**Graphics Media
   Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
 * GNB - Graphics NorthBridge
-* GND - Power: Ground
 * GNVS - Global Non-Volatile Storage
 * GPD - PCH GPIO in Deep Sleep well (D5 power)
 * GPE - ACPI: General Purpose Event
@@ -416,28 +405,23 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
 * GSPI - Generic SPI - These are SPI controllers available for general
   use, not dedicated to flash, for example.
-* GTDT - ACPI: Generic Timer Description Table
-* GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
 * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
 
 
 ## H
 
-* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline
 * HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio)
 * HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection)
 * HDD - Hard Disk Drive
 * HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI)
 * HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range)
 * HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI)
-* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline.
 * HID - [**Human Interface
   Device**](https://en.wikipedia.org/wiki/Human_interface_device)
 * HOB - UEFI: Hand-Off Block
 * HPD - Hot-Plug Detect
 * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
 * HSP - AMD: Hardware Security Processor
-* HSPHY - USB: USB3 High-Speed PHY
 * HSTI - Hardware Security Test Interface
 * HSW - Intel: Haswell
 * Hybrid S3 - System Power State:  This is where the operating system
@@ -446,7 +430,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   resume quickly from S3 if the system stays powered, and resume from
   the disk if power is lost.
 * Hypertransport - AMD: The
-  [**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus
+  [**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
   is an older (2001-2017) high-speed electrical interconnection protocol
   specification between CPU, Memory, and (occasionally) peripheral
   devices.  This was originally called the Lightning Data Transport
@@ -467,7 +451,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   - Also known as SenseWire
 * IA - Intel Architecture
 * IA-64 - Intel Itanium 64-bit architecture
-* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions
 * IBB – Initial Boot Block
 * IBV - Independent BIOS Vendor
 * IC - Integrated Circuit
@@ -485,7 +468,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
 * IFD - Intel: Intel Flash Descriptor
-* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions
 * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
   into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
   This never worked well for anything beyond fan control and caused
@@ -497,7 +479,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IoC - Security: Indicator of Compromise
 * IOC - Intel: I/O Cache
 * IOE - Intel: I/O Expander
-* IOHC - AMD: I/O Hub Controller
 * IOM - Intel: I/O Manager
 * IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit)
 * IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
@@ -598,14 +579,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MBR - Master Boot Record
 * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
 * MCR - Machine Check Registers
-* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MCU - Memory Control Unit
 * MCU - [**MicroController
   Unit**](https://en.wikipedia.org/wiki/Microcontroller)
-* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization.
+* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MDFIO - Intel: Multi-Die Fabric IO
 * MDN - AMD: Mendocino
-* mDP - Mini DisplayPort connector
 * ME - Intel: Management Engine
 * MEI - Intel: ME Interface (Previously known as HECI)
 * Memory training - the process of finding the best speeds, voltages,
@@ -622,7 +601,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MKBP - Matrix Keyboard Protocol
 * MMC - [**MultiMedia
   Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
-* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO)
+* MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
   allows peripherals' memory or registers to be accessed directly
   through the memory bus.  When the memory bus size was very small, this
   was initially done by hiding any memory at that address, effectively
@@ -649,17 +628,16 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MSB - Most Significant Bit
 * MSI - Message Signaled Interrupt
 * MSR - Machine-Specific Register
-* MTS or MT/s - MegaTransfers per second
+* MT/s - MegaTransfers per second
 * MTL - Intel: Meteor Lake
 * MTL - ARM: MHU Transport Layer
-* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR)
+* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
   allows to set the cache behaviour on memory access in x86. Basically,
   it tells the CPU how to cache certain ranges of memory
   (e.g. write-through, write-combining, write-back...). Memory ranges
   are specified over physical address ranges. In Linux, they are visible
   over `/proc/mtrr` and they can be modified there. For further
   information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
-* MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module)
 
 
 ## N
@@ -685,7 +663,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * NVME - Non-Volatile Memory Express - An SSD interface that allows
   access to the flash memory through a PCIe bus.
 * NVPCF - Nvidia Platform and Control Framework
-* NVVDD - Nvidia Power: Core voltage
 * NX - No Execute
 
 
@@ -731,17 +708,17 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PCD - UEFI: Platform Configuration Database
 * PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
 * PCI - [**Peripheral Control
-  Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
+  Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
   - Replaced generally by PCIe (PCI Express)
 * PCI Configuration Space - The [**PCI Config
-  space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
+  space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
   [address space](https://en.wikipedia.org/wiki/Address_space) for all
   PCI devices.  Originally, this address space was accessed through an
   index/data pair by writing the address that you wanted to read/write
   into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
   This has been updated to an MMIO method which increases each PCI
   function's configuration space from 256 bytes to 4K.
-* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express)
+* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
 * PCMCIA: Personal Computer Memory Card International Association
 * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
 * PCR: TPM: Platform Configuration Register
@@ -755,9 +732,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PEI - UEFI: Pre-EFI Initialization
 * PEIM - UEFI: PEI Module
 * PEP - Intel: Power Engine Plug-in
-* PEXVDD - Nvidia Power: PCIExpress Voltage
 * PHX - AMD: Phoenix SoC
-* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The
+* PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
   hardware that implements the send/receive functionality of a
   communication protocol.
 * PI - Platform Initialization
@@ -776,7 +752,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PIT - Generally refers to the 8253/8254 [**Programmable Interval
   Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
 * PLCC - [**Plastic leaded chip
-  carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
+  carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
 * PLL - [**Phase-Locked
   Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
 * PM - Platform Management
@@ -807,8 +783,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PSF - Intel: Primary Sideband Fabric
 * PSP - AMD: Platform Security Processor
 * PSPP - AMD: PCIE Speed Power Policy
-* PSR - Intel: Platform Service Record
-* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP
 * PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
 * PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
   resistor. The resistor allows the signal to still be set to ground
@@ -835,7 +809,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be
   used.
 * RAPL - Running Average Power Limit
-* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions
 * RCS - [**Revision control
   system**](https://en.wikipedia.org/wiki/Revision_Control_System)
 * Real mode - The original 20-bit addressing mode of the 8086 & 8088
@@ -843,7 +816,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Segment:Offset index pair.  In 2022, this is still the mode that
   x86-64 processors are in at the reset vector!
 * RDMA - [**Remote Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
+  Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
   a concept whereby two or more computers communicate via DMA directly
   from main memory of one system to the main memory of another.
 * RFC - Request for Comment
@@ -856,7 +829,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ROM - Read Only Memory
 * RoT - Root of Trust
 * RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake)
-* RPP - Intel: Raptor Point PCH
 * RRG - AMD (ATI): Register Reference Guide
 * RSDP - Root System Description Pointer
 * RTC - Real Time Clock
@@ -948,7 +920,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SMBus -  [**System Management
   Bus**](https://en.wikipedia.org/wiki/System_Management_Bus)
   * [http://www.smbus.org/](http://www.smbus.org/)
-* SME - AMD: Secure Memory Encryption
 * SMI - System management interrupt
 * SMM - [**System management
   mode**](https://en.wikipedia.org/wiki/System_Management_Mode)
@@ -962,7 +933,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SO-DIMM: Small Outline Dual In-Line Memory Module
 * SoC - System on a Chip
 * SOIC - [**Small-Outline Integrated
-  Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
+  Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
 * SPD - [**Serial Presence
   Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
 * SPI - [**Serial Peripheral
@@ -987,7 +958,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SSI-TEB - Physical board format: [**SSI Thin Electronics
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
 * SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
-* SSPHY - USB: USB3 Super-Speed PHY
 * STAPM - AMD: Skin Temperature Aware Power Management
 * STB - AMD: Smart Trace Buffer
 * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
@@ -995,16 +965,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   peripherals.  Most common are: A PS/2 Keyboard and mouse port, LPT
   Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any
   of a number of various other devices.
-* SVC - ARM: Supervisor Call
 * SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
-* SWCM - Intel: Software Connection Manager
 
 
 ## T
 
 * TBT - Thunderbolt
 * TBT - Intel: Turbo Boost Technology
-* tBUF - I2C: The bus free time between a STOP and START condition
 * TCC - Intel: Thermal Control Circuit
 * TCP - Transmission Control Protocol
 * TCPC - Type C Port Controller
@@ -1046,7 +1013,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode)
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
-* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives
 * UEFI - Unified Extensible Firmware Interface
 * UFC - User Facing Camera
 * UFP - USB: Upstream Facing Port
@@ -1064,7 +1030,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UPS - Uninterruptible Power Supply
 * USART - Universal Synchronous/Asynchronous Receiver/Transmitter
 * USB - Universal Serial Bus
-* USF - Intel: Universal Scalable Firmware
 
 
 ## V
@@ -1073,7 +1038,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VBNV - Vboot Non-Volatile storage
 * VBT - [**Video BIOS
   Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
-* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip.
 * VESA - Video Electronics Standards Association
 * VGA: Video Graphics Array
 * VID: Vendor Identifier
@@ -1081,17 +1045,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VLB - VESA Local Bus
 * VOIP - Voice over IP
 * Voodoo mode - a silly name for Big Real mode.
-* VMX - Intel: CPU flag for Hardware Virtualization
 * VPD - Vital Product Data
 * VPN - Virtual Private Network
-* VPU - Intel: Versatile Processor Unit
 * VR - Voltage Regulator
 * VRAM - Video Random Access Memory
-* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ.
 * VRM - Voltage Regulator Module
 * VT-d - Intel: Virtualization Technology for Directed I/O
-* VTT Memory/Power: Tracking Termination Voltage
-* vUART - Virtual UART
 
 
 ## W
@@ -1109,7 +1068,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * WLAN - Wireless LAN (Local Area Network)
 * WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
-* WPT - Intel: Wildcat Point - PCH for Broadwell
 * WO - Write-only
 * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
 * WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
@@ -1130,9 +1088,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   supporting 1.x, 2.0, and 3.x devices.
 
 
-## Y
 
-* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video
+## Y
 
 
 ## Z

Documentation/community/code_of_conduct.md

@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
-## Legal action
-
-Threatening or starting legal action against the project, sibling
-projects hosted on coreboot.org infrastructure, project or infrastructure
-maintainers leads to an immediate ban from coreboot.org and related
-systems.
-
-The ban can be reconsidered, but it's the default action because the
-people who pour lots of time and money into the projects aren't interested
-in seeing their resources used against them.
-
 ## Scope
 
 We expect all community participants (contributors, paid or otherwise;

Documentation/community/forums.md

@@ -14,7 +14,7 @@ read its
 ## Real time chat
 
 We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
-also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
+also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
 [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
 [OSF Slack](https://osfw.slack.com/), which has channels on many open source
 firmware related topics. Slack requires that people come from specific domains

Documentation/conf.py

@@ -55,7 +55,7 @@ else:
 #
 # This is also used if you do content translation via gettext catalogs.
 # Usually you set "language" from the command line for these cases.
-language = 'en'
+language = None
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
@@ -87,9 +87,11 @@ html_theme = 'sphinx_rtd_theme'
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
 
-html_css_files = [
+html_context = {
-    'theme_overrides.css',  # override wide tables in RTD theme
+      'css_files': [
-]
+        '_static/theme_overrides.css',  # override wide tables in RTD theme
+      ],
+}
 
 # Output file base name for HTML help builder.
 htmlhelp_basename = 'corebootdoc'

Documentation/getting_started/build_system.md

@@ -62,23 +62,6 @@ supported options are:
 
 `position` and `align` are mutually exclusive.
 
-### Adding Makefile fragments
-
-You can use the `add_intermediate` helper to add new post-processing steps for
-the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.inc`
-
-```
-$(call add_intermediate, add_mrc_data)
-	$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
-```
-
-Note that the second line must start with a tab, not spaces.
-
-```eval_rst
-See also :doc:`../tutorial/managing_local_additions`.
-```
-
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
 need to extend the specification of files to provide more precise control

Documentation/getting_started/devicetree.md

@@ -79,7 +79,7 @@ with no properties as a direct child of the SoC.
 ## Device drivers
 
 Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info.
+See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
 
 ## Notes
 

Documentation/mainboard/asus/p2b-ls.md

@@ -92,7 +92,7 @@ for only CPU models that the board will actually be run with.
 
 ```eval_rst
 +------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
+| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
 +------------------+--------------------------------------------------+
 | Southbridge      | i82371eb                                         |
 +------------------+--------------------------------------------------+

Documentation/mainboard/asus/p3b-f.md

@@ -90,7 +90,7 @@ for only CPU models that the board will actually be run with.
 
 ```eval_rst
 +------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
+| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
 +------------------+--------------------------------------------------+
 | Southbridge      | i82371eb                                         |
 +------------------+--------------------------------------------------+

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -1,65 +0,0 @@
-# HP Compaq Elite 8300 USDT
-
-This page describes how to run coreboot on the [Compaq Elite 8300 USDT] desktop
-from [HP].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+-------------+
-| Type                | Value       |
-+=====================+=============+
-| Socketed flash      | no          |
-+---------------------+-------------+
-| Model               | W25Q128BVFG |
-+---------------------+-------------+
-| Size                | 16 MiB      |
-+---------------------+-------------+
-| In circuit flashing | yes         |
-+---------------------+-------------+
-| Package             | SOIC-16     |
-+---------------------+-------------+
-| Write protection    | No          |
-+---------------------+-------------+
-| Dual BIOS feature   | No          |
-+---------------------+-------------+
-```
-
-### Internal programming
-
-Internal programming is possible. Shorting the Flash Descriptor Override
-(FDO) jumper bypasses all write protections.
-
-### External programming
-
-Remove the lid. The flash chip can be found on the edge opposite to the CPU.
-There is a spot for a "ROM RCVRY" header next to the flash chip but it is
-unpopulated. If you don't feel like using a clip, you can easily solder
-a standard pin header there yourself and use it for programming.
-
-Programming powers some parts of the board. Programming when
-Wake on LAN is active works great.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | NPCD379HAKFX                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-### SuperIO
-
-This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
-fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
-
-[Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
-[HP]: https://www.hp.com/

Documentation/mainboard/hp/elitebook_820_g2.md

@@ -1,141 +0,0 @@
-# HP EliteBook 820 G2
-
-This page is about the notebook [HP EliteBook 820 G2].
-
-## Release status
-
-HP EliteBook 820 G2 was released in 2015 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-
-1. EC firmware
-2. Intel ME firmware
-3. Broadwell mrc.bin and refcode.elf
-
-HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller.
-The EC firmware is stored in the flash chip, but we don't need to touch it
-or use it in the coreboot build process.
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-The Broadwell memory reference code binary and reference code blob is needed
-when building coreboot. Read the document [Blobs used in Intel Broadwell boards]
-on how to get these blobs.
-
-## Programming
-
-Before flashing, remove the battery and the hard drive cover according to the
-[Maintenance and Service Guide] of this laptop.
-
-HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB
-private flash. To install coreboot, we need to program both flash chips.
-Read [HP Sure Start] for detailed information.
-
-![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg)
-
-To access the system flash, we need to connect the AC adapter to the machine,
-then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
-made with an STM32 development board is tested to work.
-
-To access the private flash chip, we can use a ch341a based flash programmer and
-flash the chip with the AC adapter disconnected.
-
-To flash coreboot on a board running OME firmware, create a backup for both flash
-chips, then do the following:
-
-1. Erase the private flash to disable the IFD protection
-2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside
-   the protected flash region
-
-To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
-then run:
-
-    flashrom -p <programmer> --erase
-
-To modify the IFD, write the following flash layout to a file:
-
-    00000000:00000fff fd
-    00001000:00002fff gbe
-    00003000:005fffff me
-    00600000:00bfffff bios
-    00eb5000:00ffffff pd
-
-Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
-is in ``factory-sys.rom``, run:
-
-    ifdtool -n layout.txt factory-sys.rom
-
-Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
-
-Flash the IFD of the system flash:
-
-    flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
-
-Then flash the coreboot image:
-
-    # first extend the 12M coreboot.rom to 16M
-    fallocate -l 16M build/coreboot.rom
-    flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
-
-After coreboot is installed, the coreboot firmware can be updated with internal flashing:
-
-    flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
-
-## Debugging
-
-The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
-
-## Test status
-
-### Untested
-
-- NFC module
-- Fingerprint reader
-- Smart Card reader
-
-### Working
-
-- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory
-- SATA and M.2 SATA disk
-- PCIe SSD
-- Webcam
-- Touch screen
-- Audio output from speaker and headphone jack
-- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards])
-- WLAN
-- WWAN
-- SD card reader
-- Internal LCD, DisplayPort and VGA video outputs
-- Dock
-- USB
-- Keyboard and touchpad
-- EC ACPI
-- S3 resume
-- TPM
-- Arch Linux with Linux 5.11.16
-- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1
-- Graphics initialization with libgfxinit
-- Payload: SeaBIOS 1.16.2
-- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05
-- Internal flashing under coreboot
-
-## Technology
-
-```eval_rst
-+------------------+-----------------------------+
-| SoC              | Intel Broadwell             |
-+------------------+-----------------------------+
-| EC               | SMSC MEC1324                |
-+------------------+-----------------------------+
-| Coprocessor      | Intel Management Engine     |
-+------------------+-----------------------------+
-```
-
-[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
-[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf
-[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
-[HP Sure Start]: hp_sure_start.md

Documentation/mainboard/index.md

@@ -75,7 +75,6 @@ The boards in this section are not real mainboards, but emulators.
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
-- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
 - [Z220 Workstation SFF](hp/z220_sff.md)
 
 ### EliteBook series
@@ -86,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)
-- [EliteBook 820 G2](hp/elitebook_820_g2.md)
 
 ## Intel
 
@@ -125,7 +123,8 @@ The boards in this section are not real mainboards, but emulators.
 ### Ivy Bridge series
 
 - [T430](lenovo/t430.md)
-- [T530 / W530](lenovo/w530.md)
+- [T530](lenovo/w530.md)
+- [W530](lenovo/w530.md)
 - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
 - [T431s](lenovo/t431s.md)
 - [X230s](lenovo/x230s.md)
@@ -206,33 +205,24 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Adder Workstation 1](system76/addw1.md)
 - [Adder Workstation 2](system76/addw2.md)
-- [Adder Workstation 3](system76/addw3.md)
 - [Bonobo Workstation 14](system76/bonw14.md)
-- [Bonobo Workstation 15](system76/bonw15.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
 - [Darter Pro 8](system76/darp8.md)
-- [Darter Pro 9](system76/darp9.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Galago Pro 6](system76/galp6.md)
-- [Galago Pro 7](system76/galp7.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
-- [Gazelle 17](system76/gaze17.md)
-- [Gazelle 18](system76/gaze18.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Lemur Pro 11](system76/lemp11.md)
-- [Lemur Pro 12](system76/lemp12.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
 - [Oryx Pro 9](system76/oryp9.md)
 - [Oryx Pro 10](system76/oryp10.md)
-- [Oryx Pro 11](system76/oryp11.md)
-- [Serval Workstation 13](system76/serw13.md)
 
 ## Texas Instruments
 

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
 
 ## Flashing coreboot
 
@@ -63,6 +63,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -38,7 +38,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
 
 ## Flashing coreboot
 
@@ -60,6 +60,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_adl.md

@@ -5,8 +5,6 @@
 - CPU (full processor specs available at https://ark.intel.com)
     - Intel i7-1260P (Alder Lake)
     - Intel i3-1220P (Alder Lake)
-    - Intel i3-1315U (Raptor Lake)
-    - Intel i7-1360P (Raptor Lake)
 - EC
     - ITE IT5570E
     - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
@@ -35,15 +33,14 @@
     - RTS5129 MicroSD card reader
 - USB
     - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left) (Alder Lake)
+    - USB 3.1 Gen 2 (left)
-    - Thunderbolt 4.0 (left) (Raptor Lake)
     - USB 3.1 Gen 2 Type-A (left)
     - USB 3.1 Gen 1 Type-A (right)
     - USB 2.0 Type-A (right)
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
 
 ### Preliminaries
 
@@ -61,21 +58,12 @@ These files exist in the correct location in the StarLabsLtd/blobs repo on GitHu
 
 The following commands will build a working image:
 
-
-Alder Lake:
 ```bash
 make distclean
 make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
 make
 ```
 
-Raptor Lake:
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_rpl
-make
-```
-
 ## Flashing coreboot
 
 ```eval_rst
@@ -96,6 +84,5 @@ make
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
 
 ## Flashing coreboot
 
@@ -62,6 +62,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/system76/addw3.md

@@ -1,71 +0,0 @@
-# System76 Adder Workstation 3 (addw3)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP displays
-    - 15.6" 1920x1080@144Hz LCD
-    - 17.3" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
-- Networking
-  - Intel I219-V gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 280W (20V, 14A) DC-in port
-    - Included: Chicony A18-280P1A
-  - 73Wh 4-cell Lithium-Ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 (PCIe NVMe Gen 4) SSDs
-  - MicroSD card reader
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 1 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 2.71cm x 35.95cm x 23.8cm, 2.05kg
-  - 17": 2.82cm x 39.69cm x 26.2cm, 2.85kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U65) is above the battery connector.

Documentation/mainboard/system76/bonw15.md

@@ -1,65 +0,0 @@
-# System76 Bonobo Workstation 15 (bonw15)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4080
-    - NVIDIA GeForce RTX 4090
-  - eDP 17.3" 3840x2160@144Hz LCD (BOE NE173QUM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 2x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Onboard Intel Killer Ethernet E3100X 2.5 GbE
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 330W (19.5V, 16.42A) AC adapter (Chicony A20-330P1A)
-    - Rectangular connector; not a barrel connector
-  - 99Wh 8-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 3x M.2 PCIe NVMe Gen 4 SSDs
-- USB
-  - 2x USB Type-C with Thunderbolt 4
-  - 2x USB 3.2 Gen 2 Type-A
-- Dimensions
-  - 2.49cm x 39.6cm x 27.8cm, 3.29kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U58) is next to the left M.2 port.

Documentation/mainboard/system76/darp9.md

@@ -1,62 +0,0 @@
-# Syste76 Darter Pro 9 (darp9)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1340P
-  - Intel Core i7-1360P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 15.6" 1920x1080@60Hz LCD
-  - 1x HDMI
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Gigabit Ethernet (Realtek RTL8111H)
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U22) is above the left DIMM slot.

Documentation/mainboard/system76/galp7.md

@@ -1,58 +0,0 @@
-# System76 Galago Pro 7 (galp7)
-
-## Specs
-
-- CPU
-  - Intel Core i5-13500H
-  - Intel Core i7-13700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@144Hz LCD (Sharp LQ140M1JW49)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/mainboard/system76/gaze17.md

@@ -1,65 +0,0 @@
-# System76 Gazelle 17 (gaze17)
-
-The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
-
-## Specs
-
-- CPU
-  - Intel Core i5-12500H
-  - Intel Core i7-12700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 3050
-    - NVIDIA GeForce RTX 3050 Ti
-    - NVIDIA GeForce RTX 3060
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
-- Networking
-  - Gigabit Ethernet
-    - 3050: Realtek RTL8111H controller
-    - 3060: Onboard Intel I219-V
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6 AX201
-- Power
-  - 3050: 150W (20V, 7.5A) AC barrel adapter
-  - 3060: 180W (20V, 9A) AC barrel adapter
-      - Lite-On PA-1181-76, using a C5 power cord
-  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The position of the flash chip depends on the variant:
-
-- 3050: U24, below the bottom DIMM slot.
-- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/mainboard/system76/gaze18.md

@@ -1,72 +0,0 @@
-# System76 Gazelle 18 (gaze18)
-
-## Specs
-
-- CPU
-  - Intel i9-13900H
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - NVIDIA GeForce RTX 3050 (70W TDP)
-  - Intel Irix Xe Graphics
-  - eDP displays
-    - 17.3" 1920x1080@144Hz LCD
-    - 15.6" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Realtek RTL8111H gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 150W AC barrel adapter
-    - Included: LiteOn PA-1151-76, using a C5 power cord
-  - 54Wh 4-cell battery (NP50BAT-4-54)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP audio
-- Storage
-  - 1x M.2 (PCIe NVMe Gen 4)
-  - 1x M.2 (PCIe NVMe Gen 3)
-  - MicroSD card reader
-    - Realtek RTS5227S
-- USB
-  - 2x USB 3.2 Gen 2 Type-C
-    - Does not support USB-C charging (USB-PD) or Thunderbolt
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
-  - 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U24) is right of the M.2 SSD connectors.

Documentation/mainboard/system76/lemp12.md

@@ -1,62 +0,0 @@
-# System76 Lemur Pro 12 (lemp12)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1335U
-  - Intel Core i7-1355U
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.0" 1920x1080@60Hz LCD (Innolux N140HCE-EN2)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Channel 0: 8-GB onboard DDR5 (Samsung M425R1GB4BB0-CQKOD)
-  - Channel 1: 8/16/32-GB DDR5 SO-DIMM @ 4800 MHz
-- Networking
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 65W (19V, 3.42A) AC adapter (AcBel ADA012)
-  - USB-C charging, compatible with 65W+ charger
-  - 73Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5 mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thudnerbolt 4
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 1.65cm x 32.2cm x 21.68cm, 1.15kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp11.md

@@ -1,66 +0,0 @@
-# System76 Oryx Pro 11 (oryp11)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - 16" 1920x1200@165Hz LCD
-  - External outputs:
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86)
-  - 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73)
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 2.1 Gen 1 Type-A
-- Dimensions
-  - 35.95cm x 27.3cm x 1.99cm, 2.7kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the memory slots.

Documentation/mainboard/system76/serw13.md

@@ -1,69 +0,0 @@
-# System76 Serval Workstation 13 (serw13)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP options:
-    - 15.6" 1920x1080@165Hz LCD (BOE NV156FHM-NY8)
-    - 17.6" 3840x2160@144Hz LCD (AUO B173ZAN03.0)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 280W (20V, 14A) AC adapter (Chicony A18-280P1A)
-  - 80Wh 6-cell Lithium-ion battery ()
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 15": 2.49cm x 35.8cm x 24.0cm, 2.4kg
-  - 17": 2.49cm x 39.6cm x 26.2cm, 2.8kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U46) is left of the memory slots.

Documentation/releases/coreboot-4.19-relnotes.md

@@ -15,10 +15,6 @@ It takes constant effort to just stay afloat, let alone improve the
 codebase. Thank you very much to everyone who has contributed, both in
 this release and in previous times.
 
-Note that the first set of tarballs posted for the 4.19 release had
-bad timestamps. This has been fixed. Hashes for all tarballs are at
-the bottom of this document.
-
 The 4.20 release is planned for the 20th of April, 2023.
 
 
@@ -248,20 +244,3 @@ Issues from the coreboot bugtracker: https://ticket.coreboot.org/
 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
 +-----+-----------------------------------------------------------------+
 ```
-
-Hashes for tarballs & signatures
---------------------------------
-
-Old tarballs:
-
-- a1f9ec1252a3cc19f0b4ba1a2b9d66ea9327499cbeecebd85377db7d5c68555d  coreboot-4.19.tar.xz
-- 6ceaa39429a2094d75e4c8a94615ae60664ddad7b4115570b65b9bb516cbd96d  coreboot-4.19.tar.xz.sig
-- 881a3477221d1b77e161759344df14eccda115086af3ef54e66485ae0eb2e5d9  coreboot-blobs-4.19.tar.xz
-- 16f4f1f7acc6203ce915ffea64edce8512bd9eb9e94e65db22a0cb5282a6e157  coreboot-blobs-4.19.tar.xz.sig
-
-New tarballs:
-
-- 65ccb2f46535b996e0066a1b76f81c8cf1ff3e27df84b3f97d8ad7b3e7cf0a43  coreboot-4.19.tar.xz
-- d3c52a209b8ccb49049960318f04f158dd47db52ebe6019d6a3dffe3196d9cbe  coreboot-4.19.tar.xz.sig
-- 30214caed07b25f11e47bec022ff6234841376e36689eb674de2330a3e980cbc  coreboot-blobs-4.19.tar.xz
-- 023d511d074703beab98c237c3e964dc7c598af86d5a0e2091195c68980b6c5d  coreboot-blobs-4.19.tar.xz.sig

Documentation/releases/coreboot-4.20-relnotes.md

@@ -1,16 +1,10 @@
-coreboot 4.20 release
+Upcoming release - coreboot 4.20
 ========================================================================
 
-The 4.20 release was done on May 15, 2023. Unfortunately, a licensing
+The 4.20 release is being done on May 15, 2023.
-issues was found immediately after the release was completed, and it
-was decided to hold the release until that was fixed.
-
-Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
-4.20_branch will contain all code for 4.20, 4.20.1, and any further
-changes required for this release.
 
 The coreboot community has done a tremendous amount of work on the
-codebase over the last three and a half months. We've had over 1600
+codebase over the last three and a half month. We've had over 1600
 commits in that time period, doing ongoing cleanup and improvement.
 
 It can be hard to remember at times how much the codebase really has
@@ -25,23 +19,20 @@ or push even a single patch to fix a bug that they've noticed.
 
 Many thanks to everyone involved!
 
-We plan to get the 4.21 release done in mid August, 2023.
+We plan to get the 4.21 release done in mid August, 2023,
-
 
 Significant or interesting changes
 ----------------------------------
 
-
 ### cpu/mp_init.c: Only enable CPUs once they execute code
 
 On some systems the BSP cannot know how many CPUs are present in the
 system. A typical use case is a multi socket system. Setting the enable
 flag only on CPUs that actually exist makes it more flexible.
 
-
 ### cpu/x86/smm: Add PCI resource store functionality
 
-In certain cases data within protected memory areas like SMRAM could
+In certain cases data within protected memmory areas like SMRAM could
 be leaked or modified if an attacker remaps PCI BARs to point within
 that area. Add support to the existing SMM runtime to allow storing
 PCI resources in SMRAM and then later retrieving them.
@@ -49,12 +40,10 @@ PCI resources in SMRAM and then later retrieving them.
 This helps prevent moving BARs around to get SMM to access memory in
 areas that shouldn't be accessed.
 
-
 ### acpi: Add SRAT x2APIC table support
 
 For platforms using X2APIC mode add SRAT x2APIC table
-generation. This allows the setup of proper SRAT tables.
+generation. This allows to setup proper SRAT tables.
-
 
 ### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
 
@@ -68,11 +57,10 @@ The ACPI and USB driver of linux kernel need corresponding functions
 to support this feature. Please see
 https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
 
-
 ### drivers/efi: Add EFI variable store option support
 
 Add a driver to read and write EFI variables stored in a region device.
-This is particularly useful for EDK2 as payload and allows it to reuse
+This is particularly useful for EDK2 as payload and allows to reuse
 existing EFI tools to set/get options used by the firmware.
 
 The write implementation is fault tolerant and doesn't corrupt the
@@ -101,11 +89,11 @@ variable, first a new is written to the end of the store and then the
 previous is marked invalid. This only works on PNOR flash that allow to
 clear set bits, but keep cleared bits state.
 This mechanisms allows a fault tolerant write, but it also requires to
-"clean" the variable store from time to time. This cleaning would remove
+"clean" the variable store for time to time. This cleaning would remove
 variables that have been marked "deleted".
 Such cleaning mechanism in turn must be fault tolerant and thus must use
 a second partition in the SPI flash as backup/working region.
-For now, cleaning is done in coreboot.
+For now to cleaning is done in coreboot.
 
 Fault checking:
 The driver should check if a previous write was successful and if not
@@ -117,7 +105,6 @@ mark variables as deleted on the next operation.
 Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
 and prints EWL type 3 primarily associated with MRC training failures.
 
-
 ### Toolchain updates
 
 * Upgrade MPC from version 1.2.1 to 1.3.1
@@ -127,7 +114,6 @@ and prints EWL type 3 primarily associated with MRC training failures.
 * Upgrade GCC from version 11.2.0 to 11.3.0
 * Upgrade binutils from version 2.37 to 2.40
 
-
 Additional coreboot changes
 ---------------------------
 
@@ -149,10 +135,8 @@ Additional coreboot changes
 * Do initial work on Xeon SPR
 * CMOS defaults greater than 128 bytes long now extend to bank 1.
 
-
 New Mainboards
 --------------
-
 * Asrock: B75M-ITX
 * Dell: Latitude E6400
 * Google: Aurash
@@ -178,21 +162,16 @@ New Mainboards
 * System76: oryp10
 * System76: oryp9
 
-
 Removed Mainboards
 ------------------
-
 * Intel Icelake U DDR4/LPDDR4 RVP
 * Intel Icelake Y LPDDR4 RVP
 * Scaleway TAGADA
 
-
 Updated SoCs
 ------------
-
 * Removed soc/intel/icelake
 
-
 Plans to move platform support to a branch
 ------------------------------------------
 
@@ -209,57 +188,39 @@ be maintained on the release 4.20 branch.
   * Intel Quark SoC
   * Intel Galileo mainboard
 
-
 Statistics from the 4.19 to the 4.20 release
 --------------------------------------------
 
-Total Commits: 1630
+Total Commits: ~1625
-Average Commits per day: 13.72
+Average Commits per day: ~13.71
-Total lines added: 102592
+Total lines added: ~101911
-Average lines added per commit: 62.94
+Average lines added per commit: ~62.71
-Number of patches adding more than 100 lines: 128
+Number of patches adding more than 100 lines: ~126
-Average lines added per small commit: 37.99
+Average lines added per small commit: ~37.98
-Total lines removed: 34824
+Total lines removed: ~34756
-Average lines removed per commit: 21.36
+Average lines removed per commit: ~21.39
-Total difference between added and removed: 67768
+Total difference between added and removed: ~67155
 Total authors: ~170
 New authors: ~35
 
-
 Significant Known and Open Issues
 ---------------------------------
 
 Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
+
-+-----+-----------------------------------------------------------------+
 | #   | Subject                                                         |
-+=====+=================================================================+
+|-----|-----------------------------------------------------------------|
 | 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
 | 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
 | 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
 | 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
 | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
 | 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
 | 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
 | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
 | 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
 | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
 | 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
 | 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
 | 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```

Documentation/releases/coreboot-4.21-relnotes.md

@@ -1,407 +1,51 @@
 Upcoming release - coreboot 4.21
 ========================================================================
 
-The 4.21 release is scheduled for August 21st, 2023
+The 4.21 release is planned for mid-August, 2023
 
-In the past quarter year, the coreboot project has gotten over 1200 new
+Update this document with changes that should be in the release notes.
-patches from around 140 authors, 20 of whom contributed for the first
-time.
 
-Thank you to all of our donors, the code contributors, the people who
+* Please use Markdown.
-take time to review all of those patches and all of the people who care
+* See the past few release notes for the general format.
-about the coreboot project. There have been a number of new companies
+* The chip and board additions and removals will be updated right
-starting to use coreboot recently, and we appreciate all of the
+  before the release, so those do not need to be added.
-contributions and support.
+* Note that all changes before the release are done are marked upcoming.
-
+  A final version of the notes are done after the release.
-### Upcoming switch from master branch to main branch
-
-Historically, the initial branch that was created in a new git
-repository was named ‘master’. In line with many other projects,
-coreboot has decided to switch away from this name and use the name
-‘main’ instead. You can read about the initial reasoning on the SFC’s
-website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
-
-At some point before the 4.22 release, coreboot will be switching from
-the master branch to the main branch. This shouldn’t be a difficult
-change for most people, as everyone will just have to rebase on top of
-a different branch name.
-
-We’ve already created the main branch, and it is currently synced with
-the master branch. Please update any scripts to point to main instead
-of master.
-
-At the point of the changeover, we will move all patches in gerrit to
-the main branch and disable pushes to the master branch.
-
-After the switch, we will sync the main branch to the master branch for
-a while to give people a little more time to update any scripts that
-are currently pointed at the master branch. Note that this update will
-probably be done just once per day, and the frequency of updates will
-be decreased over time. We plan to stop updating the master branch
-following the 4.22 release.
 
 Significant or interesting changes
 ----------------------------------
 
-### lib: Support localized text of memory_training_desc in ux_locales.c
+### Add changes that need a full description here
-
-Most of the text in coreboot is for logging, and does not use
-localization. There are however, some bits of text that can be
-presented to the user, and this patch supplies a method to localize
-them.
-
-To support the localized text, we need to get the locale id by vboot
-APIs and read raw string content file: preram_locales located at either
-RO or RW.
-
-The preram_locales file follows the format:
-
-    [PRERAM_LOCALES_VERSION_BYTE (\x01)]
-    [string_name_1] [\x00]
-    [locale_id_1] [\x00] [localized_string_1] [\x00]
-    [locale_id_2] [\x00] [localized_string_2] …
-    [\x01]
-    [string_name_2] [\x00] ...
-
-This code will search for the correct localized string that its string
-name is `memory_training_desc` and its locale ID matches the ID vb2api
-returns. If no valid string found, we will try to display in English
-(locale ID 0).
-
-
-### Improved the bootsplash support
-
-The JPEG decoder, that was added many years ago to display a bootsplash
-in coreboot, has a few quirks. People used to do some voodoo with GIMP
-to convert images to the right format, but we can also achieve the same
-with ImageMagick's `convert`. The currently known constraints are:
-
-* The framebuffer's color format is ignored,
-* only YCC 4:2:0 color sampling is supported, and
-* width and height have to be a multiple of 16 pixels.
-
-Beside that, we can only display the bootsplash if it completely fits
-into the framebuffer. As the latter's size is often decided at runtime,
-we can't do much more than offering an option to set a specific size.
-
-The build system has been extended so that the necessary adjustments to
-the picture can be done by it and several options have been added to
-Kconfig.
-
-
-### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
-
-This is a complete rewrite of the UHCI root-hub driver, based on the
-xHCI one. We are doing things by the book as far as possible. One
-special case is uhci_rh_reset_port() which does the reset sequencing
-that usually the hardware would do.
-
-This abandons some quirks of the old driver:
-* Ports are not disabled/re-enabled for every attachment anymore.
-* We solely rely on the Connect Status Change bit to track changes.
-* Further status changes are now deferred to the next polling round.
-
-
-### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
-
-Translate the coreboot framebuffer info from coreboot tables to the
-Linux zero page.
-
-To support full 64-bit addresses, there is a new field `ext_lfb_base`
-since Linux 4.1. It is unclear, however, how a loader is supposed to
-know if the kernel is compatible with this. Filling these previously
-reserved bits doesn't hurt, but an old kernel would probably ignore
-them and not know that it's handling a clipped, invalid address. So we
-play safe, and only allow 64-bit addresses for kernels after the 2.15
-version bump of the boot protocol.
-
-
-### arch/x86: Don't allow hw floating point operations
-
-Even though coreboot does not allow floating point operations, some
-compilers like clang generate code using hw floating point registers,
-e.g. SSE %XMMx registers on 64bit code by default. Floating point
-operations need to be enabled in hardware for this to work (CR4). Also
-in SMM we explicitly need to save and restore floating point registers
-for this reason. If we instruct the compiler to not generate code with
-FPU ops, this simplifies our code as we can skip that step.
-
-With clang this reduces the binary size a bit. For instance ramstage
-for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
-decompressed to 212768 bytes.
-
-Since we now explicitly compile both ramstage and smihandler code
-without floating point operations and associated registers we don't
-need to save/restore floating point registers in SMM.
-
-The EFER MSR is in the SMM save state and RSM properly restores it.
-Returning to 32bit mode was only done so that fxsave was done in the
-same mode as fxrstor, but this is no longer done.
-
-
-### Caching of PCIe 5.0 HSPHY firmware in SPI flash
-
-This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
-flash. A new flashmap region is created for that purpose. The goal of
-caching is to reduce the dependency on the CSME (Converged Security and
-Management Engine) and the HECI (Host Embedded Controller Interface) IP
-LOAD command which may fail when the CSME is disabled, e.g. soft
-disabled by HECI command or HAP (High Assurance Platform mode). By
-caching that firmware, this allows the PCIe 5.0 root ports to keep
-functioning even if CSME/HECI is not functional.
-
-
-### Extracting of TPM logs using cbmem tool
-
-CBMEM can contain logs in different forms (at most one is present):
- * coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
-   LB_TAG_TPM_CB_LOG)
- * TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
- * TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
-
-The last two follow specifications by Trusted Computing Group, but
-until now cbmem couldn't print them.
-
-These changes make the cbmem utility check for existence of TPM1.2/TPM2
-logs in CBMEM and add code necessary for parsing and printing of their
-entries.
-
-`cbmem -L` for CONFIG_TPM1=y case
-
-```
-TCPA log:
-	Specification: 1.21
-	Platform class: PC Client
-TCPA log entry 1:
-	PCR: 2
-	Event type: Action
-	Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
-	Event data: FMAP: FMAP
-```
-
-`cbmem -L` for CONFIG_TPM2=y case
-
-```
-TPM2 log:
-	Specification: 2.00
-	Platform class: PC Client
-TPM2 log entry 1:
-	PCR: 2
-	Event type: Action
-	Digests:
-		 SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
-	Event data: FMAP: FMAP
-```
-
-
-### soc/amd: read domain resource window configuration from hardware
-
-Read the MMIO and IO decode windows for the PCI root complex and the
-PCI bus number range decoded to the PCI root complex from the data
-fabric registers and pass the information to the resource allocator so
-it has the correct constraints to do its job. Also generate the
-corresponding ACPI resource producers in the SSDT so that the OS knows
-about this too. This is required for the upcoming USB 4 support.
 
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
 
 Additional coreboot changes
 ---------------------------
 
-* Added SPDX headers to more files to help automated license checking.
+The following are changes across a number of patches, or changes worth
-  The linter has been enabled to check the Makefiles as well.
+noting, but not needing a full description.
-* Cleaned up Kconfig files and source code.
-* Enabled acpigen to generate tables for SPCR (Serial Port Console
-  Redirection) and GTDT (Generic Timer Description Table).
-* The resource allocation above the 4GiB boundary has been improved.
-* Most of the code has been adjusted to make use of C99 flexible arrays
-  instead of one-element or zero-length arrays.
-* Additional Dockerfiles based on Arch and Alpine Linux have been added
-  to build-test with alternate build environments, including musl-libc.
-  They are very basic at the moment and not equal to the coreboot-sdk.
-  They will be extended in the future.
-* Added support for ITE IT8784E to superiotool.
-* Added support for Intel 700 chipset series to inteltool and a build
-  issue with musl–libc has been fixed.
-* Added support for Intel 800 chipset series to ifdtool.
-* The coreboot-sdk container has been extended so that it allows
-  extracting the MRC binary from Haswell-based ChromeOS firmware images.
-* From now on POST code preprocessor macros should have a POSTCODE
-  prefix following the name of the POST code.
-* The NASM compiler provided by the coreboot toolchain wasn’t properly
-  integrated into xcompile and thus it wasn’t used by the build system.
-  Instead, it was required to install NASM on the host in order to use
-  it. This has been fixed.
-* The time measurement done in abuild got improved and also an issue
-  has been fixed when the variant name contains hyphens.
-* The RISC-V code was enabled to build with Clang.
-* Initial work has been done to transform Camelcase options to
-  Snakecase.
-* The buildgcc script is now able to just fetch the tarballs if desired,
-  which is needed for reproducible build environments for example.
 
+* Changes that only need a line or two of description go here.
 
+Platform Updates
+----------------
 
-Changes to external resources
+* To be filled in immediately before the release by the release team
------------------------------
 
-### Toolchain
+Plans to move platform support to a branch
-
+------------------------------------------
-* binutils
-  * Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
-* Upgrade IASL from 20221020 to 20230628
-* Upgrade LLVM from 15.0.7 to 16.0.6
-* Upgrade NASM from 2.15.05 to 2.16.01
-  * Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
-* Upgrade CMake from 3.26.3 to 3.26.4
-* Upgrade GCC from 11.3.0 to 11.4.0
-  * Added gcc-11.4.0_rv32iafc.patch
-
-
-### Git submodule pointers
-
-#### /3rdparty
-* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
-* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
-(851 commits)
-* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
-* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
-* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
-commits)
-* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
-commits)
-* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
-* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
-* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
-
-#### /util
-* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
-* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
-commit)
-
-
-### External payloads
-
-* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
-* Upgrade EDK2-MrChromebox from version 202304 to version 202306
-* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
-* Update tint from version 0.05 to version 0.07
-* Update U-Boot from version 2021.07 to version v2023.07
-
-
-Added mainboards:
------------------
-* ByteDance ByteDance bd_egs
-* Google: Craaskov
-* Google: Expresso
-* Google: Karis
-* Google: Karis4ES
-* Google: Pirrha
-* Google: Ponyta
-* Google: Screebo4ES
-* Google: Ovis
-* Google: Ovis4ES
-* Google: Rex EC ISH
-* Google: Rex4ES
-* HP Compaq Elite 8300 USDT
-* HP EliteBook 820 G2
-* IBM SBP1
-* Intel Raptorlake silicon with Alderlake-P RVP
-* Inventec Transformers
-* MSI PRO Z790-P (WIFI)
-* MSI PRO Z790-P (WIFI) DDR4
-* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
-* System76 addw3
-* System76 bonw15
-* System76 darp9
-* System76 galp7
-* System76 gaze17 3050
-* System76 gaze17 3060-b
-* System76 gaze18
-* System76 lemp12
-* System76 oryp11
-* System76 serw13
-
-
-Removed Mainboards
-------------------
-
-* Intel Galileo
-
-
-Updated SoCs
-------------
-
-* Removed src/soc/intel/quark
 
+* Seciton to be filled in or removed after discussion
 
 Statistics from the 4.20 to the 4.21 release
 --------------------------------------------
 
-* Total Commits: 1252
+* To be filled in immediately before the release by the release team
-* Average Commits per day: 12.59
-* Total lines added: 317734
-* Average lines added per commit: 253.78
-* Number of patches adding more than 100 lines: 86
-* Average lines added per small commit: 36.22
-* Total lines removed: 261063
-* Average lines removed per commit: 208.52
-* Total difference between added and removed: 56671
-
-* Total authors: 143
-* New authors: 21
 
 
 Significant Known and Open Issues
 ---------------------------------
 
+* To be filled in immediately before the release by the release team
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* IRC: https://web.libera.chat/#coreboot
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.22-relnotes.md

@@ -1,48 +0,0 @@
-Upcoming release - coreboot 4.22
-========================================================================
-
-The 4.22 release is planned for mid-November, 2023
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-### Significant or interesting changes
-
-* Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-### Toolchain updates
-
-* To be filled in immediately before the release by the release team
-
-### Additional coreboot changes
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-### Platform Updates
-
-* To be filled in immediately before the release by the release team
-
-### Plans to move platform support to a branch
-
-* Section to be filled in or removed after discussion
-
-### Statistics from the 4.21 to the 4.22 release
-
-* To be filled in immediately before the release by the release team
-
-
-### Significant Known and Open Issues
-
-* To be filled in immediately before the release by the release team

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.22 - November 2023](coreboot-4.22-relnotes.md)
+* [4.21 - August 2023](coreboot-4.21-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,8 +15,7 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.21   - August 2023](coreboot-4.21-relnotes.md)
+* [4.20 - May 2023](coreboot-4.20-relnotes.md)
-* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
 * [4.19 - January 2023](coreboot-4.19-relnotes.md)
 * [4.18 - October 2022](coreboot-4.18-relnotes.md)
 * [4.17 - May 2022](coreboot-4.17-relnotes.md)
@@ -28,7 +27,7 @@ important is taken care of.
 * [4.11 - November 2019](coreboot-4.11-relnotes.md)
 * [4.10 - July 2019](coreboot-4.10-relnotes.md)
 * [4.9 - December 2018](coreboot-4.9-relnotes.md)
-* [4.8.1  - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 * [4.7 - January 2018](coreboot-4.7-relnotes.md)
 * [4.6 - April 2017](coreboot-4.6-relnotes.md)
 * [4.5 - October 2016](coreboot-4.5-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -36,37 +36,16 @@
 - Agah
 - Anahera
 - Anahera4ES
-- Aurash
-- Banshee
 - Brask
 - Brya 0
-- Craask
-- Craaskov
-- Constitution
-- Crota
 - Felwinter
-- Gaelin
 - Gimble
 - Gimble4ES
-- Gladios
-- Gothrax
-- Hades
 - Kano
-- Kinox
-- Kuldax
-- Joxer
-- Lisbon
-- Marasov
-- Mithrax
-- Moli
 - Nivviks
 - Nereid
-- Omnigul
-- Osiris
-- Pirrha
 - Primus
 - Primus4ES
-- Pujjo
 - Redrix
 - Redrix4ES
 - Skolas
@@ -74,13 +53,31 @@
 - Taeko
 - Taeko4ES
 - Taniks
-- Uldren
 - Vell
 - Volmar
+- Banshee
+- Crota
+- Moli
+- Kinox
+- Craask
+- Osiris
+- Mithrax
+- Kuldax
+- Joxer
+- Pujjo
 - Xivu
+- Gaelin
 - Yaviks
-- Yavilla
+- Lisbon
 - Zydron
+- Gladios
+- Marasov
+- Omnigul
+- Constitution
+- Aurash
+- Hades
+- Uldren
+- Yavilla
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -88,7 +85,6 @@
 - Kingler
 - Steelix
 - Voltorb
-- Ponyta
 - Krabby
 - Tentacruel
 - Magikarp
@@ -215,13 +211,6 @@
 - Coral
 - Rex 0
 - Screebo
-- Screebo4ES
-- Karis
-- Karis4ES
-- Rex EC ISH
-- Ovis
-- Ovis4ES
-- Rex4ES
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Skyrim
@@ -256,21 +245,21 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Chronicler (FMV Chromebook 14F)
+- Chronicler
-- Collis (Asus Chromebook Flip CX3)
+- Collis
 - Copano (ASUS Chromebook Flip CX5400)
 - Delbin (ASUS Chromebook Flip CX5)
 - Drobit (ASUS Chromebook CX9400)
-- Eldrid (HP Chromebook x360 14c)
+- Eldrid
 - Elemi (HP Pro c640 G2 Chromebook)
 - Halvor
-- Lindar (Lenovo 5i-14/Slim 5 Chromebook)
+- Lindar
 - Malefor
 - Terrador
 - Todor
 - Trondo
-- Voema (Acer Chromebook Spin 514)
+- Voema
-- Volet (Acer Chromebook 515)
+- Volet
 - Volteer
 - Volteer2
 - Volteer2_Ti50
@@ -298,7 +287,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP
 - Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
@@ -307,6 +295,7 @@
 - Coffeelake S U-DIMM DDR4 RVP8
 - Cometlake U DDR4 RVP
 - Elkhartlake LPDDR4x CRB
+- Galileo
 - Glkrvp
 - Jasperlake DDR4/LPDDR4 RVP
 - Jasperlake DDR4/LPDDR4 RVP with Chrome EC
@@ -358,8 +347,6 @@
 ## MSI
 - PRO Z690-A (WIFI) DDR4
 - PRO Z690-A (WIFI)
-- PRO Z790-P (WIFI) DDR4
-- PRO Z790-P (WIFI)
 
 ## OpenCellular
 - Elgon (GBCv2)
@@ -385,11 +372,6 @@
 ## Star Labs
 - Star Labs Lite Mk III (N5000)
 - Star Labs Lite Mk IV (N5030)
-- Star Labs LabTop Mk III (i7-8550u)
-- Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-- Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-- Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
-- Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
 
 ## Supermicro
 - X11SSH-TF

Documentation/soc/intel/broadwell/blobs.md

@@ -29,25 +29,6 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede
 otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
 in the list of PCI devices.
 
-For the refcode binary extracted from Purism Librem 13 v1 (SHA256:
-8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4,
-.program section starts at file offset 0x2040), we can see the
-following code sequence:
-
-    1e06b:       c6 43 0c 00             movb   $0x0,0xc(%ebx)
-    1e06f:       c6 83 7e 03 00 00 00    movb   $0x0,0x37e(%ebx)
-    1e076:       c6 83 70 03 00 00 01    movb   $0x1,0x370(%ebx)
-    1e07d:       66 89 43 0a             mov    %ax,0xa(%ebx)
-    1e081:       c6 83 da 01 00 00 01    movb   $0x1,0x1da(%ebx)
-    1e088:       c6 83 86 03 00 00 01    movb   $0x1,0x386(%ebx)
-
-The code at 0x1e06f sets the field that is to enable the GbE to the
-hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5)
-to 0x01 to make the refcode support Intel GbE:
-
-    cp refcode.elf refcode_gbe.elf
-    printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc
-
 ## Use Broadwell SoC code for Haswell ULT boards
 
 Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT

Documentation/tutorial/part3.md

@@ -1,20 +1,20 @@
 # Writing unit tests for coreboot
 
 ## Introduction
-General thoughts about unit testing coreboot can be found in
+General thoughts about unit testing coreboot can be found in [Unit
-[Unit-testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
+testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
 Additionally, [code coverage](../technotes/2021-05-code-coverage.md)
 support is available for unit tests.
 
 This document aims to guide developers through the process of adding and
 writing unit tests for coreboot modules.
 
-As an example of unit-under-test, `src/device/i2c.c` (referred hereafter
+As an example of unit under test, `src/device/i2c.c` (referred hereafter
 as UUT "Unit Under Test") will be used. This is simple module, thus it
 should be easy for the reader to focus solely on the testing logic,
 without the need to spend too much time on digging deeply into the
 source code details and flow of operations. That being said, a good
-understanding of what the unit-under-test is doing is crucial for
+understanding of what the unit under test is doing is crucial for
 writing unit tests.
 
 This tutorial should also be helpful for developers who want to follow
@@ -23,7 +23,7 @@ though TDD has a different work flow of building tests first, followed
 by the code that satisfies them, the process of writing tests and adding
 them to the tree is the same.
 
-## Analysis of unit-under-test
+## Analysis of unit under test
 First of all, it is necessary to precisely establish what we want to
 test in a particular module. Usually this will be an externally exposed
 API, which can be used by other modules.
@@ -69,7 +69,7 @@ UUT and not on the other modules. While some software dependencies may
 be hard to be mock (for example due to complicated dependencies) and
 thus should be simply linked into the test binaries, all hardware
 dependencies need to be mocked out, since in the user-space host
-environment, target hardware is not available.
+environment, targets hardware is not available.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -142,12 +142,12 @@ for coreboot `make unit-tests`.
      make unit-tests
 ```
 
-When trying to build test binary, one can often see the linker complaining
+When trying to build test binary, one can often see linker complains
-about `undefined reference` for a couple of symbols. This is one of the
+about `undefined reference` to couple of symbols. This is one of
 solutions to determine all external dependencies of UUT - iteratively
 build test and resolve errors one by one. At this step, developer should
 decide either it's better to add an extra module to provide necessary
-definitions or rather mock such dependency. A quick guide about adding
+definitions or rather mock such dependency. Quick guide through adding
 mocks is provided later in this doc.
 
 ## Writing new tests
@@ -324,8 +324,8 @@ a described range.
 .. admonition:: i2c-test example
 
    In our example, we may want to check that `platform_i2c_transfer` is
-   fed with a number of segments bigger than 0, each segment has flags
+   fed with number of segments bigger than 0, each segment has flags
-   which are in the supported range and each segment has a buf which is
+   which are in supported range and each segment has buf which is
    non-NULL. We are expecting such values for _every_ call, thus the
    last parameter in `expect*` macros is -1.
 
@@ -375,16 +375,16 @@ API documentation.
 
 ### Test runner
 Finally, the developer needs to implement the test `main()` function.
-All tests should be registered there and the cmocka test runner invoked.
+All tests should be registered there and cmocka test runner invoked. All
-All methods for invoking Cmocka test are described
+methods for invoking Cmocka test are described
 [here](https://api.cmocka.org/group__cmocka__exec.html).
 
 ```eval_rst
 .. admonition:: i2c-test example
 
    We don't need any extra setup and teardown functions for i2c-test, so
-   let's simply register the test for `i2c_read_field` and return from
+   let's simply register test for `i2c_read_field` and return from main
-   main the output of Cmocka's runner (it returns number of tests
+   value which is output of Cmocka's runner (it returns number of tests
    that failed).
 
    .. code-block:: c

Documentation/util.md

@@ -49,8 +49,8 @@ file `Python`
 * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
 * __chromeos__ - These scripts can be used to access ChromeOS
 resources, for example to extract System Agent reference code and other
-blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS recovery
+blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
-image. `C`
+recovery image. `C`
 * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
 libc support) `Bash`
 * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
@@ -88,7 +88,7 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
 embedded controller and insert them to the firmware image. `C`
 * __kconfig__ - Build system `Make`
 * __lint__ - Source linter and linting rules `Shell`
-* __nixos__ - A script and NixOS configuration files to create an ISO
+* __liveiso__ - A script and NixOS configuration files to create an ISO
 image for testing purposes and for working on firmware. `Bash`
 * __mainboard__ - mainboard specific scripts
 	* _google_ - Directory for google mainboard specific scripts
@@ -138,10 +138,6 @@ for the files modified in a patch or for a file `Perl`
 license headers `Shell`
 	* _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS
 file `Perl`
-	* _rm_unused_code_ - Remove all code not used for a platform
-from the local git repository for auditing or release `Bash`
-	* _show_platforms.sh_ - Makes a list of platforms in the tree.
-Does not show variants. `Shell`
 	* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
 	* _update_submodules_ - Check all submodules for updates `Bash`
 * __showdevicetree__ - Compile and dump the device tree `C`
@@ -166,9 +162,9 @@ the documentation `Bash`
 * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
 `Go`
 * __xcompile__ - Cross compile setup `Bash`
+
 ## In depth documentation
 
-* [abuild](util/abuild/index.md)
 * [cbfstool](util/cbfstool/index.md)
 * [ifdtool](util/ifdtool/index.md)
 * [intelp2m](util/intelp2m/index.md)

Documentation/util/abuild/index.md

@@ -1,260 +0,0 @@
-abuild
-======
-
-This utility is a great tool to check whether your coreboot tree
-compiles for one or all targets. It compiles the 'default' build for a
-mainboard. This is roughly equivalent to removing the .config file,
-running `make menuconfig`, selecting the manufacturer and mainboard,
-then saving the config without making any other changes.
-
-It is run on all patches submitted via gerrit as part of the process.
-Before submitting a patch, it is a very good idea to run abuild first
-to make sure your patch compiles cleanly for all.
-
-Note that abuild is a tool to do a simple build test, and binaries it
-produces may well not boot if flashed to a system.
-
-### Basic usage
-
-abuild needs to be run from the coreboot directory. If you cd into the
-coreboot/util/abuild directory and try to run it from there, it will
-not run correctly.
-
-If you invoke abuild with no parameters, it will build all boards
-automatically.
-
-You can also specify a single board to build with the -t option. For
-example, to build the Lenovo X230 target, run:
-
-```bash
-$ util/abuild/abuild -t lenovo/x230
-```
-
-### Where builds and logs are stored
-
-The resulting images and logs are stored in directory coreboot-builds/
-under your current directory. This can be overridden with --outdir:
-
-```bash
-$ util/abuild/abuild --outdir /mnt/portable/coreboot-builds
-```
-
-This is useful if you want to divert the build to an external hard
-drive, e.g. to keep the solid-state drive holding the coreboot tree
-young.
-
-(We will still refer to this directory as "coreboot-builds" below.)
-
-After running the X230 build above, the build log will be in
-coreboot-builds/LENOVO_X230/make.log.
-
-For an overview of what passed and what failed, look at
-coreboot-builds/passing_boards and coreboot-builds/failing_boards.
-**These logs are overwritten with each abuild run.** Save them elsewhere
-if you feel a need to reference the results later.
-
-### Payloads
-
-You can also specify a payload directory with -p:
-
-```bash
-mkdir payloads
-cp /somewhere/filo.elf payloads
-```
-
-Then add a file payloads/payload.sh which prints the name of the
-payload to use (and takes the mainboard as a parameter) such as:
-
-```bash
-echo "`dirname $0`/build/filo.elf"
-```
-
-Then you can build an image with payload by specifying:
-
-```bash
-util/abuild/abuild -t lenovo/x230 -p ./payloads
-```
-
-You can also tell abuild not to use a payload:
-
-```bash
-util/abuild/abuild -t lenovo/x230 -p none
-```
-
-### Build non-default configurations
-
-Sometimes you do need to build test a custom, non-default configuration.
-This can be accomplished by placing a config file in configs/.
-
-First, clean your slate with `make distclean` or `rm .config`.
-
-Then run `make menuconfig`, select the manufacturer and mainboard, and
-configure the options you need to test building for.
-
-Then save a minimal config file omitting options that did not change
-from default:
-
-```bash
-make savedefconfig
-```
-
-This file is saved as `defconfig` and can be edited further.
-
-Now this file can be saved in configs/ which will form the basis of a
-custom configuration included in an abuild. However, it needs to be
-named in a specific way for abuild to pick it up:
-
-```
-config.<board>_<suffix>
-```
-
-<board> is effectively the BOARD\_xxx Kconfig option without "BOARD\_".
-<suffix> is a free form description of the configuration being built.
-
-For example, a config for ASUS P8Z77-M PRO that tests building with MRC
-raminit code (as opposed to the default native raminit) would be named
-`config.asus_p8z77_m_pro_mrc_bin` and contains:
-
-```
-CONFIG_VENDOR_ASUS=y
-CONFIG_BOARD_ASUS_P8Z77_M_PRO=y
-# CONFIG_USE_NATIVE_RAMINIT is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
-# CONFIG_BOOTBLOCK_CONSOLE is not set
-# CONFIG_POSTCAR_CONSOLE is not set
-```
-
-For what we are trying to do, not setting USE_NATIVE_RAMINIT is the
-important part. The other three optional changes are meant to speed
-things up. All these options can be selected during `make menuconfig`.
-
-Path to MRC binary blob remains default and thus not included here.
-
-Custom configurations can also be put in a file and applied to an entire
-abuild run using -K. Assume for example you are not interested in
-the postcar stage at all and just want it to shut up, you can create
-a file named `myconfig` with this line:
-
-```
-# CONFIG_POSTCAR_CONSOLE is not set
-```
-
-and run `abuild -K myconfig` to build everything with a silent postcar
-stage.
-
-### Selectively build certain targets only (also config file naming caveats)
-
-The P8Z77-M PRO example above would fail for P8Z77-M, because the
-config file name is ambiguous. `abuild` would pick up this config when
-building for P8Z77-M, but fails when it sees that this config isn't
-meant for P8Z77-M (but for P8Z77-M PRO). To avoid this error, you have
-to skip this config using --skip_set:
-
-```bash
-util/abuild/abuild --skip_set BOARD_ASUS_P8Z77_M_PRO
-```
-
-To complete the test, run abuild again specifically for this board
-variant (see next section).
-
-You can skip building other targets based on other Kconfigs. To skip
-building targets without a Kconfig set, use --skip_unset:
-
-```bash
-util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT
-```
-This example skips building configs not using (Sandy/Ivy Bridge) native
-RAM init.
-
-### Additional Examples
-
-Many boards have multiple variants. You can build for a specific
-variant of a board:
-
-```bash
-util/abuild/abuild -t asus/p8x7x-series -b p8z77-m_pro -p none
-```
-
-Many of the boards need files from the 'blobs' repository, which will
-be initialized by the -B option. If the blobs repo has already been
-initialized in your local tree, it won't hurt to add the -B.
-
-```bash
-util/abuild/abuild -B -t lenovo/x230 -p none
-```
-
-Adding ccache to your system and telling abuild to use it with the -y
-option will speed things up a bit:
-
-```bash
-util/abuild/abuild -B -y -t lenovo/x230 -p none
-```
-
-Telling abuild to use multiple cores with the -c option helps speed
-things up as well:
-
-```bash
-util/abuild/abuild -B -y -c 8 -t lenovo/x230 -p none
-```
-
-Of course, the real power of abuild is in testing multiple boards.
-
-```bash
-util/abuild/abuild -B -y -c 8 -p none
-```
-
-### Full options list
-
-```text
-coreboot autobuild v0.11.01 (Feb 3, 2023)
-[...]
-Usage: util/abuild/abuild [options]
-       util/abuild/abuild [-V|--version]
-       util/abuild/abuild [-h|--help]
-
-Options:
-    [-a|--all]                    Build previously succeeded ports as well
-    [-A|--any-toolchain]          Use any toolchain
-    [-b|--board-variant <name>]   Build specific board variant under the
-                                  given target.
-    [-B|--blobs]                  Allow using binary files
-    [--checksum <path/basefile>]  Store checksums at path/basefile
-    [-c|--cpus <numcpus>]         Build on <numcpus> at the same time
-    [-C|--config]                 Configure-only mode
-    [-d|--dir <dir>]              Directory containing config files
-    [-e|--exitcode]               Exit with a non-zero errorlevel on failure
-    [-J|--junit]                  Write JUnit formatted xml log file
-    [-K|--kconfig <name>]         Prepend file to generated Kconfig
-    [-l|--loglevel <num>]         Set loglevel
-    [-L|--clang]                  Use clang on supported arch
-    [-n|--name]                   Set build name - also sets xmlfile if not
-                                  already set
-    [-o|--outdir <path>]          Store build results in path
-                                  (defaults to coreboot-builds)
-    [-p|--payloads <dir>]         Use payloads in <dir> to build images
-    [-P|--prefix <name>]          File name prefix in CBFS
-    [-q|--quiet]                  Print fewer messages
-    [-r|--remove]                 Remove output dir after build
-    [-R|--root <path>]            Absolute path to coreboot sources
-                                  (defaults to /usr/src/coreboot)
-    [--scan-build]                Use clang's static analyzer
-    [--skip_set <value>]          Skip building boards with this Kconfig set
-    [--skip_unset <value>]        Skip building boards with this Kconfig not set
-    [--timeless]                  Generate timeless builds
-    [-t|--target <vendor/board>]  Attempt to build target vendor/board only
-    [-T|--test]                   Submit image(s) to automated test system
-    [-u|--update]                 Update existing image
-    [-v|--verbose]                Print more messages
-    [-x|--chromeos]               Build with CHROMEOS enabled
-                                  Skip boards without ChromeOS support
-    [-X|--xmlfile <name>]         Set JUnit XML log file filename
-                                  (defaults to /usr/src/coreboot/abuild.xml)
-    [-y|--ccache]                 Use ccache
-    [-z|--clean]                  Remove build results when finished
-    [-Z|--clean-somewhat]         Remove build but keep coreboot.rom + config
-
-    [-V|--version]                Print version number and exit
-    [-h|--help]                   Print this help and exit
-
-    [-s|--silent]                 obsolete
-```

MAINTAINERS

@@ -340,22 +340,18 @@ F:	src/mainboard/gizmosphere/
 
 GOOGLE REX MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <tstuli@gmail.com>
+M:	Tarun Tuli <taruntuli@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <jacz@semihalf.com>
-M:	Eran Mitrani <mitrani@google.com>
 S:	Maintained
 F:	src/mainboard/google/rex/
 
 GOOGLE BRYA MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
+M:	Tarun Tuli <taruntuli@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
 GOOGLE HATCH MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
+M:	Tarun Tuli <taruntuli@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/hatch/
 
@@ -421,10 +417,7 @@ M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
 S:	Maintained
 F:	src/mainboard/intel/harcuvar/
 
-INVENTEC MAINBOARDS
+
-M:	Annie Chen <Chen.AnnieET@inventec.com>
-S:	Maintained
-F:	src/mainboard/inventec/
 
 JETWAY MAINBOARDS
 S:	Orphan
@@ -868,16 +861,14 @@ F:	src/soc/amd/stoneyridge/
 
 INTEL METEORLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <tstuli@gmail.com>
+M:	Tarun Tuli <taruntuli@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <jacz@semihalf.com>
-M:	Eran Mitrani <mitrani@google.com>
 S:	Maintained
 F:	src/soc/intel/meteorlake/
 
 INTEL ALDERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
@@ -894,10 +885,6 @@ S:	Maintained
 F:	/src/soc/intel/braswell/
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 
-INTEL CANNONLAKE SOC
-S:	Orphan
-F:	src/soc/intel/cannonlake/
-
 INTEL DENVERTON-NS SOC
 M:	Jeff Daly <jeffd@silicom-usa.com>
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
@@ -912,7 +899,7 @@ F:	src/soc/intel/elkhartlake/
 
 INTEL TIGERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/soc/intel/tigerlake/
 
@@ -968,12 +955,6 @@ M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 M:	Martin Roth <gaumless@gmail.com>
 F:	payloads/external/
 
-COREDOOM PAYLOAD INTEGRATION
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-W:	https://github.com/nic3-14159/coreDOOM
-S:	Maintained
-F:	payloads/external/coreDOOM/
-
 LINUXBOOT PAYLOAD INTEGRATION
 M:	Christian Walter <christian.walter@9elements.com>
 M:	Marcello Sylvester Bauer <info@marcellobauer.com>
@@ -1133,7 +1114,8 @@ F:	src/drivers/*/tpm/
 F:	src/security/tpm/
 
 SUPERIOS & SUPERIOTOOL
-S:	Orphan
+M:	Felix Held <felix-coreboot@felixheld.de>
+S:	Odd Fixes
 F:	src/superio/
 F:	util/superiotool/
 

Makefile

@@ -85,7 +85,7 @@ help_coreboot help::
 	@echo  '  clean                 - Remove coreboot build artifacts'
 	@echo  '  distclean             - Remove build artifacts and config files'
 	@echo  '  sphinx                - Build sphinx documentation for coreboot'
-	@echo  '  sphinx-lint           - Build sphinx documentation for coreboot with warnings as errors'
+	@echo  '  sphinx-lint           - Build sphinx documenttion for coreboot with warnings as errors'
 	@echo  '  filelist              - Show files used in current build'
 	@echo  '  printall              - print makefile info for debugging'
 	@echo  '  gitconfig             - set up git to submit patches to coreboot'
@@ -190,6 +190,10 @@ endif
 # are reproducible
 export LANG LC_ALL TZ SOURCE_DATE_EPOCH
 
+ifneq ($(CONFIG_MMX),y)
+CFLAGS_x86_32 += -mno-mmx
+endif
+
 ifneq ($(UNIT_TEST),1)
 include toolchain.inc
 endif
@@ -197,10 +201,6 @@ endif
 strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
 # fix makefile syntax highlighting after strip macro \" "))
 
-ifneq ($(NOCOMPILE),1)
-$(shell rm -f $(CCACHE_STATSLOG))
-endif
-
 # The primary target needs to be here before we include the
 # other files
 
@@ -273,7 +273,6 @@ src-to-ali=\
 # Add paths to files in X-y to X-srcs
 # Add subdirs-y to subdirs
 includemakefiles= \
-	$(if $(wildcard $(1)), \
 	$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
 	$(eval -include $(1)) \
 	$(foreach class,$(classes-y), $(call add-class,$(class))) \
@@ -284,7 +283,7 @@ includemakefiles= \
 			$$(subst $(absobj)/,$(obj)/, \
 			$$(subst $(top)/,, \
 			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
-		$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))))
+	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
 
 # For each path in $(subdirs) call includemakefiles
 # Repeat until subdirs is empty
@@ -316,11 +315,6 @@ $(eval $(postinclude-hooks))
 # Eliminate duplicate mentions of source files in a class
 $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
 
-ifeq ($(CONFIG_IWYU),y)
-MAKEFLAGS += -k
-SAVE_IWYU_OUTPUT := 2>&1 | grep "should\|\#include\|---\|include-list\|^[[:blank:]]\?\'" | tee -a $$(obj)/iwyu.txt
-endif
-
 # Build Kconfig .ads if necessary
 ifeq ($(CONFIG_ROMSTAGE_ADA),y)
 romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
@@ -387,7 +381,7 @@ $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4)
 	@printf "    CC         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(CC_$(1)) \
 		-MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \
-		$(3) -c -o $$$$@ $$$$< $(SAVE_IWYU_OUTPUT)
+		$(3) -c -o $$$$@ $$$$<
 end$(EMPTY)if
 en$(EMPTY)def
 end$(EMPTY)if
@@ -468,10 +462,10 @@ cscope:
 	cscope -bR
 
 sphinx:
-	$(MAKE) -C Documentation sphinx
+	$(MAKE) -C Documentation -f Makefile.sphinx html
 
 sphinx-lint:
-	$(MAKE) SPHINXOPTS=-W -C Documentation sphinx
+	$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
 
 symlink:
 	@echo "Creating Symbolic Links.."; \

Makefile.inc

@@ -23,7 +23,7 @@ ifeq ($(BUILD_TIMELESS),1)
 KERNELVERSION := -TIMELESS--LESSTIME-
 else
 KERNELVERSION := $(strip $(if $(GIT),\
-	$(shell git describe --abbrev=12 --dirty --always || git describe),\
+	$(shell git describe --dirty --always || git describe),\
 	$(if $(wildcard $(top)/.coreboot-version),\
 		$(shell cat $(top)/.coreboot-version),\
 		coreboot-unknown$(KERNELREVISION))))
@@ -66,11 +66,8 @@ coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(
 # targets after the build completes by creating a Makefile.inc in the
 # site-local directory with a target named 'build_complete::'
 build_complete:: coreboot
-	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
+	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) \
-	if [ -f "$(CCACHE_STATSLOG)" ]; then \
+		$(CONFIG_MAINBOARD_PART_NUMBER)
-		printf "\nccache statistics\n"; \
-		$(CCACHE) --show-log-stats -v; \
-	fi
 
 # This target can be used to run rules after all files were added to CBFS,
 # for example to process FMAP regions or the entire image.
@@ -146,7 +143,6 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
 # tolower:        returns the value in all lowercase
 # toupper:        returns the value in all uppercase
 # ws_to_under:    returns the value with any whitespace changed to underscores
-# get_fmap_value  returns the value of a given FMAP field from fmap_config.h
 _toint=$(shell printf "%d" $1)
 _tohex=$(shell printf 0x"%x" $1)
 _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2))
@@ -166,7 +162,6 @@ file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
 tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
 toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
 ws_to_under=$(shell echo '$1' | tr ' \t' '_')
-get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
 
 #######################################################################
 # Helper functions for ramstage postprocess
@@ -331,19 +326,6 @@ define cbfs-files-processor-config
 		mv -f $(2).tmp $(2))
 endef
 
-#######################################################################
-# Add a file to CBFS with just type and compression values
-# arg1: name in CBFS
-# arg2: filename and path
-# arg3: type in CBFS
-# arg4: compression type
-define add-cbfs-file-simple
-	$(eval cbfs-files-y += $(1))
-	$(eval $(1)-file := $(2))
-	$(eval $(1)-type := $(3))
-	$(eval $(1)-compression := $(4))
-endef
-
 #######################################################################
 # Compile a C file with a bare struct definition into binary
 # arg1: C source file
@@ -356,41 +338,6 @@ cbfs-files-processor-struct= \
 		rm -f $(2).tmp) \
 	$(eval DEPENDENCIES += $(2).d)
 
-#######################################################################
-# Convert image to YCC 4:2:0 JPEG
-#
-# In two steps:
-# 1. Convert to RGB colors, optionally resize and store as BMP.
-# 2. Round final size to multiples of 16, optionally swap colors,
-#    convert (back) to sRGB and store as JPEG.
-# The split is necessary because we don't know the exact, scaled
-# size due to aspect-ratio. Note: IM v7 would allow us to do the
-# calculations in one command using %[fx:...] syntax.
-#
-# arg1: image input file
-# arg2: output jpg
-cbfs-files-processor-jpg420= \
-	$(eval $(2): $(1) $(KCONFIG_AUTOCONFIG);				\
-		printf "    CONVERT    $$<\n";					\
-		res=$(CONFIG_BOOTSPLASH_CONVERT_RESOLUTION);			\
-		res=$$$$(convert $$<						\
-			-colorspace RGB						\
-			$$(BOOTSPLASH_RESIZE-y)					\
-			-format '%wx%h' -write info:				\
-			bmp:$$@);						\
-		convert $$@							\
-			$$(BOOTSPLASH_ROUND16)					\
-			$$(BOOTSPLASH_COLORSWAP-y)				\
-			-colorspace sRGB					\
-			-quality $$(CONFIG_BOOTSPLASH_CONVERT_QUALITY)%		\
-			-interlace none -colorspace YCC -sampling-factor 4:2:0	\
-			jpg:$$@)
-BOOTSPLASH_FLOOR = $$(($${res%%x*} & ~15))x$$(($${res\#\#*x} & ~15))
-BOOTSPLASH_RESIZE-$(CONFIG_BOOTSPLASH_CONVERT_RESIZE) = -resize $(BOOTSPLASH_FLOOR)
-BOOTSPLASH_CEIL = $$((($${res%%x*} + 15) & ~15))x$$((($${res\#\#*x} + 15) & ~15))
-BOOTSPLASH_ROUND16 = -background black -gravity center -extent $(BOOTSPLASH_CEIL)
-BOOTSPLASH_COLORSWAP-$(CONFIG_BOOTSPLASH_CONVERT_COLORSWAP) := -channel-fx 'red<=>blue'
-
 #######################################################################
 # Add handler for arbitrary files in CBFS
 $(call add-special-class,cbfs-files)
@@ -488,7 +435,7 @@ ifeq ($(CONFIG_COMPILER_GCC),y)
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
-CFLAGS_common += -Wnull-dereference
+CFLAGS_common += -Wnull-dereference -Wreturn-type
 CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
 endif
 endif
@@ -650,8 +597,6 @@ APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
 APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
 
-APCB_V3A_EDIT_TOOL:=$(top)/util/apcb/apcb_v3a_edit.py
-
 CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
 
 FUTILITY?=$(objutil)/futility/futility
@@ -866,7 +811,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
 #                mma, efi, deleted, null
 # 4 - Compression type      [$(FILENAME)-compression]
 #                      none, LZMA
-# 5 - Base address          [$(FILENAME)-position]
+# 5 - Base address          [$(FILANAME)-position]
 # 6 - Alignment             [$(FILENAME)-align]
 # 7 - cbfstool flags        [$(FILENAME)-options]
 #
@@ -1068,15 +1013,6 @@ else
 FMAP_VPD_ENTRY :=
 endif
 
-ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
-FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000)
-FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE)
-FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)
-FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE))
-else
-FMAP_HSPHY_FW_ENTRY :=
-endif
-
 #
 # X86 FMAP region
 #
@@ -1155,7 +1091,6 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
 	    -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
 	    -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
 	    -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
-	    -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \
 	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
 	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
 		$(DEFAULT_FLASHMAP) > $@.tmp
@@ -1316,19 +1251,10 @@ cbfs-files-y += build_info
 build_info-file := $(obj)/build_info
 build_info-type := raw
 
-ifeq ($(CONFIG_BOOTSPLASH_CONVERT),y)
-ifeq ($(shell command -v convert),)
-$(error CONFIG_BOOTSPLASH_CONVERT requires the convert program (part of ImageMagick))
-endif
-cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash.jpg
-bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)):jpg420
-bootsplash.jpg-type := bootsplash
-else
 BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
 cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
 bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
 bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
-endif
 
 # Ensure that no payload segment overlaps with memory regions used by ramstage
 # (not for x86 since it can relocate itself in that case)

configs/builder/config.transformers

@@ -1,16 +0,0 @@
-# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
-# Inventec Transformers is a dual socket CRB based on Intel.
-# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
-#
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
-
-CONFIG_VENDOR_INVENTEC=y
-CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-CONFIG_PAYLOAD_LINUX=y
-CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"

configs/config.intel_galileo_gen1

@@ -0,0 +1,10 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_GALILEO_GEN2 is not set
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_460800=y

configs/config.intel_galileo_gen2

@@ -0,0 +1,9 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.debug

@@ -0,0 +1,13 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_DISPLAY_MTRRS=y
+CONFIG_DISPLAY_ESRAM_LAYOUT=y
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+CONFIG_VERIFY_HOBS=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.fsp2.0

@@ -0,0 +1,8 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.sd

@@ -0,0 +1,18 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_COMMONLIB_STORAGE_MMC=y
+CONFIG_STORAGE_ERASE=y
+CONFIG_STORAGE_EARLY_ERASE=y
+CONFIG_STORAGE_WRITE=y
+CONFIG_STORAGE_EARLY_WRITE=y
+CONFIG_SD_MMC_DEBUG=y
+CONFIG_SD_MMC_TRACE=y
+CONFIG_SDHC_TRACE=y
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.vboot

@@ -0,0 +1,9 @@
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_VBOOT_WITH_CRYPTO_SHIELD=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.msi_ms7e06_ddr4

@@ -1,11 +0,0 @@
-CONFIG_VENDOR_MSI=y
-CONFIG_VBOOT=y
-CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-CONFIG_TPM2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_CBMEM_LOGGING=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

configs/config.msi_ms7e06_ddr5

@@ -1,11 +0,0 @@
-CONFIG_VENDOR_MSI=y
-CONFIG_VBOOT=y
-CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-CONFIG_TPM2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_CBMEM_LOGGING=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

configs/config.scaleway_tagada

@@ -0,0 +1,15 @@
+CONFIG_VENDOR_SCALEWAY=y
+CONFIG_BOARD_SCALEWAY_TAGADA=y
+CONFIG_CBFS_SIZE=0x400000
+CONFIG_CONSOLE_POST=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_IQAT_ENABLE is not set
+CONFIG_LEGACY_UART_MODE=y
+CONFIG_USE_DENVERTON_NS_FSP_CAR=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd"
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_BOOT_STATE=y

configs/config.starlabs_starbook_adl_option_table

@@ -1,8 +0,0 @@
-CONFIG_VENDOR_STARLABS=y
-CONFIG_BOARD_STARLABS_STARBOOK_ADL=y
-CONFIG_MAINBOARD_SERIAL_NUMBER="B6I0000"
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_LOCALVERSION="8.42"
-CONFIG_MAINBOARD_USE_LIBGFXINIT=n
-CONFIG_SMMSTORE=y
-CONFIG_SMMSTORE_V2=y

payloads/coreinfo/bootlog_module.c

@@ -17,7 +17,7 @@ static s32 g_max_cursor_line = 0;
 struct cbmem_console {
 	u32 size;
 	u32 cursor;
-	u8 body[];
+	u8 body[0];
 } __packed;
 
 #define CURSOR_MASK ((1 << 28) - 1)

payloads/coreinfo/cbfs_module.c

@@ -31,7 +31,7 @@ struct cbheader {
 	u32 align;
 	u32 offset;
 	u32 architecture;
-	u32 pad[];
+	u32 pad[1];
 } __packed;
 
 struct cbfile {
@@ -40,7 +40,7 @@ struct cbfile {
 	u32 type;
 	u32 checksum;
 	u32 offset;
-	char filename[];
+	char filename[0];
 } __packed;
 
 static int filecount = 0, selected = 0, start_row = 0;

payloads/external/FILO/Kconfig

@@ -9,7 +9,7 @@ config FILO_STABLE
 	help
 	  Tested FILO version
 
-config FILO_HEAD
+config FILO_MASTER
 	bool "HEAD"
 	help
 	  Newest FILO version

payloads/external/FILO/Makefile

@@ -1,5 +1,5 @@
-TAG-$(CONFIG_FILO_HEAD)=origin/main
+TAG-$(CONFIG_FILO_MASTER)=origin/master
-NAME-$(CONFIG_FILO_HEAD)=MAIN
+NAME-$(CONFIG_FILO_MASTER)=MASTER
 TAG-$(CONFIG_FILO_STABLE)=c2fa1ea6125c63e84cdf7779c37d76da8c5bc412
 NAME-$(CONFIG_FILO_STABLE)=STABLE
 
@@ -20,7 +20,7 @@ checkout:
 	test -d filo || \
 		git clone $(project_git_repo) $(project_dir)
 	cd filo && \
-		git checkout main && \
+		git checkout master && \
 		git remote update && \
 		test -n $(TAG-y) && \
 			git branch -f $(NAME-y) $(TAG-y) && \

payloads/external/LinuxBoot/Kconfig

@@ -19,13 +19,6 @@ config LINUXBOOT_X86
 	help
 	  X86 kernel and initramfs
 
-config LINUXBOOT_ARM
-	bool "arm64"
-	depends on ARCH_ARM
-	select PAYLOAD_FIT_SUPPORT
-	help
-	  arm kernel and initramfs
-
 config LINUXBOOT_ARM64
 	bool "arm64"
 	depends on ARCH_ARM64
@@ -33,16 +26,9 @@ config LINUXBOOT_ARM64
 	help
 	  AARCH64 kernel and initramfs
 
-config LINUXBOOT_RISCV_RV32
+config LINUXBOOT_RISCV
 	bool "RISC-V"
-	depends on ARCH_RISCV_RV32
+	depends on ARCH_RISCV
-	select PAYLOAD_FIT_SUPPORT
-	help
-	  RISC-V kernel and initramfs
-
-config LINUXBOOT_RISCV_RV64
-	bool "RISC-V"
-	depends on ARCH_RISCV_RV64
 	select PAYLOAD_FIT_SUPPORT
 	help
 	  RISC-V kernel and initramfs
@@ -55,38 +41,76 @@ config LINUXBOOT_COMPILE_KERNEL
 	bool "Compile kernel"
 	default n
 
+if LINUXBOOT_COMPILE_KERNEL
+comment "parse linux crosscompiler with: LINUXBOOT_CROSS_COMPILE"
+endif
+
 config LINUXBOOT_KERNEL_PATH
 	string "Path to kernel"
-	default "build/uImage" if LINUXBOOT_KERNEL_UIMAGE
+	default "Image"
-	default "build/bzImage" if LINUXBOOT_KERNEL_BZIMAGE
+	depends on !LINUXBOOT_COMPILE_KERNEL
-	help
-	  The kernel path is either and absolute path or relative to the
-	  LinuxBoot directory
 
 if LINUXBOOT_COMPILE_KERNEL
 
-config LINUXBOOT_CROSS_COMPILE
+choice
-	string "cross compiler"
+	prompt "Kernel release"
-	default "" # e.g. "aarch64-linux-gnu-"
+	default LINUXBOOT_KERNEL_STABLE
 	help
-	  Choose a custom cross compiler toolchain to use.
+	  Choose the kernel release.
-	  It can be useful if you don't want to use the coreboot toolchain
-	  or experience problems using it.
 
-config LINUXBOOT_KERNEL_VERSION
+	  Select 'custom' if your want to define the kernel version.
+	  For more information about the current 'mainline', 'stable' or 'longterm'
+	  version, visit: https://www.kernel.org/
+
+config LINUXBOOT_KERNEL_MAINLINE
+	bool "mainline"
+	help
+	  Mainline kernel version
+
+config LINUXBOOT_KERNEL_STABLE
+	bool "stable"
+	help
+	  Stable kernel version
+
+config LINUXBOOT_KERNEL_LONGTERM
+	bool "longterm"
+	help
+	  Longterm (LTS) kernel version
+
+config LINUXBOOT_KERNEL_CUSTOM
+	bool "custom"
+	help
+	  Custom kernel version
+
+endchoice
+
+config LINUXBOOT_KERNEL_CUSTOM_VERSION
 	string "kernel version"
-	default "6.3"
+	default ""
+	depends on LINUXBOOT_KERNEL_CUSTOM
 	help
 	  Choose the Linux kernel version number. (x.x.x)
 	  Release candidate kernels (rc) are currently are not supported.
 
+choice
+	prompt "Kernel configuration"
+	default LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
+
+config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
+	bool "Default architecture configuration"
+	help
+	  This option will use the default configuration for the
+	  selected architecture.
+
+config LINUXBOOT_KERNEL_CUSTOM_CONFIG
+	bool "Custom (def)config file"
+
+endchoice
+
 config LINUXBOOT_KERNEL_CONFIGFILE
 	string "Config file path"
-	default "i386/defconfig"     if LINUXBOOT_X86
+	default "defconfig"
-	default "x86_64/defconfig"   if LINUXBOOT_X86_64
+	depends on LINUXBOOT_KERNEL_CUSTOM_CONFIG
-	default "arm64/defconfig"    if LINUXBOOT_ARM64
-	default "riscv/defconfig-32" if LINUXBOOT_RISCV_RV32
-	default "riscv/defconfig-64" if LINUXBOOT_RISCV_RV64
 	help
 	  Path to the kernel configuration file.
 
@@ -95,7 +119,7 @@ config LINUXBOOT_KERNEL_CONFIGFILE
 choice
 	prompt "Kernel binary format"
 	default LINUXBOOT_KERNEL_BZIMAGE if LINUXBOOT_X86 || LINUXBOOT_X86_64
-	default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
+	default LINUXBOOT_KERNEL_UIMAGE if LINUXBOOT_ARM64 || LINUXBOOT_RISCV
 
 config LINUXBOOT_KERNEL_BZIMAGE
 	bool "bzImage"
@@ -103,14 +127,14 @@ config LINUXBOOT_KERNEL_BZIMAGE
 
 config LINUXBOOT_KERNEL_UIMAGE
 	bool "uImage"
-	depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
+	depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV
 
 endchoice
 
-config LINUXBOOT_DTS_FILE
+config LINUXBOOT_DTB_FILE
 	string "Compiled devicetree file"
-	depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV_RV32 || LINUXBOOT_RISCV_RV64
+	depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV
-	default "empty.dts"
+	default ""
 
 endif #LINUXBOOT_COMPILE_KERNEL
 
@@ -121,7 +145,9 @@ config LINUX_COMMAND_LINE
 	  Add your own kernel command-line arguments.
 
 config PAYLOAD_FILE
-	default "payloads/external/LinuxBoot/build/Image"
+	default "payloads/external/LinuxBoot/linuxboot/bzImage" if LINUXBOOT_COMPILE_KERNEL && ( LINUXBOOT_X86 || LINUXBOOT_X86_64 )
+	default "payloads/external/LinuxBoot/linuxboot/uImage" if LINUXBOOT_COMPILE_KERNEL && (LINUXBOOT_ARM64 || LINUXBOOT_RISCV)
+	default LINUXBOOT_KERNEL_PATH if !LINUXBOOT_COMPILE_KERNEL
 
 comment "Linux initramfs"
 
@@ -131,17 +157,16 @@ config LINUXBOOT_BUILD_INITRAMFS
 
 config LINUXBOOT_INITRAMFS_PATH
 	string "Path to initramfs"
-	default "build/initramfs_u-root.cpio" if LINUXBOOT_UROOT
+	depends on !LINUXBOOT_BUILD_INITRAMFS
 
 if LINUXBOOT_BUILD_INITRAMFS
 
 choice
-	prompt "Initramfs"
+	prompt "Payload Mode"
 	default LINUXBOOT_UROOT
 
 config LINUXBOOT_UROOT
 	bool "u-root"
-	depends on !LINUXBOOT_RISCV_RV32 # not supported by u-root
 	help
 	  Enable u-root linuxboot mode.
 	  See http://u-root.tk/ for more information.
@@ -320,6 +345,11 @@ config LINUXBOOT_INITRAMFS_COMPRESSION_XZ
 
 endchoice
 
+config LINUX_INITRD
+	string
+	default "payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio" if LINUXBOOT_UROOT
+	default LINUXBOOT_INITRAMFS_PATH if !LINUXBOOT_BUILD_INITRAMFS
+
 config LINUXBOOT_INITRAMFS_SUFFIX
 	string
 	default "" if LINUXBOOT_INITRAMFS_COMPRESSION_NONE

payloads/external/LinuxBoot/Makefile

@@ -1,57 +1,62 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+project_dir=linuxboot
+
 unexport $(COREBOOT_EXPORTS)
 
-DTC ?= dtc
+all: linuxboot
 
-LINUX_ARCH-$(CONFIG_LINUXBOOT_X86_64)     = x86_64
+u-root:
-LINUX_ARCH-$(CONFIG_LINUXBOOT_X86)        = i386
+	$(MAKE) -f targets/u-root.mk
-LINUX_ARCH-$(CONFIG_LINUXBOOT_ARM64)      = arm64
-LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv
-LINUX_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv
 
-build/Image: $(CONFIG_LINUXBOOT_KERNEL_PATH) | build
+ifeq ($(CONFIG_LINUXBOOT_BUILD_INITRAMFS),y)
-	ln -s -r $< $@
+ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
+initramfs: u-root
+endif
+else
+ifneq ($(CONFIG_LINUXBOOT_INITRAMFS),)
+initramfs:
+	if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_INITRAMFS)" ]]; then \
+	echo "<< Linux initramfs '$(CONFIG_LINUXBOOT_INITRAMFS)' is missing. >>"; \
+	exit 1; \
+	fi
+endif
+endif
 
+initramfs_compressed: initramfs
+ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
+	xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS)
+endif
 
 ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y)
-include targets/linux.mk
+ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+kernel: initramfs
+	if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_DTB_FILE)" ]]; then \
+	echo "<< Linux kernel devicetree is missing. >>"; \
+	exit 1; \
+	fi
+	$(MAKE) -f targets/linux.mk
+else
+kernel:
+	$(MAKE) -f targets/linux.mk
 endif
-ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
+else
-include targets/u-root.mk
+kernel:
+	if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_KERNEL)" ]]; then \
+	echo "<< Linux kernel '$(CONFIG_LINUXBOOT_KERNEL)' is missing. >>"; \
+	exit 1; \
+	fi
 endif
 
-build/initramfs: $(CONFIG_LINUXBOOT_INITRAMFS_PATH) | build
+linuxboot: kernel initramfs_compressed
-ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
-	xz --keep --force --check=crc32 --lzma2=dict=1MiB $(CONFIG_LINUXBOOT_INITRAMFS_PATH)
-endif
-	cp $(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $@
-
-ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
-
-build/bzImage: $(kernel_dir)/arch/x86/boot/bzImage | build
-	cp $< $@
-
-else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
-
-build/target.dtb: $(CONFIG_LINUXBOOT_DTS_FILE)
-	$(DTC) -o $@ $<
-
-build/uImage: build/vmlinux.bin.lzma build/initramfs build/target.dtb $(LINUX_ARCH-y)/kernel_fdt_lzma.its | build
-	mkimage -f $(LINUX_ARCH-y)/kernel_fdt_lzma.its $@
-
-endif # CONFIG_LINUXBOOT_KERNEL_BZIMAGE
-
-build:
-	mkdir build
 
 clean:
-	rm -rf build/kernel*
+	rm -rf $(project_dir)/kernel*
-	rm -f  build/u-root
+	rm -f $(project_dir)/u-root
-	rm -f  build/initramfs*
+	rm -f $(project_dir)/initramfs*
-	rm -f  build/bzImage
+	rm -f $(project_dir)/bzImage
 
 distclean:
-	rm -rf build
+	rm -rf $(project_dir)
 
-.PHONY: linuxboot clean distclean
+.PHONY: linuxboot kernel initramfs_compressed initramfs u-root clean distclean

payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its

@@ -11,7 +11,7 @@
 	images {
 		kernel {
 			description = "Vanilla Linux kernel";
-			data = /incbin/("../build/vmlinux.bin.lzma");
+			data = /incbin/("vmlinux.bin.lzma");
 			type = "kernel";
 			arch = "arm64";
 			os = "linux";
@@ -30,7 +30,7 @@
 		};
 		fdt-1 {
 			description = "Flattened Device Tree blob";
-			data = /incbin/("../build/target.dtb");
+			data = /incbin/("target.dtb");
 			type = "flat_dt";
 			arch = "arm64";
 			compression = "none";
@@ -46,7 +46,7 @@
 		};
 		ramdisk-1 {
 			description = "Compressed Initramfs";
-			data = /incbin/("../build/initramfs");
+			data = /incbin/("initramfs");
 			type = "ramdisk";
 			arch = "arm64";
 			os = "linux";
@@ -65,7 +65,6 @@
 	configurations {
 		default = "conf-1";
 		conf-1 {
-			compatible = "linuxboot";
 			description = "Boot Linux kernel with FDT blob";
 			kernel = "kernel";
 			fdt = "fdt-1";

payloads/external/LinuxBoot/empty.dts

@@ -1,4 +0,0 @@
-/dts-v1/;
-
-/ {
-};

payloads/external/LinuxBoot/riscv/defconfig-32

@@ -1,4 +0,0 @@
-CONFIG_ARCH_RV32I=y
-CONFIG_32BIT=y
-# CONFIG_PORTABLE is not set
-CONFIG_NONPORTABLE=y

payloads/external/LinuxBoot/riscv/defconfig-64

@@ -1,2 +0,0 @@
-CONFIG_ARCH_RV64I=y
-CONFIG_64BIT=y

payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its

@@ -1,74 +0,0 @@
-/*
- * Simple U-Boot uImage source file containing a single kernel and FDT blob
- */
-
-/dts-v1/;
-
-/ {
-	description = "Simple image with single Linux kernel and FDT blob";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("../build/vmlinux.bin.lzma");
-			type = "kernel";
-			arch = "riscv64";
-			os = "linux";
-			compression = "lzma";
-			load = <0x80000>;
-			entry = <0x80000>;
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-			hash-3 {
-				algo = "sha256";
-			};
-		};
-		fdt-1 {
-			description = "Flattened Device Tree blob";
-			data = /incbin/("../build/target.dtb");
-			type = "flat_dt";
-			arch = "riscv64";
-			compression = "none";
-			hash-1 {
-				algo = "crc32";
-			};
-			hash-2 {
-				algo = "sha1";
-			};
-			hash-3 {
-				algo = "sha256";
-			};
-		};
-		ramdisk-1 {
-			description = "Compressed Initramfs";
-			data = /incbin/("../build/initramfs");
-			type = "ramdisk";
-			arch = "riscv64";
-			os = "linux";
-			compression = "none";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "sha1";
-			};
-			hash-2 {
-				algo = "sha256";
-			};
-		};
-	};
-
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			description = "Boot Linux kernel with FDT blob";
-			kernel = "kernel";
-			fdt = "fdt-1";
-			ramdisk = "ramdisk-1";
-		};
-	};
-};

payloads/external/LinuxBoot/targets/linux.mk

@@ -1,20 +1,41 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-SHELL := /bin/sh
+SHELL := /bin/bash
 
-OBJCOPY:=$(CONFIG_LINUXBOOT_CROSS_COMPILE)objcopy
+ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64
+ARCH-$(CONFIG_LINUXBOOT_X86)=x86
+ARCH-$(CONFIG_LINUXBOOT_ARM64)=arm64
+
+TAG-$(CONFIG_LINUXBOOT_KERNEL_MAINLINE)=mainline
+TAG-$(CONFIG_LINUXBOOT_KERNEL_STABLE)=stable
+TAG-$(CONFIG_LINUXBOOT_KERNEL_LONGTERM)=longterm
+
+pwd:=$(shell pwd)
+top:=../../..
+project_dir=linuxboot
+tarball_dir:=$(project_dir)/tarball
+decompress_flag=.done
+
+OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy
 KERNEL_MAKE_FLAGS = \
-	CROSS_COMPILE=$(CONFIG_LINUXBOOT_CROSS_COMPILE) \
+	ARCH=$(ARCH-y) \
-	ARCH=$(LINUX_ARCH-y) \
 	KBUILD_BUILD_USER="coreboot" \
 	KBUILD_BUILD_HOST="reproducible" \
 	KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \
 	KBUILD_BUILD_VERSION="0"
 
-kernel_version = $(CONFIG_LINUXBOOT_KERNEL_VERSION)
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y)
-kernel_dir = build/kernel-$(subst .,_,$(kernel_version))
+	kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION)
-kernel_tarball = linux-$(kernel_version).tar
+else
-kernel_mirror  = https://mirrors.edge.kernel.org/pub/linux/kernel
+	kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \
+		sed -n -e 's@.*<guid isPermaLink="false">\(.*\)</guid>.*@\1@p' | \
+		awk -F ',' '/$(TAG-y)/{ print $$3 }' | \
+		head -n 1)
+endif
+
+kernel_dir=$(project_dir)/kernel-$(subst .,_,$(kernel_version))
+kernel_tarball=linux-$(kernel_version).tar
+kernel_mirror=https://mirrors.edge.kernel.org/pub/linux/kernel
 
 ifeq ($(findstring x2.6.,x$(kernel_version)),x2.6.)
 kernel_mirror_path := $(kernel_mirror)/v2.6
@@ -28,35 +49,81 @@ else ifeq ($(findstring x6.,x$(kernel_version)),x6.)
 kernel_mirror_path := $(kernel_mirror)/v6.x
 endif
 
-build/$(kernel_tarball).xz: | build
+all: kernel
-	echo "    Test $(kernel_version)"
-	echo "    WWW        $(kernel_mirror_path)/$(kernel_tarball).xz";
-	curl -OLSs --output-dir build "$(kernel_mirror_path)/$(kernel_tarball).xz";
 
-$(kernel_dir): build/$(kernel_tarball).xz
+lookup:
-	echo "    XZ         $(kernel_tarball).xz";
+ifeq ($(kernel_version),)
-	mkdir $(kernel_dir);
+	$(error kernel version lookup failed for $(TAG-y) release)
-	tar xJf build/$(kernel_tarball).xz --strip 1 -C $(kernel_dir);
+endif
+	@echo "    WWW        Kernel [$(TAG-y)] $(kernel_version)"
 
-$(kernel_dir)/.config: $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) | $(kernel_dir)
+fetch:
+ifneq ($(shell [[ -d "$(kernel_dir)" && -f "$(kernel_dir)/$(decompress_flag)" ]];echo $$?),0)
+	mkdir -p $(tarball_dir)
+	if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \
+	echo "    WWW        $(kernel_tarball).xz"; \
+	cd $(tarball_dir); \
+	curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \
+	cd $(pwd); \
+	fi
+endif
+
+unpack: fetch
+	if [[ -d "$(kernel_dir)" && ! -f "$(kernel_dir)/$(decompress_flag)" ]]; then \
+	rm -rf $(kernel_dir); \
+	fi
+	if [[ ! -d "$(kernel_dir)" ]]; then \
+	mkdir $(kernel_dir); \
+	echo "    XZ         $(kernel_tarball).xz"; \
+	tar xJf $(tarball_dir)/$(kernel_tarball).xz --strip 1 -C $(kernel_dir); \
+	fi
+	touch $(kernel_dir)/$(decompress_flag)
+
+$(kernel_dir)/.config: unpack
 	@echo "    CONFIG     Linux $(kernel_version)"
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG),y)
 	cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
+else
+	cp $(ARCH-y)/defconfig $(kernel_dir)/.config
+endif
 	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig
 
-$(kernel_dir)/vmlinux : $(kernel_dir)/.config | $(kernel_dir)
+build: $(kernel_dir)/.config
 	@echo "    MAKE       Linux $(kernel_version)"
-	echo "$(MAKE) -j 4 -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux"
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
-	$(MAKE) -j 4 -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) vmlinux
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage
+else
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux
+endif
+endif
 
-build/vmlinux.bin: $(kernel_dir)/vmlinux | build
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
+$(top)/$(CONFIG_LINUXBOOT_KERNEL): build
+	@echo "    CP         bzImage"
+	cp $(kernel_dir)/arch/x86/boot/bzImage $@
+else
+ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
+$(project_dir)/target.dtb: $(top)/$(CONFIG_LINUXBOOT_DTB_FILE)
+	cp $< $@
+$(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux
 	$(OBJCOPY) -O binary $< $@
-
+$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
-build/vmlinux.bin.lzma: build/vmlinux.bin
 	xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@
+$(top)/$(CONFIG_LINUXBOOT_KERNEL): build $(project_dir)/vmlinux.bin.lzma $(project_dir)/target.dtb
+	cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
+	cp $(top)/$(CONFIG_LINUXBOOT_INITRAMFS)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $(project_dir)/initramfs
+	mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
+else
+	$(error Kernel image format not found)
+	exit 1
+endif
+endif
 
-$(kernel_dir)/arch/x86/boot/bzImage: $(kernel_dir)/.config
+ifneq ($(TAG-y),)
-	@echo "    MAKE       Linux $(kernel_version)"
+kernel: lookup $(top)/$(CONFIG_LINUXBOOT_KERNEL)
-	echo "$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) bzImage"
+else
-	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) bzImage
+kernel: $(top)/$(CONFIG_LINUXBOOT_KERNEL)
+endif
 
-.PHONY: kernel
+.PHONY: all kernel build unpack fetch check

payloads/external/LinuxBoot/targets/u-root.mk

@@ -1,26 +1,29 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-uroot_package = github.com/u-root/u-root
+project_dir=$(shell pwd)/linuxboot
-uroot_build = build/go/src/$(uroot_package)
+go_path_dir=$(project_dir)/go
+uroot_bin=$(project_dir)/u-root
+uroot_package=github.com/u-root/u-root
 
-UROOT_ARCH-$(CONFIG_LIBUXBOOT_X86_64)      = amd64
+ARCH-$(CONFIG_LIBUXBOOT_X86_64)=amd64
-UROOT_ARCH-$(CONFIG_LINUXBOOT_X86)         = 386
+ARCH-$(CONFIG_LINUXBOOT_X86)=i386
-UROOT_ARCH-$(CONFIG_LINUXBOOT_ARM64)       = arm64
+ARCH-$(CONFIG_LINUXBOOT_ARM64)=arm64
-UROOT_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64)  = riscv64
 
-go_version = $(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
+go_version=$(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
-go_version_major = $(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
+go_version_major=$(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
-go_version_minor = $(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')
+go_version_minor=$(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')
 
-uroot_args += -build=$(CONFIG_LINUXBOOT_UROOT_FORMAT)
+uroot_args+=-build=$(CONFIG_LINUXBOOT_UROOT_FORMAT)
-uroot_args += -initcmd $(CONFIG_LINUXBOOT_UROOT_INITCMD)
+uroot_args+=-initcmd $(CONFIG_LINUXBOOT_UROOT_INITCMD)
-uroot_args += -uinitcmd=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)
+uroot_args+=-uinitcmd=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)
-uroot_args += -defaultsh $(CONFIG_LINUXBOOT_UROOT_SHELL)
+uroot_args+=-defaultsh $(CONFIG_LINUXBOOT_UROOT_SHELL)
 ifneq (CONFIG_LINUXBOOT_UROOT_FILES,)
-uroot_args += $(foreach file,$(CONFIG_LINUXBOOT_UROOT_FILES),-files $(PWD)/$(file))
+uroot_args+=$(foreach file,$(CONFIG_LINUXBOOT_UROOT_FILES),-files $(PWD)/$(file))
 endif
 
-uroot_cmds = $(CONFIG_LINUXBOOT_UROOT_COMMANDS)
+uroot_cmds=$(CONFIG_LINUXBOOT_UROOT_COMMANDS)
+
+all: u-root
 
 version:
 ifeq ("$(go_version)","")
@@ -35,16 +38,27 @@ ifeq ($(shell if [ $(go_version_minor) -lt 9 ]; then echo y; fi),y)
 endif
 endif
 
-$(uroot_build):
+get: version
-	git clone https://$(uroot_package) $(uroot_build)
+	if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \
-	git -C $(uroot_build) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
+	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet main; \
+	git -C $(go_path_dir)/src/$(uroot_package) pull || \
+	echo -e "\n<<Pulling u-root package from GitHub failed>>\n"; \
+	else \
+	git clone https://${uroot_package} ${go_path_dir}/src/${uroot_package} || \
+	(echo -e "\n<<Failed to clone u-root package. Please check your internet access>>\n" && \
+	exit 1); \
+	fi
 
-$(uroot_build)/u-root: $(uroot_build)
+checkout: get
-	cd $(uroot_build); \
+	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
-	go build -o u-root .
 
-#$(CONFIG_LINUXBOOT_INITRAMFS_PATH)
+build: checkout
-build/initramfs_u-root.cpio: $(uroot_build)/u-root
+	cd ${go_path_dir}/src/${uroot_package}; \
-	GOARCH=$(UROOT_ARCH-y) $(uroot_build)/u-root \
+	go build -o ${uroot_bin} .
-	-uroot-source $(uroot_build) \
+
-	$(uroot_args) -o build/initramfs_u-root.cpio $(uroot_cmds)
+u-root: build
+	GOARCH=$(ARCH-y) $(uroot_bin) \
+	-uroot-source ${go_path_dir}/src/${uroot_package} \
+	$(uroot_args) -o $(project_dir)/initramfs_u-root.cpio $(uroot_cmds)
+
+.PHONY: all u-root build checkout get version

payloads/external/Makefile.inc

@@ -24,10 +24,10 @@ ifeq ($(CONFIG_PAYLOAD_LINUX)$(CONFIG_PAYLOAD_LINUXBOOT),y)
 ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
       ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE)
 endif
-ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH))),)
+ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
 ifneq ($(CONFIG_LINUXBOOT_ARM64),y)
-      ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_PATH)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
+      ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
-      prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS)))
+      prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)))
 endif
 endif
 endif
@@ -161,7 +161,6 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
 		CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
 		CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
-		CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
 		CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
 		CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
 		CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
@@ -185,14 +184,9 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
 		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
-		CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=$(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS) \
 		CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
-		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \
+		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
 		CONFIG_EDK2_SECURE_BOOT_SUPPORT=$(CONFIG_EDK2_SECURE_BOOT_SUPPORT) \
-		CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \
-		CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \
-		CONFIG_INTEL_GMA_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \
-		CONFIG_TPM_GOOGLE_CR50=$(CONFIG_TPM_GOOGLE_CR50) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -210,7 +204,6 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
 		CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
 		CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
 		CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
-		CONFIG_EDK2_UNIVERSAL_PAYLOAD=$(CONFIG_EDK2_UNIVERSAL_PAYLOAD) \
 		CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
 		CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
 		CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
@@ -233,7 +226,7 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
 		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
 		CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
-		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \
+		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -304,14 +297,8 @@ img/tint-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 # Memtest86+
 
-ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
-memtest_dir:=memtest86plus_v6
-else
-memtest_dir:=memtest86plus_v5
-endif
-
 cbfs-files-$(CONFIG_MEMTEST_SECONDARY_PAYLOAD) += img/memtest
-img/memtest-file := payloads/external/Memtest86Plus/$(memtest_dir)/memtest
+img/memtest-file := payloads/external/Memtest86Plus/memtest86plus/memtest
 img/memtest-type := payload
 img/memtest-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
@@ -321,7 +308,7 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy)
 		SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD)
 endif
 
-payloads/external/Memtest86Plus/$(memtest_dir)/memtest: $(DOTCONFIG)
+payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/Memtest86Plus all \
 		CC="$(CC_x86_32)" \
 		LD="$(LD_x86_32)" \
@@ -329,10 +316,8 @@ payloads/external/Memtest86Plus/$(memtest_dir)/memtest: $(DOTCONFIG)
 		AS="$(AS_x86_32)" \
 		CONFIG_MEMTEST_REVISION=$(CONFIG_MEMTEST_REVISION) \
 		CONFIG_MEMTEST_REVISION_ID=$(CONFIG_MEMTEST_REVISION_ID) \
-		CONFIG_MEMTEST_MAIN=$(CONFIG_MEMTEST_MAIN) \
+		CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
 		CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
-		CONFIG_MEMTEST86PLUS_V5=$(CONFIG_MEMTEST86PLUS_V5) \
-		CONFIG_MEMTEST86PLUS_V6=$(CONFIG_MEMTEST86PLUS_V6) \
 		$(MEMTEST_SERIAL_OPTIONS) \
 		MFLAGS= MAKEFLAGS=
 
@@ -379,45 +364,41 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT)
 	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86)        = x86_32
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86_64)     = x86_64
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM)        = arm
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_ARM64)      = arm64
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV32) = riscv
-LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_RISCV_RV64) = riscv
-ifeq ($(CONFIG_LINUXBOOT_CROSS_COMPILE),"")
-	CONFIG_LINUXBOOT_CROSS_COMPILE=$(CROSS_COMPILE_$(LINUXBOOT_CROSS_COMPILE_ARCH-y))
-endif
 .PHONY: linuxboot
-payloads/external/LinuxBoot/build/Image linuxboot:
+linuxboot:
 	$(MAKE) -C payloads/external/LinuxBoot \
 		CPUS=$(CPUS) \
 		CONFIG_LINUXBOOT_X86_64=$(CONFIG_LINUXBOOT_X86_64) \
 		CONFIG_LINUXBOOT_X86=$(CONFIG_LINUXBOOT_X86) \
-		CONFIG_LINUXBOOT_ARM=$(CONFIG_LINUXBOOT_ARM) \
 		CONFIG_LINUXBOOT_ARM64=$(CONFIG_LINUXBOOT_ARM64) \
-		CONFIG_LINUXBOOT_RISCV_RV32=$(CONFIG_LINUXBOOT_RISCV_RV32) \
+		CONFIG_LINUXBOOT_KERNEL=$(CONFIG_PAYLOAD_FILE) \
-		CONFIG_LINUXBOOT_RISCV_RV64=$(CONFIG_LINUXBOOT_RISCV_RV64) \
+		CONFIG_LINUXBOOT_INITRAMFS=$(CONFIG_LINUX_INITRD) \
-		CONFIG_LINUXBOOT_CROSS_COMPILE=$(CONFIG_LINUXBOOT_CROSS_COMPILE) \
-		CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \
-		CONFIG_LINUXBOOT_INITRAMFS_PATH=$(CONFIG_LINUXBOOT_INITRAMFS_PATH) \
 		CONFIG_LINUXBOOT_INITRAMFS_SUFFIX=$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) \
-		CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \
 		CONFIG_LINUXBOOT_COMPILE_KERNEL=$(CONFIG_LINUXBOOT_COMPILE_KERNEL) \
-		CONFIG_LINUXBOOT_KERNEL_PATH=$(CONFIG_LINUXBOOT_KERNEL_PATH) \
+		CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \
-		CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
+		CONFIG_LINUXBOOT_KERNEL_MAINLINE=$(CONFIG_LINUXBOOT_KERNEL_MAINLINE) \
+		CONFIG_LINUXBOOT_KERNEL_STABLE=$(CONFIG_LINUXBOOT_KERNEL_STABLE) \
+		CONFIG_LINUXBOOT_KERNEL_LONGTERM=$(CONFIG_LINUXBOOT_KERNEL_LONGTERM) \
+		CONFIG_LINUXBOOT_KERNEL_CUSTOM=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM) \
+		CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) \
+		CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG) \
 		CONFIG_LINUXBOOT_KERNEL_BZIMAGE=$(CONFIG_LINUXBOOT_KERNEL_BZIMAGE) \
 		CONFIG_LINUXBOOT_KERNEL_UIMAGE=$(CONFIG_LINUXBOOT_KERNEL_UIMAGE) \
 		CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
+		CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \
 		CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
 		CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
 		CONFIG_LINUXBOOT_UROOT_FORMAT=$(CONFIG_LINUXBOOT_UROOT_FORMAT) \
 		CONFIG_LINUXBOOT_UROOT_INITCMD=$(CONFIG_LINUXBOOT_UROOT_INITCMD) \
-		CONFIG_LINUXBOOT_UROOT_UINITCMD=$(CONFIG_LINUXBOOT_UROOT_UINITCMD) \
+		CONFIG_LINUXBOOT_UROOT_UINITCMD=$(CONFIG_LINUXBOOT_UROOT_UINITCMD)\
 		CONFIG_LINUXBOOT_UROOT_SHELL=$(CONFIG_LINUXBOOT_UROOT_SHELL) \
 		CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \
 		CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
-		CONFIG_LINUXBOOT_DTS_FILE=$(CONFIG_LINUXBOOT_DTS_FILE)
+		CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE)
+
+payloads/external/LinuxBoot/linuxboot/bzImage: linuxboot
+payloads/external/LinuxBoot/linuxboot/uImage: linuxboot
+payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio: linuxboot
 
 # BOOTBOOT
 

payloads/external/Memtest86Plus/Kconfig.secondary

@@ -1,32 +1,8 @@
 if MEMTEST_SECONDARY_PAYLOAD
 
-comment "Memtest86+"
-
 choice
-	prompt "Memtest86+ 5/6"
+	prompt "Memtest86+ version"
-
+	default MEMTEST_STABLE
-config MEMTEST86PLUS_V6
-	bool "Memtest86+ V6"
-
-config MEMTEST86PLUS_V5
-	bool "Memtest86+ V5"
-
-endchoice
-
-choice
-	prompt "Target architecture"
-	depends on MEMTEST86PLUS_V6
-
-config MEMTEST86PLUS_ARCH_64
-	bool "64 bit"
-
-config MEMTEST86PLUS_ARCH_32
-	bool "32 bit"
-
-endchoice
-
-choice
-	prompt "Memtest86+ revision"
 	depends on MEMTEST_SECONDARY_PAYLOAD
 
 config MEMTEST_STABLE
@@ -35,21 +11,20 @@ config MEMTEST_STABLE
 	  Stable Memtest86+ version.
 
 	  For reproducible builds, this option must be selected.
-config MEMTEST_MAIN
+config MEMTEST_MASTER
-	bool "Main"
+	bool "Master"
 	help
 	  Newest Memtest86+ version.
 
 	  This option will fetch the newest version of the Memtest86+ code,
 	  updating as new changes are committed.  This makes the build
 	  non-reproducible, as it can fetch different code each time.
-
 config MEMTEST_REVISION
 	bool "git revision"
 	help
 	  Select this option if you have a specific commit or branch
 	  that you want to use as the revision from which to
-	  build Memtest86+. Using a branch version makes the build
+	  build Memtest86+.  This makes the build
 	  non-reproducible, as it can fetch different code each time.
 
 	  You will be able to specify the name of a branch or a commit id
@@ -60,7 +35,7 @@ endchoice
 config MEMTEST_REVISION_ID
 	string "Insert a commit's SHA-1 or a branch name"
 	depends on MEMTEST_REVISION
-	default "origin/main"
+	default "origin/master"
 	help
 	   The commit's SHA-1 or branch name of the revision to use.
 

payloads/external/Memtest86Plus/Makefile

@@ -1,32 +1,14 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-project_name=Memtest86+
+TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
-
+NAME-$(CONFIG_MEMTEST_MASTER)=Master
-ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
-project_dir=$(CURDIR)/memtest86plus_v6
-
-ifeq ($(MEMTEST86PLUS_ARCH_64),y)
-build_dir=$(project_dir)/build64
-else
-build_dir=$(project_dir)/build32
-endif
-project_git_repo=https://github.com/memtest86plus/memtest86plus.git
-TAG-$(CONFIG_MEMTEST_MAIN)=origin/main
-NAME-$(CONFIG_MEMTEST_MAIN)=Main
-TAG-$(CONFIG_MEMTEST_STABLE)=v6.20
-NAME-$(CONFIG_MEMTEST_STABLE)=Stable
-TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
-else
-project_dir=$(CURDIR)/memtest86plus_v5
-
-build_dir=$(project_dir)
-project_git_repo=https://review.coreboot.org/memtest86plus.git
-TAG-$(CONFIG_MEMTEST_MAIN)=origin/main
-NAME-$(CONFIG_MEMTEST_MAIN)=Main
 TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753
 NAME-$(CONFIG_MEMTEST_STABLE)=Stable
 TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
-endif
+
+project_name=Memtest86+
+project_dir=$(CURDIR)/memtest86plus
+project_git_repo=https://review.coreboot.org/memtest86plus.git
 
 all: build
 
@@ -43,27 +25,24 @@ ifeq ($(CONFIG_MEMTEST_REVISION),y)
 endif
 	false
 endif
-	-cd $(project_dir) 2>/dev/null; git show $(TAG-y) >/dev/null 2>&1 ; \
+	-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
-		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/main" ]; then \
+		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
 		echo "    Fetching new commits from the $(project_name) git repo"; \
 		git fetch; fi
 
 checkout: fetch
 	echo "    Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
 	cd $(project_dir); \
-		git checkout main; \
+		git checkout master; \
 		git branch -D coreboot 2>/dev/null; \
 		git checkout -b coreboot $(TAG-y)
 
 build: checkout
 	echo "    MAKE       $(project_name) $(NAME-y)"
-	$(MAKE) -C $(build_dir) all
+	$(MAKE) -C $(project_dir) all
-ifeq ($(CONFIG_MEMTEST86PLUS_V6),y)
-	cp $(build_dir)/memtest.bin $(project_dir)/memtest
-endif
 
 clean:
-	test -d $(build_dir) && $(MAKE) -C $(build_dir) clean || exit 0
+	test -d $(project_dir) && $(MAKE) -C $(project_dir) clean || exit 0
 
 distclean:
 	rm -rf $(project_dir)
@@ -71,4 +50,4 @@ distclean:
 print-repo-info:
 	echo "$(project_git_repo) $(project_dir)"
 
-.PHONY: all build checkout check_version clean distclean fetch print-repo-info
+.PHONY: all build checkout clean distclean fetch print-repo-info

payloads/external/SeaBIOS/Kconfig

@@ -15,7 +15,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.16.2"
+	bool "1.16.1"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

payloads/external/SeaBIOS/Makefile

@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=ea1b7a0733906b8425d948ae94fba63c32b1d425
+TAG-$(CONFIG_SEABIOS_STABLE)=3208b098f51a9ef96d0dfa71d5ec3a3eaec88f0a
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://review.coreboot.org/seabios.git

payloads/external/U-Boot/Kconfig

@@ -7,14 +7,14 @@ config PAYLOAD_SPECIFIC_OPTIONS
 
 config UBOOT_STABLE_COMMIT_ID
 	string
-	default "v2023.07"
+	default "v2021.07"
 
 choice
 	prompt "U-Boot version"
 	default UBOOT_STABLE
 
 config UBOOT_STABLE
-	bool "v2023.07"
+	bool "v2021.07"
 	help
 	  Stable U-Boot version
 

payloads/external/U-Boot/Kconfig.name

@@ -1,5 +1,5 @@
 config PAYLOAD_UBOOT
-	bool "U-Boot"
+	bool "U-Boot (Experimental)"
 	depends on ARCH_X86
 	help
 	  Select this option if you want to build a coreboot image

payloads/external/U-Boot/Makefile

@@ -5,7 +5,7 @@ TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
 
 project_name=U-Boot
 project_dir=u-boot
-project_git_repo=http://github.com/u-boot/u-boot/
+project_git_repo=http://git.denx.de/u-boot.git
 project_build_dir=build
 project_config_file=$(project_build_dir)/.config
 

payloads/external/depthcharge/Makefile

@@ -1,5 +1,5 @@
-# 2023-05-10
+# Wed Apr 25, 2018
-STABLE_COMMIT_ID=c48613a71c1ee29295b184c51fe5dadf71b543c4
+STABLE_COMMIT_ID=902681db13c170fc2d028f7391a9e9a5f69082a3
 
 project_name=depthcharge
 project_dir=$(CURDIR)/depthcharge

payloads/external/edk2/Kconfig

@@ -3,42 +3,15 @@ if PAYLOAD_EDK2
 config PAYLOAD_FILE
 	string "edk2 binary"
 	default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD
-	default "$(obj)/ShimmedUniversalPayload.elf" if EDK2_UNIVERSAL_PAYLOAD
 	help
 	  The result of a UefiPayloadPkg build
 
-choice
-	prompt "EDK II build type"
-	default EDK2_UEFIPAYLOAD
-	help
-	  Select the build type for edk2. UniversalPayload is recommended, as it is
-	  replacing UefiPayloadPkg. Whilst in the transition phase between the two,
-	  both options exist.
-
 config EDK2_UEFIPAYLOAD
 	bool "Build UefiPayloadPkg"
+	default y
 	help
 	  Build the standard UefiPayloadPkg
 
-config EDK2_UNIVERSAL_PAYLOAD
-	bool "Build Universal Payload"
-	help
-	  Select this option if you want to build a coreboot image
-	  with EDK2s Universal Payload. If you don't know what this is
-	  about, just leave it enabled.
-
-	  Universal Payload should ideally only be built from upstream EDK2,
-	  https://github.com/tianocore/edk2, as this is regularly build tested
-	  and it encourages patches to be merged upstream.
-
-	  Whilst the required patches are being merged, this is pointed to
-	  Star Labs GitHub repository which contains these patches and is based
-	  on a known working commit.
-
-	  See https://universalscalablefirmware.github.io/documentation/ for more information.
-
-endchoice
-
 choice
 	prompt "Tianocore's EDK II payload"
 	default EDK2_REPO_MRCHROMEBOX
@@ -71,7 +44,6 @@ endchoice
 
 config EDK2_REPOSITORY
 	string "URL to git repository for edk2"
-	default "https://github.com/starlabsltd/edk2" if EDK2_UNIVERSAL_PAYLOAD
 	default "https://github.com/mrchromebox/edk2" if EDK2_REPO_MRCHROMEBOX
 	default "https://github.com/tianocore/edk2" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM
@@ -81,8 +53,7 @@ config EDK2_REPOSITORY
 
 config EDK2_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202306" if EDK2_REPO_MRCHROMEBOX
+	default "origin/uefipayload_202304" if EDK2_REPO_MRCHROMEBOX
-	default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD
 	default "origin/master" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM
 	help
@@ -262,20 +233,6 @@ config EDK2_SECURE_BOOT_SUPPORT
 	  Select this option to enable UEFI SecureBoot support in edk2.
 	  UEFI SecureBoot will be disabled by default and can be enabled from the menu option.
 
-config EDK2_GOP_DRIVER
-	bool "Add a GOP driver to the Tianocore build"
-	depends on INTEL_GMA_ADD_VBT && NO_GFX_INIT && (EDK2_REPO_MRCHROMEBOX || EDK2_REPO_CUSTOM)
-	default y if INTEL_GMA_ADD_VBT && NO_GFX_INIT && EDK2_REPO_MRCHROMEBOX
-	help
-	  Select this option to have edk2 use an external GOP driver for display init.
-
-config EDK2_GOP_FILE
-	string "GOP driver file"
-	depends on EDK2_GOP_DRIVER
-	default "IntelGopDriver.efi"
-	help
-	  The name of the GOP driver file passed to edk2.
-
 config EDK2_CUSTOM_BUILD_PARAMS
 	string "edk2 additional custom build parameters"
 	default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2

payloads/external/edk2/Makefile

@@ -71,10 +71,6 @@ endif
 ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y)
 BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
 endif
-# MAX_VARIABLE_SIZE		= 0x10000
-ifeq ($(CONFIG_SMMSTORE_V2),y)
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize=0x8000
-endif
 # PCIE_BASE_ADDRESS		= 0
 ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
 BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
@@ -115,14 +111,6 @@ endif
 ifeq ($(CONFIG_EDK2_SECURE_BOOT_SUPPORT), y)
 BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE
 endif
-# PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE
-ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y)
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE
-endif
-# GOP_DRIVER			= FALSE
-ifeq ($(CONFIG_EDK2_GOP_DRIVER), y)
-BUILD_STR += -D USE_PLATFORM_GOP=TRUE
-endif
 
 #
 # EDKII has the below PCDs that are relevant to coreboot:
@@ -135,10 +123,6 @@ BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
 endif
 
-ifeq ($(CONFIG_TPM_GOOGLE_CR50)$(CONFIG_EDK2_REPO_MRCHROMEBOX),yy)
-BUILD_STR += -D TPM_ENABLE=FALSE
-endif
-
 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
 
 ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)
@@ -199,13 +183,6 @@ logo: $(EDK2_PATH)
 			BMP3:$(EDK2_PATH)/MdeModulePkg/Logo/Logo.bmp;; \
 	esac \
 
-gop_driver:
-	if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \
-		echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \
-		cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \
-		cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \
-	fi; \
-
 checktools:
 	echo -n "EDK2: Checking uuid-dev:"
 	echo "#include <uuid/uuid.h>" > libtest.c
@@ -243,7 +220,7 @@ print:
 		-e 's/s /Build:          Silent/' \
 		-e 's/t /Toolchain:      /'
 
-prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver
+prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
 		unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \
@@ -270,7 +247,7 @@ $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
 		echo -n "EDK2: Building... "; \
-		$(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR)
+		$(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR)
 		if [ ! -f $@ ]; then \
 			echo "Failed!"; \
 			exit 1; \

payloads/external/tint/Makefile

@@ -6,11 +6,12 @@
 # Properties of the current TINT version
 #
 
-TINT_VERSION=0.07
+TINT_VERSION=0.05
-TINT_BASE_URL="https://mirror.fsf.org/trisquel/pool/main/t/tint"
+TINT_EXT_VERSION=0.05
+TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.tar.xz"
 TINT_ARCHIVE="tint_${TINT_VERSION}.tar.xz"
 TINT_DIR="tint-${TINT_VERSION}"
-TINT_SHA1SUM="a7ec9355b9ea9d47576757219e9b1f4e51ac93a7"
+TINT_SHA1SUM="859008216930a4584e622d0df41fd75c44d2b47f"
 
 #
 # Locations of the input/output scripts
@@ -49,7 +50,7 @@ tint:
 		"./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \
 		chmod +x "./tintify_core.sh" ; \
 		"./tintify_core.sh" ${corescript} ${tintified} \
-			${TINT_BASE_URL} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_SHA1SUM} ; \
+			${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_SHA1SUM} ; \
 	fi ; \
 	chmod +x ${tintified}
 	${tintified}

payloads/external/tint/generate_core.sh

@@ -97,7 +97,6 @@ sed -i -e "s/util\/crossgcc\///g" "$corescript"
 
 if [ ! -z "${prepare_before_patch}" ] ; then
 	sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript"
-	sed -i -e "/\$TAR \$FLAGS \"\$archive\"/a prepare_\${package} || exit \"\$?\"" "$corescript"
 fi
 
 #

payloads/external/tint/tintify_core.sh

@@ -9,7 +9,7 @@
 #
 # USAGE:
 #      	./tintify_core.sh <corescript> <tintified> \
-# 			<TINT_BASE_URL> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM>
+# 			<TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM>
 # where
 #       corescript - path to input core script
 #       tintified  - path to output tint script
@@ -28,12 +28,10 @@ tintified="$2"
 #
 
 echo "#!/bin/sh" > "$tintified"
-echo "TINT_BASE_URL=${3}" >> "$tintified"
+echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified"
 echo "TINT_ARCHIVE=${4}" >> "$tintified"
-echo "TINT_ARCHIVE_LINK=${3}/${4}" >> "$tintified"
 echo "TINT_DIR=${5}" >> "$tintified"
 echo "TINT_SHA1SUM=${6}" >> "$tintified"
-echo "USE_COREBOOT_MIRROR=0" >> "$tintified"
 
 #
 # Add the replace_plus_with_minus() function - needed to fix the version number

payloads/libpayload/Kconfig

@@ -167,6 +167,14 @@ config BASE_ADDRESS
 
 endmenu
 
+config USE_MARCH_586
+	bool "Use march=586 qualifier to build"
+	default n
+	depends on ARCH_X86
+	help
+	  Allow a platform or processor to select to be compiled using
+	  the '-march=i586' option instead of the typical '-march=i686'
+
 menu "Standard Libraries"
 
 config LIBC

payloads/libpayload/arch/arm/Kconfig

@@ -26,5 +26,10 @@
 ## SUCH DAMAGE.
 ##
 
-config ARCH_ARM
+if ARCH_ARM
+
+config ARCH_SPECIFIC_OPTIONS
+	def_bool y
 	select LITTLE_ENDIAN
+
+endif

payloads/libpayload/arch/arm/main.c

@@ -29,6 +29,11 @@
 #include <exception.h>
 #include <libpayload.h>
 
+int main_argc;    /**< The argc value to pass to main() */
+
+/** The argv value to pass to main() */
+char *main_argv[MAX_ARGC_COUNT];
+
 /**
  * This is our C entry function - set up the system
  * and jump into the payload entry point.
@@ -58,7 +63,7 @@ void start_main(void)
 	 * In the future we may care about the return value.
 	 */
 
-	(void) main(0, NULL);
+	(void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
 
 	/*
 	 * Returning here will go to the _leave function to return

payloads/libpayload/arch/arm64/Kconfig

@@ -26,11 +26,12 @@
 ## SUCH DAMAGE.
 ##
 
-config ARCH_ARM64
-	select LITTLE_ENDIAN
-
 if ARCH_ARM64
 
+config ARCH_SPECIFIC_OPTIONS
+	def_bool y
+	select LITTLE_ENDIAN
+
 config ARM64_A53_ERRATUM_843419
 	bool "Enable Cortex-A53 erratum 843419 linker workaround"
 	default n

payloads/libpayload/arch/arm64/main.c

@@ -30,6 +30,11 @@
 #include <libpayload.h>
 #include <arch/mmu.h>
 
+int main_argc;    /**< The argc value to pass to main() */
+
+/** The argv value to pass to main() */
+char *main_argv[MAX_ARGC_COUNT];
+
 /*
  * Func: pre_sysinfo_scan_mmu_setup
  * Desc: We need to setup and enable MMU before we can go to scan coreboot
@@ -120,7 +125,7 @@ void start_main(void)
 	 * In the future we may care about the return value.
 	 */
 
-	(void) main(0, NULL);
+	(void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
 
 	/*
 	 * Returning here will go to the _leave function to return

payloads/libpayload/arch/mock/Kconfig

@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-config ARCH_MOCK
-	select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN
-	select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN
-
 if ARCH_MOCK
 
 config ARCH_MOCK_BIG_ENDIAN
@@ -12,4 +8,9 @@ config ARCH_MOCK_BIG_ENDIAN
 	help
 	  This option enables big-endinan support in the code.
 
+config ARCH_SPECIFIC_OPTIONS
+	def_bool y
+	select LITTLE_ENDIAN if !ARCH_MOCK_BIG_ENDIAN
+	select BIG_ENDIAN if ARCH_MOCK_BIG_ENDIAN
+
 endif

payloads/libpayload/arch/x86/Kconfig

@@ -26,12 +26,13 @@
 ## SUCH DAMAGE.
 ##
 
-config ARCH_X86
+if ARCH_X86
+
+config ARCH_SPECIFIC_OPTIONS
+	def_bool y
 	select LITTLE_ENDIAN
 	select IO_ADDRESS_SPACE
 
-if ARCH_X86
-
 config ENABLE_APIC
 	bool "Enables the Local APIC"