To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:348345301
BRANCH=firmware-rex-15709.B
TEST=BRDS method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the configuration of 320MHz Bandwidth per MCC based on
countries. The implementation follows document #559910 Intel
Connectivity Platforms BIOS Guidelines revision 8.3.
BUG=b:333804562
BRANCH=firmware-rex-15709.B
TEST=WBEM method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides
ability to utilize increased device Transmit power capability for
Bluetooth applications in coordination with Wi-Fi adhering to product
SAR limit when Bluetooth and Wi-Fi run together.
This commit introduces a `bluetooth_companion' field to the generic
Wi-Fi drivers chip data. This field can be set in the board design
device tree to supply the bluetooth device for which the BRDS function
must be created.
This feature is required for Meteor Lake rex karis variant.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:348345301
BRANCH=firmware-rex-15709.B
TEST=BRDS method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM!
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- both RJ-45 Gigabit LAN Ports
- USB 2.0 Ports
- USB 3.1 Gen1 Ports
- both USB 3.1 Gen1 headers
- HD Audio Jack (audio output)
- all six SATA3 6.0 Gb/s connectors by Intel
- all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061
- all three PCI Express 3.0 x16 slots
- PCI Express 2.0 x1 slot
- half mini-PCI Express slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection via jumper
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
not (yet) working:
- Front panel audio connector
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config
GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG,
we remove GERALT_USE_MAX98390 from Kconfig.
BUG=b:345629159
BRANCH=none
TEST=emerge-GERALT coreboot
TEST=Verify beep function through deploy in depthcharge successfully.
Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Fast boot will used pre-saved hardware configuration data to
accelerate the boot process, e.g. DDR training is skipped by using
pre-saved training data. Enable fast boot on cold and warm resets
by default.
Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
If BMP_LOGO is set, currently display_init_required() will always return
1, so that platform code will always initialize display. However, that
information isn't passed to vboot, which may result in unnecessary extra
reboots, for example when the payload needs to request display init (by
vb2api_need_reboot_for_display()).
Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to
tell vboot that "display is available on this boot", enable it by
default if BMP_LOGO is set.
BUG=b:345085042
TEST=none
BRANCH=none
Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Working:
- Both DIMM slots
- All Rear USB 2.0 ports
- Integrated graphics (libgfxinit)
- Realtek RTL8111F GbE
- Flashing internally with flashrom (Note: Works from stock too
due to Gigabyte not following Intel recommendations,
confusing ME)
- SeaBIOS (1.16.3) to boot Arch Linux Installer
- EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
- Audio output (green jack, rear)
- S3 suspend/resume
- VBT
Untested for now (i.e. should work, will eventually test):
- EHCI debug
- Front USB 2.0 ports
- The other audio jacks
- PCIe ports
- Non-Linux OSes
Untestable (i.e. cannot test due to unavailable hardware):
- PS/2 port
- Serial port
- SATA ports
Not working:
- USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
so its firmware needs to be loaded on each boot. However,
documentation about the (chip-specific) firmware loading procedure
is nowhere to be found.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <me@pugzarecute.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This change skips the ME firmware version logging in
print_me_fw_version() if the ME firmware SKU is detected as Lite SKU.
The reasoning is that the RO (BP1) and RW (BP2) versions are already
logged by the cse_print_boot_partition_info() function for Lite SKUs,
making the additional log redundant.
The check for the Lite SKU has been moved to print_me_fw_version(),
where the decision to print the version is made, instead of in
get_me_fw_version(), where the version information is retrieved.
TEST=Able to build and boot google/rex.
w/o this patch:
[DEBUG] ME: Version: Unavailable
w/ this patch:
Unable to see such debug msg.
Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This change modifies the get_me_fw_version() function to be statically
scoped within src/soc/intel/common/block/cse/cse.c, as it is only used
by the print_me_fw_version() function in the same file.
The function declaration is also removed from intelblocks/cse.h.
The order of the function definitions in cse.c was also changed to be
more logical, with the now static helper function get_me_fw_version()
defined first, before it is used.
TEST=Able to build google/rex.
Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the ME status reporting functionality
(dump_me_status, print_me_fw_version) in the CSE driver when
SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined.
This is likely intended for platforms or configurations where the
CSE communication is only limited to payload.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I5e360408a7847968117df475ff244d79ceafa23f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch skips the ISH firmware version print when CSE sync is done
by payload. The payload is responsible to dump the ISH version as
ISH version resides into the CSE boot partition table.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch skips the CSE firmware version print when CSE sync is done
by payload. The payload is responsible to dump the CSE version.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Refactor CSE lite End-of-Post (EOP) configs to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE EOP operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_SEND_EOP_EARLY
- SOC_INTEL_CSE_SEND_EOP_LATE
- SOC_INTEL_CSE_SEND_EOP_ASYNC
- SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor CSE lite configs (specifically CSE sync related) to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE sync operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_LITE_PSR
- SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
- SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
- SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This reverts commit 6ab188ee6c99b1d9924b607d7e939d91e35014ec.
This breaks the build using a slightly older toolchain that doesn't know
this option yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bdc909c0e53b5353743dca521c963bbec792f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83311
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This double-colon target doesn't do anything unless it's implemented by
another makefile. It's intended to be used only by the site-local
makefile to allow it to run any necessary steps before the actual
coreboot build begins.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I01f98c9cf8375bca21ab87f9becf66a25402c758
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This port was done via autoport and subsequent manual tweaking.
Special thanks to Nicholas Chin! This port would have never succeeded
without his help.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection switch and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- USB 2.0 Ports
- Vertical Type A USB 2.0
- USB 3.1 Gen1 Ports
- HD Audio Jack (audio output)
- Front panel audio connector (audio output)
- RJ-45 Gigabit LAN Port
- SATA3 6.0 Gb/s connectors
- mSATA/mini-PCI Express slot
- half mini-PCI Express slot
- PCI Express 3.0 x16 slots (both)
- PCI Express 2.0 x4 slot
- PCI Express 2.0 x1 slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection Switch
- Slow Mode Switch (locks the CPU at 800MHz)
not (yet) tested:
- IR header
- COM Port header
- Power LED header
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- Optical SPDIF Out Port
not (yet) working:
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
- Post Status Checker (PSC)
Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Updating from commit id 09fcd218:
2024-02-23 06:42:12 +0000 - (Makefile: Test compiler for -Wincompatible-function-pointer-types)
to commit id b6f44e62:
2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10)
This brings in 58 new commits:
b6f44e62 futility: updater: Increase try count from 8 to 10
cfc87db2 OWNERS: Add czapiga
eabf5784 OWNERS: Remove twawrzynczak and quasisec
f8af818e host: Add stub implementation for pkcs11 key
aaf4ecbb crossystem: Add support for Panther Lake gpiochip
de89c5cd make_dev_ssd: allow ptracers to write proc/mem
ffc9cc15 utility: Add vbnv_util.py for debugging
b6174bdb futility: show: Print keyblock signature size and data size
6e39c99f Android: Add support for doing zipalign before doing apksigner
ead73381 futility: flash: Enhance WP status reporting by adding more instructions
c3368084 futility: modify private key validation to work for both local and cloud
c22d72f8 futility: flash: Correct the output syntax of 32bit hex
f423ae13 crossystem: Drop support for tried_fwb and fwb_tries
fc5488c7 futility: flash: Correct the allowlist of options
16dede85 Revert "futility: Split load_firmware_image() into two functions for AP and EC"
ded07831 futility: Try to load ecrw versions regardless of image type
7a685705 futility: Refactor code for --manifest
f5ad0856 futility: Add more checks for incompatible arguments
05659d33 futility/updater_manifest: Warn about inconsistent RW versions
6720827b futility: Support ecrw version for --manifest
daae7e56 futility: Split load_firmware_image() into two functions for AP and EC
40c77bba futility: Warn about inconsistent RW_FWID_A and RW_FWID_B versions
c168ac8e tests/futility/data: Update bios_geralt_cbfs.bin with swapped ecrw
512648ae host/lib: Add cbfstool_file_exists() and cbfstool_extract()
e37e6511 sign_official_build: add missing info keyword
2c0758b4 sign_official_build: loem support for firmware
016f6149 scripts/image_signing/swap_ec_rw: Always add ecrw.* as raw CBFS file
b26c700a scripts/image_signing/swap_ecrw: Support ecrw.version
2e8d1003 tlcl: Add const qualifier to TlclTakeOwnership arguments
96b8674c host: stop installing unused image signing scripts
8da83c43 Android: Handle update certs using for hardcoded certs
4ca60534 scripts/image_signing: Add swap_ec_rw
d30d6b54 make_dev_ssd: Remove logic choosing editor value
4cc5d090 futility/dump_fmap: Fix error message prefix for '-x'
e7062a58 futility/dump_fmap: Exit with error if specified section is not found
4489dd09 scripts: Remove newbitmaps directory
8dcc82b0 host/lib/cbfstool: Redesign cbfstool_get_config_value() API
856fd693 Android: Hack for now to let things silently fail instead of erroring
28845c97 sign_uefi: Handle case where the crdyshim key does not exist
201244c3 sign_uefi_unittest: Refactor in preparation for more tests
702f8b53 tests: Add tests for cbfstool_get_config_value()
52a21327 Android: Add support for gcloud KMS in android signing
3310c49f tests/futility/test_update.sh: Use unique test names for IFD tests
493f7afc sign_gsc_firmware: add support for Nightly target
5c307cad keycfg: more consistent typo fix
11e4f60b image_signing: Add missing arg in sign_uefi_kernel
37c730d8 keycfg: handle arrays appropriately in key_config
59c37697 sign_uefi: Add detached crdyboot signature
b66926e2 sign_uefi: Refactor the is-pkcs11 function for reuse
94aa8b80 image_signing: Pass crdyshim private key to sign_uefi.py
0ac99bcb sign_uefi: Stop signing crdyboot files with sbsign
6f6a6432 vboot_reference-sys: replace denylist with allowlist
73ebd8f8 vboot_reference-sys: add vboot_host pkg-config fallback
476282ef make_dev_ssd: Skip firmware validity checks on nonchrome
9330a65a vboot_reference: Add support for allowing overlayfs
48c8833f sign_official_build: remove cloud-signing
aa70bb19 create_new_keys.sh: add --arv-root-uri
38d1af69 sign_official_build: Dedup calls to sign_uefi.py
Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Ensure consistent spacing around colons in bit fields, operators,
statements and function calls.
Found by the linter (check-style).
Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Also capitalize the first letter of each help line while I'm here.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I595265d53a5ecfeb5989075dd4ce23dbdf366c00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This almost completely replaces the original clean-symlink target to
remove links from site-local into the coreboot tree. Changes include:
- Symbolic links removed are based on the EXTERNAL_SYMLINKS value of
symlink.txt files under site-local.
- Verify that there are site-local symlink.txt files to work on before
doing anything.
- Verify that the symlink.txt files reference links inside the coreboot
directory.
- Print out whether or not there are remaining symbolic links in the
tree.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ife0e7cf1b856b7394cd5e1de9b35856bd984663c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Define a devicetree alias for `cpu_cluster` so that it can be referenced
in C code as `DEV_PTR(cpu_bus)`.
Change-Id: Id6ead3d98d8fc17cab44ecf0b2af60a23187e036
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently the HiFive Unleashed produces the following exception:
[DEBUG] Exception: Load address misaligned
[DEBUG] Hart ID: 0
[DEBUG] Previous mode: machine
[DEBUG] Bad instruction pc: 0x080010d0
[DEBUG] Bad address: 0x08026ab3
[DEBUG] Stored ra: 0x080010c8
[DEBUG] Stored sp: 0x08010cc8
The coreboot LZ4 decompression code does some misaligned access during
decompression which the FU540 apparently does not support in SRAM.
Make the compiler generate code that adheres to natural alignment by
fixing the LZ4_readLE16() function and creating LZ4_readLE32().
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touchscreen vendor (Goodix) needs to use this value
(hid-report-addr) in the touch driver, and this value
needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table.
BUG=b:342932183
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add STA panel LCE_LMFBX101117480 serializable data to CBFS.
Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf
About the init code, we communicated with the vendor through the
datasheet to confirm the writing method of each register value.
BUG=b:331870701
TEST=build and check the CBFS includes the panel
BRANCH=None
Change-Id: I60858109e4b07f720461e320212d7b197ec1130c
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove
it to clean up a bit.
Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Use one line per *_common flag like it's done elsewhere in the tree.
It makes the list of options more readable.
Change-Id: I33c500e6eb74daf1e66c2b5e07b50f81c0f4587d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename fdt_node_name to the actual function name and also rename the
references.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I527146df26264a0c3af1ad01c21644d751b80236
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83084
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP
register is RO (Read Only). However, it is known that in some Intel
PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some
of the bitfields in the GCAP register are R/WO (Read / Write Once).
GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock
bit for GCAP elsewhere.
Lock GCAP by reading GCAP and writing back the same value. This has
no effect on platforms that implement GCAP as a RO register or lock
GCAP through a different mechanism.
Change-Id: Id61e6976a455273e8c681dbeb4bad35d57b1a8a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
vtd_probe_bar_size is used to decide the BAR size.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD
sizes larger than 4KB. If the value in the field is N, the size of
the register set is 2^N 4 KB pages.
Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying
to use the beyond 4KB part of the DRHD BAR if they exist. They need
the DRHD size field to set up page mapping before access those
registers.
Re-add acpi_create_dmar_drhd with a size parameter to support the
needs.
TEST=Build and boot on intel/archercity CRB
Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned
off, based on fw_config. Otherwise, when device boots without the cbi
settings for wifi6, boot may fail with assertion error for line 817 &
819 of file 'src/soc/intel/alderlake/fsp_params.c'.
BUG=b:345596420
BRANCH=NONE
TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along
with enumeration of corresponding BT device.
Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
