Commit Graph

47248 Commits

Author SHA1 Message Date
Jeremy Soller
6d20bf4a9f soc/intel/alderlake: Add SLP_S0 residency register and enable LPIT support
Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413
2022-05-27 12:54:34 -06:00
Jeremy Soller
d9a9796150 mb/system76/gaze17: Disable S3 suspend
Change-Id: I83a3932f1f7eee5680820882e9bce1a9a7b05e35
2022-05-27 12:54:34 -06:00
Jeremy Soller
221796fa23 mb/system76/gaze17: Enable ME by default
Change-Id: I6cb3adecfd9a808c9c6dcddedd906b208c5f56fb
2022-05-27 12:54:34 -06:00
Jeremy Soller
9798b1f3fd mb/system76/gaze17: Enable SATA DEVSLP
Change-Id: If7dfbf7816b0487fd03d11fbd60649de71b3e654
2022-05-27 12:54:34 -06:00
Tim Crawford
7d38db7d49 mb/system76/gaze17: WIP: S0ix
Change-Id: If03f92549ac76e2e0d04bdfe919048879b691f7d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-27 12:54:34 -06:00
Jeremy Soller
1522e01426 mb/system76/gaze17: Let FSP set TPM IRQ
Change-Id: If15cc71d808cb1327be68da203d4cc408143068e
2022-05-27 12:54:34 -06:00
Jeremy Soller
01e11ae288 mb/system76/gaze17: Add pin muxing
Change-Id: I82b94c0e30471af65b0a6e58001c18edfe88e923
2022-05-27 12:54:34 -06:00
Jeremy Soller
e19c39eb59 mb/system76/gaze17: Add new mainboard
Change-Id: Ie4c5297088b06c4e4b9c111f798cb17638fa8592
2022-05-16 11:41:27 -06:00
Jeremy Soller
48e7ffc9cd Refactor GC6 support for all boards
Change-Id: Id9191c76e0055d5f02a1de8c25a35cf05718c092
2022-05-16 11:41:07 -06:00
Jeremy Soller
8c4eeafcfe mb/system76/addw1: Disable SaOcSupport to eliminate hangs with 3200MT/s memory
Change-Id: I586e8cf97a52b2fa8386ce3742a4f4ae9465bbcf
2022-05-16 11:38:25 -06:00
Michał Żygowski
6b56932606 soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU
PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init.
Implementation based on Slimbootloader's
"Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib" and FSP source.

TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded and its recipe
and version is printed.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080
2022-05-16 11:38:24 -06:00
Michał Żygowski
28cc4183c8 soc/alderlake: Add ADL-S PCIe support
Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
2022-05-16 11:38:23 -06:00
Michał Żygowski
ffb97ba314 include/smbios.h: Add PCIe Gen5 slot type definitions
Add PCI Express Gen5 slot type definitions from DMTF SMBIOS
specification 3.5.0.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624
2022-05-16 11:38:22 -06:00
Tim Crawford
b47923d714 soc/intel/adl: Don't send EOP early
Early EOP prevents disabling CSME.

Disabling CSME now occurs, but checking the result fails:

    [DEBUG]  HECI: ME state change send success!
    [DEBUG]  HECI: ME state change result failure!

CSME is disabled on subsequent boots.

Change-Id: I1c1416bb6537774f4bf09820c551b3b4ca7d1a38
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:38:21 -06:00
Tim Crawford
5783ad7a65 mb/system76: TGL-U: Disable AER for CPU PCIe RP
Fixes suspend with certain SSDs installed in the PCIe 4 slot.

Change-Id: Ib91b154963aeafe96c8118cbab89f0e70634e8bc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:38:20 -06:00
Tim Crawford
090448674d mb/system76: Configure I2C HID IRQs as level triggered
Per Microsoft's spec for HID over I2C [1], interrupts must be level
triggered. Switch GPIOs and the devicetree config to conform to this.

[1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx

Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:18 -06:00
Tim Crawford
7f1b3fa98c mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:17 -06:00
Tim Crawford
0004ff6f28 mb/system76/addw1: Increase max CPUs to 16
The addw1 supports an i9-9980HK and the addw2 uses an i7-10875H.
These CPUs have 8 cores and 16 threads. Fixes booting on addw2.

Change-Id: I4639b40c3ab9c6d6ad5abbbb3618c750c7d40695
Fixes: 6a93a45242 ("mb/system76/addw1: Add System76 Adder Workstation 1")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:16 -06:00
Tim Crawford
f55ab41430 src/mb/system76/*: Shrink CMOS option table 1 byte
The option table is shrunk 1 byte to force coreboot to invalid the table
and write the new defaults. This will ensure the IME is in the correct
mode on the next update.

Change-Id: I805c53fee55fea69fa3363fea0609858cc88f2d3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:15 -06:00
Tim Crawford
912122d95f mb/system76: TGL-H: Disable D3cold for TCSS
Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:14 -06:00
Jeremy Soller
8933418194 mb/system76/lemp9: Fix TPM error message
Change-Id: Id5456c0d6abee6d79761fae0bed78cc6def351f3
2022-05-16 11:36:13 -06:00
Jeremy Soller
25eb9c20a8 mb/system76: select TPM_RDRESP_NEED_DELAY
Change-Id: I7909b05e9203ce9ad07c8e87a847bc46cf281b34
2022-05-16 11:36:12 -06:00
Jeremy Soller
9b0cf73235 soc/intel: Add Cometlake-H/S Q0 (10+2) CPU
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
2022-05-16 11:36:11 -06:00
Jeremy Soller
7727cc504b intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2022-05-16 11:36:10 -06:00
Jeremy Soller
9c0913d5c2 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
2022-05-16 11:36:09 -06:00
Jeremy Soller
c7998fda31 soc/intel/tigerlake: Remove write to IOP TCSS_IN_D3
Change-Id: Ibbf6b5e0bf627536d10c8dee2f632e66da427151
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:08 -06:00
Tim Crawford
2fae43f36a mb/system76/*: Enable dGPUs
Change-Id: Ib5bab02801407c8bf05e6028bf8f9fa7ccc5ecd0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:36:01 -06:00
Tim Crawford
fa92d159d4 drivers/gfx/nvidia: Add driver for NVIDIA Optimus
Add a driver for systems with NVIDIA Optimus (hybrid) graphics using
GC6 3.0. The driver provides ACPI support for dynamically powering on
and off the GPU, and a function for enabling the GPU power in romstage.

Tested on system76/gaze15.

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:35:13 -06:00
Tim Crawford
243b89b15c mb/system76/*: Apply custom backlight levels
Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2022-05-16 11:35:12 -06:00
Tim Crawford
832fd34cf5 submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2022-05-16 11:35:11 -06:00
Subrata Banik
670572ff6a soc/intel/cmn/cse: Enforce CSE disabling
This patch enforces disabling of the CSE device if CSE stays in
SOFT TEMP DISABLE state. The recommendation is to make CSE function
disable to avoid receiving any CSE commands from the OS layer.

BUG=b:228789015
TEST=None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-29 15:13:47 +00:00
Subrata Banik
4b1f4e3a99 soc/intel/cmn/cse: Drop redundant macro check for heci1_disable()
This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.

As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.

BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-29 15:13:27 +00:00
Subrata Banik
c176fc2dfb soc/intel: Decouple HECI disabling interface from HECI disable Kconfig
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.

BUG=b:228789015
TEST=Able to build google/redrix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-29 15:12:52 +00:00
Elyes Haouas
09106f75f1 sb/intel/i82801dx/pci.c: Use pci_or_config16() and macros
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I658fa9cee4517b9f68102b74949d32d7ab0309f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-29 14:41:09 +00:00
Werner Zeh
9f15a6c031 MAINTAINERS: Add myself as maintainer of mc_ehl boards
Change-Id: I203f122de6641359306c2659cb9d9dc2c93d184c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-04-29 13:14:24 +00:00
Tony Huang
394057e715 mb/google/brya/var/agah: Change Aux settings to TCSS port 2
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.

Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-29 13:14:09 +00:00
Matt DeVillier
02944888d6 mb/google/{octopus,reef}: add RO_VPD region to default FMAP
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.

Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-28 12:56:52 +00:00
Terry Chen
df2685cc4a mb/google/brya/var/crota: fix Goodix touchpad
- Fix Goodix hid and hid offset

BUG=b:230415144
BRANCH=brya
TEST=build and boot without error

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I5a5c1cdca0cec15d65fe62a3104652d2d347fd54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28 12:56:30 +00:00
Wonkyu Kim
92c1042a35 soc/intel/cmn/sa: Introduce PCIEXBAR_PCIEXBAREN macro
Use PCIEXBAR_PCIEXBAREN instead of constant value(1)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ica9e8162945da0a714822c37753914575c26024e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-28 12:56:04 +00:00
Hsuan Ting Chen
be345c0bb4 commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h>
The header file <inttypes.h> includes <stdint.h> and defines some
additional PRI* macros. Since elog.h and elog.c do not use any of the
PRI* macro, we should include <stdint.h> directly.

Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-04-28 12:55:32 +00:00
Peter Marheine
c814fa5915 mb/google/brya: disable early EC sync for nereid
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.

Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.

BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
     Nereid.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2022-04-28 01:00:30 +00:00
Frank Wu
c4af5e4009 mb/google/brya/var/banshee: Update the FIVR configurations
This patch enables V1p05 and Vnn external bypass VRs for Banshee.

BUG=b:207116793
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Idb56890db40f90f163d8dadf5bf7c7335469771a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63860
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27 20:16:22 +00:00
Gaggery Tsai
2f4246ab0c mb/google/brya/var/vell: Enable TBT PCIe root port 3
This patch enables TBT PCIe root port 3.

BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
     ensure 07.3 is in the list.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27 20:16:04 +00:00
Fred Reitberger
248916ad57 mb/amd/chausie: Auto-detect DDI type
Read the EEPROM to detect the DDI type.

BUG=b:225139014
TEST=Boot chausie and correctly detect display card type

Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27 20:14:25 +00:00
Teddy Shih
263f143c44 mb/google/dedede/beadrix: Update DPTF setting
Update DPTF Policy and temperature sensor values from thermal team.

BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27 18:03:13 +00:00
Simon Yang
dec327b03b soc/intel/jasperlake: Revert CdClock setting
Revert CdClock setting and use default value 0xff.

Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.

BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"

Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27 17:15:13 +00:00
Fred Reitberger
19788cd9a4 mb/amd/chausie: Add EC support
Add support for the chausie EC. Use EC to configure default board GPIO
settings.

Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27 16:08:36 +00:00
Fred Reitberger
6e184e6bdf md/amd/chausie: call espi_switch_to_spi1_pads
Chausie uses the spi1 pads for eSPI

Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27 16:07:45 +00:00
Felix Held
8fbf88fd8c include/device/i2c_simple: add i2c_2ba_read_bytes function
To read data from an I2C EEPROM that uses 2 byte offsets or any other
I2C device that uses 2 byte offsets, first the two offset bytes are sent
to the device and then the data bytes are read from it. The main
difference to the existing i2c_read_bytes is that that function will
only send one offset byte to the I2C device.

TEST=Reading the contents of an EEPROM on the AMD Chausie board works

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-27 16:07:29 +00:00
Arthur Heymans
66538e0877 cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.

This fixes building when some debug options are enabled.

Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27 13:04:23 +00:00