Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the
same value and conveys additional information to the reader. Done with a
bulk search and replace operation.
Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch introduces support for storing the MRC cache based on the
MRC version for both ADL-N and TWL platforms. It select the
MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_ALDERLAKE_PCH_N
is chosen.
BUG=b:296433836
Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brandon Weeks <bweeks@google.com>
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for
ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT
FSP for both Client and IoT configurations, despite the Client FSP
requiring distinct headers.
The CWWK CW-ADL-4L-V1.0 board relies on the FSP provided by the
3rdparty/fsp submodule, which means it has been using the IoT FSP by
default. To ensure the board continues to use the correct FSP as we
plan to introduce Client FSP headers into vendorcode, we are now
explicitly select FSP_TYPE_IOT for the CWWK CW-ADL-4L-V1.0 board.
Change-Id: Ie3844cb24740e4d95ee835a44e55b4d5cb6854e5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Brandon Weeks <bweeks@google.com>
Currently, the 3rdparty/fsp submodule contains only the IoT FSP for
ADL-N. However, coreboot's Kconfig is incorrectly applying the IoT
FSP for both Client and IoT configurations, despite the Client FSP
requiring distinct headers.
The aoostar/wtr_r1 board relies on the FSP provided by the 3rdparty/fsp
submodule, which means it has been using the IoT FSP by default. To
ensure the board continues to use the correct FSP as we plan to
introduce Client FSP headers into vendorcode, we are now explicitly
select FSP_TYPE_IOT for the aoostar/wtr_r1 board.
Change-Id: I68feeaaffd825013ae1012694047b067535e7341
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82914
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both, the list of IDs that we hooked our driver up to and the list
that we use for VBIOS mapping, had gaps. Fill those.
Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the entries which have the same state as the ones from the
chipset devicetree.
Change-Id: I4981cd835ef28a673d480808dd486fed4d9b45e5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The QEMU Bochs display driver and the QEMU Firmware Configuration
interface code (in the qemu-i440fx mainboard dir) were written for x86.
These devices are available in QEMU VMs of other architectures as well,
so we want to port them to be independent from x86.
The main problem is that the drivers use x86 port I/O functions to
communicate with devices over PCI I/O space. These are currently not
available for ARM* and RISC-V, although it is often still possible to
access PCI I/O ports over MMIO through a translator.
Add implementations of port I/O functions that work with PCI I/O space
on these architectures as well, assuming there is such a translator at a
known address configured at build-time.
Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80372
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This was done using Haswell autoport, with manual fixes to get the
output to build against current main. I do not physically have this
board; I was sent the output of autoport with some fixes on top of
which I added additional changes. The VBT was copied from
/sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware.
The flash chip is 8MiB in a socketed DIP8 package, making it easy to
externally flash to recover from a brick.
Working:
- Haswell MRC.bin
- S3 suspend and resume
- Libgfxinit
- HDMI
- DVI-I (including passive DVI to VGA adapter)
- DisplayPort
- SATA ports
- mSATA SSD
- mPCIe WiFi slot
- Rear USB ports
- USB 3.0 header
- Audio header
- Ethernet
- x16 PCIe slot
- EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector)
- edk2 (MrChromebox uefipayload_202309)
Not Tested:
- PS/2 keyboard/mouse
- eSATA
- USB 2.0 header
Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch flips the polarity of CONFIG_USE_1G_PAGES_TLB into
CONFIG_NEED_SMALL_2MB_PAGE_TABLES which is off by default, meaning
CPUs added in the future will automatically build the smaller 1GB pages.
We can expect support for this feature to be available on all future CPU
generations (with the possible exception of embedded edge cases), so
this default setting should make mistakes less likely and keep
maintenance effort lower. (Besides, enabling the support where it
doesn't work fails fast, whereas keeping it disabled where it could work
is an inefficiency that can easily go overlooked for a long time.)
While this is technically a CPU feature, not a northbridge feature, we
support a lot more individual CPUs than northbridges in the pre-SoC era,
and they tend to be closely coupled anyway. So select the option at the
northbridge level for older CPUs to keep things simpler.
Change-Id: I2cf1237a7fb63b8904c2a3d57fead162c66bacde
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field
description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented.
If numsets and associativity from CCSIDR_EL1 are not correct, the system
would hang during mmu_disable().
Rather than assuming that FEAT_CCIDX is not implemented, this patch
adds a check to dcache_apply_all to use the right register format.
Reference:
- https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770
BUG=b:317015456
TEST=mmu_disable works on the FEAT_CCIDX supported SoC.
Change-Id: I892009890f6ae889e87c877ffffd76a33d1dc789
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82636
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field
description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented.
If numsets and associativity from CCSIDR_EL1 are not correct, the system
would hang during mmu_disable().
Rather than assuming that FEAT_CCIDX is not implemented, this patch
adds a check to dcache_apply_all to use the right register format.
Reference:
- https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770
BUG=b:317015456
TEST=mmu_disable works on the FEAT_CCIDX supported SoC.
TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and
verify with the command
qemu-system-aarch64 -bios \
./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \
virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \
-nographic -m 8192M
Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82635
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Based on schematic, update slot number for PCIe port used for NIC
controller.
Change-Id: I7a1ead8f7e4588db45303041e60dbfe27ee12ea7
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
There's two copies of the `get_cxl_mode()` function to map the OCP VPD
value to the values expected by platform code. As this is unnecessary,
have a single copy of this function in the OCP VPD driver code. As the
`get_cxl_mode()` function is Xeon-SP only, keep it in a separate file.
This change simplifies things for boards using OCP VPD for CXL and has
no impact for boards *not* using OCP VPD:
- Boards not using OCP VPD can still define get_cxl_mode() in mainboard
code as needed, just like they were able to do before.
- Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not
enabled), this code won't get compiled in at all (see `Makefile.mk`).
- Boards using OCP VPD and CXL will automatically make use of this
`get_cxl_mode()` definition, which should be the same for all boards.
It is possible that this may need to be expanded/adapted in the future,
which is easy to handle in a follow-up commit when the need arises.
TEST=Build and boot on intel/archercity CRB
Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Just follow the examples of other payloads and simply remove the build
directory of said payload.
Change-Id: Idf2a8f3b9ecbb300514d2d1deede76785fd402b7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Set LpDdrDqDqsReTraining to 1 for xol. Value 0 will cause black screen
issue.
Reference: https://review.coreboot.org/c/coreboot/+/79527
> FSP default value for LpDdrDqDqsReTraining is 1. For boards
> that didn't set LpDdrDqDqsReTraining to any value, 0 was being
> assigned and it caused black screen issue.
BUG=b:332980211
BRANCH=brya
TEST=Built and verified there is no black screen issue during power
on/off test for over 100 cycles.
Change-Id: Ia346ce559b4509ea1a63abe28b12ad909f9b7b0d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82778
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit 79503ef515967ffceab7bd2a16a381e6a02c3d30.
The Intel FSP repository at https://github.com/intel/FSP.git currently
lacks the Client ADL-N headers. The existing coreboot code references
the "IoT/AlderLakeN/" directory for these headers, but it is missing the
crucial FspProducerDataHeader.h file. Without this header, the ADL-N
platform is unable to utilize the appropriate MRC version needed for
updating MRC caches. This patch aims to restore the necessary FSP
headers for the ADL-N platform within the vendorcode directory.
Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Wflex-array-member-not-at-end & Wcalloc-transposed-args are
not supported when using GCC older than GCC-14.
Use them only when supported.
Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82785
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This adds another external payload to coreboot. The payload has been
heavily based on u-boots UEFI implementation.
The leanefi payload is basically a translator from coreboot to UEFI. It
takes the coreboot tables and transforms them into UEFI interfaces.
Although it can potentially load any efi application that can
handle the minimized interface that leanefi provides, it has only
been tested with LinuxBoot (v6.3.5) as a payload. It has been optimized
to support only those interfaces that Linux requires to start.
Among other leanefi does not support:
- efi capsule update (also efi system resource table)
- efi variables
- efi text input protocol (it can only output)
- most boot services. mostly memory services are left (e.g. alloc/free)
- all runtime services (although there is still a very small runtime
footprint that is planned to be removed in the near future)
- TCG2/TPM (although that is mostly because of laziness)
The README.md currently provides more details on why.
The payload currently only supports arm64 and has only been tested
on emulation/simulator targets. The original motivation was to get ACPI
on arm64 published to the OS without using EDK2. It is however also
possible to supply the leanefi with a FDT that is published to the OS.
At that point one would however probably use coreboot only instead of
this shim layer on top. It would be way nicer to have Linux support
something else than UEFI to propagate the ACPI tables, but it requires
to get the Linux maintainer/community on board. So for now this shim
layer ciruimvents that.
LBBR Test:
// 1. dump FDT from QEMU like mentioned in aarch64 coreboot doc
// 2. compile u-root however you like (aarch64)
// 3. compile Linux (embed u-root initramfs via Kconfig)
// 4. copy Linux kernel to payloads/leanefi/Image
// 5. copy following coreboot defconfig to configs/defconfig:
CONFIG_BOARD_EMULATION_QEMU_AARCH64=y
CONFIG_PAYLOAD_NONE=n
CONFIG_PAYLOAD_LEANEFI=y
CONFIG_LEANEFI_PAYLOAD=y
CONFIG_LEANEFI_PAYLOAD_PATH="[path-to-linux]/arch/arm64/boot/Image"
CONFIG_LEANEFI_FDT=y
CONFIG_LEANEFI_FDT_PATH="[path-to-dumped-DTB]"
// 6. compile coreboot
make defconfig
make -j$(nproc)
// 7. run qemu like mentioned in coreboot doc (no FIT)
// 8. say hello to u-root and optionally kexec into the next kernel
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4093378e89c3cb43fb0846666de80a7da36b03f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ron Minnich <rminnich@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This reverts commit f4acef92.
Reason for revert: '-Wflex-array-member-not-at-end' is new command
option came with GCC-14. older versions will not support it.
Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82758
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U
variant, as originally committed, with the SKU number RZ09-01962, also
known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963
and RZ09-01964, known as the Mid 2017 model. This commit adds support
for the H3Q model. With respect to coreboot, there are few known
differences:
1. Only the H2U has TPM.
2. The USB ports are different.
3. The screen size (and therefore VBIOS Table) is different.
4. The hda_verb is very slightly different.
5. The gpio is different.
Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Apply commit c6b65c1a811e ("soc/intel/alderlake: Enable USB2 port reset
message on Type-C ports") to Meteor Lake.
This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.
The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state.
Change-Id: Iac702a8d8edd2b3b7e03abcac020be7e45335821
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82730
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
linux_trampoline.c generation is broken with latest crossgcc-i386
toolchain. Fix the issue to enable the building.
../cbfstool/linux_trampoline.S: Assembler messages:
../cbfstool/linux_trampoline.S💯 Error: no instruction mnemonic
suffix given and no register operands; can't size
instruction
<builtin>: recipe for target '../cbfstool/linux_trampoline.o'
failed
TEST=Build and boot on intel/archercity CRB
cd util/cbfstool/
rm linux_trampoline.c
make linux_trampoline.c
Change-Id: I7faca296f946bb4e9fd510661357925e5dcf9a6b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82704
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.
Same exact situation as with Alder Lake in CL 71715.
Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit
0a280ff7) with string changes. Dasharo-specific features will be added
in subsequent commits, similar to how Librem EC support was added in
changes 52390 and 52391.
Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
coreboot needs to figure out top of memory to place CBMEM data. On some
non-x86 QEMU virtual machines, this is achieved by probing the RAM space
to find where the VM starts discarding data since it's not backed by
actual RAM. This behaviour seems to have changed on the QEMU side since
then, VMs using the "virt" model have started raising exceptions/errors
instead of silently discarding data (likely [1] for example) which has
previously broken coreboot on these emulation boards.
The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt"
models and had this issue, which were mostly fixed by using exception
handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we
fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on
64-bit RISC-V we had to limit probing to 16383 MiB because it can run
into MMIO regions otherwise.
The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM
which doesn't appear to suffer from this issue. Still, the issue can be
observed on the ARMv7 "virt" model via a port based on qemu-aarch64.
QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the
device tree blob it provides for device information (incl. RAM size).
Implement functions that parse the device tree blob to find described
memory regions and calculate the top of memory in order to use it in
mainboard code as an alternative to probing RAM space. ARM64 code
initializes CBMEM in romstage where malloc isn't available, so take care
to do parsing without unflattening the blob and make the code available
in romstage as well.
[1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u
[2] https://review.coreboot.org/c/coreboot/+/34774
[3] https://review.coreboot.org/c/coreboot/+/36486
[4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html
[5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html
Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da.
Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it.
Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Obviously one should return NULL if a FDT is not valid an not the other
way around.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I77c0e187b841e60965daac17025110181bdd32bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
- Add Rex64 board to Kconfig menu
- Enable building for Rex64 with x86_64 support
Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The crashlog code in intel/common/block and meteorlake soc
was casting integer addresses directly to pointer types,
which caused compilation errors in x86_64 bit builds.
This commit fixes the issue by using uintptr_t for casting
integer addresses to pointer types before dereferencing.
BUG=b:329034258
TEST=Successfully build Meteor Lake (rex) in both x86_32 and
x86_64 modes.
Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
