mb/system76/gaze17: 3060: Fix RTD3 configs

The gaze17, like the oryp9, ties all resets for RTD3 to BUF_PLT_RST#
instead of using dedicated lines and ties the enable GPIO to 3.3VS.

Disable RTD3 config for the CPU PCIe RP and disable L23 for the PCH SSD
slot to fix suspend with Western Digital drives.

Change-Id: Iab3796d98ce74e09e74abb48b437e74a60c7b6b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/ec/system76/ec/Kconfig

@@ -6,7 +6,7 @@ config EC_SYSTEM76_EC
 config EC_SYSTEM76_EC_BAT_THRESHOLDS
 	depends on EC_SYSTEM76_EC
 	bool
-	default n
+	default y
 
 config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	depends on EC_SYSTEM76_EC

src/include/cpu/intel/cpu_ids.h

@@ -60,4 +60,6 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
+#define CPUID_RAPTORLAKE_P_J0		0xb06a2
+
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -3008,8 +3008,6 @@
 #define PCI_DID_INTEL_ADP_P_ESPI_29			0x7a1d
 #define PCI_DID_INTEL_ADP_P_ESPI_30			0x7a1e
 #define PCI_DID_INTEL_ADP_P_ESPI_31			0x7a1f
-#define PCI_DID_INTEL_ADP_P_ESPI_32			0x5181
-#define PCI_DID_INTEL_ADP_P_ESPI_33			0x5182
 #define PCI_DID_INTEL_ADP_S_ESPI_0			0x7a80
 #define PCI_DID_INTEL_ADP_S_ESPI_1			0x7a81
 #define PCI_DID_INTEL_ADP_S_ESPI_2			0x7a82
@@ -3074,7 +3072,6 @@
 #define PCI_DID_INTEL_ADP_M_N_ESPI_29			0x549d
 #define PCI_DID_INTEL_ADP_M_N_ESPI_30			0x549e
 #define PCI_DID_INTEL_ADP_M_N_ESPI_31			0x549f
-#define PCI_DID_INTEL_ADP_M_ESPI_32			0x5186
 #define PCI_DID_INTEL_SPR_ESPI_1			0x1b80
 #define PCI_DID_INTEL_MTL_ESPI_0			0x7e00
 #define PCI_DID_INTEL_MTL_ESPI_1			0x7e01
@@ -3084,6 +3081,38 @@
 #define PCI_DID_INTEL_MTL_ESPI_5			0x7e05
 #define PCI_DID_INTEL_MTL_ESPI_6			0x7e06
 #define PCI_DID_INTEL_MTL_ESPI_7			0x7e07
+#define PCI_DID_INTEL_RPP_P_ESPI_0			0x5180
+#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1		0x5181
+#define PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2		0x5182
+#define PCI_DID_INTEL_RPP_P_ESPI_3			0x5183
+#define PCI_DID_INTEL_RPP_P_ESPI_4			0x5184
+#define PCI_DID_INTEL_RPP_P_ESPI_5			0x5185
+#define PCI_DID_INTEL_RPP_P_ADP_M_ESPI_6		0x5186
+#define PCI_DID_INTEL_RPP_P_ESPI_7			0x5187
+#define PCI_DID_INTEL_RPP_P_ESPI_8			0x5188
+#define PCI_DID_INTEL_RPP_P_ESPI_9			0x5189
+#define PCI_DID_INTEL_RPP_P_ESPI_10			0x518a
+#define PCI_DID_INTEL_RPP_P_ESPI_11			0x518b
+#define PCI_DID_INTEL_RPP_P_ESPI_12			0x518c
+#define PCI_DID_INTEL_RPP_P_ESPI_13			0x518d
+#define PCI_DID_INTEL_RPP_P_ESPI_14			0x518e
+#define PCI_DID_INTEL_RPP_P_ESPI_15			0x518f
+#define PCI_DID_INTEL_RPP_P_ESPI_16			0x5190
+#define PCI_DID_INTEL_RPP_P_ESPI_17			0x5191
+#define PCI_DID_INTEL_RPP_P_ESPI_18			0x5192
+#define PCI_DID_INTEL_RPP_P_ESPI_19			0x5193
+#define PCI_DID_INTEL_RPP_P_ESPI_20			0x5194
+#define PCI_DID_INTEL_RPP_P_ESPI_21			0x5195
+#define PCI_DID_INTEL_RPP_P_ESPI_22			0x5196
+#define PCI_DID_INTEL_RPP_P_ESPI_23			0x5197
+#define PCI_DID_INTEL_RPP_P_ESPI_24			0x5198
+#define PCI_DID_INTEL_RPP_P_ESPI_25			0x5199
+#define PCI_DID_INTEL_RPP_P_ESPI_26			0x519a
+#define PCI_DID_INTEL_RPP_P_ESPI_27			0x519b
+#define PCI_DID_INTEL_RPP_P_ESPI_28			0x519c
+#define PCI_DID_INTEL_RPP_P_ESPI_29			0x519d
+#define PCI_DID_INTEL_RPP_P_ESPI_30			0x519e
+#define PCI_DID_INTEL_RPP_P_ESPI_31			0x519f
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3434,6 +3463,10 @@
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11		0x7ecb
 #define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12		0x7ecc
 
+#define PCI_DID_INTEL_RPL_P_PCIE_RP1			0xa74d
+#define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
+#define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3506,6 +3539,8 @@
 #define PCI_DID_INTEL_ADP_M_SATA_2		0x54d7
 #define PCI_DID_INTEL_ADP_M_SATA_3		0x282a
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
+#define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
+#define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
 
 /* Intel PMC device Ids */
 #define PCI_DID_INTEL_SPT_LP_PMC		0x9d21
@@ -3530,6 +3565,7 @@
 #define PCI_DID_INTEL_MTL_SOC_PMC		0x7e21
 #define PCI_DID_INTEL_MTL_IOE_M_PMC		0x7ebe
 #define PCI_DID_INTEL_MTL_IOE_P_PMC		0x7ece
+#define PCI_DID_INTEL_RPP_P_PMC			0x51a1
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -3959,6 +3995,9 @@
 #define PCI_DID_INTEL_MTL_M_GT2				0x7d40
 #define PCI_DID_INTEL_MTL_P_GT2_1			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d60
+#define PCI_DID_INTEL_RPL_P_GT1				0xa720
+#define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
+#define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
 
 
 /* Intel Northbridge Ids */
@@ -4079,6 +4118,8 @@
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
+#define PCI_DID_INTEL_RPL_P_ID_1		0xa706
+#define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4102,6 +4143,7 @@
 #define PCI_DID_INTEL_ADP_S_SMBUS			0x7aa3
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
+#define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4137,6 +4179,7 @@
 #define PCI_DID_INTEL_MTL_XHCI			0x7e7d
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
+#define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4161,6 +4204,7 @@
 #define PCI_DID_INTEL_MTL_SOC_P2SB		0x7e20
 #define PCI_DID_INTEL_MTL_IOE_M_P2SB		0x7eb8
 #define PCI_DID_INTEL_MTL_IOE_P_P2SB		0x7ec8
+#define PCI_DID_INTEL_RPP_P_P2SB		0x51a0
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4206,6 +4250,7 @@
 #define PCI_DID_INTEL_ADP_S_AUDIO_7		0x7ad6
 #define PCI_DID_INTEL_ADP_S_AUDIO_8		0x7ad7
 #define PCI_DID_INTEL_ADP_P_AUDIO		0x51c8
+#define PCI_DID_INTEL_RPP_P_AUDIO		0x51ca
 
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1		0x54c8
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2		0x54c9
@@ -4337,6 +4382,11 @@
 #define PCI_DID_INTEL_MTL_M_TBT_DMA0		0x7eb2
 #define PCI_DID_INTEL_MTL_P_TBT_DMA0		0x7ec2
 #define PCI_DID_INTEL_MTL_P_TBT_DMA1		0x7ec3
+#define PCI_DID_INTEL_RPL_TBT_RP0		0xa76e
+#define PCI_DID_INTEL_RPL_TBT_RP1		0xa73f
+#define PCI_DID_INTEL_RPL_TBT_RP2		0xa72f
+#define PCI_DID_INTEL_RPL_TBT_DMA0		0xa73e
+#define PCI_DID_INTEL_RPL_TBT_DMA1		0xa76d
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4376,6 +4426,7 @@
 #define PCI_DID_INTEL_ADL_IPU			0x465d
 #define PCI_DID_INTEL_ADL_N_IPU			0x462e
 #define PCI_DID_INTEL_MTL_IPU			0x7d19
+#define PCI_DID_INTEL_RPL_IPU			0xa75d
 
 /* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
@@ -4383,6 +4434,7 @@
 #define PCI_DID_INTEL_JSL_DTT			0x4E03
 #define PCI_DID_INTEL_ADL_DTT			0x461d
 #define PCI_DID_INTEL_MTL_DTT			0x7d03
+#define PCI_DID_INTEL_RPL_DTT			0xa71d
 
 /* Intel CNVi WiFi/BT device IDs */
 #define PCI_DID_INTEL_CML_LP_CNVI_WIFI		0x02f0
@@ -4427,6 +4479,7 @@
 #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM		0x54ef
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
+#define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291

src/mainboard/system76/addw1/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select EC_SYSTEM76_EC_OLED

src/mainboard/system76/adl-p/Kconfig

@@ -1,14 +1,16 @@
-if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11
+if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9
+	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
@@ -32,6 +34,7 @@ config MAINBOARD_DIR
 config VARIANT_DIR
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -39,14 +42,17 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP8
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9
 
 config MAINBOARD_VERSION
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
 
 config CBFS_SIZE
 	default 0xA00000
@@ -57,6 +63,9 @@ config CONSOLE_POST
 config DIMM_SPD_SIZE
 	default 512
 
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
 config POST_DEVICE
 	default n
 

src/mainboard/system76/adl-p/Kconfig.name

@@ -3,3 +3,6 @@ config BOARD_SYSTEM76_DARP8
 
 config BOARD_SYSTEM76_LEMP11
 	bool "lemp11"
+
+config BOARD_SYSTEM76_ORYP9
+	bool "oryp9"

src/mainboard/system76/adl-p/Makefile.inc

@@ -1,4 +1,5 @@
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
@@ -8,5 +9,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
 
 SPD_SOURCES = samsung-P4AAF165WA-BCWDE

src/mainboard/system76/adl-p/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +12,11 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }
-

src/mainboard/system76/adl-p/variants/darp8/overridetree.cb

@@ -1,8 +1,9 @@
 chip soc/intel/alderlake
+	# FIXME: Limit PL4 to PL2 to prevent power off on battery power
 	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 56,
-		.tdp_pl4 = 65,
+		.tdp_pl4 = 56,
 	}"
 
 	# GPE configuration

src/mainboard/system76/adl-p/variants/oryp9/board_info.txt

@@ -0,0 +1,2 @@
+Board name: oryp9
+Release year: 2022

src/mainboard/system76/adl-p/variants/oryp9/gpio.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
+	PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // Top swap override
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+	PAD_NC(GPP_E18, NATIVE), // TBTA_LSX2_TXD
+	PAD_NC(GPP_E19, NATIVE), // TBTA_LSX2_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // Strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
+	PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	//PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	//PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), // GLAN_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/adl-p/variants/oryp9/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155867f5, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155867f5),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+	// Enable DMIC microphone on ALC1220
+	0x02050036,
+	0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/adl-p/variants/oryp9/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb

@@ -0,0 +1,226 @@
+chip soc/intel/alderlake
+	# FIXME: Limit PL4 to PL2 to prevent power off on battery power
+	# EC will set PL4 on AC adapter plug/unplug
+	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 115,
+		.tdp_psyspl2 = 135,
+		.tdp_pl4 = 72,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x65f5 inherit
+
+		device ref pcie5 on
+			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
+		end
+		device ref igpu on
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+		end
+		device ref pcie4_0 on
+			# CPU PCIe RP#1 x4, Clock 0 (SSD1)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+			# FIXME: WD drives fail to suspend
+			#chip soc/intel/common/block/pcie/rtd3
+			#	register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
+			#	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+			#	register "srcclk_pin" = "0" # SSD0_CLKREQ#
+			#	device generic 0 on end
+			#end
+		end
+		device ref pcie4_1 on
+			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(3)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR,
+			}"
+			# FIXME: WD drives fail to suspend
+			#chip soc/intel/common/block/pcie/rtd3
+			#	register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2
+			#	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+			#	register "srcclk_pin" = "4" # SSD1_CLKREQ#
+			#	device generic 0 on end
+			#end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Per-KB""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref sata off end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to 3.3VS?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe RP#8 x1, Clock 5 (GLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# TYPEC2
+						use usb2_port9 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref smbus on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+	end
+end

src/mainboard/system76/adl-p/variants/oryp9/romstage.c

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+		.rcomp = { .resistor = 100, },
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/bonw14/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/cml-u/Kconfig

@@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP6
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES

src/mainboard/system76/darp7/Kconfig

@@ -1,57 +0,0 @@
-if BOARD_SYSTEM76_DARP7
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_I2C_HID
-	select DRIVERS_INTEL_PMC
-	select DRIVERS_INTEL_USB4_RETIMER
-	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MEMORY_MAPPED_TPM
-	select MAINBOARD_HAS_TPM2
-	select NO_UART_ON_SUPERIO
-	select PCIEXP_HOTPLUG
-	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
-	select SOC_INTEL_TIGERLAKE
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SPD_READ_BY_WORD
-	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
-
-config MAINBOARD_DIR
-	default "system76/darp7"
-
-config MAINBOARD_PART_NUMBER
-	default "darp7"
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Darter Pro"
-
-config MAINBOARD_VERSION
-	default "darp7"
-
-config CBFS_SIZE
-	default 0xA00000
-
-config CONSOLE_POST
-	default y
-
-config POST_DEVICE
-	default n
-
-config UART_FOR_CONSOLE
-	default 2
-
-# PM Timer Disabled, saves power
-config USE_PM_ACPI_TIMER
-	default n
-
-endif

src/mainboard/system76/darp7/Kconfig.name

@@ -1,2 +0,0 @@
-config BOARD_SYSTEM76_DARP7
-	bool "darp7"

src/mainboard/system76/darp7/Makefile.inc

@@ -1,8 +0,0 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-
-bootblock-y += bootblock.c
-bootblock-y += gpio_early.c
-
-ramstage-y += gpio.c
-ramstage-y += hda_verb.c
-ramstage-y += ramstage.c

src/mainboard/system76/darp7/acpi/mainboard.asl

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define EC_GPE_SCI 0x6E
-#define EC_GPE_SWI 0x6B
-#include <ec/system76/ec/acpi/ec.asl>
-
-Scope (\_SB) {
-	#include "sleep.asl"
-	Scope (PCI0) {
-		#include "backlight.asl"
-	}
-}

src/mainboard/system76/darp7/bootblock.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <mainboard/gpio.h>
-
-void bootblock_mainboard_early_init(void)
-{
-	mainboard_configure_early_gpios();
-}

src/mainboard/system76/darp7/ramstage.c

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <mainboard/gpio.h>
-#include <soc/ramstage.h>
-
-static void mainboard_init(void *chip_info)
-{
-	mainboard_configure_gpios();
-}
-
-struct chip_operations mainboard_ops = {
-	.init = mainboard_init,
-};

src/mainboard/system76/galp5/Kconfig.name

@@ -1,2 +0,0 @@
-config BOARD_SYSTEM76_GALP5
-	bool "galp5"

src/mainboard/system76/galp5/Makefile.inc

@@ -1,3 +0,0 @@
-bootblock-y += bootblock.c
-ramstage-y += ramstage.c
-ramstage-y += hda_verb.c

src/mainboard/system76/galp5/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/galp5/acpi/sleep.asl

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/gpio.h>
-
-Method (PGPM, 1, Serialized)
-{
-	For (Local0 = 0, Local0 < 6, Local0++)
-	{
-		\_SB.PCI0.CGPM (Local0, Arg0)
-	}
-}
-
-/*
- * Method called from _PTS prior to system sleep state entry
- * Enables dynamic clock gating for all 5 GPIO communities
- */
-Method (MPTS, 1, Serialized)
-{
-	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
-	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
-}
-
-/*
- * Method called from _WAK prior to system sleep state wakeup
- * Disables dynamic clock gating for all 5 GPIO communities
- */
-Method (MWAK, 1, Serialized)
-{
-	PGPM (0)
-	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
-}
-
-/*
- * S0ix Entry/Exit Notifications
- * Called from \_SB.PEPD._DSM
- */
-Method (MS0X, 1, Serialized)
-{
-	If (Arg0 == 1) {
-		/* S0ix Entry */
-		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
-	} Else {
-		/* S0ix Exit */
-		PGPM (0)
-	}
-}

src/mainboard/system76/galp5/board_info.txt

@@ -1,8 +0,0 @@
-Vendor name: System76
-Board name: galp5
-Category: laptop
-Release year: 2020
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y

src/mainboard/system76/galp5/bootblock.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <gpio.h>
-#include "gpio.h"
-
-void bootblock_mainboard_early_init(void)
-{
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}

src/mainboard/system76/galp5/cmos.default

@@ -1,3 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-me_state=Enable

src/mainboard/system76/galp5/cmos.layout

@@ -1,39 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-entries
-
-0	384	r	0	reserved_memory
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-
-# RTC_CLK_ALTCENTURY
-400	8	r	0	century
-
-412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
-976	16	h	0	check_sum
-
-enumerations
-
-2	0	Enable
-2	1	Disable
-
-4	0	Fallback
-4	1	Normal
-
-6	0	Emergency
-6	1	Alert
-6	2	Critical
-6	3	Error
-6	4	Warning
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 408 975 976

src/mainboard/system76/galp5/dsdt.asl

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/tigerlake/acpi/southbridge.asl>
-		#include <soc/intel/tigerlake/acpi/tcss.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	Scope (\_SB.PCI0.LPCB)
-	{
-		#include <drivers/pc80/pc/ps2_controller.asl>
-	}
-
-	#include "acpi/mainboard.asl"
-}

src/mainboard/system76/galp5/ramstage.c

@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/ramstage.h>
-#include "gpio.h"
-
-void mainboard_silicon_init_params(FSP_S_CONFIG *params)
-{
-	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
-
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
-}

src/mainboard/system76/gaze15/Kconfig

@@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/gaze16/Kconfig

@@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/gaze17/Kconfig

@@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_TABLES

src/mainboard/system76/gaze17/devicetree.cb

@@ -66,7 +66,6 @@ chip soc/intel/alderlake
 				.clk_src = 3,
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
 			}"
 			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
@@ -75,50 +74,13 @@ chip soc/intel/alderlake
 				device pci 00.3 on end # USB Type-C UCSI controller
 			end
 		end
-		device ref igpu on
-			# DDIA is eDP
-			register "ddi_portA_config" = "1"
-			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
-		end
-		device ref pcie4_0 on
-			# PCIe PEG0 x4, Clock 0 (SSD2)
-			register "cpu_pcie_rp[CPU_RP(1)]" = "{
-				.clk_src = 0,
-				.clk_req = 0,
-				.flags = PCIE_RP_LTR,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD1_RST#
-				register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
-				device generic 0 on end
-			end
-		end
-		device ref tbt_pcie_rp0 on end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
 			device ref tcss_root_hub on
 				device ref tcss_usb3_port1 on end
 			end
 		end
-		device ref tcss_dma0 on end
 
-		# From PCH EDS(TODO)
-		device ref xhci on
-			# USB2
-			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
-			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
-			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
-			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
-			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
-			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
-			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
-			# USB3
-			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
-			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
-			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
-		end
 		device ref shared_sram on end
 		device ref cnvi_wifi on
 			chip drivers/wifi/generic
@@ -130,7 +92,15 @@ chip soc/intel/alderlake
 			# Touchpad I2C bus
 			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
 			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
 				register "generic.desc" = ""FocalTech Touchpad""
 				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
 				register "generic.probed" = "1"
@@ -143,62 +113,6 @@ chip soc/intel/alderlake
 			register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
 			register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
 		end
-		device ref pcie_rp5 on
-			# PCIe root port #5 x1, Clock 2 (WLAN)
-			register "pch_pcie_rp[PCH_RP(5)]" = "{
-				.clk_src = 2,
-				.clk_req = 2,
-				.flags = PCIE_RP_LTR,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" # M2_WLAN_RST#
-				register "srcclk_pin" = "2" # WLAN_CLKREQ#
-				device generic 0 on end
-			end
-		end
-		device ref pcie_rp6 on
-			# PCIe root port #6 x1, Clock 5 (CARD)
-			register "pch_pcie_rp[PCH_RP(6)]" = "{
-				.clk_src = 5,
-				.clk_req = 5,
-				.flags = PCIE_RP_LTR,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: No enable_gpio = no D3cold?
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
-				register "srcclk_pin" = "5" # CARD_CLKREQ#
-				device generic 0 on end
-			end
-		end
-		device ref pcie_rp7 on
-			# PCIe root port #7 x1, Clock 6 (GLAN)
-			# Clock source is shared with LAN and hence marked as free running.
-			register "pch_pcie_rp[PCH_RP(7)]" = "{
-				.clk_src = 6,
-				.clk_req = 6,
-				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
-			}"
-			register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
-		end
-		device ref pcie_rp9 on
-			# PCIe root port #9 x4, Clock 1 (SSD1)
-			register "pch_pcie_rp[PCH_RP(9)]" = "{
-				.clk_src = 1,
-				.clk_req = 1,
-				.flags = PCIE_RP_LTR,
-				.PcieRpL1Substates = L1_SS_FSP_DEFAULT,
-			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_PCH_SSD_RST#
-				register "srcclk_pin" = "1" # SSD_CLKREQ#
-				device generic 0 on end
-			end
-		end
 		device ref pch_espi on
 			register "gen1_dec" = "0x00040069" # EC PM channel
 			register "gen2_dec" = "0x00fc0E01" # AP/EC command

src/mainboard/system76/gaze17/ramstage.c

@@ -8,10 +8,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
 	params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
 
-	params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
 	params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
+	params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
+	params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
+	params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
 
-	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 (DEVSLP1B)
+	params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
+	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
 
 	variant_configure_gpios();
 }

src/mainboard/system76/gaze17/variants/3050/gpio.c

@@ -33,10 +33,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A11, NONE),
 	PAD_NC(GPP_A12, NONE),
 	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
-	PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
 	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
 	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
-	_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000), // TP_ATTN#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
 	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
 	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
 	PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
@@ -102,10 +102,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D2, NONE),
 	PAD_NC(GPP_D3, NONE),
 	PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
-	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
-	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
-	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
-	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
 	PAD_NC(GPP_D9, NONE),
 	PAD_NC(GPP_D10, NONE),
 	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
@@ -120,10 +120,10 @@ static const struct pad_config gpio_table[] = {
 
 	/* ------- GPIO Group GPP_E ------- */
 	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
-	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
 	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
 	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
-	//PAD_CFG_GP0(GPP_E4, 0, DEEP), // DGPU_PWR_EN
+	PAD_NC(GPP_E4, NONE),
 	PAD_NC(GPP_E5, NONE),
 	PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
 	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
@@ -150,7 +150,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
 	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
 	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
 	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
 	PAD_NC(GPP_F7, NONE),
 	//PAD_NC(GPP_F8, NONE),
@@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
 	PAD_NC(GPP_F17, NONE),
 	PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
 	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
 	PAD_NC(GPP_F21, NONE),
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
@@ -181,8 +181,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
 	PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
 	PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
-	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
-	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
 	PAD_NC(GPP_H12, NONE),
 	_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
 	//PAD_NC(GPP_H14, NONE),
@@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
 	PAD_NC(GPP_H21, NONE),
 	PAD_NC(GPP_H22, NONE),
-	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
 
 	/* ------- GPIO Group GPP_R ------- */
 	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK

src/mainboard/system76/gaze17/variants/3050/gpio_early.c

@@ -4,8 +4,10 @@
 #include <soc/gpio.h>
 
 static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_GPO(GPP_E4, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
 	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
 };
 
 void variant_configure_early_gpios(void)

src/mainboard/system76/gaze17/variants/3050/hda_verb.c

@@ -20,6 +20,10 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
 };
 
-const u32 pc_beep_verbs[] = {};
+const u32 pc_beep_verbs[] = {
+	// Adjust mic coefficient
+	0x02050007,
+	0x02040202,
+};
 
 AZALIA_ARRAY_SIZES;

src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h

@@ -6,7 +6,7 @@
 #include <soc/gpio.h>
 
 #define DGPU_RST_N	GPP_B2
-#define DGPU_PWR_EN	GPP_E4
+#define DGPU_PWR_EN	GPP_A14
 #define DGPU_GC6	GPP_F13
 #define DGPU_SSID	0x866d1558
 

src/mainboard/system76/gaze17/variants/3050/overridetree.cb

@@ -1,5 +1,106 @@
 chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x866d inherit
+
+		device ref igpu on
+			# DDIA is eDP
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+			#chip soc/intel/common/block/pcie/rtd3
+			#	# XXX: Enable tied to 3.3VS?
+			#	#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
+			#	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+			#	register "reset_delay_ms" = "100"
+			#	register "reset_off_delay_ms" = "100"
+			#	register "srcclk_pin" = "0" # SSD0_CLKREQ#
+			#	device generic 0 on end
+			#end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+		end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x4, Clock 1 (SSD)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "disable_l23" = "true"
+				register "srcclk_pin" = "1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x1, Clock 6 (GLAN)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp10 on
+			# PCIe RP#10 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp11 on
+			# PCIe RP#11 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
 	end
 end

src/mainboard/system76/gaze17/variants/3060/overridetree.cb

@@ -2,6 +2,96 @@ chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x867c inherit
 
+		device ref igpu on
+			# DDIA is eDP
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+		end
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+			#chip soc/intel/common/block/pcie/rtd3
+			#	# XXX: Enable tied to 3.3VS?
+			#	register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
+			#	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+			#	register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
+			#	device generic 0 on end
+			#end
+		end
+		device ref tbt_pcie_rp0 on end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
+		end
+		device ref pcie_rp5 on
+			# PCIe root port #5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe root port #6 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: No enable_gpio = no D3cold?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 6 (GLAN)
+			# Clock source is shared with LAN and hence marked as free running.
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "disable_l23" = "true" # Fixes suspend on WD drives
+				register "srcclk_pin" = "1" # SSD_CLKREQ#
+				device generic 0 on end
+			end
+		end
 		device ref gbe on end
 	end
 end

src/mainboard/system76/lemp10/Kconfig

@@ -1,57 +0,0 @@
-if BOARD_SYSTEM76_LEMP10
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_I2C_HID
-	select DRIVERS_INTEL_PMC
-	select DRIVERS_INTEL_USB4_RETIMER
-	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select HAVE_SPD_IN_CBFS
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MEMORY_MAPPED_TPM
-	select MAINBOARD_HAS_TPM2
-	select NO_UART_ON_SUPERIO
-	select PCIEXP_HOTPLUG
-	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
-	select SOC_INTEL_TIGERLAKE
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SPD_READ_BY_WORD
-	select SYSTEM_TYPE_LAPTOP
-	select TPM_MEASURED_BOOT
-	select TPM_RDRESP_NEED_DELAY
-
-config MAINBOARD_DIR
-	default "system76/lemp10"
-
-config MAINBOARD_PART_NUMBER
-	default "lemp10"
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Lemur Pro"
-
-config MAINBOARD_VERSION
-	default "lemp10"
-
-config CBFS_SIZE
-	default 0xA00000
-
-config CONSOLE_POST
-	default y
-
-config POST_DEVICE
-	default n
-
-config UART_FOR_CONSOLE
-	default 2
-
-# PM Timer Disabled, saves power
-config USE_PM_ACPI_TIMER
-	default n
-
-endif

src/mainboard/system76/lemp10/Kconfig.name

@@ -1,2 +0,0 @@
-config BOARD_SYSTEM76_LEMP10
-	bool "lemp10"

src/mainboard/system76/lemp10/Makefile.inc

@@ -1,10 +0,0 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
-
-bootblock-y += bootblock.c
-bootblock-y += gpio_early.c
-
-ramstage-y += ramstage.c
-ramstage-y += gpio.c
-ramstage-y += hda_verb.c
-
-SPD_SOURCES = samsung-M471A1G44AB0-CWE

src/mainboard/system76/lemp10/acpi/backlight.asl

@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/intel/gma/acpi/gma.asl>
-
-Scope (GFX0)
-{
-	Name (BRIG, Package (22) {
-		40, /* default AC */
-		40, /* default Battery */
-		5,
-		10,
-		15,
-		20,
-		25,
-		30,
-		35,
-		40,
-		45,
-		50,
-		55,
-		60,
-		65,
-		70,
-		75,
-		80,
-		85,
-		90,
-		95,
-		100
-	})
-}

src/mainboard/system76/lemp10/acpi/mainboard.asl

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define EC_GPE_SCI 0x6E
-#define EC_GPE_SWI 0x6B
-#include <ec/system76/ec/acpi/ec.asl>
-
-Scope (\_SB) {
-	#include "sleep.asl"
-	Scope (PCI0) {
-		#include "backlight.asl"
-	}
-}

src/mainboard/system76/lemp10/acpi/sleep.asl

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/gpio.h>
-
-Method (PGPM, 1, Serialized)
-{
-	For (Local0 = 0, Local0 < 6, Local0++)
-	{
-		\_SB.PCI0.CGPM (Local0, Arg0)
-	}
-}
-
-/*
- * Method called from _PTS prior to system sleep state entry
- * Enables dynamic clock gating for all 5 GPIO communities
- */
-Method (MPTS, 1, Serialized)
-{
-	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
-	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
-}
-
-/*
- * Method called from _WAK prior to system sleep state wakeup
- * Disables dynamic clock gating for all 5 GPIO communities
- */
-Method (MWAK, 1, Serialized)
-{
-	PGPM (0)
-	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
-}
-
-/*
- * S0ix Entry/Exit Notifications
- * Called from \_SB.PEPD._DSM
- */
-Method (MS0X, 1, Serialized)
-{
-	If (Arg0 == 1) {
-		/* S0ix Entry */
-		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
-	} Else {
-		/* S0ix Exit */
-		PGPM (0)
-	}
-}

src/mainboard/system76/lemp10/board_info.txt

@@ -1,8 +0,0 @@
-Vendor name: System76
-Board name: lemp10
-Category: laptop
-Release year: 2020
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y

src/mainboard/system76/lemp10/cmos.default

@@ -1,3 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-me_state=Enable

src/mainboard/system76/lemp10/cmos.layout

@@ -1,39 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-entries
-
-0	384	r	0	reserved_memory
-
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-
-# RTC_CLK_ALTCENTURY
-400	8	r	0	century
-
-412	4	e	6	debug_level
-416	1	e	2	me_state
-417	3	h	0	me_state_counter
-976	16	h	0	check_sum
-
-enumerations
-
-2	0	Enable
-2	1	Disable
-
-4	0	Fallback
-4	1	Normal
-
-6	0	Emergency
-6	1	Alert
-6	2	Critical
-6	3	Error
-6	4	Warning
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 408 975 976

src/mainboard/system76/lemp10/dsdt.asl

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725
-)
-{
-	#include <acpi/dsdt_top.asl>
-	#include <soc/intel/common/block/acpi/acpi/platform.asl>
-	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Device (\_SB.PCI0)
-	{
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/tigerlake/acpi/southbridge.asl>
-		#include <soc/intel/tigerlake/acpi/tcss.asl>
-	}
-
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	Scope (\_SB.PCI0.LPCB)
-	{
-		#include <drivers/pc80/pc/ps2_controller.asl>
-	}
-
-	#include "acpi/mainboard.asl"
-}

src/mainboard/system76/lemp10/include/mainboard/gpio.h

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-void mainboard_configure_early_gpios(void);
-void mainboard_configure_gpios(void);
-
-#endif

src/mainboard/system76/lemp9/Kconfig

@@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT

src/mainboard/system76/oryp5/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/oryp5/gpio.c

@@ -164,8 +164,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
 	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
-	PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+	//PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+	//PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
 
 	/* ------- GPIO Group GPP_G ------- */
 	PAD_NC(GPP_G0, NONE),

src/mainboard/system76/oryp5/gpio_early.c

@@ -6,6 +6,8 @@
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
 };
 
 void mainboard_configure_early_gpios(void)

src/mainboard/system76/oryp5/hda_verb.c

@@ -8,6 +8,7 @@ const u32 cim_verb_data[] = {
 	0x155896e1, /* Subsystem ID */
 	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155896e1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)

src/mainboard/system76/oryp6/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/oryp8/Kconfig

@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME

src/mainboard/system76/tgl-u/Kconfig

@@ -1,18 +1,19 @@
-if BOARD_SYSTEM76_GALP5
+if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_BAT_THRESHOLDS
-	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP7
+	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_GALP5
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP10
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MEMORY_MAPPED_TPM
@@ -28,16 +29,30 @@ config BOARD_SPECIFIC_OPTIONS
 	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
-	default "system76/galp5"
+	default "system76/tgl-u"
+
+config VARIANT_DIR
+	default "darp7" if BOARD_SYSTEM76_DARP7
+	default "galp5" if BOARD_SYSTEM76_GALP5
+	default "lemp10" if BOARD_SYSTEM76_LEMP10
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
-	default "galp5"
+	default "darp7" if BOARD_SYSTEM76_DARP7
+	default "galp5" if BOARD_SYSTEM76_GALP5
+	default "lemp10" if BOARD_SYSTEM76_LEMP10
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Galago Pro"
+	default "Darter Pro" if BOARD_SYSTEM76_DARP7
+	default "Galago Pro" if BOARD_SYSTEM76_GALP5
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP10
 
 config MAINBOARD_VERSION
-	default "galp5"
+	default "darp7" if BOARD_SYSTEM76_DARP7
+	default "galp5" if BOARD_SYSTEM76_GALP5
+	default "lemp10" if BOARD_SYSTEM76_LEMP10
 
 config CBFS_SIZE
 	default 0xA00000
@@ -45,9 +60,6 @@ config CBFS_SIZE
 config CONSOLE_POST
 	default y
 
-config ONBOARD_VGA_IS_PRIMARY
-	default y
-
 config POST_DEVICE
 	default n
 
@@ -58,7 +70,15 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+# For galp5 with dGPU
+if DRIVERS_GFX_NVIDIA
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
 config DRIVERS_GFX_NVIDIA_BRIDGE
 	default 0x1c
 
+endif # DRIVERS_GFX_NVIDIA
+
 endif

src/mainboard/system76/tgl-u/Kconfig.name

@@ -0,0 +1,8 @@
+config BOARD_SYSTEM76_DARP7
+	bool "darp7"
+
+config BOARD_SYSTEM76_GALP5
+	bool "galp5"
+
+config BOARD_SYSTEM76_LEMP10
+	bool "lemp10"

src/mainboard/system76/tgl-u/Makefile.inc

@@ -0,0 +1,13 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+SPD_SOURCES = samsung-M471A1G44AB0-CWE

src/mainboard/system76/tgl-u/acpi/mainboard.asl

@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "../gpio.h"
+#if CONFIG(BOARD_SYSTEM76_GALP5)
+#include <variant/gpio.h>
+#endif
 
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
@@ -10,8 +12,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+#if CONFIG(BOARD_SYSTEM76_GALP5)
 		Scope (RP01) { // Remapped from RP05
 			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
 		}
+#endif
 	}
 }

src/mainboard/system76/tgl-u/board_info.txt

@@ -1,7 +1,5 @@
 Vendor name: System76
-Board name: darp7
 Category: laptop
-Release year: 2021
 ROM package: SOIC-8
 ROM protocol: SPI
 ROM socketed: n

src/mainboard/system76/tgl-u/devicetree.cb

@@ -0,0 +1,142 @@
+chip soc/intel/tigerlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# ACPI (soc/intel/tigerlake/acpi.c)
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Enable s0ix, required for TGL-U
+	register "s0ix_enable" = "1"
+
+# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+	# System Agent dynamic frequency support
+	register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable" = "1"
+
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Read LPM_EN, make sure to invert the bits
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
+	# Thermal
+	register "tcc_offset" = "12"
+
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP
+			register "DdiPortAConfig" = "1"
+			register "DdiPortAHpd" = "1"
+			register "DdiPortADdc" = "0"
+
+			# DDIB is HDMI
+			register "DdiPortBConfig" = "0"
+			register "DdiPortBHpd" = "1"
+			register "DdiPortBDdc" = "1"
+
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref dptf on end
+		device ref tbt_pcie_rp0 on end
+		device ref gna on end
+		device ref shared_ram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 on
+			# TODO: USB-PD?
+			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+		device ref heci1 on end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x00040069"
+			register "gen2_dec" = "0x00fc0E01"
+			register "gen3_dec" = "0x00fc0F01"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "PchHdaAudioLinkHdaEnable" = "1"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end

src/mainboard/system76/tgl-u/variants/darp7/board_info.txt

@@ -0,0 +1,2 @@
+Board name: darp7
+Release year: 2021

src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb

@@ -1,21 +1,4 @@
 chip soc/intel/tigerlake
-	register "common_soc_config" = "{
-		// Touchpad I2C bus
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 80,
-			.fall_time_ns = 110,
-		},
-	}"
-
-# ACPI (soc/intel/tigerlake/acpi.c)
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
-
-	# Enable s0ix, required for TGL-U
-	register "s0ix_enable" = "1"
-
-# CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits
 	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
 		.tdp_pl1_override = 28,
@@ -26,86 +9,14 @@ chip soc/intel/tigerlake
 		.tdp_pl2_override = 40,
 	}"
 
-# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
-	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
-
-	# System Agent dynamic frequency support
-	register "SaGv" = "SaGv_Enabled"
-
-# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
-	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable" = "1"
-
-	# FIVR configuration
-	#   Read EXT_RAIL_CONFIG to determine bitmaps
-	#     sudo devmem2 0xfe0011b8
-	#     0x0
-	#   Read EXT_V1P05_VR_CONFIG
-	#     sudo devmem2 0xfe0011c0
-	#     0x1a42000
-	#   Read EXT_VNN_VR_CONFIG0
-	#     sudo devmem2 0xfe0011c4
-	#     0x1a42000
-	# TODO: v1p05 voltage and vnn icc max?
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = 0,
-		.vnn_enable_bitmap = 0,
-		.v1p05_supported_voltage_bitmap = 0,
-		.vnn_supported_voltage_bitmap = 0,
-		.v1p05_icc_max_ma = 500,
-		.vnn_sx_voltage_mv = 1050,
-	}"
-
-	# Read LPM_EN, make sure to invert the bits
-	register "LpmStateDisableMask" = "
-		LPM_S0i2_1 |
-		LPM_S0i2_2 |
-		LPM_S0i3_1 |
-		LPM_S0i3_2 |
-		LPM_S0i3_3 |
-		LPM_S0i3_4
-	"
-
-	# Thermal
-	register "tcc_offset" = "12"
-
-	# Enable CNVi BT
-	register "CnviBtCore" = "true"
-
-# PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "PMC_GPP_A"
 	register "pmc_gpe0_dw1" = "PMC_GPP_R"
 	register "pmc_gpe0_dw2" = "PMC_GPD"
 
-# Actual device tree
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
 	device domain 0 on
 		subsystemid 0x1558 0x51a1 inherit
 
-		#From CPU EDS (575683)
-		device ref system_agent on end
-		device ref igpu on
-			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
-			register "DdiPortAHpd" = "1"
-			register "DdiPortADdc" = "0"
-
-			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
-			register "DdiPortBHpd" = "1"
-			register "DdiPortBDdc" = "1"
-
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref dptf on end
 		device ref peg on
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
@@ -117,7 +28,6 @@ chip soc/intel/tigerlake
 				device generic 0 on end
 			end
 		end
-		device ref tbt_pcie_rp0 on end # J_TYPEC2
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
 			register "TcssXhciEn" = "1"
@@ -140,7 +50,6 @@ chip soc/intel/tigerlake
 			end
 		end
 
-		# From PCH EDS (576591)
 		device ref south_xhci on
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
@@ -218,34 +127,6 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device ref shared_ram on end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref i2c1 on
-			# TODO: USB-PD?
-			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
-		end
-		device ref heci1 on end
-		device ref uart2 on
-			# Debug console
-			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
-		end
 		device ref sata on
 			# SATA1 (SSD0)
 			register "SataPortsEnable[1]" = "1"
@@ -298,16 +179,6 @@ chip soc/intel/tigerlake
 				device generic 0 on end
 			end
 		end
-		device ref pch_espi on
-			register "gen1_dec" = "0x000c0081"
-			register "gen2_dec" = "0x00040069"
-			register "gen3_dec" = "0x00fc0E01"
-			register "gen4_dec" = "0x00fc0F01"
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end
-		device ref p2sb on end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
 			# PMC.MUX device in the ACPI hierarchy.
@@ -323,10 +194,5 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device ref hda on
-			register "PchHdaAudioLinkHdaEnable" = "1"
-		end
-		device ref smbus on end
-		device ref fast_spi on end
 	end
 end

src/mainboard/system76/tgl-u/variants/galp5/board_info.txt

@@ -0,0 +1,2 @@
+Board name: galp5
+Release year: 2020

src/mainboard/system76/tgl-u/variants/galp5/gpio.c

@@ -1,24 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
+#include <mainboard/gpio.h>
 #include <soc/gpio.h>
 
-#define DGPU_RST_N	GPP_U4
-#define DGPU_PWR_EN	GPP_U5
-#define DGPU_GC6	GPP_D2
-#define DGPU_SSID	0x40181558
-
-#ifndef __ACPI__
-
-static const struct pad_config early_gpio_table[] = {
-	PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
-	PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
-	PAD_CFG_GPO(GPP_U4, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
-};
-
 static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
 	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
@@ -229,6 +213,7 @@ static const struct pad_config gpio_table[] = {
 	//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
 };
 
-#endif /* __ACPI__ */
-
-#endif /* MAINBOARD_GPIO_H */
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_GPO(GPP_U4, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+

src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_U4
+#define DGPU_PWR_EN	GPP_U5
+#define DGPU_GC6	GPP_D2
+#define DGPU_SSID	0x40181558
+
+#endif

src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb

@@ -1,21 +1,4 @@
 chip soc/intel/tigerlake
-	register "common_soc_config" = "{
-		// Touchpad I2C bus
-		.i2c[0] = {
-			.speed = I2C_SPEED_FAST,
-			.rise_time_ns = 80,
-			.fall_time_ns = 110,
-		},
-	}"
-
-# ACPI (soc/intel/tigerlake/acpi.c)
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
-
-	# Enable s0ix, required for TGL-U
-	register "s0ix_enable" = "1"
-
-# CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits
 	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
 		.tdp_pl1_override = 28,
@@ -26,86 +9,14 @@ chip soc/intel/tigerlake
 		.tdp_pl2_override = 51,
 	}"
 
-# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
-	# Enable C6 DRAM
-	register "enable_c6dram" = "1"
-
-	# System Agent dynamic frequency support
-	register "SaGv" = "SaGv_Enabled"
-
-# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
-	# Acoustic settings
-	register "AcousticNoiseMitigation" = "1"
-	register "SlowSlewRate" = "SLEW_FAST_8"
-	register "FastPkgCRampDisable" = "1"
-
-	# FIVR configuration
-	#   Read EXT_RAIL_CONFIG to determine bitmaps
-	#     sudo devmem2 0xfe0011b8
-	#     0x0
-	#   Read EXT_V1P05_VR_CONFIG
-	#     sudo devmem2 0xfe0011c0
-	#     0x1a42000
-	#   Read EXT_VNN_VR_CONFIG0
-	#     sudo devmem2 0xfe0011c4
-	#     0x1a42000
-	# TODO: v1p05 voltage and vnn icc max?
-	register "ext_fivr_settings" = "{
-		.configure_ext_fivr = 1,
-		.v1p05_enable_bitmap = 0,
-		.vnn_enable_bitmap = 0,
-		.v1p05_supported_voltage_bitmap = 0,
-		.vnn_supported_voltage_bitmap = 0,
-		.v1p05_icc_max_ma = 500,
-		.vnn_sx_voltage_mv = 1050,
-	}"
-
-	# Read LPM_EN, make sure to invert the bits
-	register "LpmStateDisableMask" = "
-		LPM_S0i2_1 |
-		LPM_S0i2_2 |
-		LPM_S0i3_1 |
-		LPM_S0i3_2 |
-		LPM_S0i3_3 |
-		LPM_S0i3_4
-	"
-
-	# Thermal
-	register "tcc_offset" = "12"
-
-	# Enable CNVi BT
-	register "CnviBtCore" = "true"
-
-# PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "PMC_GPP_A"
 	register "pmc_gpe0_dw1" = "PMC_GPP_R"
 	register "pmc_gpe0_dw2" = "PMC_GPD"
 
-# Actual device tree
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
 	device domain 0 on
 		subsystemid 0x1558 0x4018 inherit
 
-		#From CPU EDS(575683)
-		device ref system_agent on end
-		device ref igpu on
-			# DDIA is eDP
-			register "DdiPortAConfig" = "1"
-			register "DdiPortAHpd" = "1"
-			register "DdiPortADdc" = "0"
-
-			# DDIB is HDMI
-			register "DdiPortBConfig" = "0"
-			register "DdiPortBHpd" = "1"
-			register "DdiPortBDdc" = "1"
-
-			register "gfx" = "GMA_DEFAULT_PANEL(0)"
-		end
-		device ref dptf on end
 		device ref peg on
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
@@ -117,8 +28,6 @@ chip soc/intel/tigerlake
 				device generic 0 on end
 			end
 		end
-		device ref tbt_pcie_rp0 on end # J_TYPEC2
-		device ref gna on end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
 			register "TcssXhciEn" = "1"
@@ -141,7 +50,6 @@ chip soc/intel/tigerlake
 			end
 		end
 
-		# From PCH EDS(576591)
 		device ref south_xhci on
 			# USB2
 			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
@@ -225,38 +133,10 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device ref shared_ram on end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
-		device ref i2c0 on
-			# Touchpad I2C bus
-			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
-			chip drivers/i2c/hid
-				register "generic.hid" = ""PNP0C50""
-				register "generic.desc" = ""FocalTech Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 38 on end
-			end
-		end
-		device ref i2c1 on
-			# TODO: USB-PD?
-			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
-		end
 		device ref i2c2 on
 			# TODO: Pantone ROM?
 			register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
 		end
-		device ref heci1 on end
-		device ref uart2 on
-			# Debug console
-			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
-		end
 		device ref pcie_rp5 on
 			# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
 			register "PcieRpEnable[4]" = "1"
@@ -298,15 +178,6 @@ chip soc/intel/tigerlake
 			register "PcieClkSrcClkReq[1]" = "1"
 			register "PcieRpSlotImplemented[10]" = "1"
 		end
-		device ref pch_espi on
-			register "gen1_dec" = "0x00040069"
-			register "gen2_dec" = "0x00fc0E01"
-			register "gen3_dec" = "0x00fc0F01"
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-		end
-		device ref p2sb on end
 		device ref pmc hidden
 			# The pmc_mux chip driver is a placeholder for the
 			# PMC.MUX device in the ACPI hierarchy.
@@ -322,10 +193,5 @@ chip soc/intel/tigerlake
 				end
 			end
 		end
-		device ref hda on
-			register "PchHdaAudioLinkHdaEnable" = "1"
-		end
-		device ref smbus on end
-		device ref fast_spi on end
 	end
 end

src/mainboard/system76/tgl-u/variants/galp5/romstage.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "gpio.h"
+#include <variant/gpio.h>
 #include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>

src/mainboard/system76/tgl-u/variants/lemp10/board_info.txt

@@ -0,0 +1,2 @@
+Board name: lemp10
+Release year: 2020