This fixes a few "cross-reference target not found" warnings from MyST
parser. In these cases, the relative path to the target markdown
document was incorrect.
Change-Id: I5d01deacc3ba7401faba30fc832e2357d4aedad8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83383
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This board has a DVI-I connector, which supports both digital and analog
display outputs. The I2C bus to retrieve the EDID is shared between both
outputs, so `select GFX_GMA_ANALOG_I2C_HDMI_B` to describe this.
Can't currently test this due to lack of hardware.
Change-Id: Ib8239917e2f7ee5bb982621752ec406c2d3ca302
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82753
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove m4 as it will be installed automatically by flex and bison.
Change-Id: Ifb748e5aaabb96825813ddb92cf28d2ea7bdcbf9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
With commit 238ff1e9c7 ("payloads/ipxe: Prefix iPXE options with "IPXE"
instead "PXE""), the prefix for iPXE related Kconfig identifiers was
unified to "IPXE". So rename the identifier for the TRUST_CMD option as
well, which was introduced later.
Change-Id: I918358b859003503526ba7849494bb23f8c893fd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83361
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 4a8d73d6a4 ("Makefile.mk: Remove bc dependency") broke the left
shift, since the expr tool does not support shifting operations.
This patch uses the left shift operator inside arithmetic expansion.
Every posix shell should support this.
Tested:
Build amd/birman mainboard and check that the soft-fuse parameter
doesn't change.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If3b29dae727875b0788100a2cb02c86736ffaf8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83377
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Chrome EC currently supports two ways to read battery strings on
ACPI platforms:
* Read up to 8 bytes from EC shared memory BMFG, BMOD, ...
* Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from
the response. This is assumed to be exclusively controlled by the OS,
because host commands' use of buffers is prone to race conditions.
To support readout of longer strings via ACPI mechanisms, this change
adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473)
and allows ACPI firmware to read strings of arbitrary length (currently
limited to 64 characters in the implementation) from the EC and to
determine whether this function is supported by the EC (falling back to
shared memory if not).
BUG=b:339171261
TEST=on yaviks, the EC console logs FIFO readout messages when used in
ACPI and correct strings are shown in the OS. If EC support is
removed, correct strings are still shown in the OS.
BRANCH=nissa
Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
bc was added as dependency in commit 229e021110 ("Makefile.inc: Add left shift macro")
bc is not stated as dependency in our docs (e.g. package installation).
If you don't have bc installed you can easily get false positives on
coreboot builds. For example you build a mainboard and coreboot tells
you the build succeeded, even though you don't have bc installed.
This patch is from julius comment on CB:21601.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I6ab4bc2bd7a45e84b923d4fe7ec473e6c7db2146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These fields are documented in the Alder Lake-S Client Platform SPI
Programming Guide, but they are not presented in the Skylake-LP
Client Platform SPI Programming Guide
Change-Id: I624fe5cb28aa3cb207bc48aa8d31b2a71b70bcf2
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a new fw config field to determine which firmware edition shall be
flashed to the PDC.
BUG=b:334793686
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
getopt() optarg value can be used without duplicaing if it is not
modified, as it is the case here.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie5a27f64077af1c04b06732cd601145b8becacfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70525
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Autoport determines the mainboard vendor and board names based on DMI
entries, which sometimes doesn't result in the most obvious name. In
addition, newcomers may not be familiar with coreboot's directory
structure and have no idea where to look. Print out the absolute patch
of the generated sources once autoport finishes so that it is easier to
locate the files.
Change-Id: I4ba00484ac57355d7539fa6e36e0e6df62719f8a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83344
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register
format and thus mainboards using using these platforms have similar
gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so
that it other chipsets added to autoport can use it.
This was originally written by Iru Cai in his Haswell autoport patch in
CB:30890; I have simply split out the code to a separate commit as it is
a separate logical change.
TEST=Generated output is identical before and after this patch when run
against logs from a Dell Latitude E6430
Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When starting a nested instance Make communicates information on the
number of jobs and how to synchronize difference instances via MAKEFLAGS
variable. Explicitly overwriting it when invoking
payloads/external/iPXE/Makefile ends up forcing serial build of iPXE.
iPXE builds hundreds of files and its dependency generation is done
separately from compilation making the whole process take couple minutes
on a single CPU (which becomes several seconds if large enough number of
CPUs is available).
iPXE seems to have Make-based build system that has no problems with
parallel build and not utilizing that effectively turns it into a
bottleneck when building a coreboot image in parallel.
It's unclear whether MAKEFLAGS= was even added for any particular
purpose. It doesn't prevent child instances from using variables of
parents, nor it prevents child instance from running in parallel
(because it's still passed as an environment variable that's processed
prior of variable assignments on command-line), but it does prevent
grandchild instance from running in parallel (actual iPXE's Makefile).
MFLAGS contains flags from MAKEFLAGS and isn't used implicitly by Make,
so no need to clear it either because iPXE doesn't use it.
Change-Id: Iac00e2f86d160793d3217e00ddc5012202b3196a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable
the MPHY clock in the SKU2 configuration to ensure that S0ix functions
normally.
BUG=b:350609955
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Use the PCI_DEVFN macro to make the calculation of the ivhd->device_id
value a bit clearer.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b7949ad3524790e7d7d527c488a32e785f55bc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83343
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a new domika variant which is a Twin Lake platform.
This variant uses Yavilla board mounted with the Twin Lake SOC and hence
the plan is to reuse the existing yavilla code.
BUG=b:350399367
BRANCH=firmware-nissa-15217.B
TEST=build, and boot into OS
Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Domain device objects are created with HID/CID/UID/_OSC/_PXM
Dynamic domain SSDT generation could benefit the support of SoCs with
multiple SKUs, or the case where one set of codes supports multiple
SoCs. One possible side-effect might be the extra performance cost for
generating these tables, which should not bring big impact on high
performance server CPUs.
GNR codes run with dynamic domain SSDT generation to fit for both
GraniteRapids and SierraForest SoCs.
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB
Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Already included <types.h> is supposed to provide <limits.h>. See
`Documentation/contributing/coding_style.md` section `Headers and includes`
Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc.
Reason for revert: The version downloaded does not match the version
that is printed out when executing `iasl --version`. coreboot notices
that and refuses to compile QEMU-Q35 mainboard. I tested it on 2
different PCs.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83296
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This is a rudimentary port of this board. It was done with Haswell
Autoport, wherein some adjustments for Broadwell were made
(Thanks to Angel Pons!).
The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version
2.20 of the vendor firmware.
Working:
- Broadwell MRC.bin
- S3 suspend and resume
- All DIMM slots
- Libgfxinit
- HDMI-Out Port
- DVI-I Port (including passive DVI to VGA adapter)
- USB 2.0 Ports
- USB 3.1 Gen1
- RJ-45 LAN Port
- SATA3 6.0 Gb/s Connectors
- m.2 PCIe SSD
- mPCIe WiFi slot
- x16 PCIe slot
- USB 3.1 Gen1 Header
- Front Panel Audio Connector
- edk2
Not yet tested:
- SATA Express 10 Gb/s Connector
- HDMI-In Port
- DisplayPort 1.2
- Optical SPDIF Out Port
- PS/2 Mouse/Keyboard Port
- USB 2.0 Headers
Not working:
- Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6:
Add new mainboard)
Special thanks to Angel Pons for guiding me through the process of
porting this board and pushing it to Gerrit!
Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:348345301
BRANCH=firmware-rex-15709.B
TEST=BRDS method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the configuration of 320MHz Bandwidth per MCC based on
countries. The implementation follows document #559910 Intel
Connectivity Platforms BIOS Guidelines revision 8.3.
BUG=b:333804562
BRANCH=firmware-rex-15709.B
TEST=WBEM method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides
ability to utilize increased device Transmit power capability for
Bluetooth applications in coordination with Wi-Fi adhering to product
SAR limit when Bluetooth and Wi-Fi run together.
This commit introduces a `bluetooth_companion' field to the generic
Wi-Fi drivers chip data. This field can be set in the board design
device tree to supply the bluetooth device for which the BRDS function
must be created.
This feature is required for Meteor Lake rex karis variant.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:348345301
BRANCH=firmware-rex-15709.B
TEST=BRDS method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM!
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- both RJ-45 Gigabit LAN Ports
- USB 2.0 Ports
- USB 3.1 Gen1 Ports
- both USB 3.1 Gen1 headers
- HD Audio Jack (audio output)
- all six SATA3 6.0 Gb/s connectors by Intel
- all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061
- all three PCI Express 3.0 x16 slots
- PCI Express 2.0 x1 slot
- half mini-PCI Express slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection via jumper
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
not (yet) working:
- Front panel audio connector
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config
GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG,
we remove GERALT_USE_MAX98390 from Kconfig.
BUG=b:345629159
BRANCH=none
TEST=emerge-GERALT coreboot
TEST=Verify beep function through deploy in depthcharge successfully.
Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Fast boot will used pre-saved hardware configuration data to
accelerate the boot process, e.g. DDR training is skipped by using
pre-saved training data. Enable fast boot on cold and warm resets
by default.
Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
If BMP_LOGO is set, currently display_init_required() will always return
1, so that platform code will always initialize display. However, that
information isn't passed to vboot, which may result in unnecessary extra
reboots, for example when the payload needs to request display init (by
vb2api_need_reboot_for_display()).
Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to
tell vboot that "display is available on this boot", enable it by
default if BMP_LOGO is set.
BUG=b:345085042
TEST=none
BRANCH=none
Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Working:
- Both DIMM slots
- All Rear USB 2.0 ports
- Integrated graphics (libgfxinit)
- Realtek RTL8111F GbE
- Flashing internally with flashrom (Note: Works from stock too
due to Gigabyte not following Intel recommendations,
confusing ME)
- SeaBIOS (1.16.3) to boot Arch Linux Installer
- EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
- Audio output (green jack, rear)
- S3 suspend/resume
- VBT
Untested for now (i.e. should work, will eventually test):
- EHCI debug
- Front USB 2.0 ports
- The other audio jacks
- PCIe ports
- Non-Linux OSes
Untestable (i.e. cannot test due to unavailable hardware):
- PS/2 port
- Serial port
- SATA ports
Not working:
- USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
so its firmware needs to be loaded on each boot. However,
documentation about the (chip-specific) firmware loading procedure
is nowhere to be found.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <me@pugzarecute.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This change skips the ME firmware version logging in
print_me_fw_version() if the ME firmware SKU is detected as Lite SKU.
The reasoning is that the RO (BP1) and RW (BP2) versions are already
logged by the cse_print_boot_partition_info() function for Lite SKUs,
making the additional log redundant.
The check for the Lite SKU has been moved to print_me_fw_version(),
where the decision to print the version is made, instead of in
get_me_fw_version(), where the version information is retrieved.
TEST=Able to build and boot google/rex.
w/o this patch:
[DEBUG] ME: Version: Unavailable
w/ this patch:
Unable to see such debug msg.
Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This change modifies the get_me_fw_version() function to be statically
scoped within src/soc/intel/common/block/cse/cse.c, as it is only used
by the print_me_fw_version() function in the same file.
The function declaration is also removed from intelblocks/cse.h.
The order of the function definitions in cse.c was also changed to be
more logical, with the now static helper function get_me_fw_version()
defined first, before it is used.
TEST=Able to build google/rex.
Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the ME status reporting functionality
(dump_me_status, print_me_fw_version) in the CSE driver when
SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined.
This is likely intended for platforms or configurations where the
CSE communication is only limited to payload.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I5e360408a7847968117df475ff244d79ceafa23f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch skips the ISH firmware version print when CSE sync is done
by payload. The payload is responsible to dump the ISH version as
ISH version resides into the CSE boot partition table.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch skips the CSE firmware version print when CSE sync is done
by payload. The payload is responsible to dump the CSE version.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Refactor CSE lite End-of-Post (EOP) configs to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE EOP operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_SEND_EOP_EARLY
- SOC_INTEL_CSE_SEND_EOP_LATE
- SOC_INTEL_CSE_SEND_EOP_ASYNC
- SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor CSE lite configs (specifically CSE sync related) to support
the alternative of sending CSE communication from the payload.
When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE sync operations and rely on the payload CSE
driver implementation.
The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_LITE_PSR
- SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
- SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
- SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This reverts commit 6ab188ee6c99b1d9924b607d7e939d91e35014ec.
This breaks the build using a slightly older toolchain that doesn't know
this option yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bdc909c0e53b5353743dca521c963bbec792f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83311
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
