Set these values in Kconfig like other boards so they do not need to be
set in the config file passed to defconfig.
Change-Id: I70640824581c117e5237edf74a7cbab6705e5e68
Partially revert 37c69a0123 to restore USB-C and likely TBT
functionality on galp3-c.
Fixes: 37c69a0123 ("Update whl-u to match cml-u")
Change-Id: I6fc189b3185d51cd8e67ae2d1eedef65a6049a12
This reverts commit c1e0229094.
This change breaks the touchpad on oryp6. We will change these as-needed
if it proves to resolve issues, not just because Microsoft says so.
Upstream is moving towards having registers set within their relevant
device. Do this now to reduce the diff for upstreaming and later syncing
changes back.
Does not touch the TGL boards or lemp9, which have most of the changes.
- Move registers to devices
- Remove unneeded registers
- Remove extra comments
Change-Id: I8cd54d428493981538722e9fe6a8f3ff2918a041
- Remove the comments, which were copied from the header
- Remove the dq entries for LPDDR, which are not used
- Allow higher memory speeds on oryp5
Change-Id: Ied41e9aad832c19344f92845b0d8d4bdab7e1ac8
The `clear` command for SMMSTORE version 1 does not require a parameter.
Change-Id: I992b7ce5962bf7ee62b7e1970ae7aa1b975ef42e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Two configuration files are added:
1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode
2. MT53E1G32D2NP-046-4GB: new single rank mode
Also initialize the rank number field 'rank_num' for all configs.
BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fw_config field SPI_SPEED is not used for zork devices.
To define SAR config, use the fw_config bit[23..26].
Then vilboz can loaded different WiFi SAR table for different SKUs.
BUG=b:176858126, b:176751675, b:176538384
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add code to collect all required information and generate ACPI CRAT
table entries. Publish tables generated from cb, rather than use the
tables created by FSP binary.
BUG=b:155307433
TEST=Boot trembyle and compare coreboot generated tables with tables
that FSP published previously.
BRANCH=Zork
Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Do LPC/eSPI pad configuration at board-level to match other platforms.
Early gpio configuration was done in romstage, while LPC pads were
configured in bootblock. Instead of adding another dedicated gpio table
for bootblock, move early gpio configuration completely to bootblock on
these boards. This won't hurt, since there is no code touching the pads
in between.
The soc code gets dropped in CB:49410.
Change-Id: I2a614afb305036b0581eac8ed6a723a3f80747b3
Tested-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
