mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Change-Id: I2df115c323a4fa50ffac191461060df9059381f7 Signed-off-by: Tim Crawford <tcrawford@system76.com>
mb/system76/tgl-u: galp5: Re-add CPU PCIe RTD3
2023-01-19 09:15:55 -07:00 · 2023-01-19 09:15:44 -07:00 · 2023-01-19 09:15:33 -07:00 · 2023-01-19 09:13:54 -07:00 · 2023-01-17 07:54:54 -07:00 · 2023-01-17 07:54:54 -07:00
37 changed files with 113 additions and 32 deletions
--- a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
+++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865d1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
--- a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c
+++ b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865e1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
--- a/src/mainboard/system76/adl-p/variants/darp8/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/darp8/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256,
 	0x15587716,
-	11,
+	12,
 	AZALIA_SUBVENDOR(0, 0x15587716),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
@@ -20,8 +20,14 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
+				register "srcclk_pin" = "0" # SSD2_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
--- a/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x15584041, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15584041),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
@@ -18,8 +18,14 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST#
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
--- a/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256,
 	0x15587718,
-	11,
+	12,
 	AZALIA_SUBVENDOR(0, 0x15587718),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
@@ -18,8 +18,14 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
+				register "srcclk_pin" = "0" # SSD0_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref tcss_xhci on
 			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
--- a/src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155867f5, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155867f5),
 	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
--- a/src/mainboard/system76/bonw14/hda_verb.c
+++ b/src/mainboard/system76/bonw14/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x15587714, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
--- a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c
+++ b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581404, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581404),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c
+++ b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581403, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581403),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c
+++ b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC269VC */
 	0x10ec0269, /* Vendor ID */
 	0x15588560, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15588560),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
 	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
--- a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c
+++ b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15588520, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15588520),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3050/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x15585017, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15585017),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c
+++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x155850e2, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155850e2),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/gaze17/variants/3050/hda_verb.c
+++ b/src/mainboard/system76/gaze17/variants/3050/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x1558866d, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x1558866d),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/gaze17/variants/3060/hda_verb.c
+++ b/src/mainboard/system76/gaze17/variants/3060/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC256 */
 	0x10ec0256, /* Vendor ID */
 	0x1558867c, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x1558867c),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c
+++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC269VC */
 	0x10ec0269, /* Vendor ID */
 	0x15581303, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581303),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170120),
 	AZALIA_PIN_CFG(0, 0x15, 0x02211010),
--- a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c
+++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC269VC */
 	0x10ec0269, /* Vendor ID */
 	0x15581414, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581414),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170120),
 	AZALIA_PIN_CFG(0, 0x15, 0x02211010),
--- a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c
+++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC269VC */
 	0x10ec0269, /* Vendor ID */
 	0x15581313, /* Subsystem ID */
-	11, /* Number of entries */
+	12, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581313),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170120),
 	AZALIA_PIN_CFG(0, 0x15, 0x02211010),
--- a/src/mainboard/system76/lemp9/hda_verb.c
+++ b/src/mainboard/system76/lemp9/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581401, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581401),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/oryp5/hda_verb.c
+++ b/src/mainboard/system76/oryp5/hda_verb.c
@@ -6,7 +6,7 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155896e1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155896e1),
 	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC
--- a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c
+++ b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155850d3, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155850d3),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
--- a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c
+++ b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865e5, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865e5),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
--- a/src/mainboard/system76/oryp8/hda_verb.c
+++ b/src/mainboard/system76/oryp8/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865f1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865f1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
--- a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c
+++ b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x155851a1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155851a1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
@@ -21,6 +21,12 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
 			register "PcieClkSrcClkReq[0]" = "0"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
--- a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c
+++ b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15584018, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15584018),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -21,6 +21,12 @@ chip soc/intel/tigerlake
 			# PCIe PEG0 x4, Clock 0 (SSD1)
 			register "PcieClkSrcUsage[0]" = "0x40"
 			register "PcieClkSrcClkReq[0]" = "0"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref north_xhci on # J_TYPEC2
 			register "UsbTcPortEn" = "1"
--- a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x155814a1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155814a1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
@@ -22,6 +22,12 @@ chip soc/intel/tigerlake
 			# Despite the name, SSD2_CLKREQ# is used for SSD1
 			register "PcieClkSrcUsage[3]" = "0x40"
 			register "PcieClkSrcClkReq[3]" = "3"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
+				register "srcclk_pin" = "3" # SSD2_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref north_xhci on # J_TYPEC1
 			register "UsbTcPortEn" = "1"
@@ -135,7 +141,7 @@ chip soc/intel/tigerlake
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
-				register "srcclk_pin" = "0"
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
 				device generic 0 on end
 			end
 		end
--- a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c
+++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581325, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581325),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c
+++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c
@@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581323, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581323),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -251,6 +251,9 @@ static enum dev_sleep_states get_min_sleep_state(const struct device *dev)
 		return DEFAULT_CPU_D_STATE;

 	case DEVICE_PATH_PCI:
+		/* skip external buses*/
+		if (dev->bus->secondary != 0)
+			return NONE;
 		for (size_t i = 0; i < ARRAY_SIZE(min_pci_sleep_states); i++)
 			if (min_pci_sleep_states[i].pci_dev == dev->path.pci.devfn)
 				return min_pci_sleep_states[i].min_sleep_state;
--- a/src/soc/intel/alderlake/acpi/pcie.asl
+++ b/src/soc/intel/alderlake/acpi/pcie.asl
@@ -323,3 +323,13 @@ Device (PEG2)
 	Name (_ADR, 0x00010000)
 }
 #endif
+
+Device (SRAM)
+{
+	Name (_ADR, 0x00140002)
+}
+
+Device (HEC1)
+{
+	Name (_ADR, 0x00160000)
+}
--- a/src/soc/intel/alderlake/acpi/serialio.asl
+++ b/src/soc/intel/alderlake/acpi/serialio.asl
@@ -50,6 +50,12 @@ Device (I2C7)
 	Name (_DDN, "Serial IO I2C Controller 7")
 }

+Device (FSPI)
+{
+	Name (_ADR, 0x001f0005)
+	Name (_DDN, "Fast SPI")
+}
+
 Device (SPI0)
 {
 	Name (_ADR, 0x001e0002)
Author	SHA1	Message	Date
Tim Crawford	83083250f9	mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3 Change-Id: I2df115c323a4fa50ffac191461060df9059381f7 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-19 09:15:55 -07:00
Tim Crawford	49c455b353	mb/system76/tgl-u: galp5: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: I7491c4ffd62b284ba47fded70793830f63cb9c5f Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-19 09:15:44 -07:00
Tim Crawford	b3e9fbe971	mb/system76/tgl-u: lemp10: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E-00BCA0) - WD Blue SN580 (WDS500G2B0C-00PXH0) - WD Green SN350 (WDS240G2G0C-00AJM0) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: I8e2d23fff9c89aa1364c5f982d227ec52e3ac8a2 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-19 09:15:33 -07:00
Tim Crawford	ddfd79d8c7	mb/system76: Reset Realtek codec before configuring Change-Id: I64c1fd23f708f77a81fad0bc889f42d4df3f6e61 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-19 09:13:54 -07:00
Anil Kumar	900962f8d5	soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDT HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb: device pci 16.0 alias heci1 on end device pci 14.2 alias shared_sram off end This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel TEST=Built and tested on brya to confirm errors are not seen. BUG=b:260258765 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2023-01-17 07:54:54 -07:00
Eran Mitrani	8f668295e2	soc/intel/alderlake: skip external buses for D-states list The devices in the list that was introduced in commit `c66ea98577` ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>	2023-01-17 07:54:54 -07:00
Tim Crawford	3dacf7f26b	mb/system76/adl-p: darp8: Enable AER on CPU PCIe RP Change-Id: Ia2979038f19e1af536d216b5867db2aeff9558ad	2023-01-12 09:13:19 -07:00
Tim Crawford	d78cc205c2	mb/system76/adl-p: darp8: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: I9251034ccd52d7b7b37358991978933c7b733ca7 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-12 09:13:19 -07:00
Tim Crawford	6734cf0eef	mb/system76/adl-p: galp6: Enable AER on CPU PCIe RP Change-Id: Ia9cb20a73bfc2bc8b856dbcf16d632c8640cc4bb Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-11 12:46:07 -07:00
Tim Crawford	4416e2bc7a	mb/system76/adl-p: galp6: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: I51eec89444cd0b7bc7834ee52c3b17ca0b3bf9ac Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-11 12:46:07 -07:00
Tim Crawford	0a440232f4	mb/system76/adl-p: lemp11: Enable AER on CPU PCIe RP The WD Black SN850X (WDS100T2XD0E) reports corrected RX errors on suspend/resume. Change-Id: I570ce0c392003f5514931272664bb4f9ec3c0803 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-06 13:49:40 -07:00
Tim Crawford	789de6a7d7	mb/system76/adl-p: lemp11: Re-add CPU PCIe RTD3 Tested with the following drives: - Crucial P5 Plus (CT500P5PSSD8) - Kingston KC3000 (SKC3000S/512G) - Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500) - Samsung 970 EVO (MZ-V7E250) - Samsung 970 EVO Plus (MZ-V7S250) - Samsung 980 PRO (MZ-V8P2T0) - WD Black SN850X (WDS100T2XD0E) - WD Blue SN580 (WDS500G2B0C) - WD Green SN350 (WDS240G2G0C) Test: - PCH asserts `SLP_S0#` during suspend (power LED blinks) - `slp_s0_residency_usec` increases after suspend Change-Id: Ib94665f2504200388c093600e8b359fde092bd79 Signed-off-by: Tim Crawford <tcrawford@system76.com>	2023-01-06 13:49:40 -07:00
Eran Mitrani	a6635a0e50	soc/intel/adl/acpi: add FSPI to DSDT A previous CL ("Add missing ACPI device path names", commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors from the Kernel on Brya devices (see Tim's comment on patchset 8): > ACPI Error: AE_NOT_FOUND, While resolving a named reference > package element - \_SB_.PCI0.FSPI FSPI is defined in src/soc/intel/alderlake/chipset.cb: device pci 1f.5 alias fast_spi on end This CL adds the corresponding FSPI device to the DSDT to prevent the error mentioned above. TEST=Built and tested on brya by verifying the error is gone. BUG=b:231582182 Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2022-12-29 11:41:41 -07:00