mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Change-Id: I2df115c323a4fa50ffac191461060df9059381f7 Signed-off-by: Tim Crawford <tcrawford@system76.com>
mb/system76/tgl-u: galp5: Re-add CPU PCIe RTD3
2023-01-19 09:15:55 -07:00 · 2023-01-19 09:15:44 -07:00 · 2023-01-19 09:15:33 -07:00 · 2023-01-19 09:13:54 -07:00 · 2023-01-17 07:54:54 -07:00 · 2023-01-17 07:54:54 -07:00
413 changed files with 12220 additions and 1461 deletions
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,63 +1,63 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
--- a/Documentation/coreboot_logo.bmp
+++ b/Documentation/coreboot_logo.bmp
--- a/Documentation/mainboard/hp/z220_sff.md
+++ b/Documentation/mainboard/hp/z220_sff.md
@@ -44,8 +44,17 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.

-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
-as otherwise there's not enough space near the flash.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
+otherwise there's not enough space near the flash.
+
+In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
+be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
+interfere.
+
+## Side note
+The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
+that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
+even interchangeable, so should do coreboot images built for them.

 ## Technology

@@ -66,5 +75,6 @@ as otherwise there's not enough space near the flash.
 ```

 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
+[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -202,16 +202,20 @@ The boards in this section are not real mainboards, but emulators.
 - [Bonobo Workstation 14](system76/bonw14.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
+- [Darter Pro 8](system76/darp8.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
+- [Lemur Pro 11](system76/lemp11.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
+- [Oryx Pro 9](system76/oryp9.md)

 ## Texas Instruments

--- a/Documentation/mainboard/system76/darp8.md
+++ b/Documentation/mainboard/system76/darp8.md
@@ -0,0 +1,82 @@
+# Syste76 Darter Pro 8 (darp8)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1240P
+  - Intel Core i7-1260P
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 15.6" 1920x1080@60Hz LCD
+  - 1x HDMI
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (OZ711LV2)
+- USB
+  - 1x USB-C Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 2.0 Type-A
+- Dimensions
+  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | GigaDevice          |
+---------------------+---------------------+
+| Model               | GD25B256E           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Winbond             |
+---------------------+---------------------+
+| Model               | W25Q256.V           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U19) is above the left DIMM slot.
--- a/Documentation/mainboard/system76/gaze17.md
+++ b/Documentation/mainboard/system76/gaze17.md
@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | GigaDevice          |
+---------------------+---------------------+
+| Model               | GD25B256E           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.
--- a/Documentation/mainboard/system76/lemp11.md
+++ b/Documentation/mainboard/system76/lemp11.md
@@ -0,0 +1,62 @@
+# System76 Lemur Pro 11 (lemp11)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1235U
+  - Intel Core i7-1255U
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 14.0" 1920x1080@60Hz LCD
+  - 1x HDMI 2.1
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
+  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
+- Networking
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5 mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 3.2 (Gen 1) Type-A
+- Dimensions
+    - 1.65cm x 32.2cm x 21.68cm, 1.15kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Macronix            |
+---------------------+---------------------+
+| Model               | MX25L25673G         |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U41) is left of the DIMM slot.
--- a/Documentation/mainboard/system76/oryp9.md
+++ b/Documentation/mainboard/system76/oryp9.md
@@ -0,0 +1,44 @@
+# System76 Oryx Pro 9 (oryp9)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+- Sound
+- Storage
+- USB
+- Dimensions
+  - 35.8cm x 24.0cm x 2.49cm, 2.4kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Macronix            |
+---------------------+---------------------+
+| Model               | MX25L25673G         |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.
--- a/Documentation/security/vboot/list_vboot.md
+++ b/Documentation/security/vboot/list_vboot.md
@@ -211,6 +211,7 @@
 - Marzipan
 - Mrbland
 - Pazquel
+- Pazquel360
 - Pompom
 - Quackingstick
 - Wormdingler
--- a/6
+++ b/6
@@ -362,7 +362,11 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/msi/h81m-p33/

-
+MSI MS-7D25 MAINBOARDS
+M:	Michał Żygowski <michal.zygowski@3mdeb.com>
+M:	Michał Kopeć <michal.kopec@3mdeb.com>
+S:	Maintained
+F:	src/mainboard/msi/ms7d25/

 OCP DELTALAKE MAINBOARD
 M:	Arthur Heymans <arthur@aheymans.xyz>
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -173,14 +173,16 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
 		CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
+		CONFIG_TIANOCORE_FULL_SCREEN_SETUP=$(CONFIG_TIANOCORE_FULL_SCREEN_SETUP) \
 		CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
 		CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
 		CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
-		CONFIG_TIANOCORE_SERIAL_SUPPORT=$(TIANOCORE_SERIAL_SUPPORT) \
+		CONFIG_TIANOCORE_SERIAL_SUPPORT=$(CONFIG_TIANOCORE_SERIAL_SUPPORT) \
 		CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
+		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_V2) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
--- a/payloads/external/tianocore/Kconfig
+++ b/payloads/external/tianocore/Kconfig
@@ -52,7 +52,7 @@ config TIANOCORE_REPOSITORY

 config TIANOCORE_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
+	default "origin/uefipayload_202207" if TIANOCORE_UEFIPAYLOAD
 	default "origin/master" if TIANOCORE_UPSTREAM
 	default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
 	help
@@ -94,17 +94,25 @@ config TIANOCORE_ABOVE_4G_MEMORY

 config TIANOCORE_BOOTSPLASH_FILE
 	string "Tianocore Bootsplash path and filename"
-	default "bootsplash.bmp"
+	default "Documentation/coreboot_logo.bmp"
 	help
-	  Select this option if you have a bootsplash image that you would
-	  like to be used. If this option is not selected, the default
+	  The path and filename of the file to use as graphical bootsplash
+	  image. If this option is not configured, the default
 	  coreboot logo (European Brown Hare) will used.

-	  The path and filename of the file to use as graphical bootsplash
-	  image. The file must be an uncompressed BMP, in BMP 3 format.
+	  You can use any image format supported by imagemagick, a list of which
+	  can be found [here](https://imagemagick.org/script/formats.php).

-	  Linux can create these with the below command:
-	      `convert splosh.bmp BMP3:splash.bmp`
+	  The build process will automatically convert this to the format that
+	  EDK2 requires, which is an uncompressed BMP, in BMP3 format. It does
+	  this using imagemagick (`convert splosh.bmp BMP3:splash.bmp`).
+
+	  The newly formatted file will be the dimensions size as the original
+	  one.
+
+	  The build process will automatically do this conversion, so it can
+	  be supplied with any format that imagemagick can process (which is
+	  pretty much any!).

 	  This image will also be used as the BGRT boot image, which may
 	  persist through your OS boot process.
@@ -150,6 +158,14 @@ config TIANOCORE_FOLLOW_BGRT_SPEC
 	  the Boot Logo 38.2% will be vertically centered 38.2% from
 	  the top of the display.

+config TIANOCORE_FULL_SCREEN_SETUP
+	bool "Use the full screen for the edk2 frontpage"
+	default y
+	help
+	  Allow edk2 to use the full screen to display the frontpage
+	  (aka "Boot Menu"). With this option disable, it will be
+	  limited to 640x480.
+
 config TIANOCORE_HAVE_EFI_SHELL
 	bool "Include EFI Shell"
 	default y
@@ -194,15 +210,14 @@ config TIANOCORE_USE_8254_TIMER

 endif

-if TIANOCORE_CUSTOM
-
 config TIANOCORE_CUSTOM_BUILD_PARAMS
 	string "TianoCore additional custom build parameters"
+	default "-D VARIABLE_SUPPORT=SMMSTORE" if TIANOCORE_UEFIPAYLOAD && SMMSTORE_V2
 	help
-	  Custom TianoCore forks may have different sets of parameters passed
-	  to build command. You may specify additional parameters to the custom
-	  TianoCore build
-
-endif
+	  edk2 has build options that are not modified by coreboot, and these can be
+	  found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support
+	  additional build options that should have been upstreamed but have not.
+
+	  This option can support both macros `-D` and Pcds `--pcd`.

 endif
--- a/payloads/external/tianocore/Makefile
+++ b/payloads/external/tianocore/Makefile
@@ -78,16 +78,18 @@ BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
 endif
 # SD_MMC_TIMEOUT		= 1000000
 ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
-BUILD_STR += -D SD_MMC_TIMEOUT=$(call int-multiply, $(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) 1000)
+BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) * 1000)) )
 endif
 #
-# EDKII has the below PCDs that are revalant to coreboot:
+# EDKII has the below PCDs that are relevant to coreboot:
 #
 # Allows EDKII to use the full framebuffer
+ifeq ($(CONFIG_TIANOCORE_FULL_SCREEN_SETUP),y)
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
 BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
+endif
 #
 # The below are legacy options only available in CorebootPayloadPkg:
 #
@@ -104,11 +106,9 @@ endif # CONFIG_TIANOCORE_COREBOOTPAYLOAD

 bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))

-ifeq ($(CONFIG_TIANOCORE_CUSTOM),y)
 ifneq ($(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS),)
 BUILD_STR += $(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS)
 endif
-endif

 all: clean build

@@ -136,18 +136,37 @@ update: $(project_dir)
 		fi; \
 		git submodule update --init --checkout

+logo: $(project_dir)
+	case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
+		"") ;; \
+		/*) convert -background None $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+		*) convert -background None $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+			BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+	esac \
+
 checktools:
-	echo "Checking uuid-dev..."
+	echo -n "EDK2: Checking uuid-dev:"
 	echo "#include <uuid/uuid.h>" > libtest.c
 	echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
-	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
-		( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
+	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo "    Found!" || \
+		( echo "    Not found!"; \
+			echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
 	rm -rf libtest.c libtest
-	echo "Checking nasm..."
-	type nasm > /dev/null 2>&1 && echo " found nasm." || \
-		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
+	echo -n "EDK2: Checking nasm:"
+	type nasm > /dev/null 2>&1 && echo "        Found!" || \
+		( echo "        Not found!"; echo "ERROR: Please install nasm."; exit 1 )
+	echo -n "EDK2: Checking imagemagick:"
+	-convert -size 1x1 xc: test.png &> /dev/null;
+	if [ -f test.png ]; then \
+		rm test.png && echo " Found!"; \
+	else \
+		echo " Not found!"; \
+		echo "ERROR: Please install imagemagick"; \
+		exit 1; \
+	fi

-build: update checktools
+build: update logo checktools
 	echo "   ##### $(project_name) Build Summary #####"
 	echo "   Repository:     $(CONFIG_TIANOCORE_REPOSITORY)"
 	echo "   Branch:         $(CONFIG_TIANOCORE_TAG_OR_REV)"
@@ -160,15 +179,6 @@ build: update checktools
 		-e 's/q /Build:          Quiet/' \
 		-e 's/t /Toolchain:      /'
 	unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
-	if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
-		echo "    Copying custom bootsplash image"; \
-		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
-			/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-			*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
-				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
-		esac \
-	fi; \
 	cd $(project_dir); \
 		export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
 		export WORKSPACE=$(project_dir); \
@@ -188,4 +198,4 @@ clean:
 distclean:
 	rm -rf */

-.PHONY: all update checktools config build clean distclean
+.PHONY: all update checktools config build clean distclean logo
--- a/spd/lp4x/memory_parts.json
+++ b/spd/lp4x/memory_parts.json
@@ -351,6 +351,18 @@
                "ranksPerChannel": 2,
                "speedMbps": 4267
            }
+        },
+        {
+            "name": "H54G68CYRBX248",
+            "attribs": {
+                "densityPerChannelGb": 8,
+                "banks": 8,
+                "channelsPerDie": 4,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 8,
+                "ranksPerChannel": 2,
+                "speedMbps": 4267
+            }
        }
    ]
 }
--- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt
@@ -30,3 +30,4 @@ H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
 MT53E2G32D4NQ-046 WT:C,spd-7.hex
+H54G68CYRBX248,spd-2.hex
--- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt
@@ -30,3 +30,4 @@ H54G56CYRBX247,spd-3.hex
 K4U6E3S4AB-MGCL,spd-1.hex
 K4UBE3D4AB-MGCL,spd-3.hex
 MT53E2G32D4NQ-046 WT:C,spd-10.hex
+H54G68CYRBX248,spd-2.hex
--- a/spd/lp5/memory_parts.json
+++ b/spd/lp5/memory_parts.json
@@ -109,6 +109,16 @@
                "ranksPerChannel": 1,
                "speedMbps": 7500
            }
+        },
+        {
+            "name":  "MT62F2G32D4DS-026 WT:B",
+            "attribs": {
+                "densityPerDieGb": 16,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 7500
+            }
        }
    ]
 }
--- a/spd/lp5/set-0/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -12,3 +12,4 @@ H58G56AK6BX069,spd-3.hex
 MT62F1G32D4DS-031 WT:B,spd-2.hex
 K3LKCKC0BM-MGCP,spd-6.hex
 MT62F1G32D2DS-026 WT:B,spd-7.hex
+MT62F2G32D4DS-026 WT:B,spd-8.hex
--- a/spd/lp5/set-0/spd-8.hex
+++ b/spd/lp5/set-0/spd-8.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 16 22 B5 08 00 00 00 00 0A 01 00 00
+00 00 09 00 00 00 00 00 AB 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 C9 00 C5 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--- a/spd/lp5/set-1/parts_spd_manifest.generated.txt
+++ b/spd/lp5/set-1/parts_spd_manifest.generated.txt
@@ -12,3 +12,4 @@ H58G56AK6BX069,spd-3.hex
 MT62F1G32D4DS-031 WT:B,spd-2.hex
 K3LKCKC0BM-MGCP,spd-5.hex
 MT62F1G32D2DS-026 WT:B,spd-3.hex
+MT62F2G32D4DS-026 WT:B,spd-5.hex
--- a/src/arch/x86/acpi/debug.asl
+++ b/src/arch/x86/acpi/debug.asl
@@ -27,12 +27,12 @@ OperationRegion(CREG, SystemIO, 0x3F8, 8)
 */
 Method(DINI)
 {
-	store(0x83, DLCR)
-	store(0x01, CDAT)	/* 115200 baud (low) */
-	store(0x00, CDLM)	/* 115200 baud (high) */
-	store(0x03, DLCR)	/* word=8 stop=1 parity=none */
-	store(0x03, CMCR)	/* DTR=1 RTS=1 Out2=Off Loop=Off */
-	store(0x00, CDLM)	/* turn off interrupts */
+	DLCR = 0x83
+	CDAT = 1	/* 115200 baud (low) */
+	CDLM = 0	/* 115200 baud (high) */
+	DLCR = 3	/* word=8 stop=1 parity=none */
+	CMCR = 3	/* DTR=1 RTS=1 Out2=Off Loop=Off */
+	CDLM = 0	/* turn off interrupts */
 }

 /*
@@ -41,9 +41,9 @@ Method(DINI)
 */
 Method(THRE)
 {
-	and(CLSR, 0x20, local0)
+	local0 = CLSR & 0x20
 	while (local0 == 0) {
-		and(CLSR, 0x20, local0)
+		local0 = CLSR & 0x20
 	}
 }

@@ -54,7 +54,7 @@ Method(THRE)
 Method(OUTX, 1)
 {
 	THRE()
-	store(Arg0, CDAT)
+	CDAT = Arg0
 }

 /*
@@ -75,11 +75,11 @@ Method(OUTC, 1)
 */
 Method(DBGN, 1)
 {
-	and(Arg0, 0x0f, Local0)
-	if (LLess(Local0, 10)) {
-		add(Local0, 0x30, Local0)
+	Local0 = Arg0 & 0x0f
+	if (Local0 < 10) {
+		Local0 += 0x30
 	} else {
-		add(Local0, 0x37, Local0)
+		Local0 += 0x37
 	}
 	OUTC(Local0)
 }
@@ -136,10 +136,10 @@ Method(DBGO, 1)
 		}
 	} else {
 		Name(BDBG, Buffer(80) {})
-		store(Arg0, BDBG)
-		store(0, Local1)
+		BDBG = Arg0
+		Local1 = 0
 		while (One) {
-			store(GETC(BDBG, Local1), Local0)
+			Local0 = GETC(BDBG, Local1)
 			if (Local0 == 0) {
 				return (0)
 			}
--- a/src/arch/x86/acpi/globutil.asl
+++ b/src/arch/x86/acpi/globutil.asl
@@ -9,7 +9,7 @@ Scope(\_SB) {
 /* string compare functions */
 Method(MIN, 2)
 {
-	if (LLess(Arg0, Arg1)) {
+	if (Arg0 < Arg1) {
 		Return(Arg0)
 	} else {
 		Return(Arg1)
@@ -18,7 +18,7 @@ Method(MIN, 2)

 Method(SLEN, 1)
 {
-	Store(Arg0, Local0)
+	Local0 = Arg0
 	Return(Sizeof(Local0))
 }

@@ -26,36 +26,36 @@ Method(S2BF, 1, Serialized)
 {
 	Local0 = SLEN(Arg0) + 1
 	Name(BUFF, Buffer(Local0) {})
-	Store(Arg0, BUFF)
+	BUFF = Arg0
 	Return(BUFF)
 }

 /* Strong string compare.  Checks both length and content */
 Method(SCMP, 2)
 {
-	Store(S2BF(Arg0), Local0)
-	Store(S2BF(Arg1), Local1)
-	Store(Zero, Local4)
-	Store(SLEN(Arg0), Local5)
-	Store(SLEN(Arg1), Local6)
-	Store(MIN(Local5, Local6), Local7)
+	Local0 = S2BF(Arg0)
+	Local1 = S2BF(Arg1)
+	Local4 = 0
+	Local5 = SLEN(Arg0)
+	Local6 = SLEN(Arg1)
+	Local7 = MIN(Local5, Local6)

-	While(LLess(Local4, Local7)) {
-		Store(Derefof(Local0[Local4]), Local2)
-		Store(Derefof(Local1[Local4]), Local3)
+	While(Local4 < Local7) {
+		Local2 = Derefof(Local0[Local4])
+		Local3 = Derefof(Local1[Local4])
 		if (Local2 > Local3) {
 			Return(One)
 		} else {
-			if (LLess(Local2, Local3)) {
+			if (Local2 < Local3) {
 				Return(Ones)
 			}
 		}
 		Local4++
 	}
-	if (LLess(Local4, Local5)) {
+	if (Local4 < Local5) {
 		Return(One)
 	} else {
-		if (LLess(Local4, Local6)) {
+		if (Local4 < Local6) {
 			Return(Ones)
 		} else {
 			Return(Zero)
@@ -69,17 +69,16 @@ Method(SCMP, 2)
 */
 Method(WCMP, 2)
 {
-	Store(S2BF(Arg0), Local0)
-	Store(S2BF(Arg1), Local1)
-	if (LLess(SLEN(Arg0), SLEN(Arg1))) {
+	Local0 = S2BF(Arg0)
+	Local1 = S2BF(Arg1)
+	if (SLEN(Arg0) < SLEN(Arg1)) {
 		Return(0)
 	}
-	Store(Zero, Local2)
-	Store(SLEN(Arg1), Local3)
+	Local2 = 0
+	Local3 = SLEN(Arg1)

-	While(LLess(Local2, Local3)) {
-		if (LNotEqual(Derefof(Local0[Local2]),
-			Derefof(Local1[Local2]))) {
+	While(Local2 < Local3) {
+		if (Derefof(Local0[Local2]) != Derefof(Local1[Local2])) {
 			Return(0)
 		}
 		Local2++
@@ -92,9 +91,9 @@ Method(WCMP, 2)
 */
 Method(I2BM, 1)
 {
-	Store(0, Local0)
-	if (LNotEqual(ARG0, 0)) {
-		Store(1, Local1)
+	Local0 = 0
+	if (ARG0 != 0) {
+		Local1 = 1
 		Local0 = Local1 << ARG0
 	}
 	Return(Local0)
--- a/src/commonlib/bsd/include/commonlib/bsd/compiler.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
@@ -15,19 +15,25 @@
 #define __aligned(x) __attribute__((__aligned__(x)))
 #endif

-/* Because there may be variables/parameters whose name contains "__unused" in
-   header files of libc, namely musl, names consistent with the ones in the
-   Linux kernel may be a better choice. */
+/*
+ * Because there may be variables/parameters whose name contains "__unused" in
+ * header files of libc, namely musl, names consistent with the ones in the
+ * Linux kernel may be a better choice.
+ */

-/* This is used to mark identifiers unused in all conditions, e.g. a parameter
-   completely unused in all code branch, only present to fit an API. */
+/*
+ * This is used to mark identifiers unused in all conditions, e.g. a parameter
+ * completely unused in all code branch, only present to fit an API.
+ */
 #ifndef __always_unused
 #define __always_unused __attribute__((__unused__))
 #endif

-/* This is used to mark identifiers unused in some conditions, e.g. a parameter
-   only unused in some code branches, a global variable only accessed with code
-   being conditionally preprocessed, etc. */
+/*
+ * This is used to mark identifiers unused in some conditions, e.g. a parameter
+ * only unused in some code branches, a global variable only accessed with code
+ * being conditionally preprocessed, etc.
+ */
 #ifndef __maybe_unused
 #define __maybe_unused __attribute__((__unused__))
 #endif
@@ -52,13 +58,15 @@
 #define __fallthrough __attribute__((__fallthrough__))
 #endif

-/* This evaluates to the type of the first expression, unless that is constant
-   in which case it evaluates to the type of the second. This is useful when
-   assigning macro parameters to temporary variables, because that would
-   normally circumvent the special loosened type promotion rules for integer
-   literals. By using this macro, the promotion can happen at the time the
-   literal is assigned to the temporary variable. If the literal doesn't fit in
-   the chosen type, -Werror=overflow will catch it, so this should be safe. */
+/*
+ * This evaluates to the type of the first expression, unless that is constant
+ * in which case it evaluates to the type of the second. This is useful when
+ * assigning macro parameters to temporary variables, because that would
+ * normally circumvent the special loosened type promotion rules for integer
+ * literals. By using this macro, the promotion can happen at the time the
+ * literal is assigned to the temporary variable. If the literal doesn't fit in
+ * the chosen type, -Werror=overflow will catch it, so this should be safe.
+ */
 #define __TYPEOF_UNLESS_CONST(expr, fallback_expr) __typeof__( \
 	__builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr))

--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -60,7 +60,7 @@ config X2APIC_RUNTIME
 config X2APIC_LATE_WORKAROUND
 	prompt "Use XAPIC for AP bringup, then change to X2APIC"
 	bool
-	depends on PARALLEL_MP && MAX_CPUS < 255
+	depends on PARALLEL_MP && MAX_CPUS < 256
 	help
 	  Choose this option if the platform supports dynamic switching between
 	  XAPIC to X2APIC. The initial Application Processors (APs) are configured
--- a/src/drivers/gfx/nvidia/Kconfig
+++ b/src/drivers/gfx/nvidia/Kconfig
@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
--- a/src/drivers/gfx/nvidia/Makefile.inc
+++ b/src/drivers/gfx/nvidia/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c
--- a/src/drivers/gfx/nvidia/acpi/coffeelake.asl
+++ b/src/drivers/gfx/nvidia/acpi/coffeelake.asl
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"
--- a/src/drivers/gfx/nvidia/acpi/common/dsm.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/dsm.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}
--- a/src/drivers/gfx/nvidia/acpi/common/gpu.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/gpu.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
--- a/src/drivers/gfx/nvidia/acpi/common/nvjt.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}
--- a/src/drivers/gfx/nvidia/acpi/common/power.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/power.asl
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
--- a/src/drivers/gfx/nvidia/acpi/common/utility.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/utility.asl
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}
--- a/src/drivers/gfx/nvidia/acpi/tigerlake.asl
+++ b/src/drivers/gfx/nvidia/acpi/tigerlake.asl
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"
--- a/src/drivers/gfx/nvidia/chip.h
+++ b/src/drivers/gfx/nvidia/chip.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */
--- a/src/drivers/gfx/nvidia/gpu.h
+++ b/src/drivers/gfx/nvidia/gpu.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */
--- a/src/drivers/gfx/nvidia/nvidia.c
+++ b/src/drivers/gfx/nvidia/nvidia.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus Graphics Device")
+	.enable_dev = nvidia_enable
+};
--- a/src/drivers/gfx/nvidia/romstage.c
+++ b/src/drivers/gfx/nvidia/romstage.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -517,21 +517,19 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
 	/* Scope */
 	acpigen_write_scope(scope);

-	if (dev->path.type == DEVICE_PATH_GENERIC) {
-		if (config) {
-			/* Wake capabilities */
-			acpigen_write_PRW(config->wake, ACPI_S3);
+	if (config) {
+		/* Wake capabilities */
+		acpigen_write_PRW(config->wake, ACPI_S3);

-			/* Add _DSD for DmaProperty property. */
-			if (config->is_untrusted) {
-				struct acpi_dp *dsd, *pkg;
+		/* Add _DSD for DmaProperty property. */
+		if (config->is_untrusted) {
+			struct acpi_dp *dsd, *pkg;

-				dsd = acpi_dp_new_table("_DSD");
-				pkg = acpi_dp_new_table(ACPI_DSD_DMA_PROPERTY_UUID);
-				acpi_dp_add_integer(pkg, "DmaProperty", 1);
-				acpi_dp_add_package(dsd, pkg);
-				acpi_dp_write(dsd);
-			}
+			dsd = acpi_dp_new_table("_DSD");
+			pkg = acpi_dp_new_table(ACPI_DSD_DMA_PROPERTY_UUID);
+			acpi_dp_add_integer(pkg, "DmaProperty", 1);
+			acpi_dp_add_package(dsd, pkg);
+			acpi_dp_write(dsd);
 		}
 	}

@@ -603,9 +601,7 @@ void wifi_pcie_fill_ssdt(const struct device *dev)
 		return;

 	wifi_ssdt_write_device(dev, path);
-	const struct device *child = dev->link_list->children;
-	if (child && child->path.type == DEVICE_PATH_GENERIC)
-		wifi_ssdt_write_properties(child, path);
+	wifi_ssdt_write_properties(dev, path);
 }

 const char *wifi_pcie_acpi_name(const struct device *dev)
--- a/src/drivers/wifi/generic/generic.c
+++ b/src/drivers/wifi/generic/generic.c
@@ -21,7 +21,6 @@ struct device_operations wifi_pcie_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= wifi_pci_dev_init,
 	.ops_pci		= &pci_dev_ops_pci,
-	.scan_bus		= scan_static_bus,
 #if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name		= wifi_pcie_acpi_name,
 	.acpi_fill_ssdt		= wifi_pcie_fill_ssdt,
@@ -42,11 +41,6 @@ struct device_operations wifi_cnvi_ops = {
 #endif
 };

-struct device_operations wifi_generic_ops = {
-	.read_resources		= noop_read_resources,
-	.set_resources		= noop_set_resources,
-};
-
 static bool is_cnvi(const struct device *dev)
 {
 	return dev && dev->path.type != DEVICE_PATH_PCI;
@@ -66,11 +60,10 @@ bool wifi_generic_cnvi_ddr_rfim_enabled(const struct device *dev)
 static void wifi_generic_enable(struct device *dev)
 {
 #if !DEVTREE_EARLY
-	const struct device *parent = dev->bus->dev;
-	if (parent && parent->ops == &wifi_pcie_ops)
-		dev->ops = &wifi_generic_ops;
-	else
+	if (is_cnvi(dev))
 		dev->ops = &wifi_cnvi_ops;
+	else
+		dev->ops = &wifi_pcie_ops;
 #endif
 }

--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -64,6 +64,7 @@ config BOARD_GOOGLE_BASEBOARD_GHOST
 	def_bool n
 	select BOARD_GOOGLE_BASEBOARD_BRYA if BOARD_GOOGLE_GHOST4ADL
 	select BOARD_GOOGLE_BASEBOARD_SKOLAS if !BOARD_GOOGLE_GHOST4ADL
+	select DRIVERS_I2C_CS42L42

 config BOARD_GOOGLE_BASEBOARD_NISSA
 	def_bool n
@@ -216,6 +217,7 @@ config MAINBOARD_PART_NUMBER
 	default "Joxer" if BOARD_GOOGLE_JOXER
 	default "Pujjo" if BOARD_GOOGLE_PUJJO
 	default "Xivu" if BOARD_GOOGLE_XIVU
+	default "Gaelin4ADL" if BOARD_GOOGLE_GAELIN4ADL

 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
@@ -252,6 +254,7 @@ config VARIANT_DIR
 	default "joxer" if BOARD_GOOGLE_JOXER
 	default "pujjo" if BOARD_GOOGLE_PUJJO
 	default "xivu" if BOARD_GOOGLE_XIVU
+	default "gaelin" if BOARD_GOOGLE_GAELIN4ADL

 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -214,7 +214,6 @@ config BOARD_GOOGLE_CROTA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_I2C_CS42L42
-	select VPD

 config BOARD_GOOGLE_MOLI
 	bool "->  Moli"
@@ -254,12 +253,14 @@ config BOARD_GOOGLE_KULDAX

 config BOARD_GOOGLE_JOXER
 	bool "->  Joxer"
+	select ALDERLAKE_CONFIGURE_DESCRIPTOR
 	select BOARD_GOOGLE_BASEBOARD_NISSA
 	select DRIVERS_GENESYSLOGIC_GL9750

 config BOARD_GOOGLE_PUJJO
 	bool "->  Pujjo"
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select HAVE_WWAN_POWER_SEQUENCE
@@ -270,3 +271,7 @@ config BOARD_GOOGLE_XIVU
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_INTEL_MIPI_CAMERA
+
+config BOARD_GOOGLE_GAELIN4ADL
+	bool "->  Gaelin4ADL"
+	select BOARD_GOOGLE_BASEBOARD_BRASK
--- a/src/mainboard/google/brya/acpi/power.asl
+++ b/src/mainboard/google/brya/acpi/power.asl
@@ -174,7 +174,6 @@ Method (PGOF, 0, Serialized)

 	/* Assert PERST# */
 	\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
-	Sleep (5)

 	/* All rails are about to go down */
 	\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
@@ -183,7 +182,6 @@ Method (PGOF, 0, Serialized)
 	/* Ramp down FBVDD (active-low) and let rail discharge to <10% */
 	\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
 	GPPL (GPIO_FBVDD_PG, 0, 20)
-	Sleep (40)

 	/* Ramp down PEXVDD and let rail discharge to <10% */
 	\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
@@ -223,6 +221,7 @@ Method (NPON, 0, Serialized)
 	Else
 	{
 		PGON ()
+		\_SB.PCI0.PEG0.LD23 ()
 	}
 }

@@ -241,6 +240,7 @@ Method (NPOF, 0, Serialized)
 	}
 	Else
 	{
+		\_SB.PCI0.PEG0.DL23 ()
 		PGOF ()
 	}
 }
--- a/src/mainboard/google/brya/variants/agah/gpio.c
+++ b/src/mainboard/google/brya/variants/agah/gpio.c
@@ -10,7 +10,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* A7  : SRCCLK_OE7# ==> LAN_WAKE_ODL */
 	PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
 	/* A8  : SRCCLKREQ7# ==> USB2_A2_RT_RST_ODL */
-	PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	PAD_NC(GPP_A8, NONE),
 	/* A12 : SATAXPCIE1 ==> EN_PP3300_LAN_X */
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
 	/* A14 : USB_OC1# ==> USB_C0_OC_ODL */
@@ -110,6 +110,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 	/* F13 : GSXDOUT ==> NC */
 	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
+	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT),
 	/* F15 : GSXSRESET# ==> NC */
 	PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 	/* F16 : GSXCLK ==> NC */
--- a/src/mainboard/google/brya/variants/agah/overridetree.cb
+++ b/src/mainboard/google/brya/variants/agah/overridetree.cb
@@ -80,7 +80,7 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-				.pcie_rp_aspm = ASPM_DISABLE
+				.pcie_rp_aspm = ASPM_L0S,
 			}"
 			device pci 00.0 alias dgpu on end
 		end
--- a/src/mainboard/google/brya/variants/agah/variant.c
+++ b/src/mainboard/google/brya/variants/agah/variant.c
@@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = {

 /* In GCOFF entry order (i.e., power-off order) */
 static const struct power_rail_sequence gpu_off_seq[] = {
-	{ "FBVDD",		FBVDD_PWR_EN,	true,  FBVDD_PG,	40,},
+	{ "FBVDD",		FBVDD_PWR_EN,	true,  FBVDD_PG,	0,},
 	{ "PEXVDD",		PEXVDD_PWR_EN,	false, PEXVDD_PG,	10,},
 	{ "NVVDD+MSVDD",	NVVDD_PWR_EN,	false, NVVDD_PG,	2,},
 	{ "NV3_3",		NV33_PWR_EN,	false, NV33_PG,		4,},
@@ -89,7 +89,6 @@ static void dgpu_power_sequence_off(void)
 {
 	/* Assert reset and clear power-good */
 	gpio_output(GPU_PERST_L, 0);
-	mdelay(5);

 	/* Inform the GPU that the power is no longer good. */
 	gpio_output(GPU_ALLRAILS_PG, 0);
@@ -132,10 +131,6 @@ static void dgpu_power_sequence_on(void)

 void variant_init(void)
 {
-	/* Disable ASPM for the GPU until it is verified working. */
-	struct device *dgpu = DEV_PTR(dgpu);
-	dgpu->disable_pcie_aspm = 1;
-
 	if (acpi_is_wakeup_s3())
 		return;

--- a/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/anahera/memory/Makefile.inc
@@ -7,5 +7,5 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
--- a/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/anahera/memory/dram_id.generated.txt
@@ -19,3 +19,4 @@ K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
+H54G68CYRBX248                 3 (0011)
--- a/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
+H54G68CYRBX248
--- a/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/Makefile.inc
@@ -7,5 +7,5 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
--- a/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/dram_id.generated.txt
@@ -19,3 +19,4 @@ K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
+H54G68CYRBX248                 3 (0011)
--- a/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/anahera4es/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
+H54G68CYRBX248
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -58,7 +58,68 @@ chip soc/intel/alderlake
 		.vnn_icc_max_ma = 500,
 	}"

+	register "power_limits_config[ADL_N_041_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 12,
+		.tdp_pl4 = 78,
+	}"
+
+	register "power_limits_config[ADL_N_021_6W_CORE]" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 12,
+		.tdp_pl4 = 78,
+	}"
+
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""Memory""
+				register "options.tsr[1].desc" = ""Charger""
+
+				# TODO: below values are initial reference values only
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_1, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 3000,
+							.max_power = 6000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200
+						},
+					.pl2 = {
+							.min_power = 12000,
+							.max_power = 12000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000
+						}
+				}"
+
+				## Charger Performance Control (Control, mA)
+				register "controls.charger_perf" = "{
+					[0] = { 255, 1700 },
+					[1] = {  24, 1500 },
+					[2] = {  16, 1000 },
+					[3] = {   8,  500 }
+				}"
+
+				device generic 0 on end
+			end
+		end
 		device ref ipu on
 			chip drivers/intel/mipi_camera
 				register "acpi_uid" = "0x50000"
--- a/src/mainboard/google/brya/variants/crota/variant.c
+++ b/src/mainboard/google/brya/variants/crota/variant.c
@@ -14,13 +14,6 @@ const char *get_wifi_sar_cbfs_filename(void)
 	return "wifi_sar_0.hex";
 }

-static const char *get_dock_mac_from_vpd(char *buf, int size)
-{
-	/* Support MAC address pass-through */
-	/* Read value of 'dock_mac' from RO VPD */
-	return vpd_gets("dock_mac", buf, size, VPD_RO);
-}
-
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
 	if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_USB))) {
@@ -37,49 +30,3 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 		config->ext_fivr_settings.vnn_sx_voltage_mv = 1250;
 	}
 }
-
-void variant_fill_ssdt(const struct device *unused)
-{
-	/* Write MAC address to SSDT for Linux kernel r8152 driver */
-	/* enable pass-through support */
-	/* and read ACPI object name: "\_SB.AMAC" */
-
-	/* ASL code like this */
-	//     Scope (\_SB)
-	// {
-	//     Method (AMAC, 0, Serialized)
-	//     {
-	//         Return (ToBuffer (STRING))
-	//     }
-	// }
-
-	char buf[32], acpi_buf[32];
-	if (get_dock_mac_from_vpd(buf, sizeof(buf)) != NULL) {
-		printk(BIOS_INFO, "RO_VPD, dock_mac=%s\n", buf);
-
-		/* remove ':' from mac address string */
-		size_t len = strlen(buf);
-		int i, j;
-		for (i = 0; i < len; i++) {
-			if (buf[i] == ':') {
-				for (j = i; j < len; j++)
-					buf[j] = buf[j+1];
-				len--;
-				i--;
-			}
-		}
-		buf[len] = '\0';
-
-		/* Format expected by the Linux kernel r8152 driver */
-		/* "_AUXMAC_#XXXXXXXXXXXX#" */
-		int acpi_buf_len = snprintf(acpi_buf, sizeof(acpi_buf), "_AUXMAC_#%s#", buf);
-
-		acpigen_write_scope("\\_SB");
-		acpigen_write_method_serialized("AMAC", 0);
-
-		acpigen_write_return_byte_buffer((uint8_t *)acpi_buf, acpi_buf_len);
-
-		acpigen_write_method_end();
-		acpigen_write_scope_end();
-	}
-}
--- a/src/mainboard/google/brya/variants/gaelin/include/variant/ec.h
+++ b/src/mainboard/google/brya/variants/gaelin/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
--- a/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
--- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+        device domain 0 on
+        end
+
+end
--- a/src/mainboard/google/brya/variants/ghost/gpio.c
+++ b/src/mainboard/google/brya/variants/ghost/gpio.c
@@ -45,8 +45,8 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_A6 : GPP_A6 ==> ESPI_ALERT1 configured on reset, do not touch */
 	/* GPP_A7 : No heuristic was found useful */
 	PAD_NC(GPP_A7, NONE),
-	/* GPP_A8 : No heuristic was found useful */
-	PAD_NC(GPP_A8, NONE),
+	/* GPP_A8 : HP_RST_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
 	/* GPP_A9 : GPP_A9 ==> ESPI_PCH_CLK_R configured on reset, do not touch */
 	/* GPP_A10 : GPP_A10 ==> ESPI_PCH_RST_EC_L configured on reset, do not touch */
 	/* GPP_A11 : [NF6: USB_C_GPP_A11] ==> EN_SPKR_PA */
@@ -215,18 +215,18 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E22, NONE),
 	/* GPP_E23 : net NC is not present in the given design */
 	PAD_NC(GPP_E23, NONE),
-	/* GPP_F0 : CNV_BRI_DT_STRAP ==> Component NC */
-	PAD_NC(GPP_F0, NONE),
-	/* GPP_F1 : No heuristic was found useful */
-	PAD_NC(GPP_F1, NONE),
-	/* GPP_F2 : CNV_RGI_DT_STRAP ==> Component NC */
-	PAD_NC(GPP_F2, NONE),
-	/* GPP_F3 : No heuristic was found useful */
-	PAD_NC(GPP_F3, NONE),
-	/* GPP_F4 : No heuristic was found useful */
-	PAD_NC(GPP_F4, NONE),
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 	/* GPP_F5 : [NF2: MODEM_CLKREQ NF3: CRF_XTAL_CLKREQ NF6: USB_C_GPP_F5] ==> CNV_CLKREQ0 */
-	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
 	/* GPP_F6 : net NC is not present in the given design */
 	PAD_NC(GPP_F6, NONE),
 	/* GPP_F7 : GPP_F7_STRAP ==> Component NC */
--- a/src/mainboard/google/brya/variants/ghost/memory.c
+++ b/src/mainboard/google/brya/variants/ghost/memory.c
@@ -17,36 +17,36 @@ static const struct mb_cfg baseboard_memcfg = {
 	 */
 	.lpx_dq_map = {
 		.ddr0 = {
-			.dq0 = {  5,  0,  4,  1,  2,  6,  7,  3, },
-			.dq1 = {  9, 12,  8, 13, 15, 10, 14, 11, },
+			.dq0 = {  5,  0,  4,  1,  2,  6,  7,  3 },
+			.dq1 = {  11, 15, 13, 12, 10, 14,  8, 9 },
 		},
 		.ddr1 = {
-			.dq0 = {  9, 10, 11,  8, 13, 15, 14, 12, },
-			.dq1 = {  0,  3,  1,  2,  7,  5,  6,  4, },
+			.dq0 = {  9, 10, 11,  8, 13, 14, 12, 15 },
+			.dq1 = {  0,  2,  1,  3,  7,  5,  6,  4 },
 		},
 		.ddr2 = {
-			.dq0 = {  9, 13,  8, 12, 15, 10, 14, 11, },
-			.dq1 = {  7,  6,  4,  5,  0,  3,  1,  2, },
+			.dq0 = {  3,  7,  2,  6,  4,  1,  5,  0 },
+			.dq1 = {  12, 14, 15, 13, 11, 10,  8,  9 },
 		},
 		.ddr3 = {
-			.dq0 = {  3,  7,  2,  6,  4,  1,  5,  0, },
-			.dq1 = { 12, 14, 15, 13, 11, 10,  8,  9, },
+			.dq0 = {  15, 14, 12, 13,  10,  9, 11, 8 },
+			.dq1 = {  7,  6,  4,  5,  0,  3,  1,  2 },
 		},
 		.ddr4 = {
-			.dq0 = { 15, 14, 12, 13, 10,  9,  8, 11, },
-			.dq1 = {  7,  5,  4,  6,  2,  0,  1,  3, },
+			.dq0 = {  15, 14, 12, 13, 10,  9,  8, 11 },
+			.dq1 = {  1,  3,  0,  2,  5,  6,  7,  4 },
 		},
 		.ddr5 = {
-			.dq0 = {  9, 10, 11,  8, 12, 15, 13, 14, },
-			.dq1 = {  3,  7,  2,  6,  0,  4,  5,  1, },
+			.dq0 = {  9, 10, 11,  8, 12, 15, 13, 14 },
+			.dq1 = {  3,  7,  2,  6,  0,  4,  5,  1 },
 		},
 		.ddr6 = {
-			.dq0 = {  3,  2,  1,  0,  7,  5,  6,  4, },
-			.dq1 = { 12, 13, 10,  9, 14, 11,  8, 15, },
+			.dq0 = { 11,  8, 10,  9, 12, 14, 13, 15 },
+			.dq1 = {  0,  7,  1,  2,  6,  4,  3,  5 },
 		},
 		.ddr7 = {
-			.dq0 = { 11,  8, 10,  9, 12, 14, 13, 15, },
-			.dq1 = {  1,  7,  0,  2,  5,  3,  4,  6, },
+			.dq0 = {  1,  2,  3,  0,  7,  5,  6,  4 },
+			.dq1 = {  15, 14, 11,  13, 8, 9,  12, 10 },
 		},
 	},

@@ -59,12 +59,12 @@ static const struct mb_cfg baseboard_memcfg = {
 	 */
 	.lpx_dqs_map = {
 		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
 	},

--- a/src/mainboard/google/brya/variants/ghost/overridetree.cb
+++ b/src/mainboard/google/brya/variants/ghost/overridetree.cb
@@ -14,38 +14,20 @@ chip soc/intel/alderlake
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.i2c[0] = {
-			.speed = I2C_SPEED_STANDARD,
-			.speed_config[0] = {
-				.speed = I2C_SPEED_STANDARD,
-				.scl_lcnt = 45,
-				.scl_hcnt = 33,
-				.sda_hold = 20,
-			},
+			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[1] = {
 			.early_init = 1,
-			.speed = I2C_SPEED_STANDARD,
-			.rise_time_ns = 600,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[2] = {
-			.speed = I2C_SPEED_STANDARD,
-			.rise_time_ns = 650,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[3] = {
-			.speed = I2C_SPEED_STANDARD,
-			.rise_time_ns = 650,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed = I2C_SPEED_FAST,
 		},
 		.i2c[5] = {
-			.speed = I2C_SPEED_STANDARD,
-			.rise_time_ns = 650,
-			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed = I2C_SPEED_FAST,
 		},
 	}"

@@ -100,6 +82,24 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+		device ref i2c0 on
+			chip drivers/i2c/cs42l42
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "ts_inv" = "true"
+				register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
+				register "ts_dbnc_fall" = "FALL_DEB_0_MS"
+				register "btn_det_init_dbnce" = "100"
+				register "btn_det_event_dbnce" = "10"
+				register "bias_lvls[0]" = "15"
+				register "bias_lvls[1]" = "8"
+				register "bias_lvls[2]" = "4"
+				register "bias_lvls[3]" = "1"
+				register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
+				register "hs_bias_sense_disable" = "true"
+				device i2c 48 on end
+			end
+		end
 		device ref i2c1 on
 			chip drivers/i2c/tpm
 				register "hid" = ""GOOG0005""
--- a/src/mainboard/google/brya/variants/joxer/Makefile.inc
+++ b/src/mainboard/google/brya/variants/joxer/Makefile.inc
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
+bootblock-y += variant.c

 romstage-y += gpio.c

--- a/src/mainboard/google/brya/variants/joxer/overridetree.cb
+++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb
@@ -132,7 +132,7 @@ chip soc/intel/alderlake
 				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "hid_desc_reg_offset" = "0x01"
-				device i2c 5d on end
+				device i2c 0x14 on end
 			end
 		end
 		device ref i2c3 on
--- a/src/mainboard/google/brya/variants/joxer/variant.c
+++ b/src/mainboard/google/brya/variants/joxer/variant.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <soc/bootblock.h>
+
+/*
+ * TODO(b/229022567): This is a workaround which will be removed once we
+ * implement a proper solution for configuring the descriptor differently for
+ * different SKUs.
+ */
+void variant_update_descriptor(void)
+{
+	/*
+	 * UfsCont1Config = "Disabled"
+	 * IshSupported = "No"
+	 */
+	struct descriptor_byte emmc_bytes[] = {
+		{ 0x1f8, 0x55 },
+		{ 0x1f9, 0x55 },
+		{ 0xc18, 0x89 },
+		{ 0xc1d, 0xb8 },
+	};
+
+	/*
+	 * UfsCont1Config = "X2"
+	 * IshSupported = "Yes"
+	 */
+	struct descriptor_byte ufs_bytes[] = {
+		{ 0x1f8, 0x95 },
+		{ 0x1f9, 0x59 },
+		{ 0xc18, 0x09 },
+		{ 0xc1d, 0x28 },
+	};
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		printk(BIOS_INFO, "Configuring descriptor for UFS\n");
+		configure_descriptor(ufs_bytes, ARRAY_SIZE(ufs_bytes));
+	} else {
+		printk(BIOS_INFO, "Configuring descriptor for eMMC\n");
+		configure_descriptor(emmc_bytes, ARRAY_SIZE(emmc_bytes));
+	}
+}
--- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb
@@ -6,6 +6,23 @@ fw_config
 end

 chip soc/intel/alderlake
+	register "usb2_ports[1]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 1
+	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 2
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	# Disable USB2 Port 4
+
+	register "usb3_ports[0]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A0
+	register "usb3_ports[1]" = "{
+		.enable           = 1,
+		.ocpin            = OC_SKIP,
+		.tx_de_emp        = 0x2B,
+		.tx_downscale_amp = 0x00,
+	}" # Type-A port A1
+
 	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
--- a/src/mainboard/google/brya/variants/moli/overridetree.cb
+++ b/src/mainboard/google/brya/variants/moli/overridetree.cb
@@ -35,6 +35,80 @@ chip soc/intel/alderlake
 	register "tcss_ports[3]" = "TCSS_PORT_EMPTY"		# Disable TCP3
 	register "tcc_offset" = "0"	# TCC of 100C
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				## sensor information
+				register "options.tsr[0].desc" = ""SSD""
+				register "options.tsr[1].desc" = ""CPU_VR""
+				register "options.tsr[2].desc" = ""DIMM""
+
+				# TODO: below values are initial reference values only
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {
+						.target = DPTF_CPU,
+						.thresholds = {
+								TEMP_PCT(85, 90),
+								TEMP_PCT(80, 80),
+								TEMP_PCT(75, 70),
+						}
+					}
+				}"
+
+				## Passive Policy
+				register "policies.passive" = "{
+					[0] = DPTF_PASSIVE(CPU,		CPU,           95, 5000),
+					[1] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_0, 75, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[3] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_2, 75, 5000),
+				}"
+
+				## Critical Policy
+				register "policies.critical" = "{
+					[0] = DPTF_CRITICAL(CPU,               105, SHUTDOWN),
+					[1] = DPTF_CRITICAL(TEMP_SENSOR_0,      85, SHUTDOWN),
+					[2] = DPTF_CRITICAL(TEMP_SENSOR_1,      85, SHUTDOWN),
+					[3] = DPTF_CRITICAL(TEMP_SENSOR_2,      85, SHUTDOWN),
+				}"
+
+				register "controls.power_limits" = "{
+					.pl1 = {
+							.min_power = 15000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 200,
+						},
+					.pl2 = {
+							.min_power = 55000,
+							.max_power = 55000,
+							.time_window_min = 28 * MSECS_PER_SEC,
+							.time_window_max = 32 * MSECS_PER_SEC,
+							.granularity = 1000,
+						}
+				}"
+
+				## Fan Performance Control (Percent, Speed, Noise, Power)
+				register "controls.fan_perf" = "{
+					[0] = {  90, 6700, 220, 2200, },
+					[1] = {  80, 5800, 180, 1800, },
+					[2] = {  70, 5000, 145, 1450, },
+					[3] = {  60, 4900, 115, 1150, },
+					[4] = {  50, 3838,  90,  900, },
+					[5] = {  40, 2904,  55,  550, },
+					[6] = {  30, 2337,  30,  300, },
+					[7] = {  20, 1608,  15,  150, },
+					[8] = {  10,  800,  10,  100, },
+					[9] = {   0,    0,   0,   50, }
+				}"
+
+				## Fan options
+				register "options.fan.fine_grained_control" = "1"
+				register "options.fan.step_size" = "2"
+
+				device generic 0 alias dptf_policy on end
+			end
+		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer
 				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
--- a/src/mainboard/google/brya/variants/pujjo/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/pujjo/memory/Makefile.inc
@@ -7,3 +7,4 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-3.hex      # ID = 0(0b0000)  Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B
 SPD_SOURCES += spd/lp5/set-0/spd-6.hex      # ID = 2(0b0010)  Parts = K3LKCKC0BM-MGCP
+SPD_SOURCES += spd/lp5/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = MT62F1G32D4DR-031 WT:B
--- a/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt
@@ -8,4 +8,5 @@ H58G56AK6BX069                 0 (0000)
 H9JCNNNBK3MLYR-N6E             1 (0001)
 K3LKBKB0BM-MGCP                0 (0000)
 K3LKCKC0BM-MGCP                2 (0010)
+MT62F1G32D4DR-031 WT:B         3 (0011)
 MT62F512M32D2DR-031 WT:B       1 (0001)
--- a/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt
@@ -13,4 +13,5 @@ H58G56AK6BX069
 H9JCNNNBK3MLYR-N6E
 K3LKBKB0BM-MGCP
 K3LKCKC0BM-MGCP
+MT62F1G32D4DR-031 WT:B
 MT62F512M32D2DR-031 WT:B
--- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/alderlake
 	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"

 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WFC Camera
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for PCIe WLAN
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth port for CNVi WLAN

 	# Configure external V1P05/Vnn/VnnSx Rails
@@ -228,6 +229,18 @@ chip soc/intel/alderlake
 				device i2c 0x2c on end
 			end
 		end
+		device ref pcie_rp4 on
+			# PCIe 4 WLAN
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				device pci 00.0 on end
+			end
+		end
 		device ref pcie_rp7 on
 			# Enable SD Card PCIe 7 using clk 3
 			register "pch_pcie_rp[PCH_RP(7)]" = "{
@@ -314,6 +327,13 @@ chip soc/intel/alderlake
 					chip drivers/usb/acpi
 						register "desc" = ""USB2 Bluetooth""
 						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""CNVi Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
 						register "reset_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
 						device ref usb2_port10 on end
--- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc
@@ -7,5 +7,5 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
--- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt
@@ -19,3 +19,4 @@ K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
+H54G68CYRBX248                 3 (0011)
--- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
+H54G68CYRBX248
--- a/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/Makefile.inc
@@ -7,5 +7,5 @@ SPD_SOURCES =
 SPD_SOURCES += spd/lp4x/set-0/spd-4.hex      # ID = 0(0b0000)  Parts = MT53E1G32D2NP-046 WT:A
 SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 1(0b0001)  Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL
 SPD_SOURCES += spd/lp4x/set-0/spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL
-SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE, H54G68CYRBX248
 SPD_SOURCES += spd/lp4x/set-0/spd-7.hex      # ID = 4(0b0100)  Parts = MT53E2G32D4NQ-046 WT:A, MT53E2G32D4NQ-046 WT:C
--- a/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/dram_id.generated.txt
@@ -19,3 +19,4 @@ K4U6E3S4AB-MGCL                1 (0001)
 H54G56CYRBX247                 2 (0010)
 K4UBE3D4AB-MGCL                2 (0010)
 MT53E2G32D4NQ-046 WT:C         4 (0100)
+H54G68CYRBX248                 3 (0011)
--- a/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/redrix4es/memory/mem_parts_used.txt
@@ -13,3 +13,4 @@ K4U6E3S4AB-MGCL
 H54G56CYRBX247
 K4UBE3D4AB-MGCL
 MT53E2G32D4NQ-046 WT:C
+H54G68CYRBX248
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

 #include <bl31.h>
+#include <boardid.h>
 #include <bootmode.h>
 #include <console/console.h>
 #include <delay.h>
@@ -16,6 +17,7 @@
 #include <soc/i2c.h>
 #include <soc/msdc.h>
 #include <soc/mtcmos.h>
+#include <soc/pcie.h>
 #include <soc/spm.h>
 #include <soc/usb.h>

@@ -29,6 +31,32 @@
 #define GPIO_EDP_HPD_1V8 GPIO(GPIO_07)
 #define GPIO_EN_PP3300_DISP_X GPIO(I2SO1_D2)

+bool mainboard_needs_pcie_init(void)
+{
+	uint32_t sku;
+
+	if (!CONFIG(BOARD_GOOGLE_DOJO))
+		return false;
+
+	sku = sku_id();
+	switch (sku) {
+	case 0:
+	case 1:
+	case 4:
+	case 5:
+		return false;
+	case 2:
+	case 3:
+	case 6:
+	case 7:
+		return true;
+	default:
+		/* For example CROS_SKU_UNPROVISIONED */
+		printk(BIOS_WARNING, "Unexpected sku %#x; assuming PCIe", sku);
+		return true;
+	}
+}
+
 static void register_reset_to_bl31(void)
 {
 	static struct bl_aux_param_gpio param_reset = {
--- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb
@@ -284,6 +284,20 @@ chip soc/intel/jasperlake
 				register "hid_desc_reg_offset" = "0x01"
 				device i2c 15 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""WDHT0002""
+				register "generic.desc" = ""WDT Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
+				register "generic.reset_delay_ms" = "130"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "10"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
 		end # I2C 2
 		device pci 15.3 on
 			chip drivers/intel/mipi_camera
--- a/src/mainboard/google/geralt/romstage.c
+++ b/src/mainboard/google/geralt/romstage.c
@@ -1,13 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

 #include <arch/stages.h>
+#include <soc/clkbuf.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
 #include <soc/pmif.h>
+#include <soc/rtc.h>

 void platform_romstage_main(void)
 {
 	mtk_pmif_init();
 	mt6315_init();
 	mt6359p_init();
+	clk_buf_init();
+	rtc_boot();
 }
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -1,11 +1,19 @@
 chip soc/intel/meteorlake

+	# GPE configuration
+	register "pmc_gpe0_dw0" = "GPP_A"
+	register "pmc_gpe0_dw1" = "GPP_E"
+	register "pmc_gpe0_dw2" = "GPP_F"
+
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"
 	register "gen2_dec" = "0x000c0201"
 	# EC memory map range is 0x900-0x9ff
 	register "gen3_dec" = "0x00fc0901"

+	# Enable CNVi BT
+	register "cnvi_bt_core" = "true"
+
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoPci,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
--- a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
+++ b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
@@ -17,5 +17,11 @@
 #define EC_SCI_GPI	GPE0_ESPI
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_E11
+#define GPIO_MEM_CONFIG_1	GPP_E02
+#define GPIO_MEM_CONFIG_2	GPP_E01
+#define GPIO_MEM_CONFIG_3	GPP_E12
+#define GPIO_MEM_CH_SEL		GPP_E13

 #endif /* __BASEBOARD_GPIO_H__ */
--- a/src/mainboard/google/rex/variants/baseboard/rex/memory.c
+++ b/src/mainboard/google/rex/variants/baseboard/rex/memory.c
@@ -6,7 +6,9 @@

 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP5X,
-	/* TODO: Add Memory configuration */
+	.lp5x_config = {
+		.ccc_config = 0x66,
+	},
 	.ect = 1, /* Enable Early Command Training */
 };

@@ -17,12 +19,19 @@ const struct mb_cfg *__weak variant_memory_params(void)

 int __weak variant_memory_sku(void)
 {
-	return 0;
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 }

 bool __weak variant_is_half_populated(void)
 {
-	return 0;
+	return gpio_get(GPIO_MEM_CH_SEL);
 }

 void __weak variant_get_spd_info(struct mem_spd *spd_info)
--- a/src/mainboard/google/rex/variants/rex0/gpio.c
+++ b/src/mainboard/google/rex/variants/rex0/gpio.c
@@ -2,51 +2,449 @@

 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
-#include <boardid.h>
 #include <soc/gpio.h>
+#include <console/console.h>
+#include <boardid.h>

 /* Pad configuration in ramstage */
-static const struct pad_config gpio_table[] = {
-	/* ToDo: Fill gpio configuration */
-	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+static const struct pad_config gpio_table_id0[] = {
+	/* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */
+	/* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */
+	/* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */
+	/* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */
+	/* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */
+	/* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */
+	/* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */
+	/* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	/* GPP_A12 : [] ==> EN_UCAM_PWR */
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+	/* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */
+	PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG),
+	/* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A14, 1, DEEP),
+	/* GPP_A15 : [] ==> WWAN_RST_L */
+	PAD_CFG_GPO(GPP_A15, 1, DEEP),
+	/* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */
+	/* GPP_A17 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_A18 : [] ==> CAM_PSW_L */
+	PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG),
+	/* GPP_A19 : [] ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_A19, 1, DEEP),
+	/* GPP_A20 : [] ==> SSD_PERST_L */
+	PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG),
+	/* GPP_A21 : [] ==> WWAN_CONFIG2 */
+	PAD_CFG_GPI(GPP_A21, NONE, DEEP),
+
+	/* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_B01 : [] ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_B01, 1, DEEP),
+	/* GPP_B02 : net NC is not present in the given design */
+	PAD_NC(GPP_B02, NONE),
+	/* GPP_B03 : net NC is not present in the given design */
+	PAD_NC(GPP_B03, NONE),
+	/* GPP_B04 : GPP_B04_STRAP ==> Component NC */
+	PAD_NC(GPP_B04, NONE),
+	/* GPP_B05 : net NC is not present in the given design */
+	PAD_NC(GPP_B05, NONE),
+	/* GPP_B06 : net NC is not present in the given design */
+	PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH),
+	/* GPP_B07 : net NC is not present in the given design */
+	PAD_NC(GPP_B07, NONE),
+	/* GPP_B08 : net NC is not present in the given design */
+	PAD_NC(GPP_B08, NONE),
+	/* GPP_B09 : [] ==> EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_B09, 0, DEEP),
+	/* GPP_B10 : [] ==> WIFI_DISABLE_L */
+	PAD_CFG_GPO(GPP_B10, 1, DEEP),
+	/* GPP_B11 : [] ==> EN_FP_PWR */
+	PAD_CFG_GPO_LOCK(GPP_B11, 1, LOCK_CONFIG),
+	/* GPP_B12 : [] ==> SLP_SO_R_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* GPP_B13 : [] ==> PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14 : GPP_B14_STRAP ==> Component NC */
+	PAD_NC(GPP_B14, NONE),
+	/* GPP_B15 : [] ==> USB_OC3# */
+	PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG),
+	/* GPP_B16 : No heuristic was found useful */
+	PAD_NC(GPP_B16, NONE),
+	/* GPP_B17 : [] ==> EN_WWAN_PWR */
+	PAD_CFG_GPO(GPP_B17, 1, DEEP),
+	/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
+	PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG),
+	/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
+	PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG),
+	/* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */
+	PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG),
+	/* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */
+	PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG),
+	/* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	/* GPP_B23 : [] ==> WWAN_CONFIG0 */
+	PAD_CFG_GPI_LOCK(GPP_B23, NONE, LOCK_CONFIG),
+
+	/* GPP_C00 : [] ==> EN_PP3300_TCHSCR */
+	PAD_CFG_GPO(GPP_C00, 1, DEEP),
+	/* GPP_C01 : [] ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C01, 0, DEEP),
+	/* GPP_C02 : GPP_C02_STRAP ==> Component NC */
+	PAD_NC(GPP_C02, NONE),
+	/* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */
+	PAD_CFG_GPO_LOCK(GPP_C03, 0, LOCK_CONFIG),
+	/* GPP_C04 : [] ==> EN_WCAM_PWR */
+	PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG),
+	/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
+	PAD_CFG_GPO(GPP_C05, 0, PLTRST),
+	/* GPP_C06 : [] ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_C06, 0, DEEP),
+	/* GPP_C07 : [] ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_C08 : No heuristic was found useful */
+	PAD_NC(GPP_C08, NONE),
+	/* GPP_C09 : net NC is not present in the given design */
+	PAD_NC(GPP_C09, NONE),
+	/* GPP_C10 : net NC is not present in the given design */
+	PAD_NC(GPP_C10, NONE),
+	/* GPP_C11 : [] ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+	/* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* GPP_C13 : [] ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* GPP_C15 : [] ==> GPP_C15_STRAP */
+	PAD_NC(GPP_C15, NONE),
+	/* GPP_C16 : [] ==> USB_C0_LSX_TX */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17 : [] ==> USB_C0_LSX_RX */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18 : [] ==> USB_C0_AUX_DC_P */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF6),
+	/* GPP_C19 : [] ==> USB_C0_AUX_DC_N */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF6),
+	/* GPP_C20 : [] ==> USB_C1_LSX_TX */
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* GPP_C21 : [] ==> USB_C1_LSX_RX */
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	/* GPP_C22 : [] ==> SOC_FP_BOOT0 */
+	PAD_CFG_GPO_LOCK(GPP_C22, 0, LOCK_CONFIG),
+	/* GPP_C23 : [] ==> FP_RST_ODL */
+	PAD_CFG_GPO_LOCK(GPP_C23, 1, LOCK_CONFIG),
+
+	/* GPP_D00 : WCAM_MCLK_R */
+	PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
+	/* GPP_D01 : [] ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG),
+	/* GPP_D02 : [] ==> SD_PERST_L */
+	PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG),
+	/* GPP_D03 : [] ==> EN_PP3300_SD */
+	PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG),
+	/* GPP_D04 : [] ==> EN_SPKR */
+	PAD_CFG_GPO(GPP_D04, 1, DEEP),
+	/* GPP_D05 : net NC.  Test pad. */
+	PAD_NC(GPP_D05, NONE),
+	/* GPP_D06 : net NC.  Test pad.*/
+	PAD_NC(GPP_D06, NONE),
+	/* GPP_D07 : net NC.  Test pad. */
+	PAD_NC(GPP_D07, NONE),
+	/* GPP_D08 : net NC.  Test pad. */
+	PAD_NC(GPP_D08, NONE),
+	/* GPP_D09 : [] ==> I2S_MCLK_R */
+	PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
+	/* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),
+	/* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */
+	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	/* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */
+	PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2),
+	/* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2),
+	/* GPP_D14 : [] ==> I2S_HP_SCLK_R */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2),
+	/* GPP_D15 : [] ==> I2S_HP_SFRM_R */
+	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2),
+	/* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */
+	PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
+	/* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
+	/* GPP_D18 : net NC is not present in the given design */
+	PAD_NC(GPP_D18, NONE),
+	/* GPP_D19 : net NC is not present in the given design */
+	PAD_NC(GPP_D19, NONE),
+	/* GPP_D20 : net NC is not present in the given design */
+	PAD_NC(GPP_D20, NONE),
+	/* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */
+	PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2),
+	/* GPP_D22 : net NC is not present in the given design */
+	PAD_NC(GPP_D22, NONE),
+	/* GPP_D23 : net NC is not present in the given design */
+	PAD_NC(GPP_D23, NONE),
+
+	/* GPP_E00 : [] ==> SAR1_INT_L */
+	PAD_CFG_GPI_APIC(GPP_E00, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_E01 : MEM_STRAP_2 ==> Component NC */
+	PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG),
+	/* GPP_E02 : MEM_STRAP_1 ==> Component NC */
+	PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG),
+	/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/* GPP_E04 : [] ==> HPS_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, NONE),
+	/* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_E05, 1, DEEP),
+	/* GPP_E06 : GPP_E06_STRAP ==> Component NC */
+	PAD_NC(GPP_E06, NONE),
+	/* GPP_E07 : [] ==> WWAN_FCPO_L */
+	PAD_CFG_GPO(GPP_E07, 1, DEEP),
+	/* GPP_E08 : [] ==> SAR2_INT_L */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, NONE, LOCK_CONFIG),
+	/* GPP_E09 : No heuristic was found useful */
+	PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG),
+	/* GPP_E10 : net NC is not present in the given design */
+	PAD_NC(GPP_E10, NONE),
+	/* GPP_E11 : [] ==> MEM_STRAP_0 */
+	PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
+	/* GPP_E12 : [] ==> MEM_STRAP_3 */
+	PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
+	/* GPP_E13 :  [] ==> MEM_CH_SEL */
+	PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
+	/* GPP_E14 : [] ==> SOC_EDP_HPD_L */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* GPP_E15 : net NC is not present in the given design */
+	PAD_NC(GPP_E15, NONE),
+	/* GPP_E16 : net NC.  Test pad. */
+	PAD_NC(GPP_E16, NONE),
+	/* GPP_E17 : [] ==> EN_HPS_PWR */
+	PAD_CFG_GPO(GPP_E17, 1, DEEP),
+	/* GPP_E22 : net EN_PP3300_WLAN is not present in the given design */
+	PAD_NC(GPP_E22, NONE),
+
+	/* GPP_F00 :  [] ==> CNV_BRI_DT_R */
+	PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1),
+	/* GPP_F01 :  [] ==> CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1),
+	/* GPP_F02 :  [] ==> CNV_RGI_DT_Rl */
+	PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1),
+	/* GPP_F03 :  [] ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1),
+	/* GPP_F04 :  [] ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1),
+	/* GPP_F05 :  [] ==> CNV_CLKREQ */
+	PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3),
+	/* GPP_F06 :  [] ==> WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+	/* GPP_F07 :  [] ==> UCAM_MCLK_R */
+	PAD_CFG_GPO(GPP_F07, 0, DEEP),
+	/* GPP_F08 : [] ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
+	/* GPP_F09 : No heuristic was found useful */
+	PAD_NC(GPP_F09, NONE),
+	/* GPP_F10 : [] ==> WWAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_F11 : GSP1_SOC_CLK_R */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5),
+	/* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5),
+	/* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5),
+	/* GPP_F14 : GSPI_SOC_DO_TCHSCR_DI */
+	PAD_NC(GPP_F14, NONE),
+	/* GPP_F15 : [] ==> GSPI_SOC_DI_TCHSCR_DO */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F16 : [] ==> GSPI_SOC_TCHSCR_CLK */
+	PAD_NC(GPP_F16, NONE),
+	/* GPP_F17 : [] ==> GSPI1_SOC_CS_L */
+	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
+	/* GPP_F18 : [] ==> GSPI_SOC_TCHSCR_CS_L */
+	PAD_NC(GPP_F18, NONE),
+	/* GPP_F19 : [] ==> GPP_F19_STRAP */
+	PAD_NC(GPP_F19, NONE),
+	/* GPP_F20 : [] ==> GPP_F20_STRAP */
+	PAD_NC(GPP_F20, NONE),
+	/* GPP_F21 : [] ==> GPP_F21_STRAP */
+	PAD_NC(GPP_F21, NONE),
+	/* GPP_F22 : net NC is not present in the given design */
+	PAD_NC(GPP_F22, NONE),
+	/* GPP_F23 : net NC is not present in the given design */
+	PAD_NC(GPP_F23, NONE),
+
+	/* GPP_H00 : GPP_H00_STRAP ==> Component NC */
+	PAD_NC(GPP_H00, NONE),
+	/* GPP_H01 : GPP_H01_STRAP ==> Component NC */
+	PAD_NC(GPP_H01, NONE),
+	/* GPP_H02 : GPP_H02_STRAP ==> Component NC */
+	PAD_NC(GPP_H02, NONE),
+	/* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
+	/* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2),
+	/* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */
+	PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG),
+	/* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */
+	PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG),
+	/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+	/* GPP_H10 : [] ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
+	/* GPP_H11 : net NC is not present in the given design */
+	PAD_NC(GPP_H11, NONE),
+	/* GPP_H13 : [] ==> CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+	/* GPP_H14 : [] ==> SLP_S0_GATE_R */
+	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	/* GPP_H15 : net NC is not present in the given design */
+	PAD_NC(GPP_H15, NONE),
+	/* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	/* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */
+	PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+	/* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+	/* GPP_H21 : [] ==>  SOC_I2C_TCHSCR_SDA */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22 : [] ==>  SOC_I2C_TCHSCR_SCL */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* GPP_S00 :  [] ==> SDW_HP_CLK  */
+	PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+	/* GPP_S01 :  [] ==> SDW_HP_DATA */
+	PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+	/* GPP_S02 : [] ==> DMIC_SOC_CLK0_DB_RC */
+	PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3),
+	/* GPP_S03 : [] ==> DMIC_SOC_DATA0_DB_R */
+	PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3),
+	/* GPP_S04 : [] ==> SDW_SPKR_CLK */
+	PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1),
+	/* GPP_S05 : [] ==> SDW_SPKR_DATA */
+	PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1),
+	/* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */
+	PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+	/* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */
+	PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+	/* GPP_V00 : [] ==> BATLOW_L */
+	PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+	/* GPP_V01 : [] ==> ACPRESENT */
+	PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+	/* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */
+	PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+	/* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */
+	PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+	/* GPP_V04 : [] ==> SLP_S3_L */
+	PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+	/* GPP_V05 : [] ==> SLP_S4_L */
+	PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+	/* GPP_V06 : [] ==> SOC_SLP_A_L */
+	PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+	/* GPP_V08 : [] ==> SOC_SUSCLK */
+	PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+	/* GPP_V09 : [] ==> SOC_SLP_WLAN_L */
+	PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+	/* GPP_V10 : [] ==> SLP_S5_L */
+	PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+	/* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/
+	PAD_NC(GPP_V11, NONE),
+	/* GPP_V12 : [] ==> SOC_SLP_LAN_L */
+	PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+	/* GPP_V14 : [] ==> SOC_WAKE_L */
+	PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+	/* GPP_V22 : [] ==> WCAM_RST_L */
+	PAD_CFG_GPO(GPP_V22, 0, DEEP),
+	/* GPP_V23 : [] ==> UCAM_RST_L */
+	PAD_CFG_GPO(GPP_V23, 0, DEEP),
 };

 /* Early pad configuration in bootblock */
-static const struct pad_config early_gpio_table[] = {
-	/* ToDo: Fill early gpio configuration */
-	/* H08 : UART0_RXD ==> UART_DBG_TX_SOC_RX */
+static const struct pad_config early_gpio_table_id0[] = {
+	/* TODO: Verify all early config in place */
+
+	/* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
+	/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
+
+	/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
 	PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
-	/* H09 : UART0_TXD ==> UART_DBG_RX_SOC_TX */
+	/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
 	PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+	/* GPP_D03 : [] ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D03, 1, DEEP),
+
+	/* GPP_E13 :  [] ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+
+	/* GPP_A17 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+
+	/* GPP_A20 : [] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+
+	/* GPP_H10 : [] ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
 };

-static const struct pad_config romstage_gpio_table[] = {
-	/* ToDo: Fill romstage gpio configuration */
+static const struct pad_config romstage_gpio_table_id0[] = {
+	/* A20  : [] ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
 };

 const struct pad_config *variant_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(gpio_table);
-	return gpio_table;
+	const uint32_t id = board_id();
+	switch (id) {
+	case 0:
+		*num = ARRAY_SIZE(gpio_table_id0);
+		return gpio_table_id0;
+
+	case BOARD_ID_UNKNOWN:
+	default:
+		printk(BIOS_ERR, "board_id() not found.  Unable to load gpio table.\n");
+		*num = 0;
+		return NULL;
+	}
 }

 const struct pad_config *variant_early_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(early_gpio_table);
-	return early_gpio_table;
+	const uint32_t id = board_id();
+	switch (id) {
+	case 0:
+		*num = ARRAY_SIZE(early_gpio_table_id0);
+		return early_gpio_table_id0;
+
+	case BOARD_ID_UNKNOWN:
+	default:
+		printk(BIOS_ERR, "board_id() not found.  Unable to load early gpio table.\n");
+		*num = 0;
+		return NULL;
+	}
 }

 /* Create the stub for romstage gpio, typically use for power sequence */
 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 {
-	*num = ARRAY_SIZE(romstage_gpio_table);
-	return romstage_gpio_table;
+	const uint32_t id = board_id();
+	switch (id) {
+	case 0:
+		*num = ARRAY_SIZE(romstage_gpio_table_id0);
+		return romstage_gpio_table_id0;
+
+	case BOARD_ID_UNKNOWN:
+	default:
+		printk(BIOS_ERR,
+		       "board_id() not found.  Unable to load romstage gpio table.\n");
+		*num = 0;
+		return NULL;
+	}
 }

-static const struct cros_gpio cros_gpios[] = {
-};
+static const struct cros_gpio cros_gpios[] = {};

 DECLARE_WEAK_CROS_GPIOS(cros_gpios);
--- a/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc
+++ b/src/mainboard/google/rex/variants/rex0/memory/Makefile.inc
@@ -5,3 +5,5 @@

 SPD_SOURCES =
 SPD_SOURCES += spd/lp5/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = MT62F512M32D2DR-031 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex      # ID = 1(0b0001)  Parts = MT62F1G32D2DS-026 WT:B
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex      # ID = 2(0b0010)  Parts = MT62F2G32D4DS-026 WT:B
--- a/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt
+++ b/src/mainboard/google/rex/variants/rex0/memory/dram_id.generated.txt
@@ -5,3 +5,5 @@

 DRAM Part Name                 ID to assign
 MT62F512M32D2DR-031 WT:B       0 (0000)
+MT62F1G32D2DS-026 WT:B         1 (0001)
+MT62F2G32D4DS-026 WT:B         2 (0010)
--- a/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt
+++ b/src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt
@@ -10,3 +10,5 @@

 # Part Name
 MT62F512M32D2DR-031 WT:B
+MT62F1G32D2DS-026 WT:B
+MT62F2G32D4DS-026 WT:B
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -13,6 +13,17 @@ chip soc/intel/meteorlake
 	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
 	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

+	# Enable eDP in Port A
+	register "ddi_port_A_config" = "1"
+	# Enable HDMI in Port B
+	register "ddi_port_B_config" = "0"
+
+	# Enable Display Port Configuration
+	register "ddi_ports_config" = "{
+		[DDI_PORT_A] = DDI_ENABLE_HPD,
+		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+	}"
+
 	register "serial_io_gspi_mode" = "{
 		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
 		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
--- a/src/mainboard/google/trogdor/Kconfig
+++ b/src/mainboard/google/trogdor/Kconfig
@@ -81,6 +81,7 @@ config MAINBOARD_PART_NUMBER
 	default "Marzipan" if BOARD_GOOGLE_MARZIPAN
 	default "Mrbland" if BOARD_GOOGLE_MRBLAND
 	default "Pazquel" if BOARD_GOOGLE_PAZQUEL
+	default "Pazquel360" if BOARD_GOOGLE_PAZQUEL360
 	default "Pompom" if BOARD_GOOGLE_POMPOM
 	default "Quackingstick" if BOARD_GOOGLE_QUACKINGSTICK
 	default "Trogdor" if BOARD_GOOGLE_TROGDOR
--- a/src/mainboard/google/trogdor/Kconfig.name
+++ b/src/mainboard/google/trogdor/Kconfig.name
@@ -38,6 +38,10 @@ config BOARD_GOOGLE_PAZQUEL
 	bool "->  Pazquel"
 	select BOARD_GOOGLE_TROGDOR_COMMON

+config BOARD_GOOGLE_PAZQUEL360
+	bool "->  Pazquel360"
+	select BOARD_GOOGLE_TROGDOR_COMMON
+
 config BOARD_GOOGLE_POMPOM
 	bool "->  Pompom"
 	select BOARD_GOOGLE_TROGDOR_COMMON
--- a/src/mainboard/hp/z220_series/devicetree.cb
+++ b/src/mainboard/hp/z220_series/devicetree.cb
@@ -22,6 +22,7 @@ chip northbridge/intel/sandybridge
 		device pci 00.0 on  end	# Host bridge Host bridge
 		device pci 01.0 on  end	# PCIe Bridge for discrete graphics
 		device pci 02.0 on  end	# Internal graphics VGA controller
+		device pci 06.0 off end	# Extra x4 port on north bridge

 		chip southbridge/intel/bd82x6x # Intel Series 7 PCH
 			register "docking_supported" = "0"
@@ -47,8 +48,8 @@ chip northbridge/intel/sandybridge
 			device pci 1c.3 off end	# PCIe Port #4
 			device pci 1c.4 on  end	# PCIe Port #5
 			device pci 1c.5 off end	# PCIe Port #6
-			device pci 1c.6 on  end	# PCIe Port #7
-			device pci 1c.7 on  end	# PCIe Port #8
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
 			device pci 1d.0 on  end	# USB2 EHCI #1
 			device pci 1e.0 on  end	# PCI bridge
 			device pci 1f.0 on	# LPC bridge PCI-LPC bridge
--- a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb
+++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb
@@ -3,6 +3,7 @@
 chip northbridge/intel/sandybridge
 	device domain 0 on
 		subsystemid 0x103c 0x1791 inherit
+		device pci 06.0 on  end	# Extra x4 port on north bridge
 		chip southbridge/intel/bd82x6x
 			register "sata_port_map" = "0x3f"

@@ -10,6 +11,8 @@ chip northbridge/intel/sandybridge
 			device pci 1c.2 on  end	# PCIe Port #3
 			device pci 1c.3 on  end	# PCIe Port #4
 			device pci 1c.5 on  end	# PCIe Port #6
+			device pci 1c.6 on  end	# PCIe Port #7
+			device pci 1c.7 on  end	# PCIe Port #8
 		end
 	end
 end
--- a/src/mainboard/lenovo/haswell/Kconfig
+++ b/src/mainboard/lenovo/haswell/Kconfig
@@ -10,7 +10,6 @@ config BOARD_LENOVO_HASWELL_COMMON
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
-	select INTEL_INT15
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MAINBOARD_HAS_TPM1
 	select MAINBOARD_USES_IFD_GBE_REGION
@@ -23,6 +22,10 @@ config BOARD_LENOVO_HASWELL_COMMON

 config BOARD_LENOVO_THINKPAD_T440P
 	select BOARD_LENOVO_HASWELL_COMMON
+	select INTEL_INT15
+
+config BOARD_LENOVO_THINKPAD_W541
+	select BOARD_LENOVO_HASWELL_COMMON

 if BOARD_LENOVO_HASWELL_COMMON

@@ -43,6 +46,7 @@ config VBOOT_VBNV_OFFSET

 config VARIANT_DIR
 	default "t440p" if BOARD_LENOVO_THINKPAD_T440P
+	default "w541" if BOARD_LENOVO_THINKPAD_W541

 config DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
@@ -55,10 +59,11 @@ config MAINBOARD_DIR

 config MAINBOARD_PART_NUMBER
 	default "ThinkPad T440p" if BOARD_LENOVO_THINKPAD_T440P
+	default "ThinkPad W541" if BOARD_LENOVO_THINKPAD_W541

 config VGA_BIOS_ID
 	string
-	default "8086,0416"
+	default "8086,0416" if BOARD_LENOVO_THINKPAD_T440P

 config USBDEBUG_HCD_INDEX
 	int
@@ -72,9 +77,13 @@ config PS2K_EISAID
 	default "LEN0071"

 config PS2M_EISAID
-	default "LEN0036"
+	default "LEN0036" if BOARD_LENOVO_THINKPAD_T440P
+	default "LEN004A" if BOARD_LENOVO_THINKPAD_W541

 config THINKPADEC_HKEY_EISAID
 	default "LEN0068"

+config GFX_GMA_PANEL_1_PORT
+	default "DP3" if BOARD_LENOVO_THINKPAD_W541
+
 endif
--- a/src/mainboard/lenovo/haswell/Kconfig.name
+++ b/src/mainboard/lenovo/haswell/Kconfig.name
@@ -1,2 +1,5 @@
 config BOARD_LENOVO_THINKPAD_T440P
 	bool "ThinkPad T440p"
+
+config BOARD_LENOVO_THINKPAD_W541
+	bool "ThinkPad W541"
--- a/src/mainboard/lenovo/haswell/Makefile.inc
+++ b/src/mainboard/lenovo/haswell/Makefile.inc
@@ -1,5 +1,6 @@
 romstage-y += variants/$(VARIANT_DIR)/gpio.c
 romstage-y += variants/$(VARIANT_DIR)/romstage.c

-ramstage-y += mainboard.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+subdirs-y += variants/$(VARIANT_DIR)
--- a/src/mainboard/lenovo/haswell/variants/t440p/Makefile.inc
+++ b/src/mainboard/lenovo/haswell/variants/t440p/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += mainboard.c
--- a/src/mainboard/lenovo/haswell/variants/t440p/mainboard.c
+++ b/src/mainboard/lenovo/haswell/variants/t440p/mainboard.c
--- a/src/mainboard/lenovo/haswell/variants/w541/board_info.txt
+++ b/src/mainboard/lenovo/haswell/variants/w541/board_info.txt
--- a/src/mainboard/lenovo/haswell/variants/w541/data.vbt
+++ b/src/mainboard/lenovo/haswell/variants/w541/data.vbt
--- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
--- a/src/mainboard/lenovo/haswell/variants/w541/gma-mainboard.ads
+++ b/src/mainboard/lenovo/haswell/variants/w541/gma-mainboard.ads
--- a/Show More
+++ b/Show More