darp7 SD card does not support RTD3

Change-Id: Ie393e9cd42f58d2b3b7172c99b9cd5a1b3a41d87

Documentation/arch/x86/index.md

@@ -65,33 +65,3 @@ The reference implementation is
 * Test how well CAR works with x86_64 and paging
 * Improve mode switches
 * Test libgfxinit / VGA Option ROMs / FSP
-
-## Known bugs on real hardware
-
-According to Intel x86_64 mode hasn't been validated in CAR environments.
-Until now it could be verified on various Intel platforms and no issues have
-been found.
-
-## Known bugs on KVM enabled qemu
-
-The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues
-when using KVM mode on some machines. The workaround is to *not* place
-page-tables in ROM, as done in
-[CB:49228](https://review.coreboot.org/c/coreboot/+/49228).
-
-Here's a list of known issues:
-
-* After entering long mode, the FPU doesn't work anymore, including accessing
-  MMX registers. It works fine before entering long mode. It works fine when
-  switching back to protected mode. Other registers, like SSE registers, are
-  working fine.
-* Reading from virtual memory, when the page tables are stored in ROM, causes
-  the MMU to abort the "page table walking" mechanism when the lower address
-  bits of the virtual address to be translated have a specific pattern.
-  Instead of loading the correct physical page, the one containing the
-  page tables in ROM will be loaded and used, which breaks code and data as
-  the page table doesn't contain the expected data. This in turn leads to
-  undefined behaviour whenever the 'wrong' address is being read.
-* Disabling paging in compability mode crashes the CPU.
-* Returning from long mode to compability mode crashes the CPU.
-* Entering long mode crashes on AMD host platforms.

Documentation/cbfstool/index.md

@@ -1,5 +0,0 @@
-# cbfstool
-
-Contents:
-
-* [Handling memory mapped boot media](mmap_windows.md)

Documentation/cbfstool/mmap_windows.md

@@ -1,77 +0,0 @@
-# cbfstool: Handling memory mapped boot media
-
-`cbfstool` is a utility used for managing coreboot file system (CBFS)
-components in a ROM image. x86 platforms are special since they have
-the SPI flash boot media memory mapped into host address space at
-runtime. This requires `cbfstool` to deal with two separate address
-spaces for any CBFS components that are eXecute-In-Place (XIP) - one
-is the SPI flash address space and other is the host address space
-where the SPI flash gets mapped.
-
-By default, all x86 platforms map a maximum of 16MiB of SPI flash at
-the top of 4G in host address space. If the flash is greater than
-16MiB, then only the top 16MiB of the flash is mapped in the host
-address space. If the flash is smaller than 16MiB, then the entire SPI
-flash is mapped at the top of 4G and the rest of the space remains
-unused.
-
-In more recent platforms like Tiger Lake (TGL), it is possible to map
-more than 16MiB of SPI flash. Since the host address space has legacy
-fixed device addresses mapped below `4G - 16M`, the SPI flash is split
-into separate windows when being mapped to the host address space.
-Default decode window of maximum 16MiB size still lives just below the
-4G boundary. The additional decode window is free to live in any
-available MMIO space that the SoC chooses.
-
-Following diagram shows different combinations of SPI flash being
-mapped into host address space when using multiple windows:
-
-![MMAP window combinations with different flash sizes][mmap_windows]
-
-*(a) SPI flash of size 16MiB (b) SPI flash smaller than 16MiB (c) SPI flash
-of size (16MiB+ext window size) (d) SPI flash smaller than (16MiB+ext
-window size)*
-
-The location of standard decode window is fixed in host address space
-`(4G - 16M) to 4G`. However, the platform is free to choose where the
-extended window lives in the host address space. Since `cbfstool`
-needs to know the exact location of the extended window, it allows the
-platform to pass in two parameters `ext-win-base` and `ext-win-size`
-that provide the base and the size of the extended window in host
-address space.
-
-`cbfstool` creates two memory map windows using the knowledge about the
-standard decode window and the information passed in by the platform
-about the extended decode window. These windows are useful in
-converting addresses from one space to another (flash space and host
-space) when dealing with XIP components.
-
-## Assumptions
-
-1. Top 16MiB is still decoded in the fixed decode window just below 4G
-   boundary.
-1. Rest of the SPI flash below the top 16MiB is mapped at the top of
-   the extended window. Even though the platform might support a
-   larger extended window, the SPI flash part used by the mainboard
-   might not be large enough to be mapped in the entire window. In
-   such cases, the mapping is assumed to be in the top part of the
-   extended window with the bottom part remaining unused.
-
-## Example
-
-If the platform supports extended window and the SPI flash size is
-greater, then `cbfstool` creates a mapping for the extended window as
-well.
-
-```
-ext_win_base = 0xF8000000
-ext_win_size = 32 * MiB
-ext_win_limit = ext_win_base + ext_win_size - 1 = 0xF9FFFFFF
-```
-
-If SPI flash is 32MiB, then top 16MiB is mapped from `0xFF000000 -
-0xFFFFFFFF` whereas the bottom 16MiB is mapped from `0xF9000000 -
-0xF9FFFFFF`. The extended window `0xF8000000 - 0xF8FFFFFF` remains
-unused.
-
-[mmap_windows]: mmap_windows.svg

Documentation/drivers/index.md

@@ -4,9 +4,7 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code accross platforms.
 
-* [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
 * [SoundWire](soundwire.md)
 * [SMMSTOREv2](smmstorev2.md)
-* [USB4 Retimer](retimer.md)

Documentation/mainboard/index.md

@@ -16,7 +16,6 @@ This section contains documentation about coreboot on specific mainboards.
 
 ## ASUS
 
-- [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
 - [P5Q](asus/p5q.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
@@ -90,15 +89,15 @@ The boards in this section are not real mainboards, but emulators.
 - [X2xx common](lenovo/x2xx_series.md)
 - [vboot](lenovo/vboot.md)
 
+### Arrandale series
+
+- [T410](lenovo/t410.md)
+
 ### GM45 series
 
 - [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
 - [X301](lenovo/x301.md)
 
-### Arrandale series
-
-- [T410](lenovo/t410.md)
-
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
@@ -177,10 +176,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Lemur Pro](system76/lemp9.md)
 
-## Texas Instruments
-
-- [Beaglebone Black](ti/beaglebone-black.md)
-
 ## UP
 
 - [Squared](up/squared/index.md)

Documentation/mainboard/lenovo/montevina_series.md

@@ -9,15 +9,6 @@ the chip in your machine through flashrom:
 Note that this does not allow you to determine whether the chip is in a SOIC-8
 or a SOIC-16 package.
 
-## Installing with ME firmware
-
-To install coreboot and keep ME working, you don't need to do anything special
-with the flash descriptor. Only flash the `bios` region externally and don't
-touch any other regions:
-```console
-# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
-```
-
 ## Installing without ME firmware
 
 ```eval_rst
@@ -136,6 +127,15 @@ Chipset --->
 
 Then build coreboot and flash whole `build/coreboot.rom` to the chip.
 
+## Installing with ME firmware
+
+To install coreboot and keep ME working, you don't need to do anything special
+with the flash descriptor. Just flash only `bios` externally and don't touch any
+other regions:
+```console
+# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
+```
+
 ## Flash layout
 
 The flash layouts of the OEM firmware are as follows:

Documentation/mainboard/ocp/deltalake.md

@@ -9,25 +9,23 @@ build/test/release cycle.
 OCP Delta Lake server platform is a component of multi-host server system
 Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
 
-Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
+Delta Lake server is a single socket Cooper Lake Scalable Processor server.
 
 Yosemite-V3 has multiple configurations. Depending on configurations, it may
 host up to 4 Delta Lake servers in one sled.
 
-The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners
+The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners
 jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative
-solution. This development reached EVT exit equivalent status.
+solution. This development is moving toward EVT exit equivalent status.
 
 ## Required blobs
 
 This board currently requires:
 - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
   is not yet available to the public. It will be made public some time after the MP
-  (Mass Production) of CPX-SP.
+  (Mass Production) of CooperLake Scalable Processor when the FSP is mature.
 - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
-- ME binary: Ignition binary will be made public some time after the MP
-  of CPX-SP.
-- ACM binaries: only required for CBnT enablement.
+- ME binary: Not yet available to the public.
 
 ## Payload
 - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload.
@@ -50,16 +48,6 @@ To power off/on the host:
 To connect to console through SOL (Serial Over Lan):
     sol-util slotx
 
-## Firmware configurations
-[ChromeOS VPD] is used to store most of the firmware configurations.
-RO_VPD region holds default values, while RW_VPD region holds customized
-values.
-
-VPD variables supported are:
-- firmware_version: This variable holds overall firmware version. coreboot
-  uses that value to populate smbios type 1 version field.
-- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
-
 ## Working features
 The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root]
 as initramfs.
@@ -73,12 +61,8 @@ as initramfs.
     - Type 8 -- Port Connector Information
     - Type 9 -- PCI Slot Information
     - Type 11 -- OEM String
-    - Type 16 -- Physical Memory Array
-    - Type 17 -- Memory Device
-    - Type 19 -- Memory Array Mapped Address
     - Type 32 -- System Boot Information
     - Type 38 -- IPMI Device Information
-    - Type 41 -- Onboard Devices Extended Information
     - Type 127 -- End-of-Table
 - BMC integration:
     - BMC readiness check
@@ -87,12 +71,6 @@ as initramfs.
     - POST complete pin acknowledgement
     - Check BMC version: ipmidump -device
 - SEL record generation
-- Converged Bootguard and TXT (CBnT)
-    - TPM
-    - Bootguard profile 0T
-    - TXT
-    - SRTM (verified through tboot)
-    - memory secret clearance upon ungraceful shutdown
 - Early serial output
 - port 80h direct to GPIO
 - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
@@ -109,41 +87,44 @@ as initramfs.
 - Power button
 - localboot
 - netboot from IPv6
-- basic memory hardware error injection/detection (SMI handler not upstreamed)
-- basic PCIe hardware error injection/detection (SMI handler not upstreamed)
+- TPM
 
 ## Stress/performance tests passed
-- OS warm reboot (1000 cycles)
-- DC reboot (1000 cycles)
-- AC reboot (1000 cycle)
+- OS warm reboot (300 cycles)
+- DC reboot (300 cycles)
+- AC reboot (300 cycle)
 - Mprime test (6 hours)
 - StressAppTest (6 hours)
 - Ptugen (6 hours)
-
-## Performance tests on par with traditional firmware
-- coremark
-- SpecCPU
+- MLC (Intel Memory Latency Check)
 - Linkpack
 - Iperf(IPv6)
 - FIO
 
-## Other tests passed
-- Power
-- Thermal
+## Firmware configurations
+[ChromeOS VPD] is used to store most of the firmware configurations.
+RO_VPD region holds default values, while RW_VPD region holds customized
+values.
+
+VPD variables supported are:
+- firmware_version: This variable holds overall firmware version. coreboot
+  uses that value to populate smbios type 1 version field.
+- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
 
 ## Known issues
-- MLC (Intel Memory Latency Check) and stream performance issue
-- HECI access at OS run time:
-    - spsInfoLinux64 command fail to return ME version
-    - ptugen command fail to get memory power
+- spsInfoLinux64 command fail to return ME version.
+- fwts test failures related to mtrr.
+- kernel error message related to SleepButton ACPI event.
 
 ## Feature gaps
-- flashrom command not able to update ME region
-- ACPI APEI tables
-- PCIe hotplug, Virtual Pin Ports
-- PCIe Live Error Recovery
-- RO_VPD region as well as other RO regions are not write protected
-- Not able to selectively enable/disable core
+- SMBIOS:
+    - Type 16 -- Physical Memory Array
+    - Type 17 -- Memory Device
+    - Type 19 -- Memory Array Mapped Address
+    - Type 41 -- Onboard Devices Extended Information
+- Verified measurement through CBnT
+- Boot guard of CBnT
+- RO_VPD region as well as other RO regions are not write protected.
 
 ## Technology
 

Documentation/mainboard/ti/beaglebone-black.md

@@ -1,131 +0,0 @@
-# Beaglebone Black
-This page gives some details about the [BeagleBone Black] coreboot port and
-describes how to build and run it.
-
-The port currently only supports booting coreboot from a micro SD card and has
-some other limitations listed below.
-
-## Supported Boards
-The Beaglebone port supports the following boards:
-
-- Beaglebone Black
-- Beaglebone Black Wireless
-- Beaglebone Pocket (untested, may need tweaking)
-- Beaglebone Blue (untested, may need tweaking)
-- Beaglebone Original (untested, may need tweaking)
-
-## Use Cases
-This port was primarily developed as a learning exercise and there is
-potentially little reason to use it compared to the defacto bootloader choice of
-U-Boot. However, it does have some interesting practical use cases compared to
-U-Boot:
-
-1. Choosing coreboot as a lightweight alternative to U-Boot. In this case,
-   coreboot is used to do the absolute minimum necessary to boot Linux, forgoing
-   some U-Boot features and functionality. Complex boot logic can then instead
-   be moved into Linux where it can be more flexibly and safely executed. This
-   is essentially the LinuxBoot philosophy. [U-Boot Falcon mode] has similar
-   goals to this as well.
-2. Facilitating experimenting with coreboot on real hardware. The Beaglebone
-   Black is widely available at a low pricepoint (~$65) making it a great way to
-   experiment with coreboot on real ARMv7 hardware. It also works well as a
-   development platform as it has exposed pads for JTAG and, due to the way it
-   boots, is effectively impossible to brick.
-3. The Beaglebone Black is often used as a external flasher and EHCI debug
-   gadget in the coreboot community, so many members have access to it and can
-   use it as a reference platform.
-
-## Quickstart
-1. Run `make menuconfig` and select _TI_/_Beaglebone_ in the _Mainboard_ menu.
-2. Add a payload as normal.
-3. Run `make`.
-4. Copy the resulting `build/MLO` file to the micro SD card at offset 128k - ie
-   `dd if=build/MLO of=/dev/sdcard seek=1 bs=128k`.
-
-**NOTE**: By default, the Beaglebone is configured to try to boot first from
-eMMC before booting from SD card. To ensure that the Beaglebone boots from SD,
-either erase the internal eMMC or hold the _S2_ button while powering on (note
-that this has to be while powering on - ie when plugging in the USB or DC barrel
-jack - the boot order doesn't change on reset) to prioritize SD in the boot
-order.
-
-## Serial Console
-By default, coreboot uses UART0 as the serial console. UART0 is available
-through the J1 header on both the Beaglebone Black and Beaglebone Black
-Wireless. The serial runs at 3.3V and 115200 8n1.
-
-The pin mapping is shown below for J1.
-
-    ```eval_rst
-    +----------------------------+------------+
-    | Pin number                 | Function   |
-    +============================+============+
-    | 1 (Closest to barrel jack) | GND        |
-    +----------------------------+------------+
-    | 4                          | RX         |
-    +----------------------------+------------+
-    | 5                          | TX         |
-    +----------------------------+------------+
-    ```
-
-## Boot Process
-The AM335x contains ROM code to allow booting in a number of different
-configurations. More information about the boot ROM code can be found in the
-AM335x technical reference manual (_SPRUH73Q_) in the _Initialization_ section.
-
-This coreboot port is currently configured to boot in "SD Raw Mode" where the
-boot binary, with header ("Table of Contents" in TI's nomenclature), is placed
-at the offset of 0x20000 (128KB) on the SD card. The boot ROM loads the coreboot
-bootblock stage into SRAM and executes it.
-
-The bootblock and subsequent romstage and ramstage coreboot stages expect that
-the coreboot image, containing the CBFS, is located at 0x20000 on the SD card.
-All stages directly read from the SD card in order to load the next stage in
-sequence.
-
-## Clock Initialization and PMIC
-To simplify the port, the TPS65217C Power Management IC (PMIC) on the Beaglebone
-Black is not configured by coreboot. By default, the PMIC reset values for
-VDD_MPU (1.1V) and VDD_CORE (1.8V) are within the Operating Performance Point
-(OPP) for the MPU PLL configuration set by the boot ROM of 500 MHz.
-
-When using Linux as a payload, the kernel will appropriately scale the core
-voltages for the desired MPU clock frequency as defined in the device tree.
-
-One significant difference because of this to the U-Boot port is that the DCDC1
-rail that powers the DDR3 RAM will be 1.5V by default. The Micron DDR3 supports
-both 1.35V and 1.5V and U-Boot makes use of this by setting it to 1.35V to
-conserve power. Fortunately, Linux is again able to configure this rail but it
-involves adding an entry to the device tree:
-
-    &dcdc1_reg {
-    regulator-name = "vdd_ddr3";
-    regulator-min-microvolt = <1350000>;
-    regulator-max-microvolt = <1350000>;
-    regulator-boot-on;
-    regulator-always-on;
-    };
-
-If this port was to be extended to work with boards or SoCs with different
-requirements for the MPU clock frequency or different Operating Performance
-Points, then the port may need to be extended to set the core voltages and MPU
-PLL within coreboot, prior to loading a payload. Extending coreboot so that it
-can configure the PMIC would also be necessary if there was a requirement for
-coreboot to run at a different MPU frequency than the 500 MHz set by the boot
-ROM.
-
-# Todo
-- Allow coreboot to run from the Beaglebone Black's internal eMMC. This would
-  require updating the `mmc.c` driver to support running from both SD and eMMC.
-- Support the boot ROMs *FAT mode* so that the coreboot binary can be placed on
-  a FAT partition.
-- Increase the MMC read speed, it currently takes ~15s to read ~20MB which is a
-  bit slow. To do this, it should be possible to update the MMC driver to:
-    - Increase the supported blocksize (currently is always set to 1)
-    - Support 4-bit data width (currently only supports 1-bit data width)
-- Convert the while loops in the MMC driver to timeout so that coreboot does not
-  hang on a bad SD card or when the SD card is removed during boot.
-
-
-[Beaglebone Black]: https://beagleboard.org/black [U-Boot Falcon mode]:
-https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon

Documentation/soc/intel/icelake/iceLake_coreboot_development.md

@@ -20,6 +20,11 @@ Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel
    :doc:`../../../mainboard/intel/icelake_rvp`
    ```
 
+3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
+   ```eval_rst
+   :doc:`../../../mainboard/google/dragonegg`
+   ```
+
 ### Summary:
 * SoC is Ice Lake.
 * Reference platform is icelake_rvp.

Documentation/soc/intel/index.md

@@ -11,4 +11,4 @@ This section contains documentation about coreboot on specific Intel SOCs.
 - [Microcode Updates](microcode.md)
 - [Firmware Interface Table](fit.md)
 - [Apollolake](apollolake/index.md)
-- [CSE FW Update](cse_fw_update/cse_fw_update.md)
+- [CSE FW Update](cse_fw_update/cse_fw_update_model.md)

Documentation/util.md

@@ -20,7 +20,7 @@ status repository `Bash` `Go`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
-	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file `C`
+	* _cbfstool_ - For manipulating CBFS file `C`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`

MAINTAINERS

@@ -137,14 +137,6 @@ Maintainers List (try to look for most precise areas first)
 # Mainboards
 ################################################################################
 
-AMD family 17h and 19h reference boards
-M:	Marshall Dawson <marshalldawson3rd@gmail.com>
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-S:	Maintained
-F:	src/mainboard/amd/majolica/
-F:	src/mainboard/amd/mandolin/
-
 APPLE MAINBOARDS
 M:	Evgeny Zinoviev <me@ch1p.io>
 S:	Maintained
@@ -559,20 +551,6 @@ F:	src/drivers/intel/fsp2_0/
 # Systems on a Chip
 ################################################################################
 
-AMD Cezanne
-M:	Marshall Dawson <marshalldawson3rd@gmail.com>
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-S:	Maintained
-F:	src/soc/amd/cezanne/
-
-AMD common SoC code
-M:	Marshall Dawson <marshalldawson3rd@gmail.com>
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-S:	Maintained
-F:	src/soc/amd/common/
-
 AMD Picasso
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
@@ -717,8 +695,6 @@ F:	src/drivers/aspeed/common/
 F:	src/drivers/aspeed/ast2050/
 
 ACPI
-M:	Lance Zhao <lance.zhao@gmail.com>
-S:	Supported
 F:	src/acpi/
 F:	src/arch/x86/acpi/
 F:	util/acpi/

Makefile

@@ -8,7 +8,6 @@ src := src
 srck := $(top)/util/kconfig
 obj ?= build
 override obj := $(subst $(top)/,,$(abspath $(obj)))
-xcompile ?= $(obj)/xcompile
 objutil ?= $(obj)/util
 objk := $(objutil)/kconfig
 absobj := $(abspath $(obj))
@@ -120,7 +119,7 @@ UNIT_TEST:=1
 NOCOMPILE:=
 endif
 
-$(xcompile): util/xcompile/xcompile
+.xcompile: util/xcompile/xcompile
 	rm -f $@
 	$< $(XGCCPATH) > $@.tmp
 	\mv -f $@.tmp $@ 2> /dev/null
@@ -147,17 +146,15 @@ ifneq ($(UNIT_TEST),1)
 include $(DOTCONFIG)
 endif
 
-# The toolchain requires xcompile to determine the ARCH_SUPPORTED, so we can't
-# wait for make to generate the file.
-$(if $(wildcard $(xcompile)),, $(shell \
-	mkdir -p $(dir $(xcompile)) && \
-	util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile)))
+# in addition to the dependency below, create the file if it doesn't exist
+# to silence stupid warnings about a file that would be generated anyway.
+$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile)))
 
-include $(xcompile)
+-include .xcompile
 
 ifneq ($(XCOMPILE_COMPLETE),1)
-$(shell rm -f $(xcompile))
-$(error $(xcompile) deleted because it's invalid. \
+$(shell rm -f .xcompile)
+$(error .xcompile deleted because it's invalid. \
 	Restarting the build should fix that, or explain the problem)
 endif
 

Makefile.inc

@@ -77,15 +77,14 @@ PHONY+= clean-abuild coreboot check-style build-dirs build_complete
 
 #######################################################################
 # root source directories of coreboot
-subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
+subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
-subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*)
+subdirs-y += src/superio
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
 subdirs-y += src/cpu src/vendorcode
 subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
 subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu
-subdirs-y += util/ifdtool
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += src/security
@@ -184,6 +183,9 @@ decompressor-generic-ccopts += -D__DECOMPRESSOR__
 bootblock-generic-ccopts += -D__BOOTBLOCK__
 romstage-generic-ccopts += -D__ROMSTAGE__
 ramstage-generic-ccopts += -D__RAMSTAGE__
+ifeq ($(CONFIG_TRACE),y)
+ramstage-c-ccopts += -finstrument-functions
+endif
 ifeq ($(CONFIG_COVERAGE),y)
 ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
 endif
@@ -334,7 +336,7 @@ endef
 # arg2: binary file
 cbfs-files-processor-struct= \
 	$(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
-		printf "    CC+STRIP   $(1)\n"; \
+		printf "    CC+STRIP   $(@)\n"; \
 		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
 		$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
 		rm -f $(2).tmp) \
@@ -521,8 +523,7 @@ build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION
 # Report new `build.ht` as dependency if `build.h` differs.
 build_h_check := \
 	export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \
-	util/genbuild_h/genbuild_h.sh $(xcompile) \
-		>$(build_h)t 2>/dev/null; \
+	util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \
 	cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t
 
 $(build_h): $$(shell $$(build_h_check))
@@ -532,12 +533,6 @@ $(build_h): $$(shell $$(build_h_check))
 build-dirs $(objcbfs) $(objgenerated):
 	mkdir -p $(objcbfs) $(objgenerated)
 
-$(obj)/build_info:
-	@echo 'COREBOOT_VERSION: $(call strip_quotes,$(KERNELVERSION))' > $@.tmp
-	@echo 'MAINBOARD_VENDOR: $(call strip_quotes,$(CONFIG_MAINBOARD_VENDOR))' >> $@.tmp
-	@echo 'MAINBOARD_PART_NUMBER: $(call strip_quotes,$(CONFIG_MAINBOARD_PART_NUMBER))' >> $@.tmp
-	mv $@.tmp $@
-
 #######################################################################
 # Build the tools
 CBFSTOOL:=$(objutil)/cbfstool/cbfstool
@@ -577,6 +572,10 @@ endif
 BINCFG:=$(objutil)/bincfg/bincfg
 
 IFDTOOL:=$(objutil)/ifdtool/ifdtool
+$(IFDTOOL):
+	@printf "    Compile IFDTOOL\n"
+	+$(MAKE) -C $(top)/util/ifdtool
+	cp -a $(top)/util/ifdtool/ifdtool $@
 
 AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 
@@ -734,6 +733,16 @@ TXTIBB :=
 
 endif
 
+ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
+
+CBNTIBB := --cbnt
+
+else
+
+CBNTIBB :=
+
+endif # CONFIG_INTEL_CBNT_SUPPORT
+
 ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
 
 $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool
@@ -827,10 +836,6 @@ endif
 
 # cbfs-add-cmd-for-region
 # $(call cbfs-add-cmd-for-region,file in extract_nth format,region name)
-#
-# CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply
-# add commands with any additional arguments for cbfstool.
-# Example: --ext-win-base <base> --ext-win-size <size>
 define cbfs-add-cmd-for-region
 	$(CBFSTOOL) $@.tmp \
 	add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \
@@ -845,8 +850,8 @@ define cbfs-add-cmd-for-region
 	-r $(2) \
 	$(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \
 		$(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \
-		$(call extract_nth,7,$(1)) \
-	$(CBFSTOOL_ADD_CMD_OPTIONS)
+		$(call extract_nth,7,$(1))
+
 
 endef
 # Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a
@@ -970,25 +975,6 @@ else
 FMAP_SMMSTORE_ENTRY :=
 endif
 
-ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y)
-FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
-FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE))
-FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000)
-FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)
-FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE))
-else
-FMAP_SPD_CACHE_ENTRY :=
-endif
-
-ifeq ($(CONFIG_VPD),y)
-FMAP_VPD_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
-FMAP_VPD_SIZE := $(CONFIG_VPD_FMAP_SIZE)
-FMAP_VPD_ENTRY := $(CONFIG_VPD_FMAP_NAME)@$(FMAP_VPD_BASE) $(FMAP_VPD_SIZE)
-FMAP_CURRENT_BASE := $(call int-add, $(FMAP_VPD_BASE) $(FMAP_VPD_SIZE))
-else
-FMAP_VPD_ENTRY :=
-endif
-
 #
 # X86 FMAP region
 #
@@ -1065,8 +1051,6 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
 	    -e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
 	    -e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
 	    -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
-	    -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
-	    -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
 	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
 	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
 		$(DEFAULT_FLASHMAP) > $@.tmp
@@ -1100,9 +1084,9 @@ ifeq ($(CONFIG_ARCH_X86),y)
 		-n bootblock \
 		-t bootblock \
 		$(TXTIBB) \
+		$(CBNTIBB) \
 		-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
-		$(TS_OPTIONS) \
-		$(CBFSTOOL_ADD_CMD_OPTIONS)
+		$(TS_OPTIONS)
 else # ifeq ($(CONFIG_ARCH_X86),y)
 	$(CBFSTOOL) $@.tmp write -u \
 		-r BOOTBLOCK \
@@ -1114,11 +1098,10 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
 		-f $@.tmp.2 \
 		-n "header pointer" \
 		-t "cbfs header" \
-		-b -4 \
-		$(CBFSTOOL_ADD_CMD_OPTIONS)
+		-b -4
 	rm -f $@.tmp.2
 endif # ifeq ($(CONFIG_ARCH_X86),y)
-	$(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
+	$(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS)
 	$(prebuild-files) true
 	mv $@.tmp $@
 else # ifneq ($(CONFIG_UPDATE_IMAGE),y)
@@ -1144,10 +1127,6 @@ else
 RAMSTAGE=
 endif
 
-add_intermediate = \
-	$(1): $(2) | $(INTERMEDIATE) \
-	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
-
 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
@@ -1226,10 +1205,6 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision
 revision-file := $(obj)/build.h
 revision-type := raw
 
-cbfs-files-y += build_info
-build_info-file := $(obj)/build_info
-build_info-type := raw
-
 BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
 cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
 bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
@@ -1251,7 +1226,7 @@ cbfs-get-segments-cmd = $(CBFSTOOL) $(obj)/coreboot.pre print -v | sed -n \
 ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \
 	sed -n '/ $(1)$$/s/^\([0-9a-fA-F]*\) .*/0x\1/p'
 
-$(call add_intermediate, check-ramstage-overlaps, $(obj)/coreboot.pre)
+check-ramstage-overlaps: $(obj)/coreboot.pre
 	programs=$$($(foreach file,$(check-ramstage-overlap-files), \
 		$(call cbfs-get-segments-cmd,$(file)) ; )) ; \
 	regions=$$($(foreach region,$(check-ramstage-overlap-regions), \
@@ -1277,4 +1252,6 @@ $(call add_intermediate, check-ramstage-overlaps, $(obj)/coreboot.pre)
 	    pstart= ; pend= ; \
 	done
 
+INTERMEDIATE+=check-ramstage-overlaps
+PHONY+=check-ramstage-overlaps
 endif

configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100

@@ -1,38 +0,0 @@
-# Not meant for actual use, but rather to build-test individual options.
-# If keeping this combination of options buildable becomes too hard in
-# the future, then this config can be split into several smaller chunks.
-# Exercises, among other things:
-# + PCIe hotplug
-# + Fatal assertions
-# + Debug options
-# + SMMSTORE
-# + YABEL
-# + VESA framebuffer
-# + EM100 support
-CONFIG_VENDOR_ASUS=y
-CONFIG_CBFS_SIZE=0x200000
-CONFIG_BOARD_ASUS_P8Z77_V_LX2=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-# CONFIG_S3_VGA_ROM_RUN is not set
-CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y
-CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y
-CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF=y
-CONFIG_VGA_ROM_RUN=y
-CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_VBE_LINEAR_FRAMEBUFFER=y
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SMMSTORE=y
-CONFIG_FATAL_ASSERTS=y
-CONFIG_DEBUG_CBFS=y
-CONFIG_DEBUG_RAM_SETUP=y
-CONFIG_DEBUG_SMBUS=y
-CONFIG_DEBUG_SMI=y
-CONFIG_DEBUG_MALLOC=y
-CONFIG_DEBUG_CONSOLE_INIT=y
-CONFIG_DEBUG_SPI_FLASH=y
-CONFIG_DEBUG_BOOT_STATE=y
-CONFIG_DEBUG_ADA_CODE=y
-CONFIG_HAVE_EM100_SUPPORT=y
-CONFIG_EM100=y

payloads/external/Makefile.inc

@@ -101,24 +101,26 @@ endif
 
 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
-$(call add_intermediate, seabios_ps2_timeout, $(obj)/coreboot.pre $(CBFSTOOL))
+ifneq ($(CONFIG_UPDATE_IMAGE),y)
+INTERMEDIATE+=seabios_ps2_timeout
+seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL)
 	@printf "    SeaBIOS    Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
-	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/ps2-keyboard-spinup 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup
 endif
 endif
+endif
 
 ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
-$(call add_intermediate, seabios_sercon, $(obj)/coreboot.pre $(CBFSTOOL))
+INTERMEDIATE+=seabios_sercon
+seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL)
 	@printf "    SeaBIOS    Add sercon-port file\n"
-	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/sercon-port 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
 endif
 
 ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
-$(call add_intermediate, seabios_thread_optionroms, $(obj)/coreboot.pre $(CBFSTOOL))
+INTERMEDIATE+=seabios_thread_optionroms
+seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL)
 	@printf "    SeaBIOS    Thread optionroms\n"
-	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/threads 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i 2 -n etc/threads
 endif
 
@@ -148,7 +150,6 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
 		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
-		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \

payloads/external/tianocore/Kconfig

@@ -100,12 +100,4 @@ config TIANOCORE_BOOTSPLASH_FILE
 	  If an absolute path is not given, the path will assumed to be
 	  relative to the coreboot root directory.
 
-config TIANOCORE_BOOT_TIMEOUT
-	int
-	default 2
-	help
-	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
-	  For boards with an internal display, the default value of 2s is generally sufficient.
-	  For boards without an internal display, a value of 5s is generally sufficient.
-
 endif

payloads/external/tianocore/Makefile

@@ -37,16 +37,12 @@ ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
 TIMER=-DUSE_HPET_TIMER
 endif
 
-TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
-
 ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-ARCH=-a IA32 -p $(bootloader)/$(bootloader)Ia32.dsc
+	BUILD_STR=-q -a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 else
-ARCH=-a IA32 -a X64 -p $(bootloader)/$(bootloader)Ia32X64.dsc
+	BUILD_STR=-q -a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 endif
 
-BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)
-
 all: clean build
 
 $(project_dir):

payloads/libpayload/Kconfig

@@ -375,6 +375,10 @@ config PC_KEYBOARD
 	default y if ARCH_X86 # uses IO
 	default n
 
+config PC_KEYBOARD_AT_TRANSLATED
+	bool "AT Translation keyboard device"
+	default n
+
 config PC_KEYBOARD_LAYOUT_US
 	bool "English (US) keyboard layout"
 	depends on PC_KEYBOARD

payloads/libpayload/Makefile

@@ -118,11 +118,6 @@ NOCOMPILE:=1
 endif
 endif
 
-xcompile ?= $(obj)/xcompile
-$(xcompile): $(top)/../../util/xcompile/xcompile
-	$< $(XGCCPATH) > $@.tmp
-	\mv -f $@.tmp $@ 2> /dev/null
-
 ifeq ($(NOCOMPILE),1)
 include $(TOPLEVEL)/Makefile.inc
 real-all: config
@@ -131,17 +126,13 @@ else
 
 # in addition to the dependency below, create the file if it doesn't exist
 # to silence stupid warnings about a file that would be generated anyway.
-$(if $(wildcard $(xcompile)),,$(shell	\
-	mkdir -p $(dir $(xcompile)) &&	\
-	$(top)/../../util/xcompile/xcompile $(XGCCPATH) > $(xcompile) || rm -f $(xcompile)))
+$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell $(top)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile)))
 
-include $(xcompile)
+.xcompile: $(top)/../../util/xcompile/xcompile
+	$< $(XGCCPATH) > $@.tmp
+	\mv -f $@.tmp $@ 2> /dev/null
 
-ifneq ($(XCOMPILE_COMPLETE),1)
-$(shell rm -f $(xcompile))
-$(error $(xcompile) deleted because it's invalid. \
-	Restarting the build should fix that, or explain the problem)
-endif
+-include .xcompile
 
 CC := $(CC_$(ARCH-y))
 AS := $(AS_$(ARCH-y))
@@ -303,7 +294,7 @@ doxygen-clean:
 	rm -rf $(DOXYGEN_OUTPUT_DIR)
 
 clean-for-update: doxygen-clean clean-for-update-target
-	rm -f $(allobjs) $(xcompile)
+	rm -f $(allobjs) .xcompile
 	rm -f $(DEPENDENCIES)
 	rmdir -p $(alldirs) 2>/dev/null >/dev/null || true
 

payloads/libpayload/Makefile.inc

@@ -69,10 +69,7 @@ ifeq ($(CONFIG_LP_LTO),y)
 CFLAGS += -flto
 endif
 
-$(obj)/libpayload.config: $(DOTCONFIG)
-	cp $< $@
-
-$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config
+$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER)
 	cmp $@ $< 2>/dev/null || cp $< $@
 
 library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a
@@ -124,7 +121,7 @@ install: real-target
 	install -m 755 bin/lpas $(DESTDIR)/libpayload/bin
 	install -m 644 bin/lp.functions $(DESTDIR)/libpayload/bin
 	install -m 644 $(DOTCONFIG) $(DESTDIR)/libpayload/libpayload.config
-	install -m 755 $(xcompile) $(DESTDIR)/libpayload/libpayload.xcompile
+	install -m 755 .xcompile $(DESTDIR)/libpayload/libpayload.xcompile
 
 clean-for-update-target:
 	rm -f $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a

payloads/libpayload/arch/arm64/mmu.c

@@ -705,8 +705,3 @@ void mmu_presysinfo_enable(void)
 	mmu_init(&usedmem_ranges);
 	mmu_enable();
 }
-
-const struct mmu_ranges *mmu_get_used_ranges(void)
-{
-	return &usedmem_ranges;
-}

payloads/libpayload/bin/lp.functions

@@ -35,10 +35,6 @@ warn() {
 	echo "Warning: $1"
 }
 
-# For in-tree builds, allow to override the libpayload build dir.
-
-_OBJ=${_OBJ:-$BASE/../build}
-
 # If the user didn't specify LIBPAYLOAD_PREFIX, then preload it
 # with the default prefix value
 
@@ -52,8 +48,8 @@ fi
 
 if [ -f $BASE/../lib/libpayload.a ]; then
 	_LIBDIR=$BASE/../lib
-elif [ -f $_OBJ/libpayload.config ]; then
-	_LIBDIR=$_OBJ
+elif [ -f $BASE/../build/libpayload.a ]; then
+	_LIBDIR=$BASE/../build
 else
 	_LIBDIR=$LIBPAYLOAD_PREFIX/lib
 fi

payloads/libpayload/bin/lpgcc

@@ -57,17 +57,11 @@ BASE=`dirname $0`
 # This will set the _LIBDIR and _INCDIR variables used below
 . $BASE/lp.functions
 
-if [ $_LIBDIR != $_OBJ ]; then
-	_DOTCONFIG=$BASE/../libpayload.config
-	_XCOMPILE=$BASE/../libpayload.xcompile
-else
-	_DOTCONFIG=$_OBJ/libpayload.config
-	_XCOMPILE=$_OBJ/xcompile
-fi
-
 # include libpayload config
-if [ -f $_DOTCONFIG ]; then
-	. $_DOTCONFIG
+if [ -f $BASE/../libpayload.config ]; then
+	. $BASE/../libpayload.config
+elif [ -f $BASE/../.config ]; then
+	. $BASE/../.config
 else
 	echo "Can't find config"
 	exit 1
@@ -143,19 +137,14 @@ while [ $# -gt 0 ]; do
 	shift
 done
 
-_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1"
+_CFLAGS="$_ARCHEXTRA -nostdinc -nostdlib -I$BASE/../build -I$_INCDIR -I$_ARCHINCDIR -D__LIBPAYLOAD__=1"
 
-if [ $_LIBDIR = $_OBJ ]; then
-    _CFLAGS="$_CFLAGS -I$_OBJ"
+if [ "$CONFIG_LP_PDCURSES" = y ]; then
+  _CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses"
+fi
 
-    if [ "$CONFIG_LP_PDCURSES" = y ]; then
-	_CFLAGS="$_CFLAGS -I$BASE/../curses/PDCurses -I$BASE/../curses/pdcurses-backend"
-	_CFLAGS="$_CFLAGS -I$BASE/../curses/form -I$BASE/../curses/menu"
-    fi
-
-    if [ "$CONFIG_LP_TINYCURSES" = y ]; then
+if [ "$CONFIG_LP_TINYCURSES" = y ]; then
   _CFLAGS="$_CFLAGS -I$BASE/../curses"
-    fi
 fi
 
 # Check for the -fno-stack-protector silliness
@@ -166,7 +155,7 @@ trygccoption -fno-stack-protector
 _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h"
 _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include"
 
-_LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static"
+_LDFLAGS="-L$BASE/../lib -L$_LIBDIR $_LDSCRIPT -static"
 
 if [ $DOLINK -eq 0 ]; then
     if [ $DEBUGME -eq 1 ]; then
@@ -178,15 +167,15 @@ else
     _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
     if [ -f $_ARCHLIBDIR/head.o ]; then
 	    HEAD_O=$_ARCHLIBDIR/head.o
-    elif [ -f $_OBJ/head.o ]; then
-	    HEAD_O=$_OBJ/head.o
+    elif [ -f $BASE/../build/head.o ]; then
+	    HEAD_O=$BASE/../build/head.o
     else
 	    echo "Could not find head.o"
 	    exit 1
     fi
 
-    if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] &&
-       grep -q fix-cortex-a53-843419 $_XCOMPILE; then
+    if grep -q ARM64_A53_ERRATUM_843419=y $BASE/../libpayload.config &&
+       grep -q fix-cortex-a53-843419 $BASE/../libpayload.xcompile; then
             _LDFLAGS="$_LDFLAGS -Wl,--fix-cortex-a53-843419"
     fi
 

payloads/libpayload/drivers/i8042/i8042.c

@@ -28,7 +28,6 @@
 
 #include <libpayload-config.h>
 #include <libpayload.h>
-#include <stdbool.h>
 #include <stddef.h>
 
 #include "i8042.h"
@@ -112,19 +111,6 @@ static u8 fifo_pop(struct fifo *fifo)
 	return ret;
 }
 
-/** Peek on the head of fifo queue.
- * Returns the oldest object on the queue if any.
- * In case the queue is empty 0 is returned.
- * @fifo: Fifo to use
- */
-static u8 fifo_peek(struct fifo *fifo)
-{
-	if (fifo_is_empty(fifo))
-		return 0;
-
-	return fifo->buf[fifo->rx];
-}
-
 /** Destroys a fifo queue.
  * @fifo: Fifo to use
  */
@@ -332,24 +318,6 @@ void i8042_write_data(u8 data)
 		return;
 }
 
-/**
- * Send command & data to keyboard controller.
- *
- * @param cmd: The command to be sent.
- * @param data: The data to be sent.
- * Returns 0 on success, -1 on failure.
- */
-static int i8042_cmd_with_data(const u8 cmd, const u8 data)
-{
-	const int ret = i8042_cmd(cmd);
-	if (ret != 0)
-		return ret;
-
-	i8042_write_data(data);
-
-	return ret;
-}
-
 /**
  * Probe for keyboard controller data and queue it.
  */
@@ -403,14 +371,6 @@ u8 i8042_read_data_ps2(void)
 	return fifo_pop(ps2_fifo);
 }
 
-/**
- * Returns available keyboard data without advancing the queue.
- */
-u8 i8042_peek_data_ps2(void)
-{
-	return fifo_peek(ps2_fifo);
-}
-
 /**
  * Returns available mouse data, if any.
  */
@@ -448,36 +408,3 @@ int i8042_wait_read_aux(void)
 
 	return (retries <= 0) ? -1 : i8042_read_data_aux();
 }
-
-/**
- * Get the keyboard scancode translation state.
- *
- * Returns: -1 on timeout, 1 if the controller translates
- *          scancode set #2 to #1, and 0 if not.
- */
-int i8042_get_kbd_translation(void)
-{
-	const int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE);
-	if (cfg < 0)
-		return cfg;
-
-	return !!(cfg & I8042_CMD_BYTE_XLATE);
-}
-
-/**
- * Sets the keyboard scancode translation state.
- *
- * Returns: -1 on timeout, 0 otherwise.
- */
-int i8042_set_kbd_translation(const bool xlate)
-{
-	int cfg = i8042_cmd_with_response(I8042_CMD_RD_CMD_BYTE);
-	if (cfg < 0)
-		return cfg;
-
-	if (xlate)
-		cfg |= I8042_CMD_BYTE_XLATE;
-	else
-		cfg &= ~I8042_CMD_BYTE_XLATE;
-	return i8042_cmd_with_data(I8042_CMD_WR_CMD_BYTE, cfg);
-}

payloads/libpayload/drivers/i8042/i8042.h

@@ -56,6 +56,9 @@
 #define   I8042_MODE_SCROLL_LOCK_ON	(1 << 0)
 #define   I8042_MODE_SCROLL_LOCK_OFF	(0 << 0)
 #define I8042_KBCMD_SET_SCANCODE	0xf0
+#define   I8042_SCANCODE_SET_1		(1)
+#define   I8042_SCANCODE_SET_2		(2)
+#define   I8042_SCANCODE_SET_3		(3)
 #define I8042_KBCMD_SET_TYPEMATIC	0xf3
 #define I8042_KBCMD_EN			0xf4
 #define I8042_KBCMD_DEFAULT_DIS		0xf5

payloads/libpayload/drivers/i8042/keyboard.c

@@ -28,7 +28,6 @@
  */
 
 #include <stdbool.h>
-#include <stdint.h>
 
 #include <keycodes.h>
 #include <libpayload-config.h>
@@ -36,12 +35,6 @@
 
 #include "i8042.h"
 
-#ifdef DEBUG
-#define debug(x...) printf(x)
-#else
-#define debug(x...) do {} while (0)
-#endif
-
 #define POWER_BUTTON         0x90
 #define MEDIA_KEY_PREFIX     0xE0
 
@@ -178,253 +171,16 @@ static struct layout_maps keyboard_layouts[] = {
 #endif
 };
 
-static void keyboard_drain_input(void)
-{
-	while (i8042_data_ready_ps2())
-		(void)i8042_read_data_ps2();
-}
-
 static bool keyboard_cmd(unsigned char cmd)
 {
-	const uint64_t timeout_us = cmd == I8042_KBCMD_RESET ? 1*1000*1000 : 200*1000;
-	const uint64_t start_time = timer_us(0);
-
 	i8042_write_data(cmd);
 
-	do {
-		if (!i8042_data_ready_ps2()) {
-			udelay(50);
-			continue;
-		}
-
-		const uint8_t data = i8042_read_data_ps2();
-		switch (data) {
-		case 0xfa:
-			return true;
-		case 0xfe:
-			return false;
-		default:
-			/* Warn only if we already disabled keyboard input. */
-			if (cmd != I8042_KBCMD_DEFAULT_DIS)
-				debug("WARNING: Keyboard sent spurious 0x%02x.\n", data);
-			break;
-		}
-	} while (timer_us(start_time) < timeout_us);
-
-	debug("ERROR: Keyboard command timed out.\n");
-	return false;
-}
-
-static bool set_scancode_set(const unsigned char set)
-{
-	bool ret;
-
-	if (set < 1 || set > 3)
-		return false;
-
-	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret) {
-		debug("ERROR: Keyboard set scancode failed!\n");
-		return ret;
-	}
-
-	ret = keyboard_cmd(set);
-	if (!ret) {
-		debug("ERROR: Keyboard scancode set#%u failed!\n", set);
-		return ret;
-	}
-
-	return ret;
-}
-
-static enum keyboard_state {
-	STATE_INIT = 0,
-	STATE_SIMPLIFIED_INIT,
-	STATE_DISABLE_SCAN,
-	STATE_DRAIN_INPUT,
-	STATE_DISABLE_TRANSLATION,
-	STATE_START_SELF_TEST,
-	STATE_SELF_TEST,
-	STATE_CONFIGURE,
-	STATE_CONFIGURE_SET1,
-	STATE_ENABLE_TRANSLATION,
-	STATE_ENABLE_SCAN,
-	STATE_RUNNING,
-	STATE_IGNORE,
-} keyboard_state;
-
-#define STATE_NAMES_ENTRY(name) [STATE_##name] = #name
-static const char *const state_names[] = {
-	STATE_NAMES_ENTRY(INIT),
-	STATE_NAMES_ENTRY(SIMPLIFIED_INIT),
-	STATE_NAMES_ENTRY(DISABLE_SCAN),
-	STATE_NAMES_ENTRY(DRAIN_INPUT),
-	STATE_NAMES_ENTRY(DISABLE_TRANSLATION),
-	STATE_NAMES_ENTRY(START_SELF_TEST),
-	STATE_NAMES_ENTRY(SELF_TEST),
-	STATE_NAMES_ENTRY(CONFIGURE),
-	STATE_NAMES_ENTRY(CONFIGURE_SET1),
-	STATE_NAMES_ENTRY(ENABLE_TRANSLATION),
-	STATE_NAMES_ENTRY(ENABLE_SCAN),
-	STATE_NAMES_ENTRY(RUNNING),
-	STATE_NAMES_ENTRY(IGNORE),
-};
-
-__attribute__((unused))
-static const char *state_name(enum keyboard_state state)
-{
-	if (state >= ARRAY_SIZE(state_names) || !state_names[state])
-		return "<unknown>";
-	return state_names[state];
-}
-
-static uint64_t keyboard_time;
-static uint64_t state_time;
-
-static void keyboard_poll(void)
-{
-	enum keyboard_state next_state = keyboard_state;
-	unsigned int i;
-
-	switch (keyboard_state) {
-
-	case STATE_INIT:
-		/* Wait until keyboard_init() has been called. */
-		break;
-
-	case STATE_SIMPLIFIED_INIT:
-		/* On the first try, start opportunistically, do
-		   the first steps at once and skip the self-test. */
-		(void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS);
-		keyboard_drain_input();
-		(void)i8042_set_kbd_translation(false);
-		next_state = STATE_CONFIGURE;
-		break;
-
-	case STATE_DISABLE_SCAN:
-		(void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS);
-		next_state = STATE_DRAIN_INPUT;
-		break;
-
-	case STATE_DRAIN_INPUT:
-		/* Limit number of bytes drained per poll. */
-		for (i = 0; i < 50 && i8042_data_ready_ps2(); ++i)
-			(void)i8042_read_data_ps2();
-		if (i == 0)
-			next_state = STATE_DISABLE_TRANSLATION;
-		break;
-
-	case STATE_DISABLE_TRANSLATION:
-		/* Be opportunistic and assume it's disabled on failure. */
-		(void)i8042_set_kbd_translation(false);
-		next_state = STATE_START_SELF_TEST;
-		break;
-
-	case STATE_START_SELF_TEST:
-		if (!keyboard_cmd(I8042_KBCMD_RESET))
-			debug("ERROR: Keyboard self-test couldn't be started.\n");
-		/* We ignore errors and always move to the self-test state
-		   which will simply try again if necessary. */
-		next_state = STATE_SELF_TEST;
-		break;
-
-	case STATE_SELF_TEST:
-		if (!i8042_data_ready_ps2()) {
-			if (timer_us(state_time) > 5*1000*1000) {
-				debug("WARNING: Keyboard self-test timed out.\n");
-				next_state = STATE_DISABLE_SCAN;
-			}
-			break;
-		}
-
-		const uint8_t self_test_result = i8042_read_data_ps2();
-		switch (self_test_result) {
-		case 0xaa:
-			debug("INFO: Keyboard self-test succeeded.\n");
-			next_state = STATE_CONFIGURE;
-			break;
-		case 0xfc:
-		case 0xfd:
-			/* Failure. Try again. */
-			debug("WARNING: Keyboard self-test failed.\n");
-			next_state = STATE_START_SELF_TEST;
-			break;
-		default:
-			debug("WARNING: Keyboard self-test received spurious 0x%02x\n",
-			       self_test_result);
-			break;
-		}
-		break;
-
-	case STATE_CONFIGURE:
-		if (set_scancode_set(2))
-			next_state = STATE_ENABLE_TRANSLATION;
-		else
-			next_state = STATE_CONFIGURE_SET1;
-		break;
-
-	case STATE_CONFIGURE_SET1:
-		if (!set_scancode_set(1)) {
-			debug("ERROR: Keyboard failed to set any scancode set.\n");
-			next_state = STATE_DISABLE_SCAN;
-			break;
-		}
-
-		next_state = STATE_ENABLE_SCAN;
-		break;
-
-	case STATE_ENABLE_TRANSLATION:
-		if (i8042_set_kbd_translation(true) != 0) {
-			debug("ERROR: Keyboard controller set translation failed!\n");
-			next_state = STATE_DISABLE_SCAN;
-			break;
-		}
-
-		next_state = STATE_ENABLE_SCAN;
-		break;
-
-	case STATE_ENABLE_SCAN:
-		if (!keyboard_cmd(I8042_KBCMD_EN)) {
-			debug("ERROR: Keyboard enable scanning failed!\n");
-			next_state = STATE_DISABLE_SCAN;
-			break;
-		}
-
-		next_state = STATE_RUNNING;
-		break;
-
-	case STATE_RUNNING:
-		/* TODO: Use echo command to detect detach. */
-		break;
-
-	case STATE_IGNORE:
-		/* TODO: Try again after timeout if it ever seems useful. */
-		break;
-
-	}
-
-	switch (next_state) {
-	case STATE_INIT:
-	case STATE_RUNNING:
-	case STATE_IGNORE:
-		break;
-	default:
-		if (timer_us(keyboard_time) > 30*1000*1000)
-			next_state = STATE_IGNORE;
-		break;
-	}
-
-	if (keyboard_state != next_state) {
-		debug("INFO: Keyboard advancing state to '%s'.\n", state_name(next_state));
-		keyboard_state = next_state;
-		state_time = timer_us(0);
-	}
+	return i8042_wait_read_ps2() == 0xfa;
 }
 
 bool keyboard_havechar(void)
 {
-	keyboard_poll();
-	return keyboard_state == STATE_RUNNING && i8042_data_ready_ps2();
+	return i8042_data_ready_ps2();
 }
 
 unsigned char keyboard_get_scancode(void)
@@ -557,22 +313,83 @@ static struct console_input_driver cons = {
 	.input_type = CONSOLE_INPUT_TYPE_EC,
 };
 
+/* Enable keyboard translated */
+static bool enable_translated(void)
+{
+	if (!i8042_cmd(I8042_CMD_RD_CMD_BYTE)) {
+		int cmd = i8042_read_data_ps2();
+		cmd |= I8042_CMD_BYTE_XLATE;
+		if (!i8042_cmd(I8042_CMD_WR_CMD_BYTE)) {
+			i8042_write_data(cmd);
+		} else {
+			printf("ERROR: i8042_cmd WR_CMD failed!\n");
+			return false;
+		}
+	} else {
+		printf("ERROR: i8042_cmd RD_CMD failed!\n");
+		return false;
+	}
+	return true;
+}
+
+/* Set scancode set 1 */
+static bool set_scancode_set(void)
+{
+	bool ret;
+	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
+	if (!ret) {
+		printf("ERROR: Keyboard set scancode failed!\n");
+		return ret;
+	}
+
+	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
+	if (!ret) {
+		printf("ERROR: Keyboard scancode set#1 failed!\n");
+		return ret;
+	}
+
+	/*
+	 * Set default parameters.
+	 * Fix for broken QEMU PS/2 make scancodes.
+	 */
+	ret = keyboard_cmd(I8042_KBCMD_SET_DEFAULT);
+	if (!ret) {
+		printf("ERROR: Keyboard set default params failed!\n");
+		return ret;
+	}
+
+	/* Enable scanning */
+	ret = keyboard_cmd(I8042_KBCMD_EN);
+	if (!ret) {
+		printf("ERROR: Keyboard enable scanning failed!\n");
+		return ret;
+	}
+
+	return ret;
+}
+
 void keyboard_init(void)
 {
-	if (keyboard_state != STATE_INIT)
-		return;
-
 	map = &keyboard_layouts[0];
 
 	/* Initialized keyboard controller. */
 	if (!i8042_probe() || !i8042_has_ps2())
 		return;
 
+	/* Empty keyboard buffer */
+	while (keyboard_havechar())
+		keyboard_getchar();
+
 	/* Enable first PS/2 port */
 	i8042_cmd(I8042_CMD_EN_KB);
 
-	keyboard_state = STATE_SIMPLIFIED_INIT;
-	keyboard_time = state_time = timer_us(0);
+	if (CONFIG(LP_PC_KEYBOARD_AT_TRANSLATED)) {
+		if (!enable_translated())
+			return;
+	} else {
+		if (!set_scancode_set())
+			return;
+	}
 
 	console_add_input_driver(&cons);
 }
@@ -587,18 +404,20 @@ void keyboard_disconnect(void)
 	if (!i8042_has_ps2())
 		return;
 
+	/* Empty keyboard buffer */
+	while (keyboard_havechar())
+		keyboard_getchar();
+
 	/* Disable scanning */
 	keyboard_cmd(I8042_KBCMD_DEFAULT_DIS);
-	keyboard_drain_input();
 
 	/* Send keyboard disconnect command */
 	i8042_cmd(I8042_CMD_DIS_KB);
 
 	/* Hand off with empty buffer */
-	keyboard_drain_input();
+	while (keyboard_havechar())
+		keyboard_getchar();
 
 	/* Release keyboard controller driver */
 	i8042_close();
-
-	keyboard_state = STATE_INIT;
 }

payloads/libpayload/include/arm64/arch/mmu.h

@@ -194,12 +194,4 @@ struct mmu_memrange* mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges,
  */
 void mmu_presysinfo_memory_used(uint64_t base, uint64_t size);
 void mmu_presysinfo_enable(void);
-
-/*
- * Functions for exposing the used memory ranges to payloads. The ranges contain
- * all used memory ranges that are actually used by payload. i.e. _start -> _end
- * in linker script, the coreboot tables and framebuffer/DMA allocated in MMU
- * initialization.
- */
-const struct mmu_ranges *mmu_get_used_ranges(void);
 #endif // __ARCH_ARM64_MMU_H__

payloads/libpayload/include/coreboot_tables.h

@@ -261,25 +261,12 @@ struct cb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-/* Memory map windows to translate addresses between SPI flash space and host address space. */
-struct flash_mmap_window {
-	uint32_t flash_base;
-	uint32_t host_base;
-	uint32_t size;
-};
-
 struct cb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
 	uint32_t flash_size;
 	uint32_t sector_size;
 	uint32_t erase_cmd;
-	/*
-	 * Number of mmap windows used by the platform to decode addresses between SPI flash
-	 * space and host address space. This determines the number of entries in mmap_table.
-	 */
-	uint32_t mmap_count;
-	struct flash_mmap_window mmap_table[0];
 };
 
 struct cb_boot_media_params {

payloads/libpayload/include/libpayload.h

@@ -233,15 +233,11 @@ u8 i8042_data_ready_ps2(void);
 u8 i8042_data_ready_aux(void);
 
 u8 i8042_read_data_ps2(void);
-u8 i8042_peek_data_ps2(void);
 u8 i8042_read_data_aux(void);
 
 int i8042_wait_read_ps2(void);
 int i8042_wait_read_aux(void);
 
-int i8042_get_kbd_translation(void);
-int i8042_set_kbd_translation(bool xlate);
-
 /** @} */
 
 /**

payloads/libpayload/include/sysinfo.h

@@ -40,9 +40,6 @@
 /* Up to 10 MAC addresses */
 #define SYSINFO_MAX_MACS 10
 
-/* Maximum of 2 MMAP windows for decoding SPI flash. */
-#define SYSINFO_MAX_MMAP_WINDOWS 2
-
 #include <coreboot_tables.h>
 
 /*
@@ -129,8 +126,6 @@ struct sysinfo_t {
 		uint32_t size;
 		uint32_t sector_size;
 		uint32_t erase_cmd;
-		uint32_t mmap_window_count;
-		struct flash_mmap_window mmap_table[SYSINFO_MAX_MMAP_WINDOWS];
 	} spi_flash;
 	uint64_t fmap_offset;
 	uint64_t cbfs_offset;

payloads/libpayload/libc/coreboot.c

@@ -211,13 +211,6 @@ static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info)
 	info->spi_flash.size = flash->flash_size;
 	info->spi_flash.sector_size = flash->sector_size;
 	info->spi_flash.erase_cmd = flash->erase_cmd;
-
-	if (flash->mmap_count == 0)
-		return;
-
-	info->spi_flash.mmap_window_count = MIN(flash->mmap_count, SYSINFO_MAX_MMAP_WINDOWS);
-	memcpy(info->spi_flash.mmap_table, flash->mmap_table,
-	       info->spi_flash.mmap_window_count * sizeof(struct flash_mmap_window));
 }
 
 static void cb_parse_boot_media_params(unsigned char *ptr,

payloads/libpayload/sample/Makefile

@@ -28,7 +28,7 @@
 
 # Sample libpayload Makefile.
 include ../.config
-include ../build/xcompile
+include ../.xcompile
 
 ARCH-$(CONFIG_LP_ARCH_ARM)   := arm
 ARCH-$(CONFIG_LP_ARCH_X86)   := x86_32

payloads/nvramcui/nvramcui.c

@@ -37,7 +37,7 @@ static int max(int x, int y)
 	return y;
 }
 
-static void render_form(FORM *form)
+void render_form(FORM *form)
 {
 	int y, x, line;
 	WINDOW *w = form_win(form);

src/Kconfig

@@ -720,6 +720,12 @@ config ACPI_NHLT
 	help
 	  Build support for NHLT (non HD Audio) ACPI table generation.
 
+config ACPI_LPIT
+	bool
+	default y
+	help
+	  Build an ACPI Low Power Idle Table.
+
 #These Options are here to avoid "undefined" warnings.
 #The actual selection and help texts are in the following menu.
 
@@ -905,7 +911,7 @@ config DEBUG_PERIODIC_SMI
 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 # printk(BIOS_DEBUG, ...) calls.
 config DEBUG_MALLOC
-	prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
+	prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
 	bool
 	default n
 	help
@@ -917,7 +923,7 @@ config DEBUG_MALLOC
 
 # Only visible if DEBUG_SPEW (8) is set.
 config DEBUG_RESOURCES
-	bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
+	bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8
 	default n
 	help
 	  This option enables additional PCI memory and IO debug messages.
@@ -939,7 +945,7 @@ config DEBUG_CONSOLE_INIT
 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
 # printk(BIOS_DEBUG, ...) calls.
 config REALMODE_DEBUG
-	prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
+	prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
 	bool
 	default n
 	depends on PCI_OPTION_ROM_RUN_REALMODE
@@ -1113,12 +1119,23 @@ config DEBUG_INTEL_ME
 	  is present on Intel 6-series chipsets.
 endif
 
+config TRACE
+	bool "Trace function calls"
+	default n
+	help
+	  If enabled, every function will print information to console once
+	  the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+	  the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+	  of calling function. Please note some printk related functions
+	  are omitted from trace to have good looking console dumps.
+
 config DEBUG_FUNC
 	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
 	default n
 	help
 	  This option enables additional function entry and exit debug messages
-	  for select functions.
+	  for select functions. If supported, this is less output than
+	  the TRACE option.
 	  Note: This option will increase the size of the coreboot image.
 	  If unsure, say N.
 

src/acpi/Kconfig

@@ -24,11 +24,8 @@ config ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	  Provide common definitions for Intel hardware PM1_CNT register sleep
 	  values.
 
-config ACPI_SOC_NVS
+config ACPI_NO_SMI_GNVS
 	bool
-	help
-	  Set to indicate <soc/nvs.h> exists for the platform with a definition
-	  for global_nvs.
 
 config ACPI_NO_PCAT_8259
 	bool
@@ -40,9 +37,3 @@ config HAVE_ACPI_TABLES
 	help
 	  This variable specifies whether a given board has ACPI table support.
 	  It is usually set in mainboard/*/Kconfig.
-
-config ACPI_LPIT
-	bool
-	depends on HAVE_ACPI_TABLES
-	help
-	  Selected by platforms that support and fill Intel Low Power Idle Table.

src/acpi/Makefile.inc

@@ -12,7 +12,6 @@ ramstage-y += acpigen_usb.c
 ramstage-y += device.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c
 ramstage-y += gnvs.c
-ramstage-$(CONFIG_ACPI_SOC_NVS) += nvs.c
 ramstage-y += pld.c
 ramstage-y += sata.c
 ramstage-y += soundwire.c

src/acpi/acpi.c

@@ -878,35 +878,6 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 	header->checksum = acpi_checksum((void *)ivrs, header->length);
 }
 
-void acpi_create_crat(struct acpi_crat_header *crat,
-		      unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct,
-		      unsigned long current))
-{
-	acpi_header_t *header = &(crat->header);
-	unsigned long current = (unsigned long)crat + sizeof(struct acpi_crat_header);
-
-	memset((void *)crat, 0, sizeof(struct acpi_crat_header));
-
-	if (!header)
-		return;
-
-	/* Fill out header fields. */
-	memcpy(header->signature, "CRAT", 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-
-	header->asl_compiler_revision = asl_revision;
-	header->length = sizeof(struct acpi_crat_header);
-	header->revision = get_acpi_table_revision(CRAT);
-
-	current = acpi_fill_crat(crat, current);
-
-	/* (Re)calculate length and checksum. */
-	header->length = current - (unsigned long)crat;
-	header->checksum = acpi_checksum((void *)crat, header->length);
-}
-
 unsigned long acpi_write_hpet(const struct device *device, unsigned long current,
 	acpi_rsdp_t *rsdp)
 {
@@ -1293,42 +1264,76 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	    acpi_checksum((void *) fadt, header->length);
 }
 
-void acpi_create_lpit(acpi_lpit_t *lpit)
+/*
+ * The value of residency couneter register address is MSR value and
+ * implementation specific.e.e.g, scenerios:
+ * 1. For CNL: space_id:0,residency_counter.addrl:0x632 and ACPI_LPIT
+ * selected in soc Kconfig sysfs file thet kernel creates is
+ * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us.
+ * 2. For CNL: space_id:0, residency_counter.addrl:0xfe000000 + 0x193C
+ * and ACPI_LPIT elected in soc Kconfig sysfs file thet kernel creates is
+ * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
+ * which gets populated with integer values whenever system goes in s0ix.
+ */
+__weak void soc_residency_counter(struct acpi_lpit_native *lpit_soc)
 {
-	acpi_header_t *header = &(lpit->header);
-	unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t);
+	lpit_soc->header.unique_id = 0;
 
-	memset((void *)lpit, 0, sizeof(acpi_lpit_t));
+	lpit_soc->residency = 0x7530;
+	lpit_soc->latency = 0xBB8;
 
-	if (!header)
-		return;
+	lpit_soc->entry_trigger.space_id = 0x7f;
+	lpit_soc->entry_trigger.bit_width = 0x01;
+	lpit_soc->entry_trigger.bit_offset = 0x02;
+	lpit_soc->entry_trigger.addrl = 0x60;
 
-	/* Fill out header fields. */
-	memcpy(header->signature, "LPIT", 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-
-	header->asl_compiler_revision = asl_revision;
-	header->revision = get_acpi_table_revision(LPIT);
-	header->oem_revision = 42;
-	header->length = sizeof(acpi_lpit_t);
-
-	current = acpi_fill_lpit(current);
-
-	/* (Re)calculate length and checksum. */
-	header->length = current - (unsigned long)lpit;
-	header->checksum = acpi_checksum((void *)lpit, header->length);
+	lpit_soc->residency_counter.space_id = 0x7f;
+	lpit_soc->residency_counter.bit_width = 0x40;
+	lpit_soc->residency_counter.addrl = 0x632;
 }
 
-unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid)
+__weak void system_residency_counter(struct acpi_lpit_native *lpit_system)
 {
-	memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t));
-	lpi_desc->header.length = sizeof(acpi_lpi_desc_ncst_t);
-	lpi_desc->header.type = ACPI_LPI_DESC_TYPE_NATIVE_CSTATE;
-	lpi_desc->header.uid = uid;
+	lpit_system->header.unique_id = 1;
 
-	return lpi_desc->header.length;
+	lpit_system->counter_frequency = 0x256c;
+	lpit_system->residency = 0x7530;
+	lpit_system->latency = 0xBB8;
+
+	lpit_system->entry_trigger.space_id = 0x7f;
+	lpit_system->entry_trigger.bit_width = 0x01;
+	lpit_system->entry_trigger.bit_offset = 0x02;
+	lpit_system->entry_trigger.addrl = 0x60;
+
+	lpit_system->residency_counter.space_id = 0x00;
+	lpit_system->residency_counter.bit_width = 0x20;
+	lpit_system->residency_counter.access_size = 0x03;
+	lpit_system->residency_counter.addrl = 0xfe00193c;
+}
+
+static void acpi_create_lpit_generator(acpi_table_lpit *lpit)
+{
+	acpi_header_t *header = &(lpit->header);
+
+	memset((void *)lpit, 0, sizeof(acpi_table_lpit));
+
+	memcpy(header->signature, "LPIT", 4);
+	header->revision = 2; /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	header->oem_revision = 42;
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+	header->length = sizeof(acpi_table_lpit);
+	lpit->lpit_soc.header.length = sizeof(struct acpi_lpit_native);
+	lpit->lpit_system.header.length = sizeof(struct acpi_lpit_native);
+
+	soc_residency_counter(&lpit->lpit_soc);
+	system_residency_counter(&lpit->lpit_system);
+
+
+	/* (Re)calculate length and checksum. */
+	header->checksum = acpi_checksum((void *)lpit, header->length);
 }
 
 unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
@@ -1351,7 +1356,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_tcpa_t *tcpa;
 	acpi_tpm2_t *tpm2;
 	acpi_madt_t *madt;
-	acpi_lpit_t *lpit;
+	acpi_table_lpit *lpit;
 	struct device *dev;
 	unsigned long fw;
 	size_t slic_size, dsdt_size;
@@ -1408,7 +1413,9 @@ unsigned long write_acpi_tables(unsigned long start)
 		return fw;
 	}
 
-	dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size);
+	dsdt_file = cbfs_boot_map_with_leak(
+				     CONFIG_CBFS_PREFIX "/dsdt.aml",
+				     CBFS_TYPE_RAW, &dsdt_size);
 	if (!dsdt_file) {
 		printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n");
 		return current;
@@ -1421,7 +1428,8 @@ unsigned long write_acpi_tables(unsigned long start)
 		return current;
 	}
 
-	slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size);
+	slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic",
+				     CBFS_TYPE_RAW, &slic_size);
 	if (slic_file
 	    && (slic_file->length > slic_size
 		|| slic_file->length < sizeof(acpi_header_t)
@@ -1472,9 +1480,6 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += sizeof(acpi_header_t);
 
 		acpigen_set_current((char *) current);
-
-		acpi_fill_gnvs();
-
 		for (dev = all_devices; dev; dev = dev->next)
 			if (dev->ops && dev->ops->acpi_inject_dsdt)
 				dev->ops->acpi_inject_dsdt(dev);
@@ -1549,18 +1554,6 @@ unsigned long write_acpi_tables(unsigned long start)
 		}
 	}
 
-	if (CONFIG(ACPI_LPIT)) {
-		printk(BIOS_DEBUG, "ACPI:     * LPIT\n");
-
-		lpit = (acpi_lpit_t *)current;
-		acpi_create_lpit(lpit);
-		if (lpit->header.length >= sizeof(acpi_lpit_t)) {
-			current += lpit->header.length;
-			current = acpi_align_current(current);
-			acpi_add_table(rsdp, lpit);
-		}
-	}
-
 	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
 
 	madt = (acpi_madt_t *) current;
@@ -1570,6 +1563,17 @@ unsigned long write_acpi_tables(unsigned long start)
 		acpi_add_table(rsdp, madt);
 	}
 
+	if (CONFIG(ACPI_LPIT)) {
+		printk(BIOS_DEBUG, "ACPI:     * LPIT\n");
+
+		lpit = (acpi_table_lpit *)current;
+		acpi_create_lpit_generator(lpit);
+		if (lpit->header.length >= sizeof(acpi_table_lpit)) {
+			current += lpit->header.length;
+			acpi_add_table(rsdp, lpit);
+		}
+	}
+
 	current = acpi_align_current(current);
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
@@ -1718,10 +1722,6 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 5;
 	case BERT:
 		return 1;
-	case CRAT:
-		return 1;
-	case LPIT: /* ACPI 5.1 up to 6.3: 0 */
-		return 0;
 	default:
 		return -1;
 	}

src/acpi/acpigen.c

@@ -291,10 +291,6 @@ void acpigen_emit_namestring(const char *namepath)
 	int dotcount = 0, i;
 	int dotpos = 0;
 
-	/* Check for NULL pointer */
-	if (!namepath)
-		return;
-
 	/* We can start with a '\'. */
 	if (namepath[0] == '\\') {
 		acpigen_emit_byte('\\');

src/acpi/chromeos-gnvs.c

@@ -6,10 +6,7 @@
 
 void gnvs_assign_chromeos(void)
 {
-	chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
-	if (!gnvs_chromeos)
-		return;
-
+	chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr();
 	chromeos_init_chromeos_acpi(gnvs_chromeos);
 
 	/* EC can override to ECFW_RW. */
@@ -18,12 +15,3 @@ void gnvs_assign_chromeos(void)
 	if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro())
 		gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
 }
-
-void gnvs_set_ecfw_rw(void)
-{
-	chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
-	if (!gnvs_chromeos)
-		return;
-
-	gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
-}

src/acpi/gnvs.c

@@ -24,20 +24,11 @@ void *acpi_get_gnvs(void)
 
 static void gnvs_assign_cbmc(void)
 {
-	uint32_t *gnvs_cbmc = gnvs_cbmc_ptr(gnvs);
+	uint32_t *gnvs_cbmc = gnvs_cbmc_ptr();
 	if (gnvs_cbmc)
 		*gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
 }
 
-/* Needs implementation in platform code. */
-__weak uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs_)
-{
-	return NULL;
-}
-
-__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { }
-__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }
-
 void *gnvs_get_or_create(void)
 {
 	size_t gnvs_size;
@@ -50,12 +41,10 @@ void *gnvs_get_or_create(void)
 		return gnvs;
 
 	gnvs_size = gnvs_size_of_array();
-	if (!gnvs_size)
-		return NULL;
 
 	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size);
 	if (!gnvs)
-		return NULL;
+		return gnvs;
 
 	memset(gnvs, 0, gnvs_size);
 
@@ -68,15 +57,13 @@ void *gnvs_get_or_create(void)
 	return gnvs;
 }
 
-void acpi_fill_gnvs(void)
+void acpi_inject_nvsa(void)
 {
-	if (!gnvs)
+	uintptr_t gnvs_address = (uintptr_t)acpi_get_gnvs();
+	if (!gnvs_address)
 		return;
 
-	soc_fill_gnvs(gnvs);
-	mainboard_fill_gnvs(gnvs);
-
 	acpigen_write_scope("\\");
-	acpigen_write_name_dword("NVSA", (uintptr_t)gnvs);
+	acpigen_write_name_dword("NVSA", gnvs_address);
 	acpigen_pop_len();
 }

src/acpi/nvs.c

@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <acpi/acpi_gnvs.h>
-#include <soc/nvs.h>
-#include <stdint.h>
-
-size_t gnvs_size_of_array(void)
-{
-	return sizeof(struct global_nvs);
-}
-
-uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs)
-{
-	return &gnvs->cbmc;
-}
-
-/* Some <soc/nvs.h> have no chromeos entry. */
-#if CONFIG(MAINBOARD_HAS_CHROMEOS)
-void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
-{
-	return &gnvs->chromeos;
-}
-#endif

src/arch/arm/Makefile.inc

@@ -27,6 +27,11 @@ endif # CONFIG_ARCH_ARM
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y)
 
+decompressor-y += id.S
+bootblock-y += id.S
+$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h
+$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
+
 decompressor-y += boot.c
 bootblock-y += boot.c
 decompressor-y += div0.c

src/arch/arm/id.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <build.h>
+
+	.section ".id", "a", %progbits
+
+	.globl __id_start
+__id_start:
+ver:
+	.asciz COREBOOT_VERSION
+vendor:
+	.asciz CONFIG_MAINBOARD_VENDOR
+part:
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end - ver  /* Reverse offset to the vendor id */
+.long __id_end - vendor  /* Reverse offset to the vendor id */
+.long __id_end - part    /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE                               /* Size of this romimage */
+	.globl __id_end
+
+__id_end:
+.previous

src/arch/arm64/Makefile.inc

@@ -26,6 +26,10 @@ decompressor-y += div0.c
 bootblock-y += div0.c
 decompressor-y += eabi_compat.c
 bootblock-y += eabi_compat.c
+decompressor-y += id.S
+bootblock-y += id.S
+$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h
+$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
 
 decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c

src/arch/arm64/id.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <build.h>
+
+	.section ".id", "a", %progbits
+
+	.globl __id_start
+__id_start:
+ver:
+	.asciz COREBOOT_VERSION
+vendor:
+	.asciz CONFIG_MAINBOARD_VENDOR
+part:
+	.asciz CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end - ver  /* Reverse offset to the vendor id */
+.long __id_end - vendor  /* Reverse offset to the vendor id */
+.long __id_end - part    /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE                               /* Size of this romimage */
+	.globl __id_end
+
+__id_end:
+.previous

src/arch/ppc64/bootblock.S

@@ -8,3 +8,27 @@
 .org 0x100, 0xff
 _start:
 	b _start
+	.section ".id", "a", %progbits
+
+	.section ".id", "a", @progbits
+
+	.globl __id_start
+__id_start:
+ver:
+	.asciz "4" //COREBOOT_VERSION
+vendor:
+	.asciz "qemu" //CONFIG_MAINBOARD_VENDOR
+part:
+	.asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+	/* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
+	/* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
+	/* Reverse offset to the part number */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part
+	/* of this romimage */
+.long CONFIG_ROM_SIZE
+	.globl __id_end
+
+__id_end:
+.previous

src/arch/ppc64/id.ld

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+SECTIONS {
+	. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+	.id (.): {
+		*(.id)
+	}
+}

src/arch/ppc64/prologue.inc

@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.section ".rom.data", "a", @progbits
+.section ".rom.text", "ax", @progbits

src/arch/x86/Kconfig

@@ -144,13 +144,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE
 	help
 	  Increase this value if preram cbmem console is getting truncated
 
-config CBFS_MCACHE_SIZE
-	hex
-	depends on !NO_CBFS_MCACHE
-	default 0x2000
-	help
-	  Increase this value if you see CBFS mcache overflow warnings.
-
 config PC80_SYSTEM
 	bool
 	default y if ARCH_X86
@@ -186,6 +179,10 @@ config HPET_ADDRESS
 	hex
 	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
 
+config ID_SECTION_OFFSET
+	hex
+	default 0x80
+
 # 64KiB default bootblock size
 config C_ENV_BOOTBLOCK_SIZE
 	hex

src/arch/x86/Makefile.inc

@@ -45,6 +45,25 @@ pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
 # common support for early assembly includes
 ###############################################################################
 
+# Chipset specific assembly stubs in the romstage program flow. Certain
+# boards have more than one assembly stub so collect those and put them
+# into a single generated file.
+crt0s = $(cpu_incs-y)
+
+$(objgenerated)/assembly.inc: build-dirs $$(crt0s)
+	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@
+
+
+define early_x86_assembly_entry_rule
+# $1 stage name
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated assembly.inc is a proper
+# dependency.
+$(1)-y += assembly_entry.S
+$(call src-to-obj,$(1),$(dir)/assembly_entry.S): $(objgenerated)/assembly.inc
+endef
+
 define early_x86_stage
 # $1 stage name
 # $2 oformat
@@ -79,7 +98,6 @@ bootblock-y += memmove.c
 bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
-bootblock-y += gdt_init.S
 bootblock-y += id.S
 bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 
@@ -103,7 +121,6 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 
-verstage-y += assembly_entry.S
 verstage-y += boot.c
 verstage-y += post.c
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S
@@ -125,6 +142,8 @@ verstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 
 verstage-libs ?=
 
+$(eval $(call early_x86_assembly_entry_rule,verstage))
+
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32),y)
 $(eval $(call early_x86_stage,verstage,elf32-i386))
 else
@@ -139,9 +158,10 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-y += assembly_entry.S
 romstage-y += boot.c
 romstage-y += post.c
+# gdt_init.S is included by entry32.inc when romstage is the first C
+# environment.
 romstage-y += gdt_init.S
 romstage-y += cpu_common.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
@@ -157,6 +177,8 @@ romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
 romstage-libs ?=
 
+$(eval $(call early_x86_assembly_entry_rule,romstage))
+
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
 $(eval $(call early_x86_stage,romstage,elf32-i386))
 else

src/arch/x86/acpi_s3.c

@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <arch/cpu.h>
 #include <commonlib/helpers.h>
+#include <cpu/x86/smm.h>
 #include <fallback.h>
 #include <timestamp.h>
 
@@ -17,6 +18,9 @@ extern unsigned int __wakeup_size;
 
 void __noreturn acpi_resume(void *wake_vec)
 {
+	/* Restore GNVS pointer in SMM if found. */
+	apm_control(APM_CNT_GNVS_UPDATE);
+
 	/* Call mainboard resume handler first, if defined. */
 	mainboard_suspend_resume();
 

src/arch/x86/bootblock.ld

@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-gdtptr_offset = gdtptr & 0xffff;
-nullidt_offset = nullidt & 0xffff;
-
-/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
- * Startup IPI message without RAM.
- */
-#if CONFIG(SIPI_VECTOR_IN_ROM)
-_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary");
-ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff;
-#endif
-
-SECTIONS {
-	/* Trigger an error if I have an unusable start address */
-	_bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");
-
-	. = _ID_SECTION;
-	.id (.): {
-		KEEP(*(.id));
-	}
-
-	/* Flashrom and FILO have two alternatives for the location of .id section. */
-	_ID_SECTION_END = SIZEOF(.fit_pointer) && SIZEOF(.id) > 0x28 ? 0xffffff80 : _X86_RESET_VECTOR;
-	_ID_SECTION = _ID_SECTION_END - SIZEOF(.id);
-
-	. = _FIT_POINTER;
-	.fit_pointer (.): {
-		KEEP(*(.fit_pointer));
-	}
-	_FIT_POINTER = SIZEOF(.fit_pointer) ? 0xffffffc0 : _X86_RESET_VECTOR;
-
-	. = 0xfffffff0;
-	_X86_RESET_VECTOR = .;
-	.reset . : {
-		*(.reset);
-		. = 15;
-		BYTE(0x00);
-	}
-}

src/arch/x86/bootblock_crt0.S

@@ -10,7 +10,7 @@
 
 #include <cpu/x86/cr.h>
 
-.section .init._start, "ax", @progbits
+.section .text
 
 /*
  * Include the old code for reset vector and protected mode entry. That code has

src/arch/x86/bootblock_normal.c

@@ -18,7 +18,7 @@ int legacy_romstage_selector(struct prog *romstage)
 	const char *boot_candidate;
 	size_t stages_len;
 
-	boot_candidate = cbfs_map("coreboot-stages", &stages_len);
+	boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len);
 	if (!boot_candidate)
 		boot_candidate = default_filenames;
 

src/arch/x86/c_start.S

@@ -142,10 +142,10 @@ gdtaddr:
 
 	/* This is the gdt for GCC part of coreboot.
 	 * It is different from the gdt in ASM part of coreboot
-	 * which is defined in gdt_init.S
+	 * which is defined in entry32.inc
 	 *
 	 * When the machine is initially started, we use a very simple
-	 * gdt from ROM (that in gdt_init.S) which only contains those
+	 * gdt from ROM (that in entry32.inc) which only contains those
 	 * entries we need for protected mode.
 	 *
 	 * When we're executing code from RAM, we want to do more complex
@@ -235,4 +235,10 @@ setCodeSelectorLongJump:
 	# restore rsp, it might not have been 16-byte aligned on entry
 	mov	%rdx, %rsp
 	ret
+
+	.previous
+.code64
+#else
+	.previous
+.code32
 #endif

src/arch/x86/car.ld

@@ -48,9 +48,6 @@
 
 	TIMESTAMP(., 0x200)
 
-#if !CONFIG(NO_CBFS_MCACHE)
-	CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
-#endif
 #if !CONFIG(NO_FMAP_CACHE)
 	FMAP_CACHE(., FMAP_SIZE)
 #endif
@@ -120,7 +117,3 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
 _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
 #endif
 _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
-#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE)
-_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
-_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
-#endif

src/arch/x86/gdt_init.S

@@ -1,10 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 .code32
-
-.section .init, "ax", @progbits
-
-.section .init._gdt_, "ax", @progbits
+.section ".text._gdt_", "ax", @progbits
 
 	.globl gdt_init
 gdt_init:
@@ -20,7 +17,7 @@ gdtptr:
 
 #ifdef __x86_64__
 .code64
-.section .init._gdt64_, "ax", @progbits
+.section ".text._gdt64_", "ax", @progbits
 	.globl gdt_init64
 gdt_init64:
 	/* Workaround a bug in the assembler.

src/arch/x86/id.S

@@ -2,23 +2,27 @@
 
 #include <build.h>
 
-.section ".id", "a", @progbits
+	.section ".id", "a", @progbits
 
+	.globl __id_start
+__id_start:
 ver:
 	.asciz COREBOOT_VERSION
 vendor:
 	.asciz CONFIG_MAINBOARD_VENDOR
 part:
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
-
-#if ENV_X86_64
-.long 	0xffffffff - ver + 1		/* Reverse offset to the version */
-.long	0xffffffff - vendor + 1		/* Reverse offset to the vendor id */
-.long	0xffffffff - part + 1		/* Reverse offset to the part number */
-#else
-.long 	- ver		/* Reverse offset to the version */
-.long	- vendor	/* Reverse offset to the vendor id */
-.long	- part		/* Reverse offset to the part number */
-#endif
-
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver     /* Reverse offset to the
+						     *vendor id
+						     */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor  /* Reverse offset to the
+						     * vendor id
+						     */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part    /* Reverse offset to the
+						     * part number
+						     */
 .long CONFIG_ROM_SIZE                               /* Size of this romimage */
+	.globl __id_end
+
+__id_end:
+.previous

src/arch/x86/id.ld

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+SECTIONS {
+	. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
+	.id (.): {
+		KEEP(*(.id))
+	}
+}

src/arch/x86/include/mode_switch.h

@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stddef.h>
-#include <stdint.h>
-
-#if ENV_X86_64
-int protected_mode_call_narg(uint32_t arg_count,
-			     uint32_t func_ptr,
-			     uint32_t opt_arg1,
-			     uint32_t opt_arg2);
-
-/*
- * Drops into protected mode and calls the function, which must have been compiled for x86_32.
- * After the function returns it enters long mode again.
- * The function pointer destination must be below 4GiB in physical memory.
- *
- * The called function doesn't have arguments and returns an int.
- */
-static inline int protected_mode_call(void *func)
-{
-	return protected_mode_call_narg(0, (uintptr_t)func, 0, 0);
-}
-
-/*
- * Drops into protected mode and calls the function, which must have been compiled for x86_32.
- * After the function returns it enters long mode again.
- * The function pointer destination must be below 4GiB in physical memory.
- * Only the lower 32bits of the argument are passed to the called function.
- *
- * The called function have one argument and returns an int.
- */
-static inline int protected_mode_call_1arg(void *func, uint32_t arg1)
-{
-	return protected_mode_call_narg(1, (uintptr_t)func, arg1, 0);
-}
-
-/*
- * Drops into protected mode and calls the function, which must have been compiled for x86_32.
- * After the function returns it enters long mode again.
- * The function pointer destination must be below 4GiB in physical memory.
- * Only the lower 32bits of the argument are passed to the called function.
- *
- * The called function has two arguments and returns an int.
- */
-static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2)
-{
-	return protected_mode_call_narg(2, (uintptr_t)func, arg1, arg2);
-}
-#else
-static inline int protected_mode_call(void *func)
-{
-	int (*doit)(void) = func;
-
-	return doit();
-}
-
-static inline int protected_mode_call_1arg(void *func, uint32_t arg1)
-{
-	int (*doit)(uint32_t arg1) = func;
-
-	return doit(arg1);
-}
-
-static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2)
-{
-	int (*doit)(uint32_t arg1, uint32_t arg2) = func;
-
-	return doit(arg1, arg2);
-}
-#endif

src/arch/x86/memlayout.ld

@@ -39,5 +39,11 @@ SECTIONS
 }
 
 #if ENV_BOOTBLOCK
-#include <arch/x86/bootblock.ld>
+/* Bootblock specific scripts which provide more SECTION directives. */
+#include <cpu/x86/16bit/entry16.ld>
+#include <cpu/x86/16bit/reset16.ld>
+#include <arch/x86/id.ld>
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#include <cpu/intel/fit/fit.ld>
+#endif
 #endif  /* ENV_BOOTBLOCK */

src/arch/x86/mmap_boot.c

@@ -2,7 +2,6 @@
 
 #include <boot_device.h>
 #include <endian.h>
-#include <spi_flash.h>
 
 /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
 #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE))
@@ -14,12 +13,3 @@ const struct region_device *boot_device_ro(void)
 {
 	return &boot_dev.rdev;
 }
-
-uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
-{
-	table->flash_base = 0;
-	table->host_base = (uint32_t)(uintptr_t)rom_base;
-	table->size = CONFIG_ROM_SIZE;
-
-	return 1;
-}

src/arch/x86/smbios.c

@@ -414,7 +414,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
 #if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)
 	u32 version_offset = (u32)smbios_string_table_len(t->eos);
 	/* SMBIOS offsets start at 1 rather than 0 */
-	chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1);
+	chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1);
 #endif
 	t->bios_version = smbios_add_string(t->eos, get_bios_version());
 	uint32_t rom_size = CONFIG_ROM_SIZE;

src/arch/x86/walkcbfs.S

@@ -21,7 +21,7 @@
 #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
 
 .code32
-.section .init
+.section .text
 .global walkcbfs_asm
 
 /*

src/commonlib/bsd/cbfs_mcache.c

@@ -95,7 +95,7 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
 	const void *end = mcache + mcache_size;
 	const void *current = mcache;
 
-	while (current + sizeof(uint32_t) <= end) {
+	while (current + sizeof(uint32_t) < end) {
 		const union mcache_entry *entry = current;
 
 		if (entry->magic == MCACHE_MAGIC_END)
@@ -106,8 +106,8 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
 		assert(entry->magic == MCACHE_MAGIC_FILE);
 		const uint32_t data_offset = be32toh(entry->file.h.offset);
 		const uint32_t data_length = be32toh(entry->file.h.len);
-		if (namesize <= data_offset - offsetof(union cbfs_mdata, h.filename) &&
-		    memcmp(name, entry->file.h.filename, namesize) == 0) {
+		if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) &&
+		    memcmp(name, entry->file.filename, namesize) == 0) {
 			LOG("Found '%s' @%#x size %#x in mcache @%p\n",
 			    name, entry->offset, data_length, current);
 			*data_offset_out = entry->offset + data_offset;

src/commonlib/bsd/cbfs_private.c

@@ -46,7 +46,7 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
 		const uint32_t data_offset = be32toh(mdata.h.offset);
 		const uint32_t data_length = be32toh(mdata.h.len);
 		const uint32_t type = be32toh(mdata.h.type);
-		const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_NULL);
+		const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2);
 
 		DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n",
 		      offset, type, attr_offset, data_offset, data_length);
@@ -75,7 +75,7 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
 		if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h),
 				  offset + sizeof(mdata.h), todo) != todo)
 			return CB_CBFS_IO;
-		DEBUG("File name: '%s'\n", mdata.h.filename);
+		DEBUG("File name: '%s'\n", mdata.filename);
 
 		if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset))
 			return CB_ERR;
@@ -134,9 +134,10 @@ static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_md
 			      size_t already_read, void *arg)
 {
 	struct cbfs_lookup_args *args = arg;
+
 	/* Check if the name we're looking for could fit, then we can safely memcmp() it. */
-	if (args->namesize > already_read - offsetof(union cbfs_mdata, h.filename) ||
-	    memcmp(args->name, mdata->h.filename, args->namesize) != 0)
+	if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) ||
+	    memcmp(args->name, mdata->filename, args->namesize) != 0)
 		return CB_CBFS_NOT_FOUND;
 
 	LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len));
@@ -158,35 +159,3 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_o
 	};
 	return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0);
 }
-
-const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check)
-{
-	uint32_t offset = be32toh(mdata->h.attributes_offset);
-	uint32_t end = be32toh(mdata->h.offset);
-
-	if (!offset)
-		return NULL;
-
-	while (offset + sizeof(struct cbfs_file_attribute) <= end) {
-		const struct cbfs_file_attribute *attr = (const void *)mdata->raw + offset;
-		const uint32_t tag = be32toh(attr->tag);
-		const uint32_t len = be32toh(attr->len);
-
-		if (offset + len > end) {
-			ERROR("Attribute %s[%u] overflows end of metadata\n",
-			      mdata->h.filename, tag);
-			return NULL;
-		}
-		if (tag == attr_tag) {
-			if (size_check && len != size_check) {
-				ERROR("Attribute %s[%u] size mismatch: %u != %zu\n",
-				      mdata->h.filename, tag, len, size_check);
-				return NULL;
-			}
-			return attr;
-		}
-		offset += len;
-	}
-
-	return NULL;
-}

src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h

@@ -48,8 +48,12 @@
  * avoid byte-order confusion, fields should always and only be converted to host byte order at
  * exactly the time they are read from one of these structures into their own separate variable.
  */
+#define CBFS_METADATA_MAX_SIZE 256
 union cbfs_mdata {
+	struct {
 		struct cbfs_file h;
+		char filename[];
+	};
 	uint8_t raw[CBFS_METADATA_MAX_SIZE];
 };
 
@@ -130,9 +134,4 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
 /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */
 size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size);
 
-/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian).
-   If |size| is not 0, will check that it matches the length of the attribute (if found)...
-   else caller is responsible for checking the |len| field to avoid reading out-of-bounds. */
-const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check);
-
 #endif	/* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */

src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h

@@ -6,40 +6,45 @@
 #include <stdint.h>
 #include <vb2_sha.h>
 
-enum cbfs_compression {
-	CBFS_COMPRESS_NONE	= 0,
-	CBFS_COMPRESS_LZMA	= 1,
-	CBFS_COMPRESS_LZ4	= 2,
-};
+/** These are standard values for the known compression
+    algorithms that coreboot knows about for stages and
+    payloads.  Of course, other CBFS users can use whatever
+    values they want, as long as they understand them. */
 
-enum cbfs_type {
-	CBFS_TYPE_DELETED	= 0x00000000,
-	CBFS_TYPE_NULL		= 0xffffffff,
-	CBFS_TYPE_BOOTBLOCK	= 0x01,
-	CBFS_TYPE_CBFSHEADER	= 0x02,
-	CBFS_TYPE_STAGE		= 0x10,
-	CBFS_TYPE_SELF		= 0x20,
-	CBFS_TYPE_FIT		= 0x21,
-	CBFS_TYPE_OPTIONROM	= 0x30,
-	CBFS_TYPE_BOOTSPLASH	= 0x40,
-	CBFS_TYPE_RAW		= 0x50,
-	CBFS_TYPE_VSA		= 0x51,
-	CBFS_TYPE_MBI		= 0x52,
-	CBFS_TYPE_MICROCODE	= 0x53,
-	CBFS_TYPE_FSP		= 0x60,
-	CBFS_TYPE_MRC		= 0x61,
-	CBFS_TYPE_MMA		= 0x62,
-	CBFS_TYPE_EFI		= 0x63,
-	CBFS_TYPE_STRUCT	= 0x70,
-	CBFS_TYPE_CMOS_DEFAULT	= 0xaa,
-	CBFS_TYPE_SPD		= 0xab,
-	CBFS_TYPE_MRC_CACHE	= 0xac,
-	CBFS_TYPE_CMOS_LAYOUT	= 0x01aa,
-};
+#define CBFS_COMPRESS_NONE  0
+#define CBFS_COMPRESS_LZMA  1
+#define CBFS_COMPRESS_LZ4   2
 
-#define CBFS_HEADER_MAGIC  0x4F524243		/* BE: 'ORBC' */
-#define CBFS_HEADER_VERSION1 0x31313131		/* BE: '1111' */
-#define CBFS_HEADER_VERSION2 0x31313132		/* BE: '1112' */
+/** These are standard component types for well known
+    components (i.e - those that coreboot needs to consume.
+    Users are welcome to use any other value for their
+    components */
+
+#define CBFS_TYPE_DELETED    0x00000000
+#define CBFS_TYPE_DELETED2   0xffffffff
+#define CBFS_TYPE_BOOTBLOCK  0x01
+#define CBFS_TYPE_STAGE      0x10
+#define CBFS_TYPE_SELF       0x20
+#define CBFS_TYPE_FIT        0x21
+#define CBFS_TYPE_OPTIONROM  0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW        0x50
+#define CBFS_TYPE_VSA        0x51
+#define CBFS_TYPE_MBI        0x52
+#define CBFS_TYPE_MICROCODE  0x53
+#define CBFS_TYPE_FSP        0x60
+#define CBFS_TYPE_MRC        0x61
+#define CBFS_TYPE_MMA        0x62
+#define CBFS_TYPE_EFI        0x63
+#define CBFS_TYPE_STRUCT     0x70
+#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_SPD          0xab
+#define CBFS_TYPE_MRC_CACHE    0xac
+#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
+
+#define CBFS_HEADER_MAGIC  0x4F524243
+#define CBFS_HEADER_VERSION1 0x31313131
+#define CBFS_HEADER_VERSION2 0x31313132
 #define CBFS_HEADER_VERSION  CBFS_HEADER_VERSION2
 
 /* this is the master cbfs header - it must be located somewhere available
@@ -63,15 +68,9 @@ struct cbfs_header {
 /* "Unknown" refers to CBFS headers version 1,
  * before the architecture was defined (i.e., x86 only).
  */
-enum cbfs_architecture {
-	CBFS_ARCHITECTURE_UNKNOWN  = 0xFFFFFFFF,
-	CBFS_ARCHITECTURE_X86      = 0x00000001,
-	CBFS_ARCHITECTURE_ARM      = 0x00000010,
-	CBFS_ARCHITECTURE_AARCH64  = 0x0000aa64,
-	CBFS_ARCHITECTURE_MIPS     = 0x00000100,	/* deprecated */
-	CBFS_ARCHITECTURE_RISCV    = 0xc001d0de,
-	CBFS_ARCHITECTURE_PPC64    = 0x407570ff,
-};
+#define CBFS_ARCHITECTURE_UNKNOWN  0xFFFFFFFF
+#define CBFS_ARCHITECTURE_X86      0x00000001
+#define CBFS_ARCHITECTURE_ARM      0x00000010
 
 /** This is a component header - every entry in the CBFS
     will have this header.
@@ -89,7 +88,6 @@ enum cbfs_architecture {
 */
 
 #define CBFS_FILE_MAGIC "LARCHIVE"
-#define CBFS_METADATA_MAX_SIZE 256
 
 struct cbfs_file {
 	char magic[8];
@@ -97,13 +95,8 @@ struct cbfs_file {
 	uint32_t type;
 	uint32_t attributes_offset;
 	uint32_t offset;
-	char filename[0];
 } __packed;
 
-#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406
-_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch");
-#endif
-
 /* The common fields of extended cbfs file attributes.
    Attributes are expected to start with tag/len, then append their
    specific fields. */
@@ -116,16 +109,13 @@ struct cbfs_file_attribute {
 
 /* Depending on how the header was initialized, it may be backed with 0x00 or
  * 0xff. Support both. */
-enum cbfs_file_attr_tag {
-	CBFS_FILE_ATTR_TAG_UNUSED	= 0,
-	CBFS_FILE_ATTR_TAG_UNUSED2	= 0xffffffff,
-	CBFS_FILE_ATTR_TAG_COMPRESSION	= 0x42435a4c, /* BE: 'BCZL' */
-	CBFS_FILE_ATTR_TAG_HASH		= 0x68736148, /* BE: 'hsaH' */
-	CBFS_FILE_ATTR_TAG_POSITION	= 0x42435350, /* BE: 'BCSP' */
-	CBFS_FILE_ATTR_TAG_ALIGNMENT	= 0x42434c41, /* BE: 'BCLA' */
-	CBFS_FILE_ATTR_TAG_IBB		= 0x32494242, /* BE: '2IBB' */
-	CBFS_FILE_ATTR_TAG_PADDING	= 0x47444150, /* BE: 'GNDP' */
-};
+#define CBFS_FILE_ATTR_TAG_UNUSED 0
+#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
+#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
+#define CBFS_FILE_ATTR_TAG_HASH 0x68736148
+#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350  /* PSCB */
+#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */
+#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */
 
 struct cbfs_file_attr_compression {
 	uint32_t tag;
@@ -186,13 +176,11 @@ struct cbfs_payload {
 	struct cbfs_payload_segment segments;
 };
 
-enum cbfs_payload_segment_type {
-	PAYLOAD_SEGMENT_CODE   = 0x434F4445,	/* BE: 'CODE' */
-	PAYLOAD_SEGMENT_DATA   = 0x44415441,	/* BE: 'DATA' */
-	PAYLOAD_SEGMENT_BSS    = 0x42535320,	/* BE: 'BSS ' */
-	PAYLOAD_SEGMENT_PARAMS = 0x50415241,	/* BE: 'PARA' */
-	PAYLOAD_SEGMENT_ENTRY  = 0x454E5452,	/* BE: 'ENTR' */
-};
+#define PAYLOAD_SEGMENT_CODE   0x434F4445
+#define PAYLOAD_SEGMENT_DATA   0x44415441
+#define PAYLOAD_SEGMENT_BSS    0x42535320
+#define PAYLOAD_SEGMENT_PARAMS 0x50415241
+#define PAYLOAD_SEGMENT_ENTRY  0x454E5452
 
 struct cbfs_optionrom {
 	uint32_t compression;

src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h

@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
-
-#ifndef _COMMONLIB_BSD_METADATA_HASH_H_
-#define _COMMONLIB_BSD_METADATA_HASH_H_
-
-#include <stdint.h>
-#include <vb2_sha.h>
-
-/* This structure is embedded somewhere in the (uncompressed) bootblock. */
-struct metadata_hash_anchor {
-	uint8_t magic[8];
-	struct vb2_hash cbfs_hash;
-	/* NOTE: This is just reserving space. sizeof(struct vb2_hash) may change between
-	   configurations/versions and cannot be relied upon, so the FMAP hash must be placed
-	   right after the actual data for the particular CBFS hash algorithm used ends. */
-	uint8_t reserved_space_for_fmap_hash[VB2_MAX_DIGEST_SIZE];
-} __packed;
-
-/* Always use this function to figure out the actual location of the FMAP hash. It always uses
-   the same algorithm as the CBFS hash. */
-static inline uint8_t *metadata_hash_anchor_fmap_hash(struct metadata_hash_anchor *anchor)
-{
-	return anchor->cbfs_hash.raw + vb2_digest_size(anchor->cbfs_hash.algo);
-}
-
-/*
- * Do not use this constant anywhere else in coreboot code to ensure the bit pattern really only
- * appears once in the CBFS image. The only coreboot file allowed to use this is
- * src/lib/metadata_anchor.c to define the actual anchor data structure. It is defined here so
- * that it can be shared with cbfstool (which may use it freely).
- */
-#define DO_NOT_USE_METADATA_HASH_ANCHOR_MAGIC_DO_NOT_USE	"\xadMdtHsh\x15"
-
-#endif /* _COMMONLIB_BSD_MASTER_HASH_H_ */

src/commonlib/cbfs.c

@@ -335,7 +335,7 @@ int cbfs_vb2_hash_contents(const struct region_device *cbfs,
 		if (cbfsf_file_type(fh, &ftype))
 			return VB2_ERROR_UNKNOWN;
 
-		if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL)
+		if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2)
 			continue;
 
 		rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data);

src/commonlib/include/commonlib/cbmem_id.h

@@ -25,7 +25,6 @@
 #define CBMEM_ID_IGD_OPREGION	0x4f444749
 #define CBMEM_ID_IMD_ROOT	0xff4017ff
 #define CBMEM_ID_IMD_SMALL	0x53a11439
-#define CBMEM_ID_MDATA_HASH	0x6873484D
 #define CBMEM_ID_MEMINFO	0x494D454D
 #define CBMEM_ID_MMA_DATA	0x4D4D4144
 #define CBMEM_ID_MMC_STATUS	0x4d4d4353
@@ -56,7 +55,6 @@
 #define CBMEM_ID_TCPA_TCG_LOG	0x54445041
 #define CBMEM_ID_TIMESTAMP	0x54494d45
 #define CBMEM_ID_TPM2_TCG_LOG	0x54504d32
-#define CBMEM_ID_TPM_PPI	0x54505049
 #define CBMEM_ID_VBOOT_HANDOFF	0x780074f0  /* deprecated */
 #define CBMEM_ID_VBOOT_SEL_REG	0x780074f1  /* deprecated */
 #define CBMEM_ID_VBOOT_WORKBUF	0x78007343

src/commonlib/include/commonlib/coreboot_tables.h

@@ -81,7 +81,6 @@ enum {
 	LB_TAG_FMAP			= 0x0037,
 	LB_TAG_PLATFORM_BLOB_VERSION	= 0x0038,
 	LB_TAG_SMMSTOREV2		= 0x0039,
-	LB_TAG_TPM_PPI_HANDOFF		= 0x003a,
 	LB_TAG_BOARD_CONFIG		= 0x0040,
 	/* The following options are CMOS-related */
 	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
@@ -350,26 +349,12 @@ struct lb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-/* Memory map windows to translate addresses between SPI flash space and host address space. */
-struct flash_mmap_window {
-	uint32_t flash_base;
-	uint32_t host_base;
-	uint32_t size;
-};
-
 struct lb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
 	uint32_t flash_size;
 	uint32_t sector_size;
 	uint32_t erase_cmd;
-	/*
-	 * Number of mmap windows used by the platform to decode addresses between SPI flash
-	 * space and host address space. This determines the number of entries in mmap_table.
-	 */
-
-	uint32_t mmap_count;
-	struct flash_mmap_window mmap_table[0];
 };
 
 struct lb_boot_media_params {
@@ -522,27 +507,4 @@ struct lb_smmstorev2 {
 	uint8_t unused[3];		/* Set to zero */
 };
 
-enum lb_tmp_ppi_tpm_version {
-	LB_TPM_VERSION_UNSPEC = 0,
-	LB_TPM_VERSION_TPM_VERSION_1_2,
-	LB_TPM_VERSION_TPM_VERSION_2,
-};
-
-/*
- * Handoff buffer for TPM Physical Presence Interface.
- * * ppi_address   Pointer to PPI buffer shared with ACPI
- *                 The layout of the buffer matches the QEMU virtual memory device
- *                 that is generated by QEMU.
- *                 See files 'hw/i386/acpi-build.c' and 'include/hw/acpi/tpm.h'
- *                 for details.
- * * tpm_version   TPM version: 1 for TPM1.2, 2 for TPM2.0
- * * ppi_version   BCD encoded version of TPM PPI interface
- */
-struct lb_tpm_physical_presence {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t ppi_address;	/* Address of ACPI PPI communication buffer */
-	uint8_t tpm_version;	/* 1: TPM1.2, 2: TPM2.0 */
-	uint8_t ppi_version;	/* BCD encoded */
-} __packed;
 #endif

src/commonlib/include/commonlib/region.h

@@ -6,7 +6,6 @@
 #include <sys/types.h>
 #include <stddef.h>
 #include <stdbool.h>
-#include <commonlib/bsd/helpers.h>
 #include <commonlib/mem_pool.h>
 
 /*
@@ -211,33 +210,14 @@ void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
 void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
 int mmap_helper_rdev_munmap(const struct region_device *, void *);
 
-/*
- * A translated region device provides the ability to publish a region device in one address
- * space and use an access mechanism within another address space. The sub region is the window
- * within the 1st address space and the request is modified prior to accessing the second
- * address space provided by access_dev.
- *
- * Each xlate_region_device can support multiple translation windows described using
- * xlate_window structure. The windows need not be contiguous in either address space. However,
- * this poses restrictions on the operations being performed i.e. callers cannot perform
- * operations across multiple windows of a translated region device. It is possible to support
- * readat/writeat/eraseat by translating them into multiple calls one to access device in each
- * window. However, mmap support is tricky because the caller expects that the memory mapped
- * region is contiguous in both address spaces. Thus, to keep the semantics consistent for all
- * region ops, xlate_region_device does not support any operations across the window
- * boundary.
- *
- * Note: The platform is expected to ensure that the fmap description does not place any
- * section (that will be operated using the translated region device) across multiple windows.
- */
-struct xlate_window {
+/* A translated region device provides the ability to publish a region device
+ * in one address space and use an access mechanism within another address
+ * space. The sub region is the window within the 1st address space and
+ * the request is modified prior to accessing the second address space
+ * provided by access_dev. */
+struct xlate_region_device {
 	const struct region_device *access_dev;
 	struct region sub_region;
-};
-
-struct xlate_region_device {
-	size_t window_count;
-	const struct xlate_window *window_arr;
 	struct region_device rdev;
 };
 
@@ -245,31 +225,38 @@ extern const struct region_device_ops xlate_rdev_ro_ops;
 
 extern const struct region_device_ops xlate_rdev_rw_ops;
 
-#define XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, ops_)		\
+#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_,	\
+		parent_sz_, ops_)					\
 	{								\
-		.window_count = ARRAY_SIZE(window_arr_),		\
-		.window_arr = window_arr_,				\
+		.access_dev = access_dev_,				\
+		.sub_region = {						\
+			.offset = (sub_offset_),			\
+			.size = (sub_size_),				\
+		},							\
 		.rdev = REGION_DEV_INIT((ops_), 0,  (parent_sz_)),	\
 	}
 
-#define XLATE_REGION_DEV_RO_INIT(window_arr_, parent_sz_)		\
-		XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_ro_ops)
+#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_,	\
+		parent_sz_)						\
+		XLATE_REGION_DEV_INIT(access_dev_, sub_offset_,		\
+			sub_size_, parent_sz_, &xlate_rdev_ro_ops),	\
 
-#define XLATE_REGION_DEV_RW_INIT(window_count_, window_arr_, parent_sz_) \
-		XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_rw_ops)
+#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_,	\
+		parent_sz_)						\
+		XLATE_REGION_DEV_INIT(access_dev_, sub_offset_,		\
+			sub_size_, parent_sz_, &xlate_rdev_rw_ops),	\
 
 /* Helper to dynamically initialize xlate region device. */
 void xlate_region_device_ro_init(struct xlate_region_device *xdev,
-			      size_t window_count, const struct xlate_window *window_arr,
+			      const struct region_device *access_dev,
+			      size_t sub_offset, size_t sub_size,
 			      size_t parent_size);
 
 void xlate_region_device_rw_init(struct xlate_region_device *xdev,
-			      size_t window_count, const struct xlate_window *window_arr,
+			      const struct region_device *access_dev,
+			      size_t sub_offset, size_t sub_size,
 			      size_t parent_size);
 
-void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev,
-			      size_t sub_region_offset, size_t sub_region_size);
-
 /* This type can be used for incoherent access where the read and write
  * operations are backed by separate drivers. An example is x86 systems
  * with memory mapped media for reading but use a spi flash driver for

src/commonlib/region.c

@@ -188,37 +188,33 @@ void region_device_init(struct region_device *rdev,
 
 static void xlate_region_device_init(struct xlate_region_device *xdev,
 			const struct region_device_ops *ops,
-			size_t window_count, const struct xlate_window *window_arr,
+			const struct region_device *access_dev,
+			size_t sub_offset, size_t sub_size,
 			size_t parent_size)
 {
 	memset(xdev, 0, sizeof(*xdev));
-	xdev->window_count = window_count;
-	xdev->window_arr = window_arr;
+	xdev->access_dev = access_dev;
+	xdev->sub_region.offset = sub_offset;
+	xdev->sub_region.size = sub_size;
 	region_device_init(&xdev->rdev, ops, 0, parent_size);
 }
 
 void xlate_region_device_ro_init(struct xlate_region_device *xdev,
-			      size_t window_count, const struct xlate_window *window_arr,
+			      const struct region_device *access_dev,
+			      size_t sub_offset, size_t sub_size,
 			      size_t parent_size)
 {
-	xlate_region_device_init(xdev, &xlate_rdev_ro_ops, window_count, window_arr,
-			parent_size);
+	xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev,
+			sub_offset, sub_size, parent_size);
 }
 
 void xlate_region_device_rw_init(struct xlate_region_device *xdev,
-			      size_t window_count, const struct xlate_window *window_arr,
+			      const struct region_device *access_dev,
+			      size_t sub_offset, size_t sub_size,
 			      size_t parent_size)
 {
-	xlate_region_device_init(xdev, &xlate_rdev_rw_ops, window_count, window_arr,
-			parent_size);
-}
-
-void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev,
-			      size_t sub_region_offset, size_t sub_region_size)
-{
-	window->access_dev = access_dev;
-	window->sub_region.offset = sub_region_offset;
-	window->sub_region.size = sub_region_size;
+	xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev,
+			sub_offset, sub_size, parent_size);
 }
 
 static void *mdev_mmap(const struct region_device *rd, size_t offset,
@@ -325,21 +321,6 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
 	return 0;
 }
 
-static const struct xlate_window *xlate_find_window(const struct xlate_region_device *xldev,
-						    const struct region *req)
-{
-	size_t i;
-	const struct xlate_window *xlwindow;
-
-	for (i = 0; i < xldev->window_count; i++) {
-		xlwindow = &xldev->window_arr[i];
-		if (region_is_subregion(&xlwindow->sub_region, req))
-			return xlwindow;
-	}
-
-	return NULL;
-}
-
 static void *xlate_mmap(const struct region_device *rd, size_t offset,
 			size_t size)
 {
@@ -348,29 +329,24 @@ static void *xlate_mmap(const struct region_device *rd, size_t offset,
 		.offset = offset,
 		.size = size,
 	};
-	const struct xlate_window *xlwindow;
 
 	xldev = container_of(rd, __typeof__(*xldev), rdev);
 
-	xlwindow = xlate_find_window(xldev, &req);
-	if (!xlwindow)
+	if (!region_is_subregion(&xldev->sub_region, &req))
 		return NULL;
 
-	offset -= region_offset(&xlwindow->sub_region);
+	offset -= region_offset(&xldev->sub_region);
 
-	return rdev_mmap(xlwindow->access_dev, offset, size);
+	return rdev_mmap(xldev->access_dev, offset, size);
 }
 
-static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused)
+static int xlate_munmap(const struct region_device *rd, void *mapping)
 {
-	/*
-	 * xlate_region_device does not keep track of the access device that was used to service
-	 * a mmap request. So, munmap does not do anything. If munmap functionality is required,
-	 * then xlate_region_device will have to be updated to accept some pre-allocated space
-	 * from caller to keep track of the mapping requests. Since xlate_region_device is only
-	 * used for memory mapped boot media on the backend right now, skipping munmap is fine.
-	 */
-	return 0;
+	const struct xlate_region_device *xldev;
+
+	xldev = container_of(rd, __typeof__(*xldev), rdev);
+
+	return rdev_munmap(xldev->access_dev, mapping);
 }
 
 static ssize_t xlate_readat(const struct region_device *rd, void *b,
@@ -380,18 +356,16 @@ static ssize_t xlate_readat(const struct region_device *rd, void *b,
 		.offset = offset,
 		.size = size,
 	};
-	const struct xlate_window *xlwindow;
 	const struct xlate_region_device *xldev;
 
 	xldev = container_of(rd, __typeof__(*xldev), rdev);
 
-	xlwindow = xlate_find_window(xldev, &req);
-	if (!xlwindow)
+	if (!region_is_subregion(&xldev->sub_region, &req))
 		return -1;
 
-	offset -= region_offset(&xlwindow->sub_region);
+	offset -= region_offset(&xldev->sub_region);
 
-	return rdev_readat(xlwindow->access_dev, b, offset, size);
+	return rdev_readat(xldev->access_dev, b, offset, size);
 }
 
 static ssize_t xlate_writeat(const struct region_device *rd, const void *b,
@@ -401,18 +375,16 @@ static ssize_t xlate_writeat(const struct region_device *rd, const void *b,
 		.offset = offset,
 		.size = size,
 	};
-	const struct xlate_window *xlwindow;
 	const struct xlate_region_device *xldev;
 
 	xldev = container_of(rd, __typeof__(*xldev), rdev);
 
-	xlwindow = xlate_find_window(xldev, &req);
-	if (!xlwindow)
+	if (!region_is_subregion(&xldev->sub_region, &req))
 		return -1;
 
-	offset -= region_offset(&xlwindow->sub_region);
+	offset -= region_offset(&xldev->sub_region);
 
-	return rdev_writeat(xlwindow->access_dev, b, offset, size);
+	return rdev_writeat(xldev->access_dev, b, offset, size);
 }
 
 static ssize_t xlate_eraseat(const struct region_device *rd,
@@ -422,18 +394,16 @@ static ssize_t xlate_eraseat(const struct region_device *rd,
 		.offset = offset,
 		.size = size,
 	};
-	const struct xlate_window *xlwindow;
 	const struct xlate_region_device *xldev;
 
 	xldev = container_of(rd, __typeof__(*xldev), rdev);
 
-	xlwindow = xlate_find_window(xldev, &req);
-	if (!xlwindow)
+	if (!region_is_subregion(&xldev->sub_region, &req))
 		return -1;
 
-	offset -= region_offset(&xlwindow->sub_region);
+	offset -= region_offset(&xldev->sub_region);
 
-	return rdev_eraseat(xlwindow->access_dev, offset, size);
+	return rdev_eraseat(xldev->access_dev, offset, size);
 }
 
 const struct region_device_ops xlate_rdev_ro_ops = {

src/console/printk.c

@@ -10,6 +10,7 @@
 #include <console/vtxprintf.h>
 #include <smp/spinlock.h>
 #include <smp/node.h>
+#include <trace.h>
 #include <timer.h>
 
 DECLARE_SPIN_LOCK(console_lock)
@@ -80,6 +81,7 @@ int do_vprintk(int msg_level, const char *fmt, va_list args)
 	if (log_this < CONSOLE_LOG_FAST)
 		return 0;
 
+	DISABLE_TRACE;
 	spin_lock(&console_lock);
 
 	console_time_run();
@@ -94,6 +96,7 @@ int do_vprintk(int msg_level, const char *fmt, va_list args)
 	console_time_stop();
 
 	spin_unlock(&console_lock);
+	ENABLE_TRACE;
 
 	return i;
 }

src/console/vsprintf.c

@@ -2,6 +2,7 @@
 
 #include <console/vtxprintf.h>
 #include <string.h>
+#include <trace.h>
 
 struct vsnprintf_context {
 	char *str_buf;
@@ -23,12 +24,16 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args)
 	int i;
 	struct vsnprintf_context ctx;
 
+	DISABLE_TRACE;
+
 	ctx.str_buf = buf;
 	ctx.buf_limit = size ? size - 1 : 0;
 	i = vtxprintf(str_tx_byte, fmt, args, &ctx);
 	if (size)
 		*ctx.str_buf = '\0';
 
+	ENABLE_TRACE;
+
 	return i;
 }
 

src/cpu/amd/agesa/Kconfig

@@ -14,6 +14,7 @@ config CPU_AMD_AGESA
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_AGESA
 

src/cpu/amd/pi/00730F01/update_microcode.c

@@ -115,7 +115,8 @@ void amd_update_microcode_from_cbfs(void)
 	size_t ucode_len;
 	uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();
 
-	ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len);
+	ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
+					CBFS_TYPE_MICROCODE, &ucode_len);
 	if (!ucode) {
 		printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
 		return;

src/cpu/amd/pi/Kconfig

@@ -13,6 +13,7 @@ config CPU_AMD_PI
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_PI
 

src/cpu/intel/car/core2/cache_as_ram.S

@@ -4,7 +4,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
-.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -7,7 +7,6 @@
 #define NoEvictMod_MSR 0x2e0
 #define BBL_CR_CTL3_MSR 0x11e
 
-.section .init
 .global bootblock_pre_c_entry
 
 #include <cpu/intel/car/cache_as_ram_symbols.inc>

src/cpu/intel/car/p3/cache_as_ram.S

@@ -4,7 +4,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 
-.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/car/p4-netburst/cache_as_ram.S

@@ -8,7 +8,6 @@
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 
-.section .init
 .global bootblock_pre_c_entry
 
 .code32

src/cpu/intel/fit/Makefile.inc

@@ -6,14 +6,16 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 
 ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
 
-$(call add_intermediate, add_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL))
+INTERMEDIATE+=add_mcu_fit
+add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
 	@printf "    UPDATE-FIT Microcode\n"
 	$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
 
 # Second FIT in TOP_SWAP bootblock
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 
-$(call add_intermediate, add_ts_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL))
+INTERMEDIATE+=add_ts_mcu_fit
+add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
 	@printf "    UPDATE-FIT Top Swap: Microcode\n"
 ifneq ($(FIT_ENTRY),)
 	$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT

src/cpu/intel/fit/fit.S

@@ -6,6 +6,7 @@
 fit_pointer:
 .long fit_table
 .long 0
+.previous
 
 .section .text
 .align 16
@@ -28,3 +29,4 @@ fit_table:
 .byte 0x7d
 .fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16
 fit_table_end:
+.previous

src/cpu/intel/fit/fit.ld

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+SECTIONS {
+	. = 0xffffffc0;
+	.fit_pointer (.): {
+		KEEP(*(.fit_pointer))
+	}
+}

src/cpu/intel/haswell/acpi.c

@@ -14,18 +14,6 @@
 
 #include <southbridge/intel/lynxpoint/pch.h>
 
-static int cstate_set_lp[3] = {
-	C_STATE_C1E,
-	C_STATE_C3,
-	C_STATE_C7S_LONG_LAT,
-};
-
-static int cstate_set_trad[3] = {
-	C_STATE_C1,
-	C_STATE_C3,
-	C_STATE_C6_LONG_LAT,
-};
-
 static int get_cores_per_package(void)
 {
 	struct cpuinfo_x86 c;
@@ -42,6 +30,41 @@ static int get_cores_per_package(void)
 	return cores;
 }
 
+static void generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return;
+
+	acpigen_write_package(cstate_count + 1);
+	acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0) {
+		cstates[c1].ctype = 1;
+		acpigen_write_CST_package_entry(&cstates[c1]);
+	}
+	if (c2 > 0) {
+		cstates[c2].ctype = 2;
+		acpigen_write_CST_package_entry(&cstates[c2]);
+	}
+	if (c3 > 0) {
+		cstates[c3].ctype = 3;
+		acpigen_write_CST_package_entry(&cstates[c3]);
+	}
+
+	acpigen_pop_len();
+}
+
 static acpi_tstate_t tss_table_fine[] = {
 	{ 100, 1000, 0, 0x00, 0 },
 	{ 94, 940, 0, 0x1f, 0 },
@@ -96,12 +119,18 @@ static void generate_T_state_entries(int core, int cores_per_package)
 
 static void generate_C_state_entries(void)
 {
-	acpi_cstate_t map[3];
-	int *set;
-	int i;
-
 	struct cpu_info *info;
 	struct cpu_driver *cpu;
+	struct device *lapic;
+	struct cpu_intel_haswell_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return;
+	conf = lapic->chip_info;
+	if (!conf)
+		return;
 
 	/* Find CPU map of supported C-states */
 	info = cpu_info();
@@ -111,18 +140,25 @@ static void generate_C_state_entries(void)
 	if (!cpu || !cpu->cstates)
 		return;
 
-	if (haswell_is_ult())
-		set = cstate_set_lp;
-	else
-		set = cstate_set_trad;
+	acpigen_emit_byte(0x14);		/* MethodOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("_CST");
+	acpigen_emit_byte(0x00);		/* No Arguments */
 
-	for (i = 0; i < ARRAY_SIZE(map); i++) {
-		map[i] = cpu->cstates[set[i]];
-		map[i].ctype = i + 1;
-	}
+	/* If running on AC power */
+	acpigen_emit_byte(0xa0);		/* IfOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("PWRS");
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_pop_len();
 
-	/* Generate C-state tables */
-	acpigen_write_CST_package(map, ARRAY_SIZE(map));
+	/* Else on battery power */
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_pop_len();
 }
 
 static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -173,7 +209,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 		/* Max Non-Turbo Ratio */
 		ratio_max = (msr.lo >> 8) & 0xff;
 	}
-	clock_max = ratio_max * CPU_BCLK;
+	clock_max = ratio_max * HASWELL_BCLK;
 
 	/* Calculate CPU TDP in mW */
 	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
@@ -237,7 +273,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 
 		/* Calculate power at this ratio */
 		power = calculate_power(power_max, ratio_max, ratio);
-		clock = ratio * CPU_BCLK;
+		clock = ratio * HASWELL_BCLK;
 
 		acpigen_write_PSS_package(
 			clock,			/*MHz*/

src/cpu/intel/haswell/bootblock.c

@@ -4,7 +4,6 @@
 #include <arch/bootblock.h>
 #include <cpu/x86/msr.h>
 #include <arch/io.h>
-#include <delay.h>
 #include <halt.h>
 
 #include "haswell.h"
@@ -51,10 +50,6 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	/* Set soft reset control to use register value */
 	RCBA32_OR(SOFT_RESET_CTRL, 1);
 
-	/* Delay before reset to avoid potential TPM lockout */
-	if (CONFIG(TPM1) || CONFIG(TPM2))
-		mdelay(30);
-
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, 0xcf9);
 	outb(0x6, 0xcf9);

src/cpu/intel/haswell/chip.h

@@ -3,35 +3,16 @@
 /* Magic value used to locate this chip in the device tree */
 #define SPEEDSTEP_APIC_MAGIC 0xACAC
 
-#include <stdbool.h>
-#include <stdint.h>
-
-struct cpu_vr_config {
-	/*
-	 * Minimum voltage for C6/C7 state:
-	 * 0x67 = 1.6V (full swing)
-	 *  ...
-	 * 0x79 = 1.7V
-	 *  ...
-	 * 0x83 = 1.8V (no swing)
-	 */
-	uint8_t cpu_min_vid;
-
-	/*
-	 * Set slow VR ramp rate on C-state exit:
-	 * 0 = Fast VR ramp rate / 2
-	 * 1 = Fast VR ramp rate / 4
-	 * 2 = Fast VR ramp rate / 8
-	 * 3 = Fast VR ramp rate / 16
-	 */
-	uint8_t slow_ramp_rate_set;
-
-	/* Enable slow VR ramp rate */
-	bool slow_ramp_rate_enable;
-};
-
 struct cpu_intel_haswell_config {
-	int tcc_offset;		/* TCC Activation Offset */
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
 
-	struct cpu_vr_config vr_config;
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+
+	int tcc_offset;		/* TCC Activation Offset */
 };

src/cpu/intel/haswell/haswell.h

@@ -18,32 +18,25 @@
 #define HASWELL_STEPPING_ULT_C0		1
 
 /* Haswell bus clock is fixed at 100MHz */
-#define CPU_BCLK			100
+#define HASWELL_BCLK			100
 
 #define MSR_CORE_THREAD_COUNT		0x35
-#define MSR_PLATFORM_INFO		0xce
-#define  PLATFORM_INFO_SET_TDP		(1 << 29)
-#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
-#define MSR_PMG_IO_CAPTURE_BASE		0xe4
 #define MSR_FEATURE_CONFIG		0x13c
-#define SMM_MCA_CAP_MSR			0x17d
-#define   SMM_CPU_SVRSTR_BIT		57
-#define   SMM_CPU_SVRSTR_MASK		(1 << (SMM_CPU_SVRSTR_BIT - 32))
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)
 #define  FLEX_RATIO_EN			(1 << 16)
 #define MSR_TEMPERATURE_TARGET		0x1a2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+
+#define MSR_PLATFORM_INFO		0xce
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PMG_IO_CAPTURE_BASE		0xe4
+
 #define MSR_MISC_PWR_MGMT		0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define MSR_TURBO_RATIO_LIMIT		0x1ad
-#define MSR_PRMRR_PHYS_BASE		0x1f4
-#define MSR_PRMRR_PHYS_MASK		0x1f5
 #define MSR_POWER_CTL			0x1fc
-#define MSR_LT_LOCK_MEMORY		0x2e7
-#define MSR_UNCORE_PRMRR_PHYS_BASE	0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
-#define SMM_FEATURE_CONTROL_MSR		0x4e0
-#define   SMM_CPU_SAVE_EN		(1 << 1)
 
 #define MSR_C_STATE_LATENCY_CONTROL_0	0x60a
 #define MSR_C_STATE_LATENCY_CONTROL_1	0x60b
@@ -60,7 +53,7 @@
 #define  IRTL_33554432_NS		(5 << 10)
 #define  IRTL_RESPONSE_MASK		(0x3ff)
 
-/* Long duration in low dword, short duration in high dword */
+/* long duration in low dword, short duration in high dword */
 #define MSR_PKG_POWER_LIMIT		0x610
 #define  PKG_POWER_LIMIT_MASK		0x7fff
 #define  PKG_POWER_LIMIT_EN		(1 << 15)
@@ -83,6 +76,18 @@
 #define MSR_CONFIG_TDP_CONTROL		0x64b
 #define MSR_TURBO_ACTIVATION_RATIO	0x64c
 
+#define SMM_MCA_CAP_MSR			0x17d
+#define   SMM_CPU_SVRSTR_BIT		57
+#define   SMM_CPU_SVRSTR_MASK		(1 << (SMM_CPU_SVRSTR_BIT - 32))
+
+#define MSR_PRMRR_PHYS_BASE		0x1f4
+#define MSR_PRMRR_PHYS_MASK		0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE	0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK	0x2f5
+
+#define SMM_FEATURE_CONTROL_MSR		0x4e0
+#define   SMM_CPU_SAVE_EN		(1 << 1)
+
 /* SMM save state MSRs */
 #define SMBASE_MSR			0xc20
 #define IEDBASE_MSR			0xc22
@@ -91,26 +96,33 @@
 #define SMRR_SUPPORTED			(1 << 11)
 #define PRMRR_SUPPORTED			(1 << 12)
 
-/* Intel suggested latency times in units of 1024ns. */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
-
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
-	(((1 << ((base) * 5)) * (limit)) / 1000)
-#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
-	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
-				      (IRTL_1024_NS >> 10))
-
 /* P-state configuration */
 #define PSS_MAX_ENTRIES			8
 #define PSS_RATIO_STEP			2
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
 /* Sanity check config options. */
 #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
 # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
@@ -125,27 +137,6 @@
 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
 #endif
 
-/*
- * List of supported C-states for Haswell and Broadwell.
- * Only the ULT parts support C8, C9, and C10.
- */
-enum {
-	C_STATE_C0		=  0,
-	C_STATE_C1		=  1,
-	C_STATE_C1E		=  2,
-	C_STATE_C3		=  3,
-	C_STATE_C6_SHORT_LAT	=  4,
-	C_STATE_C6_LONG_LAT	=  5,
-	C_STATE_C7_SHORT_LAT	=  6,
-	C_STATE_C7_LONG_LAT	=  7,
-	C_STATE_C7S_SHORT_LAT	=  8,
-	C_STATE_C7S_LONG_LAT	=  9,
-	C_STATE_C8		= 10,
-	C_STATE_C9		= 11,
-	C_STATE_C10		= 12,
-	NUM_C_STATES,
-};
-
 /* Lock MSRs */
 void intel_cpu_haswell_finalize_smm(void);
 
@@ -154,9 +145,8 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 
 /* CPU identification */
-static inline int haswell_is_ult(void)
-{
-	return CONFIG(INTEL_LYNXPOINT_LP);
-}
+int haswell_family_model(void);
+int haswell_stepping(void);
+int haswell_is_ult(void);
 
 #endif

src/cpu/intel/haswell/haswell_init.c

@@ -20,6 +20,41 @@
 #include "haswell.h"
 #include "chip.h"
 
+/* Intel suggested latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
+	(((1 << ((base)*5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
+	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
+				      (IRTL_1024_NS >> 10))
+
+/*
+ * List of supported C-states in this processor. Only the ULT parts support C8,
+ * C9, and C10.
+ */
+enum {
+	C_STATE_C0,             /* 0 */
+	C_STATE_C1,             /* 1 */
+	C_STATE_C1E,            /* 2 */
+	C_STATE_C3,             /* 3 */
+	C_STATE_C6_SHORT_LAT,   /* 4 */
+	C_STATE_C6_LONG_LAT,    /* 5 */
+	C_STATE_C7_SHORT_LAT,   /* 6 */
+	C_STATE_C7_LONG_LAT,    /* 7 */
+	C_STATE_C7S_SHORT_LAT,  /* 8 */
+	C_STATE_C7S_LONG_LAT,   /* 9 */
+	C_STATE_C8,             /* 10 */
+	C_STATE_C9,             /* 11 */
+	C_STATE_C10,            /* 12 */
+	NUM_C_STATES
+};
+
 #define MWAIT_RES(state, sub_state)                         \
 	{                                                   \
 		.addrl = (((state) << 4) | (sub_state)),    \
@@ -151,6 +186,27 @@ static const u8 power_limit_time_msr_to_sec[] = {
 	[0x11] = 128,
 };
 
+int haswell_family_model(void)
+{
+	return cpuid_eax(1) & 0x0fff0ff0;
+}
+
+int haswell_stepping(void)
+{
+	return cpuid_eax(1) & 0xf;
+}
+
+/* Dynamically determine if the part is ULT. */
+int haswell_is_ult(void)
+{
+	static int ult = -1;
+
+	if (ult < 0)
+		ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT);
+
+	return ult;
+}
+
 /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate
  * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly
  * when a core is woken up. */
@@ -228,17 +284,8 @@ static u32 pcode_mailbox_read(u32 command)
 
 static void initialize_vr_config(void)
 {
-	struct cpu_vr_config vr_config = { 0 };
 	msr_t msr;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-
-	if (lapic && lapic->chip_info) {
-		const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
-		vr_config = conf->vr_config;
-	}
-
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
 
 	/*  Configure VR_CURRENT_CONFIG. */
@@ -248,7 +295,7 @@ static void initialize_vr_config(void)
 	msr.hi &= 0xc0000000;
 	msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A. */
 	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A. */
-	msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */
+	msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
 
 	if (haswell_is_ult())
 		msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
@@ -268,35 +315,24 @@ static void initialize_vr_config(void)
 	msr.hi &= ~(1 << (51 - 32));
 	/* Enable decay mode on C-state entry. */
 	msr.hi |= (1 << (52 - 32));
-	/* Set the slow ramp rate */
 	if (haswell_is_ult()) {
+		/* Set the slow ramp rate to be fast ramp rate / 4 */
 		msr.hi &= ~(0x3 << (53 - 32));
-		/* Configure the C-state exit ramp rate. */
-		if (vr_config.slow_ramp_rate_enable) {
-			/* Configured slow ramp rate. */
-			msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32));
-			/* Set exit ramp rate to slow. */
-			msr.hi &= ~(1 << (50 - 32));
-		} else {
-			/* Fast ramp rate / 4. */
-			msr.hi |= (1 << (53 - 32));
-		}
+		msr.hi |= (0x01 << (53 - 32));
 	}
 	/* Set MIN_VID (31:24) to allow CPU to have full control. */
 	msr.lo &= ~0xff000000;
-	msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24;
 	wrmsr(MSR_VR_MISC_CONFIG, msr);
 
 	/*  Configure VR_MISC_CONFIG2 MSR. */
-	if (!haswell_is_ult())
-		return;
-
+	if (haswell_is_ult()) {
 		msr = rdmsr(MSR_VR_MISC_CONFIG2);
 		msr.lo &= ~0xffff;
 		/* Allow CPU to control minimum voltage completely (15:8) and
 		 * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
 		msr.lo |= 0x006f;
 		wrmsr(MSR_VR_MISC_CONFIG2, msr);
+	}
 }
 
 static void configure_pch_power_sharing(void)
@@ -367,7 +403,8 @@ void set_power_limits(u8 power_limit_1_time)
 	u8 power_limit_1_val;
 
 	if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
-		power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
+		power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr)
+		- 1;
 
 	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 		return;
@@ -444,6 +481,12 @@ static void configure_c_states(void)
 	/* The deepest package c-state defaults to factory-configured value. */
 	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
+	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0xffff;
+	msr.lo |= (get_pmbase() + 0x14);	// LVL_2 base address
+	/* The deepest package c-state defaults to factory-configured value. */
+	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
 	msr = rdmsr(MSR_MISC_PWR_MGMT);
 	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
 	wrmsr(MSR_MISC_PWR_MGMT, msr);
@@ -469,24 +512,26 @@ static void configure_c_states(void)
 	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 
-	/* Only Haswell ULT supports the 3-5 latency response registers */
-	if (!haswell_is_ult())
-		return;
-
+	/* Haswell ULT only supoprts the 3-5 latency response registers.*/
+	if (haswell_is_ult()) {
 		/* C-state Interrupt Response Latency Control 3 - package C8 */
 		msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
+		msr.lo = IRTL_VALID | IRTL_1024_NS |
+			 C_STATE_LATENCY_CONTROL_3_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 
 		/* C-state Interrupt Response Latency Control 4 - package C9 */
 		msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
+		msr.lo = IRTL_VALID | IRTL_1024_NS |
+			 C_STATE_LATENCY_CONTROL_4_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 
 		/* C-state Interrupt Response Latency Control 5 - package C10 */
 		msr.hi = 0;
-	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
+		msr.lo = IRTL_VALID | IRTL_1024_NS |
+			 C_STATE_LATENCY_CONTROL_5_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+	}
 }
 
 static void configure_thermal_target(void)
@@ -539,10 +584,7 @@ static void set_max_ratio(void)
 	perf_ctl.hi = 0;
 
 	/* Check for configurable TDP option */
-	if (get_turbo_state() == TURBO_ENABLED) {
-		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
-		perf_ctl.lo = (msr.lo & 0xff) << 8;
-	} else if (cpu_config_tdp_levels()) {
+	if (cpu_config_tdp_levels()) {
 		/* Set to nominal TDP ratio */
 		msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
 		perf_ctl.lo = (msr.lo & 0xff) << 8;
@@ -554,7 +596,7 @@ static void set_max_ratio(void)
 	wrmsr(IA32_PERF_CTL, perf_ctl);
 
 	printk(BIOS_DEBUG, "CPU: frequency set to %d\n",
-	       ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+	       ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK);
 }
 
 static void configure_mca(void)
@@ -574,7 +616,7 @@ static void configure_mca(void)
 }
 
 /* All CPUs including BSP will run the following function. */
-static void cpu_core_init(struct device *cpu)
+static void haswell_init(struct device *cpu)
 {
 	/* Clear out pending MCEs */
 	configure_mca();
@@ -601,6 +643,9 @@ static void cpu_core_init(struct device *cpu)
 	/* Set energy policy */
 	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 
+	/* Set Max Ratio */
+	set_max_ratio();
+
 	/* Enable Turbo */
 	enable_turbo();
 }
@@ -616,11 +661,10 @@ static void pre_mp_init(void)
 
 	initialize_vr_config();
 
-	if (!haswell_is_ult())
-		return;
-
+	if (haswell_is_ult()) {
 		calibrate_24mhz_bclk();
 		configure_pch_power_sharing();
+	}
 }
 
 static int get_cpu_count(void)
@@ -656,9 +700,6 @@ static void per_cpu_smm_trigger(void)
 
 static void post_mp_init(void)
 {
-	/* Set Max Ratio */
-	set_max_ratio();
-
 	/* Now that all APs have been relocated as well as the BSP let SMIs
 	 * start flowing. */
 	global_smi_enable();
@@ -685,7 +726,7 @@ void mp_init_cpus(struct bus *cpu_bus)
 }
 
 static struct device_operations cpu_dev_ops = {
-	.init = cpu_core_init,
+	.init     = haswell_init,
 };
 
 static const struct cpu_device_id cpu_table[] = {

src/cpu/intel/microcode/microcode.c

@@ -126,7 +126,9 @@ const void *intel_microcode_find(void)
 	unsigned int x86_model, x86_family;
 	msr_t msr;
 
-	ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len);
+	ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE,
+						CBFS_TYPE_MICROCODE,
+						&microcode_len);
 	if (ucode_updates == NULL)
 		return NULL;
 

src/cpu/intel/microcode/microcode_asm.S

@@ -44,7 +44,7 @@
  */
 
 .code32
-.section .init
+.section .text
 .global update_bsp_microcode
 
 update_bsp_microcode:

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -264,6 +264,9 @@ static void model_1067x_init(struct device *cpu)
 	/* Test for TM2 only if EIST is available. */
 	const char tm2 = eist && (cpuid1.ecx & (1 << 8));
 
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
 	/* Print processor name */
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);

src/cpu/intel/model_1067x/mp_init.c

@@ -33,7 +33,7 @@ static int get_cpu_count(void)
 static void get_microcode_info(const void **microcode, int *parallel)
 {
 	*microcode = microcode_patch;
-	*parallel = !intel_ht_supported();
+	*parallel = 1;
 }
 
 /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL