Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Required in SSDB for Windows drivers. Tested on google/brya (kano)
and verified Intel Webcam shows up to Windows as a camera source
Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82068
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's nothing in this header file that needs to be updated for the
Phoenix SoC, so remove the 'Update for Phoenix' TODO.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82150
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When in Package C3 or deeper the PSI settings are used to switch the
CPU VR into a low power state. It was found that the voltage regulator
on the Sandy-Bridge series has non-default PSI settings, compared to
Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3
as the vendor BIOS does to fix a hang when the package is idle.
Since neither the vendor BIOS is open-source, nor datasheet exists for
the used VR it's unclear why those PSI values must be used and how
they influence the regulator.
The X220 already has the correct PSI values configured and is now stable
for more than 24h in Package C7 state.
TEST: Not tested on the affected boards, only checked vendor firmware.
Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current fast_spi code uses memcpy for rw. The SPI flash read/write
has 4 byte limit, due to which the current 64 bit memcpy doesn't work.
Hence update rw ops to use read32p/write32p.
BUG=b:242829490
TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms
and RPL(brox/skolas) 32-bit platforms.
Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
U-Boot v2024.04 was released on Tue 02 April 2024
Change-Id: I21fe81e9e01f2f21f9a4581fa8fdbf661fe270bd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82007
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CONFIG_LP_MULTIBOOT is enabled, save the values of EAX and EBX
passed from the bootloader. This information can be useful for
multiboot payloads feature alone.
Change-Id: I98c2cd00206ee48eb0fc67edd9533032bcf3e5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This
is from Intel's guidance for MRC to map the memory speed to proper POR
number.
BUG=b:332980211
BRANCH=brya
TEST=Built and compare the results of command 'dmidecode -t 17'
[Before]
(Same values in all of memory device handle)
Speed: 6400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
(Same values in all of memory device handle)
Speed: 5200 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem
buffer is released after FSP-S init is complete. In certain platforms,
the logo file is displayed during PCI enumeration. This means the logo
buffer is used after it is released. Fix this issue by releasing the
logo buffer when the coreboot has finished loading payload. During S3
scenario CBMEM is locked, bmp logo is not loaded and hence the release
is a no-op.
BUG=b:337144954
TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS
boot logo is seen without any corruption.
Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Boot device is stubbed to be able to build boards without errors.
Change-Id: Ie74b1e34f9aebe151d0fdb0e95c003510fd864c3
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Integrated Boot Logic (IBL) codes doesn't support bootloader
controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden.
Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF)
by bootloader is not supported, because when P2SB is hidden the
register access is denied.
TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB
Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch sets different names for different mtlrvp
variants so they can be matched properly at runtime against
unique frids (i.e. firmware read-only identifiers).
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on intel/mtlrvp
Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Clean up by using is_devfn_enabled().
Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up by using is_devfn_enabled().
Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In NUMA architecture, all devices (cpu, memory and PCI device)
belong to specific proximity domain. Add utils to map device
instance to their proximity domain.
Proximity domain ID is the index assigned at the creation of
proximity domains. There is no hard relationship between proximity
domain ID and the device identities (e.g. socket ID). Hence we
need the map utils to explicitly link them.
For now the Sub-NUMA config isn't taken into account.
TEST=Build and boot on intel/archercity CRB
Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One URL in this document did not show up as a link. Fix it.
Change-Id: I22bf2014e71e6a127a7981cc90a028e48c25da49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82160
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.
Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80323
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.
BUG=b:329034258
TEST=Verified both x86_32 and x86_64 builds on Meteor Lake board (Rex)
Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81663
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Same fsp_header struture is being used for x64 and x32 modes
and hence dropping the x64 assertion.
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81662
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned
in x86_64 mode.This is already setup properly with the default
value of the `mpreferred-stack-boundary' compiler option (4).
2. The FSP heap buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned. This alignment is consistent for
both x86_64 and x86_32 modes to simplify the implementation.
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest/firmware_DevMode.
BUG=b:337365524
TEST=built and run autotest firmware_DevMode
Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
GPP_D14 is floating when ISH is not being used and wasting power. Add
pulldown to prevent this from happening.
BUG=b:336654954
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
make sure OS boots up
HW team validated that power usage is 20 mW lower
Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.
However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.
Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.
Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DVI connector on this board is DVI-D (digital only), not DVI-I.
Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup
using Trackpad.
246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3
247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3
248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67
249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3
250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3
251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67
Also suspend to S0ix and wakeup using Trackpad.
Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Found in a Clevo V560TU with Intel Core Ultra 155H
Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The Fn key on Xol emits a scancode of 94 (0x5e).
BUG=b:327656989
TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix ++ as suffix and * precedence. After modification, the gpio index
can be obtained correctly.
The error was introduced in the commit making it public:
commit 01344bce
BUG=None
TEST= Can get the correct index test on nissa.
Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When installing the packages, apt-get returns an error about holding
broken packages. It occurs the diffutils depends on libcurl4t64
which breaks the libcurl4.
As a solution, remove the libcurl4 from the list, and let the package
manager resolve the dependencies.
TEST=Build coreboot-sdk
Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This is a minimal framework that allows the build to compile.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
If the TPM is not detected in the system it may mean it is inactive
due to enabled ME with active PTT. In such case, the chipset will route
the TPM traffic to PTT CRB TPM on Intel systems.
If TPM is not probed, disable the PC80 TPM device driver, so that
coreboot will not generate improper SSDT ACPI table.
Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
If CRB TPM is not detected in the system it may mean it is inactive
due to disabled or neutered ME. In such case, the chipset will route
the TPM traffic to LPC/SPI on Intel systems.
If CRB TPM is not probed, disable the CRB TPM device driver, so that
coreboot will not generate improper SMBIOS/SSDT ACPI tables.
Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
