This removes the boilerplate --oformat out of the makefile.mk
Change-Id: Ib78934fff4a31c4375da2038efca5027b813b07b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83999
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add the condition of unprovisioned fw_config to enable all storages
and devices. It's for first boot on all storags and preliminary test
in factory when fw_config is unprovisioned.
BUG=None
TEST=Build jubilant firmware and boot to OS on storages when fw_config
is unprovisioned and ensure all devices are enable.
Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When fw_config is unprovisioned (eg. in the factory), devices that do
not have any probe list are enabled by default and those that have probe
list are disabled. On mainboards that support multiple types of boot
critical devices (eg. storage) through probing fw_config, all of
them are disabled when fw_config is unprovisioned. Hence the devices do
not boot to OS. Add sconfig fw_config rule `probe unprovisioned` to
enable such devices when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I178f821e077912776d654971924d67203a7c43df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83983
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Since the voltage value measured by the USB2 pin of the wlan is 500mv,
it does not meet the design requirements. Adjusting the port length
can reduce the voltage to 450mv, which meets the expected settings.
BUG=b:361037189
TEST=1. The voltage measurements are as expected.
2. The Bluetooth and WiFi functions of the wlan module are
verified to be normal.
Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Enables early serial console for debugging.
TEST=build/boot drobit, verify console output available starting in
bootblock on CPU UART (/dev/ttyUSB1) vs ramstage.
Change-Id: If94eb8caca3469143433fef06b972050f886be6a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These field defines are SOC-specific. The AUX bias virtual wire field
positons are shifted in PTL.
In MTL SOC and older:
7:0 GROUP_ID Group ID in PCH GPIO
10:8 BIT_NUM Data bit Position in PCH GPIO
23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC:
15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 BIT_NUM Data bit Position in PCH GPIO
31:24 VW_INDEX VW Index in PCH GPIO
BUG=361048817
TEST=boot to OS and use iotools to read AUX Bias Ctrl register to
verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83980
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This mainboard does not have AT24RF08C (Asset Identification EEPROM) and
will show "*INVALID*" in the SMBIOS table.
Change-Id: If6f948bc4c63c7afdc8b31e1945d3c3beb99883f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Enable Intel CrashLog diagnostic feature by default on all Google
Dedede variants.
BUG=b:354834461
TEST=Built for Google Dedede and verifed that CrashLog is enabled by
default.
Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Extend support for CrashLog to Intel Jasperlake based platforms.
This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.
BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.
Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
This patch extends the eSOL implementation on Alder Lake to render text
messages during late CSE sync (from ramstage).
Currently, the eSOL is limited to the early boot phase (until romstage)
and only displays FSP-M memory training warnings or messages during
early CSE sync (at romstage).
Platforms like Nissa/Nirul and Trulo, which use CSE sync from ramstage,
cannot display any eSOL messages, resulting in a brief black screen
during CSE firmware updates.
This patch implements the following logic to scale eSOL for late CSE
sync (at ramstage) without recompiling eSOL code for ramstage:
1. During boot, check if the MRC cache is available. This indicates the
need for memory/DRAM training and triggers an eSOL message.
2. For CSE lite SKUs (applicable to CrOS), leverage the
`is_cse_fw_update_required` API to check if the current CSE RW
firmware version differs from the CBFS metadata file version.
If so, trigger an eSOL message indicating a CSE sync is required.
3. If either condition #1 and/or #2 is true, the AP firmware renders
an eSOL text message using LibGfxInit for the Alder Lake platform.
BUG=b:359814797
TEST=eSOL text messages are displayed during CSE sync and FSP updates.
tirwen-rev3 ~ # elogtool list
0 | ... | Log area cleared | 4088
1 | ... | Early Sign of Life | MRC Early SOL Screen Shown
1 | ... | Early Sign of Life | CSE Sync Early SOL Screen Shown
2 | ... | System boot | 197
3 | ... | Memory Cache Update | Normal | Success
4 | ... | System boot | 198
5 | ... | Firmware Splash Screen | Enabled
Change-Id: I1c7d4475ed5cf6888df1beebab0641ee4203b497
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83975
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch prevents the eSOL screen from being wiped out on Alder Lake
platforms that use late CSE sync (from ramstage). This allows the eSOL
text message to remain visible until ramstage.
Currently, the eSOL only functions during the early boot phase (until
romstage), so platforms like Nissa/Nirul and Trulo, which use CSE sync
from ramstage, cannot display any eSOL messages to the user.
A future patch will ensure the eSOL remains relevant for CSE sync in
ramstage, but this patch is necessary to avoid tearing down the IGD text
mode when exiting romstage.
BUG=b:359814797
TEST=eSOL text mode is not torn down when exiting romstage.
Change-Id: I81548b4057ab95ce3da0dbc69703977baf0581f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
MyST Parser automatically generates label "slugs" for headers which
should be used to reference them from links [1]. These labels are in
"slug-case", i.e. the original header text in lower case separated by
dashes, with punctuation removed. This fixes a few "cross-reference
target not found" warnings.
[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-slug-structure
Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds pmc_ipc to bootblock if SOC_INTEL_COMMON_BLOCK_PMC is enabled.
The good place to report SoC QDF can be report_cpu_info in bootblock.
QDF read is done by PMC IPC Command, so this adds pmc_ipc to bootblock
to enable calling pmc_dump_soc_qdf_info.
Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Kinox has two VBT options, selected via fw_config. Add the second
option to CBFS, and update the original file.
Extracted from Google_Kinox.14505.704.0.bin.
TEST=build/boot kinix, verify firmware display init successful and
payload menu visible. Verify correct VBT selected via cbmem log.
Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As
a result, when the `div' instruction is called to compute the needed
number of ways, there could be a remainder. When there is, one extra
way should be added to cover `CONFIG_DCACHE_RAM_SIZE'.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 16ab9bdcd578612bb3822373547f939eb90afd82 ("soc/intel/common:
Calculate and configure SF Mask 2") breaks the computation of the
number of ways and as result, all the derived masks. It results in MSR
such as `IA32_L3_MASK_1' to be improperly programmed yielding
unpredictable NEM issues such as hangs.
Indeed, this commit has introduced a backup of 0x1 into %edx before
comparing the requested cache-as-RAM size against the way size. When
the requested cache-as-RAM is larger, it reaches the second part of
the algorithm which computes the necessary number of ways to fit the
requested cache-as-RAM.
This algorithm uses the `div' instruction. Per specification, the div
instruction divides the 64 bits combination of %edx and %eax register.
Since 0x1 got backed up in %edx and assuming a
`CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000
by the way size instead of 0x200000 which result in a necessary number
of ways of 4098 for a way size of 0x100000.
This commit clears the %edx register before calling the `div'
instruction.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83948
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel's PMC CrashLog size in legacy mode is expressed in DWORDs and
therefore needs to be explicitly recalculated to bytes.
BUG=None
TEST=Built and checked the size in logs
Change-Id: I2678d537439c24fbd10aa3ceffee63c9a849d28b
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify brox DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify rex DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I3fdc02a82d197fd2b075e0a66c578149cef3a69f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, nissa, or brya DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch replaces the SoC-specific config option
`SOC_INTEL_PANTHERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
TEST=Able to build and boot google/fatcat without any functional impact
while debugging.
Change-Id: I36bbe14d02654ed9dbda21df0d9a6a6769b87754
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch replaces the SoC-specific config option
`SOC_INTEL_METEORLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/rex0 without any functional impact
while debugging.
Change-Id: I657d20a38e15eee333a4e45c0c600736148173d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83961
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch replaces the SoC-specific config option
`SOC_INTEL_ALDERLAKE_DEBUG_CONSENT` with the generic
`SOC_INTEL_COMMON_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/redrix without any functional impact
while debugging.
Change-Id: I9a9c81b72d707f5ed2e1a53c139ee22be0e30068
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch drops the SoC-specific config option
`SOC_INTEL_TIGERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/volteer without any functional
impact while debugging.
Change-Id: I3e96b20e7e8b3ce3c2e4884abd315a5cc55fe71d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch drops the SoC-specific config option
`SOC_INTEL_JASPERLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/dedede without any functional
impact while debugging.
Change-Id: I3e7abaf5fb3a0d5528041af5ce767a15fc738870
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83960
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch drops the SoC-specific config option
`SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot intel/elkhartlake_crb without any
functional impact while debugging.
Change-Id: Idb8db7230c432792e742218d41d891c529b2114f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83959
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch drops the SoC-specific config option
`SOC_INTEL_CANNONLAKE_DEBUG_CONSENT`.
Additionally, updates the FSP configuration to use the new generic
config option.
TEST=Able to build and boot google/hatch without any functional impact
while debugging.
Change-Id: Ifad11652b5fa6ff14f713f55a721cdbbfbfde471
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83958
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With commit 26b1a5f62b ("mb/acer/g43t-am3: Rework mainboard for variant
mechanism"), the files related to the G43T-AM3 mainboard were supposed
to be moved into its own variant directory. However, it seems it was
forgotten to delete the old ones and thus remove the duplicates.
Change-Id: I450fab074621d21e80216e4667eaf2510b0e14ad
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83985
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The USB IDs of the EHCI rate matching hubs found in these chipsets were
missing, preventing the utility from detecting connected USB devices.
Change-Id: I52858e2c75e8a3e1424a13bcddc2f5ec1216164b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This board now uses merlin so it can be removed.
Change-Id: I6036695ccf80b0a7d6e6463d26e5b32aa6cb9d57
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the ITE mirror functionality; all devices will mirror
automatically when they exit G3, and this is good enough.
Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This properly supports power_on_after_fail setting on affected
mainboards.
Tested on GA-H61M-S2PV
Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15dfd5ed0541352930c3b70252b3e536ad1e6efd
Signed-off-by: Michael Strosche <michael.strosche@gmail.com>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously RAM probing was necessary for our QEMU-RISCV target in order
to find the available amount of memory.
Now we get the memory from the devicetree propagated by QEMU, so there
is no reason to keep it anymore.
Tested:
Start QEMU-RISCV and cause an exception to make sure the trap handler
still works.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a generic config option, SOC_INTEL_COMMON_DEBUG_CONSENT,
to control the debug interface on Intel SoCs. This eliminates the need
for SoC-specific config options like SOC_INTEL_<SOC_NAME>_DEBUG_CONSENT.
Default values are provided for various debug types:
- 0: Disabled
- 1: Enabled (DCI OOB + [DbC])
- 2: Enabled (DCI OOB)
- 3: Enabled (USB3 DbC)
- 4: Enabled (XDP/MIPI60)
- 5: Enabled (USB2 DbC)
- 6: Enabled (2-wire DCI OOB)
- 7: Manual
Specific SoCs can override the SOC_INTEL_COMMON_DEBUG_CONSENT value
using SoC config override methods.
TEST=Able to build google/rex.
Change-Id: I84ad03f0ffe5da4bc53c665489c430fe9b65ede7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch selects the SOC_INTEL_COMMON_BASECODE option for Elkhart
Lake so that future patches can incorporate the common code debug
feature with it.
TEST=Able to build the EHL platform.
Change-Id: I71d95352fe627a7f1912f802aa971ad1ebbbead7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adjust settings as recommended by thermal team.
Set tcc_offset value to 12 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I0ae97bb0b2dbb2fe8f35221522506ec1f7da47f6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83971
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds SoundWire driver to support ALC722 audio codec.
The existing ALC711 codec driver is refactored to include support for
ALC722 device based on config flag.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
For example this device is connected to master link ID 0 and has strap
settings configuring it for unique ID 1:
chip drivers/soundwire/alc711
register "desc" = ""Headset Codec""
device generic 0.1 on end
end
reference datasheet: Realtek ALC722-CG ver. 0.56
TEST=This driver was tested on Intel RVP with on board ALC722 codec
by booting and disassembling the runtime SSDT to ensure that the
devices have the expected address and properties. Test soundcard
binding works and devices are detected and check for audio playback
using speaker output.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This adds some error handling to the code that adds the input segments
(e.g. kernel, cmdline, initrd...) to the output file.
Currently the compress function can fail and coreboot will still
build "successfully" leaving whoever build coreboot puzzled.
Change-Id: Ie36ad469c73cb3ff9360acc9bbe66c245e8b4a1e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83617
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commonlib/region.h requires SIZE_MAX to be defined.
Change-Id: I588d59c2637b10def046ea02293e5503c9b6bc3d
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83907
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The reference in Doc/mb/index.md was to starlabs/lite_adl.md, whereas
the file was actually named starlite_adl.md. Rename the file to fix the
broken reference and match the naming scheme of the markdown files for
the other StarLite systems.
Change-Id: I1922940fd18cc806d9647cbe05ad11b2a70e0d08
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83977
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
