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Author SHA1 Message Date
Jeremy Soller
f3ba5937e7 Change system76_ec timeout to 10 ms 
Change-Id: Ic3d01892df83c09d8323433585e1d8fe507f8c3a
 2020-07-02 09:39:46 -06:00
Jeremy Soller
5a9fddc3de gaze15 does not support SaOcSupport 2020-07-01 15:23:52 -06:00
Jeremy Soller
46dacbd7c3 Sync addw2 and gaze15 with oryp6 2020-07-01 12:44:59 -06:00
Jeremy Soller
9ba7399ee9 oryp6: allow memory clocks higher than 2933 MHz 
Change-Id: I6ea0e402f5ec0c89fa97cdd50615209551ad839f
 2020-06-30 15:28:06 -06:00
Jeremy Soller
4459b6355f oryp6: set reset config of TBT GPIO pins to RSMRST, and configure them early 2020-06-29 14:15:38 -06:00
Jeremy Soller
04c88e9113 oryp6: Set M.2 and LAN power and reset lines to reset with RSMRST to avoid glitching during reboots 2020-06-29 10:12:23 -06:00
Jeremy Soller
87a74eb767 oryp6: set subsystem IDs 
Change-Id: I659ae6da3c5ff61c22a10ed112b82984cb3168d7
 2020-06-26 14:25:57 -07:00
Jeremy Soller
264f4cd55b oryp6: Enable DMIC microphone on ALC1220 2020-06-26 10:35:03 -07:00
Jeremy Soller
8e7ffe4952 Refactor DGPU implementation, fix hybrid suspend 
Change-Id: Ia7873a016e003532346170a3d27469bf085a47c4
 2020-06-26 10:35:03 -07:00
Jeremy Soller
3b8e9fa539 oryp6: Disable PCH DMIC, remove verbs for other codecs 
Change-Id: Ib22dca12568ec768a0b10883c38dfb0fcf4e4499
 2020-06-26 10:35:03 -07:00
Jeremy Soller
b294e590d9 oryp6: Add GPIO_LANRTD3 to early_gpio_table 2020-06-25 11:02:57 -06:00
Jeremy Soller
6e2c6eb6b5 oryp6: Add GPIO descriptions 
Change-Id: I668d72e655ceb12d7f15ffff51b86780628b4bbf
 2020-06-25 10:27:23 -06:00
Jeremy Soller
f1e696b4a5 Add smart amp init 
Change-Id: I55749428284387629ba760fc713d0bfb62e8f8ab
 2020-06-23 14:10:53 -06:00
Jeremy Soller
11aca6bb7c Add stub for tas5825m driver and add it to oryp6 model 2020-06-19 09:39:18 -06:00
Jeremy Soller
90a93a8a32 Update cml-h pl2 to 90W 
Change-Id: Ibc1c142c4191334308eb02c5dee65d38c51b34e8
 2020-06-17 11:52:14 -06:00
Jeremy Soller
e0de23478e Sync addw2 and gaze15 with oryp6 
Change-Id: Ifb117d95d98c42a8ed0004e66b822df947e610ba
 2020-06-17 11:29:11 -06:00
Jeremy Soller
b0a89bfc26 Disable GPU power if GC6 is not enterred 2020-06-16 09:21:47 -06:00
Jeremy Soller
c9ec63b78b oryp6 GC6 support 
Change-Id: Ic2be6aecf1c4ab1fbba6b20d1d2a11e4b69df07f
 2020-06-11 22:04:16 -06:00
Jeremy Soller
0484c85cb3 Disable s0ix 
Change-Id: I8c3249a6c5f652a0a032835e55a2045b95758aa5
 2020-06-11 12:55:57 -06:00
Jeremy Soller
8a580cb7a7 Add ACPI backlight code 
Change-Id: I325fb544e2f2fa06606fd02138b95b236782fdbf
 2020-06-11 12:55:57 -06:00
Jeremy Soller
bc3e31005d Use DISABLE HECI message instead of HMRFPO 
Change-Id: If1c3dfed4aff7f8299951cfe429677c9ea92b086
 2020-06-11 12:55:57 -06:00
Jeremy Soller
1ca3e44c90 Add gaze15 and oryp6 
Change-Id: Iff7c619b388f95ef60b32a77858c790d2e0f6126
 2020-06-11 12:55:57 -06:00
Jeremy Soller
42cf287a62 Disable i2c-hid on galp3-c and galp4 2020-06-04 11:42:37 -06:00
Jeremy Soller
05577fc186 Revert "whl-u: remove invalid i2c_hid interrupt" 
This reverts commit 09b8f28bb0.
 2020-06-04 11:27:04 -06:00
Jeremy Soller
09b8f28bb0 whl-u: remove invalid i2c_hid interrupt 
Change-Id: Id62800031ba9c2e990bfd25de708ab249c9f2e96
 2020-06-04 11:13:57 -06:00
Jeremy Soller
cde1985ec3 Add addw2 
Change-Id: I773fc5561857591da12c31f0f7be9f74cc98a239
 2020-06-04 10:11:18 -06:00
Jeremy Soller
5b18ffb566 Update cannonlake FSP 
Change-Id: I7be51195779a1cca77186e8dab54b168fc234fb0
 2020-06-04 10:09:13 -06:00
Jeremy Soller
24ba49558e system76_ec: Improve performance 
Change-Id: I4c35dd70067d78c3eded549de1a37ded6db3d364
 2020-06-04 10:05:39 -06:00
Jeremy Soller
d06f9c7699 kbl-u: Fix compilation 2020-06-04 09:13:54 -06:00
Jeremy Soller
6bd5d1934c kbl-u: remove MAINBOARD_USES_FSP2_0 2020-06-04 08:59:27 -06:00
Jeremy Soller
37dc6de31d kbl-u: Sync some changes from whl-u 2020-06-04 08:56:09 -06:00
Jeremy Soller
5c6c34c32b whl-u: Sync with cml-u 2020-06-04 08:41:06 -06:00
Jeremy Soller
64faf29f6b cml-u: enable s0ix and c6dram 2020-06-04 08:40:48 -06:00
Jeremy Soller
27753e2b4f lemp9: enable s0ix and c6dram 2020-06-04 08:40:35 -06:00
Jeremy Soller
7f40e1b1f7 lemp9: Remove backlight code 2020-06-04 08:40:21 -06:00
Jeremy Soller
15eec6ad44 cml-u: sync with lemp9, enable i2c-hid 2020-06-03 15:39:47 -06:00
Jeremy Soller
ba59168f06 cml-u: update license headers 2020-06-03 15:39:19 -06:00
Jeremy Soller
a14d7ac871 Fix submodule URLs 2020-06-03 14:19:46 -06:00
Jeremy Soller
0625765de5 Merge remote-tracking branch 'origin/master' into system76 
Change-Id: I4593b91276d447f8ac00daca7388fdfb22bca7f2
 2020-06-01 14:11:34 -06:00
Angel Pons
8d09a06aa6 src: Fix up #-commented SPDX headers 
Delete leading empty comment lines.

Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-06-01 17:08:53 +00:00
Angel Pons
d5d4fbc072 sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits 
Commit 73ae076 "fixed" accesses to the PCI command register that were
not 16 bits, but also lost some bits to be written in the process.

Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2020-06-01 17:05:58 +00:00
Angel Pons
d49690bbe8 src: Fix up ##-commented SPDX headers 
Delete leading empty comment lines.

Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-06-01 17:01:13 +00:00
Angel Pons
4b975bb79f soc/intel/common/block: Remove unused headers 
Change-Id: I8877a70661cacc57ea893da172d9a4b6d19ba06a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-06-01 17:01:04 +00:00
Angel Pons
95d429b1cd mb/asrock/b85m_pro4/cmos.layout: Remove copyright notices 
Change-Id: I2aaabec17073c0a2ccd40de068223a9215186db3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-06-01 17:00:44 +00:00
Angel Pons
db0d949380 mb/asrock/e350m1: Do not redefine AGESA_VERSION_STRING 
This is the only AGESA f14 board which has a different version string.
As it is most likely a copy-paste error, drop the redefinition of this
macro from buildOpts.c and use the value defined in AGESA f14 headers.

Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-06-01 17:00:26 +00:00
Angel Pons
db2e11841a AGESA f14/f15tn/f16kb: Clean up buildOpts.c files 
Until now, the buildOpts.c files were primarily made out of copy-pasted
AGESA options, commented-out definitions and several useless comments;
that is, the materialization of technical debt in GCC-parsable form...

Until now.

It is assumed that the boards in the tree still boot. So, by comparing
their settings, we can extract saner defaults to place into AGESA. Many
of the settings were common across all boards of the same family, so we
promote those values to default settings. In some cases flipping a flag
was required, so the macros to alter that option had to be adapted as
well. Since those AGESA versions are expected to never receive updates,
it should not be a problem to change their files to suit our needs.

As a result, all but two buildOpts.c files now have less than 100 lines.
AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require
about 60 or 70 lines in those files. Hopefully, this will make porting
more mainboards using AGESA f14/f15tn/f16kb a substantially easier task.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
 2020-06-01 17:00:15 +00:00
Edward O'Callaghan
a81be27dc5 mb/google/hatch: Add Noibat variant 
A verbatim copy of variants/puff.

BUG=b:156429564
BRANCH=none
TEST=none

Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-06-01 02:24:26 +00:00
Venkata Krishna Nimmagadda
fc3eb1ca1d soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntax 
This change updates pch_hda.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

BUG=none
BRANCH=none
TEST="BUILD for Volteer"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-05-31 09:37:21 +00:00
Venkata Krishna Nimmagadda
03a05b47e0 soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0 
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

BUG=none
BRANCH=none
TEST="BUILD for volteer"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-05-31 09:37:00 +00:00
Jan Dabros
5694342a81 Documentation/tutorial: Add tutorial for writing unit tests 
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I1ebd2786a49ec8bc25e209d67ecc4c94b475442d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-05-30 08:46:59 +00:00