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Author SHA1 Message Date
37d8c215a2 update coreboot trunk version
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 18:30:41 +00:00
c9f5f87709 get rid of old news.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 17:04:04 +00:00
af97d33ec4 Clean up ACPI:
- unify all iasl related rules into the toplevel Makefile
- build a filesystem standard for ACPI files and use it
- pass ACPI sources through cpp, so constants can be shared
  between C and ACPI more easily
- use cpp's #include instead of ACPI's Include() so cpp gets
  the whole picture

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 15:46:37 +00:00
0e92974904 straighten naming scheme for application processor rom stage files.
Apparently they are not used. If you have any of the boards touched in this
commit, please test and report (so we can figure out what to do with the
ap_romstage.c files in general)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 12:32:30 +00:00
38f147ed3d janitor task: unify and cleanup naming.
cache_as_ram_auto.c and auto.c are both called "romstage.c" now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 12:20:50 +00:00
d51eddbb66 fix further build.h dependencies that were undetected before we enabled it on
our parallel build server ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 22:56:06 +00:00
bfff67db7d romcc _also_ has to wait for build.h to be generated.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 22:27:49 +00:00
abf2ad716d newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 21:43:48 +00:00
389240f288 this should get the VIA VT8454c in shape with Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-05 16:10:01 +00:00
b6b192af9f Add -pipe .. notably speeds up windows builds.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-05 14:32:00 +00:00
2598214f57 This patch fixes the build for the dsdt.asl/dsdt.c.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 11:08:59 +00:00
f14e69bc62 typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 11:05:59 +00:00
d8ab6bd0db Remove lots of cruft from gigabyte/m57sli's Config.lb
and fix the build.
Change the default ROM size to 1MB

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 10:28:16 +00:00
de7c6fa5fc Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there
were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file - one
setting the parameter to 0, the other setting it to 2.

Revision 5051 removed one of the two SB_HT_CHAIN_ON_BUS0 sections - the wrong
one. This patch fixes that.

Revision 5051 removed the wrong setting because newconfig for this board was
*also* wrong. This patch fixes that too.

Tested on real hardware, both with Kconfig and newconfig.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 03:03:39 +00:00
04d74b1fdd Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.
This automatically adds the settings for those boards that didn't have settings
at all yet. Also, small fixup to compareboard.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

--> Please help porting all boards from newconfig to Kconfig <--

This is a lot of janitor work and we can use your helping hands.
The sooner we can get rid of Kbuild, the better. The KBuild report
on the mailing list shows the config differences between newconfig
and Kconfig. In theory, all Kconfig configs should be equal to their
newconfig pendant. In practice it's better to come close but stay 
clean.

--> Please help porting all boards from newconfig to Kconfig <--



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 01:32:43 +00:00
52da560bf6 Add dump support for the Winbond W83877AF (trivial).
This Super I/O doesn't seem to know the concept of LDNs, it's just a
bunch of registers not splitted into banks/LDNs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 00:55:06 +00:00
d0d7c0158d Supermicro H8QME-2+ (Fam10) whitespace fixes (trivial).
This makes the code more similar to the h8dmr_fam10 target in order to make
the diff between both smaller and more readable.

Build-tested with newconfig and kconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 22:07:57 +00:00
3fb8c6637e Add missing CONFIG_ prefix to make manual QEMU build work (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 20:52:14 +00:00
f657bfce3b Trivial: In QEmu, the fallback image should USE_FALLBACK_IMAGE.
(fixed buildtarget)


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 17:57:55 +00:00
a6c337dec0 Guards against errors that are hard to track down:
- if crt0s is empty (eg. because crt0-y is still used),
  break the build, and say where that behaviour changed
- if a stage is unusable for cbfstool because it's placed
  outside the ROM space (linked to 0 is somewhat notorious),
  warn about it, give some hints and exit instead of crashing.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 17:56:37 +00:00
f1b6f1f2bb Fix incorrect board names in Kconfig strings (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 17:25:34 +00:00
081c8978ac This patch adds the Supermicro H8QME-2+ (fam10) Motherboard with the
following remaining issues:
- ACPI not working
- SMBus gets irq 0 instead of 5
- Loading VGA rom fails (using seabios to do it)

(copied a newer Makefile.inc from h8dmr_fam10 vs. the patch on the list)

Signed-off-by: Knut Kujat <knuku@gap.upv.es>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 16:04:40 +00:00
5a559d4386 The UART2 on the AMD cs5536 is incorrectly configured in two places.
GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault).

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-03 13:49:24 +00:00
fa742da56b Alot of it is trivial clean ups and 830 is now able to initialize one row/side of memory at a time.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-01 22:51:18 +00:00
14be4d0d52 - Improve help texts for option ROM initialization methods
- disallow REAL_MODE method if ARCH_X86 is not set.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 21:46:12 +00:00
15b0354107 compareboard:
- drop all occurences of LOGLEVEL settings.
- drop CONFIG_CPU_[VIA|INTEL|AMD] because they're Kconfig only.
- re-enable CONFIG_IOAPIC for now, it might need some fixing.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 20:51:00 +00:00
588d166091 Add detection support for the Winbond W83877AF (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 18:48:34 +00:00
6f0074e6b6 Trivial fixup on IP1000 and RM4100 copyright entries.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 14:56:15 +00:00
b8a89da213 These lines slipped in. Sorry for the inconvenience.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 10:58:30 +00:00
c2ef1463b6 ifeq wants a space before the (
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 10:50:57 +00:00
68003b8d14 add Kbuild support to abuild and enable it per default;
use -o/--oldconfig to get the old behavior (and use that 
option in kbuildall to get the old config)

I changed the qa.coreboot.org autobuild system to use -o
for now so we get build reports from the old and new config,
still.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 10:44:28 +00:00
e37785791a * fix crt0s/ldscripts paths to fix out of tree build.
* fix iasl output directory for i945 boards (patch
  for moving it to the mainboard directory will follow)
* coreboot_table.c: lb_mainboard can be static
* coreboot_table.c: dump memory table in debug and spew mode
* fix a warning in bootblock.c
* don't include arch/i386/init in arch/i386/Makefile.inc
* announce generation of crt0_includes.h
* allow overriding $(obj)
* drop unused src_types from Makefile
* correctly use hostname -s instead of hostname for COMPILE_HOST

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 09:47:18 +00:00
89e45773a9 RCA RM4100 and Thomson IP1000 auto.c rework.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-29 19:15:10 +00:00
6bba29f84a Add the BSD-licensed getopt tool to crossgcc, to use
if there's no native getopt around.

Use $PATCH instead of the hardcoded "patch" for patching
files (after we already looked it up)

Ignore various temporary files via svn:ignore

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-29 17:40:52 +00:00
cccbb898e2 Make $(obj)/build.h an explicit dependency for all
object files, as it's dragged into the build by
-include $(obj)/build.h for pretty much everything.

Also, generate build.h atomically.

This fixes parallel build with kconfig on my box.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-29 17:38:57 +00:00
24ddfd4b7d Fix manual build of the ASUS A8N-E (trivial).
Without this patch the manual newconfig (not kconfig) build would fail with:

  #error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"

I tested an image on hardware, it starts booting now, but doesn't fully
succeed as there are other issues (I'm investigating).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-28 22:25:49 +00:00
d9d5e345c0 reformat Kconfig file, too.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-27 19:55:01 +00:00
4355beb893 Add the MSR writes that are needed to provide VGA legacy routing for the Geode LX
Add appropriate Kconfig defines to provide 8mb of VGA ram allocation
Add the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup
Two small warning removals about excessive prototyping.

Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-27 19:20:29 +00:00
87d0c542b6 Change memory map of geode lx: 768kb-systop is a
single range.
This change allows both seabios and filo to boot
linux successfully (which was confused before)

Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-27 18:19:33 +00:00
47afa44a9f Mark c0000-fffff as usable on geode-lx. SeaBIOS needs it.
a0000-bffff might be usable as well, but it won't hurt to
keep that range excluded.

Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-26 15:34:15 +00:00
c6d3ff6cdd use stdint types for structures, and don't use pointers
for fields defined 32bit in the multi processor specification.

Also, fix lots of trivial warnings in the code.

If you ever wondered, why you get odd or wrong mp tables on your x64
system: It's not because bios vendors neglected mp tables; it's because
we neglected 64bit systems. ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-26 14:09:30 +00:00
a9796ed362 - Clean up and comment writing of MSRs for cache control (Backport from v3)
- Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM
- Re-enable cache after flush of CAR to RAM


Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-26 11:22:43 +00:00
e8d943f266 Fix ACPI build on a couple of boards (now that it's active)
Fix timer handling on amd/sc520 systems
Match UDELAY_* configuration of newconfig in Kconfig

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 15:17:11 +00:00
3e4a0b87c8 This code was copied from amdk8 and never really made usable.
It's supposed to be a userspace regression test for ram init, but
in fact, it doesn't even execute ram init. This was suggested by
Carl-Daniel on 2009-08-27
Thus, dropping it.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 13:15:17 +00:00
2b962a3c39 More Kconfig changes to improve match with newconfig:
DIMM_SUPPORT
APIC_ID_OFFSET
ACPI_SSDTX_NUM
IRQ_SLOT_COUNT
MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
	(except msi/ms9185)
MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
MEM_TRAIN_SEQ
HAVE_ACPI_RESUME

Also remove MMX (kconfig specific) and HAVE_MOVNTI and IOAPIC
(which we deliberately differ in kconfig) from compareboard
report.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 10:50:21 +00:00
29647d97c5 Align several kconfig options to match newconfig:
HT_CHAIN_UNITID_BASE
HT_CHAIN_END_UNITID_BASE
SB_HT_CHAIN_ON_BUS0
SB_HT_CHAIN_UNITID_OFFSET_ONLY
MAX_CPUS
MAX_PHYSICAL_CPUS
ROM_SIZE
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2

Also hook up asus/p2b-ds

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 07:56:01 +00:00
480b37f8e9 Document CONFIG_PCI usage in the README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 17:29:38 +00:00
2ca94910d8 Update list of superiotool contributors to r5048 (trivial).
The list is mostly generated by grepping for Signed-off-by in 'svn log'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 17:15:25 +00:00
622fb793e5 Add missing files from the last commit (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 01:47:58 +00:00
bb38f3213b Add VIA VT82C686A/VT82C686B detection support to superiotool.
This adds an additional requirement to superiotool: libpci.
The PCI code is conditional on PCI_SUPPORT. You can set the
CONFIG_PCI variable in the Makefile to 'no' to disable it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-24 01:40:46 +00:00
5142dcd530 Add detection support for the Winbond W83667HG Super I/O.
$ sudo ./superiotool
superiotool r4931
Found Winbond W83667HG (id=0xa5, rev=0x13) at 0x2e

Details: http://lists.lm-sensors.org/pipermail/lm-sensors/2008-July/023683.html

Signed-off-by: David Bartley <dtbartle@csclub.uwaterloo.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-23 21:51:10 +00:00
b850eb8e47 Add detection support for ITE IT8510E/TE/G and IT8511E/TE/G.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-23 15:50:12 +00:00
16f515adfc These two files accidently got a wrong license header.
Clarified with the authors

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-20 18:44:30 +00:00
762a230dc0 Kontron 986LCD-M MP table:
When any of the onboard network cards are disabled, the bus numbers change 
and thus PCI devices in the riser wouldn't get their interrupts right if a
kernel without ACPI support is booted. This patch dynamically creates the 
correct bus numbers for the firewire and riser card entries

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-19 21:15:37 +00:00
c6f2bd0d69 Add Yabel support (int 15 5fXX callbacks for vga bios) on the kontron 986lcd-m
so it's possible to use the LCD panel connector. Values are hard coded instead
of read from CMOS but it's a start.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-19 21:15:01 +00:00
775a766462 dev->rom_address was dropped a while ago which broke yabel. This patch fixes it
again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-19 21:14:24 +00:00
8ed1b6d2dc drop COREBOOT_V2 and COREBOOT_V4 define. We're not sharing code with v3
anymore so this ugly hack is no longer needed.
 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-19 21:13:44 +00:00
d5663bac2c Move all IOAPIC selection to southbridges, and remove them
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.

Fix intel/d945gclf build, which was missing some ACPI component.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 17:30:36 +00:00
2e97383b54 run preprocessor on DSDT of D945GCLF, otherwise
smart iasl will segfault.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 15:08:14 +00:00
6acc0a1795 ncurses is only a requirement for make menuconfig, not for Kconfig in general.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 12:01:10 +00:00
81d5b0ca30 add ncurses to list of requirements
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 11:10:03 +00:00
29c0ec10a6 get rid of Kconfig warning.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 11:09:24 +00:00
85bb83aeaf msrtool: Fix typo
Trivial!

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 21:59:27 +00:00
cba6169515 msrtool: Read both MSR values from file in diff mode
Previously, msrtool would assume that MSR values should be compared
between stored value in file and current value in hardware which msrtool
was running on. This does not always fit the use case and with this
change msrtool can now compare two sets of MSR values stored in a file.
If only one MSR value is stored in the file, msrtool will behave as
before, and read the second MSR value from hardware.

This change means that msrtool does not always need access to the system
MSR functions so it can now be run as a regular user when using diff
mode with both MSR values stored in the file.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 18:34:00 +00:00
34f2907a1b msrtool: Add endptr to str2msr() showing how many characters were parsed
This also introduces a small change in the user interface for immediate
mode (-i). Previously, whitespace could separate high and low words in
an MSR as such:

msrtool -i 4c00000f='f2f100ff 56960004'

That is no longer allowed, a space character now ends the MSR value. Any
other character can still be used as separator however, so the following
syntax still works as expected:

msrtool -i 4c00000f=f2f100ff:56960004

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 18:33:53 +00:00
838c5a5d80 Add support for the Roda RK886EX a.k.a Rocky III+ ruggedised notebook
http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 14:08:17 +00:00
f6eb88adfb Initial PCIe tuning: Enable Active State Power Management (ASPM)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:54:08 +00:00
2e73e19751 Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:52:50 +00:00
f00052afbf Add support for Renesas M3885x Embedded Controller
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:51:48 +00:00
55426dfd57 Add support for the SMSC LPC47n227 SuperI/O chip
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:50:17 +00:00
7a3d095213 ICH7 update
* change the code to use macros names instead of constants in many places
* SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x)
* SMI: Add support for mainboard GPI handler
* SMI: immediate power-off on power button press, if OSPM is not active
* Add fix for some USB errata
* Some register tweaks for mobile systems
* Enable configure SCI on interrupt 9 correctly.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:49:07 +00:00
24b4df5f99 Support a few more i945 variants. With this framework in place it should
be possible to support i955 and i975 relatively easy, too.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-17 13:47:35 +00:00
e6cf7c0d4f msrtool: More trivial rearrangement
Rename some variables
Remove the 'found' variable which turns out not to be needed anyway

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 18:39:35 +00:00
0401bd89b6 coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 18:31:34 +00:00
9fe4d797a3 coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)

read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.

This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 17:53:38 +00:00
984e0f3a0c ectool: Support for dumping EC "index ram"
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 17:50:55 +00:00
350ca4a94f msrtool: Remove indent by using continue inside for() to avoid an if block
The only actual code change is from
if (.. >= 1) {
}
to
if (.. < 1)
	continue
so this is pretty trivial.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 17:21:17 +00:00
6ade161442 Update reference toolchain to
gcc 4.4.2
binutils 2.20
gdb 7.0

and add mingw support.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 16:44:20 +00:00
f2da0d5654 Intel D945GCLF: Enable SMI and ACPI in Kconfig, too (it's enabled in newconfig)
and guard SMI specific parts of the ACPI code.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 16:39:50 +00:00
38c9965977 (trivial) cosmetics for i82801gx cmos failover.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 16:37:27 +00:00
67cd802990 * drop reset files from 945 mainboards (and use southbridge specific reset)
* drop debug.c files from 945 mainboards (and share it in the northbridge code)
* adapt the mainboard and auto.c files for above changes.

Rather trivial 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 16:35:38 +00:00
42944c3989 nvramtool: Consider a string with non-printable characters a "bad value".
Otherwise nvramtool -a with random cmos contents can mess up your terminal.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 14:57:32 +00:00
12ee934cb3 Make internal functions static in speedstep ACPI generation code.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:49:03 +00:00
f0ec230280 Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.
This unifies the base with Core and Core 2 CPUs.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:48:20 +00:00
ba8b21c376 Micro-optimization: movl $0 --> xorl.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:47:07 +00:00
68b3c4637a new microcode for Intel Core 2(tm) CPUs
(taken from Intel's Linux microcode release)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:42:43 +00:00
2fbbea0f30 RTC: Don't drop the alpha specific code but get it in shape for our Kconfig scheme.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:27:39 +00:00
fb333c423e (missing svn add)
Support for the AMD Geode GX2 
Processors to Msrtool.
It seems to work as it was tested on a Wyse Winterm S50.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-15 10:07:05 +00:00
58a901f6f9 Support for the AMD Geode GX2
Processors to Msrtool.
It seems to work as it was tested on a Wyse Winterm S50.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-15 10:06:39 +00:00
90b96b68e0 indent all of nvramtool to make it fit into coreboot's
coding style

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-13 21:00:23 +00:00
766db7ea09 Make qemu use the udelay function in src/pc80/udelay_io.c
instead of the equivalent copy in src/cpu/emulation/qemu-x86/northbridge.c.
Also, delete the copy.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-11 09:05:52 +00:00
07684e6ce7 - Makefile.romccboard.inc supports tinybootblock romcc boards, too.
- via/epia-cn is a romcc board, not a CAR board. (Thanks Kevin, for the report)
- Make emulation/qemu-x86, dell/s1850, via/epia-cn use Makefile.romccboard.inc
- New flag: BIG_BOOTBLOCK, which is always the inverse of tinybootblock
  Suitable for Makefile.inc rules (foo-$(CONFIG_BIG_BOOTBLOCK) += ...)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-08 11:26:02 +00:00
f44eb7876b Print (empty) instead of nothing at all for empty
filename entries (particularily "null" files)

Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-07 21:37:18 +00:00
7250d9d00e Move fam10 temp files from build/ to build/northbridge/amd/amdfam10/ Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-06 17:05:37 +00:00
1af297c6eb Check for installed compilers (remove .xcompile) at make clean, not distclean.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-06 16:59:18 +00:00
3d1135948a Fix amdht on newer compilers.
We were lucky with friendly compilers. Now they're assuming too much.

Identified-by: Myles Watson <mylesgw@gmail.com>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-06 10:07:31 +00:00
753169dc25 Kconfig builds all boards now.
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.

Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.

AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-06 09:14:08 +00:00
95c50c6091 - Let AMD CAR code pick the right XIP area
for tinybootblock
- move asus/m2v-mx_se to tinybootblock
- Add romstrap for via southbridge to tinybootblock-bootblock

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05 17:35:44 +00:00
a0c68f864e * Explicitly add __PRE_RAM__ where it should be added.
* Don't implicitly add __PRE_RAM__ in romcc. 

Fixes intel/xe7501devkit

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05 13:03:02 +00:00
1f807fd42f - Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
(defaults to UDELAY_IO again, like newconfig)
- Use UDELAY_TSC on Via C7 [kconfig]
- Support Tinybootblock on Intel CPUs
- set XIP location correctly for Tinybootblock on Intel
- provide correct XIP location in Tinybootblock configuration
- Make kontron/986lcd-m use Tinybootblock
- Some kconfig fixes to kontron/986lcd-m [kconfig]

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-04 20:09:27 +00:00
ce56835a5c - use LAPIC timer if selected (instead of TSC all the time) [kconfig]
- uncomment commented out intel socket [kconfig]
- HAVE_MOVNTI is a property of the cpu [kconfig]

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-04 14:36:55 +00:00
a29fb61ff4 improve debug output.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-03 15:35:52 +00:00
1bb6828900 romcc:
- Set __PRE_RAM__ define per default
- Properly handle ignored (#ifdef'd out) #include lines

amd/serengeti_cheetah_fam10:
- write ACPI files to $(obj) instead of the top dir (alias $(CURDIR))

tinybootblock:
- provide a way to define code that should be added to the bootblock,
  to map the entire ROM for use by CBFS

amd/model_fxx, amd/model_10xxx:
- add CONFIG_SSE

walkcbfs.S:
- eliminate the use of two registers, to make space for romcc to wiggle

amd/serengeti_cheetah_fam10:
- use the enable_rom framework. not entirely functional yet

Boot-tested on emulation/qemu-x86
Build-tested on amd/serengeti_cheetah_fam10
amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-31 12:56:53 +00:00
9db833bec3 trival. All the changes is about comment and spaces.
In superio folder.

1. Delete trailing white spaces.
2. Change the // comment to /* */.
3. Add some copyright header.
4. reindent.
5. delete multi blank lines.

I tried my best to find them. If anything left, please fix it
or tell me.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-28 09:59:44 +00:00
0f0aa15e7e Fix technexion tim5690 build failure - REALMODE option required for x86.c mainboard function to be built.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-23 22:16:18 +00:00
a64f888b27 newconfig compilation failed with
(.text+0x4989): undefined reference to `vgabios_init'

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-23 19:46:36 +00:00
c143693c26 Add mainboard x86emu interrupt function support. Add tim5690 VGA BIOS functions: int15 getting LCD panel ID.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-23 19:16:47 +00:00
9341acda13 Tiny Bootblock, step 1/n.
Introduce the tiny bootblock infrastructure and use it on QEmu.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-23 12:52:56 +00:00
336daa76fa make strcmp happy by including string.h (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-21 15:09:01 +00:00
467b12acab Allow user to specify the size of a newly created cbfs image
to be stated in kilobytes or megabytes. Usage is
cbfstool coreboot.rom create 1048576 coreboot.bootblock
cbfstool coreboot.rom create 1024k coreboot.bootblock
cbfstool coreboot.rom create 1m coreboot.bootblock
to get an 1048576 bytes = 1024kb = 1mb image.

Kconfig also uses this instead of calculating bytes from kilobytes itself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-21 13:50:37 +00:00
7a27fc558d Make coreboot load VSA from CBFS on amd/gx2.
You have to convert the VSA bios image to ELF using the following
commands (assuming i386/32bit binutils, if in doubt, use crossgcc's
i386-elf-* tools):

objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o
ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf

Then, after build, use
cbfstool coreboot.rom add-stage vsa.elf vsa l
to add it to the image.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-21 12:32:29 +00:00
eecaba8b6c Clean up amd/dbm690t and kontron/986lcd-m some more (not
fully). Also fix the kconfig build for HAVE_ACPI_RESUME.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-18 16:43:30 +00:00
f3662fcd2c CONFIG_K8_MEM_BANK_B_ONLY and CONFIG_PCIE_CONFIGSPACE_HOLE aren't used _anywhere_, so drop
them from view (they could be dropped from newconfig, too - but why bother?)

trivial

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-18 15:29:23 +00:00
99cf3499b0 Filter out some more K8/Fam10 specific options on unrelated boards.
Trivial.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-18 13:36:43 +00:00
50b5b2b4ee - speed up board comparison by only building abuild configs, not the whole
target.
- use a template for mktemp (fixes OSX error)
- convert all numbers to hex to make comparison easier.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-18 10:20:15 +00:00
1a4d90078a Make "KBuild report" a bit happier
- drop some unused options from "newconfig"
- filter some Kconfig only options from the report
- drop targets directory of a non existent mainboard.

(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-17 18:47:50 +00:00
48ca7b2d08 minor bug in the cbfs documentation (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-17 09:42:30 +00:00
ee55f80410 Make sure that the h8dmr_fam10 has the proper version string.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-16 19:48:45 +00:00
8fddb24abb The drivers for the k8t890 weren't being built. Increased heapsize.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-14 21:52:56 +00:00
85e6870098 crossgcc: Fix MPFR download location
We want to download a specific version so fetch it from the right directory.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-13 13:39:01 +00:00
b66fb79d56 Push VSA into CBFS for amd/lx systems. It's not hooked up to
the build system yet, so some additional steps are necessary.
It's not that bad, given that the code didn't work before.

You have to convert the VSA bios image to ELF using the following
commands (assuming i386/32bit binutils, if in doubt, use crossgcc's
i386-elf-* tools):

objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o
ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf

Then, after build, use
cbfstool coreboot.rom add-stage vsa.elf vsa l
to add it to the image.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-10 17:38:30 +00:00
f4aca1da48 cbfstool: Fill memory allocated in create_cbfs_file() with 0xff
This should improve programming speed a bit.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-06 12:14:39 +00:00
1a76ebe2a2 Trivial fixes for kconfig. They fix all non-fam10 build failures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-02 21:11:12 +00:00
59968f5c81 Trivial fix for kconfig socket 441 (typo was 411) so that d945gclf builds.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-02 05:43:50 +00:00
eb097aad6a Eliminate some noise in the output of compareboard on non-K8/Fam10h boards
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-01 18:19:42 +00:00
0f6ee7b719 Not all boards cope with automatically sized bootblocks, leading to 4GB
images due to the "helpful" 4GB rollover behaviour of ld(1).

Back out r4961, something like this should go in eventually, but more
completely tested and working.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-01 09:35:19 +00:00
702a5a5741 Atom only supports 32bit MTRRs (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-01 08:15:38 +00:00
01dd9e1182 Trivial. SCH4304 and SCH4307 have the same device id.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-01 03:22:16 +00:00
6085527461 Add support for the SMSC SCH4304 Super I/O.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-30 23:53:06 +00:00
4d41a3bfc3 Maciej Pijanka tried to get the Biostar M6TLD running, and created a patch for
440lx using the 440bx code as a template.

Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-28 09:31:30 +00:00
f30a222074 msrtool: Fix simple breakage in r4964
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-28 05:30:57 +00:00
d80e57c9c8 msrtool: Add FreeBSD support using /dev/cpuctl ioctl interface
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-28 05:21:42 +00:00
7df17af13b msrtool: Make configure more POSIX sh friendly
Change a few bash-specific constructs to more portable syntax specified by
POSIX.  After the change the script keeps working with bash interpreter and
can also be interpreted by FreeBSD /bin/sh.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-28 04:54:33 +00:00
be89c41ae3 msrtool: Actually do PREFIX substitution in Makefile
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-28 04:45:34 +00:00
436f99b72a Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
where necessary (if romstraps get in the way).
For Kconfig, the special case is set per southbridge (as these define the necessity for this
workaround), for newconfig it's added to each single board.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27 16:55:13 +00:00
c58290c2ff Let ld(1) calculate the required size for code in the bootblock
automatically.

Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27 14:32:17 +00:00
b0f82d9cd3 Really hook up s2850 and s2875. Trivial.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27 11:04:08 +00:00
4638c924f0 Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID
Usually, this means adding values to Kconfig, but in a few cases, adding values
to newconfig, too (which doesn't hurt).

Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still
build.

Trivial and stupid kconfig changes, just lots of them.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-27 11:03:20 +00:00
13250d13f7 Remove commented out example MSR definitions
Now there are definitions for actual MSRs that can be referenced instead.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-26 14:03:25 +00:00
226280cdb9 Add the following GeodeLX memory controller MSRs
0x20000018 MC_CF07_DATA
0x20000019 MC_CF8F_DATA
0x2000001a MC_CF1017_DATA
0x2000001b MC_CFPERF_CNT1
0x2000001c MC_PERFCNT2
0x2000001d MC_CFCLK_DBUG

Signed-off-by: Nathan Williams <nathan@traverse.com.au>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Nathan Williams <nathan@traverse.com.au>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-26 13:54:40 +00:00
d9276e5eab Trivial style changes, replace a few C++ type comments, and some code reuse
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25 08:35:59 +00:00
4e54b4037f This patch is buzzer of TechNexion TIM-5690.
I forgot to svn add the speaker.c and speaker.h.

Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25 08:14:04 +00:00
4cede71767 This patch is buzzer of TechNexion TIM-5690.
Change EARLY_STAGE into __PRE_RAM__.

Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25 07:48:24 +00:00
46c920e13a msrtool: Fix Geode LX probe function, Family/Model were swapped
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-25 02:25:37 +00:00
26774f2b72 Make the kconfig-style build work in mingw:
* use relative paths in ldscript.ld and crt0_includes.h
* avoid use of dd(1) in xcompile
* build libregex for kconfig, if necessary
* work around missing utsname on win32
* unlink targets before rename on win32
* implement (crude) mkstemp for win32
* avoid open/read/close, use fopen/fread/fclose instead
* don't free certain data structures in romcc on win32 to
  avoid crashes (likely use-after-free())
* handle "\CRLF" and win32 style absolute paths (X:/ or X:\)
  in romcc
* make lzma (part of cbfstool) build on XP
* implement ntohl/htonl on win32
* handle CRLF in awk script
* set larger stack for romcc on win32

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-21 19:54:02 +00:00
b198a478ed Add GLCP_SYS_RSTPLL MSR defines for GeodeLX
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Nathan Williams <nathan@traverse.com.au>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-21 06:02:48 +00:00
354bde6e0d Trivial fix for tyan/s2912 to build. Remove overspecified options in Config.lb.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-19 14:25:31 +00:00
3aa5f6178a Update amdk8/util.c since __PRE_RAM__. Make node & link more unique.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-18 17:10:36 +00:00
7a1e81a56f This is a patch to control the DIP switch and digital I/O.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-18 03:47:34 +00:00
ae3e9989ed Silence two warnings. Only use the Qemu hard-coded address for VGA devices.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-17 15:20:22 +00:00
61c6aec071 Initialize memory before using it. put_bits wants it that way.
Trivial.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-17 11:52:18 +00:00
34b876cfe1 msrtool: Add comment with DirectIO URL to the code where it is used.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-16 17:29:22 +00:00
cafac66d16 Fix manual (non-kconfig) build of the following boards, due to
missing renames of CONFIG_HAVE_PIRQ_TABLE to CONFIG_GENERATE_PIRQ_TABLE:

 - iwill/dk8s2
 - iwill/dk8x
 - emulation/qemu-x86
 - iei/juki-511p
 - tyan/s1846
 - msi/ms7135
 - arima/hdama

Build-tested for the QEMU target and IEI JUKI-511P.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-14 19:34:55 +00:00
5b69883877 Complete the Kconfig of socket_AM2r2.
This patch is from socket_F_1207, even though the fam10
can not be "make menuconfig"ed currently.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-13 06:43:33 +00:00
6a3ca4e0e9 Cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 20:06:32 +00:00
0d082d512e Print size of file on cbfs_add_file failure. The size of the file after
compression is nice to know.  Trivial

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 17:46:59 +00:00
bdf4157d81 Adapt ROM_IMAGE_SIZE, too. ROMBASE should probably be defined
by ROM_IMAGE_SIZE (so ROM_IMAGE_SIZE + ROMBASE - 4GB == 0),
but that's for another patch.

Should fix the issues created by the bootblock cleanup patch.

Build tested on kontron/986lcd-m, trivial change.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 17:25:16 +00:00
2e67273624 Add CONFIG_WARNINGS_ARE_ERRORS and set it for qemu.
Remove all remaining warnings from qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 16:38:03 +00:00
f9a72600a9 Trivial debug print format string fix for romcc.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 16:20:04 +00:00
2d892f1b37 Get rid of the ugly warning the right way.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-12 13:48:39 +00:00
339722e89e Revert my too-hasty commit.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-11 23:59:19 +00:00
8f84813775 Silence an ugly-looking warning. Two casts were not enough, so just don't cast
it.  Trust the option_table generator to get the length correct.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-11 23:32:36 +00:00
6056b97fce Rework bootblock size handling:
- don't pretend to create a bootblock as large
  as the ROM in Kconfig (it's 64k at most)
- don't pretend to accept a bootblocksize value
  in cbfstool create (it ignored it)
- patch up the build systems to keep it working

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-11 21:32:23 +00:00
c243639797 Help track down enable_rom issues in CBFS. If the magic
looks like unmapped memory, point to the wiki page with
more information.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-11 19:31:53 +00:00
c0ac7e9046 * Simplify acpi_add_table
* fix some comments
* Simplify ACPI wakeup code and make it work without a memory hole
* Add resume entries to global GDT so we don't need our own for resume.
* add ECDT description to acpi.h for anyone who might need it  ;-) 
* remove rather stupid math to get the right number of MAX_ACPI_TABLES
  and just define a reasonable maximum for now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-10 22:17:15 +00:00
a0141f050b Add detection and dump support for the Winbond WPCD376I.
Signed-off-by: Sean Young <sean@mess.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-09 22:34:17 +00:00
7f91d9236c Enable Multiboot table support (for GRUB2) by default.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Robert Millan <rmh.grub@aybabtu.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-09 17:56:47 +00:00
0da38dde4b Add a "locate" function cbfstool, which helps you find
out a suitable address to put a XIP stage to.

Specifically, you pass it the file (to get its filesize), its filename
(as the header has a variable length that depends on it), and the
granularity requirement it has to fit in (for XIP).
The granularity is MTRR-style: when you request 0x10000, cbfstool looks
for a suitable place in a 64kb-aligned 64kb block.

cbfstool simply prints out a hex value which is the start address of a
suitably located free memory block. That value can then be used with
cbfs add-stage to store the file in the ROM image.

It's a two-step operation (instead of being merged into cbfs add-stage)
because the image must be linked twice: First, with some bogus, but safe
base address (eg. 0) to figure out the target address (based on file
size). Then a second time at the target address.

The work flow is:
 - link file
 - cbfstool locate
 - link file again
 - cbfstool add-stage.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-09 17:18:02 +00:00
031029d4d4 These are post codes for TIM-5690 LED debug message.
Signed-off-by: Libra Li <libra.li@technexion.com>
Added object reference to Config.lb, too and
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-09 11:53:41 +00:00
d27c08c289 Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS.

Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 23:42:26 +00:00
547d48ab01 Remove some white space and comment differences from devicetree.cb and Config.lb
files.

These boards have non-trivial differences:
gigabyte/m57sli
kontron/986lcd-m
dell/s1850
via/epia-m700

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 17:32:32 +00:00
d63085b20e Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer 
necessary.

Also, drop vga_rom_address from RS690 completely, it was never used 
in the code.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 17:11:05 +00:00
eeec0ef00a Revert the deletion of drivers/pci/onboard that snuck in ahead of its time.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 17:09:11 +00:00
1d6d45e3c9 Split the two usages of __ROMCC__:
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."

There are probably some places where both are tested, but only one is needed.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 17:02:51 +00:00
637309d65e Remove hard coded bus numbers from arima/hdama mptable code and fix warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06 15:31:49 +00:00
be10190b7b Add debugging utility file for dumping routing registers on K8.
Ported from Ron's code in v3.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 21:02:35 +00:00
eb81a5b5fc Don't try to set fixed resources. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 20:06:19 +00:00
4374f428ff fix length field in dmi tables. Newer DMI versions through errors
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 18:08:16 +00:00
d18faac7eb if x86emu was running for VGA init a corrupted low table RSDP
is generated in the F segment. Clear the memory before generating an
RSDP to fix the problem.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 18:06:43 +00:00
4172efc17f biosemu (non-yabel) cleanup
* Drop pcbios folder that only exists for a single function
* include int1a handler in biosemu.c
* Wipe a lot of dead code, and set up F segment correctly
* include return value check from yabel.

On the long run we should teach yabel to be able to run with a reduced feature
set, ie. no emulation of (almost) all system hardware. Then we could drop the
non-yabel x86emu.
But for now this patch cleans up the non-yabel biosemu.c to a state where it's
not all that ugly anymore..

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 17:24:03 +00:00
46634e7100 fix Qemu
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 12:44:50 +00:00
67fed69653 http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html
This function is not called right now,... Please step in and fix up your code,
folks.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 12:38:34 +00:00
e6ad7fa4a6 If the coreboot and filo overlap, it will "slice off" a piece at the
"beginning" or "end". In the beginning case, a new segment is inserted
before the current one.  But the ptr will move forward and doesn't
seem to have any other chance to process the "new" segment.

                ptr ---------+     move --->
                             |
                             V
        +--------+       +--------+
        |        |       |        |
        |  new   | <---> |current | <---> .....
        |        |       |        |
        +--------+       +--------+

Now we change the ptr to the previous one and restart the loop. The
new and current segment will both be processed. Even if the current
segment is done twice, no new segment will come up and ptr will move
forward as we expect.

      +----------------ptr      move --->
      |
      V
 +--------+        +--------+       +--------+
 |        |        |        |       |        |
 |  prev  | <--->  |  new   | <---> |current | <---> .....
 |        |        |        |       |        |
 +--------+        +--------+       +--------+

It is tested and fixes the crashing on my AMD Family 10 board.

Some trailing whitespaces were deleted.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 10:02:59 +00:00
448509bb4e Get the passed in Bus/Device/Function from the correct location on the
stack.

Signed-off-by: Mark Marshall <mark.marshall@csr.com>

Clarified the comment and
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 09:09:20 +00:00
d08e69dd5e Use more care when implementing the PCI BIOS functions.
The READ_CONF and WRITE_CONF functions would both do the wrong thing
if the passed in BDF was not found.  We should return and error to the
caller, but not stop running the option ROM.

Signed-off-by: Mark Marshall <mark.marshall@csr.com>

I slightly reworked the patch:

The 'CHECK' function seemed to be both wrong code and the wrong
number. 

In fact the CHECK function was given the function number of
the "Microsoft Real-Time Compression Interface". Since this is definitely wrong 
I removed the code.

Dropped some unneeded scopes, too, to make the code easier to read.

Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 09:03:04 +00:00
2fa7c2e210 When loading an option ROM use the class stored in the device to
decide whether the option ROM is a special VGA type.

An S3 card that I've got has the wrong class in the VGA BIOS.
(A Stealth 64 DRAM T PCI, from 1994 - BIOS V2.02)

Signed-off-by: Mark Marshall <mark.marshall@csr.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-05 08:10:12 +00:00
5fc7f98c51 Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-04 12:18:44 +00:00
c6680487b9 Some fixes.
Atom does not like 36bit MTRRs in CAR setup.
Enable XIP setup again (works with 32bit MTRRs)
Keep code more similar to 6ex code..

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-03 15:02:15 +00:00
7110d40fbf x86emu: Add support for the following opcodes:
* SMSW
* INVD/WBINVD
* RDMSR/WRMSR
* CPUID

The implementation is kept very simple (mostly dummies) but it should get
us successfully through the Poulsbo VGA OPROM code in order to determine
further requirements.

Also, fix up a lot of warnings (mostly about missing prototypes for 
functions that should be static anyways)

This version adds a break in smsw that was missing in the patch that was sent
to the list.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-03 14:59:43 +00:00
8429de75a6 Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
The registers are (as far as I can tell) unchanged with respect to those
of the PM965.

Signed-off-by: Loïc Grenié <loic.grenie@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-02 15:01:49 +00:00
ba49fb76a5 typo. trivial. Then -> Than.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-01 09:18:23 +00:00
68ce4e7692 Set SB_HT_CHAIN_ON_BUS0 correctly for arima/hdama. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-31 22:13:04 +00:00
dc3214851b Only remove .xcompile with distclean. Look for crossgcc in util.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-31 20:47:14 +00:00
3f3a5f60d3 ADLO has long been replaced by SeaBIOS, and it's also in v1 if someone needs
it...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 20:38:15 +00:00
20d626572b drop svn:externals in the tree and add it locally.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 18:16:09 +00:00
9ac9e94b45 new utility.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 16:54:52 +00:00
850b22b90a coreboot repository cleanup
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 16:53:37 +00:00
552890b6cd clean up coreboot repo structure.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 16:51:46 +00:00
b7b82ef5c0 Fix, um... a typo.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 13:10:03 +00:00
81b3c0a10f Allow per-northbridge and per-board VGA BIOS file name and PCI ID defaults.
Of course, the user can still override those defaults, if needed.

Add defaults for VIA pc2500e, Kontron 986LCD-M/mITX, MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 12:56:59 +00:00
7943fe61df Remove some warnings from the tyan s2895.
Declare superio functions to be static and remove duplicates.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-30 02:08:07 +00:00
8f6354b6d3 Split a print statement that called dev_path twice, and add a warning comment.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-29 21:27:43 +00:00
dc4ca9a5de Add prototypes to silence these warnings.
src/lib/gcc.c:30: warning: no previous prototype for '__wrap___divdi3'

The prototypes were not added to lib.h because the functions should never be
called directly.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-29 16:49:50 +00:00
59b52190b3 Comment out option ROM line in Config-abuild.lb to fix build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 19:56:34 +00:00
3d83cff04b Add an initial version of some tools to compare (extended) K8 memory settings.
This generates (dirty) html with interpreted differences between PCI dumps,
based on the K8 socket F bkdg.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stepan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 19:41:52 +00:00
88214a48cc Drop remainders of PPC port
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 19:40:46 +00:00
e696942cfc Drop remainder of PPC port
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 19:38:58 +00:00
8d09e231fe Fix some builds with Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 18:57:06 +00:00
4ec4fbe0e9 Make d945gclf build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 18:51:47 +00:00
2d2f0c121f Add some missing license headers, consistency fixes for others (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 17:36:11 +00:00
6c73b4416c Remove all build/ prefixes in the build output.
Also, remove one missing hardcoded "build" dir in the distclean target,
and clean up files generated by sconfig in 'make clean'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 17:10:51 +00:00
1a08f582b5 preliminary Intel D945GCLF Atom+i945 support.
ram init fails, as the i945 driver currently only supports the mobile version
of the chipset..

Not sure how much sense it makes to check this in, but since it's a nice and
cheap board, maybe someone wants to work on this.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 16:52:48 +00:00
581707811c Create lib.h for homeless prototypes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 16:13:28 +00:00
d4e5c0a228 Replace hard coded build with $(obj) paths.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 15:30:11 +00:00
2a87ac6403 The check for zero sized resources is already done earlier. So don't redo it
here. I think we don't ever want to drop the extra check, since it indicates
that the components involved need fixing.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 14:57:14 +00:00
7782319c21 Prefix all build output file names of files which end up in the build
directory with "build/" for consistency (trivial, sort of).

Also, drop printing of "config.g" input file, we usually only print
generated/output files in the build output.

Finally, rename non-existing COMPRESSFLAG variable to
CBFS_PAYLOAD_COMPRESS_FLAG in a printf line. The build output now says

    PAYLOAD    payload.elf l

for payloads (the "l" specifies LZMA compression).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 23:14:54 +00:00
312673ca72 Improve coreboot build output and eliminate some warnings:
- Add static and const where possible.

 - Turn some #warning entries into TODO comments.

 - Add missing prototypes.

 - Remove unused variables.

 - Fix printf arguments or cast them as needed.

 - Make sconfig output look better. Drop useless "PARSED THE TREE" output.

 - Print "(this may take a while)" while building romcc. Add missing "\n".

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watosn <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 21:49:33 +00:00
a8888bd1d2 Remove redundant declarations. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 16:24:22 +00:00
a068164fc2 Add $(obj) paths for a couple of smm files so they don't end up in the top directory.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 15:53:27 +00:00
ea92185755 Add few missing prototypes, and remove few unused (thus lonelly) variables.
TODO
 - x86emu need (imo) some common header with prototypes at least
 - clog2, ulzma, hardwaremain prototypes added by this patch probably should 
   be moved to some header too.
 - in src/devices/device_util.c prototype is before function because seems, 
   it is used only within same file, if not it should be moved to debug
   section of prototypes in include/device/device.h

Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 14:29:29 +00:00
18d7c2e31e Update arima/hdama to detect how many nodes there are. Compare to tyan/s2892.
Fixes booting for Hugh.

Various white space fixes as well.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27 14:05:21 +00:00
a081a3b65f Various smaller console option fixes as suggested by Peter Stuge:
- Change "COM port" to "Serial port". 
 
 - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for
   easy recognition by the average user.
   
 - Change BAUD to Baud.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 23:52:34 +00:00
e21f75a8c3 cp src/mainboard/tyan/Makefile.k8_CAR.inc to src/mainboard/Makefile.k8_ck804.inc
Make more boards use both of them.

Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:49:00 +00:00
dbbfedf8b0 Move src/mainboard/tyan/Makefile.s289x.inc to src/mainboard/Makefile.k8_CAR.inc.
Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:03:30 +00:00
63a8f2a7c2 Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).

This patch adds choices for menuconfig to select the VIDEO_MB value for:

 - Intel 82810
 - Intel 82830
 - VIA CN400
 - VIA CN700

Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.

We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).

As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.

Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 21:42:13 +00:00
123a684ce6 Fix iei/pcisa-lx-800-r10. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 21:41:06 +00:00
afccdc0c56 Remove double include of smm directory. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 21:04:03 +00:00
472837ad61 reasonable output in cbfs loading (part 2)
run hlt in endless loop, be friendly to the cpu

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 17:17:37 +00:00
b4f3da5b14 reasonable output for cbfs loading..
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 17:15:53 +00:00
aca6ec66bf Kontron 986LCD-M update
- run ACPI code through preprocessor so we get the same values
  as the C code
- fix PCIe x16 slot
- fix ICH7 Azalia/HDA driver
- SMI/GNVS update security fix (only allow struct pointer update once)
- ACPI updates
- IDE driver fixes
- add cmos options for disabling onboard ethernet and controlling system fan

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 17:12:21 +00:00
3b31402380 CBMEM high table memory manager.
This code adds a very simple toc based memory manager for the high tables area.
The purpose of this code is to make it simpler and more reliable to find
certain data structures in memory. This will also make it possible to have ACPI
S3 Resume working without an ugly hole at 31MB.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 17:04:28 +00:00
a769344d43 intel core and core 2:
- small preprocessor fix
- leave some space in the CAR area for the usbdebug structure
  if usbdebug is used

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 16:49:16 +00:00
fbb8a01543 Use Intel Core code for eagleheights CAR init, not Intel Core 2, as
any of the CPUs might be used.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 16:48:27 +00:00
39e722958c Now that the resource allocator is working nicely we can turn down the debug
level output and make some output SPEW only.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 16:47:05 +00:00
d73c1b5bf1 Define some variables that were not defined. There are a couple left.
Do kbuildall then grep not.defined kbuildall.results/*
The interesting ones were GENERATE_*  I had to put them in twice to make it work
correctly: once outside the menu setting the defaults, and once inside the menu.
Now they show up when they should, and are always defined

Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0
in newconfig.
Define MEM_TRAIN_SEQ to be an integer and set it correctly.
Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10
MOVNTI is a performance enhancement, and should default to 0 so it doesn't break
boards that forget to define it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 15:14:07 +00:00
074356ec81 Option ROM init x86/x86emu update
- use default display in int 15 5f35
- move REALMODE_BASE to 0x600, 0x500 can be BDA
- add regparm for assembler functions
- use memset instead of own implementation
- YABEL: copy back the IVT, BDA and VBIOS. Some Xorg drivers require this.
- YABEL: use hardware timer instead of emulated timer, because the emulated
  timer's base is never initialized (leading to division by zero if the 
  timer is really used)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-25 19:50:47 +00:00
46a895e633 Fix intel/xe7501devkit build, missing "uses" clause.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 22:52:33 +00:00
1d8b0979c3 Fix kconfig build error due to "source"ing a non-existant file (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 22:42:53 +00:00
d1327ce963 Major cleanups of the hard_reset() code and config in coreboot.
- Drop unused "#object reset.o" entries.

 - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries.

 - Drop dead/commented code, i.e. useless hard_reset() from:
   - supermicro/x6dhe_g/auto.c
   - supermicro/x6dhe_g2/auto.c
   - supermicro/x6dhe_g2/auto.updated.c
   - supermicro/x6dhr_ig/auto.c
   - supermicro/x6dhr_ig2/auto.c
   - digitallogic/msm586seg/auto.c
   - dell/s1850/auto.c

 - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards
   that actually have a reset.c file.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 19:17:24 +00:00
8d2ddff011 Change QEMU CPU Makefile.inc files to match other CPUs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 19:07:05 +00:00
7223780b07 removal of that unnecessary include slipped through r4841
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:54:46 +00:00
2b09cbba9e hook up missing x86 SMM into Makefile
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:47:43 +00:00
7833048e1f drop support for various (old) PPC CPUs as per discussion from 9/10/9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:46:08 +00:00
95fca9e8f4 add CPP to xcompile in case we need it (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:38:53 +00:00
105bace68d Some ACPI implementations don't like to see full paths within a scope for
CPU power management, so don't add the scope name

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:36:51 +00:00
dd3e82ab46 Rework the keyboard driver
* use readable macro names rather than numbers.
* Factor out some commonly used code

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:15:07 +00:00
c81a12a748 drop src/include/stream/ as the source files from src/stream were dropped a
while ago...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:02:04 +00:00
c35a4511f7 * refactor x86 smi handler (put all debug stuff in an extra file smiutil.c)
* lock other CPUs in SMI handler while one CPU is handling an SMI. Without
  this various racing scenarios could happen.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 17:59:36 +00:00
311c56420b Trivial regrouping of a calculation to simplify it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 13:40:55 +00:00
ea67d4757b A (hypothetical southbridge) component might provide functionality that is not
available on all boards. Thus, only print a debug level warning instead of an
error.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 13:13:37 +00:00
52fc6b12cb re-order console output functions, add proper prototypes,
drop claim that our files were blatantly copied, because they have been
rewritten a very long time ago.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 13:06:04 +00:00
b53bed1567 Fix USB Debug Device for Intel ICH chipsets
The USB EHCI controller reset is not really needed on ICH, and in fact 
the code bailed out there which is the most stupid thing to do. So just
keep trying.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 13:02:14 +00:00
8f3b8583e2 Fix K8 boards high tables on UMA systems (KT690 for example)
Thanks to Carl-Daniel for pointing this out with some example code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 12:40:52 +00:00
561b6c68c1 s/object-y/obj-y/ in two southbridges, since otherwise kbuild will not pick up the files
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 03:55:24 +00:00
60fc92a42e First attempt to integrate SMM in Kconfig. Unused code so far
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 03:33:44 +00:00
42dc721cdf move all register fram definitions to arch/register.h
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 00:47:07 +00:00
c1e7efa98d Remove left-overs from Winbond southbridge removal (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 23:30:31 +00:00
036c15fe71 Drop dead K8_SCAN_PCI_BUS code. It's a bad idea to scan the PCI busses before
RAM is initialized, and no one does it.  Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 22:53:26 +00:00
c21b5ee584 New revision guide September 2009 3.46
Lets add some more CPUs.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 21:57:42 +00:00
5e1a8d10ba drop a lot of dead code, including an old winbond southbridge from our removed
ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped
the filesystems already to be used with it) (somewhat trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 19:33:52 +00:00
707fad0508 White space and comment fixes for cache_as_ram.inc files so it's easier to spot
differences.  Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 18:22:27 +00:00
35ed0e7ea3 Remove PRINTK_IN_CAR tests from AMD files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 18:19:22 +00:00
87f9514ab7 VGA BIOS can be added independently of having a payload
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-23 12:14:15 +00:00
c8863a234f minimal whitespace fix (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-22 17:02:44 +00:00
26eb33faca trivial: add note that VSA blob belongs into CBFS.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-22 16:59:33 +00:00
99bc4514c2 The LAN chip-set on the Technexion TIM-5690 is enabled by hardware and
does not need any handling in software.

Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-22 02:54:25 +00:00
b8f73ed14d Add CONFIG_VGA_ROM_RUN to HP e-Vectra P2706T to make VGA init work.
Also add pci_rom entries (commented) to targets/hp/e_vectra_p2706t/Config.lb
for the same reason. They have to be uncommented to be used.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-21 00:35:42 +00:00
7b8d4fae8e Add initial support for the HP e-Vectra P2706T.
Boot-tested by Paweł Stawicki <stawel@gmail.com>.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Paweł Stawicki <stawel@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 22:36:34 +00:00
ce491013ac Minimize differences between newconfig and Kconfig for arima/hdama.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 18:11:06 +00:00
bea4cc60ba When I converted an #ifdef to an #if it broke the code because the variable was
always defined, but not 1.  This commit reverts to the old behavior.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 17:13:28 +00:00
c6aadbe3eb Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.
(forgotten in last check in.)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 16:24:23 +00:00
8f74c5878d Remove CONFIG_CPU_AMD_FAM10 & CONFIG_CPU_AMDK8 from mainboards. They should be
selected in sockets, and they aren't used yet.

Add a couple of variables to src/Kconfig for lack of a better place so that
their selects work.
Add select statements according to newconfig for some variables that were
defined but never selected in mainboard configs.

Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 16:10:04 +00:00
4e015eb674 Fix all board names in Kconfig as per wiki / vendor website.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 13:55:35 +00:00
1529576019 Correct typo. Thanks to Mark Marshall for spotting it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 13:40:30 +00:00
5ec971020f Move ITE-specific option to src/superio/ite/Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19 19:08:18 +00:00
5ba7bfe7c4 Add missing SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL kconfig variable.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19 18:55:08 +00:00
42fd936de2 Fix builds of amd/db800 and digitallogic/msm800sev with smaller bootblocks.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19 16:58:51 +00:00
66f03e4b14 Unselect AP_CODE_IN_CAR in tyan/s289x. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19 16:48:32 +00:00
ec0ee64da7 Clean up some #ifdef CONFIG_*
Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-19 16:21:30 +00:00
a29ad5cb09 Add EXPERT kconfig option so we can hide more advanced options
from beginners who should rather not touch them unless they know what
they do.

Also, add a random Kconfig help comment.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 18:35:50 +00:00
7f30050939 Drop a duplicated implementation of failover.c.
Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 18:27:42 +00:00
e405327b46 Simplify Kconfig files by using "select" where possible (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 13:47:30 +00:00
5c57df6c1a Drop dead/unused code (trivial).
DEBUG_SETNORTHB is never defined, and even if it was, setnorthb()
is never called anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 13:42:50 +00:00
2c1bf62d0c Remove this, we no longer need it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 03:15:59 +00:00
d08be7eecd Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 15:01:00 +00:00
0bc615482e Remove CONFIG_ from #defines that aren't config variables. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 13:25:07 +00:00
d7b37b0a67 Silence src/Kconfig:349:warning: config symbol defined without type
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 03:00:04 +00:00
f078be2cb1 Remove some more instances of including previous empty x86/fpu/Makefile.inc
Thanks to Jakob and Uwe for spotting the mistake!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 02:51:26 +00:00
b1924301ca Drop src/cpu/x86/fpu/{Config.lb,Makefile.inc} since they are also empty
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 01:12:42 +00:00
d12b7030c6 Make COM port selection and BAUD rate a "choice" for better usability.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 22:39:55 +00:00
e052bb7a60 Drop duplicate version of the documentation/cbfs.txt file as discussed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 22:07:20 +00:00
5e19eee460 This is a snapshot as the availability of the systems for this
project is now uncertain, and I can't invest the remaining time
needed to get it done. 

Status is that memory is still not quite configured correctly. It is close
but here are DRAM Row Boundary registers. 
Here is coreboot
60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
This is close. But: 
60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
is the real hardware. So we are somehow missing those last slots. I think it's 
because the SPD connections and the chip connections differ, some dumping
of RAM registers differ. But it's very close. 

This is under serialice. Once we get to this point we get stuck here: 
Copying coreboot to RAM.
Copying coreboot to RAM.
Copying coreboot to RAM.

Forever. 

Here is the total config for 0:0.0 from coreboot: 
PCI: 00:00.00
00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c
80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00
90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07
a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0
d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00
f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00

And from factory: 
00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09)
00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10
60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c
80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00
90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07
a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00
c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0
d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00
f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00

I want to commit this because even if I get no further, someone else might. 
Note that for serialice you need the following temporary patch as well: 
Index: src/superio/nsc/pc8374/pc8374_early_init.c
===================================================================
--- src/superio/nsc/pc8374/pc8374_early_init.c	(revision 4791)
+++ src/superio/nsc/pc8374/pc8374_early_init.c	(working copy)
@@ -29,7 +29,8 @@
 static void pc8374_enable_dev(device_t dev, unsigned iobase)
 {
 	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
+/* don't disable for now, it kills serialice */
+	pnp_set_enable(dev, 1);

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 22:07:15 +00:00
3ff6358f8e Revert deletion that snuck in to 4794. Sorry.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 20:15:06 +00:00
0364618fe8 Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8.
Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 19:29:45 +00:00
04000f4642 Fix AP_CODE_IN_CAR (only selected for two boards), STACK_SIZE, and HEAP_SIZE.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 19:12:49 +00:00
2c54f90280 Drop empty cpu/x86/{mmx,sse}/{Config.lb,Makefile.inc} and remove references
Files in those directories are still used, but always with explicit path.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 18:27:13 +00:00
777e069c5a Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"
abuild tested

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 17:43:46 +00:00
d65509de14 Set default ROM sizes per-board to match the ROM chip that came
with the respective board.

Of course, the user can still override the size in menuconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 17:37:20 +00:00
04b9b92952 Drop unused and useless CONFIG_MAX_PCI_BUSES.
It was added by rsmith in r2273 on 20060424, when pci_locate_device() in
src/arch/i386/include/arch/romcc_io.h in fact scanned all busses:

 - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
 + for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) {

Today this looks like:

   for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {

and CONFIG_MAX_PCI_BUSES is never used anywhere.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 16:39:40 +00:00
0f61a4fc98 Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 16:32:57 +00:00
9969bdc4fb Fix IRQ9 and allow ACPI without an MP table for Tyan s289x.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 14:34:50 +00:00
025b8a3877 Fix kconfig setup for the VIA pc2500e.
Add/drop Kconfig variables as needed.
In Makefile.inc just include Makefile.romccboard.inc with -mcpu=c3.

Build- and runtime-tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 13:34:32 +00:00
776260675a Similar to r4626, change obj-y to driver-y for VIA C3 and C7.
Otherwise the following happens at runtime (tested on VIA pc2500e, C7):

  Initializing CPU #0
  CPU: vendor Centaur device 6a9
  CPU: family 06, model 0a, stepping 09
  Unknown cpu

We also change C3 as it is pretty clear that the same problem occurs there.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 10:06:18 +00:00
709a71a3b6 Drop duplicate CPU subdirs-y entries for "../../x86/mtrr".
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 10:03:50 +00:00
289a2f5aad Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the
VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom   pci1002,791f.rom  optionrom
to make the final image with vga bios.

The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.

##    Index: src/southbridge/amd/rs690/chip.h
##    ===================================================================
##    --- src/southbridge/amd/rs690/chip.h	(revision 4782)
##    +++ src/southbridge/amd/rs690/chip.h	(working copy)
##    @@ -23,7 +23,6 @@
##     /* Member variables are defined in Config.lb. */
##     struct southbridge_amd_rs690_config
##     {
##    -	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
##     	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
##     	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
##     	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */
##

Don't apply above patch about rs690/chip.h before every board has been fixed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 07:44:04 +00:00
9d37532bc1 this is probably in vain because this tool should use the same x86emu as
coreboot in order to produce comparable results. But, this patch drops the 
CONFIG_ from CONFIG_DEBUG because that was added by accident when we
automatically renamed coreboot variables to be consistent. "vgabios" is an
independent userspace utility, and it does not use newconfig nor Kconfig, so
it should not be converted. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 01:08:07 +00:00
61c7fbfd5e undo another accidential rename of X -> CONFIG_X (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 22:40:41 +00:00
6ba13bbf7c Start documenting a few kconfig variables and user-visible options.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 17:49:07 +00:00
3e08cb72ff Fix Kconfig for technexion/tim5690.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 14:23:33 +00:00
b8e2027be8 Add CONFIG_GENERATE_* for tables so that the user can select which tables not
to build, but by default all the tables that are available are built.

Make PIRQ table build for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 13:35:47 +00:00
45b811b135 Add Kconfig support for kontron/kt960.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 13:16:40 +00:00
74cb9eb7e7 cbfs_and_run_core() did not check the return code of cbfs_load_stage()
and jumped to (void*)-1 on error.
Die properly instead.
I didn't use die() because that caused a linker error.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 23:51:05 +00:00
75472d27e4 Fix high tables address calculation on cn700 with VIDEO_MB > 0.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 20:49:49 +00:00
9a04f17af0 Add forgotten target files for technexion/tim5690.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 03:19:33 +00:00
59b2dc2cf2 White space and typo fixes. This makes it easier to compare the s2895 & s2892.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 03:09:26 +00:00
cb69cb3e69 delete white trailing spaces. It is done by the perl command.
sh> perl -pi -e 's/[[:blank:]]+$//' $files
Trivial.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by:  Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 02:56:00 +00:00
b0575d8e1f Use CAR ck804 code with the s2892.
Reset the s2891 so the HT speed gets updated.
Remove some PANTA comments.
Add SATA init from non-CAR version.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14 02:38:24 +00:00
21ee98bf79 White space change in preparation for a patch to unify handling of ck804.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 22:53:24 +00:00
fbc11edd7a Revert some garbage that snuck into my trivial change, correct a spelling error.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 20:20:55 +00:00
54913b98e5 Remove a couple more warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 20:00:09 +00:00
95aa53a5c3 Add support for the MSI MS-6156 board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 19:21:44 +00:00
6bbe74c639 Fix kontron/kt690 build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 17:56:11 +00:00
7d3649a605 This patch support for the Technexion Tim-5690 mainboard.
It's an embedded AMD RS690/SB600 mainboard.

http://www.technexion.com/index.php/tim-5690

Myles added Kconfig support.

Signed-off-by: Libra Li <libra.li@technexion.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 16:56:58 +00:00
c270e896f0 This patch adds (initial) support for the Kontron KT690 mainboard.
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU.

Issues with this port:
- hangs early during "Starting Windows" with Windows 7, after loading all the
  drivers
- sound is untested and probably not working  
- powernow seems to be not working  

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 16:47:57 +00:00
45cbc35abb Fix obvious typos (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13 11:45:04 +00:00
3db199c00a Make fam10 build (but not boot due to bootblock size problems.)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-12 22:39:08 +00:00
b106f9bdbd Add the compareboard utility which is useful for porting
to kconfig.
Hook it up to kbuildall, too

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-12 18:43:26 +00:00
4d7ec68856 Remove useless udelay() duplication.
Abuild-tested for the boards that are touched.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 18:21:45 +00:00
c0528d61df HAVE_ACPI_TABLES cleanups for kconfig:
- Add "select HAVE_ACPI_TABLES" for boards which need it.

 - Drop sections which set HAVE_ACPI_TABLES to 'n', that's the default.

 - Convert sections which set HAVE_ACPI_TABLES to 'y' to the
   shorter "select HAVE_ACPI_TABLES".

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 17:40:44 +00:00
7fe4191fff Make console maximum/default log level a choice option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-11 13:35:24 +00:00
fcb28b66ce Drop "select CONSOLE_SERIAL8250" from QEMU, it's default-y anyway.
Tested on QEMU.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-10 16:19:12 +00:00
3fe6b7002b Add const to get rid of some warnings when passing quoted strings.
Remove an unused extern declaration.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 20:13:43 +00:00
42584096c3 This change allows us to see the spd on the s850, finally.
There is an i2c mux out there. We found it using a user level program 
that, as usual, began by inverting all gpios until we found out 
what we needed to know. In the end, we just set up the GPIOs as 
the factory bios does. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 20:07:48 +00:00
517bb208dc Remove extra CONFIG variables.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 17:40:34 +00:00
e7bbb50ba0 Remove default n statements to simplify .config and ldoptions files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 17:39:35 +00:00
86bf6795c3 Move the ulzma prototype out of the function to make the code easier to read.
Check the return value.  Minor formatting and LAR -> CBFS.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 15:22:35 +00:00
00f0267f78 Remaining boards are Kconfig'd now. Whether they work
or not still depends on how close the configuration
options are to what they should be.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 14:10:28 +00:00
91ff0df627 More Kconfig-supported boards, and also kconfig support
for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 12:32:52 +00:00
748475b800 More kconfig cleanups:
- Use "default n" for all components that shall be "select"ed.

 - Use "0x0" instead of "0" for hex variables for clarity and to reduce
   the risk of people passing integer instead of hex values to such variables.

 - Add TODO comments for boards that have irq_tables.c but don' set
   CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling.

 - ASUS M2V-MX SE doesn't have irq_tables.c so don't define
   IRQ_SLOT_COUNT in its Kconfig file.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 11:47:21 +00:00
ebb43d6943 Fix CS5535 build for kconfig, more kconfig boards (lippert, artec)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 20:17:14 +00:00
e3fcd45a7f Simplify targets/amd/serengeti_cheetah/Config.lb. There were too many
variables being set incorrectly.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 18:50:16 +00:00
ea1522b016 This dialogue on email was useful and hence included.
failover.inc MUST come after enable_sse or your CPU will hang.

> Can you say why?

yes. if you compile failover.c with romcc options that include sse, 
then you'll see code like this in failover.inc:
mov eax, %xmm0

This will hang if you have not first enabled sse. 
Verified yesterday on the dell s1850. 

>
> Does it hang in the SSE code or in the failover code?

It will hang in failover code, if that code was compiled with sse enabled
AND if the sse registers are used. 

>
> Does this mean that failover requires SSE in order to work?

It may or it may not. 
But if you compile it with romcc options that include sse, 
and it uses sse without sse being enabled, it will hang. 
This is a particularly nasty bug in that the failover code is not 
guaranteed to compile in a way that sse is used, even if sse is 
enabled; hence, this could be very hard to catch. 
I'm lucky this bug appeared as soon as it did.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 17:10:20 +00:00
cc2b9f2abe Set MMX and SSE where needed. Note that many boards don't even bother
with this as many boards (AMD in particular) use CAR.

This list determined by a series of greps etc. on mainboards, no humans
were harmed in the making of this list.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 16:06:09 +00:00
0523875e09 Disable x86emu for via based boards which bring
their own vgabios.c

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 15:12:31 +00:00
98402455c5 More kconfig:
AMD LX
AMD SC520
boards by iei, pcengines, technexion, technologic, thomson

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 14:31:56 +00:00
824fce488b Oops, wrong type for Kconfig value. Trivial fix
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 10:19:20 +00:00
5726f92027 Kconfig: AMD Fam10, all Tyan boards.
Fam10 doesn't build due to size constraints at this time.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 07:43:09 +00:00
b97ee05dc7 Emergency fix. Failover.inc can end up with code that uses sse. It has
to be run AFTER SSE is set up. I just had this problem cause a failure 
today.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 22:53:30 +00:00
95313d824d Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boards
and PIRQ tables were actually wrong, I cannot imagine they ever
worked properly.

 - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
   hard-coded numbers.

 - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.

 - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
   in the irq_tables.c file.

 - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
   boards where they were set to 0 (in order to be overridden in
   the respective targets/.../Config.lb).

   This is mainly done to aid Patrick's scripts for kconfig conversion.

 - Fix a number of comments in irq_tables.c files.

 - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
    - tyan/s1846
    - asus/a8v-e_se
    - asus/m2v-mx_se

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 21:51:33 +00:00
17aeecab89 Kconfig allows you to run all PCI ROMs, VGA only, or non-VGA only.
Update the code to support that too.

Remove an unused variable.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:41:08 +00:00
877119a995 Fix trivial typo in Kconfig spotted by Peter, introduced by me.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:07:49 +00:00
7b6a0a84be Get rid of early_serial, it is now a generic function in early_init.
Add some more enables to the s1850. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:03:41 +00:00
869bbc4616 Convert all "default y" options to "select FOO" (shorter).
Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're
global options in kconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 16:29:12 +00:00
168b11bc41 Various Kconfig fixes and improvements:
- Add helps texts to multiple user-visible Kconfig options.

 - Improve some menu and option names.

 - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down
   (instead of up) when changing "no payload" to "ELF payload" (more
   intuitive, IMHO).

 - s/cbfs/cbfstool/.

 - Add some TODO items where needed.

 - Put GDB_STUB in a "Debugging" menu, no options should be top-level.
   There'll be more debug options later, I'm pretty sure.

 - Start converting help texts which are not user-visible to #-comments.

 - Re-order some options for more intuitive menus.

 - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them.

 - "Maximum reboot count" should proabably not be user-selectable, or at
   most if CONFIG_EXPERT (yet to be added) is enabled. It does definately
   not need its own "Misc options" menu.

 - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to
   run option ROMs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 16:15:40 +00:00
dd56514502 Fix intel board build on kconfig. MAX_CPUS was missing
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 16:00:40 +00:00
66b74047d6 Kconfig:
- Add AMD Socket 754,
- Fix MCP55 boards (romstrap)
- Implement remaining MSI boards

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 15:30:58 +00:00
31f81a6de1 Enable full ROM access on AMD CS5530(A) (needed for CBFS).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 14:36:16 +00:00
fdfaada706 More boards in kconfig, and moved -O2 flag for romcc into
ROMCCFLAGS, so boards can override it where necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 14:13:36 +00:00
99950c2192 Use
select UDELAY_TSC
  select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
for all 440BX and i810 boards as per Options.lb.

The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked
and improved later when the kconfig transition is done. For now
we keep the same values as in Options.lb.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 22:25:21 +00:00
0e9a92545d Various fixes to Kconfig: All kconfig-boards should have a
complete set of variables now, though they might still have
the wrong values.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 20:48:07 +00:00
a3d6ea8a73 Remove duplicate device trees for Tyan s289x. Remove pre-CBFS statements.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 20:36:34 +00:00
c04be9322c Backport facility to specify a local coreboot version suffix from v3.
Tested on QEMU.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 13:55:28 +00:00
ba6a93ddcb Remove svn:externals that pull in all kinds of useful tools that
are not needed for building coreboot.

The website tells you where to get them individually.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 12:58:48 +00:00
652cd810f0 Without these fixes the w83627dhg driver (which is currently not used by any
mainboard in the tree) does neither compile nor work.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 12:08:37 +00:00
84d69f78df fix building on Linux again, working around crude runtime OS detection.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 10:23:36 +00:00
b24e276503 PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig and
should not be set in per-mainboard Kconfigs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 00:07:12 +00:00
90950925c7 The new CBFS based build system requires the whole ROM to be accessible
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:

  Uncompressing coreboot to RAM.
  Jumping to image.
  Check CBFS header at fffedfe0
  magic is ffffffff
  ERROR: No valid CBFS header found!
  CBFS:  Could not find file fallback/coreboot_ram
  Jumping to image.

This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).

Build-tested and runtime-tested on ASUS P2B-F.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 23:50:06 +00:00
24796fd364 This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.

Various calculations in {no,}failovercalculation.lb are adapted
accordingly.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 18:55:40 +00:00
70b0cf23ce Add initial kconfig support for all AMD GX1 boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 17:15:39 +00:00
5bb10282e9 This removes the uses of the buildrom utility and the coreboot.strip
intermediate file.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 12:30:44 +00:00
0dd713330b Remove a bit of pre-cbfs build system infrastructure.
Payloads are compressed by cbfstool itself, no need for external tools.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 12:27:48 +00:00
3c2d874958 Remove another FAILOVER variable. (trivial)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 21:13:36 +00:00
f9ef2081ba Add gigabyte/m57sli support to Kconfig.
Whitespace fixes to devicetree.cb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 21:06:53 +00:00
37ea341079 Move HAVE_FAILOVER_BOOT and USE_FAILOVER_IMAGE from
boards to global. It's not a per-board value, but
compatibility stuff.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 21:04:13 +00:00
689a720485 Tell vgabios code in a couple of boards/chipsets about CBFS
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 16:27:48 +00:00
6768f39a4b Remove:
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)

After this commit, there is no way to build an image that is not using
CBFS anymore.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 16:24:58 +00:00
8f3ec7b1a3 Remove duplicate and not too useful Kconfig board comments as
per discussion on the mailing list.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 15:34:08 +00:00
1c53d771c1 Remove the Embedded Planet board.
Signed-off-by: Ronald G. Minnich <rminich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02 15:46:10 +00:00
6cc9c0ad28 Remove left-over targets/motorola/*, fix Dell PowerEdge 1850 name.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02 12:45:18 +00:00
4703bf1619 Remove motorola PPC boards. These have lain untouched and unused by anyone
for years. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02 03:36:30 +00:00
5bf864e353 Drop remainders of the removed Totalimpact board. Fix typos.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02 00:08:00 +00:00
149d6754aa Support variables for MMX and SSE. These would be used in
e.g. Makefile.romcc.inc to enable certain features.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 23:22:50 +00:00
4c5786b1f9 Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts
Sorry, but I've forgotten where I found them. :\

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 22:34:18 +00:00
9536c06d18 Add romstrap to asus/m2v-mx_se in Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 18:23:28 +00:00
1df483d3a1 Get rid of the total impact. Vendor died 5 years ago and nobody cares.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 16:51:36 +00:00
20d5c2e14e Fix Kconfig build for K8 boards.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 16:24:58 +00:00
e3de8b7cb5 OK, this builds and even looks right. dell needs its own Makefile.inc because
it is a P4 and it needs SSE for romcc not to go into infinite loop. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 15:59:49 +00:00
8a7ffd8dec typo
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 15:47:14 +00:00
e14f58343b We need this to be Kconfig. The old way is not trusted by me.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 15:41:39 +00:00
61d66db14d This is now set up more like the real hardware likes it.
Some of this trickery was determined with serialice. 
There are several lovely undocumented features to the chipset. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 00:02:28 +00:00
26dd71c2d7 Fix payload loading in various corner cases when working
with the bounce buffer.
In particular, the not-so-rare configuration of AMD boards with RAMBASE at
2MB shouldn't crash anymore for payloads that take > 1MB in total

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 21:36:38 +00:00
aeab4fcca0 Compress stage if CONFIG_COMPRESS is activated, instead of
relying on payload compression configuration (disabled when
using abuild without payload, for example)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 19:54:15 +00:00
e23e37202c Hm, quickfix to prevent the following crash, no idea yet what happens:
*** glibc detected *** ././inteltool: double free or corruption (top): 0x08db0260 ***

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 17:14:24 +00:00
90d17407d8 Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 17:05:46 +00:00
2583dd2095 Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912
fam10 and h8dmr k8 targets.

Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
this, and to Arne for doing the s2912 fam10 port.

Build and boot tested. Abuild tested.

There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 14:46:43 +00:00
56f5fb734b Fix endless loop when trying to add a too large file to CBFS,
and report the correct error code, and a hopefully helpful
error message.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30 11:21:18 +00:00
53ad9f585d Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 21:35:48 +00:00
babb03a5be Remove pre-CBFS _vgabios_start and _vgabios_end.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 20:24:09 +00:00
e59f2e1f33 A keyboard controller fix to stop the code from waiting for a code that never
comes.  Boot tested on SimNOW (fixes the hang there), and Tyan s2895.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 19:12:23 +00:00
120bff83ff Fix a number of board names in Kconfig (trivial).
Also, simplify the M2V-MX SE Kconfig file a bit while I'm at it.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 18:15:06 +00:00
6842c0293c Remove MAINBOARD_OPTIONS, which is a relic from early
kconfig development.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 17:28:13 +00:00
6e2357676f Remove some warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 14:56:15 +00:00
5e54871375 More consistent use of "default n" and "select XYZ" in
Kconfig files


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 14:38:10 +00:00
2f2e435cc6 Make the error messages somewhat less incomprehensible. I forget
what they mean every time I see them. 

Add a proto. More work remains to be done.

Build tested on dell s1850. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 13:34:56 +00:00
cd75b1d4fb Trivial config fix for Serengeti Cheetah. Change a type and a default.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-28 22:36:40 +00:00
d05cc40390 Trivial config fix for Serengeti Cheetah. Remove duplication, add a default.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-28 21:51:39 +00:00
074d9136d7 This adds a simple script to build a default toolchain for coreboot
compilation, to be independent of broken or missing OS/distribution
tool chains.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-26 16:43:17 +00:00
bde683ce9f This patch changes following in getpir application.
1 - Moved the check sum validation to probe_table function.
2 - Proper handling of resources allocated.
3 - Signature check is done in 16 byte boundaries.
4 - irq_tables.c file is created only if a valid PIRQ table is found.
5 – Makefile and README file are modified accordingly.

Signed-off-by: Mohamed Mansoor <mansoor@iwavesystems.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-26 16:18:22 +00:00
5db685fedf * drop libgcc from coreboot_apc.o, not needed.
* wrap libgcc calls into regparm(0) variants so that coreboot can be compiled
  with other regparm values

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-26 15:52:05 +00:00
19a99c6965 check for ELF payloads in cbfstool
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 22:21:47 +00:00
6bd571e060 drop some dead code, clarify small comments and small cleanups to malloc.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 21:59:57 +00:00
0a181fd642 improve lzma error messages. When coreboot panics because lzma decompression
goes wrong, it might not be clear that it's lzma that failed, if the log level
is low enough..

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 21:57:25 +00:00
45847beb49 Trivial fixups to get this board further along.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 19:53:59 +00:00
03bdc3e070 Fix build of romcc boards.
Invalid option specified: -mcpu=-mcpu=p2
romcc 0.71 released 03 April 2009

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 19:09:23 +00:00
88f55b2c12 some progress on kconfig:
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
  the socket it has, and the CPUs are pulled in automatically. There is
  some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
  - intel/eagleheights
  - intel/jarrell
  - intel/mtarvon
  - intel/truxton
  - intel/xe7501devkit
  - sunw/ultra40
  - supermicro/h8dme
  - tyan/s2850
  - tyan/s2875
  - via/epia
  - via/epia-cn
  - via/epia-m
  - via/epia-m700
  - via/epia-n
  - via/pc2500e
(PPC not considered, probably overlooked something)

All of them only _build_, but some options are probably completely
wrong. To be fixed later

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 18:43:02 +00:00
6bb3bdf869 Rename CONFIG_SERIAL_CONSOLE to match newconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 17:24:08 +00:00
a21cc3d33e Make build_opt_tbl depend on config.h since it uses it. This fixes:
GEN        build/build.h
    OPTION     option_table.h
Error - Range end (122) does not match define (125) in line
checksum 392 983 984

This happens when you switch from one board to another with incompatible CMOS
defines.  'make clean' didn't help.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 16:56:08 +00:00
74fb8f224f Remove HyperTransport support from boards that don't need it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 15:09:11 +00:00
f0cfb22970 Re-enable option table for the ASUS MEW-VM and fix build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 14:05:19 +00:00
a57a0ac53e Add detection support for the SMSC FDC37M602.
The ID was found on a Biostar M6TLD board (not mentioned in the
FDC37M60x datasheet, though).

Thanks Maciej Pijanka <maciej.pijanka@gmail.com> for the report.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 12:17:07 +00:00
cdceab8fac Trivial fix for kbuildall: initialize "i", not CURRENTARGET [sic]
that isn't used anywhere.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 09:28:41 +00:00
892b091e96 Make all Kconfig enabled boards build (tested with kbuildall).
Also enable building individual boards with kbuildall for
debugging.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 09:03:06 +00:00
ac7a2d2f84 fix some wrong occurences of the FSF's address (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 21:53:25 +00:00
6c641ee035 fix some wrong versions of the FSF's address (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 21:52:45 +00:00
920279842d Fix the bounce_size global so that the bounce buffer works with CBFS.
Make self_boot() static.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 20:32:21 +00:00
f250f191f8 Looks like this should have become cpu init code after growing up. The
remaining questions are:

- Why was it never used?
- Why is it in /src and not in /src/cpu/ppc?

Given this is dead code and part of an unmaintained powerpc port, I consider
removing it trivial. (The code really does not do much)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 18:54:18 +00:00
c13093b148 simplify source tree hierarchy: move files from sdram/ and ram/ to lib/
It's only three files. Also fix up all the paths (Gotta love included C files)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 18:51:03 +00:00
a946214ea0 Add Kconfig support for Tyan s2881.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 17:59:56 +00:00
422d0cb712 Separate payload compression from stage compression.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 17:48:28 +00:00
d6ac964c89 Fix compilation for serengeti when HAVE_ACPI_TABLES is set. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 22:08:47 +00:00
ed03556fbf src/Kconfig: Remove HT-specific options.
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.


Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 21:29:32 +00:00
a74ae635ca failoverR.diff: Revert my failover change since Kconfig only supports fallback.
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 18:53:50 +00:00
45bb25f36f tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ...
Kconfig_bools.diff: Change some more ints to bools, change some default values.
xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB.
smp.diff: set CONFIG_SMP based on MAX_CPUS.


Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 18:49:08 +00:00
3fec29cc96 This separates the code for each command in cbfstool. For the good and for the
bad: It brings a certain amount of code duplication (some of which can be
cleaned up again, or get rid of by proper refactoring).
On the other hand now there's a very simple code flow for each command, rather
than for each operation. ie.

adding a file to a cbfs means:
 - open the cbfs
 - add the file
 - close the cbfs

rather than

open the cbfs:
 - do this for add, remove, but not for create

create a new lar
 - if we don't have an open one yet

add a file:
 - if we didn't bail out before

close the file:
 - if we didn't bail out before


The short term benefit is that this fixes a problem where cbfstool was trying
to add a file if you gave a non-existing command because it bailed out on
known, not on unknown commands.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 15:58:19 +00:00
853270af39 * guard all mallocs in cbfstool
* fix an issue that could lead to cbfstool writing outside of its allocated
  memory 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 15:55:01 +00:00
0e0655e6ef .. make abuild Kconfig proof for the time being.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 15:53:54 +00:00
dbdd91bc5b back out some overzealous renames
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 15:53:02 +00:00
7cf8c58618 Kill dead comment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 12:31:57 +00:00
93c027279f Help text for maximum and default console loglevel in Kconfig.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 12:22:35 +00:00
a4d4770a3e r4534 introduced devicetree.cb in every mainboard directory, but didn't
copy any comment lines before the start of the device tree.
Fix up amd/pistachio and technexion/tim8960.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 10:03:15 +00:00
513e03bd96 r4646 enabled early usage of pci_{read,write}_config{8,16,32}
This allows us to change
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
        sm_dev->path.pci.devfn, 0x64);

to the much more readable
dword = pci_read_config32(sm_dev, 0x64);

Clean up all PCI operations in mainboards based on AMD 690:
amd/pistachio
amd/dbm690t
technexion/tim8690

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 09:43:25 +00:00
00003ae712 If no pci access method has been set for the device tree so far (e.g.
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die().
This patch changes pci_{read,write}_config{8,16,32} to use the existing
PCI access method autodetection infrastructure instead of die()ing.

Until r4340, any usage of pci_{read,write}_config{8,16,32} in
coreboot_ram before the device tree was set up resulted in either a
silent hang or a NULL pointer dereference. I changed the code in r4340
to die() properly with a loud error message. That still was not perfect,
but at least it allowed people to see why their new ports died.
Still, die() is not something developers like to see, and thus a patch
to automatically pick a sensible default instead of dying was created.
Of course, handling PCI access method selection automatically for
fallback purposes has certain limitations before the device tree is set
up. We only check if conf1 works and use conf2 as fallback. No further
tests are done.

This patch enables cleanups and readability improvements in early
coreboot_ram code:
Without this patch:
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
        sm_dev->path.pci.devfn, 0x64);
With this patch:
dword = pci_read_config32(sm_dev, 0x64);

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 00:09:41 +00:00
6afb698433 I forgot to add CONFIG_VGA_BRIDGE_SETUP to the old build system.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 18:30:23 +00:00
079300b987 Remove warnings from Kconfig. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 16:59:07 +00:00
28412f58b6 Separate CONFIG_VGA_CONSOLE from CONFIG_VGA_BRIDGE_SETUP.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 16:54:46 +00:00
a758ca2ba9 Move VGA BIOS settings from the payload menu into it's own menu
Remove dependency on PAYLOAD_ELF so that config items are shown.
Build tested. With this, coreboot.rom has a VGA BIOS optionrom added.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 16:21:31 +00:00
5a1af7b877 There was a missing addition of the size of the .notes.pinfo
section header which could lead to corrupted malloc arena. 

Also, make cbfstool always build with debugging on. Performance
is not an issue here. Don't strip it either. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 15:35:08 +00:00
b796a06cc6 This is a patch for killing IPMI on the s1850 -- or at least geting the BMC
out of the way of the serial port. Tested extensively in user mode.
Works and gets the BMC out of my way, which is good, because there
are few more useless things than IPMI and the BMC.
The BMC, all by itself, is the cause of most of our problems in booting
and talking to these nodes. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 00:28:29 +00:00
3f76a56795 copyright name error.
I don't know what else to do for files generated by programs ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 00:24:52 +00:00
8e9910e5c9 kbuildall is a utility that generates default configs for all
boards, builds them, and keeps the config and build logs around and
creates a roster of all boards and their build status.

abuild does this for the newconfig based buildsystem, kbuildall does
this for kconfig/kbuild.

It's supposed to be put in the tree as util/kbuildall/kbuildall, and
called like that (ie. from the top level directory).

The results can be found in kbuildall.results/ in the toplevel
directory, the roster is called _overview.txt ("_" to make sure it's
sorted before or after all the board files)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-16 20:18:03 +00:00
ab13458c34 Build cbfstool with debug flags and don't strip the executable
from any symbol information.

Variant of Ron's patch.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-16 08:19:07 +00:00
057712a3b7 This is an otherwise dead platform. I'm just committing the basics that
let it build. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-15 23:38:27 +00:00
b261205f5e Don't mix int and boolean for kconfig variables. It might work, it might not.
trivial change.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-15 20:40:31 +00:00
45d8a83b29 More error checking when trying to open files in
cbfstool. (trivial)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-15 08:21:46 +00:00
fd9c9b8ff8 Use the coreboot pci config read/write functions instead of direct cf8/cfc
access. The fam10 pci functions will use mmio and do not have SMP pci access
issues.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-14 17:00:04 +00:00
fea8a4f8d3 In the mainboard selection, the selected mainboard is printed twice in
certain cases, this patch eliminates the second mention.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-14 14:15:43 +00:00
77ee932a22 Build cbfstool with native data size. Trivial change.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-14 14:13:13 +00:00
b7b56dd8fb New cbfstool. Works without mmap or fork/exec and
supports fixed location files. Some parts are salvaged
from the pre-commit version (esp. stage and payload creation),
others are completely rewritten (eg. the main loop that handles
file addition)

Also adapt newconfig (we don't need cbfs/tools anymore) and fix
some minor issues in the cbfstool-README.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-14 13:29:27 +00:00
c8d4a05f8f fix compilation issues for pirq checker tool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-10 11:21:48 +00:00
8008f88df8 Fix clean rules for the tex files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-04 19:34:43 +00:00
105c155a0c Fix various build issues and errors in LinuxBIOS-AMD64.tex.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-04 19:25:51 +00:00
6dd5223b07 Use driver-y instead of obj-y for model_6xx_init.o.
Otherwise booting (but not building) fails:

  Initializing CPU #0
  CPU: vendor Intel device 665
  CPU: family 06, model 06, stepping 05
  Unknown cpu

This patch was tested to fix the issue on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-04 16:30:31 +00:00
eed10364ce As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to
write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2
for FDX)

The default was 266MB/s but half duplex only. If you encourage any stability
issues we need to look into fine tuning the bus. The values are VIA recommended.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 15:29:12 +00:00
37f3935029 port msrtool to darwin.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>

with minor changes to allow 32bit and 64bit compilation and (I hope), Peter's
concerns addressed.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 10:03:01 +00:00
e95eb616cc * Add OSX/Darwin support
* Add DESTDIR support

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 09:57:55 +00:00
4db6cbd26c nvramtool:
* Add OSX/Darwin support
* Add $DESTDIR support
* Clean up make install/spec

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 09:54:21 +00:00
f7f2f258d8 Clean up Mac OS X support of inteltool
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>

Some minor modifications to allow 64bit/32bit compilation on Darwin



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 09:52:14 +00:00
b2aedb1a3f add i810 and ich0
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 15:45:43 +00:00
669c4a954e File I missed committing.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 03:00:51 +00:00
6ed39d9786 This is the final set of changes to allow rumba to build. Rumba is not
tested. I also addressed questions raised by Uwe: 
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
UDELAY_TSC

Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in 
the mainboard Kconfig. The remaining question of Uwe's is a deeper 
problem:

---
We'll have to check if this works. From a quick glance
the Rumba does not have the mmx related lines (which _are_ in
Makefile.romccboard.inc, though):

crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
---

We're going to need a whole variant of this standard mainboard OR
we're going to have to make (some) of the unconditional includes above 
conditional. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 02:59:35 +00:00
e7f5709e14 Set the mainboard/amd directory up to support more than one.
remove Config variables now defined elsewhere.
add rumba Kconfig and Makefile.inc

rumba won't build until my earlier patches are acked.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 02:47:57 +00:00
ea47143f15 Fixes per Uwe's comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 02:44:08 +00:00
5b1d51ba2e This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board.
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.

Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 20:42:21 +00:00
8b1c382cc0 r4534 introduced devicetree.cb in every mainboard directory, but didn't
copy any comment lines before the start of the device tree.
Copy over the comments for amd/dbm690t.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 19:00:59 +00:00
84a0f54b3b Add kconfig support for all Intel 82810 (i810) boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:38:42 +00:00
177aa3ad79 kconfig: Board name variable fixes and updates (trivial).
- Use alphabetical order.
 - Drop non-exisiting vendors.
 - Add missing vendors (Mitac, Soyo, Technologic, TeleVideo).
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 15:22:31 +00:00
07b8c2d26b This is the beginning of support for Geode and Kconfig in v2.
It also brings in the vsm from v3, which was a much cleaner cut. 

Over time, I hope to bring all the code back from v3. I have 
some rumbas at home and want to use them.

I have a patch which comes in next that makes the rumba build. 

Note that I am holding the src/*/amd/Kconfig patch until these get merged.
These have no impact on the current system. 

Note that this is not complete but I want to fill in the blanks bit 
by bit. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 14:46:59 +00:00
0d5ced0e23 Move DCACHE support into the cpu family for AMD model_fxx.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 14:40:04 +00:00
e6804955c4 Add Kconfig support for PCI option ROMS.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 14:36:12 +00:00
876d7e9658 Move some config variables that are in one or two mainboards to
more rational places. The goal is to reduce the number of Config 
variables defined in mainboard Kconfig files to the absolute minimum. 

This has the side effect of making SERIAL_POST a menu item, which is nice. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 14:23:38 +00:00
05c1e9c81c Silence unneeded #warnings, change to code comments (trіvial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 13:42:24 +00:00
18c585b78a The resource allocator complained about 0-sized fixed
resources before actually validating if the resource is
a fixed one.

No harm done, except some confusion of the user (in this case: me).

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 12:48:02 +00:00
d5f9f0024d Fix broken compilation. As CBFS is now enabled by default,
CONFIG_FALLBACK_SIZE should be equal to CONFIG_ROM_IMAGE_SIZE and not
CONFIG_ROM_SIZE

Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 10:17:03 +00:00
fa1eddac43 Correct typos /SMCSC/SMSC/ in Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 22:41:56 +00:00
dc23c95d2f For Carl-Daniel: make x86emu silent again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 22:36:13 +00:00
7ec3f67294 Added support for the AMD S1G1 socket in kconfig
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 22:19:23 +00:00
ea906b0e4e Added support for the AMD RS690 and SB600 southbridges in Kconfig
Signed-off-by: Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 21:39:20 +00:00
d30722d445 Change some more image names to "fallback" (not "image").
Also, if there's only one image, it should be named "fallback", not "normal".

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 14:22:56 +00:00
2447a9071b Revert test for pre-commit hook functionality. Commits are now checked for proper
sign off again. This is trivial, of course.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 13:14:09 +00:00
192135007d test
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 13:07:40 +00:00
66b9abc5db Another trivial patch to fix up the x86emu cleanup.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 13:02:28 +00:00
39ec29c47e Clean up some DCACHE related options.
In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a
boolean value, so make it so.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 12:10:50 +00:00
20c03fb923 Clean up the kontron Kconfig
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 12:10:05 +00:00
6c36305cdf coreboot was still using an old set (obsolete since yabel) of x86emu includes
instead of the versions in util/x86emu. Clean up this mess.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 11:34:09 +00:00
b883d4c433 Make all those locally used functions static instead of exporting them. (triv)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 11:23:06 +00:00
98457a5f3c Rename "image" image to "fallback", so CBFS can find it.
Thanks to Carl-Daniel for finding this.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 07:42:45 +00:00
5a5b8f5ba9 The new resource allocator helped me find a bug in SB600 diagnostics.
The SB600 SATA code printed that two BARs had the same address because
it didn't mask the correct number of bits in the BAR.
Functionality was not affected, but the debug output was incorrect.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 04:30:47 +00:00
0d0ede5f13 amd/pistachio: fallback image must be called fallback.
Thanks to Stefan for providing the original fix for amd/dbm690t

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 02:47:35 +00:00
932b8fad72 fallback image must be called fallback.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 01:47:41 +00:00
62b3513d63 Remove a couple of CONFIG_ prefixes that shouldn't have happened.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 18:14:30 +00:00
bca3b92df2 Add kconfig support for all missing Intel 440BX based boards.
This includes:

soyo/sy-6ba-plus-iii
a-trend/atc-6240
a-trend/atc-6220
gigabyte/ga-6bxc
biostar/m6tba
azza/pt-6ibd
tyan/s1846
abit/be6-ii_v2_0
compaq/deskpro_en_sff_p600msi/ms6119
msi/ms6147
asus/p2b
asus/p2b-d
asus/p2b-ds
asus/p3b-f

The Makefile.inc for all of them are _exactly_ the same, so I made a common
src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect
that many other romcc-based boards will be able to re-use this Makefile.inc.

Apart from the board name, most boards only differ in the Super I/O that's
being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different
as it doesn't have an irq_tables.c.

I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a
proper config in another patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 17:10:00 +00:00
d7e49b40b1 Asus M2V-MX-SE support in Kbuild
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 16:55:06 +00:00
f608205c35 Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
monitors.

Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 16:04:47 +00:00
dc4bb0d43f Set the LIBGCC_FILE_NAME to fix problems with libgcc.a.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 15:35:36 +00:00
602d2b8dc2 Fix vendor name config variables to match company name (trivial).
Any whitespace or dashes are replaced with underscores.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 14:11:48 +00:00
879c17784f Correct typos /subdir/subdirs/ in documentation and util/x86emu/Makefile.inc.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 19:46:50 +00:00
2b7418ecc6 Use the gnu make .SILENT: mechanism instead of requiring
$(Q) in front of every silent line.

make V=1 or make Q="" still make make noisy again.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 19:38:46 +00:00
698c0e0e5a Make PCI_ROM_RUN a boolean (like it is elsewhere) which
is the correct choice. Avoids type problems in kconfig

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 17:38:24 +00:00
2389cfe8a7 Add microcode to socket_940 and socket_F. Part of the last reverting commit.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 16:18:11 +00:00
5cc74faeab Revert socket abstraction.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 16:04:45 +00:00
fe2664a5f2 Improve build output.
The Makefile prints need to be @printf -- not $(Q)printf -- as they should

 (1) be printed always (with 'make' _and_ with 'make V=1'),

 (2) but the printf command itself should not be printed, hence the '@'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 15:03:20 +00:00
20a1ae8840 Replace PIRQ_TABLE with HAVE_PIRQ_TABLE, the former doesn't exist.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 14:51:25 +00:00
673c831f21 Add vendor strings in mainboard/Kconfig. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 14:41:38 +00:00
9f8ecf5eb9 Add support for AMD Socket 940. Move common files to model_fxx.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 14:22:58 +00:00
ca5d9fb74a Properly check for the LZMA compression variable, and fix a print
message for the VGA ROM that would print a useless NULL string.

Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 13:53:14 +00:00
b7fec825fe Add kconfig support for ASUS P2B-F.
Only build-tested so far, not tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 12:25:36 +00:00
f9d4c2bad8 Fix copy-paste error in src/cpu/x86/Kconfig.
That file defines XIP_ROM_BASE twice, but the latter definition should
be XIP_ROM_SIZE (not *_BASE).

These exact two definitions are listed in src/Kconfig already, though,
so maybe one of the two locations should remove them?

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 12:19:28 +00:00
f8f5b620a2 Only build option_table.o if CONFIG_HAVE_OPTION_TABLE is 'y'.
Not all boards have an option table (cmos.layout).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 12:18:05 +00:00
1476a9ecc4 Without this patch, if we only got a DIMM in Channel B, memory can not be
set up correctly. Now it can. Please test it.

Moving "mct_AfterGetCLT(pMCTstat, pDCTstat, dct);" out of the "if" is the
key point.
Changing the Get_DIMMAddress_D(pDCTstat, i) to Get_DIMMAddress_D(pDCTstat, dct + i)
doesnt seem to take any effect. But I believe this is what it should be.

And a duplicated semicolon is removed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 04:12:55 +00:00
4d7ae4d96e Remove pretty useless kconfig help strings, fix some vendor names (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 01:06:39 +00:00
5ec2c2b998 Various Kconfig and Makefile.inc fixes and cosmetics.
- Whitespace fixes, remove trailing whitespace, use TABs for identation
   (except in Kconfig "help" lines, which start with one TAB and two spaces
   as per Linux kernel style)

 - Kconfig: Standardize on 'bool' (not 'boolean').

 - s/lar/cbfs/ in one Kconfig help string.

 - Reword various Kconfig menu entries for a more usable and consistent menu.

 - Fix incorrect comment of NO_RUN in devices/Kconfig.

 - superio/serverengines/Kconfig: Incorrect config name.

 - superio/Makefile.inc: s/serverengine/serverengines/.

 - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.

 - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.

 - mainboard/via/epia-n/Kconfig: Fix "bool" menu text.

 - console/Kconfig: Don't mention defaults in the menu string, kconfig
   already displays them anyway.

 - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 00:53:22 +00:00
50d0b8ce17 Add support for Nvidia Southbridges to Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 18:36:02 +00:00
fa9f12ef75 Add support for AM2 CPUs (I fixed the 0x11 issue).
Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 16:51:27 +00:00
0696bca90a The variable is already checked when including the socketF subdirectory.
Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 16:21:12 +00:00
44163f7f71 Update Coreinfo to use TAG_FORWARD in tables.
Update the ramdump function cursor functions and make the address hex
instead of decimal

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 15:25:11 +00:00
bab2bef484 This patch is about the DA-C2 and RB-C2. Chip with install processor
Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied to
them are almost the same.

Issues:
1. I really dont know what their nicknames are (Shanghai C2 or something).
2. About the mc_patch_01000086.h, I dont know if it is allowed to be released.
   If you really need it, please contact AMD Inc to see if it is public.
3. My RB-C2 is Socket type AM3, which needs DDR3 support. Probably your RB-C2
   doesnt need DDR3. If it does and you really need it, please contack AMD Inc
   to see if it is allowed to release DDR3 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 06:30:37 +00:00
ebed2dc720 Change the intel cpu makefile.inc so that it fits the model better.
- intel/Makefile.inc only mentions sockets
- those sockets are conditionally included
- makefile.inc in socket directories are almost all unconditionally included
- Get rid of if where possible, use -$(CONFIG_VARIABLE) instead as per Kconfig 
  standards in linux kernel

See the Kconfig.tex documentation for questions.  


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-21 18:08:49 +00:00
0b028a450f Trivial spelling corrections.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-21 14:59:14 +00:00
d82e12858f This goes a surprisingly long way to building the epia-n. It also has
important corrections to the Kconfig and Makefile.inc that were there. I
would like to go ahead and get this in, because I don't want anyone to
continue using what is in the upstream tree as it now exists.
I also tested old-style build with this and it did not break anything.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-20 18:05:31 +00:00
b203c2f95e 20090819-2-trim-down-cbfs:
CBFS uses sprintf, which requires vtxprintf, which requires (in the
current design) a nested function. That works on x86, but on PPC this
requires a trampoline. In the ROM stage, this is not available, so
remove the single use of sprintf and replace it with a direct string
handler - it's only used to fill in fixed-length hex values.

20090819-3-more-noreturns-in-romcc:
Mark two more functions in romcc as noreturn. Helps clang's scan-build a
bit

20090819-4-cbfsify-ppc:
Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and
not complete yet.

20090819-5-fix-ppc-build:
The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat
plausible value.

With fixes to tohex* functions as discussed on the list, and correct
function names.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-20 14:48:03 +00:00
ce9d8640b1 Add an error message if there is a zero-sized fixed resource. Fix the existing
example of one.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19 19:12:39 +00:00
6bd93f4753 Don't let zero sized fixed resource mess up the allocator's memory map.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19 17:29:41 +00:00
d26053a10f Config-abuild.lb doesn't need to override ROM_IMAGE_SIZE.
Trivial change

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19 14:08:42 +00:00
7467664c09 Reduce size of the romstage on various boards that fail to build on QA.
This eliminates 56kb of padding in the bootblock.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19 13:40:20 +00:00
69a031c4e1 The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of
F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19 07:08:10 +00:00
c5f3f19d0f Correct usage of Makefile.inc and add support for cn400
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-18 17:15:39 +00:00
dc9cabd6c3 Add via south support. Correct usage of conditional variables.
Note the makefile.inc may be out of date given the new commits of code
today, but this is what was signed off ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-18 17:14:58 +00:00
9c2e738653 Add the rest of the files.
Thanks Jon.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-18 15:12:13 +00:00
1825be291f Get the Via EPIA-N(L)/CN400 to a reasonable level of maturity::
Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
kernel) from SATA HDD.

ACPI is working for PCI interrupt routing, some memory stuff and
Soft-Off.
USB/SATA Working
VGA Console Working
X Working via Onboard AGP

Removed dsdt.c, fixed some whitespace.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 17:09:46 +00:00
b5f4e77bff Add more docs, this time for southbridge.
No real difference from northbridge. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 15:42:18 +00:00
e70471b645 Move CBFS header to a safer place.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 15:19:52 +00:00
b5034d4703 Remove unused normal image option in Kconfig
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 14:47:32 +00:00
488c36c8e7 Allow setting up a VGABIOS image in Kconfig
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 14:46:13 +00:00
7e92ff343e Add 4MB ROM image size to Kconfig
Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 14:33:03 +00:00
10c41fa008 Most of the changes here are trivial, but the white space changes would be harder to undo than to do over.
I changed all groups of 8 spaces to tabs, then all tabs to two spaces so more of the device tree fits on the page.  It could have been three or possibly four, but the largest indents I found were 6 tabs, so 4 is a lot of the space on the page.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-13 16:02:24 +00:00
fabde37cb8 - AMD selected a couple of options that are incompatible with QEmu (and
probably others). Only select them for AMD

- Make the bootblock smaller (only one copy of it), and don't pad the
bootblock using dd(1), but top-align inside cbfstool, to reduce
dependencies on unix tools.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-13 15:29:01 +00:00
a5c8bb39b5 Fix some conflicting types of variables
Remove the normal/* files from the image. they're just
copies of fallback/* anyway.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-13 07:33:55 +00:00
b6e03200a4 \\ are not escaped in a sane way between fedora and ubuntu! Just create
these files to make sure that we don't get idiotic problems.

Fix things so they build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 20:25:24 +00:00
245a7da495 Remove duplicate file, adjust Makefile to use the original copy.
Keeping identical files around will only bite us eventually, when they
get out of sync. See coreboot-v2 history for examples.

Trivial and build tested.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:16:05 +00:00
109ab317e7 drop extra whitespace at end of line for i945 + ICH7 (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 16:08:05 +00:00
fd4519b5ef This now builds.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:56:17 +00:00
5f6572ec8b Fix multiple missing files and errors from the recent commit. This happened
when Patrick's tree and mine got out of sync.

Link stage still fails.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:39:38 +00:00
9a94843820 Missing files from last patch.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:26:31 +00:00
0588d19abe Kconfig!
Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:00:51 +00:00
38cd29ebd7 Don't pull in x86emu from a foreign directory anymore. This
produced numerous problems in the past, including the fact that
x86emu doesn't work in v3 anymore even though it lives in the v3
repository.

Since this is a cross-repository move, keeping the history in the v2 tree 
would make life hard for everone. So check the v3 repository for x86emu history
since the merger. The his commit is based on an svn export of r1175 of the
coreboot-v3 repository.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11 21:28:25 +00:00
b339e10f04 Enable CBFS everywhere. All boards compiled for me (abuild tested),
and we will fix issues as they appear.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11 17:35:02 +00:00
401c8d1da2 cpu/amd/model_lx used its own routine for copying coreboot_ram. This
change makes it use the generic infrastructure.

NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram,
this change has a high probability to break that place - so look into it.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11 17:32:26 +00:00
edee9eb350 The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1.
We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11 03:18:11 +00:00
dabae0d8fc fix for the case that CONFIG_TTYS0_DIV is defined in mainboard's Config.lb
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-06 11:36:33 +00:00
052d591e64 fix buggy comment in libpayload's strncat function
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-05 13:10:38 +00:00
dec1b47bd7 Add some more CONFIG_* prefixes that were missing.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-05 12:24:23 +00:00
313973d61a Prepare for kconfig: Rename COREBOOT_V2 to CONFIG_COREBOOT_V2
and adapt its user (x86emu) to match.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-05 12:16:01 +00:00
f537407e5a Fix the generic code for copying and running coreboot_ram in case
certain configuration options are disabled. The strings were just
at the wrong place.

Two boards fix up some variables for romstream. This isn't necessary (or
possible) when CBFS is active, as there is no romstream. It would be
nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any
invariant that forces that to be inactive if CBFS is active, and this
patch is supposed to be small, esp. as the stream loaders are on the way
out.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-05 10:48:43 +00:00
8f95edaabd oops, these two were missed in the last cleanup.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-31 14:45:41 +00:00
5fe6e23c61 Catch various cases in libpayload where malloc() or memalign() return NULL
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-31 11:39:55 +00:00
131c0070a3 * drop duplicate prototype for lib_get_sysinfo()
* fix delay handling in tiny curses keyboard driver
* fix off by one error in video driver

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-31 11:38:59 +00:00
e3f39b50cf Fix erroneous comment in src/mainboard/h8dmr/Options.lb
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-28 01:23:32 +00:00
4551b4961a drop dead nested assignment (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-26 15:11:53 +00:00
fc4226c563 trivial typo in a comment
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-26 15:05:40 +00:00
f64893a94f CBFS stuff:
- update, add, and improve comments
- whitespace here and there
- remove unused or write-only variables
- improve debug output
- only build payload.{nrv2b,lzma} for non-cbfs
- improved error checking in cbfstool

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-23 22:03:14 +00:00
aeb6c9870f sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
and through the general vga infrastructure i committed a month or two ago.
Add videoram_size option for k8m890 and the Asus M2V-MX SE.

Now the Asus M2V-MX SE will magically come up with a working standard VGA
80x25 textmode.

Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
of its components; this vga bringup was a breeze thanks to your hard work
for this excellently supported board. And separate thanks to Rudolf Marek
for spurring me on and for providing a register dump.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-23 16:04:58 +00:00
b2bd9963a5 We did together some patch which makes finally a MMCONFIG workable in
linux out of the box. There were two problems. First was that the
mmconfig ACPI structure was empty because of cut and paste (PCI ID of
K8M890 is different).

Second problem is now nicely solvable by add_region. Linux expects that
the mmconfig region is found as reserved memory. Otherwise it does not
trust it.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Luc Verhaegen <libv@skynet.be> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-23 08:10:51 +00:00
8dee52d7a8 Don't put .o files in the source tree. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-22 12:26:18 +00:00
f5c38c0da6 Fix a redundant declaration warning (trivial)
src/include/device/pci.h:75: warning: redundant redeclaration of 'pci_dev_init'
src/include/device/pci_rom.h:39: warning: previous declaration of 'pci_dev_init' was here

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-22 01:42:13 +00:00
4704dc520b Fix up the tree again...
* acpi_add_table requires a pointer to the RSDP, not the RSDT anymore, in order
  to properly support XSDT generation.
* fix compilation the DSDT on gigabyte/m57sli
* drop a remaining, forgotten HPET_NAME for "HPET"

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-22 01:11:37 +00:00
cdfe376c06 clean up acpi table strings, as discussed on the list
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 22:15:43 +00:00
aecf2511c6 Another include file slipped. This gets via/epia-m building again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 22:01:21 +00:00
a5fdadfa18 Kontron updates, get board up to date with i945 and ich7 updates.
Move interrupt routing to mainboard specific code. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:58:20 +00:00
e1a66573b1 this bug sneaked in during conversion
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:57:11 +00:00
573f7d40be Intel ICH7 updates
- code restructuring (move ich7 out of i945)
- ACPI fixes 
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:50:34 +00:00
71a3d96bc4 * drop ich7 include
* detect more i945 variants
* raminit fixes
* ACPI + PCIe updates

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:44:24 +00:00
4da810bd53 add intel speedstep support and some PM fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:41:42 +00:00
b657a3c9b7 This fixes a couple of issues with older Linux kernels (that expect an XSDT as
soon as there's an ACPI 2.0 or later table)

* add XSDT support
* add more table types

This patch will break at least the kontron (and possibly some new boards I
missed)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:38:33 +00:00
4d933dd2d6 Rewrite interrupt handling in coreboot to be more comprehensible and
more flexible. Also some minore device allocator cleanups that sneaked 
in.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:36:41 +00:00
c366cd0650 Add more warnings to CFLAGS, and also add some to HOSTCFLAGS
include ldoptions from ldscript.ld instead appending it.

Not everyone was happy about the -Wmissing-prototypes in CFLAGS. 
I put it in there now anyways, so everyone can get an overview which parts of
their code could use some cleanup. If it gets too ugly, we can still remove
that flag again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:31:36 +00:00
0001a7f129 Example how simple it is to use printk instead of printk_something in
coreboot ram stage.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:25:45 +00:00
094198cf43 Rewrite keyboard driver to actually wait time in ms as specified in the specs,
rather than doing inexact and slow idle loops.
Also improve error reporting in case of problems.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:24:22 +00:00
163ff1d5ad - Remove superfluous / from path
- use make -C instead of workaround

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:22:40 +00:00
bb01f600c8 Some USB debug updates, mostly comments fixing, license header updates
and refactoring

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:20:45 +00:00
4fbefdd1a9 * rework tsc based timer code to use inb instead of outb for calibration
* Add generic Local APIC based timer code. This timer does not need expensive
  calibration and thus reduces the boot time by up to more than a second.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:19:06 +00:00
925b6c0c43 * cleanup ricoh rl5c476 code:
- drop duplicate udelay function
  - simplify code flow
  - some cosmetics on comments

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 20:27:00 +00:00
733263c44c Remove a comment that no longer applies. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 18:06:12 +00:00
28f17dbf6b Add legacy I/O region for vt8237r southbridge.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-20 19:42:15 +00:00
85a94f66b2 Rename some preprocessor symbols. I have no idea why
those symbols were left alone before, after this, they're
somewhat more in line with the rest of the tree.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-20 19:34:47 +00:00
951f5882e2 The file string.h is also included in romcc code, which has no malloc().
The patch adds proper preprocessor guards and drops the malloc() prototype
because that's in stdlib.h

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-19 00:18:15 +00:00
0c88655b03 coding style fixes for powernow (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18 18:00:37 +00:00
6afcea8552 drop unused variable (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18 17:58:44 +00:00
f23804bda4 This patch fixes payloads on certain Fedora versions
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18 15:18:22 +00:00
219cece2f5 Fix off-by-one bug in libpayload UHCI driver
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18 15:17:40 +00:00
f107538e33 strdup the input of dirname, as dirname is free
(according to the spec) to change the string in-situ,
even if glibc doesn't do it.

This avoids errors on Mac OS and Solaris.

Kill nrv2b support in CBFS (we have lzma),
slightly improve debug output in CBFS,
properly declare all functions of CBFS in the header.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-18 14:20:39 +00:00
19bc45d1e8 Bring S1g1 cpu names up to date with the official
Revision Guide for AMD NPT Family 0Fh Processors

Rev. 3.42 March 2009, found at

  http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf

This patch takes its data from Table 9.

Build tested.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17 15:15:17 +00:00
36e8ff4c16 Bring Socket F cpu names up to date with the official
Revision Guide for AMD NPT Family 0Fh Processors

Rev. 3.42 March 2009, found at

  http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf

This patch takes its data from Table 7.

Build tested.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17 15:13:54 +00:00
fcee8fee3f Bring AM2 cpu names up to date with the official
Revision Guide for AMD NPT Family 0Fh Processors

Rev. 3.42 March 2009, found at

  http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf

This patch takes its data from Table 8.

Build tested, and boot tested on a AMD Athlon(tm) Dual Core Processor 5050e.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17 15:12:45 +00:00
b17f9528cd This is an obvious bug which I overlooked when I worked on the AM2r2
modules.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-17 05:41:34 +00:00
782de9aa5e Separate cache_as_ram_auto.c and failover.c for Tyan s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-16 15:53:11 +00:00
4e2ffb8812 Fix VIA EPIA-M700 target enough for a first serial boot log.
Add the respective Super I/O config in Config.lb (Winbond W83697HG),
enable COM1 on the board, fix irq_table.c, as well as the PCI
devices listed in Config.lb (based on lspci output).

This has been tested by Jakob Bornecrantz <wallbraker@gmail.com>
on hardware, i.e. there is serial output. It does not yet boot
to a Linux console successfully, more fixing will be needed.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-15 00:03:28 +00:00
3839a8ebd8 trivial fixes to function declarations (and build system test)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-14 19:10:10 +00:00
7a0f01f211 Superiotool: Add IT8703F support.
Kudos to ITE for providing the necessary information that quickly.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Tested-by: Glenn Mueller <mechwarrior5@hotmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-12 14:24:06 +00:00
fc6de69078 Fix MS-6178 boot by setting unused device (CIR) to 'off' (trivial).
Tested on hardware, works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-11 22:00:37 +00:00
e42e142d9f Apparently I'm not the only one who forgets which way the outb and
outl arguments go.

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10 15:05:35 +00:00
7d4fd2c108 This seems to be a more official, common, simple way to check if the CPU is dual core or
single core.


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10 03:42:13 +00:00
9f26b8f710 msrtool: CS5536: The most important interrupt MSRs and some DIVIL MSRs.
Thanks to Tom for reviewing as well!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>                                      


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10 03:10:26 +00:00
2698fe5e1b Add CONFIG_ARCH_X86=0 to sandpointx3_altimus_mpc7410.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07 19:00:10 +00:00
42f75c325f Add pci_rawops.h from the mailing list and fix the via/epia-m700 build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07 17:54:26 +00:00
bf12ddae23 ChangeLog:
Change the parallel port from polling to interrupt-driven.

This was tested by Andreas Mundt with a parallel port printer.

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07 16:15:43 +00:00
941c1fd52a Add initial support for a CBFS module for coreinfo.
Currently it prints a list of components in CBFS and their size/type.
There's a bunch of additional output that could be printed, but that's
for another patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07 15:10:13 +00:00
280df106c0 Add the IORESOURCE_BRIDGE flag to the fam10 resources for the benefit of the resource allocator.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07 13:26:35 +00:00
ca807f138c Enable onboard-VGA on the Mitac 6513WU board.
Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-06 16:05:54 +00:00
b70a45afd0 Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.

Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.

Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05 19:29:39 +00:00
3f1458ddd4 Fix build for i810 boards that don't enable onboard VGA, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05 16:23:43 +00:00
328bccc610 Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).
Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).

In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:

Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c       (Revision 4393)
+++ src/devices/pci_rom.c       (Arbeitskopie)
@@ -87,7 +87,7 @@
        if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
                printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
                           rom_data->vendor, rom_data->device);
-               return NULL;
+               // return NULL;
        }

        printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",

The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...

Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05 16:01:57 +00:00
76a88d0805 Various Intel 82810/82810E changes which allow onboard VGA to work.
At the same time also make the 82810 code handle 82810E.

 - Set SMRAM register according to CONFIG_VIDEO_MB value:
    - 512 means 512 KB
    - 1 means 1 MB
    - Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
   This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
   in a future patch may be nicer.

 - Set MISSC2 register bits as required per datasheet to make VGA work.
   The code handles both 82810 and 82810E.

 - northbridge.c: Add __pci_driver entry for the Intel 82810E.

Also:

 - Rename PAM register #define to PAMR as per datasheet.

 - Drop unused/commented code for now.

 - Don't explicitly set GMCHCFG for now, the default works ok. We'll
   have to figure out the proper/ideal settings later.

The code is based on a patch from Elia Yehuda <z4ziggy@gmail.com> but
has been modified quite a bit for correctness and minimalism.

Tested on hardware with a slightly modified MS-6178 target,
patches to enable onboard-VGA for MS-6178 will follow.

Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05 15:50:30 +00:00
bd4f2f808c Fix many things for via/epia-m700 to build.
Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 21:19:33 +00:00
29be535a40 ChangeLog:
Turn on Parallel Port and Floppy in Config.lb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 19:06:01 +00:00
c7233e0899 Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of
resource allocation.

Fam10 code could be updated the same way.

Move VGA code before resource allocation but after device enumeration.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 19:02:33 +00:00
29cc9eda20 Move the v3 resource allocator to v2.
Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 18:56:24 +00:00
2468331952 Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.

Importantly, this also sets

  default CONFIG_AP_CODE_IN_CAR=0

in

  src/mainboard/supermicro/h8dmr/Options.lb

which is required to make this box boot since the changes that went in in
r4315.

At Myles' suggestion, this patch also sets

  default CONFIG_USE_FAILOVER_IMAGE=0
  default CONFIG_USE_FALLBACK_IMAGE=0
  default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE

in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.

Build tested with abuild, boot tested on physical hardware.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 18:27:02 +00:00
1a692d8176 Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 17:01:17 +00:00
6c96517a13 Fix typo and only output post code if the work was done.
Thanks to Thomas Jourdan <thomas.jourdan@gmail.com> for reporting it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 16:34:03 +00:00
08405e7411 Fix abuild for via/epia-n. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 15:08:19 +00:00
9a7368d4b7 I missed three files.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 13:19:25 +00:00
0d4a08e7da let abuild autodetect the coreboot path a bit better. So in the top level of
coreboot you can now do:
  $ util/abuild/abuild -t foo/bar
instead of
  $ util/abuild/abuild -t foo/bar $PWD

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 12:26:11 +00:00
3c6bd6c773 the file was not really different, so use the default file (trivial, since it
didn't build before, and it still doesn't)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 12:22:26 +00:00
cfb9cd2f8a Ron,
Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>

Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 10:57:25 +00:00
db8b4114ff Add AMD family 10 AM2r2 support.
Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.

This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE.
It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 07:01:32 +00:00
9dd27bc03a the tool chain settings should not be in renamed (as they will never live in
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 17:13:58 +00:00
36f230eefb whoops. missed those two..
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:54:53 +00:00
775c04e537 commit svn:externals for last commit (what a pain) (1/2)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:23:20 +00:00
0867062412 This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:17:49 +00:00
9702b6bf7e add new supported chipset
Add identification for X58 and ICH10R.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 14:11:42 +00:00
b1ff95c14d This copy of flashrom is old and unmaintained. Delete it to avoid
confusion, after we had a grace period to get people to move over to the
new repository.

History stays available for the archaeologists and for ancient
checkouts (potentially with local changes). Use "svn diff" to get local
changes, and apply it to a newer tree (if you manage to apply it, that
is).

The new repository is available at:
svn://coreboot.org/flashrom/trunk

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 22:47:06 +00:00
1220c50919 flashrom is a separate project now. Thus we don't enforce it on our users.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 22:40:48 +00:00
3f57548625 Impact: fix vmlinux from 2.6.30
from 2.6.30 (?)
the new vmlinux with per_cpu and brk support will have more sections.

Elf file type is EXEC (Executable file)
Entry point 0x200000
There are 7 program headers, starting at offset 64

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000200000 0xffffffff80200000 0x0000000000200000
                 0x0000000000e46000 0x0000000000e46000  R E    200000
  LOAD           0x0000000001046000 0xffffffff81046000 0x0000000001046000
                 0x00000000001406e0 0x00000000001406e0  RWE    200000
  LOAD           0x0000000001200000 0xffffffffff600000 0x0000000001187000
                 0x0000000000000888 0x0000000000000888  RWE    200000
  LOAD           0x0000000001388000 0xffffffff81188000 0x0000000001188000
                 0x000000000008a086 0x000000000008a086  RWE    200000
  LOAD           0x0000000001600000 0x0000000000000000 0x0000000001213000
                 0x0000000000015e20 0x0000000000015e20  RWE    200000
  LOAD           0x0000000001629000 0xffffffff81229000 0x0000000001229000
                 0x0000000000000000 0x0000000000208000  RWE    200000
  NOTE           0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8
                 0x0000000000000024 0x0000000000000024         4

 Section to Segment mapping:
  Segment Sections...
   00     .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param 
   01     .data .init.rodata .data.cacheline_aligned .data.read_mostly 
   02     .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies 
   03     .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs 
   04     .data.percpu 
   05     .bss .brk 
   06     .notes 

So need to increase NR_SECTIONS.

also fix one typo about phys address mask.

Peter says: A similar fix was also implemented by Maciej Pijanka, so let's
commit this now, eh.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 15:04:06 +00:00
3ddbfb8901 Add a target/ directory for the VIA EPIA-M700 board, so we can build it.
Note that this board is nowhere near usable, further patches will follow
and hopefully get this into buildable and usable shape.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-27 16:06:51 +00:00
22b44ba9c3 Add dump support for SMSC LPC47N252.
Signed-off-by: François-Regis Vuillemin <coreboot@miradou.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-27 02:23:26 +00:00
db52fb8024 Don't dump 0x07 registers, they're useless as they change every time
some software wants to do an LDN access (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:53:07 +00:00
556e6fb2e3 This adds register definitions for all logical devices on the SMSC
LPC47U33x, allowing 'superiotool -d' to work.

Also, some consistency string fixes.

Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:25:04 +00:00
78fdd6046e Add dump information for F71862FG and F71863FG.
Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:16:21 +00:00
bb21b2e45b Remove the object files for cbfs from target directories and add a
cbfstool-clean target to the Makefile.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-25 21:44:38 +00:00
455e223365 The problem is that the check to see if we're at the end is never reached. I
didn't look into it enough to know why fssize is 32 bytes larger than the
offset.  There may be another bug here.  Maybe something with the CBFS header
not being included or excluded from the calculation?

Anyway, this patch fixes it for all cases size > 32.

I also changed the error message so that it doesn't look like the ROM is full
just because it can't find room for a file.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-25 15:54:57 +00:00
8c19f949fe Add support for the Soyo SY-6BA+ III board.
Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots
Linux fine. Detailed status at:

  http://www.coreboot.org/Soyo_SY-6BA_Plus_III

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro@ziltro.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-24 00:35:07 +00:00
3310d75e6c This patch adds a proper namestring generation to our ACPIgen generator.
Its used for Name and Scope and Processor now. As bonus, it allows to
create a multi name paths too. Like Scope(\ALL.YOUR.BASE).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-21 20:26:13 +00:00
f17f647a62 Undo my ugly commit that added uses clauses in lots of places instead of one.
Fix configuration of all boards. (Abuild tested)
Hopefully fix compilation of PPC boards (they've never compiled for me.)

Apologize profusely.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 21:18:14 +00:00
24fbb7d66f work around initobject breakage in pc80/Config.lb
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 19:50:58 +00:00
6114311c8e Convert the MSI MS-6178 board to CBFS.
Also, enable HIGH_TABLES support for this board.

The HIGH_TABLES failed with:

  No matching ram area found for range:
    [0x00000000000f0000, 0x0000000000100000)
  Ram areas
    [0x0000000000000000, 0x0000000000001000) Reserved
    [0x0000000000001000, 0x00000000000a0000) RAM
    [0x0000000000100000, 0x000000000fff0000) RAM
    [0x000000000fff0000, 0x0000000010000000) Reserved
  SELFBOOT RETURNED!
  Boot failed.

The fix was to change northbridge.c as follows:

  - ram_resource(dev, idx++, 1024, tolmk - 1024);
  + ram_resource(dev, idx++, 768, tolmk - 768);

This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 15:41:49 +00:00
62cfe169fa ChangeLog:
Add initial ACPI support for M57SLI.
	Activates/Enables:
		* native Coreboot ACPI for M57SLI
		* Soft-Power-Off
		* PowerNow!
		* High Precision Event Timer
		* Windows booting with ACPI support

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 12:03:40 +00:00
ecf4ef0b26 Make sure the address variable is initialized to zero - it is only set when a
[base address] parameter is supplied on the command line... This patch fixes
random segfaults when using 'cbfstool add'.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 16:38:35 +00:00
da8336176e Change Log:
Fix interrupt handling in mptable.c on M57SLI.

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 10:05:41 +00:00
b735f85379 Change Log:
Activate HIGH_TABES on M57SLI

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 09:46:11 +00:00
82bc9bc31e Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.
Abuild tested with -C.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17 16:38:43 +00:00
aac8dc81c5 Patch AMD Fam10 C2 for errata 327, 344, 346, 354, 351.
Removed c2 HT Phy 520a/530a reserved bit.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17 15:33:57 +00:00
cbefc238c5 Maximilian Thuermer found a bug where the HT link capability code was always
updating the passed value to the next link offset even when it was on the
requested link (cap_count).

Maximilian also found a bug where the linktype was still getting attributes
even when it wasn't initialized.

This should fix the HT problems for Fam10 C2. There are still issues with the
microcode which need to be resolved.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16 23:02:39 +00:00
d41de2ea7a These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice 
thing: no more included .S or .c files. It's all separate compilation. 
That should allow our Makefiles to work much better.

Note that the current non-CAR implementation is the default and 
continues to work (tested FILO boot to Linux on both CAR and non-CAR).

Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that 
depend on this variable are grouped in one if, and the other parts 
(romcc etc.) are in the else. This change is a model of how we should be 
able to do other motherboards.

Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options. 

Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file. 

Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3. 

Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem. 

Index: src/pc80/serial.c
make uart_init non-static. 

Index: src/pc80/Config.lb
add initobject

Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3. 

Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init. 

Index: src/arch/i386/init/car.S
generic i386 car code from v3. 

Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section. 

Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well 
get all the debugging we can. 

Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds. 

Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16 15:02:52 +00:00
3ba18a67eb Fix typo in Winbond W83977TF register listing.
Signed-off-by: Ioannis Barkas <tripl3fault@yahoo.com>
Signed-off-by: Nikos Barkas <levelwol@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-12 14:20:27 +00:00
124d8767da Fix s2895 failover booting.
Abuild tested and boot tested on s2895 and serengeti_cheetah.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-11 18:27:41 +00:00
9ca6ed548e this port is horribly broken and should not have been checked in. This patch
gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-09 15:22:47 +00:00
a88db7bb87 Fix a little white space issue. Also, don't copy the rom image
if it is already in its correct location. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-09 14:44:37 +00:00
e8c6f86b80 Add (commented) line for VGA blob adding (CBFS version) to simplify things for users a bit.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-08 13:05:47 +00:00
6ce41c06cc This is transition code for cbfs to implement
cbfs files at fixed addresses.

I call this transitional as the approach I am taking is to add
capability to cbfstool but not change code in a way that will break
existing usages. Later, once we're sure nothing has broken, we can start to 
smooth the edges. 

Right now, fixed address file are only supported via the add command. 

There is one additional command syntax, so, example:
cbfstool add rom romstrap optionrom 0xffffd000

Will add the file to that fix location for a romstrap.

The assumption is that the ROM is based at the end of a 32-bit address
space. As you can see from the code, that assumption can easily be
over-ridden, if we ever need to, with a command option.

Here is one example output result.

rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print
x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
h                              0x0        optionrom   251
                             0x130      free         917120
h3                             0xdffe0    optionrom    251
                             0xe0110    free         97960

The way this is implemented is pretty simple. I introduce a new
operator, split, that splits an unallocated area into two unallocated
areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits:
0 split -- the free area is the exact fit
1 splits -- need to split some off the front or back
2 splits -- need to split off BOTH the front and back

I think you'll be able to see what I've done. I call this transitional
because, in the end state, we only need one allocate function; for now
I've left two in, to make sure I don't break compatibilty.

Why I like this better than ldscript approach: I like having the
ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes
romstrap visible as a first class object. I think I would have latched
onto a problem I was having much more quickly had I remembered the
ROMSTRAP. It gets lost in the linker scripts.

At this point, we should be able to start removing special ROMSTRAP location 
code from linker scripts. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-08 03:33:57 +00:00
d64f403f8e A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes:
- Make get_dsdt script executable.

 - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.

 - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
   is correct.

 - Fix broken or incorrect #include names to increase likelyhood of a
   successful compile.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-07 14:38:32 +00:00
0ffff3434e First bunch of coding style and consistency cleanups for the
EPIA-M700 target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-07 13:46:50 +00:00
cff071ab0e When I started refactoring mainboard Config.lb, I added two different
files for targets without failover:
src/config/nofailovercalculation.lb (64 kB XIP)
src/config/nofailovercalculation128.lb (128 kB XIP)
Targets with other XIP sizes were ignored.

This patch moves XIP size back into mainboard code.

Benefits from this patch:
- src/config/nofailovercalculation128.lb is no longer needed
- Targets with XIP sizes besides 64k and 128k benefit from refactoring
- Conceptually, this makes the include files pure calculation files
without settings.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 16:50:38 +00:00
a7d8ae3b1d Make failover larger and decrease fallback's size so the total stays the
same. The errata need some extra room in failover.

Trivial and abuild tested


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 12:19:59 +00:00
a774192e22 Fix for Erratum 350 for AMD Fam10h CPUs.
Compared to posted patch, there are whitespace fixes
(request by Uwe), and a guard to run the erratum only
on AMD_RB_C2 (request by Marc).

Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 11:33:58 +00:00
c263b4471d Fix for Erratum 343 for AMD Fam10h CPUs.
Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 11:21:52 +00:00
240ef7c769 Change the CBFS build process to use coreboot.rom
instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.

This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.

Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
  crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
  as it's done everywhere else
- change the default config of abuild to not
  provide ROM_IMAGE_SIZE values for the images
  in a CBFS configuration
- change abuild's crosscompile autodetection to
  not try to use "i386-elf-i386-elf-gcc" (which
  is bogus)

Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS

The changes in util/abuild/abuild are trivial and
abuild tested.

As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 07:19:53 +00:00
aa58f5427f Fix non-revF K8 ram init compilation which was broken in r4341.
Change all printk_raminit to printk_spew.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 23:43:11 +00:00
20a98c9201 Initial untested board code for the VIA EPIA-M700 Mini-ITX board.
The patch has been submitted by bari <bari@onelabs.com> and written
by OLPC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 23:02:43 +00:00
3c45a96138 K8 RAM init debug messages are pretty short and sometimes cryptic. Make
them a bit more verbose and hopefully more understandable.

Old messages for my machine with 5 GB:
RAM: 0x00400000 kB
Ram3
[...]
Initializing memory:  done
RAM: 0x00500000 kB

New messages:
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
[...]
Initializing memory:  done
Handling memory hole at 0x00300000 (default)
RAM end at 0x00500000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00500000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x00300000 kB

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 20:37:35 +00:00
87e7050bff die() does never return. Annotate it as such.
Any endless loop after die() can be eliminated.
Dereferencing a NULL pointer is bad. die() instead.
Replace endless loops with die().

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 11:41:51 +00:00
28d71b9445 After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.

Tested on dbm690t.

Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.

http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 10:00:07 +00:00
a24e1dd6da Add a hopefully more correct and flexible set_dram_buffer_strength()
function based on test results with many different DIMMs.

Tested by Uwe Hermann <uwe@hermann-uwe.de> on hardware.

Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see.

Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 00:22:25 +00:00
1725703a1d The point of the patch is to make it easier to understand the raminit
code, specifically the difference between pre_f and f code.

The only functional changes are in printk statements.  The rest is white space.

1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks.  All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code

There is much more that could be done, but it's a start.

Abuild tested and boot tested on s2892 and serengeti_cheetah.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-04 20:18:42 +00:00
d11bd003c6 This patch is about some noticable bugs which was made by no reason.
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
  (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
      In rpr 5.10.2, step 2, step 2.1 & step 2.6
  (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
      instead of PCIEIND_P: 0x20.
      In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-04 01:57:03 +00:00
a9c5ea08d0 Revert "CMOS: Add set_option and rework get_option."
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.

Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 14:19:33 +00:00
9efecc5408 Revert "kontron 986lcd_m: cmos.layout: mark boot_devices as reserved."
This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec.

Stepan pointed out that 's' means string, and that therefor strings do exist.
Marking this as reserved breaks some payloads.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 14:19:20 +00:00
b005f0e2e0 kontron 986lcd_m: cmos.layout: mark boot_devices as reserved.
The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices".
The changes to the cmos code no longer allow usage of values larger than
32bits. Since this option was completely unused, mark it as reserved.

Fixes build after the get_option change (r4332)..

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 11:53:54 +00:00
9ceae905f1 CMOS: Add set_option and rework get_option.
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.

get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.

The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.

build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 10:47:19 +00:00
a922b3195b Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 03:15:05 +00:00
f8318fe8f9 More compact format for wiki output at
http://www.coreboot.org/Coreboot_Options (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-02 23:49:00 +00:00
c7a6447c8f cbfstool reacts to a too large bootblock file by stopping
with an error code now.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-01 20:02:21 +00:00
fff87d31ca Cosmetics and consistency fixes in src/superio/serverengines/pilot/ (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-01 01:38:29 +00:00
a519fe77b6 Following patch moves all vt8237 fadt.c from mainboard/* file to chipset
directory just with one common file.

Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
Change the compiler to CORE , its revision to 42. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-31 17:00:25 +00:00
608762793a Many Kudos go to Segher Boessenkool and Patrick Georgi for figuring this one
out. Fix the libgcc dependency on abort() due to nested functions.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-30 15:12:33 +00:00
41216225a1 rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 18:41:09 +00:00
60f0f1b18f enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 13:45:22 +00:00
f8a5c6ec02 drop most of the crappy vm86 code and replace it with a rewritten
version that has all assembler in a .S file and all C code in a .c
file. Also, remove requirement to move around between GDTs.

This version includes the suggestions from Peter to clean up CR0 manipulation
and to guard critical code paths by cli/sti. Tested and working on my hardware.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 13:08:27 +00:00
43bc5a9c74 Fix build with CONFIG_*_ROM_RUN.
Last commit broke it due to leftover "void" from prototype.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 03:44:47 +00:00
5c5beb765d Implement native VGA Support.
This code brings a rather complete set of VGA IO routines for whoever wants it.
These consist of the by now familiar read/write/mask sets. Due to the crazy
nature of VGA, an ancient standard with bits all over the place, it makes no
sense to define individual registers. You need a vga register spec at hand if
you want to do anything anyway. These IO routines are always exposed.

It also provides code to natively set up a 640x400 VGA textmode with an 8x16
font. The native VGA mode code is behind the OPTION_VGA option, as the font
really adds to the size of the compiled/compressed rom. The font is the one
also present in the linux kernel, but this file is unlicensed. Another copy of
this is also present in coreboot in the deprecated console/btext code.

The vga console code has been cleaned up, but it still has some TODO's left
open, but that's for when i finally have found the remaining issue with the
epia-m. Right now, it is important to get parts of my work out already and to
make the remainder managable again.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 03:04:16 +00:00
195f5cd666 Add lzma.o for CBFS, regardless if CONFIG_COMPRESSED_PAYLOAD_LZMA is
enabled or not.
CONFIG_COMPRESSED_PAYLOAD_LZMA is set only if the lzma utility is found
on the system - at least when using abuild. CBFS doesn't use this tool
for compression.

The result was a failed build if lzma (the tool) wasn't found, or
failed runtime (if src/lib/cbfs.c disables lzma decompression based on
CONFIG_COMPRESSED_PAYLOAD_LZMA)


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-28 22:18:25 +00:00
f9f4eaf7ab Make memmove copy (dev->resources -i) resource structs instead of
(dev->resources-i) bytes in compact_resources.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-28 21:57:11 +00:00
7365004424 First batch of indent-aided code cleanups, more will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 18:55:19 +00:00
5c044c732f Make directory hierarchy flat to match the same layout we use
for other chipsets, as suggested on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 17:06:54 +00:00
f2a4e63f92 Trivial, but brown paper bag worthy:
#ifdef CONFIG_foo
is a bad idea with our build system


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 14:57:53 +00:00
a034dca42c Move coreboot_ram and coreboot_apc to CBFS. This allows to
reduce the size of the bootblock (done for kontron/986lcd-m)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 14:19:31 +00:00
8341f44f98 Change all vx800 file names from CamelCase to camel_case to match
our coding guidelines (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 13:46:37 +00:00
612163e383 Here's the VIA vx800 patch from OLPC.
It's untested, but a good starting point for everyone.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 13:12:42 +00:00
e6e899dde9 util/vgabios: build/warning fixes.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27 11:39:16 +00:00
bab4f92c8b Clean up acpi table writing code, and don't rely
on a given alignment for the RSDP and RSDT - look
it up instead.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 19:39:14 +00:00
5429e26b9c Tell lpgcc about the target architecture directory. This slipped through since
FILO does not use lpgcc (yet)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 18:01:53 +00:00
21dbe8ad3c Make printk_* behaviour more consistent. Without it, side
effects in the arguments (eg. a pci config read, or variable increment) 
"vanish" with the message, and the behaviour changes.

Some of these effects might be unwanted, but at least they are consistent now.
To reduce the memory footprint slightly, the formatted strings are discarded. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:49:59 +00:00
af7da72533 encapsule mbi initialization in write_multiboot_table, where it belongs. (very
simple and trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:37:17 +00:00
736221f1b2 Make vsprintf reentrant. More importantly, eliminate global variable.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:31:37 +00:00
f2152ecf4f Major cleanup of i386 tables.c:
* fix copyright messages
* remove all HAVE_HIGH_TABLES and HAVE_LOW_TABLES preprocessor hackery
  and instead use high_tables_base to find out if high tables should be used.
  The code path with high tables disabled and high tables not available for
  another reason should be the same.
* put MP-table into Fseg instead of 0x10. This allows us to drop an huge and ugly
  portion of code. And it will make some ugly Linux warnings go away.
* use ALIGN macro instead of hand crafted aligning.
* renumber post codes in this piece of code (don't jump ahead and
  back anymore)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:07:44 +00:00
a84a99b994 Various fixes to the tree to get coreboot-v2 to build on Solaris
- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
  the Solaris version behaves differently, but CURDIR is a safe
  choice on gnu make (and we require gnu make already)
- Use tail -1 instead of tail -n1 in a file that already relies on
  tail -1 support in another place
- Use tail -1 as alternative to tail -n1 in another place
- Use #define for ulong_t in romcc, as that name is used on Solaris
- Avoid fprinting a null pointer. The standard doesn't mandate that
  this is a special case, and Solaris doesn't implement it that way.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:03:51 +00:00
d1185bfd35 Attached patch moves the CBFS payload loader to selfboot.c as it's
the only selfboot user in CBFS.

This way, CBFS can be used without importing selfboot.c, as long as
no payloads are loaded.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 14:00:49 +00:00
58bb497f89 the i82801xx driver does not know ide{0,1}_enable in its chip.h, so comment it
out in the mainboard config file. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 13:03:30 +00:00
069385fcb3 ops can not be const because of the pci conf1/conf2 hackery we do. trivial
patch, just removes the warnings like
coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c:73: warning: initialization discards qualifiers from pointer target type


Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 12:58:00 +00:00
69390dbba1 acpi.c: add a cast to remove warning (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 12:33:52 +00:00
4b556a16d3 remove some dead code from cpu.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 12:33:06 +00:00
3a5c27763f Cosmetic cbfstool update (trivial)
* remove some dead code
* fix indentation
* comment in some destructors and fix some other warnings 
* use HOSTCC instead of CC (not all the way cosmetic, but very simple)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 12:22:10 +00:00
bbe29ee06e keyboard driver: function definitions should not omit void if they don't take
parameters.  (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-23 22:02:31 +00:00
e2825504fd fix comment in keyboard driver (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-23 22:00:58 +00:00
5e445c5fee Make the getpir output look less crappy and add a license
header template, as people keep forgetting them.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-22 18:17:06 +00:00
cf7f148ac8 Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr
tree it was copied from.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-22 16:03:04 +00:00
54336fde0e Defaulting to the board's default size is the correct thing to do.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 15:12:39 +00:00
d385ed29b9 This change adds PPC support to libpayload, and hooks it up in the build
process.
The PPC support is still stubbed, with commented out x86 code as guide
line for an implementor.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21 10:02:52 +00:00
1e6f6929c1 Trivial update of Config-lab.lb so that it works again.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-19 18:15:49 +00:00
c9a6f0f442 Add type field to memranges, and fill it from the source data.
type field contains e820 type ids, which are used by coreboot
and multiboot (the two source formats), so they can be used
as-is.

The MEMMAP_RAM_ONLY define is a way to allow a payload to opt
for only having CB_MEM_RAM type fields, which might be helpful
to support older payloads easily (just add the define, and it
won't encounter "weird" fields)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-17 20:36:45 +00:00
56ae8fcb6f This patch implements a "flash friendly" value for initialized areas of flash.
It makes the write part of flashrom dramatically faster with small
payloads like filo; and it also eliminates unnecessary wear on flash
by not writing zeros (it's unlikely this really matters; let me know 
next time you flash a BIOS flash 100,000 times!). 

More importantly, it allows for future partial flash upgrades with cbfs. 

Note that uninitialized_flash_value is a global that can, if we ever need it, 
be set by an argument in main. Assuming we ever see a flash where the 
"erased" value is 0, not 0xff. 

At the same time, "erased" value has been "1" on every EEPROM or 
FLASH I've used for some time now. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-16 23:05:20 +00:00
d12acea520 There were a few updates lately that generates ROM size > 512K. I am changing the default ROM size to 1M to accommodate this and future changes. I tested on SimNow family10h_1p.bsd and it POSTs OK.
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-15 18:02:25 +00:00
99fd2a3b3a Update equivalent processor revision ID to load latest microcode patches and
register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14 23:42:41 +00:00
9ea1e0c18a Trivia: remove comment
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Vincent Lim <vincent.lim@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14 22:11:08 +00:00
fed6475f6e From AMD family 10h Processor BKDG (rev. D): a platform is capable of having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores.
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14 22:00:28 +00:00
671cedc92f #136: failed to boot under KVM\QEMU
> -------------------------------------+--------------------------------------
>   Reporter:  silicium@…             |          Owner:  somebody
>       Type:  defect                 |         Status:  new
>   Priority:  major                  |      Milestone:
>  Component:  coreboot               |        Version:  v2
>   Keywords:                         |   Dependencies:
> Patchstatus:  patch needs review     |
> -------------------------------------+--------------------------------------

Fix use of uninitialized pointers. To help in future, move 
the declaration to the same scope as the use. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14 21:26:28 +00:00
67befdc22b The cbfstool print command should pretty-print the type of components that are
type 'deleted'.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-14 03:00:15 +00:00
df042a18ec This patch fixes a segfault when a file too large to fit is added to a rom
image.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 20:11:04 +00:00
a064b5239d Add support for human-friendly component string types for the cbfstool add
command.

Make use of it in config.g (Myles)

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 20:08:28 +00:00
5eceb32a79 Allow dynamic size for the {s,}elfboot bounce buffer.
Use that to fix selfboot with compressed payloads.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 16:27:25 +00:00
8f047de352 Make ACPI with low and high tables work again. The RSDP contained a
bogus RSDT pointer due to a wrong order of commands.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 14:39:59 +00:00
4b35354d39 Remove a shadowed variable and an unnecessary local variable in cbfstool/fs.c.
It is nearly trivial.

Signed-off-by: Myles Watson<mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 02:48:58 +00:00
5f0482dd8b Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 02:47:14 +00:00
459259e98d This is the final patch that got everything working for me with the HP dl145g3.
I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That feature was
explicitly disabled by the factory BIOS.
Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS)
than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read
config space of a device that is actually not present.
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
./cbfstool coreboot.rom add-payload filo.elf img/FILO

Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 15:15:07 +00:00
1c7cf64f1e This fixes a rather silly bug in cbfs with filenames > 16 characters.
Tested to booting linux with qemu. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson<mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 15:06:54 +00:00
67ee8f86fb There's no 'svg2pdf' in Debian AFAICT, probably the same problem on
other systems too.

So, check for svg2pdf, convert, and inkscape and use the first one that is
found to convert the SVG files to PDF.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 14:24:25 +00:00
019b5f4230 I guess a couple of function calls pushed these boards over the 0x1700 edge on
the build server.

Add Config-abuild.lb to fix s2892 & s2891.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 14:14:54 +00:00
8d27248682 Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 14:03:12 +00:00
503959c356 Fix pdflatex build issues (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 14:01:14 +00:00
cd5d7566d3 Use the debugging functions to print out the tree and resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12 13:43:34 +00:00
bb3d8128ed Bring v3-style debug output to v2. Fix a minor typo.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 22:45:35 +00:00
0520d55f5b This patch adds high table support to qemu. It was already added to
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c

It also adds a driver for the ISA device that is found when using
0.9.1  If you look in a log without this patch you won't find the RTC
init lines.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 22:44:14 +00:00
032a9653a6 Trivial white space fixes so that the next patches are easier to read.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 22:24:53 +00:00
7c29dada3e We should separate the it8718f_24mhz_clkin like the way IT8712 does.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by; Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 13:45:11 +00:00
dcda7fd527 Fix manual build on the Kontron board (trivial).
A manual build was yielding section overlaps, so increase
ROM_IMAGE_SIZE to the same size the Config-abuild.lb is using.

Build-tested by me using a manual build.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 01:44:54 +00:00
c720795868 Following patch fixes the XIP computation issue. I removed the normal image
because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)

This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-10 20:35:18 +00:00
442fc92b1f I would have liked to get an ack, but the error this corrects is pretty
critical, since unless it is fixed this tool creates empty tables that cause
coreboot to (in some cases, e.g. on qemu) triple fault and die. 

For the record, an empty option_table is not allowed. The table must, 
at least, have 3 32-bit entries in this order: 
type -- should be 200, 0r 0xc8, i.e. 0xc8, 0, 0, 0
size of table in LE order, 4 bytes
size of header in LE order, which is always 12,0,0,0

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-09 17:14:58 +00:00
b534e42565 Trivial clean up of print usage and parameter checking.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 20:07:00 +00:00
475aeda9d6 Add -Werror to help us keep the code clean.
Change sizes from unsigned int to int.
Clean up some usage and parameter checking.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 19:39:15 +00:00
83b8f0c485 I have made a very simple mod to cbfstool that is compatible with the
src/lib/ code in coreboot. I.e. the tool changes but the coreboot code
does not.

Currently, as cbfstool manages the ROM, there are files and empty
space. To allocate files, the code does, first, a walk of the headers
and, if that fails, does a brute-force search of the rest of the
space.

We all agree that the brute-force search has lots of problems from a
performance and correctness standpoint.

I've made a slight change. Instead of an "empty space" area with no
valid headers, I've made a header for the empty space.

So cbfs creation looks like this:
- set up the boot block
- create a file, of type CBFS_COMPONENT_NULL, that contains the empty
space. CBFS_COMPONENT_NULL was already defined in cbfs.h

Here's an example:

[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs create 1048576 2048
(cbfstool) E: Unable to open (null): Bad address
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
                              0x0        0xffffffff   1046456

So how do we create a new file?

It's easy: walk the files and find a file of type CBFS_COMPONENT_NULL,
which is as large
or larger than the file you are trying to create. Then you use that file.
- if the file is the same size as the NULL file, then it's easy: take it
- if the file is smaller than the NULL file, you split the NULL file
into two parts.

note that this works in the base case: the base case is that the whole
storage is CBFS_COMPONENT_NULL.

Here's an example of adding a file.
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed t
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
t                              0x0        stage        23176
                              0x5ab0     0xffffffff   1023240

Note that the NULL split and got smaller. But the entire ROM is still
contained by the two files. To walk this entire rom will require two
FLASH accesses.

Add another file:
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed tt
[rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
t                              0x0        stage        23176
tt                             0x5ab0     stage        23176
                              0xb560     0xffffffff   1000024
[rminnich@xcpu2 cbfstool]$

So, taking current ROMs as an example, I can reduce FLASH accesses for
cbfs from (potentially) thousands to (typically) less than 10.

Index: fs.c
Changes for readability and cleanliness. Move common blobs of code to functions. 
New function: rom_alloc,which allocates files by finding NULL files and using/splitting. 
Other changes as needed to support this usage. 
Index: util.c
Creating a cbfs archive now requires creation of a NULL file covering the file system space. 
Index: cbfs.h
Add a DELETED file type with value 0. Any file can be marked deleted by zero its type; this is a 
FLASH-friendly definition for all known FLASH types. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

I think it is a step in the right direction.  Could you add the
function prototype to cbfstool.h?

Acked-by: Myles Watson <mylesgw@gmail.com>
(I added the prototype)




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 19:23:00 +00:00
aa1df9cba5 Trivial fixup IRQS on IP1000 and RM4100.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 00:45:47 +00:00
9b04724a0a Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 00:24:24 +00:00
06025df741 Disable the AC97 modem via the ICH4 LPC disable function register early in the boot process.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-08 00:19:13 +00:00
919b56e6ea Trivial checksum fixup for irq tables on IP1000 and RM4100.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-07 05:47:05 +00:00
2ac37ca113 Fix my last commit. I looked at the wrong dead laptop.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-07 00:21:02 +00:00
0dae44c71f Support for detecting the SMSC FDC37N869 (trivial).
No datasheet available, chip identified by probing and looking at the PCB.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-07 00:03:18 +00:00
1bb3675c19 Fix a bug introduced in the copy_and_run refactoring.
The new code always decompressed to dst (as it should)
and then jumped to _iseg, when it should jump to dst.

With dst != _iseg this breaks (coreboot_apc)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-05 14:06:20 +00:00
f95b49eeb8 This patch removes these warnings:
Makefile:435: warning: overriding commands for target `src/lib/memset.o'

And replaces these debug messages:
partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8>
part pci_domain
with:
partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-04 20:27:09 +00:00
ef04d82ec6 The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change.
I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-04 19:26:43 +00:00
4f0154c937 Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 21:30:57 +00:00
88e71e8859 Run dos2unix on all files:
find . -type f| grep -v svn | xargs dos2unix

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 12:42:30 +00:00
a0dbddff17 Trivial, update email address.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 00:59:03 +00:00
fff297327d Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 00:50:58 +00:00
3544c6b3b0 Trivial removal of svn:executable property from vga.c.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 14:33:19 +00:00
03c65ef4e7 This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 - PS/2 Mouse.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 04:53:58 +00:00
5252b1184a This patch changes the default rom emulator to VM86.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 04:44:36 +00:00
97e6dfed12 This patch allows a custom vga driver that will give the flexibility to run code after vga is initialized for tv-out.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 04:37:13 +00:00
96a46920f2 Trivial patch to make #defines generated from cmos.layout have unique names. Kills a few more compiler warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 04:36:38 +00:00
183cadda26 Trivial cosmetic fixes to IP1000 and RM4100 irq_tables.c Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 03:04:20 +00:00
041734d859 The semantics of the changed code are pretty simple and looking at
other parts of the same file shows that it is a common construct.

Remove the shadowed variable.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 02:24:40 +00:00
fa12b67771 Remove warnings from compilation of the s2892 with and without CBFS.
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.

For shadowed variable declarations I renamed the inner-most variable.  

The one in src/pc80/keyboard.c might need help.  I didn't change the
functionality but it looks like a bug.

I boot tested it on s2892 and abuild tested it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 22:45:41 +00:00
d233f363c1 Some driver fixes for libpayload:
- fix minor bug in serial driver.
- latest USB stack fixes
- fix dead store in options.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 16:46:12 +00:00
b5fb0c5c4e Add high tables support to all northbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 13:58:42 +00:00
6841ce6537 Trivial fix for tyan/s2735: a newly used option wasn't defined as "used"
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 12:53:00 +00:00
94875b3f62 Add "printk" support to all CAR targets
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 10:16:39 +00:00
c7757f20ac * Use latest version of intel microcodes from their Linux drivers page for
models 6ex and 6fx (core and core2 solo and duo). Also, use the names suggested 
  by Intel for the microcode files instead our short version of it. This allows to
  create new microcode patches with a simple set of scripts.
* some minor cpu setup fixes for c and p states

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 10:14:22 +00:00
9cf95bfc64 And add the new file I forgot to "svn add" in the last commit.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 07:23:15 +00:00
12aba82e55 Refactor copy_and_run so that it uses a single code base instead of
3 (with one of them way too much assembler code).

On the way, I had to make some changes to the way the code is built, 
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as 
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects 
lots of post-raminit code (memcpy doesn't really make sense before 
raminit, or at least CAR)

The coreboot_apc code (AMD boards) gained some .c includes because I 
don't know that part of the code enough to really rework it and only 
have limited possibilities to test it. The includes should give an 
identical situation for this part of the code.

This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 07:07:22 +00:00
a43ee75d9a increase image size
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-29 20:34:41 +00:00
1ff26a7778 working memalign version for libpayload. This fixes problems with the USB stack
in FILO.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-29 19:11:18 +00:00
2c9617dc94 Mostly cosmetical changes.
- #if 0 some incomplete, non-working code instead of failing half way through
  the function
- Don't read a NULL pointer in wclrtoeol

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-29 19:10:10 +00:00
0ae0bcefe1 don't initialize "in" as it is initialized again one line below.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-29 19:09:19 +00:00
76b5d20d78 getopt for libpayload. in case someone wants to pass parameters to payloads and
parse them.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-29 19:08:29 +00:00
b8a939eab5 dd the family10h Rev C0-C2 support to coreboot.
Signed-off-by: Vincent Lim vincent.lim@amd.com

Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 16:36:16 +00:00
870f0133f4 fix warning: no return statement in function returning non-void
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 14:49:50 +00:00
1b04403e7f Only add ACPI tables if ACPI is enabled for the board.
Trivial fix to make abuild happy.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 14:49:21 +00:00
a19f644799 Enable HAVE_HIGH_TABLES by default for northbridges with
support for it.
The related mainboards don't need to activate it
themselves anymore.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 14:18:16 +00:00
bccaafc677 add_mainboard_resources is necessary for some boards (eg. kontron), but
this generic code could be added to the caller of
add_mainboard_resources (wrapped in HAVE_HIGH_TABLES, of course).
That way, boards that really need it (for other things) can use this
function, while others don't have to do anything to use
HAVE_HIGH_TABLES.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 12:57:25 +00:00
d107593691 Add high table support to via vt8454c.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 20:19:48 +00:00
55faef348a Add high tables support for Supermicro H8DME.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 20:19:06 +00:00
2d0b93bb54 Special handling for MP table in low memory is only necessary if there are
tables in low memory.

This removes a hang when HAVE_LOW_TABLES=0 and HAVE_HIGH_TABLES=1. With this
patch I can boot all the way to a payload. Tested on a Supermicro H8DME.

Many thanks to Patrick Georgi for figuring this out.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 20:00:29 +00:00
1670857cc9 Migrate via/vt8454c to CBFS.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 18:31:09 +00:00
932257869f Create a valid stack pointer after leaving CAR, so function calls don't
reset the machine in the small window between CAR and coreboot_ram.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 18:26:43 +00:00
bc9de2f1e2 Revert 4099 patch that causes an ECC error. Memory has to be written while ECC
error checking is disabled.  The purpose of the patch was to preserve memory
used by ACPI resume code.  One possible solution is to read that memory and
write it back while ECC error-checking is disabled. 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-27 16:08:26 +00:00
0d6ce50a1e Change Flashrom's URL to svn://coreboot.org/flashrom/trunk.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-26 19:50:53 +00:00
6388d49143 Flashrom is now moved over to its own repository.
Add a note to the coreboot-v2 version of the tree that
contains the new location.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-26 18:17:40 +00:00
bb2c61d844 Use pci_rom, as we have it. Thanks Myles!
trivial patch.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-26 07:20:45 +00:00
79cba771fc Trivial: allow "," in filenames
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-26 07:15:19 +00:00
b61bc7c68a Enable CBFS for qemu and kontron. Both are builds-and-runs
tested, incl. optionrom-in-cbfs for kontron, and compressed payloads
for both.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 22:15:29 +00:00
baa4374cad The flashrom makefile wants to redirect both stdout and stderr to
/dev/null for one compile test.
The old variant of using &>/dev/null works on bash and zsh, but not on
dash and tcsh. dash and tcsh interpret it as "background command and
truncate /dev/null" which is not what we want. >& works on tcsh and
bash, but it is not POSIX compliant.
Since make uses /bin/sh and /bin/sh has to be POSIX compliant, we can
use the POSIX variant of stderr and stdout redirection.

>/dev/null 2>&1
is POSIX compliant. This is specified in SuSv3, Shell Command Language,
sections 2.7.2 and 2.7.6.

Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 22:07:28 +00:00
dcce5210c7 Make the CBFS file lookup skip file data instead of brute-forcing
its way through it, looking for magic numbers.
For one, it should speed up file access, esp. with many entries,
but it also helps against false positives (eg. seabios, which
contains the magic number for its own CBFS support, which _might_
just be aligned properly)

Also avoid infinite loops and give up searching for new files for
invalid magic numbers.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 14:39:12 +00:00
72631a01fa The master cbfs record was located at the end of the flash and overwrote
anything that was there.  For ck804 or mcp55-based machines that was the
romstrap.

The fix is simple:
1. Put the master cbfs record above the bootblock instead of on it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 12:39:04 +00:00
fe62016512 Enable cbfs payload compression (the "l" flag) if payloads are
supposed to be compressed (with lzma only, as cbfstool lacks
nrv2b compression support for now)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 07:33:25 +00:00
369bc7882a Move decompression further down the code flow, so that - where
possible - code is decompressed directly to the right place
(instead of copying around, as before).

The downside of this approach is that it's not possible (without API
changes to the decompressors) to put partial segments into bounce
buffers. So if a segment collides with coreboot _and_ is compressed,
it's bounced entirely.
But, as this only brings back the copy we already had before, the new
worst case is better than the average before.

It also fixes handling of compressed segments.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-25 07:32:24 +00:00
7994164a0e Remove the inclusion of lzma.c (which really contains code)
from another (rom_stream.c and others), instead linking it like any
source file should be linked.

The same should (and will) be done with nrv2b.c, but that has some
deeper implications as various CAR implementations include that
directly, and thus requires more care.

It fixes an issue with the cbfs code.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 16:44:34 +00:00
a5de85cb86 MAX may already be defined. Also, fix smaller cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 16:17:41 +00:00
2895c45486 Another v3-style #ifdef in v2 to kill
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 10:23:56 +00:00
7d0ff4c126 These are some really horrible bugs that got through.
(and, for the record: no more #ifdef in coreboot. We're not going to
have this happen again. If we do have it in v2, let's remove it.)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 06:32:29 +00:00
cec6dc4c15 Change the behaviour of the ACPI generating code so it only
writes at most one full ACPI table.
In the cases where both HAVE_LOW_TABLES and HAVE_HIGH_TABLES
are enabled, the table is written to high memory, and an RSDP
is written to the low memory that points to the high mem one.
All other cases work exactly the same way as before.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 06:28:48 +00:00
e9149038ee Remove duplicate code.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-24 06:27:31 +00:00
6a30a5f891 flashrom: Support MX25L3235D
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 22:51:56 +00:00
424638e7bb Add 'install' target for ectool (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 22:22:47 +00:00
06db2c4482 Fix an uninitialized variable. If it didn't end up being zero it sometimes
caused a seg fault, sometimes executed somewhere else.  Also add an error if
the algorithm is unknown.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 18:46:32 +00:00
436b9de0a3 This patch cleans up Makefile generation. It removes the
coreboot.romfs file since CBFS will eventually be the standard.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 17:01:37 +00:00
a44228c435 Don't duplicate option description in README, the manpage already has
that info. Also, additional small cosmetic fix.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 14:57:55 +00:00
72deb69ce1 Add VERSION to hp/dl145_g3. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 13:41:12 +00:00
4940ab7a21 This patch hooks up git mirrored svn revisions and adds some
error checking to the svnrevision call.

If a .svn directory exists in the top level directory and the svnversion
utility is available, we use svnversion.
Otherwise, if a .git directory exists in the top level directory and the
git utility is available, we use git log.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 13:05:45 +00:00
2c245ff70e This continues the doco attempt.
This also mentions some ideas on the new booting setup for v2. 

The latest changes will remove all need for people to do math. 

With Peter's corrections as well. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-23 03:59:33 +00:00
476053356b Instead of just
coreboot-v2 $ util/abuild/abuild -t kontron/986lcd-m $PWD

you can now also say 

  coreboot-v2 $ util/abuild/abuild -t kontron/986lcd-m/Config-myconf.lb $PWD

and instead of using Config-abuild.lb or creating a temporary Config-abuild.lb,
abuild will use the existing Config-myconf.lb to build your image. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 23:39:19 +00:00
9f0f1055f2 Sometimes when we debug the code, we need to know which version we are
working on.
Add the svn revision to the coreboot version string.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 23:27:25 +00:00
f182456013 mini fix to reliably compile inteltool on darwin, and on Linux both on x86/x86_64.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 23:17:44 +00:00
554fce6ced makes the smi handler a little bit less verbose
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 22:55:15 +00:00
d6196a494c fix compilation of hp dl145
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 22:43:02 +00:00
6315274cc8 This patch fixes the parser. '|' has special meaning so [|] is used.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 22:25:45 +00:00
85b851add8 Convert 12 more boards to use include statements in Config.lb.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 22:08:00 +00:00
723bf0c568 Trivial patch. I forgot to update K8_SET_FIDVID.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 20:41:42 +00:00
5b34bdd3e5 This patch adds the target hp/dl145_g3 together with
the appropriate mainboard sources.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>

I updated some whitespace and the Config files. - Myles


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 20:34:05 +00:00
21da019a1e This patch add rudimentary support for the superio functionality of
the Serverengines Pilot BMC chip. Necessary to get serial out on the
HP DL145 G3.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 20:30:42 +00:00
d9b1c4f42f This patch adds support for the BCM21000 (aka HT-2100)
PCIe bridge.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 20:27:53 +00:00
6f52d11e9e drop duplicate compiler options that are already mentioned in CFLAGS.
(scan-build chokes on this)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 18:16:20 +00:00
4d59eaa93b - printed CBFS rom address was always 0
- drop dead code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 16:32:18 +00:00
f96c2d96a8 fix warnings, shadowed declarations and style guide violations (all trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 16:23:47 +00:00
7faa7d6bde increase rom sizes for abuild
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 15:49:28 +00:00
e5b44ab4dc All "unknown xy SPI chip" entries claim to have status UNTESTED for
probe/read/erase/write. That is incorrect.

A bit of confusion comes from how the #defines are named. We call them
TEST_BAD_*, but the message printed by flashrom says:
"This flash part has status NOT WORKING for operations:"

Something that is unimplemented is definitely not working.

Neither of the chip entries mentioned above has erase or write functions
implemented, so erase and write are not working.
Since their size is unknown, we can't read them in. That means read is
not working as well.
Probing is a different matter. If a chip-specific probe function had
matched, we wouldn't have to handle the chip with the "unknown xy SPI
chip" fallback. I'm tempted to call that "not working" as well, but I'm
open to discussion on this point.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 13:33:43 +00:00
8afdb1c433 drop unused variable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 12:38:23 +00:00
afa5985433 no duplicate names in cmos.layout allowed. (fixes a bunch of boards)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 12:35:57 +00:00
257ae3f520 Quick 'indent' run on ectool with some additional manual cosmetic fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 12:28:14 +00:00
0408bdd240 don't ignore return values (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 12:14:39 +00:00
570933cad8 remove some style guide breaks and warnings from raminit_f_dqs.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 12:00:17 +00:00
38c49fddde argh... never redo parts of the original patch on the fly. This fixes the tree
again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 09:06:38 +00:00
73d5daaf97 * Allow coreboot to use the full 256 bytes of CMOS memory
* Make functions out of the accessor macros in mc146818rtc.c
* don't hide reserved cmos entries from coreboot, only from the user.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 09:03:08 +00:00
953253f093 This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
combined socket_mPGA604. No other sockets come with clock rates, and there is
no difference in code, except for the number of microcode patches included in a
build.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:56:50 +00:00
da65fbf208 Factor out acpi_create_madt_lapics. It can be used on all ACPI boards.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:18:37 +00:00
7e9771cc1a * move i386 / ACPI dependent code out of hardwaremain.c and into the i386
acpi code.
* add some defines for FADT flags

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:17:38 +00:00
18d7320d17 Remove the requirement for payload.sh files to be executable. This
helps if the file is generated from patches, esp. if that happens
often (eg. with quilt)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:10:48 +00:00
6af0cb6efc Trivial removal of a freudian slip.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:07:31 +00:00
b5ab323a40 A small utility to dump the RAM of a laptop's Embedded/Environmental
Controller. Nothing fancy, does not know any laptops, EC types, or what
the values mean. It just dumps them. For the dump method, have a look at
the ACPI 3.0b spec.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 07:23:00 +00:00
7e16bf3a55 - function prototypes do not need "extern"
- fix up debug messages of usb debug console
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 23:05:13 +00:00
c6236edd47 flashrom: Add support for Gigabyte GA-MA790FX-DQ6. This board uses
IT8718F LPC->SPI translation for the flash chip.

Tested by Mateusz Murawski.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mateusz Murawski <matowy@tlen.pl>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 23:03:20 +00:00
6fa0317637 remove a few warnings, and comments á la #include <foo.h> // include file foo.h
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 23:02:40 +00:00
4855f56df9 add define for Role-Based Error Reporting to PCIe defines (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 23:01:10 +00:00
5bba7529d2 fix a warning for a misnamed define, and make a debug message printk_debug
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 23:00:14 +00:00
507d843eb0 CONFIG_CHIP_NAME is dead (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 22:59:00 +00:00
236d1023de small updates as suggested by Carl-Daniel Hailfinger.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 22:05:50 +00:00
ebf2589e3b Update to this very old document
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 21:45:11 +00:00
df444bf68a Add a helper function to acpigen to create _PSD tables.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 20:34:36 +00:00
2d3e712d56 Add an "-l <num>" argument to abuild that sets the LOGLEVEL variables
to the specified value.

Only change Config-abuild.lb, as the others are for manual buildtarget
use - adding __LOGLEVEL__ there would kill the build as it isn't
replaced by the actual content.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 20:31:18 +00:00
16cdbb244c Eliminate various issues brought up by scan-build.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 20:14:31 +00:00
5cda45d5ec scan-build prefers -include over --includes=, gcc knows both.
With this change, romcc knows -include and the build system uses it.

Also use a full path to settings.h because scan-build has trouble
finding it otherwise.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 12:41:55 +00:00
7bd658873c flashrom: Support Macronix MX2512805D flash chip
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 01:47:16 +00:00
b9ceb65434 flashrom: Trivial indent fix
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 01:46:07 +00:00
b266f6fc16 Somehow svn add didn't work for the include files. Commit the remainder
of r4147.

Thanks to Myles' patch adding support for include statements,
refactoring Config.lb became possible.

Factor out ROM size calculation from Config.lb.
  
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
but it has to work around a parser bug. 

89 files changed, 209 insertions(+), 2415 deletions(-)
A total of 2206 removed lines.
  
Abuild works for all changed boards on khepri.

Myles writes:
I've tested serengeti for the failover portion and s2892 for the
nofailover portion.  ldoptions are exactly the same and they both boot
the same.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 00:25:23 +00:00
b5e10bcf1f Thanks to Myles' patch adding support for include statements,
refactoring Config.lb became possible.

Factor out ROM size calculation from Config.lb.
  
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
but it has to work around a parser bug. 

89 files changed, 209 insertions(+), 2415 deletions(-)
A total of 2206 removed lines.
  
Abuild works for all changed boards on khepri.

Myles writes:
I've tested serengeti for the failover portion and s2892 for the
nofailover portion.  ldoptions are exactly the same and they both boot
the same.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-21 00:16:06 +00:00
1089509725 After verification in datasheets, all MX25 accept the same opcodes
0x60 and 0xC7 for Chip Erase.

Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 22:54:13 +00:00
b88a1fcd80 A little more info. Failover docs are next, then proposed new mechanism
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 22:10:34 +00:00
feaaedc1cf This patch adds
cbfstool extract [FILE] [NAME]

It also factors out the csize calculation in rom_add, and fixes rom_delete so
that it can handle deleting the last entry.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 21:38:11 +00:00
2cecce5740 Continuing the slow doc-o update
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 15:36:57 +00:00
caf884ca8c flashrom: board_enables: reconstruct table.
This patch restores the pciid based board matching table. It makes this
table readable and hackable again, and the only disadvantage is that the
right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have
been string replaced by 0 to more easily spot missing ids, and extra
comments have been added to explain how the various entries are used.

Signed-Off-By: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 12:38:17 +00:00
4399d3c832 flashrom: Trivial README change Flashrom->flashrom
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 12:34:30 +00:00
dbda3a9919 Fix implicit declarations of done_cache_as_ram_main by adding a
prototype for these assembler functions.
Affected boards:
digitallogic/msm800sev
pcengines/alix1c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-20 12:02:25 +00:00
f5f0c69628 flashrom: MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-19 23:24:26 +00:00
15bbfb8418 Add MX25L1635D support, as discussed on #coreboot.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-19 23:04:00 +00:00
b5843ffcb0 There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18 23:04:28 +00:00
4365659fda drop the ChangeLog.cvsimport document from the transition from CVS
to GNU arch. Does anyone remember that? What a fun! 
All history is in the SVN repository, including the CVS and TLA parts,
so nothing is lost.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18 18:10:38 +00:00
c90bb4a1d9 Drop long-obsolete HOWTO, it's still available in wikified form at
http://www.coreboot.org/VIA_EPIA-M.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18 17:22:11 +00:00
d2a5a5abef s/LinuxBIOS/coreboot/.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18 14:18:20 +00:00
1458228b2e Add support for the ASUS P2B-D mainboard.
This is a pretty standard "yet another 440BX" target, so the code
is pretty straight-forward. It's a dual-CPU machine, which might need
some fixing, I'm booting with 'maxcpus=0' for now. It does boot
successfully up to a Linux login prompt, though.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-18 14:02:00 +00:00
b1ec2ac62d flashrom: Add VIA PC3500G board. It has SPI flash behind ITE8716 on LPC.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: illdred <illdred@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 23:01:45 +00:00
d1be3ba633 Add include to config.g
Usage: 

include path

path can be relative to the current directory or absolute starting at /src.

I tested it with:

include /config/absolute.lb
include relative.lb

in /src/northbridge/amd/amdk8/Config.lb
which included
   /src/northbridge/amd/amdk8/relatvie.lb
   /src/config/absolute.lb

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 17:58:34 +00:00
0346c22de6 Improvements for the coreboot v2 README:
- Point to the 'Payloads' wiki page for more info.
 
 - Document (most of) the build requirements of v2.

 - Point to the wiki for build instructions (wiki needs more docs, though).

 - Mention QEMU for testing coreboot, also point to wiki page.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 17:11:39 +00:00
ef5f8a73b4 Updating documentation as I get ready to put v3-style startup in (which
I have working in an early version in my tree).

Corrections welcome.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 16:18:02 +00:00
1eb1a61e07 There are two identical cfgfile rules in config.g. Remove one of them.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 16:11:24 +00:00
a80a61049b This patch allows you to add lines of the form
pci_rom PATH vendor_id = # device_id = #

to Config.lb files.  No more changing the ROM_SIZE to add an option ROM, and no more manual prepending.

Examples:

pci_rom ../ragexl.rom vendor_id = 0x1002 device_id = 0x4752
pci_rom ../nic.rom vendor_id = 0x1100 device_id = 0x4152

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 13:43:46 +00:00
aeba92ab5b Add VIA CX700 support, plus VIA vt8454c reference board support.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 08:37:18 +00:00
56c51bd120 This needed to be removed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-17 02:40:20 +00:00
e4be46b4c3 Following patch flushes the instruction queue when we set PE=0. This is normally
done by FAR JMP, but here it is more tricky because we run at EIP>1MB. Many
thanks to Marc and Kevin to tell me how to fix it

The trick is to use 0x66 prefix (done with ljmpl) it will allow to jump in real
mode to any EIP addresses  ;) 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-16 21:09:56 +00:00
f9fab37ecb I deleted mptable.c in my patch, but forgot to svn rm it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-16 16:42:05 +00:00
13e19216ef v2/src romfs->cbfs rename
romfs.c has been replaced by cbfs.c.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15 21:40:08 +00:00
472f3ffcf8 This patch cleans up mpspec.h and allows it to be included when
HAVE_MP_TABLE=0

It also removes the artifacts from the Asus m2v-mx_se that were
necessary before the change.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15 21:25:21 +00:00
4e006407ec Add -r|--remove option to force abuild to remove the output directory
after every board build, in order to save disk space if you don't need
the actual output files.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15 16:07:27 +00:00
d086e5d966 Some coding style and consistency fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15 10:52:49 +00:00
82144571ad r4097 broke the tree and it remains unfixed :-(
Repeat: Cosmetic patches shall not break the tree for 20 revisions.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-15 06:00:01 +00:00
57f6c08837 EPIA-CN does not have any ACPI tables. Fixes manual and auto build here.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 20:51:41 +00:00
45ae92ff1a util/cbfstool/tools/rom-mk*->cbfs-mk* rename
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 19:48:32 +00:00
483b7bbd77 v2/src romfs->cbfs rename
This also has the config tool changes in v2/util.

Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 07:40:01 +00:00
3935b19d9f fix up the tree.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 06:38:15 +00:00
ef4d7d4a67 util: romfs->cbfs rename
I noticed this before sed, but forgot to change it back after sed.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 00:26:24 +00:00
1d862ded11 v2/util: romfs -> cbfs rename
It's all sed here. romfs->cbfs, ROMFS->CBFS, romtool->cbfstool

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 00:08:34 +00:00
450b23fb2e v2/documentation: romfs -> cbfs rename
This is svn mv romfs.txt cbfs.txt and sed romfs->cbfs, ROMFS->CBFS along with
one manual change: CBFS_file->cbfs_file

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>                                


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14 00:01:34 +00:00
299a00feb8 Fix the build. This error was introduced by change in acpi.c, the acpi_slp_type exists only conditionally.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 21:42:49 +00:00
5c4f8392e0 Fix typo. Add missing copyright year.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 21:35:49 +00:00
c824b5844f Emergency fix. Most targets now build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 21:19:58 +00:00
743b635ca3 I need to do uses HAVE_ACPI_RESUME for each board. Here we go.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>

It should fix the build break introduced in r4101



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 20:07:26 +00:00
0fb21c4af9 The wake_vec must be HAVE_ACPI_RESUME guarded because PPC uses -Werror on this file.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Self ack, trivial fix:
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:44:06 +00:00
6bb6e03912 Following patch adds support for the ACPI resume on Asus M2V-MX SE. The ACPI
code just blinks the leds. The motherboard resources are use to reserve coreboot
used memory.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:37:17 +00:00
15bf50d820 Following patch adds resume (exit from self refresh) support for AMD K8 revF
CPUs. It handles both type of erratas on those CPUs.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:34:35 +00:00
33cafe5bfb Following patch implements ACPI resume support for coreboot. The hardware main
hook will come in separate patch perhaps.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:07:02 +00:00
497c8effce Following patch adds support for resume on VT8237 based motherboards. The NB
part of this patch adds support for resume well NVRAM. In which DQS values are
stored.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:00:09 +00:00
a572f83e71 Following patch adds necessary hooks and as well the compile time checks for
ACPI suspend/resume.

The memory cleared now is just the coreboot memory not the low memory.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 17:57:44 +00:00
3f04dade05 Fix the following errors:
In file included from
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93:
src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’:
src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of
function ‘activate_spd_rom’

In file included from
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101:
src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’:
src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of
function ‘soft_reset’

In file included from
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98:
src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’:
src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of
function ‘activate_spd_rom’

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 16:21:16 +00:00
6dcbe7f540 This patch cleans up the calls to $CC in mainboard Config.lb files. They
now all have the same parameter order.

action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS)
-I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -o $@"

The idea behind this parameter order is:
- *FLAGS at the beginning.
- Use a common set of *FLAGS.
- Include files and directories listed afterwards.
- nostdinc, nostdlib, no-builtin tell the compiler this is standalone
  code.
- Warnings. They do not influence source or compilation.
- Compilation strategy (small) and output mode (asm or binary).
- File to be compiled.
- Output name.
- $(DEBUG_CFLAGS) and -S are only used for asm output.


Other changes in this patch:

- src/supermicro/h8dme/Config.lb now uses $DEBUG_CFLAGS instead of
hardcoding the respective flags.

- $DEBUG_CFLAGS was added to asm outputting $CC calls:
supermicro/h8dme/Config.lb
lippert/roadrunner-lx/Config.lb

- $DISTRO_CFLAGS was added to some $CC calls in:
iwill/dk8_htx/Config.lb (CAR AP code)
supermicro/h8dmr/Config.lb (CAR AP code)
supermicro/h8dme/Config.lb (CAR AP code)
gigabyte/m57sli/Config.lb (CAR AP code)
gigabyte/ga_2761gxdk/Config.lb (CAR AP code)
amd/serengeti_cheetah_fam10/Config.lb (everywhere)
msi/ms7135/Config.lb (everywhere)
nvidia/l1_2pvv/Config.lb (CAR AP code)
-$CFLAGS was added to all $CC calls in:
amd/db800/Config.lb
amd/dbm690t/Config.lb
amd/norwich/Config.lb
amd/pistachio/Config.lb
amd/serengeti_cheetah/Config.lb
amd/serengeti_cheetah_fam10/Config.lb
arima/hdama/Config.lb
artecgroup/dbe61/Config.lb
asus/a8n_e/Config.lb
asus/a8v-e_se/Config.lb
asus/m2v-mx_se/Config.lb
broadcom/blast/Config.lb
digitallogic/msm800sev/Config.lb
gigabyte/ga_2761gxdk/Config.lb
gigabyte/m57sli/Config.lb
ibm/e325/Config.lb
ibm/e326/Config.lb
iei/pcisa-lx-800-r10/Config.lb
iwill/dk8_htx/Config.lb
iwill/dk8s2/Config.lb
iwill/dk8x/Config.lb
kontron/986lcd-m/Config.lb
lippert/roadrunner-lx/Config.lb
lippert/spacerunner-lx/Config.lb
msi/ms7135/Config.lb
msi/ms7260/Config.lb
msi/ms9185/Config.lb
msi/ms9282/Config.lb
newisys/khepri/Config.lb
nvidia/l1_2pvv/Config.lb
pcengines/alix1c/Config.lb
sunw/ultra40/Config.lb
supermicro/h8dme/Config.lb
supermicro/h8dmr/Config.lb
technexion/tim8690/Config.lb
tyan/s2735/Config.lb
tyan/s2850/Config.lb
tyan/s2875/Config.lb
tyan/s2880/Config.lb
tyan/s2881/Config.lb
tyan/s2882/Config.lb
tyan/s2885/Config.lb
tyan/s2891/Config.lb
tyan/s2892/Config.lb
tyan/s2895/Config.lb
tyan/s2912/Config.lb
tyan/s2912_fam10/Config.lb
tyan/s4880/Config.lb
tyan/s4882/Config.lb

- Use $@ wherever appropriate.

- Kill that evil CACHE_AS_RAM_AUTO_C variable.

- Trailing whitespace fixups on lines which were touched anyway.

We now only have 6 remaining different calls to $CC whereas before there
were 20.
If I am allowed to rename src/mainboard/kontron/986lcd-m/auto.c to
src/mainboard/kontron/986lcd-m/cache_as_ram_auto.c, we're down to 4
different calls.
If we can decide on the use of $CPU_OPT, we are down to 3 different
calls.

One additional point I'd like to clear up:
if ASSEMBLER_DEBUG
makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
end

"-dA -fverbose-asm" is only useful for asm output. For these flags,
DEBUG_CFLAGS is a total misnomer. What about calling them
DEBUG_ASMCFLAGS or somesuch?
"-g" should be controllable by a separate switch. It is useful even for
object code.


The following targets are broken by this patch because they contain
implicit declarations, but the error did not trigger due to missing
CFLAGS:
amd/serengeti_cheetah
asus/a8v-e_se
asus/m2v-mx_se
digitallogic/msm800sev
pcengines/alix1c
supermicro/h8dme
supermicro/h8dmr


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-12 21:47:09 +00:00
e86c65b62e The IT8712F needs to have the configuration bits changed to handle the power for
memory correctly during suspend.s

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-12 18:01:55 +00:00
7845fb59a2 Bring S2912 and S2912_Fam10 Config.lb in line with each other.
- Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c
- Compile apc_auto.c with $(DISTRO_CFLAGS)
- Clean up whitespace

If anyone can explain the remaining differences in Config.lb which are
NOT caused by the K8/Fam10 switch, I'd be glad to hear them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11 18:58:17 +00:00
a3ec56c17a This patch fixes an edge case for K8 raminit. Specifically, it brings the code
in line with the K10 code.

I was trying to use DDR2 800 (CL6) memory on an m57sli, but booting failed.
Marc Jones found this bug (thanks!), which fixes booting with this specific
memory. For the record, it was Crucial CT2KIT25664AA800.

I put the machine through a few days of use. It also succesfully passed a run
of http://people.redhat.com/dledford/memtest.shtml:

  $ ./memtest
  TEST_DIR:               /tmp
  SOURCE_FILE:            linux-2.6.29.1.tar.bz2
  NR_PASSES:              20
  MEGS_PER_COPY:          270
  NR_COPIES:              45
  PARALLEL:               no
  COMPRESS_RATIO:         5
  COMPRESS_FLAG:          j
  COMPRESS_PROG:          /bin/bzip2
  EXTRACT:                yes

  Creating comparison source...done.
  Starting test pass #1: unpacking, comparing, removing, done.
  Starting test pass #2: unpacking, comparing, removing, done.
  Starting test pass #3: unpacking, comparing, removing, done.
  Starting test pass #4: unpacking, comparing, removing, done.
  Starting test pass #5: unpacking, comparing, removing, done.
  Starting test pass #6: unpacking, comparing, removing, done.
  Starting test pass #7: unpacking, comparing, removing, done.
  Starting test pass #8: unpacking, comparing, removing, done.
  Starting test pass #9: unpacking, comparing, removing, done.
  Starting test pass #10: unpacking, comparing, removing, done.
  Starting test pass #11: unpacking, comparing, removing, done.
  Starting test pass #12: unpacking, comparing, removing, done.
  Starting test pass #13: unpacking, comparing, removing, done.
  Starting test pass #14: unpacking, comparing, removing, done.
  Starting test pass #15: unpacking, comparing, removing, done.
  Starting test pass #16: unpacking, comparing, removing, done.
  Starting test pass #17: unpacking, comparing, removing, done.
  Starting test pass #18: unpacking, comparing, removing, done.
  Starting test pass #19: unpacking, comparing, removing, done.
  Starting test pass #20: unpacking, comparing, removing, done.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11 18:09:03 +00:00
ebdc7c7cfe Kill remaining unneeded CAR/ROMCC if-blocks.
Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although
USE_DCACHE_RAM is always set for them. Such checks are not only
pointless, they actively make the files hard to read.

A full abuild run confirmed that compilation did not change with this
patch applied.

The patch does not change whitespace of the remaining code to ease
review and svn blame.

With this change, it should be possible to have two or three Config.lb
variants in total (except the actual hardware config). Right now, some
Config.lb have comments, some don't, some have empty lines for better
readability, some don't, some have leading whitespace, some don't. This
is an utter mess and unifying these files would certainly reduce the
headaches I have when looking at them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11 14:51:49 +00:00
4eb37059ce Mention a few more flash chip packages in README/manpage.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-11 13:59:00 +00:00
1da9a79a06 move architecture override before cross compiler detection, or the Sandpoint
skeleton will have get a cross compiler before it gets the architecture set 
to SKIP. Pretty much build system internal, so self-acked.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10 23:02:48 +00:00
708ccac6ee Add a note that 'modprobe msr' might be required.
Remove trailing whitespace. Fix typos.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10 21:05:56 +00:00
cd2cbf7200 Fix typo.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10 14:49:14 +00:00
a0eeef324f Various manpage / README fixes:
- Improve description a bit, especially wrt chip packages and
   protocols.

 - Add some missing parameters to manpage option descriptions.

 - Remove long obsolete DoC support note.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10 14:41:29 +00:00
8d9f932f2a unify spd_ddr2.h (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-10 12:27:42 +00:00
712f325237 Fixed the typo should indeed be a 0x2e.
Tested on an iWILL DK8-HTX board.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-09 14:28:36 +00:00
013c7cfab5 * commit previously forgotten romfs.txt
* fix a copy & paste error in src/lib/romfs.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-08 07:47:01 +00:00
d367037997 fix sandpointx3_altimus_mpc7410 target. We're back at all boards compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-08 07:21:52 +00:00
d40f7db2d9 Only build romfs on those target that have CONFIG_ROMFS enabled.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-08 06:41:06 +00:00
0de8b9111a This tested ok, but qemu can't really handle c0000 as RAM.
(trivial)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-07 15:38:17 +00:00
80775c1425 add Config-abuild for the new board (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-07 14:27:38 +00:00
4a8523a788 This is a bit of an emergency fix for qemu. Ethernet routing has not been
working. Given all the limitations of PIRQ routing we keep it simple
and just set the IRQ directly. Most BIOSes are doing setup this way anyways, 
since there are so many errors in PIRQ tables. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-07 02:18:13 +00:00
b3b7db777d This fixes a bug in romfs code; see comment. If we add the pci rom
to romfs for qemu,we get this: 
Check pci1013,00b8.rom
found it, @ fff99698, first word is e946aa55
In cbfs, rom address for PCI: 00:02.0 = 0
On mainboard, rom address for PCI: 00:02.0 = fff99698
copying VGA ROM Image from fff99698 to 0xc0000, 0x8c00 bytes

This is sort of OK, excpet that when it gets to payload time, the 
system explodes. I suspect that copy is kind of a problem. 

But this is a pretty important bug fix so in it goes. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 23:28:22 +00:00
308312ce6c Some changes for option roms:
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the 
%04x. 
- users pass in vendor and device id. 
- users pass in a dest. If the dest is 0, the address of the ROM image in 
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even 
in the uncompressed case).

move qemu over to always using ROMFS

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 20:38:34 +00:00
662d52d244 Add support for romfs to option rom loading.
Pretty simple: Find the rom in the romfs, if found, set dev properties so 
that the rest of the code works.

At some point, we can remove some of the other code, i.e. the first else, 
and stop requiring people to do math.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 16:03:53 +00:00
df77f345e7 (trivial) fix some warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 14:00:53 +00:00
da6d92ba11 Daniel Toussaint wrote:
As I mentioned a few weeks ago, I am in the process of porting this board:

http://www.technexion.com/products/embedded_boards/tim-8690-mt.html

This board has a dual BIOS , choosable with a jumper - much like the BIOS
savier from before - so it is a pleasure to work with as a linuxbios developer.

It is still a work in progress, however , I already submit the patch.
All on board devices and slots work as expected, only need some more stress
testing with the RAM, acpi, etc..

Signed-off-by: Daniel Toussaint <daniel@dmhome.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 13:38:54 +00:00
38891ab7e6 cross compilation fix for motorola sandpoint based boards
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05 08:43:44 +00:00
85107f28da two more totalimpact briq fixes. Gets us back to the romfs breakage on PPC
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05 08:39:13 +00:00
a73fc4b6c5 Makefile includes were mixed up.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 22:55:49 +00:00
9f243a1132 fix this warning:
coreboot-v2-4067//src/stream/ide_stream.c: In function 'stream_ide_read':
coreboot-v2-4067//src/stream/ide_stream.c:47: warning: declaration of 'offset' shadows a global declaration
coreboot-v2-4067//src/stream/ide_stream.c:13: warning: shadowed declaration is here

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 22:27:10 +00:00
dd0b6ff4dd fix this warning for the embedded planet ep405pc
/tmp/ccilLWBf.s: Assembler messages:
/tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 22:24:23 +00:00
14ad50edf6 This fixes a race condition (revealed by my other check-in r4067) in the
romtool by changing the Makefiles to be no longer recursive (once again,
recursive make is to be considered harmful).  Tried to (quickly) unify most of
the Makefile code, but medium-term this is going to be worked on for Kconfig
support anyways.

Also fix a sign cast error in rom-mkpayload in case people want to compile this
with -W -Werror

Patch relative to coreboot-v2/util/romtool

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
and
Acked-by: Stefan Reinauer <stepan@coresystems.de>
in order to get the tree working decently asap



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 22:18:26 +00:00
16e34b98a1 small workaround for romtool incompatibility with ppc ports
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 18:40:46 +00:00
e6cc67b07a build romtool in mainboard target directory.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 18:24:21 +00:00
8e304e6616 fix cross compilation in abuild for certain scenarios
(coreboot.org build system internal)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 18:16:11 +00:00
6e244da7a5 fix variable shadowing in lzmadecode.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 13:28:40 +00:00
be84b01e18 fix some warnings by casting safely. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 13:20:33 +00:00
962242ad2d use $(MAKE) instead of hardcoded "make".. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 13:05:18 +00:00
2ddacb60d4 fix configuration step of totalimpact briq and embeddedplanet ep405pc.
(trivial).

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 12:52:28 +00:00
2d2589e682 Fix the concurrency issue of building romtool.
romtool is still built in util/romtool, as happens without this patch.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 10:01:21 +00:00
d7a709a60f These are some cleanups and changes. These are build and boot tested on qemu.
Some changes for option roms: 
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the 
%04x. 
- users pass in vendor and device id. 
- users pass in a dest. If the dest is 0, the address of the ROM image in 
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even 
in the uncompressed case).

And some type and print cleanup. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 22:23:34 +00:00
ace2dc5962 Add u64 typedef to ppc (trivial)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 20:14:59 +00:00
7b6ea25f21 Fix up the incomplete commit in r4055.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:40:44 +00:00
edf480719a drop unused variables in generic smm handler. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:33:50 +00:00
2fd2c7901e drop another shadow variable (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:31:01 +00:00
f7116c3bd0 There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping
dead code around.

This patch removes ROMCC remainders from Config.lb and kills orphaned
auto.c and failover.c in the affected mainboard directories.

arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882

Abuild log is completely identical with and without the patch.

With this patch, the last ROMCC remainders for K8 boards are gone.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:29:35 +00:00
f16fb73087 I thought that romfs infrastructure is done now, but there were some
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 16:17:05 +00:00
d107831182 The attached patch tries new style compression first and runs old
style compression if the command returned an error code (happens if
you run an old lzma with the new arguments)

Tested on new-style lzma only (as I lack a build environment with
old lzma), but I tested that the old lzma returns with an error code.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 15:57:58 +00:00
48e8c3c36d Print a pointer as pointer, it's really trivial.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 15:02:08 +00:00
1b9a5c636e This patch implements --include=file.h for romcc.
The compile_file calls seem to be in the wrong order, but
romcc actually requires it that (probably some stack-like
file processing)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 14:04:06 +00:00
11f054a578 Next step. Kill auto.c and failover.c and clean up Config.lb for
tyan/s2735
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895

Abuild log is completely identical with and without the patch.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 12:55:55 +00:00
aed1f925a6 the attached patch is the last infrastructure change necessary for
romfs.
Everything else to make a target romfs aware happens in the targets.

What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build

Targets should still build (they do for me)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 12:52:43 +00:00
73ad326452 There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.

This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.

Abuild build log with and without the patch is completely identical.

More patches of the same type can be done, hopefully making
ROMCC dependencies a bit more clear for v2.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03 02:18:23 +00:00
e729846b64 Ronald Hoogenboom writes:
I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-02 23:08:16 +00:00
5cbdc1ee6f Fix typo.
trivial.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 22:07:53 +00:00
4ca5902b14 Updated microcode for for AMD Fam10 DR-B2 and B3.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 16:22:38 +00:00
90e0271b13 forgot this.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 16:06:33 +00:00
61dc06c060 (trivial) add filo call back for those few mainboards that still (need to)
use the built-in filo.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 13:54:16 +00:00
3081bdfa44 Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should
be used unconditionally, and the names don't hurt.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 13:43:21 +00:00
77cf00850f Forgot CONFIG_ROMFS for supermicro/h8dme.
Trivial fix, just add the defaults as with all other boards.


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 11:37:39 +00:00
c7798895d3 Add copyright notices to two files, src/boot/elfboot.c
and its derivative src/boot/selfboot.c.

The mail in which Eric asserts authorship on elfboot.c is
quoted below, selfboot.c was substantially edited by Ron.
With that information in mind the change is trivial.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



From: ebiederm@xmission.com (Eric W. Biederman)
Date: Wed, 01 Apr 2009 03:31:15 -0700
To: Patrick Georgi <patrick@georgi-clan.de>

Patrick Georgi <patrick@georgi-clan.de> writes:

> Hi,
>
> We found some file in the coreboot tree that we suspect is yours.
> Unfortunately,
> both copyright notice and license are missing.
> Could you please take a look at it, and state whether it's yours,
> and if so,
> what license is to be attached?

Yes. GPLv2

> The file in question is
> http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/boot/elfboot.c
> and its history goes back to
> http://tracker.coreboot.org/trac/coreboot/log/trunk/LinuxBIOSv2/src/boot/elfboot.c?rev=2890


Eric


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 11:03:32 +00:00
ae63126346 This code adds support for coreboot images that use ROMFS.
It also removes the call to FILO from hardwaremain -- that 
has needed removal for a long time. 

abuild tested.
Note that this code has been tested and works on 
both qemu and kontron. The changes to use it are coming 
next.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 10:48:39 +00:00
f834e20ba3 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 17:17:30 +00:00
ac369065cb fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 17:15:42 +00:00
45dffef232 fix shadow variable in compute_ip_checksum.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 16:42:57 +00:00
d469cdab93 Add the CONFIG_ROMS config variable.
Tested under abuild, causes no trouble. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 16:32:01 +00:00
420593e74d This fixes a shadowed declaration in multiboot.c.
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 14:11:19 +00:00
decdb3c647 cosmetic fix for function definition.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 14:10:42 +00:00
5d01ec0f80 This patch adds Jordan's romtool support for v2.
There are a few changes. The 20K bootblock size restriction is gone. 

ROMFS has been tested and works on v2 with qemu and kontron. Once this 
patch is in, those patches will follow. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31 11:57:36 +00:00
0f0f9bb9a2 flashrom: Board enable support for HP DL145 G3.
This is a BCM5785 based machine, WP# and TLB# need to be deasserted using
GPIO 2 and 5 from the PM registers of the southbridge.
This is very similar to the x3455 implementation.

Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-30 13:20:01 +00:00
3a8565a77b During the suspend/resume programming I came to an issue that first 4KB of
memory must be clear with 0s because otherwise the resources of K8 will be
totally messed up.

res = probe_resource(dev, 0x100 + (reg | link));

This is called with dev = NULL and this is no good for probe_resource at all.
The attached patch fixes the potential problems and of course the problem
itself. On one particular place was missing test if the device really exists.
This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
The rest of the patch is just very paranoid and do all checkings.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
--This line, and those below, will be igno
red--

M    src/devices/pci_ops.c
M    src/northbridge/amd/amdk8/northbridge.c
M    src/northbridge/amd/amdfam10/northbridge.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-26 21:45:26 +00:00
83da8dcf60 - List SMSC LPC47N227 runtime register block as supported.
- Add missing contributor in README.

- Cosmetic fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-25 17:38:40 +00:00
951c63f2a5 The latest ucode patches for Family 10h:
9fh for RB/BL/DA Rev C;
96h for DR Rev B.

Signed-off-by: Zeng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-25 15:47:58 +00:00
b8e2517055 Every object file with a struct pci_driver ... __pci_driver needs to be marked
as "driver" instead of "object" in order to get the init code actually
executed.

This patch fixes up all northbridges that did not do this before.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-24 12:28:44 +00:00
5f28c09ce5 msrtool: If an MSR name lookup fails in msraddrbyname(), return the strtoul() conversion result.
Thanks to Mart for finding and reporting the problem!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-23 17:43:12 +00:00
4b10ab3782 To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21 11:52:29 +00:00
9e9fa825fd To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21 11:50:20 +00:00
2a63ea580a Kevin O'Connor said:
The bug is in src/arch/i386/boot/boot.c.  The inline assembly in
  jmp_to_elf_entry uses the "g" flag to pass in parameters.  However,
  "g" allows gcc to use stack relative addressing of parameters.

  Easiest fix would be to change "g" to "ri" - put the parameter either
  in a register or as an immediate value.

That's what this patch does.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20 18:29:49 +00:00
5dd4a20b96 Add Supermicro h8dm3 mainboard. This is mostly a copy from the h8dmr.
The one issues is the SPD address switch for the second CPU. That means that
the memory must be an exact match on each CPU.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20 16:36:05 +00:00
2f4979f347 Fix CPUID typo. This caused fid to memory speed calculations to be off.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20 16:03:37 +00:00
5182f67590 Move the Atmel AT45 comments about block and page sizes from the end of
the struct to the individual struct members to improve readability.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19 12:18:13 +00:00
d0db8f904d fix the following warning on all boards that don't have PIRQ_ROUTE enabled
In file included from coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:2:
coreboot-v2-4017/src/arch/i386/include/arch/pirq_routing.h:45:5: warning: "PIRQ_ROUTE" is not defined
coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:103:6: warning: "PIRQ_ROUTE" is not defined

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19 01:30:16 +00:00
c675955f05 fix totalimpact briq compilation. the target had a cpu specific and a mainboard
specific clock.c. Since no other target uses the same cpu, I commented out the
CPU's clock.c. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19 01:13:01 +00:00
1233054fbe add YABEL flag to options to decide wether access to devices other than the one yabel is running for is possible
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Tested and Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-18 16:25:34 +00:00
5f7d506ae7 Add high coreboot table support to libpayload
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 16:41:01 +00:00
927377febe Add support for high coreboot table to mkelfimage
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 15:33:41 +00:00
b743885b43 Don't know if this is the correct fix, but it fixes compilation of the PPC
targets.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 15:15:15 +00:00
764fe40f09 This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:39:36 +00:00
3f72e32b06 This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:39:25 +00:00
efab4ba3bb This patch adds "high coreboot table support" to coreboot version 2.
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.

By moving the table to the high tables area (if it's activated), this problem
is fixed.

In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.

This patch also adds "table forward" support to flashrom and nvramtool.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 14:38:48 +00:00
5d6645ae44 - TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in the
DSDT and use the dynamic TOM2 variable instead.
- The DSDT needs to be revision 2 or above to handle 64 bit variables.
  This will require a recent (not older than 2007) iasl (ACPI compiler).
- Fix an incorrect comment.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17 01:47:25 +00:00
4d01bd5809 drop empty directory. (trivial)
Signed-off-by: <stepan@coresystems.de>
Acked-by: <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-16 17:28:07 +00:00
ec75a57e36 fix typo in pci_device.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-16 15:27:00 +00:00
6d07c932bb Fix all build problems on PPC except the _SDA_BASE issues caused by the
code expecting too old binutils(?).

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15 10:04:41 +00:00
8f556be766 abuild: Don't forget CROSS_COMPILE anymore.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15 09:55:17 +00:00
2f110a8006 trivial patch for abuild: allow powerpc-elf-gcc, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-14 16:33:22 +00:00
2075dbea45 add YABEL Debug Flags to Options
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-14 15:43:42 +00:00
84a1f4e261 this commit should fix Ticket #122 (proper log files for all builds)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 17:22:53 +00:00
cb2de6869c This patch reverts SuperIO changes that I was too hasty with. Even though the
address of the RTC is 0x70, you need to write 0x400 to it.  Now the dump from
superiotool matches the factory except 0xf0 of the keyboard.  When you boot with
the factory BIOS that is 0x04, but with coreboot it is not set.

It's trivial because it is reverts.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 17:20:59 +00:00
65e9bc13f0 This one is an example on how to drop vgabios.c from the mainboard or chipset
directories and use the global (v3) one in util/x86emu instead. It also fixes
the breakage introduced by 4000

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 17:00:46 +00:00
be7f79867e This, ladies and gentlement, is commit #4000.
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 15:42:27 +00:00
cc46e73a02 ACPI implementation for i945, ICH7, Kontron 986LCD-M
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 00:44:09 +00:00
47e42e5ebb Fix HIGH_TABLES introduced error when compiling without MP table
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-12 17:42:20 +00:00
30140a59f7 i945 northbridge update
- lots of PCIe updates
- various bug fixes to early init
- some fixes for typos and warnings
- initial support for PCIe x16
- some minor fixes to memory init code
- some subsystem vendor id patches, to be consistent with ICH7

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 16:20:39 +00:00
d229677b61 20090310-3-scanbuild:
Add support for clang's scan-build utility to abuild. scan-build wraps
the compiler and runs its own compiler on the same sources to do some
static analysis on them. It adds an option "-sb" or "--scan-build" that
creates a coreboot-builds/$target-scanbuild directory for every $target,
containing the output of scan-build, which is a HTML documentation on
its results.
Be aware, that scanbuild significantly increases build time: A board
that takes 6-7 seconds normally requires 60 seconds with that option
enabled on my test system.
The patch also moves the stack-protector option down a bit, so it
applies to crosscompiled targets, too (which overwrote the compiler
settings before)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:43:02 +00:00
118c1005ed 20090310-2-gcc-for-real:
Create a variable "GCC", which defaults to the content of CC, but allows
the user to provide a gcc to use in this instance, even when normally a
different tool is chosen. That helps with scan-build (see next patch),
and might help with distcc, ccache etc, too.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:36:39 +00:00
25399346b3 20090310-1-paths:
The rules changed in this patch originally wanted to write c_start.o
into the source tree. That triggered a bug in my other work, and is
generally not what we want.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:35:22 +00:00
e1025d0f7f Kontron 986LCD-M updates:
* ACPI updates: MCFG, HPET, FADT
* some mptable fixes for certain riser cards
* Use Channel XOR randomization
* Fix SuperIO HWM setup
* Enable all three network adapters

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:20:36 +00:00
cc44b06d9d abuild:
- add configure only mode to easily and quickly check Config.lb and Option.lb
  files
- fix up cross compiler handling
- don't use in-place sed, not all sed versions can do it
- use perl instead of date to avoid non-gnu date trouble

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 15:00:50 +00:00
a8e1168064 This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:

* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info 
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
  some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:54:18 +00:00
6df0c62b68 Add support for the LPC47M182 to superiotool
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:48:20 +00:00
34b1d4ef37 This patch adds ACPI support for Tyan s2891, s2892, and s2895. There is still
a problem with IRQ 9, but besides that Linux is happy.  BSOD in Windows still.

changes by file:

src/mainboard/tyan/s289X/Options.lb:
	Add options and defaults for ACPI tables and resources.

src/mainboard/tyan/s289X/mainboard.c:
	Add high_tables resource ala Stefan's code for the Kontron.

src/mainboard/tyan/s289X/acpi_tables.c:
	Fill out the ACPI tables, using existing code where possible.
	Only the madt is different between the boards, to be combined later.

src/mainboard/tyan/s289X/Config.lb:
	Compile in acpi_tables.c and dsdt.dsl.
	Turn on the parallel port and the real-time-clock.

src/mainboard/tyan/s289x/dsdt.dsl:
	The board layout (thanks Rudolf) and interrupts from mptable.c

src/mainboard/tyan/s289x/mptable.c:
	Minor formatting changes to make them diff better.

src/superio/smsc/lpc47b397/superio.c:
	Correct the size of the real-time-clock so it can be where it belongs.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 20:56:54 +00:00
283a494521 This patch adds common elements for ck804-based boards.
changes by file:
src/northbridge/amd/amdk8/northbridge.c:
	Add high tables code ala Stefan's code for the i945.

src/southbridge/nvidia/ck804/ck804_lpc.c:
	Enable High Precision Event Timers.
	Add pm_base for ACPI.

src/southbridge/nvidia/ck804/ck804_fadt.c:
	Since fadt is only dependent on the Southbridge, add it here.

src/southbridge/nvidia/ck804/Config.lb:
	Compile in ck804_fadt.c

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 20:39:27 +00:00
210b83e764 This patch adds empty acpi_fill_slit functions so they build again.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 18:44:34 +00:00
0b4c9f08c7 This patch makes the boards use a single amdk8_util.asl. There are only
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.

It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 18:06:47 +00:00
8f210766d5 Add some basic K8 MSRs.
Fix bash script type.
Removed const return type on msraddrbyname() to fix gcc warning/error.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-08 04:37:39 +00:00
3b1a955cce FreeBSD definitions of (read|write)[bwl] collide with our own. Before we
attempt trickery, we can simply rename the accessor functions.

Patch created with the help of Coccinelle.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 22:26:00 +00:00
45cc550c3a Some updates for core/core duo/core2/core2 duo cpus.
The microcode is from Intel's Linux microcode file, so it's unproblematic.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:54:15 +00:00
3b387458b5 * fix a minor power state issue in the ich7 smm handler
* move mainboard dependent code into a mainboard SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:52:36 +00:00
43b29cf891 Fix mmconf (PCIe memory mapped config space access) support in v2. It was
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.

Create wrapper functions similar to the io pci config space ones.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:11:52 +00:00
ae762b5d3b use include file for i8259 where appropriate (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 18:39:54 +00:00
1894463787 clean up qemu target config (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 18:38:28 +00:00
0d348f919c fix strstr. Seems the function never worked before, except the searched
substring is at the end.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:43:20 +00:00
8dcd50b155 fix a bunch of cast and type warnings and don't call the apic "nvram", that
doesn't make no sense. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:24:29 +00:00
054c7235c3 use pointers instead of size_t when dealing with pointers. Also fix a few
warnings (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:22:35 +00:00
f8c77e82c5 use inb instead of outb for delays in usb debug code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:21:23 +00:00
9cbbc7902a really clean out all compile time generated files (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 17:20:17 +00:00
59c36f97db During the conversion of flash chip accesses to helper functions, I
spotted assignments to volatile variables which were neither placed
inside the mmapped ROM area nor were they counters.
Due to the use of accessor functions, volatile usage can be reduced
significantly because the accessor functions take care of actually
performing the reads/writes correctly.

The following semantic patch spotted them (linebreak in python string
for readability reasons, please remove before usage):
@r exists@
expression b;
typedef uint8_t;
volatile uint8_t a;
position p1;
@@
 a@p1 = readb(b);

@script:python@
p1 << r.p1;
a << r.a;
b << r.b;
@@
print "* file: %s line %s has assignment to unnecessarily volatile
variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b)

Result was:
HANDLING: sst28sf040.c
* file: sst28sf040.c line 44 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 43 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 42 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 41 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 40 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 39 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 38 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 58 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 57 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 56 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 55 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 54 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 53 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 52 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);

The following semantic patch uses the spatch builtin match printing
functionality by prepending a "*" to the line with the pattern:
@@
expression b;
typedef uint8_t;
volatile uint8_t a;
@@
* a = readb(b);

Result is:
HANDLING: sst28sf040.c
diff =
--- sst28sf040.c        2009-03-06 01:04:49.000000000 +0100
@@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x040A);
 }
 
 static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
@@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040
        /* ask compiler not to optimize this */
        volatile uint8_t tmp;
 
-       tmp = readb(bios + 0x1823);
-       tmp = readb(bios + 0x1820);
-       tmp = readb(bios + 0x1822);
-       tmp = readb(bios + 0x0418);
-       tmp = readb(bios + 0x041B);
-       tmp = readb(bios + 0x0419);
-       tmp = readb(bios + 0x041A);
 }
 
 static __inline__ int erase_sector_28sf040(volatile uint8_t *bios,

It's arguably a bit easier to read if you get used to the leading "-"
for matching lines.

This patch was enabled by Coccinelle:
http://www.emn.fr/x-info/coccinelle/


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
-- 
http://www.hailfinger.org/


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 00:40:25 +00:00
bba113ec07 If get_pbus() is called for a device which has no parent/ancestor bus
with nonzero PCI bus operations, get_pbus() will get stuck in a silent
endless loop.
Detect the endless loop and break out with an error message.

Such a situation can happen if the device tree is not yet
initialized/walked completely.

This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was
used in early mainboard code for the AMD DBM690T. Instead, the code will
now die() with a meaningful error message.

Thanks to Ward Vandewege for testing my patches to track down that bug.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05 19:33:12 +00:00
ac12ecd27a flashrom: Use helper functions to access flash chips.
Right now we perform direct pointer manipulation without any abstraction
to read from and write to memory mapped flash chips. That makes it
impossible to drive any flasher which does not mmap the whole chip.

Using helper functions readb() and writeb() allows a driver for external
flash programmers like Paraflasher to replace readb and writeb with
calls to its own chip access routines.

This patch has the additional advantage of removing lots of unnecessary
casts to volatile uint8_t * and now-superfluous parentheses which caused
poor readability.

I used the semantic patcher Coccinelle to create this patch. The
semantic patch follows:
@@
expression a;
typedef uint8_t;
volatile uint8_t *b;
@@
- *(b) = (a);
+ writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ readb(b)
@@
type T;
T b;
@@
(
 readb
|
 writeb
)
 (...,
- (T)
- (b)
+ b
 )

In contrast to a sed script, the semantic patch performs type checking
before converting anything.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
Tested-by: Joe Julian


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-05 19:24:22 +00:00
51001fbd81 I just went on a bugfix frenzy and fixed all printk format warnings
triggered by the AMD 690/SB600 targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04 01:06:41 +00:00
4b95ced365 fix make clean as suggested by Myles Watson.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04 00:25:44 +00:00
6b2e760f03 Small bug somehow slipped there. The method body length is incorrectly computed.
The attached patch fixes this. I did not spotted that because the return arg is
moved just outside of method and I have overseen the closing }
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-02 22:45:31 +00:00
fc19248501 (Trivial) Add missing header file.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01 18:05:25 +00:00
36c83404a3 Some changes required to get yabel working on v2 (and they generally make
sense, too). Have one u64 instead of three.

In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)

In order to use yabel in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
  default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1

In order to use vm86 in your target, you need to add the following lines to
your config:
  uses CONFIG_PCI_OPTION_ROM_RUN_VM86
  default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01 10:16:01 +00:00
2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
3c924d2f48 fix those two boards that broke due to the config tool fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 17:19:55 +00:00
9987ad806f This is a small fix for the last checkin (does not fix those two boards) that
caused same filenames to still cause objects being dropped from the build list
- which was the whole purpose of the patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 17:09:29 +00:00
21c8b5ab5c With this patch the v2 build system will create a directory hierarchy
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 12:50:32 +00:00
3c7f46b422 Generic approach of putting BIOS tables at the end of memory
(in addition to their low locations)

This adds the kontron 986LCD-M and the i945 as a sample.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27 23:09:55 +00:00
678d6140a5 This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27 17:51:16 +00:00
a85c0059f3 flashrom: Add SST25VF040.REMS with TEST_OK_ PROBE READ
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-25 08:07:33 +00:00
c5a2ec6f96 libpayload: Fix build when both USB and PS/2 keyboard support is disabled
libpayload uses -Werror for some reason right now, and the
variable 'c' in curses_getchar is only used if CONFIG_USB_HID
or CONFIG_PC_KEYBOARD is defined, giving an unused variable
warning that gets promoted to an error.
So wrap the variable declaration around appropriate #ifdef's

Signed-off-by: Mart Raudsepp <leio@gentoo.org>
Acked-by: Ulf Jordan <jordan@chalmers.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-22 23:13:33 +00:00
bc8744e1bf flashrom: SST29EE020A TEST_OK_ PROBE READ ERASE WRITE
Report by Holger Mickler. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-22 21:07:28 +00:00
fe849b2ff7 This patch is for AMD boards which can do the P state generation. This just
removes the ugly binary DSDT patching and all other related stuff. Stick to
infrastructure in previous patch.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-19 08:39:16 +00:00
7ad11e8d33 Carl-Daniel's part:
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and 
mainboard_$VENDOR_$BOARD_config to mainboard_config.

Ron's part:
The config change that makes the naming change not break every build.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-18 20:41:57 +00:00
d58671c4bf Add QWord support to acpigen.
Add TOM2 to the K8 DSDT.

Thanks to Rudolf Marek for testing and fixing this patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 21:38:51 +00:00
142cad1503 Bayou: Clean up Bayou's window after returning from a payload.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 16:23:26 +00:00
08afc6d9e0 Unify CAR so the same compiled code does the right thing on both
K8 and Fam10+ CPUs.

What this patch does:
1. Enable SSE (to get some more registers to play with)
2. Determine CPUID, and stash it in an XMM register, and reference
   value for comparison in another XMM register (mangled somewhat to
   simplify inequality comparisons)
3. Add a macro jmp_if_k8, which jumps if the CPU is K8
   (using an SSE compare)
4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8.
   This is pretty mechanical work. The macro uses local labels
   (1: and 2:) to prevent namespace issues
5. At one time, CPU_ADDR_BITS is used to fill a register. This is
   replaced with hardcoded values for both cases, and switched
   appropriately.
6. Disable SSE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-17 12:56:58 +00:00
b575d67b9a This is a safety measure, since the shipping buildrom fails badly at present.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15 23:32:57 +00:00
5389c7f72b - Fix up amd pistachio and dbm690t.
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
  on some platforms.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15 02:53:18 +00:00
a175533dc3 Change Log:
Bellongs to r3947

Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 16:23:16 +00:00
537bd5f637 Bellongs to r3946
Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 15:42:42 +00:00
f997b5554a Following patch adds dynamically generated P-States infrastructure as well as
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-14 15:40:23 +00:00
66948f7e8c This target is dead.
The company is dead. 

It causes builds to fail, and that is not a problem we need to have. 

Removing it to remove the problems it causes. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-13 20:20:21 +00:00
31197a61d9 Increase ROM_IMAGE_SIZE for the agami aruma to resolve overlapping
sections.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-13 18:46:22 +00:00
552b327ca3 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 21:30:06 +00:00
7f86ed1220 Fix mtrr setup for UMA architectures.
If high SMM memory is used (and needs to be uncached for whatever reason; it
shouldn't in my opinion), we should do it the same way.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 16:02:16 +00:00
e755bc1596 Fix typo in PCI ID (1914 should have been 7914).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 14:50:43 +00:00
d64b2441e4 Remove dead lines. Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 13:58:31 +00:00
d76d5791fd Rename TOM to TOM1 and refer to the SSDT value with an External(TOM1)
clause.

An ITE87427 Super I/O does not exist. Use the real name (IT8712F) of
the chip on the DBM690T board.

Use decimal values for KELV, THOT and TCRT on the Pistachio board for
better readability.

Tested by Maggie Li on DBM690T and Pistachio.
Tested by Carl-Daniel Hailfinger on Asus M2A-VM.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 13:54:03 +00:00
6a208781b4 Improve mainboard.c comments for DBM690T and Pistachio.
Fix reference to documentation.
Use __FUNCTION__ instead of hardcoding function names in printk
messages.

No functional changes.

I'm slowly getting to the point where adding another RS690 board is
really easy and needs almost no changes to the existing target.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 13:39:36 +00:00
7dde1da9a7 Print a loud warning message if we run out of MTRRs.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-11 16:57:32 +00:00
9dff094efd Fix one leftover reference to AmlCode_ssdt which was forgotten in r3929.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-11 12:08:55 +00:00
6818a32367 Fix bayou payload execution.
Bayou must link with its own ldscript to end up at a load address that
doesn't interfere with payloads. Make Bayou's ldscript MB compatible, so
the link with libpayload/lib/i386/head.o succeeds.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-10 21:12:35 +00:00
3ba0ce5f58 Fix bayou payload execution.
Bayou must link with its own ldscript to end up at a load address that
doesn't interfere with payloads. Make Bayou's ldscript MB compatible, so
the link with libpayload/lib/i386/head.o succeeds.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-10 21:09:03 +00:00
94e340b22a Change 0x%p to %p. Thanks Stefan for catching the one I introduced in 3931.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-10 03:02:05 +00:00
cd7e9b55dd flashrom: Fix broken flash chip base address logic
Elan SC520 requries us to deal with flash chip base addresses at locations
other than top of 4GB. The logic for that was incorrectly triggered also when
a board had more than one flash chip. This patch will honor flashbase only when
probing for the first flash chip on the board, and look at top of 4GB for later
chips.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09 20:26:14 +00:00
c4ddbff706 Remove some warnings, mainly from format strings which didn't match the
arguments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09 17:52:54 +00:00
4505948fae Use the correct device for switching on HDA.
Reorder HDA (HD Audio) init:
The reordering was based on what order things happen in the BIOS
Developers guide, RPR, and SATA driver. I fixed the order of the devices
that didn't matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec

The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.

Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
bits.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>

Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.

Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
but some warnings remain.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-05 02:18:42 +00:00
8db0cfefd1 Following patch converts the run-time SSDT patching via update_ssdt funtion to
new AML code generator. Compile-tested on all changed targets. I think it should
work because it works for Asus M2V-MX SE.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-03 22:37:22 +00:00
742655bb4d Following patch adds missing CPU names. Please check
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
if I did not made any mistake.

Works for mine CPU  ;) 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-03 22:25:51 +00:00
15884260e7 flashrom: MSI MS-7046 board enable
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: David Tiemann <davidtiemann@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-02 22:55:26 +00:00
e66c258f1b Following patch fixes VIA SPI (VT8237S). It needs to have opcodes
initialized same way as ICH7.

 Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
 Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-01 18:40:50 +00:00
293b5f5225 Following patch adds dynamic ACPI AML code generator which can be used to
generate run-time ACPI ASL code.

Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-01 18:35:15 +00:00
1c49bc9744 Bring AMD K8 ACPI mangling more in line with Fam10 ACPI mangling. No
functional changes, only a little bit of (mostly formatting) cleanup to
make merging easier.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-30 02:05:20 +00:00
b6dc72303c Factor out read and erase functions from flashrom main().
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-28 00:27:54 +00:00
fe53c7628b Correct FDAT->FADT typo.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-28 00:19:49 +00:00
3108a12e9b msrtool: Allow MSR symbols (names) to also be used as addresses.
Thanks for the idea Mart!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 17:18:31 +00:00
c1d6ed9a21 msrtool: Linux /dev/cpu/*/msr returns the low 32 bits before the high 32 bits.
Thanks to Mart for spotting this!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 17:03:05 +00:00
a8866243d8 flashrom: Add VT8237A PCI ID
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 15:29:27 +00:00
726c16d983 flashrom: Fix one dead increment and one dead assignment as found by clang.
Thanks Patrick!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 15:19:43 +00:00
c39cb144e9 flashrom: Driver for ST M29F002T/NT/B. T/NT TEST_OK_ PROBE READ ERASE WRITE
Test report from Julia. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 06:42:02 +00:00
f3bc765493 flashrom: Fix copypaste error in r3913.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:48:01 +00:00
fbda0d3143 msrtool: AMD CS5536 probe implementation.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:12:58 +00:00
279cdbb37d msrtool: Make configure work with zsh, the default shell in Darwin.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 04:10:12 +00:00
c800eeb39b flashrom: SST25VF040B using 0x90 identification and AAI write.
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.

From July 2008.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:37:40 +00:00
9ee44151cc flashrom: Decode SST25VF040B status register, also from July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:23:50 +00:00
37c4a96874 flashrom: Intel Desktop Board D201GLY
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:12:44 +00:00
36b3932f99 flashrom: Winbond SuperIO SPI driver.
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 03:08:45 +00:00
8991302f54 flashrom: Export Winbond SuperIO register access functions in board_enable.c.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 02:34:51 +00:00
732a229a10 flashrom: Document exit() codes introduced in r3907.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 02:20:56 +00:00
800621e0c5 flashrom: exit(2) on /dev/mem open() failure and exit(3) on mmap() failure.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 02:04:19 +00:00
0860215ab2 flashrom: Add license header to physmap.c so everyone is happy. :)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:33:02 +00:00
713ee92c96 flashrom: Darwin / Mac OS X
Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
DirectIO is available at http://www.coresystems.de/en/directio

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:23:31 +00:00
d48091a35c flashrom: Small cleanup in Makefile.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:16:09 +00:00
53ac3947db flashrom: Abstract mmap() in physmap.c and only open /dev/mem on the first physmap() call.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 01:10:48 +00:00
ac29d61a45 fix a potential null pointer reference in strdup (as found by Patrick Georgi)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:57:54 +00:00
8c4421ddbd flashrom: Change flashrom.c:map_flash_registers() from int to void.
The function exit()s on failure, and no callers check the return value.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:39:57 +00:00
8dec57fe0c flashrom: Forgot some things in r3899.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:19:36 +00:00
e03d84af69 flashrom: Little readability improvement in cbtable.c:coreboot_init()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:15:56 +00:00
09c0b7c61d flashrom: Change FreeBSD #ifdef into #if defined()
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-26 00:07:25 +00:00
bb79ba4aae flashrom: Make Makefile a bit more portable. Shell echo doesn't always know -n.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-25 23:59:30 +00:00
68c0cec9da flashrom: Add dry Am29F080B Am29LV081B SST39VF080 definitions per data sheets.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-25 23:55:12 +00:00
2450419294 flashrom: Beautify flash chip ID verbose printout a little, always use %02x.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-25 23:52:45 +00:00
7e6ff8bfc0 flashrom: Fix stupid off-by-one error in erase verification.
As reported by Jody McIntyre. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-25 20:41:51 +00:00
269e1bdd13 flashrom: ST M50FW080 TEST_OK_ PROBE READ ERASE WRITE
Report by Jody McIntyre. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-24 23:01:08 +00:00
6f77eeb036 flashrom: SST25VF080B TEST_OK_PROBE
Report by Scaldov M.V. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-24 01:32:40 +00:00
cab81c03eb Fix rs690 bug about GPPSB configuration.
Signed-off-by:  Maggie Li <maggie.li@amd.com>
Reviewed-by:    Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23 22:16:13 +00:00
2e5481356f flashrom: Check all mmap() calls and print helpful Linux error message.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23 05:23:06 +00:00
8a681b1d84 flashrom: Provide some hints for the user in case /dev/mem mmap fails.
resolves #121

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-22 22:53:59 +00:00
df2eb8e97b Now that x86emu debugging is actually working, it should be switched off per
default because it adds quite noticably to the image size.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-21 01:56:53 +00:00
679c9f9299 forgot to svn add
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:54:59 +00:00
54309d637a Update Kontron board
- use new features of the ich7 update
 - move rambase above 1M to avoid memory trashing through SMM relocation
 - enable superio HWM

Update ICH7 driver

 - minor smi cosmetics (in progress)
 - add real ac97 driver
 - add real azalia driver
 - fix some interrupt issues
 - fix some sata issues 
 - include Patrick's fix for _lpc.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:53:10 +00:00
977ed2d995 fix small TOLUD issue in i945 raminit (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:46:52 +00:00
ebb763fecf put in a little comment (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:39:31 +00:00
23b655f3b0 some brown paperbag please. fix build.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:07:20 +00:00
9ab216023c fix compiler warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:40:16 +00:00
a829bfe882 add a header file for i8259.h (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:38:17 +00:00
5833f7c0e6 Backport all x86emu fixes from Pattrick Hueper to coreboot v2 (acked in v2,
hence I consider it trivial in this case). This does not include the Yabel
work.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:36:39 +00:00
20b261dacf Fix register typo for core 2 cpus (trivial)
This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:32:37 +00:00
c5983305ef fix compiler warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:27:23 +00:00
8c4af2b9e2 This fine work by Jon Dufresne was awkwardly rotting on the mailing list for
almost three years. Let's put it somewher so people find it if they're looking
for it. Someone dare sending a late announcement to the coreboot-announce list?
:-)

Add (preliminary) support for Intel 855GME (Mobile version of the 855) chipset
to coreboot.

There are some holes in the code to be filled out, but unlike the code for the
855pm this has booted a mainboard before.

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 20:25:48 +00:00
ef6cb094b8 This patch makes the recently added assembler debug optional, as it may
cause problems with certain toolchains. This patch will also safe some hard
disk space for those of us working on laptops or netbooks with always too small
disks.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 20:13:01 +00:00
94f17773ef fix inconsistent user interface naming. don't show compile paths to users
during bootup (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:21:47 +00:00
26d431a616 fix coding style (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:17:51 +00:00
fc2e8edc23 Trivial stuff:
* fix a warning that should not be one.
* fix capitalization typo

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 19:17:11 +00:00
90308bb752 Check the printk format string against the matching arguments. We have
this type of checking in the v3 code since ages, but v2 will happily
compile any code with bogus printk format strings and/or parameters.
This can cause real bugs and at least needs to emit a warning, if not
an
error. Go with a warning for now since most of the flagged format
strings are wrong but harmless in a 32-bit x86 environment.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 18:37:26 +00:00
d0363c3927 ouch. never do last minute changes. :-(
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19 21:34:41 +00:00
269563a423 First shot at factoring SMM code into generic parts and southbridge specific
parts.

This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19 21:20:22 +00:00
0fd183ce72 flashrom: Fix ICH9 locking register address and add important debug output.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-18 06:39:32 +00:00
d8aaeaa143 The DBM90T code sets bit 10 in _PSS as part of the control value, but
bit 10 is part of NewVID. That means the resulting VID is wrong and
causes the processor to crash.
The Pistachio code has the same bug.

This patch fixes the wrong setting and changes control from a magic and
incorrect unexplained value (0xE8202C00) to a combination of explained
values and shifts which has the right value (0xE8202800).

It is tested on my machine and it survived 200 changes from minimum to
maximum frequency every 100 ms under heavy load and under no load.

In the long term we want to consolidate all AMD FIDVID code into one
generic library file.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Maggie Li has tested it on her DBM690T board. It is ok.
Acked-by: Maggie li <Maggie.li@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16 12:44:41 +00:00
734d09e05b First part of heterogenous dualchannel support.
Do not allow non-identical DIMMs yet, but prepare the code.

Calculate tCL related settings per DIMM in a dual channel setup. The
check for compatibility will come in a later patch, but since DIMMs
still have to be identical, this does not hurt.

Factor out tRC calculation to prepare for per-DIMM calculation.

Add diagnostic messages to tRC code.

Test booted to FILO, behaviour is identical if you ignore the added
debug messages (which are switched off by default).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16 03:44:41 +00:00
1d72e10bb4 Refactor K8 rev F DDR2 CL timing retrieval.
This will allow usage of compatible DIMMS in a dual channel setup
instead of requiring the DIMMS to be identical.

Code impact is minimal because a large chunk of code has been moved into
a separate function with almost no changes.

Tested, yields identical results and identical logs.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16 03:03:40 +00:00
abcddcd392 Since all K8 targets now have CONFIG_USE_PRINTK_IN_CAR enabled, using
print_* in K8 RAM init does not make sense anymore. Convert almost all
print_* to printk_*. This improves readability a lot and makes the code
shorter.

Reorder the SPD equality checks in the dual channel DIMM compatibility
checking code. This is to make sure that we know if any other mismatches
are present in the DIMM. The new order eases debugging with the old
code.
Add a comment about false negatives in that code. This needs to be
implemented correctly, but that is hard to do in an efficient way.
Check if the DIMMS in a dual channel setup have any compatible CAS
latencies.

Add better comments to explain why wrong-at-first-glance SPD CL walking
code is actually correct.

Fix a few typos.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-16 00:19:17 +00:00
6912846dda Adds a retry/faildown to SB600 SATA detection logic.
SATA port status kept returning 0x1: BAR5+po+28h
1h = Device presence detected but Phy communication not established

This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 02:35:30 +00:00
0f502c7537 amdk8: This patch fixes ram init problems when using the 9W Sempron part.
Trying to read the FIDVID register when the processor does not support FIDVID
control causes a GP Fault. This patch reads the startup FID from a different
MSR. I have verified this patch to work on the dbm690t platform.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 02:21:27 +00:00
884e1cbeeb flashrom: Add ICH opcode debugging.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 02:13:18 +00:00
d860763e73 Similarly to flashchips array, this patch intends to make the table
board_pciid_enables more readable.

Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>

> What real problem does this solve?

1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.

The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 00:48:24 +00:00
3462462b2a flashrom: Always print address when verification fails, not only with -V.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-13 14:32:27 +00:00
e31a8d5c95 flashrom: Board enable for GIGABYTE GA-MA78G-DS3H
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:31:14 +00:00
88ded318c3 flashrom: IT8718F works just like IT8716F.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:28:03 +00:00
475ac26a9b flashrom: Check return value of fscanf()/fwrite()/fread()
Fix build error on distros with warn_unused_result attributes in glibc.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 21:00:35 +00:00
6ef8e0f3e3 Check to see if K8 processor is capable of changing FIDVID otherwise it will throw a GP# when reading FIDVID_STATUS
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-12 16:16:08 +00:00
6fa7e6dae9 flashrom: Update usage in README
Mimicked from flashrom.c

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11 03:31:02 +00:00
4dad150849 Ignore some more sections, created by newer toolchains
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-11 00:35:30 +00:00
0afdea4e42 Add erase and write functions to the following chip definitions:
AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641
AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321
AT26F004

Straight from the data sheets, untested because I lack the hardware.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 16:53:13 +00:00
44b3bf7ed7 The flashrom man page has incomplete author/copyright sections and an
incorrect license section.
- Remove the copyright listings and refer the reader to the source
  files.
- Update the author list to those which have copyright messages in the
source files.
- Correct the license from GPL v2+ to (GPL v2, with some files under
  later versions as well)

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 04:56:59 +00:00
901f25acd3 This patch improves machine parseability and human readability of
flashchips.c over what's currently in flashrom HEAD.
The explicit initialization makes sure any future struct flashchip
reordering is not needed. (Except for the case where we need arrays
of some of the struct members.)

Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-08 03:40:17 +00:00
d32b9e605f Add SST49LF020 support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:35:09 +00:00
f58691ffb6 Add AMD-768 chipset support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:15:46 +00:00
c84ce73ab8 Add i631x LPC support.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-07 12:11:13 +00:00
505aaf56e2 The ACPI PSS CPU Pstate table was calculating the frequency incorrectly for
revF CPUs. The 100MHz/200MHz stepping is already handled in the FID setting
and doesn't need to be checked to set the fid_multiplier. The multiplier is
always 100.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: zheng bao <zheng.bao@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-06 16:45:42 +00:00
fdbb8d860a Add support for the Winbond W83627UHG Super I/O.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-06 00:33:30 +00:00
1d7db86b6b The SB600 RPR documentation does not mention what to do if SATA_BAR0+6
is no longer 0xA0 or 0xB0. It simply assumes that will never happen.
My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the
first init after poweron.
The current code hangs forever with my drive. Fix this by rerunning the
init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0.

Add support for SATA port 2-4 (Primary Slave, Secondary Master,
Secondary Slave).

If only the 2nd SATA port is connected and the hardware acts strangely
(contrary to documentation), it will print the error message below and
continue anyway. The official AMD asm code behaves the same way.
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 23
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
[8 repetitions]
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
Primary Slave device is not ready after 10 tries

Activate and improve debug messages for SPEW log level.

Fix some comments.

New log messages look like this:
PCI: 00:12.0 init
sata_bar0=3020
sata_bar1=3060
sata_bar2=3030
sata_bar3=3070
sata_bar4=3000
sata_bar5=fc309000
SATA port 0 status = 23
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
[... 281 repetitions ...]
0x6=0, 0x7=50
drive no longer selected after 2820 ms, retrying init
drive detection done after 0 ms
Primary Master device is ready after 2 tries
SATA port 1 status = 23
drive detection done after 0 ms
Primary Slave device is ready after 1 tries
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3

With this patch, my Asus M2A-VM boots into Linux without problems.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-29 09:35:00 +00:00
098d590d42 Fix AMD Pistachio implicit declarations in the same way as with AMD
DBM690T.
Remove trailing whitespace.

Signed-off-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-24 18:23:00 +00:00
a2f722abd4 Fix implicit declarations in the AMD DBM690T target by using the right
header files.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <Zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-24 17:58:44 +00:00
1cced2fe70 This belongs to changeset: 3840
The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.

The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 18:29:50 +00:00
da3d5dffbc Following patch fixes error code 12 in Windows XP and Vista. The function field of _PRT entry must be always 0xffff (any function).
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-By: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 18:05:24 +00:00
79e532560c The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 17:34:15 +00:00
33f9633184 Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.

Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 17:20:46 +00:00
5a3c8462dc Remove a unneccessary typedef from acpi_tables.c in the AMD Pistachio
and DBM690T targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <Zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 17:16:11 +00:00
b96af1ea60 Fix implicit declarations of pci_read_config32 and pci_write_config32 in
the SB600 code.

Signed-off-by: Maggie Li <Maggie.li@amd.com>
Reviewed-by: Zheng bao <Zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 02:22:07 +00:00
c589e5acf9 Add verbose debugging output at SPEW level to noncoherent HyperTransport
initialization.

This patch has helped immensely to track down a bug in 690G ncHT init.
It depends on my earlier patch which enables CONFIG_USE_PRINTK_IN_CAR
for all boards using HT. Of course that means ROMCC is not an option
anymore for those boards, but I don't think that's a big problem.
Another way to solve this would be #defining printk_spew to nothing.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Marc says:
ROMCC doesn't make sense for k8 boards.
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 02:05:55 +00:00
a5436c66bf Fix implicit declarations of get_bus_conf.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 17:41:01 +00:00
29fbb761ec If you pass a bogus layout file to the -l option flashrom will segfault.
Fix that by throwing an error instead.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:42:59 +00:00
fdc5470bcf Add another board-enable line for the Kontron 986LCD-M/mITX.
There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.

Patch successfully tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:40:45 +00:00
bfa009f3eb Fix implicit declarations of pci_read_config8 and pci_write_config8 in
the following files:
src/mainboard/intel/jarrell/reset.c
src/mainboard/supermicro/x6dai_g/reset.c
src/mainboard/supermicro/x6dhe_g2/reset.c
src/mainboard/supermicro/x6dhe_g/reset.c
src/mainboard/supermicro/x6dhr_ig2/reset.c
src/mainboard/supermicro/x6dhr_ig/reset.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:20:55 +00:00
eb30bf8ba2 Fix implicit udelay src/southbridge/nvidia/mcp55/mcp55_aza.c
Fix imlicit mdelay in src/southbridge/nvidia/mcp55/mcp55_nic.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:19:02 +00:00
3071acf370 flashrom: Initialize ICH SPI opcodes also for ICH9 and later.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 14:12:08 +00:00
93159bf752 In the process of trying to debug some HT sync problems I added lots of
debug code to src/northbridge/amd/amdk8/incoherent_ht.c.
However, printk is not available for all boards at that stage.

I have changed the following boards:
agami/aruma
arima/hdama
asus/a8n_e
broadcom/blast
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms7135
newisys/khepri
sunw/ultra40
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882

abuild works fine for all of them.
agami/aruma needs a Config-abuild.lb which doesn't have fallback and
normal due to size problems.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 09:53:24 +00:00
da416f8986 Fix dell/s1850 broken in r3822, and prepare it for implicit declaration
error patch.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20 21:07:20 +00:00
eb390abb4e This adds register map based on NSC PC87392 datasheet. LDN#2 can be
used for a SIR/FIR device.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Ulf Jordan <jordan@chalmers.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20 19:35:54 +00:00
48994e1633 This adds a mptable for the VIA pc2500e. I've tested with the devices
in the VT8237R, and a card interrupting at Pin-A on either PCI slot.

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-20 04:08:40 +00:00
b1fc0ba3fc Add some comments to make it easier to enable onboard VGA for
different ROM chip sizes (trivial, tested with 256 KB chip).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 14:21:42 +00:00
734acd5982 Fix breakage caused by r3822. I should have known not to touch the k8 stuff...
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 05:53:30 +00:00
40e51fd95a This patch fixes the build for asus/m2v-mx_se. Its hard_reset function is not
implemented (It just prints "hard_reset not implemented.  FIX ME!" This patch
defines HAVE_HARD_RESET 1 and adds a #warning hard_reset not implemented.

The net effect is that hard_reset prints something instead of just entering an
infinite loop.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 03:55:51 +00:00
e562f7258e Fix a LOT of implicit function declarations before they become errors.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 03:36:48 +00:00
716e5670fe I honestly have no idea if the previous use of the vt8235's serial functions
worked or not, but my board doesn't have COM1, and those function don't
support using COM2, so I've changed auto.c to use the fintek f71805f
functions, the fintek is the onboard super io. I also cleaned up a
whitespace issue and unused variable.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 03:33:37 +00:00
fbfdba70fa Fix the only implicit declaration before it becomes an error.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 19:53:11 +00:00
809242a715 Fix implicit declaration in cn700/vt8237 code
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 19:37:11 +00:00
43bb9cdddd This patch gets rid of all the implicit definition warnings for serengeti except get_nodes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 18:24:11 +00:00
845a2eba16 Add another CPUID to the Via C7's table, the one on my Jetway J7F2.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 02:18:45 +00:00
bb069e1f69 Add 690G and 690(MT) internal graphics support.
The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F

This fixes booting on 690G.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-17 02:14:24 +00:00
cc4473051d Add initial support for the ASUS P2B-DS (dual-CPU) mainboard.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15 12:15:49 +00:00
a8faa2a479 * add a generic preop-opcode-pair table.
* rename ich_check_opcodes to ich_init_opcodes.

* let ich_init_opcodes do not need to access flashchip structure:
  . move the definition of struct preop_opcode_pair to a better place
  . remove preop_opcode_pairs from 'struct flashchip'
  . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure

* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.

* fix a coding style mistake.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-15 02:32:11 +00:00
e65dcfa07a oops. there went a new mainboard into the tree and i missed it. Add mainboard
specific changes based on the DBM690T code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-14 00:01:04 +00:00
045c348cf3 Move mainboard specific changes to the coreboot memory table into the
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13 20:51:34 +00:00
42f03e5647 Improve comments in early SB600 setup, handle non-LPC strapping and
document verification against the data sheets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Maggie Li <maggie.li@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-12 03:40:21 +00:00
8eaafbf25a Use -O2 and -mcpu=p2 as romcc options for all Intel 440BX boards.
This should hopefully make the "too few registers" error pop up less often.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10 15:42:37 +00:00
b3b2804482 Add 28 flash chips of the MX29 series to the flashrom ID table and
support the MX29LV040C.

MX29LV040C probe and read support tested by khetzal on IRC.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-10 10:32:05 +00:00
19ead962c4 AMD PISTACHIO mainboard support.
The following ACPI features are supported:
 1. S1, S4, S5 sleep and wake up (by power button).
 2. Thermal configuration based on ADT7475.
 3. HPET timer.
 4. Interrupt routing based on ACPI table.

Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Michael Xie <michael.xie@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-09 21:52:42 +00:00
8b643cea5a Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.
This is tested on hardware with four 128MB DIMMs and works ok, _iff_
you also fix additional registers (e.g. DRB, RPS, ...) for your setup.
This requirement will be eliminated in another upcoming patch (i.e. all
of the required settings will be auto-detected).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-09 16:36:12 +00:00
17da8d706f Kill obsolete and misplaced comment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 23:51:45 +00:00
8a07f703ec Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
configuration is locked down.

Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 18:16:58 +00:00
60e7eebf96 Breaks chip info into multiple lines.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-08 18:15:10 +00:00
baada5efaf flashrom: Display test status in -L chip listing
Looks like this:

Supported flash chips:          Tested OK operations:   Known BAD operations:

AMD Am29F002(N)BB                                       
AMD Am29F002(N)BT               PROBE READ ERASE WRITE  
AMD Am29F016D                                           
AMD Am29F040B                   PROBE READ ERASE WRITE  
AMD Am29LV040B                                          
Atmel AT45CS1282                                        READ 

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-06 01:37:09 +00:00
ce00f1d12c Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 22:38:18 +00:00
f82a07730d The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks.
Signed-off-by:  Maggie Li <maggie.li@amd.com>
Reviewed-by:    Joe Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 18:38:57 +00:00
c73fca35e2 Add initial support for the NEC PowerMate 2000 board.
See details at:
http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/

Thanks to Quentin RAMEAU <quentin.rameau@gmail.com> for providing the
required information and for testing the patch.

This boots into a Linux console just fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 14:15:17 +00:00
24788351dc flashrom: Add AMD SB700 flash enable
This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:58:43 +00:00
5a0be5193e flashrom: Fix compilation of r3797 with gcc-4.3.2
Thanks to Niels Ole Salscheider for the problem report.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:56:57 +00:00
b4b56e669b flashrom: Check if erase succeeds and exit with error on failure.
flashrom used to exit 0 even if erase failed. Not anymore.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 02:22:30 +00:00
e94e2e3d40 This belongs to changeset 3795.
The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 23:42:36 +00:00
31e52e61aa The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.


Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 23:37:12 +00:00
1162f25a49 Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 15:18:20 +00:00
fcf9be3b93 Add RDID/REMS IDs for the following flash chips:
SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 00:58:10 +00:00
fd5a2df876 flashrom: gcc thinks base could be used uninitialized, so shut it up.
Bug from r3791.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 23:36:48 +00:00
9602d1e828 flashrom: Fix bug in r3790
If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:39:56 +00:00
d53f3e7546 Replace #ifdefs for sc520 systems by run time probing.
fixes #109

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:24:40 +00:00
b9b500f456 build_opt_tbl:
make sure the temporary files are created in the same directory as the
target files so they can be rename()d. This fixes a compilation issue on
machines with the build directory living on another partition than /tmp.
Pretty trivial.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02 12:26:17 +00:00
806def8cac I missed the svn add on r3787. These are the additional files.
Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02 02:56:38 +00:00
7c3d3b2027 Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.


Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 19:52:54 +00:00
40d46ba383 Add AMD rs690 VID DID reporting and some minor cleanups.
Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 19:49:57 +00:00
164463c551 Add AMD sb600 HPET setup and some minor cleanups.
Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 19:37:21 +00:00
7a51e50582 The Winbond Super I/O chips have another indirection of registers. The
hwmon has generic registers and banked registers, mostly temperature
handling, and SMI/GPIO stuff.

Not all LDNs are switched via register offset 0x07, make it a parameter.
  
Add support for dumping the hardware monitor of Winbond W83627THF/THG
parts with the -e option.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 14:18:57 +00:00
b4eb4fb6b0 ok, another attempt to the build_opt_tbl problem:
- create temp files and move them afterwards
- remove dummy option -b
- fix usage
- drop implicit creation of .c file if no --option is specified.

Now let's see if this fixes the issue. :-) We don't want to take 24s
instead of 6s to build an image reliably (Yes, yes, I know Tiano takes
over 20 minutes)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-30 14:52:46 +00:00
70a1f735a9 Copyright update by Jason Wang for freshly written sb600 code.
Signed-off-by:  Jason Wang<Qingpei.wang@amd.com>
Reviewed-by:    Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-29 15:07:15 +00:00
8b30d5d298 Declare special commands to support the Atmel AT25F512A.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:47:55 +00:00
f86f1fe961 If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:45:27 +00:00
f22ce41840 Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.

Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 21:36:51 +00:00
4ed326be5d This patch from Ralf Grosse Boerger makes debugging more comfortable.
With this patch it's possible to 

- determine the according source code line for each asm statement
  (objdump -dS)
- determine the source code file for each asm statement 
  (objdump -ddl)

This isn't exactly trivial because cache_as_ram_auto.c gets compiled to
assembly and converted by a perl script afterwards.

This patch solves the problem 
- by extending cache_as_ram_auto.inc with debug information and line
  numbers
- by correcting the perl calls (".text" --> "\.text")
- by creating a disassembly with source code and line numbers.
  (ctr0.disasm and
  coreboot.disasm)

There's one minor downside to the patch: A complete abuild run takes up
around 1.6G instead of about 700MB now. But I'm sure this is quite
reasonable for the benefits.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Please commit while this is being worked out.
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 12:09:17 +00:00
38bee3c8b6 This patch fixes the ugly race condition created through build_opt_tbl
running twice at the same time, overwriting its output files. This caused
a depending rule to produce an object file with no symbols in it.

This should silence up the regularly happening build failure messages on
the mailing list since we moved to the newer, much faster server.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 11:56:27 +00:00
d95e43cc8f Add SST25VF080B flash chip support.
This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().

Signed-off-by:  Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by:   Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 05:40:27 +00:00
6f24cbc083 Flashrom already has the following probe functions:
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 01:25:00 +00:00
c88733c021 The existing check in probe_spi_res() was right for SPI controllers
which support all commands, but may not exist.
For controllers which support only a subset of commands, it will fail in
unexpected ways. Even if a command is supported by the controller, it
may be unavailable if the controller is locked down.

The new logic checks if RDID could be issued and its return values made
sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
Otherwise, we try RES.
There is one drawback: If RDID returned unexpected values, we don't
issue a RES probe. However, in that case we should try to match RDID
anyway.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27 22:48:48 +00:00
1683cef996 Remove the unnecessary memctrl[] indirection, 440BX only has one
memory controller.

Also, drop some unused '#if 0' code.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27 00:47:07 +00:00
544dca4195 Increase the qemu rom size (non-LAB) to 512KB so that grub2 fits.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-26 19:46:27 +00:00
58edecdc1e libpayload: Fix immediate rebuild after a clean
After running make clean, most of build/ directory gets deleted.
It is (re)created in the "prepare" make target, but that was libpayload.a
dependency after the $OBJS, while OBJS building already needs to dump its
created object files there.
Simply rearrange the make target dependencies to get at least "make clean;make" working.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-25 16:41:21 +00:00
0924dee124 msrtool: Use libpci to let system and target probes find PCI devices.
And some more notes in TODO.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-25 02:03:16 +00:00
ef8ea01c8c Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.
File util/flashrom/flash.h already had correct ID for that part.

Signed-off-by: Tero O Peippola <xeropp@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-24 20:23:23 +00:00
db8c0abefc [PATCH] libpayload: rename config.h to libpayload-config.h
Rename the generated config file to libpayload-config.h to differenciate
it from other config.h files.  Move the default location of the file to
$(src)/include so that LIBPAYLOAD_PREFIX= users can access the file
without staging it.

Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-24 17:54:46 +00:00
cc9db9dfa0 msrtool: Very small fixes I made after sending out the rc1 tarball.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 18:29:44 +00:00
dad1e3091f msrtool: Release Candidate 1
msrtool can decode MSRs and print the value of every field in human
readable form. It can also be used to save a set of MSRs to a file,
and at a later time compare the saved values with current values in
hardware.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 17:13:36 +00:00
d24fe7e80e i810: Add support for multiple DIMMs, both single-sided and double-sided,
as well as most (all?) combinations thereof.

Drop some unused code, the unused row_offset variable, and obsolete comments.
Also, fix a typo (thanks to Stefan Reinauer for noticing).

This is tested on the MSI MS-6178 with a number of different DIMM
combinations and so far all of them worked fine.

Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-21 17:14:40 +00:00
4cf5ecf39d Get rid of the unnecessary indirection by 'struct mem_controller' for the
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.

This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.

Build-tested with all three boards using the Intel 810 chipset.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-20 23:18:10 +00:00
76c6c95c1e fix Config-abuild.lb for all targets that need a failover image and
don't have one (by fixing it for amd/serengeti_cheetah and copying the
same file to all other broken targets)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-20 20:07:38 +00:00
8c558d35cb OK, people, watch this.
This is a school book example of why trivial indent patches just suck
big time.

This error was introduced by a trivial self-acked indent patch and was
never detected (because of a missing Config-abuild.lb)

So, indenting the code for no reason can make it a lot worse (read:
break it) instead of improving it. 

I ask everyone to keep this in mind when going on indent-frenzy again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-20 19:26:16 +00:00
86c9b88392 Coding-style and whitespace fixes (also to make the code more similar
the Lippert Cool SpaceRunner LX which is already in svn).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-19 13:42:14 +00:00
f31ca16793 Add support for the LiPPERT Cool RoadRunner-LX embedded PC board:
- PC/104+ form factor
- AMD Geode-LX CPU/northbridge
- AMD CS5536 southbridge
- ITE IT8712F superio
http://www.lippert-at.com/index.php?id=408

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-19 12:19:09 +00:00
8ab91d875b i810: Add some more comments, and especially add a list of tested BUFF_SC
values for different DIMM configurations. This should be converted to a
table or code later on and actually be used for BUFF_SC.

Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting
the table entries.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 12:02:03 +00:00
8c0702b89b Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:43:14 +00:00
7cb70d9abd Check for failed SPI command execution in flashrom. Although SPI itself
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:41:02 +00:00
9648351d75 Implement read support for the following Atmel chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004

I double-checked the data sheets and am confident this will work.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:36:26 +00:00
b74fbc6122 flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE
Tested fully on a ThinCan DBE61A

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-17 15:31:56 +00:00
ef3f7e38ea The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.

Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D

Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642

Add the ID, but no probing function for this chip:
AT25F512A

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15 13:55:43 +00:00
385e90ad1c Rename LinuxBIOS strings and filenames to coreboot.
Also, use the more generic and buildrom-friendly '../payload.elf' as
the default payload location.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14 19:25:37 +00:00
e35d5e3fa2 drop dead code in sb600 hda
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14 13:43:26 +00:00
a04b107c6a Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space.
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Chris Lingard <chris@stockwith.co.uk>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12 20:38:51 +00:00
ebb73f2dcf Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,
IT8780F, and Fintek F71863FG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12 19:08:58 +00:00
c1f404fc0e Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 23:41:08 +00:00
39ebf2f068 Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 23:36:12 +00:00
3bb2628c7b Thanks to Uwe Hermann for spotting this typo.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 21:57:20 +00:00
1ec5094390 Add support for the Winbond W83627DHG Super I/O.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 21:10:07 +00:00
81af3d4a00 [PATCH] coreboot-v2: Add multiboot support
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 20:20:54 +00:00
5cb4d9d663 [PATCH] coreinfo: Add multiboot parsing support
Rename the "coreboot" menu "firmware", and add a module to parse
the multiboot table.  For now, just parse memory, but it can be
expanded as needed.

Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 19:53:42 +00:00
6c6e4333c4 [PATCH] Add sysinfo_have_multiboot function
Add a new infrastructure for returning system information to payloads.
First up - a pointer to the multiboot table.

Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 19:51:14 +00:00
3b6c527322 Always enable serial before SMBus (or as early as possible), as the SMBus
enable may do printk()s which result in a 2 minute delay on some boards.

Fix this on all boards which currently do smbus_enable() before enabling
the serial console.

Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11 14:26:03 +00:00
779b3e3129 Merge some parts of the i945 review (trivial):
* fix \r\n occurence in i945 code
* drop early TOLUD write
* fix 16bit BCTRL1 access

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10 15:43:37 +00:00
fb9f35d36b cosmetic update for getpir.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10 13:52:14 +00:00
a163729862 i945.h: Add some more comments, align data for better readability (trivial).
Also, add missing C1DRA2 #define (as per public datasheet).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-09 10:57:26 +00:00
160361a1df The POST_CODE macro had the outb() argument order backwards.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 01:51:32 +00:00
f27a3eba4d flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE
Per report from Mario Rogen. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 01:39:12 +00:00
8c95338f35 Update bayou to use ACS_ macros for line drawing characters.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 00:58:16 +00:00
c1c207f627 Re-add "based on" lines.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:38:31 +00:00
65ebc791c1 Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.

Build-tested with kontron/986lcd-m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:24:05 +00:00
556801eb61 The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).

The ICH7 needs a different init code. Drop the non-working code for now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:23:05 +00:00
176e88e961 The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write by Stéphan Guilloux.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-05 22:54:36 +00:00
aad6502d8a Add support for 8 new chips to flashrom and fix up 2 existing chips
as well.
Replace age-old TODO comments with real explanations.

Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)

New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B

Straight from the data sheets, compile tested only.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04 12:11:12 +00:00
98afd9b75b Fix compile errors if CONFIG_FS_PAYLOAD=1:
Compile error in filo.c if AUTOBOOT_DELAY=0. Replace
#ifndef AUTOBOOT_DELAY
with
#if !AUTOBOOT_DELAY
which should work for both the #undef and the =0 case.

In ext2fs.c, fat.c
#if ARCH == 'i386'
results in a compile warning: "multi-character character constant" and
the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually
choking the assembler on a PPC instruction. Change it to
#ifdef __i386

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 23:16:00 +00:00
632f86515a Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT
boards need them to switch the com ports from RS232 to RS485.) The PnP
resources should prevent other devices from being mapped at the same
spot, even if no OS driver actively uses them.

The IT8712F manual makes it look like PNP_IO1 had a size/granularity of
1 byte, but that must be a mistake. The Simple-I/O resource has a size
of 5 bytes (1 for each GPIO set 1-5) and trying different addresses
reveals a granularity of 8.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 22:58:56 +00:00
9cc49b21f8 Set asus/a8v-3_se to use printk in CAR. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 22:46:27 +00:00
c87ddd91c7 Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 21:39:03 +00:00
fbeba2313f Move the default payload to be more buildrom friendly.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 16:55:22 +00:00
d4ef0541db modify pirq tables for epia-cn.
Not tested, builds, derived from getpir. Definitely better than what was there. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Bari Ari <bari@onelabs.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 04:08:35 +00:00
6f31f11031 Dump ICH8/ICH9/ICH10 SPI registers in flashrom.
This helps a lot if we have to track down configuration weirdnesses.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:20:22 +00:00
6287e2e7aa Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.

TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
  
Thanks to Stefan for reviewing and commenting.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:02:11 +00:00
d22ef49783 Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead.
This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 19:51:50 +00:00
54c5276c3a Get the lzma/ directory from v3 via svn:externals, for use with Bayou.
Also, fix a few Makefiles regarding lzma stuff and 'make clean' behaviour.

Add bayou.xml.example which users can use as a starting point.

Bayou does compile fine now (if you build ../libpayload) before.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 17:48:20 +00:00
7eb845e815 Import a slightly modified Bayou version into svn. This is based
on the last snapshot posted by Jordan Crouse. This commit is long
overdue.

Changes by me include:

 - Rename 'utils' to 'util' for consistency with our other projects.

 - Move the main code out of src/* into the top-level directory.

 - Add missing license headers to the following files:
   Makefile, pbuilder/liblar/Makefile, util/pbuilder/Makefile.

 - Dropped the util/pbuilder/lzma completely. I'm working on reusing
   the lzma/ dir from v3 via svn:externals. Alas, this also means
   that Bayou won't yet compile out of the box.

 - Coding-style and white-space fixes (indent) for all files.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 17:01:06 +00:00
91df5619db Trim down the list of southbridges supported by the i82801xx driver
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
and C-ICH.

All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
not working with this driver anyway (and there's no chance to support
them reasonably with this driver without ending up in #ifdef hell).

ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
enough to be supported by that ICH7 driver remains to be seen.

This patch was informally acked by Stefan Reinauer
<stepan@coresystems.de> on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:33:51 +00:00
8a9e23c586 Add support for the ST M50FW002 chip to flashrom. Identification only,
erase/write are not implemented.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:25:11 +00:00
3d9a12f65d inteltool 82945G/GZ/P/PL Support (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 11:11:40 +00:00
5d7a1c844e Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.
Build-tested on kontron_986lcd_m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 18:41:09 +00:00
50f37b0f9b Move the nvramtool manpage to section 8 (as it's only really usable as root),
as we've done with the superiotool and flashrom manpages, too (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 05:40:04 +00:00
70c793ce28 Leave room for ROM growth and for the payload. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 22:13:51 +00:00
51c7838cb0 Increased the size of the failover and normal ROM_IMAGE_SIZE so abuild will
pass with toolsets that compile larger images. (trivial)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 21:31:54 +00:00
429d6b6692 Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target to 1M.
Both regular and abuild images have been boot tested successfully. 

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 20:17:11 +00:00
edc7ef2b76 Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:
- PC/104+ form factor
 - AMD Geode-LX CPU/northbridge
 - AMD CS5536 southbridge
 - ITE IT8712F Super I/O

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 19:34:44 +00:00
6a4bf9886a Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 15:41:39 +00:00
b076ced581 Mark two more chips as fully tested (trivial).
- SST SST39SF010A
 - Winbond W29C011

Tested by me on actual hardware, all operations.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 03:10:17 +00:00
a69d1db504 Flashrom support for some Numonyx parts (M25PE)
using block erase d8 as discussed with Peter Stuge

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 22:13:20 +00:00
c6bb6be6d2 Enable SPI boot flash support on EP80579, which has the ICH7 register set
(trivial).

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 14:54:36 +00:00
bddc693e8d i945/ICH7: Use #defines from pci_ids.h (trivial).
Build-tested with the kontron/986lcd-m target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 13:51:31 +00:00
36a2268d17 Support for the Kontron 986LCD-M mainboard series.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:52:57 +00:00
278534d007 Support for the Intel 945 northbridge.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:51:07 +00:00
00a889c8aa Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:48:44 +00:00
debb11fc1f Support for the Intel ICH7 southbridge.
This includes an early SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:46:52 +00:00
b70d1993a4 Implement support for the Winbond W83627THG.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:45:28 +00:00
532fd2dc3d Changes required to the device allocator:
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE
  is set.
- Mask moving bits to 32bit when resources are not supposed above 4G. Linux
  does not like this, even though the resource is disabled.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 03:15:42 +00:00
b64aa60f1f Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 22:13:38 +00:00
c372aa4f77 Mark Winbond W39V040FA" (512 KB) as fully supported, tested by
Martin Stecklum <stecky@gmx.net> (both write and erase).

The tests were done on an MSI MS-7065 board, so that's supported now
too (wiki page will be updated).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 12:00:59 +00:00
49387739da Add support for the Intel 82371MX (MPIIX) southbridge (trivial).
Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 11:50:05 +00:00
13be848dfc Add initial support for the MSI MS-6147 mainboard.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-27 13:44:07 +00:00
045d32d78c Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.
Tested on PIIX3 hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-26 18:40:42 +00:00
4446aa0a29 Add support for the VIA VT82C586A/B chipset, improve documentation.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-25 18:03:50 +00:00
38204a2c18 Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.
They all use a different init sequence than the more modern ITE Super I/Os.

For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
valid. Contrary to other Super I/Os, the config port for these is _not_
hardcoded via hardware, instead it can be programmed by software, i.e.
you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.

Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23 23:33:18 +00:00
c4f294f33f make escape code handling for serial terminal more robust
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23 12:22:24 +00:00
c811a1c6ae Made await_ide(), which polls for an ide status change, check the status
reg much more often. In my case this reduced the time spent in coreboot
by 1.5 sec!
The timeout values of course aren't changed, only the granularity. Also,
I didn't see any udelay() implementation that looked like it couldn't
cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:30:17 +00:00
f6fa12d89e Changed RAM speed calculation to fix RAM modules getting rejected only
due to integer rounding errors. Previously, the formula was:
	speed = 2 * (10000/spd_value)
For spd_value=60 this means speed = 2 * 166 = 332, which is less than
333 and coreboot died saying RAM was incompatible. The new formula is:
	speed = 20000 / spd_value
For spd_value=60, speed=333, which is fine.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:26:09 +00:00
5e5bef5fbd Speed up copying coreboot to ram by using "movsl" instead of "movsb".
Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:24:47 +00:00
9a9e61b7ec Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not
getting assigned.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 22:20:48 +00:00
ea8724578e Fix ordering problem in the libpayload Makefile. The include of
'include util/kconfig/Makefile' must come before certain pattern rules
for compilation of kconfig files, otherwise the build would break
in most situations.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 15:49:20 +00:00
ac431505c6 add multiboot support to defconfig (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 11:23:32 +00:00
1b57f1c985 ouch. something went wrong with applying that old patch
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 11:06:20 +00:00
734427ea92 This has been sitting here since a looong time.
* allow versions of "install" that don't know -D
* install libpayload .config and config.h to the target.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-22 10:49:34 +00:00
1877b5e51d Reduce serial output, otherwise flashing will fail very often (trivial).
This has been tested on hardware by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 22:09:02 +00:00
6ec8285aa1 [PATCH] fix video console init
Move console_add_output-driver() inside the for() loop

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 21:49:48 +00:00
039255c59c I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.

Build-tested with the AMD dbm690t target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 16:27:38 +00:00
657a6dc390 This patch removes most of the #ifdefs in libc/console.c, and
replaces it with two queues (input, output) where drivers (serial,
keyboard, video, usb) can attach.

The only things left with #ifdefs are initialization (at some point
the drivers must get a chance to register)


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 15:08:18 +00:00
97f56a4b7e Add missing license header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 15:07:53 +00:00
f2433a9d9e [PATCH] libpayload: Fix overflow in _delay function
On faster machines, delta might be more then 32 bits

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 17:08:08 +00:00
c53cdd782a [PATCH] libpayload: Add a strtoul() function
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 17:07:47 +00:00
ec6363dc48 [PATCH] libpayload: Bail if the keyboard controller isn't there
If the system in question does not have a superIO, then a read of
0x64 will return 0xFF and we will loop forever.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 17:07:26 +00:00
6744231197 [PATCH] libpayload: Fix the PCI search function
Remove a possiblity for evil recusion and fix the function and slot
definition in the PCI search loop

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 16:52:06 +00:00
20c9cf12a4 [PATCH] libpayload: Add multiboot support
Make libpayload applications multiboot compatible.  Add the
multiboot OS table and grok the loader table, especially the
memory map and the command line.  This makes libpayload 
applications loadable by GRUB.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 16:51:43 +00:00
369a5f6c7a [PATCH] libpayload: Add pci_set_bus_master() function
Allow the payload to enable a PCI device as a bus master.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 16:51:20 +00:00
17f6a87788 [PATCH] libpayload: Use gcc to compile assembly files
Using gcc to compile assembly files lets us use preprocessor
directives.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-20 16:50:47 +00:00
c880a369de Add register definitions for W83627HF based on publicly available
specification and local testing.

Also tweak a little bit algorithm for (internal) device ID calculation:
Chips from the W83627HF/F/HG/G family have an ID of 0x52 and a multitude of
revisions (0x1x, 0x3a, 0x41, maybe more), chips from the W83627HF/GF family
have the same device ID but revisions 0xfx.

Please note that the last line of the patch simply fixes the comment
about internal device ID composition (upper half of reg 0x21 is used).
I chose the most conservative way of detecting W83627HF - only if reg
0x21 value matches 0xFx we skip the previous logic and keep using it for
all other revisions.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-19 21:03:41 +00:00
1aa329dcb0 Coding-style fixes for flashrom, partly indent-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18 21:14:13 +00:00
582364d808 flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips.
Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info
about SiS620.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18 13:54:30 +00:00
71a2fbf9d5 One more little fix for the Jetway J7F[24], option tables can only be
built in the normal image, not fallback.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17 14:17:05 +00:00
400224e71a Config-abuild.lb's for jetway/j7f24 and bcom/winnetp680, to (finally) get abuild to stop complaining about these boards. They build fine with the default configs on a regular build.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17 02:47:20 +00:00
01a9c1bf77 Final fix for C7 boards, which are still using ROMCC, to be able to
build. As far as I know, no C7 boards currently in the tree use SPI
flash.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17 02:34:06 +00:00
8829c7d904 ROMCC chokes on vt8237_early_network_init(). Since that function is only
called from one target and that target is compiled with GCC, make the
function dependent on GCC.

ROMCC also chokes on the ULL suffix for integer constants. Change the
affected ones to UL for ROMCC compiled code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17 00:06:50 +00:00
8a3ad59653 Revision 3564 improved compilation time, but it also introduced a
dependency bug which hit people running parallel make instances.

With our current makefile architecture, the "right" fix is impossible.
However, we can still kill the race conditions leading to arbitrary
compilation failures. That trick depends on the atomicity of the mv
command.

Extensive comments explain what the workaround does.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-16 23:44:21 +00:00
4727c07446 - reduced memory requirements a lot (from >100kb/controller to
560bytes/controller)
- no need for the client of libpayload to implement
  usbdisk_{create,remove}, just because USB was compiled in.
- usb hub support compiles, and works for some trivial cases (no device
  detach, trivial power management)
- usb keyboard support works in qemu, though there are reports that it
  doesn't work on real hardware yet.
- usb keyboard is integrated in both libc-getchar() and curses, if
  CONFIG_USB_HID is enabled

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-16 19:20:51 +00:00
b1b071fe17 * Add a new board, the BCom WinNET P680
* Add a function to change the 24/48Mhz clock input selector on the Winbond 
  W83697 superio to 48Mhz, used by the WinNET P680

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-16 17:45:25 +00:00
ca11e7c259 Revision 3567 introduced __attribute__((packed)) for a structured which
is also visible to ROMCC and ROMCC doesn't understand that.

The fix is to use __attribute__((packed)) only for gcc compiled code.

This has been unfixed for too long. There are more problems remaining,
but at least this one is solvable easily.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-16 15:05:18 +00:00
7528aa6de3 SB600 has four write once LPC ROM protect areas. It is not possible to write
enable that area once the register is set so print a warning.

Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-15 17:50:29 +00:00
b0ae976eaf Drop global register 0x07 for all Super I/Os (trivial).
This is useless, as it changes with each access; it doesn't convey any
useful information at all.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14 16:34:38 +00:00
b9c6b0e8f7 Add dump support to ITE IT8726F, and add comments and a missing GPIO
register to ITE IT8718F.

Signed-off-by: Josh Profitt <zorn169@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14 16:28:50 +00:00
b8e53eb50c Add support for the Intel EP80579 (Tolapai) Development Kit mainboard
(Truxton).

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13 23:18:56 +00:00
b7d781dad5 Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
Build-tested with the AMD dbm690t board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13 21:41:24 +00:00
28401bd9ea Drop unused (or commented / #if 0) reset.c files.
This is abuild-tested by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13 13:08:38 +00:00
598ba43742 Drop tons of duplicated debug.c files, move common file to
lib/debug.c and use that one.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12 22:34:08 +00:00
8ce164dda3 Remove an extra bracket left by the vt8237r cleanup patch (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12 20:35:58 +00:00
0a20c41622 VIA VT8237R cleanups (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12 14:40:23 +00:00
2e5a9d952f Add support for the VIA pc2500e mainboard (CN700 + VT8237R).
Works good enough to boot to a Linux console.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12 11:58:26 +00:00
3be4bc88fa Drop a number of duplicated failover.c files (they have the same content
as the global src/arch/i386/lib/failover.c file).

Also, drop a number of dummy failover.c files which are not even used at all.

This is abuild-tested by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-11 16:10:54 +00:00
f4b54b4135 Add ICH10 support to flashrom.
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10 20:54:41 +00:00
4e40e46d49 flashrom: Check that a filename was specified also when using force read
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10 20:43:17 +00:00
32965d8dbb Enable vga bios by default on Tyan s2881. The board has an onboard ati rage XL.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10 18:06:56 +00:00
0323a2b8f5 Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09 23:56:11 +00:00
ea7b518ec0 Indent-based + manual cleanups for CN700 (trivial). As this will be ported
to v3 sooner or later we cleanup _now_, so we don't have to do it twice.

 - Whitespace, coding style improvements.

 - Fix a few typos.

 - Add a missing #endif in raminit.h.

 - Drop an unused variable.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09 17:08:32 +00:00
c1d06b782f Added comment about sb600 wideio setting for clarity and a minor witespace cleanup. (trivial)
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Marc Jones <marcj.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09 16:05:16 +00:00
4b1971cc62 libpayload: Rename Geode video driver to Geode LX video driver.
This is simply wrong, the "Geode" video driver is only good for LX and one of
our users got bit by this just now.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-08 14:47:41 +00:00
ff9350b798 move variable declaration to where it is used, to prevent gcc failure.
Reported by Roman Yeryomin (and also seen reported earlier). (trivial)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-08 11:17:25 +00:00
964f066559 [PATCH] coreboot: Don't loop forever waiting for HDA codecs
We shouldn't assume the presence of a working HDA codec, so put in
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is 
present in Simnow, it is non functional.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07 16:25:10 +00:00
0994c397a5 Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07 12:21:12 +00:00
a643ea3beb Whitespace fixes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-06 21:00:46 +00:00
69e9cc4fbd Fix obviously (syntactically) broken cmos.layout (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-04 23:13:18 +00:00
cf762a4be5 Ron has been doing really good work over in v3. The problem is that the work got checked into v2. This should get us back to where we were. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-03 23:23:20 +00:00
6c0b6d72bc Fix/amend the incorrect pnp_dev_info[] items for the ITE IT8712F Super I/O.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-03 18:16:23 +00:00
92f3eda809 Thanks to Jason Zhao we got a skeleton CAR code for VIA C7. I have tried
to clean it up a bit and find justifications for every difference from
x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd
have preferred to do this for v3 first, we can fix v2 boards with this
change and then move them to v3.
Thanks to Bari Ari for getting the code to me for rewrite/review.

CONFIG_CARTEST shall not be enabled (breaks the build).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-03 15:17:47 +00:00
cee9438436 Whitespace cleanup (trivial).
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 19:21:30 +00:00
d61ada6555 Whitespace cleanup (trivial).
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 19:20:22 +00:00
7f3d48c9af CK804 coding-style fixed based on an 'indent' run (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 18:19:17 +00:00
5107174459 This is so that people can see it. This is the sb600 for v3. It almost
certainly won't build -- that comes later. I am hoping to get some 
eyeballs on it for simple errors. 

rs690 is next. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 15:42:14 +00:00
248a7df94a Fix a typo.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 01:35:03 +00:00
bdb96f8abe Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02 00:52:53 +00:00
5263b01657 Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se.
This fixes that build error. (trivial)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 22:15:20 +00:00
cfb6ac72d1 Add some more Super I/O IDs/names (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 20:16:58 +00:00
b816d332a3 Enable all available devices on the ASUS A8N-E (trivial).
This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 13:10:39 +00:00
2ee6779a64 The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 12:52:52 +00:00
dc65196f8f Add an abuild command line option for -fno-stack-protect for toolchains that might require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 17:09:44 +00:00
336935c378 Coding-style fixes and simplifications for the ASUS A8N-E (trivial).
The only non-cosmetic change is s/A8NE/A8N-E/ for the board name.
This is build-tested by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 15:02:40 +00:00
94c1bd8904 Do not try to display non-printable characters on the bootlog and
ramdump screens. This fixes unaligned display on serial console.

The current isprint() implementation assumes a C locale, so also
characters with the eigth bit set are supressed (they produced  
inconsistant results on VGA and serial anyway).

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 06:13:54 +00:00
45db366d5c A duplicate register address is incremented in table register_values.
A trivial fix to correct the address of the high byte in SDRAMC.
Thus the leadoff timing IPDLT will be correctly referenced.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:52:29 +00:00
166ad2d7a5 This patch fixes support for the AT49F002N(T) chip in the flashrom tool.
It replaces the write function to one based on write_byte_program_jedec()
instead of write_page_write_jedec(), as this part does not support page
programming.
I have verified the NT variant to fully work now, and adjusted the test
status accordingly. The N variant *should* also work with this patch, but
remains untested.

Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:13:32 +00:00
5de576c190 flashrom: ST M29F040B status TEST_OK_ PROBE READ ERASE WRITE
Per report from Daniel Lindenaar. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:00:23 +00:00
2080bd9a41 AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR
option.
This patch converts the following patches to use PRTINK_IN_CAR
amd/serngeti_cheetah
msi/ms9185
msi/ms9828
supermicro/h8dmr

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 22:59:23 +00:00
b246158f77 flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 21:21:36 +00:00
5f41bf97cb Mark the SyncMOS S29C51002T as working (trivial).
All operations tested by me on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 18:48:23 +00:00
b5623d18cc This patch for the AMD K8 allows a single DIMM to be populated in the
ChannelB slot. Previously a DIMM could only be populated in ChannelB
if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
the DIMM must still be matched.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 18:09:51 +00:00
a67aab7083 Add string support to nvramtool.
To add a string to your cmos.layout, you need to specify type 's':

#start     len       type    unused   name
416        512       s       0        boot_devices

With this patch you can do

$ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)"

And FILO will attempt to load a menu.lst from any of these devices in that
order.

The patch is not exactly pretty, but a cleaner solution might have resulted in
a complete rewrite of the tool, which I did not want.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27 10:08:28 +00:00
830b17d3e3 fix ppc mainboards (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27 08:51:11 +00:00
c753926a01 accidently backed out r3598. Sorry Ulf, will pay more attention next time.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 19:37:16 +00:00
ecd176f304 This patch fixes the dbm690t keyboard not working issue. It should also
fix the a8n_e and any other it8712f SIO keyboard issues. The it8712f
requires an archaic PS/2 mode setting to the keyboard controller before
accessing the keyboard. Beyond that, I made the keyboard controller and
keyboard init more robust and added more informative debug output.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 19:15:38 +00:00
678d61cf5d add svn:ignore for temporary files and directories. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:56:11 +00:00
41514397e7 * Add strsep (since strtok is considered obsolete)
* add a bunch of string function doxygen comments.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:42:40 +00:00
bc9cb27a8e Use a block cursor on VGA console :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:40:06 +00:00
71c006fe9b fix option handling in libpayload
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:39:06 +00:00
d84ef1e6dc * add keyboard layout support to libpayload
* add a reset handler mechanism (CTRL-ALT-DEL)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:37:26 +00:00
e75c3d85a3 * factor out serial hardware init
* add reverse color support for serial
* add cursor enable/disable support for serial
* fix tinycurses compilation if serial is disabled
* add functions to query whether serial or vga console is enabled in tinycurses
* initialize uninitialized COLOR_PAIRS variable
* implement has_colors(), wredrawln() functions in curses

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 18:36:26 +00:00
96bcc53071 Add IRQ12 to the dbm690t mptable for mouse interrupt support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 17:41:34 +00:00
ad9bdb4345 Activate proper support for EN29F002(A)(N)[BT].
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 13:19:02 +00:00
6c55b05cb2 Add default config file to libpayload so that one can do make defconfig
without errors.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 11:21:21 +00:00
f69d5ee13c Support for the memory controller and PCIe interface of the Intel
EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 15:06:34 +00:00
22d5ddcd09 Fix overflow in modwin erase. Do not refresh modwin yet, since it is
immediately overwritten by stdscr.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 14:21:02 +00:00
902ed76ec4 Adjust width of stdscr to exactly SCREEN_X. This fixes alignment issues due
to an extra space sent at end of each line, as well as a data corruption
issue, which could result in undefined color pairs being referenced.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 14:17:02 +00:00
0f5379ce4e Fix up remaining AMD DBM690T autobuild issue.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 10:09:03 +00:00
9856fb3821 Add abuild support for the dbm690t. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24 03:21:55 +00:00
4590ce2b3c This patch adds support for watchdog kill and adds it to Asus M2V-MX SE.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marc.jones@amd.com> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 22:26:27 +00:00
3aca4b5734 The AMD dbm690t mainboard uses the it8712f SIO with the
default 48MHz clock input. The Asus a8n_e uses the it8712f
with a 24MHz clock input. The it8712f early init code was
setting a 24MHz input clock(to support the a8n_e).
Since 48Mhz is the default I added a function to set 24MHz
input clock to the a8n_e.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 22:19:27 +00:00
0f4282b538 Attached patch removes HPET info from ACPI tables. HPET does not work fine on
VT8237R (random keyboard/mouse lockups).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 21:57:33 +00:00
3e3c83e40a 1.
Preset CC to gcc in Makefile. There are some $(shell $(CC) ...)
invocations with GCC specific options, so that shouldn't hurt.

2.
Replace stdbool.h include in util/kconfig/expr.h by a custom
implementation of booleans. This is okay as these booleans are purely
internal. It's necessary because there's some disagreement between the
Solaris headers and GCC on Solaris, about when stdbool.h is appropriate.

3.
Remove stdbool.h include from util/kconfig/zconf.tab.c_shipped. This
file includes expr.h already, so it picks up the right set of
primitives, without duplicating the special case for Solaris.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 21:29:53 +00:00
05839975bf Following patch adds support for Asus M2V-E SE. Works pretty well, the only
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers
recently released, maybe with OpenChrome too.

It wont work with the little patch which will hop in soon

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-23 20:36:03 +00:00
80d7c85fb9 Patch for AMD DBM690T board.
Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:16:18 +00:00
7586cef37a Patch for AMD SB600 chipset.
Most of the functions in SB600 are enabled except power management.

Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:11:39 +00:00
06755e404e Patch for AMD RS690 chipset.
All the PCIe slots are enabled in this patch except power management.

Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22 13:07:20 +00:00
0b0771d180 Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
 whole PCI bus.

 U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
 does we not.

 Second small change just changes a bit which controls the PSTATECTL logic.

 Third change deals with the integrated VGA, which needs to be enabled early,
 so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
 correctly. Finally the CPU accessible framebuffer is now disabled as it is not
 needed.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 22:58:59 +00:00
c4128cfbec Whitespace and style cleanup. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 21:19:46 +00:00
8d183c5846 Add AMD K8 S1G1 socket support.
Signed-off-by:  Michael Xie Michael.Xie@amd.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19 20:16:25 +00:00
64caf3607e ck804 whitespace fixes
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 16:27:00 +00:00
a67c354cbf Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1
that don't seem to clarify anything.  Abuild tested.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 15:30:42 +00:00
297b91c6cd fix two minor bugs in nvramtool. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 14:49:33 +00:00
4614aedd4b fix regression in libpayload introduced by merge of the keyboard drivers.
(add back function keys; trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 07:48:59 +00:00
e6408a36c9 - unify keycodes for non-ASCII keys by using curses' codes and labels
- fix ctrl-[a-z]
- get rid of curses' ps/2 driver. uses generic one instead
- #ifdef's around ps/2 keyboard handling and serial handling
- add alt-key handling (necessary for german keymap)
- flush keyboard controller buffer on init

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-17 18:12:46 +00:00
57700ff81f This patch adds damage detection to libpayload's tinycurses. This
significantly speeds up serial output with large windows.

It also adds the function curs_set to enable/disable the cursor (video console
only for now)

Also, use werase in one place to reduce code duplication.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-17 16:32:17 +00:00
f218d97a17 * Implement scrolling in tinycurses
* Fix an off by one bug

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-12 21:50:57 +00:00
229c20f3e2 For the jetway jf2/4 series of mainboards:
* change the comment for device f.0 from "IDE" to "SATA"
* turn on firewire device a.0
* turn on pata device f.1
* don't turn on the unusable device 10.5 (built-in vt8237 ethernet?)

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-12 20:39:04 +00:00
53bbb0f6b1 makes cursorx and cursory signed, as there
are several "if (cursorx < 0)" tests.

I also added another one, to make backspace
wrap backwards into the previous line, if necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 17:44:45 +00:00
29061a59b2 Fix the USB code to find the headers after they were moved.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 17:29:00 +00:00
6fbbd8080f Move the USB header files to a common location for install
purposes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 17:26:53 +00:00
232dc970bc Add the target for the previously-added jetway mainboard.
This target is a copy of the epia-cn target, with only 
COREBOOT_EXTRA_VERSION modified.

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 17:19:19 +00:00
f657d75375 From Vincent Legoll:
Use dev_path() to have nice debug output
patch is run-time tested

Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-11 06:52:22 +00:00
9196dd553d Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this
changes the superio to a Fintek F71805F as described at
http://www.coreboot.org/Jetway_J7F2_Build_Tutorial

It also creates the mainboard tree for this series of motherboards
(Jetway J7F2 and J7F4).  I've tested it with one motherboard
(J7F2WE1G3), and I believe it works with the others, as the differences
among them are mostly trivial (processor speed, chipset and quantity of
LAN cards, audio chipset, etc.).  A list of the relevant motherboards
with specs can be found at
http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16

The irq_tables.c is copied directly from the epia-cn, because the one
generated by getpir with the factory BIOS did not work properly while
the EPIA-CN one did.

Minor changes on checkin to cope with moved romcc in latest revision.

NOTE: This board is broken until the issue introduced in r3567 is resolved.

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10 20:40:46 +00:00
eb2b8a282c flashrom: Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITE
Per report from Kevin O'Connor. Thanks Kevin!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10 09:55:10 +00:00
05e0feece9 flashrom: Debug print actual time base calculated by myusec_calibrate_delay()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-07 03:14:27 +00:00
f044f282ea Add editing keypad keys and the missing F11 key to the curses serial
input cooking table.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05 21:23:02 +00:00
d9f29c8e5e This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Bari Ari <bari@onelabs.com> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05 18:20:57 +00:00
10d0a81ec1 define array size in a single place (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05 15:18:15 +00:00
0e0ecf27bb Make the serial output driver 8 bit clean. Remove translate_special_chars(),
since it has been superseeded by the ACS code in tinycurses.
  
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04 21:05:59 +00:00
00809ebf02 This changes the python generated makefiles
targets/*/*/Makefile
        targets/*/*/normal/Makefile
        targets/*/*/fallback/Makefile

to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.

Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.

The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04 13:44:00 +00:00
1149a3692f Tidy up identifiers, per Uwe's suggestion. Trivial.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 23:32:30 +00:00
12aa5d9acf flashrom: Only find "unknown .. SPI chip" if no other chip was found
This removes the false positive matches we've been seeing, and also removes
the true positive match in case there is more than one flash chip and the 2nd
or 3rd are unknown - but I think that case is uncommon enough to warrant the
improvement in the common case. Use flashrom -frc forced read if you have the
uncommon case, and/or please add the flash chip to the flashchips array.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 23:10:05 +00:00
d57a680632 Add support for curses color output over serial.
Note that the sequence \e[m for turning off bold resets all attributes,
including color.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 19:59:44 +00:00
d21f68bbd5 This patch adds USB capabilities to libpayload. It requires some
memalign implementation (eg. the one I sent yesterday).
Features:
 - UHCI controller driver
 - UHCI root hub driver
 - USB MSC (Mass Storage Class) driver
 - skeleton of a USB HID driver
   (requires better interrupt transfer handling, which is TODO)
 - skeleton of a USB hub driver
   (needs several blank spots filled in, eg. power management.
    Again: TODO)

OHCI and EHCI are not supported, though OHCI support should be rather
easy as the stack provides reasonable abstractions (or so I hope). EHCI
will probably be more complicated.

Isochronous transfers (eg. webcams, audio stuff, ...) are not supported.
They can be, but I doubt we'll have a reason for that in the boot
environment.

The MSC driver was tested against a couple of USB flash drives, and
should be reasonably tolerant by now. But I probably underestimate
the amount of bugs present in USB flash drives, so feedback is welcome.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 16:06:22 +00:00
5ccfa1ac79 Add memalign(align, size).
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 15:49:32 +00:00
56471f14db The keyboard driver mixed up the key press/release events for the
special keys.

Patrick Georgi explained:
The |0x80 codes are "break codes", that means, codes that are emitted
when the key transitions from pressed to non-pressed, so the modifier
was always in the wrong state, as soon as you pressed shift for the
first time.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 09:35:43 +00:00
093f6d5379 flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITE
Per test report from Bari Ari. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 00:26:11 +00:00
d4759d0f22 This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-01 01:48:07 +00:00
3153863567 Various Doxygen-related fixes in libpayload (trivial).
- Drop all '@brief's, they're not needed as we use JAVADOC_AUTOBRIEF.
   The first sentence of every description will be treated as the '@brief'
   automatically.
 
 - Also, put all documentation/descriptions on top of the Doxygen-comments,
   and put the '@foo' keywords at the bottom of the comments for consistency.
 
 - Change comments for SEEK_SET/SEEK_CUR/SEEK_END from '/**@def' to '/**<'
   in order to make them appear in the output.
 
 - Drop all explicit '@struct' lines (which are optional; Doxygen will figure
   out that it's a struct if the comment is right before the struct).
 
 - Fix various typos, whitespace issues, etc.
 
 - Fix incorrect @param variable names, e.g. change '@param n foobar' to
   '@param s foobar' if the variable is named 's'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-31 22:10:35 +00:00
0e6ad6bd09 fix typo
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-29 09:06:16 +00:00
fc58b7ee66 [PATCH]: libpayload: Document time functions
No code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:12:34 +00:00
b746178e65 [PATCH]: libpayload: Document the architecture specific routines
No code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:12:22 +00:00
483926648e [PATCH]: libpayload: change the type of the cpu_khz variable
This makes it match the extern declaration in libc/time.c -
and doxygen can find make the connection. Trivial.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:12:02 +00:00
617120c828 [PATCH]: libpayload: Document readline
No code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:11:29 +00:00
e2ad806285 [PATCH]: libpayload: Document include/libpayload.h
No code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:10:55 +00:00
4f05074188 [PATCH]: Libpayload: Remove static variables from the doxygen output
No code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 23:10:25 +00:00
d39aad9323 Add definitions for DDR2 SPD registers.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 18:23:58 +00:00
7eda890d9a Eric Biederman believes that he and Tom Zimmerman of the defunct
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
raminit code.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 18:22:40 +00:00
3a48bdcd36 libpayload: Expand doxygen definitions
Expand libpayload.h to include a main page and add individual 
groups for the API functions - this adds the Modules tab to
the doxygen output.

Specify the INPUT list rather then the EXCLUDE list of directories
to omit random .c files that we don't want.  Add clean targets to
the makefile to clean doxygen files only.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 16:53:24 +00:00
9368e4c991 fix libpayload build dependencies (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28 15:20:42 +00:00
b1b1d70d78 Capture output from 'ld --help', in order that the test
becomes meaningful. The linker puts help texts on stderr.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 22:25:55 +00:00
ec2bd53c37 If you have
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
  option CONFIG_PRECOMPRESSED_PAYLOAD=1

set in Config.lb but accidentally use an uncompressed payload, coreboot (v2)
bombs out like this:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
  Decoding error = 1
  Unexpected Exception: 6 @ 10:04000408 - Halting
  Code: 0 eflags: 00010057
  eax: 00000101 ebx: 04000400 ecx: 000003d4 edx: fffc0000
  edi: 04000400 esi: 04000401 ebp: 04000400 esp: 0013dfb4

The attached patch modifies v2's lzma code so that it assumes an uncompressed
payload if it fails to find a properly compressed payload.

Compare with the fatal error above:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
   olen = 0x00000000 done.
  Decompression failed. Assuming payload is uncompressed...
  Found ELF candidate at offset 0
  header_offset is 0
  Try to load at offset 0x0

If you don't have CONFIG_COMPRESSED_PAYLOAD_LZMA and
CONFIG_PRECOMPRESSED_PAYLOAD set and use an uncompressed payload, things are as
before:

  elfboot: Attempting to load payload.
  rom_stream: 0xfffc0000 - 0xfffdefff
  Found ELF candidate at offset 0
  header_offset is 0
  Try to load at offset 0x0

One can argue that this is a case of 'builder beware', but my counter argument
is that anything that causes unexpected runtime breakage is really, really,
really bad, and should be avoided where possible.

This patch also fixes one erroneous comment.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 21:53:11 +00:00
98829def77 flashrom: SST25VF016B TEST_OK_ PROBE READ ERASE WRITE
Per test report from Ward.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 21:28:41 +00:00
3b6412985b Add a Doxygen config file and a Makefile target 'doxy' or 'doxygen' which
generate API documentation (HTML) for libpayload in a 'doxygen' subdirectory.

A 'make clean' will remove this directory again.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 12:53:47 +00:00
3b9d1b83ab fix string function prototypes in libpayload according to sysv/4.3bsd.
Discussed on IRC, trivial

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-26 21:51:04 +00:00
54ec0afc1c Fix some Doxygen warnings and/or typos (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-26 19:37:37 +00:00
1d129fe2db How could -ffreestanding slip through here. Required because libpayload is not
going to run under an OS. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-26 11:18:38 +00:00
6adfaa690c This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,
and renames some existing macros for clarity.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 17:02:09 +00:00
6c66c95787 This patch modifies the Intel 3100 southbridge code to recognize the
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579
Integrated Processor.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 14:45:00 +00:00
1996313756 This patch implements support for the CPU core of the Intel EP80579
Integrated Processor.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 14:41:11 +00:00
b0d3e71273 A missing semicolon prevents libpayload to compile, this patch fixes that.
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-23 12:17:46 +00:00
4b461b6b78 flashrom: Recognize the Intel EP80579 LPC flash interface.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 20:31:41 +00:00
2319027d7e split the one file, as the several printing functions will continue to grow
immensly when they know more systems / cpus / chipsets

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 13:41:24 +00:00
eb02f45e6f use seperate array for core 2 cpus (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 12:42:39 +00:00
49f8df7507 this port seems somehow broken.. Now, is it using FAILOVER, or is it not?!
./s2912_fam10/Options.lb:default FALLBACK_SIZE=ROM_SIZE-0x01000

Please, someone with the board test this and fix it accordingly.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 09:17:30 +00:00
f83325ddf9 Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports
the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet).

Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 21:51:39 +00:00
989c17810b trivial fix for memcpy return code in case someone uses it.
Thanks to Ulf Jordan for figuring this out!

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 19:18:58 +00:00
33e6d5dec6 Add Tyan S2912 platform with AMD Family 10 support.
Thanks Arne. Good job.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:59:34 +00:00
34b9f867cd misc fixes:
* give struct memrange a name
 * add explicit cast.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:51:30 +00:00
99c0856903 make all drivers relocatable. Per default, an 1:1 mapping is assumed.
Patch to add relocation to libpayload will follow.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:49:53 +00:00
addf443e12 * add readline()
* add fatal()

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:48:02 +00:00
6e51ceeb2b * add readline()
* add fatal()

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:47:18 +00:00
0e4671e305 replace static functions by macros, because otherwise every unused function
would warn. Bad thing for all -Werror folks out there.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:46:02 +00:00
59fb9a2bfa add functions to query cursor position to video layer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 17:44:49 +00:00
96f57aee0a libpayload: Fix the memcpy functions
There was a bit of confusion in the memcpy functions - we could simplify
things slightly without having to revert to 8 bit copies on a 32 bit
system.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 16:55:05 +00:00
0740cdaac9 fix typo in ctype.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 16:53:47 +00:00
2aea11f57f Add a kconfig option to choose between outputing ACS characters or
their plain ASCII fallbacks over serial console.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 19:29:41 +00:00
364317b199 Fix tinycurses color output on the VGA console.
The CGA compatible 16 color VGA text mode expects Intensity RGB color
specifications, in the order IRGB from most to least significant bit.
Curses COLOR_ macros follows ANSI X3.64/ISO 6429/ECMA-48, specifying
RGB color in the order BGR from most to least significant bit.
Consequently, it is necessary to swap the red and blue bits.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 19:28:42 +00:00
43a800c55f Add more information to the libpayload README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 18:55:33 +00:00
26ba091d51 inteltool: match cpuid before attempting to print MSRs (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 10:58:09 +00:00
f394c7593f add block io functions
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-16 15:17:36 +00:00
11e45cd3ff trivial fix: ipchksum takes an unspecified input blob, not explicitly a number of shorts.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-16 15:16:36 +00:00
67b35cb163 fix typo in superiotool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-15 09:46:55 +00:00
ee673194b4 * fix memory allocator bug that lead to freelist corruption on the first malloc
(and spent 8 bytes too much per malloc)
* if the memory allocator detects freelist corruption, print a message
  instead of silently dying.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-14 14:40:10 +00:00
8e65adb67d Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codes
in a couple of occurences)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13 12:16:15 +00:00
bc5379aefd off by 1. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13 09:38:12 +00:00
28dff395ef commit real fix to pci module of coreinfo (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13 08:23:06 +00:00
87f0b13256 add PCI_BUS macro (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-13 08:21:27 +00:00
74eedaee8d Fix incorrect mapping of ACS_PI for VGA console. A pi should look like pi and
not like Gamma.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 20:23:00 +00:00
b865070023 License updated to GPL v2.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 19:45:12 +00:00
96b734ceca libpayload: fix type in keyboard driver. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 14:19:40 +00:00
716c720468 flashrom: Fix error -EINVAL on mmap()
Don't calculate "flash_baseaddr" until the final value of "size"
is known, otherwise we end up trying to map a page right after
the end of memory.

Fixes #112.

Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 11:58:00 +00:00
d133d9a230 This patch updates coreinfo to use the ACS_ macros for line graphics.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 20:35:32 +00:00
cc8a9934df Document all of the external code we use in libpayload (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 20:34:50 +00:00
b4d4bac1c4 Add support for line drawing characters and the alternate character set.
This enables using the ACS_ curses macros with libpayload.

The translation from ACS_ macros (or characters with attribute A_ALTCHARSET)
is done using one acs map for the video console, one for serial console
(xterm/vt100/vt220), and one fallback, from which an ASCII substitute is
taken if the device specific map doesn't contain an entry (ie NUL).

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 20:34:28 +00:00
42a0c80b9b Make cursor positioning work by using both halves of the VGA cursor
position register.
 
Have vga_scroll_up() and vga_clear_line() present row/column arguments to
the VIDEO() macro in the right order.
 
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 17:19:10 +00:00
12e27266c3 No really, _these_ should be the last occurences of CONFIG_ without
config.h in libpayload - also removed CONFIG_ instance in libpayload
which would have been dangerous.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 17:10:58 +00:00
5e354b7a43 these should be the last occurences of CONFIG_ without config.h in libpayload.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 16:58:23 +00:00
663ea08ef1 these use CONFIG_ variables, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 16:55:35 +00:00
cb7a7c6b8c video.c uses CONFIG_ variables, so it needs config.h (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-11 16:52:14 +00:00
b96a2ffaa7 Bugfixes to serial output functions: vt100 has bold with \e[1m,
upper left corner is (0,0) in curses, but (1,1) on the vt100.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-09 20:17:22 +00:00
c5c1442fab Fix garbage characters on screen. mvwaddch inserts one character,
not a character array.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-09 20:15:00 +00:00
68285699da Fix signedness problem in memcmp.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-09 19:34:56 +00:00
f1e127472b i messed this up.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 18:36:14 +00:00
c7e92b3cfe compile fix (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 14:17:46 +00:00
6986358341 new menu structure for libpayload
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 13:45:03 +00:00
fef915c7c4 fix some more warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 13:36:53 +00:00
d00bdd0813 fix warnings when starting make menuconfig
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 13:07:38 +00:00
5e6e98a518 flashrom: ST M50FW040 TEST_OK PROBE READ ERASE WRITE
Per test report from Marcel Konrad. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 10:55:57 +00:00
2e4df11d81 Drop useless .gitignore files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 08:43:06 +00:00
31a4f7bc5d Drop useless .gitignore files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 08:42:05 +00:00
e55b32ab62 Update the kconfig copy in libpayload to a much more recent one. Among
other things this supposedly also fixes a number of build issues on Mac OS X.

This is more or less the same version (i.e. equally recent) as we have in
coreinfo and buildrom now.

This patch also includes the libintl.h fix from r3475 (coreinfo).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 07:56:07 +00:00
dc93affe72 Enable both IDE ports for our qemu target.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 00:08:01 +00:00
a2c951edf7 Clean up whitespace and comments style. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 22:00:51 +00:00
88ad6b0f91 Add a full set of pci access functions.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 19:09:17 +00:00
85c7aec73e fix stack protection detection with Jordan's suggestion
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 15:28:31 +00:00
c359124ef4 fix cross compilationor libpayload / coreinfo by honoring
the setting of CC in the payload (coreinfo) when calling
 
make CC=i386-elf-gcc AS=i386-elf-as AR=i386-elf-ar STRIP=i386-elf-strip

This still does not cope with the hardcoded -fno-stack-protector in
libpayload's Makefile.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 15:22:01 +00:00
695cff30e1 Cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 14:35:39 +00:00
8b17bd3136 fix make menuconfig if no libintl.h is found. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 10:32:54 +00:00
95a6e1cab2 add get_option to libpayload, so coreboot cmos options can be queried.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-07 10:21:05 +00:00
ebc92186cc Add the contents of buildrom's
packages/mkelfimage/mkelfimage-autoconf.patch
  packages/mkelfimage/mkelfImage-2.7-x86_64.patch

to our svn copy of mkelfimage.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

These are the original commit messages from the buildrom svn tree:

-----------------------------------------------------------------------
r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines

[BUILDROM]  Fixup mkelfimage

My patch makes it so all targets use vmlinux and 2.7.  Including
the mkelfimage patch from Yhinghai Lu.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

------------------------------------------------------------------------
r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines

[BUILDROM] Fix breakage in the new mkelfimage autoconf scripts

Whack the autoconf scripts in mkelfimage to allow us to pass our
stack protection flags in.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>

------------------------------------------------------------------------



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-06 20:37:38 +00:00
a70872cfde Move out some hardcoded strings in coreinfo to become Kconfig variables.
This is useful for use with (e.g.) Bayou in order let the user customize the
payload name, description, version, etc.

For instance, instead of using stock coreinfo and calling the payload
"coreinfo" and the Bayou menu item "Show system information" a user might
only be interested in an NVRAM dump payload. Thus, he/she can enable
only the NVRAM coreinfo module via Kconfig, and tell Kconfig to call
the payload "NVRAMdumper" and the Bayou menu item "Show NVRAM contents".

This is build-tested, and tested against Bayou in QEMU.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-05 14:36:20 +00:00
754edf712c Remove duplicated code which is already in libpayload (trivial).
Build-tested against the latest libpayload.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-04 21:02:07 +00:00
83233d0a15 Add missing #include.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-04 21:00:49 +00:00
5f1037cb69 Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).
This works fine in Linux if you use the 'irqpoll' kernel command
line option.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-04 15:40:45 +00:00
9ecf8fb1cf Remove welcome message from elfboot. None of the other subsystems have their
own welcome message.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03 10:38:26 +00:00
912857ec6c fix lots of warnings for cache as ram builds (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-03 10:35:06 +00:00
87c938f139 adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"
in a number of places.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 19:17:42 +00:00
685240610b Go back to SIPI WAIT state for those CPUS defining the newly introduced
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
multiple cores.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:15:23 +00:00
ab8bb8b061 update copyright year (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:13:58 +00:00
a56edacbe3 This patch
* fixes a warning
* puts some debug messages to spew because they're only useful to debug CAR
* print an explicit message "Uncompressing..." instad of "Copying..." when 
  coreboot_ram.rom is compressed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:09:12 +00:00
42fb71f626 tested another intel chip (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 14:58:49 +00:00
db1b608fca oops, forgot these in the cleanup.. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 19:22:34 +00:00
11a2014f49 a heuristics is something different
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 13:08:33 +00:00
75f519ca86 Typo, thanks to Idwer for spotting this. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:53:04 +00:00
51754a38f2 clarify in the printks what function is actually called. This little smart magic
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.

(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:28:38 +00:00
1409136281 clean out obsoleted config.lb rules and output, fix indenting (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:20:26 +00:00
48b85fc6a9 use printk, when possible. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:12:37 +00:00
5a522d4a42 match against all steppings of a CPU model, because these are _model_ drivers.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:11:00 +00:00
ac555b1c69 serial.inc is not used anywhere. drop it (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:06:08 +00:00
57d2af895e same spelling in all mtrr output.. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:54:55 +00:00
df6c858218 drop unused code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:53:39 +00:00
96a60363f8 coding style fixes (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:50:52 +00:00
20ffc03efa fix compile warnings of rom_stream.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:48:00 +00:00
951c62f074 add some SPD values from specs. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:40:16 +00:00
a91e0fe441 function prototypes don't need extern. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:39:35 +00:00
749c05e0fd fix warning in vga console code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:38:23 +00:00
fec2c4f47f fix typo in coreboot_ram.ld comment (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:37:33 +00:00
bba53ed1a7 fix typo in commend of generic_sdram.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:36:40 +00:00
3c580b539e clean up comment in onboard.c (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:35:46 +00:00
807dec0ebc clean up Config.lb in lib/ (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:32:12 +00:00
7a4f688f4f fix warnings, make mptable struct members explicitly packed, as they're
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:31:08 +00:00
d98cf5bed9 fix typos and warnings in the device tree code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:25:41 +00:00
8533606db7 CONFIG_LOGICAL_CPUS=2 does not make sense because it is a BOOL. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:21:47 +00:00
62ab563ae1 fix build warnings for buildrom (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:20:33 +00:00
7e4954cd3f fix typos in config.g, and don't arbitrarily hide some build information
(doesn't make sense in v2). For silent build, use make -s
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:20:09 +00:00
96e3022cd4 This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.

The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.

Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 23:22:59 +00:00
2aa804fdcc Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it
went missing....

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 22:27:19 +00:00
35b5361636 Add AMD Fam10 B3 default settings to match AMD example code.
Includes setting for most recent errata.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:44:23 +00:00
51737cf7da Update to the latest AMD Fam10 microcode patches.
Add platform option for patch file name.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:11:20 +00:00
c3ec1ac331 Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23 21:04:03 +00:00
3a8556354d Missed a const in my previous checkin, r3426 (trivial).
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 22:23:57 +00:00
ec9e6e33a4 flashrom: Winbond W39V040C and MSI K8T Neo2-F
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.

The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.

Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 17:48:40 +00:00
3d135e6033 Add support for the Winbond W83697HF Super I/O.
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 14:49:04 +00:00
a3f057935c superiotool: add support for SMSC SIO10N268 (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19 14:42:21 +00:00
a12eb6a7e5 add support for 2 new SMSC superio chips. Information is a bit ambiguous
and scattered within the datasheets. (trivial patch)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19 14:07:35 +00:00
941aaee885 Random coding style fixes and simplifications (trivial).
This will even reduce the final payload size a bit.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-18 14:08:18 +00:00
eafceddf6c Add manual HT BUID fixup to detect previously set BUIDs in early init. This fixes the non-coherent(sb) link running at default speed.
Fix HT event notify to output useful information.

Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:54:06 +00:00
212486e9f6 Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:50:37 +00:00
2df291574d Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17 19:44:08 +00:00
aee0796506 Clean up comments, whitespace, and copyright date in the AMD HT code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-16 21:09:31 +00:00
049814cc8f Add missing Intel CPU (trivial).
Tested by me on actual hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15 13:22:21 +00:00
2c39c4c5a9 There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12 00:03:26 +00:00
2f45e770d7 Fix and clean up coreboot image detection heuristic.
Additional compile fix for NetBSD.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-11 00:06:38 +00:00
2fbbb29e54 Add a coreinfo module which can hexdump arbitrary RAM regions and
allows you to scroll through the RAM contents.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-08 16:18:38 +00:00
a4793182e8 flashrom: Trivial SPI cleanups
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.

I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07 06:38:51 +00:00
5dc95de5e6 flashrom: Trivial indent fix in ichspi.c
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07 05:14:06 +00:00
5bc95858d5 r3415 removed symbolic constants for device IDs by accident.
flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.

Trivial.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 23:04:01 +00:00
ce17f6bdb0 flashrom: Add AMIC A29002
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.

The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.

A29002T PREW functionality was tested and works.

This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.

Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 17:35:30 +00:00
3c75baea46 Adding support for flashing system with Nvidia MCP67
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05 09:48:30 +00:00
e9dcb8931e flashrom: Add PCI IDs for EPIA-CN
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
with their 1106:aa08 subsystem id:s for autodetection.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05 04:12:37 +00:00
1a20cdec2c Minor cosmetics, e.g. make stuff fit in 80 chars/line etc. (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 19:26:44 +00:00
3244b984e2 Mark SST49LF040B as tested.
Thanks to Paul Seidler and Ward Vandewege for testing.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 19:08:52 +00:00
4321f8be6e Mark the SST SST49LF040 as OK (tested by me), all operations (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 18:58:58 +00:00
8fe1a42e7d flashrom: Winbond W25x80 TEST_OK PROBE READ ERASE WRITE
Per test report from Björn Gerhart. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 16:54:05 +00:00
039b848066 Improve coreboot image detection heuristic in flashrom. It's not
absolutely perfect, but the likelihood of this check to fail is
0.000000000000000000000000013 (1.3*10^-26) which is good enough for me.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 14:40:06 +00:00
f74c208256 flashrom: probe_flash() cleanup for better code readability
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 17:15:47 +00:00
cac7286c0b set w39v080fa to fully supported. I'm am flashing this chip several times a
day.
Also enable unlocking which is only needed when running coreboot, that slipped
in the original commit and through the original review ;-) So it must be
trivial enough.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 13:33:09 +00:00
c3c4472bd1 flashrom: Update to TEST_OK for Winbond W39V040FA PROBE READ
Thanks to Jake for the test report!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 03:07:46 +00:00
1ae669771c flashrom: Don't rm *~ in make clean, who knows what files that could be
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 03:03:58 +00:00
39a582569a flashrom: Unknown vendor:board message can be triggered by -m too
Thanks to Stefan for pointing this one out.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 00:59:29 +00:00
12224acb6f flashrom: Case insensitive matching of vendor:board strings in coreboot table
Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in
flashrom.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 00:47:30 +00:00
d9b7ae8bec First attempt to clean up SPI probing and create a common
construct: the flash bus.

At some point the flash bus will be part of struct flashchip.

Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.

Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 23:45:22 +00:00
e16d43c041 Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing code.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:48:54 +00:00
d8a7e7d043 Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:45:17 +00:00
4a17e02003 This patch adds support for VIA SPI controller on VT8237S. It is similar with
few documented exceptions to ICH7 SPI controller.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:38:30 +00:00
7b425c1c11 Add a debug marker after ICH SPI opcode programming.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 10:57:13 +00:00
c2e8fd42b0 Adds a field to the serial port descriptor about the configured line speed.
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 06:41:12 +00:00
891f1a2650 flashrom: Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.

Also fixes a build error in ichspi.c with gcc 4.2.2.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 01:30:41 +00:00
50e4a095dd Use symbolic constants for PCI subsystem probing in flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-28 23:02:22 +00:00
a1dd9142c6 * ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27 16:28:34 +00:00
20e0599e69 indent according to development guidelines (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27 15:18:20 +00:00
98f32bf8ef Initial support for the A-Trend ATC-6240 board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26 19:42:25 +00:00
8613d628d5 Winbond W39V080FA: Probe and Read are OK.
Signed-off-by: Jens Kühnel <coreboot@jens.kuehnel.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26 11:57:27 +00:00
d1cd7bc054 flashrom: Test status OK for ST M50FW040 PROBE READ
Per test report from Alex Perez. Thanks Alex!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 08:18:13 +00:00
dc64a270be flashrom: Test status OK for Macronix MX25L8005 PROBE READ ERASE WRITE
Per test report from Andrew Paprocki. Thanks Andrew!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 04:17:14 +00:00
0667afd294 flashrom: Increase delay in probe_jedec() after Product ID Entry to 10ms
We should follow data sheet timing, even if chips have been tested to answer
faster in the field.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 02:09:09 +00:00
606a207d9b flashrom: Slight restructure of SPI probe_ functions
Preparation for a probe optimization patch. This patch does not change any
functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2.

The idea is to have error checks return error immediately when something
fails, rather than having code inside an if block where the condition
tests for success.

This means: Less indentation, more clear what the code is checking.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 01:22:03 +00:00
12afdd82ac Some flashrom documentation fixes, and removal of duplicated info (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 18:50:25 +00:00
6f78cd6eba flashrom: A few changes were committed before the DoC remove, update README.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:54:03 +00:00
8b835974cd as per Peter's suggestion. clean binary in make clean
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:15:03 +00:00
b05b6a2555 flashrom: Remove dead M-Systems Disk on Chip code
DOC support has been disabled by default for many years. The write function
does nothing but print text. It has a call to write_page_md2802() commented
out, but that function does not exist. This is dead code with ugly #ifdefs.

Updates README to reflect that there was a time when there was code, but it
didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:06:41 +00:00
fb73fa1bcb Enable hardware fan control for m57sli.
Tested on v1 and v2 of the board.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 14:33:17 +00:00
14669ae023 This patch allows support for multiple so-dimms, single or double sided.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 04:22:46 +00:00
67939dc75f flashrom: Update test status to TEST_OK_PREW for ST M50FLW080A and SST49LF008A
Many thanks to Julio Cesar Costa for the test report!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 02:04:49 +00:00
a6b6711cf7 flashrom: Some Makefile cleaning
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 02:00:39 +00:00
8239a1b2fd flashrom: Fix OBJS in Makefile to compile stm50flw0x0x.c like the others
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 04:39:17 +00:00
5f10902f39 flashrom: Uppercase AMIC since that's what they write in datasheets.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 04:23:10 +00:00
0e7d54a5b7 flashrom: Update comment to match delay change in probe_jedec() r3373
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 01:02:20 +00:00
ad2ef07ff7 flashrom: Update test status for Atmel AT29C020 and SST29EE010
Thanks to Urja Rannikko for reporting test results with these flash chips.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 00:21:22 +00:00
4ff88b4d49 flashrom: Increase delay in probe_jedec() to 2ms to reliably detect AT29C020
Run time is increased a few 100ms but this is needed for reliability.
I consider this trivial.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 00:19:52 +00:00
5f2e30c9ed flashrom: Show expected and read byte on verify failure. Trivial.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 02:58:42 +00:00
7600c48bf4 coreinfo: Enable serial support
Remove the lines preventing serial + curses thanks to r3370. Trivial.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 00:02:52 +00:00
3b4706591c libpayload: Support curses for serial
Support the curses interface over serial by supporting a minimal vt100
terminal.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 00:01:42 +00:00
4e48408059 Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 00:01:14 +00:00
42b127fe22 flashrom: Add support for AMIC Technology A49LF040A and do not probe W29EE011 anymore
Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
using _jedec and _49lf040 functions.

An issue was found with probe_w29ee011() for the Winbond W29EE011, which
caused the A49LF040A to no longer respond to any commands.

Ward made a patch to disable probing by default for the W29EE011 following
some discussion. Using -c W29EE011 will make flashrom probe for the chip.

Peter did some more datasheet diving and found that the Pm49FL00x functions
suited this chip quite well because of the block locking registers in
A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.

Ward confirmed that this works on alix.2c3 too.

Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 13:36:34 +00:00
646eb245e6 flashrom: Force read unknown flash chips
When flash chip detection fails, it is still useful and possible to read the
flash chip contents. If no flash chip is found in normal probes and the
-f -r -c CHIPNAME options are given, a successful probe for the specified
chip is forced, and then flashrom reads the flash chip using either the read
function for the specified chip, or if there is none, a simple memcpy().

The patch also moves the global variable int force in flashrom.c into main()
and passes it as a parameter to layout.c:show_id(), which was the only other
function that used the variable. This is needed to avoid confusion with the
new parameter int force which is added to flashrom.c:probe_flash() and used
to force probe success for the chip named in char *chip_to_probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 02:08:40 +00:00
01441bd5cf flashrom: Board enable and autodetection for GIGABYTE GA-7VT600
Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with
mainboard subsystem ID for board detection.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-13 01:39:45 +00:00
bc18fbbc60 flashrom: Add support for Amic Technology A29040B flash chip.
PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11 02:24:15 +00:00
d1f698ac27 flashrom: Board enable and autodetection for BioStar P4M80-M4.
Thanks to Reinder for clean room reverse engineering and data sheet diving!

This board is autodetected because there are some good BioStar subsystem IDs.
Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and
onboard UniChrome Pro IGP graphics with subsystem BioStar 1202.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11 02:22:42 +00:00
d63e0d041e Changes Makefile generation so that recursive "make" calls read
"$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build.

Signed-off-by: Pierre Pronchery <khorben@defora.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-08 23:05:24 +00:00
38ee631aef fix via epia cn abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-07 12:35:11 +00:00
92af509faa Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware.
Signed-off-by: Tom Sylla <tsylla@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-07 11:36:30 +00:00
6196416c27 Ward writes:
SST SST49LF160C is confirmed to work for PROBE READ ERASE WRITE, at least on
2 MCP55-based boards (gigabyte m57sli v1 and supermicro h8dmr).

On the m57sli board, it only works > 512K when booted into coreboot; the
proprietary bios seems to do something weird where it locks rom access down
to the first 512K of the chip.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-03 00:22:00 +00:00
39d4e5f790 abuild: fix gnu getopt detection (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-28 08:40:23 +00:00
41b35b52d8 Revert r3357 and fix it as intended to (forgotten header commit instead of typo)
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 23:51:55 +00:00
012fbc796d Fix typo introduced in r3356 that breaks build (trivial).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 22:20:30 +00:00
68229f35d1 flashrom: MX25L4005, S25FL016A, W39V040B, W39V080A, SST49LF008A tests.
I have tested MX25L4005, S25FL016A and W39V080A myself.

Thanks also to the following testers:
SST49LF008A Bernhard M. Wiedemann
W39V040B Dan Lenski

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:54:09 +00:00
5083811458 coreinfo: Specify a name, listname and desc item for coreinfo
These values are consumed by the chooser payload.  listname is 
presented on the chooser menu.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:07:47 +00:00
fc697ad028 libpayload: Add PAYLOAD_INFO macro
Adds the PAYLOAD_INFO macro to store payload information in a data
section in the ELF which can be consumed by other entities.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:06:54 +00:00
d9ce08dc8c not sure why this ever worked. Add --xml / -x to the supported options (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:06:30 +00:00
9e734c29cf libpayload: Add a function to verify the checksum on a LAR file
This function verifies the checksum on a LAR file.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 19:57:53 +00:00
02a4e7f6f8 sync latest version of abuild (0.6) (trivial patch)
- parallel building
- fix non-gnu-getopt systems
- silent mode

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 18:29:26 +00:00
ee9e1a3911 Mark SST49LF004A/B as tested (trivial).
Tested by me on actual hardware (all operations) - Artec Group DBE62 with SST 49LF004B

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 09:10:52 +00:00
5dfee60cac Mark the following chips as tested (trivial).
- AMD Am29F040B
  - SST SST39SF020A
  - Winbond W29C020C
  - Winbond W29EE011
  - Winbond W49F002U

All of them tested by me on actual hardware (all operations).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-26 23:12:25 +00:00
6eb5012a8c A bunch of cosmetic improvements (trivial).
- Fix typos and inconsistencies.
 - Drop duplicate line which tells us the chip name twice.
 - Also print the chip vendor, not only the name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 22:47:04 +00:00
1a02c8eeed Mark more chips as tested (all operations), tested on ASUS P4B266 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 21:26:42 +00:00
dccaf5fd00 Add support for the ASUS P4B266 board.
Tested on actual hardware.

This patch add an ich_gpio_raise() function which can be re-used by other
board-specific funtions which need to raise GPIOs on ICHx southbridges.

This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7,
as it turned out the ICH2 (and other ICHx) code works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 21:19:38 +00:00
f40532c2b3 Add support for Amic A25L40P SPI flash.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:42:23 +00:00
4b1cde877c Changes to make flashrom compile (and work) on FreeBSD.
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:22:45 +00:00
42319797a6 This is a simple patch which allows payloads to be placed in memory in
the range of 0xf0000-0x100000, where the Coreboot tables live in v2.
As long as the payload doesn't need the tables, it seems harmless, so
why not just print a warning?

This allows v2 to load "legacybios" without having to have a separate loader.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
It'll be fine for testing and doesn't really break anything that did
work before...

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21 22:10:38 +00:00
29413c76ab Add KEY_ESC (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21 13:49:03 +00:00
4cc35fdfa9 Myles reported SST49LF080A status -> TESTED_PREW
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21 07:10:15 +00:00
98cc0566ca coreinfo: Use the ESC key to exit the payload
Enable the ESC key to close coreinfo - useful if you are using a chooser
and want to return to it.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 20:16:34 +00:00
9b1c7c1645 coreinfo: Fix the subwindow refresh based on the libpayload changes
Changes to libpayload to fix subwindows broke coreinfo.  This fixes it,
and improves performance by eliminating the entire screen refresh every
second.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 20:16:03 +00:00
9dac1b4cca libpayload: Add an exec() and i386_do_exec() function
Add functions for libpayload to execute other payloads in memory,
and have those functions return cleanly.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 20:10:49 +00:00
506980808d libpayload: Add larfptr function
Add a function to get a pointer to the start of a LAR entry.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 20:09:42 +00:00
d43841defc libpayload: Fix curses subwindows
This fixes subwindows in curses so that they draw and refresh correctly.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 20:08:11 +00:00
9d10dc4ffc Add post-RAM init code for the Fintek F71805F Super I/O.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Richard Stellingwerff <remenic@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-20 18:10:24 +00:00
fcb2a311c7 Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.
This also contains various improvements of the CN700 code in svn.

Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-19 12:17:43 +00:00
710e8b1ad0 Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).
Tested on hardware:
Intel Northbridge: 8086:1a30 (i845)
Intel Southbridge: 8086:2440 (ICH2)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17 21:33:35 +00:00
ce1fb9d4e9 flashrom: Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.

This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c

Thanks go to Nikolay for this patch.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17 01:08:58 +00:00
fb047a6a54 I looked at the datasheet and erase_sector_39sf020() is totally and
completely wrong. It was a straight cut'n'paste from SST 28SF040 code
and the person doing the cut'n'paste didn't even bother to check the
data sheet. The SST 39SF020 is completely incompatible with the 28SF040.

No need for replacement. According to the data sheet, standard JEDEC
commands will work and we have those commands in the tree already.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 21:11:53 +00:00
85e46e6bd6 Doesn't have to be executable (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 18:56:24 +00:00
2ee5c9e21b Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 18:08:54 +00:00
0fd8ccd7e7 New Target and initial support for the Thomson IP1000.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 15:43:35 +00:00
d9fa5d2aba ICH8 and ICH9 have an almost identical SPI interface, only the location
of the SPIBAR differs. Add ICH8 support to the ICH9 code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 14:39:39 +00:00
ed24da499d Add support for the Atmel AT25DF321 SPI flash (tested).
Change ST M25P32 status to tested.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 13:00:28 +00:00
fac0afb87d Add support for SPI chips on ICH9. This is done by using the generic SPI
interface.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 12:55:55 +00:00
e7b1157764 Enable IT8716F LPC-to-SPI write cycle translation in flashrom if the
IT8716F decodes any address to the attached SPI ROM.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 00:19:52 +00:00
8e8eb7d261 Print detailed status register information for SST25VF series flash.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 22:32:08 +00:00
da69582ce4 This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 13:44:33 +00:00
e3da00de8d Lots of new SST flash chip IDs. Only a subset has been added to
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:24:43 +00:00
a4868c44b5 Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:19:49 +00:00
c7d29013db Some NSC Super I/Os can have their config port at 0x15c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 22:56:47 +00:00
9a6b6b51df Cosmetics, whitespace, coding style, partially ident-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 21:20:55 +00:00
621c09563b libpayload: implement wborder function
Implement the wborder function for curses to draw a box around a window.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 20:10:02 +00:00
3148935557 libpayload: Fix the putc function
Reverse rows and columns on the video putc() function, and watch printf 
work again.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 20:07:31 +00:00
f9b99450ce add ICH7-M and ICH7 DH to inteltool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 20:05:00 +00:00
3f09561ec4 Add more infrastructure for flashrom ICH9 support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:51:22 +00:00
58a1cc1d34 fix license mentioning in manpage (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:47:32 +00:00
9f7af6ef40 trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:22:59 +00:00
d466e6a874 trivial patch to fix options. Thanks to Uwe Hermann for the hint!
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 13:52:50 +00:00
e173f9904c Add the Intel 6300ESB as known chipset to the chipset struct enables.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:22:38 +00:00
42aab08d84 Fix crash caused by division by zero for unknown flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:09:31 +00:00
68db3a2bdc Check the JEDEC vendor ID for correct parity. Flash chips which can be
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:03:06 +00:00
b69e46bca3 Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
have different register meanings, so they get their own lookup tables.

This is a trivial patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 11:38:22 +00:00
1984067a86 Add lots of ATMEL SPI flash chips to flash.h.
Add a few flashchips already mentioned in flash.h to flashchips.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 04:27:02 +00:00
b77fb6bd52 flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 23:03:12 +00:00
03646bebbe Add new revised inteltool that dumps all kinds of chipset information and drop old
gpio_dump utility.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 22:14:21 +00:00
56cc34a9a7 This is a trivial patch which fixes the tint build by removing the extra
typedef for time_t.  The other half bumps the tint patch revision in buildrom
to take advantage of it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 21:29:48 +00:00
967214d559 flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:58:23 +00:00
a2e7c48d38 Change the SPI parts of flashrom to prepare for a merge of
ICH9 SPI support. In theory, this patch has no behaviour changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:01:22 +00:00
6d3fdf9b62 MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK
by Harald Gutmann.
SST39VF040 has been confirmed to probe OK by misi e.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 21:19:53 +00:00
c95f2a737a Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF
series has the same IDs.
Add short AMIC vendor ID to flashrom.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 14:25:31 +00:00
d0e687ac39 Fix the build when serial console support is disabled (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11 16:13:24 +00:00
134aaaec50 Quickfix to repair 'make clean; make menuconfig' (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11 15:51:31 +00:00
cd0b5631de Improve flashrom SPI abstraction, second step.
This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.

The third step would be calling SPI controller functions via a function
pointer.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:40:51 +00:00
31ab0314d1 flashrom: Rename generic_spi_*() functions to spi_*()
This is a very early step toward cleaning up SPI code in flashrom.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:07:52 +00:00
fa36f5048f coreboot-v2: Disable second serial port on Norwich
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-09 15:32:46 +00:00
bbd337e364 Add support for dumping ITE IT8718F EC registers (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 14:37:12 +00:00
8cb2458005 Don't split up register list in two blocks, otherwise "Register dump:"
will be printed twice in the output (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 13:50:23 +00:00
15da8ed98b flashrom: Probe for up to 3 flash chips.
Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.

[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]# 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 00:31:44 +00:00
83a965d2ef Implement GPIO configuration routines for the Intel 3100 southbridge,
allowing you to specify per-mainboard GPIO settings.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 21:57:12 +00:00
aa6e378c4e coreinfo: Add a module for browsing the boot LAR
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:43:15 +00:00
681ec27e2c libpayload: Add LAR walking support
Add suport for walking LARs.  These try to emulate the f*
functions from POSIX, though they are obviously different
in their behavior.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 20:34:02 +00:00
35993a231e Fix a typo in lbtdump output (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 19:21:18 +00:00
193378698e coreinfo: Show the current time and date in the menu
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:15:31 +00:00
de7fc55920 We were in the risk of running out of space in the option menu at
the bottom of the screen - this turns the function keys into
categories and then list specific items as part of the category.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:03:16 +00:00
7ce2666249 The previous commit had more in it then I wanted - so I am reverting
this and re-commiting so that the history and comments are correct.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 22:00:55 +00:00
646ee3eae9 coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO
rdtsc.h shouldn't be included unless we really need it (and use it).
Trivial.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 21:32:52 +00:00
9d9518ff54 cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 16:56:47 +00:00
c314b2fcec This patch changes Config-lab.lb for qemu to use lzma like the other targets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:17:43 +00:00
2342f8b343 This patch adds pc keyboard init function call for qemu in v2 since some payloads assume
Coreboot initializes it.  Coreboot v3 already does it.

Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 15:02:22 +00:00
4f9141758e Fix various issues on MSI MS-7135 board.
- W83627THF is strapped to 0x4e, not 0x2e
 - there's no device 9 on PCI-E x1 bus, it should be device 0
 - add mptable entries for AGR slot, based on info in user manual
 - enable floppy drive controller so that some legacy VGA ROMs will work

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06 13:26:32 +00:00
33c57f8403 This patch changes the payload path for Config.lb; this board is supported by
buildrom and this bit was forgotten during r3092.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-05 20:50:58 +00:00
4934fc03cb flashrom: Add a tested bitmap field to the flash chip table.
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.

All chips are TEST_UNTESTED for now.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03 04:34:37 +00:00
a9a5f49d8f By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
for both serial ports, making it challenging to use COM2 for the early
console.

Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30 18:29:35 +00:00
e21f836e4e flashrom: Enable ROM decode range to 1MB for vt8237r
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-29 13:46:38 +00:00
b19973eb8b The generic jedec.c does not work for the ST M50FLW flash
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.

It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 17:51:09 +00:00
26e08b5abe flashrom: Handle NULL probe, erase and write function pointers in the
flashchips table. The read pointer was already checked properly.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 14:47:30 +00:00
e2271430c5 libpayload: Add gettimeofday() and friends
Add a gettimeofday() implementation - it works pretty well, but it
drifts a little bit so its not very suitable for keeping time.  It
works best to track changes in time over small periods of time.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:11:02 +00:00
d772e1e7fe libpayload: Fix a small but aggressive bug in printf()
This was causing the returned counter value to be one more then it
should be when printing a single character.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:10:23 +00:00
63f181f97c libpayload: Enable keyboard translation so that we can use scancode set 1
The qemu keyboard controller defaults to using scancode set 2, we use set 1.
Turn on the translate mode in the keyboard controller to force the issue.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:09:39 +00:00
24a0404759 libpayload: Fix malloc allocation
Apparently the previous version worked on luck.  Fix the allocation
and add parens to better guide the compiler.  Also, halt() if 
the heap is poisoned (like by an overrun).  Finally, fix calloc()
so that it actually works.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:08:47 +00:00
c781584936 libpayload: Add the null terminator to the end of the duplicated string
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 23:07:39 +00:00
20ce60c9aa Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.
The FAM10 code takes up more space in the uncompressed "ROMCC" portion
of coreboot. Also, It is still growing as features are added.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 22:56:57 +00:00
65e08040f9 Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 21:34:25 +00:00
7ca3ec2e5c Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 02:02:33 +00:00
6fd385d154 Payload location fix for buildrom (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25 00:38:41 +00:00
c1cbff217a Add CPUID processor name string support for Fam10 CPUs.
Peter did a nice job cleaning up my initial patch. Thanks!

Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>

Acked-by: Marc Jones <marc.jones@amd.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 20:03:13 +00:00
403b89a14f On APs the ClLinesToNbDis was being left enabled from CAR setup.
Disabling it should help performance.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 19:49:59 +00:00
202625e61f This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)
is based on amd-lx800/cs5536.

Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 13:37:01 +00:00
20ba8eb7ab Flash pages, which where excluded from updating using the exclude or the
layout option, as well as areas, whose flash contents already contain the
desired data, will be skipped.
These ensures absolute data security of critical areas (BIOS boot block), 
e.g. against a sudden power off or a CPU hangup during flashing. As a
nice side effect, it speeds up the flash process, if the BIOS to be flashed
is very similar to the version in flash. 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 09:07:57 +00:00
a149131415 Same old story: Fam10 needs more space again. My calculations say it
needs 172 more bytes, give it 512 and hope that's enough for a while.
Trivial.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 22:54:40 +00:00
e3e4981813 Trivial payload location changes for buildrom.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 22:01:55 +00:00
e4c98d2899 These config files are so that buildrom can use these two boards.
Myles

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 21:06:08 +00:00
3d1d3b23f0 This is the sata irq patch for s2895 and ultra40. It also changes some broken
white space in the s2892 and s2891 mptable.c files.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 20:40:55 +00:00
0eec1a8e8e Fix irqs for secondary ports on both sata controllers.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 17:55:25 +00:00
bb33e4a2fe Detect SMSC SCH5027 (trivial).
This chip seems to be very similar to the SMSC DME1737, for coreboot
purposes it might even work without any code changes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 09:27:18 +00:00
c4a4116440 This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.

Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.

While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 00:40:39 +00:00
a74a8ffa07 Clean up and remove late initialization code that is no longer needed.
Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization. 
Much of this code is leftover from porting from K8.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:32:56 +00:00
f0174b5a9c Find matching settings for each CPUs FID, VID, and P-state registers and initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).

The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:27:53 +00:00
8127dc41d1 Update the FAM10 microcode to current versions.
In addition, AP microcode is now updated in early initialization to support errata settings that require it.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:20:07 +00:00
c74e362723 Missed this file in the previous check-in, r3248.
Add early MSR and PCI register initialization. 
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 23:09:34 +00:00
da4ce6b451 Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
 
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 22:11:31 +00:00
0ab8cddf02 Add support for a 'bootlog' module to coreinfo.
It displays the coreboot printk buffer in RAM and let's you scroll through it.
This feature is only available for coreboot v3 though, as v2 doesn't have a
printk-buffer feature, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 20:19:53 +00:00
16acf8b393 Show index numbers in the NVRAM dump, similar to the PCI config space dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-22 16:56:21 +00:00
5f4410b7dd libpayload: Fix keyboard buglet
This solves the multiple keystroke issue that popped up recently.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-21 22:33:58 +00:00
7bc63fd2cb This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the
generic SMSC support, and corrects a small typo.

With this patch, coreboot v2 on a mainboard with SCH3112 has been
demonstrated to correctly use the serial port.  No other chip
functions were tested.

Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-19 13:32:19 +00:00
5971121009 Replace buildtarget's check for --build-id with something
a bit less awkward (pun intended).

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-18 20:48:22 +00:00
68aab269fa Alter buildtarget to invoke the cross-compiler when
checking for --build-id, if the user has specified one by setting CC
in the environment; there's no point in checking the native linker in
this case.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-18 20:47:11 +00:00
8d0a12ac7c Change default payload location for easier buildrom support (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-16 00:46:08 +00:00
0b53ec3da9 Move curses/speaker.c to drivers/ as it's not curses-specific (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-15 17:24:08 +00:00
53693031c5 Add the patch for building tint as payload, as well as a small README,
into the payloads/external/tint directory.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-15 16:47:20 +00:00
50eff2147d Correct upper boundary for isxdigit.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-12 20:09:46 +00:00
be504d1d8d Drop unneeded #includes, add EXIT_SUCCESS/EXIT_FAILURE (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 20:16:24 +00:00
72199bc49a Rewrite and filling of libc/ctype.c (thus adjusting copyright line).
Use a simple one-liner for each of the functions. You can surely optimize
the code some more, but I chose not to do that in order to keep it readable.
When compiling with -Os the size differences are minimal.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 19:43:55 +00:00
b103345a14 Convert BIN2HEX/HEX2BIN to functions and add the abs() family
of functions while we're at it.

hex2bin() now also supports upper-case input characters.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 18:38:04 +00:00
fad8c2bd7c Various small consistency fixes (trivial):
- Use _FOO_H include guard format everywhere.

 - Add missing speaker.c prototypes to libpayload.h.

 - Consistently use short form u8/u16/u32 instead of uint8_t et. al.

 - kcofig: Use 'depends on' instead of 'depends', which seems deprecated.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 18:01:50 +00:00
54315533cc libpayload: Add a Geode video driver
Add a Geode video driver in lieu of VGA on Geode LX devices

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 15:48:21 +00:00
e3aeb93a52 Bring Fam10 memory controller init up to date with the latest AMD BKDG
recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
    The DRAM Hole Address Register is set via devx in each node, but the Node
    number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
    set in Node 0. The memmap is setup on node0 and copied to the other nodes
    later. so dev, not devx. The bug was the hole was always being set on the
    first node.

Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-11 03:20:28 +00:00
234e87f137 libpayload: Support functions for Geode
The Geode video driver will require a number of support functions,
including udelay(), PCI bus walking and MSRs.  This adds those functions
in preparation for the actual code.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-10 22:50:44 +00:00
30939bdffd libpayload: Add video console framework
Add a framework for multiple video console drivers.  This is to prepare
for the Geode driver.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-10 22:49:02 +00:00
bac89d088c libpayload: Avoid .svn files in the header install
Slight tweak to to the install target to avoid copying .svn
files.  Trivial self ack.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-10 17:57:42 +00:00
1cb92bc77f coreinfo: Make coreinfo use the gcc-wrappers from libpayload
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-10 00:05:41 +00:00
804f4df5bd Make the sample Makefile a bit more generic, so it can be adapted more
easily for other payloads. Also, add a 'distclean' target (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-09 23:48:48 +00:00
c3e728fbdf libpayload: Implement gcc wrappers for libpayload
libpayload uses a ton of flags and other scary gcc and ld options.  These
wrappers hide most of that from the user, so that using libpayload is as
easy as lpgcc -o hello hello.c

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-09 23:05:59 +00:00
c5a78ac56a Add missing prototypes for libc/rand.c functions (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-08 23:38:15 +00:00
ea72559d5d Small curses fixes/additions for libpayload (trivial).
- Properly set LINES and COLS, needed for a real curses application.

 - Implement notimeout() and wtimeout(), which are trivial.

 - Implement a dummy flushinp() for now as it's needed by a curses
   application I'm porting, will be replaced by something useful later.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-08 23:30:22 +00:00
672d0ae156 libpayload: Add a timeout function for getchar and getch
Implement a timeout option for getchar() to return after so many
milliseconds.  Also implement the same thing for curses using
the halfdelay() function.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-08 23:21:33 +00:00
4eb5089821 Add rand/rand_r/srand functions for generating pseudo-random bytes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 23:33:50 +00:00
c6092c0f34 ST M50FW016 and ST M50FW040 support the 82802ab command set, not jedec.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 22:33:33 +00:00
78f59f8352 Re-add files I deleted by mistake in r3219. They are meant for a different
patch.

Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Marc Jones (marc.jones@amd.com)



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 18:11:03 +00:00
df22f780f1 Don't check exclusive IRQ fieldin the PIR table.
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs. 

Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 17:49:57 +00:00
0dc5697220 This patch halts the tco timer early in the boot process on all ICH series southbridges.
It also keeps the boot processes from rebooting through out the coreboot process.

Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-06 04:26:19 +00:00
3860404b65 libpayload: remove unneeded stack stuff
Following on the previous code to streamline the libpayload init code,
this removes the now unneeded stack structures.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-05 01:07:27 +00:00
6c44dfb649 Fix the case where the user selects no modules in Kconfig at all.
Until now, the build would break, and even if it didn't the ELF would
triple-fault in QEMU.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-04 16:49:09 +00:00
4afb7fb761 Add a workaround for a bug in some binutils version which strictly
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669

The same change was committed in r3044 to the AMD CAR code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-04 15:02:45 +00:00
a69772157e Document a rough estimate of how much space in the ELF file each of the
coreinfo features / modules will consume (trivial).

The measurements were done with libpayload r3213 (but compiled with -Os),
and coreinfo r3211 (also compiled with -Os).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-04 13:28:10 +00:00
1bee6f9b9c Add BIN2HEX and HEX2BIN macros (trivial).
They're generally useful for lots of stuff, but especially for converting
to/from the compact 160 bit (20 byte) representation of SHA-1 hashes to
the "hex" representation (same as 'sha1sum' output), which is 40 bytes long.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-04 13:16:33 +00:00
3995593b68 Add a SHA-1 implementation to libpayload.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-03 23:01:23 +00:00
c758227406 Doing another 'make' after a 'make clean' was broken until now. Fix it
by not deleting build/config.h during 'make clean' (only in 'make distclean').

Also, change the default behaviour of 'make' from asking the user to
run 'make config' (or similar) to actually _run_ 'make config' without
asking questions. It's always possible to explicitly invoke
'make menuconfig' or 'make xconfig' and so on, of course.

Finally, make _all_ targets (allyesconfig, randconfig, and so on)
generate a build/config.h file, as we always #include it.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-03 22:20:35 +00:00
0a89625f55 Add missing snprintf() to libc/printf.c (trivial).
This is also taken from the HelenOS project.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-02 12:35:45 +00:00
2b85b6311f Setting an integrated southbridge device (like SATA or USB2.0) to
"off" in Config.lb should cause the PCI device not to respond to
configuration requests.

Replace the existing code that I naively copied from esb6300 with
something that actually works on the 3100.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01 17:14:57 +00:00
23cd49ab80 Remove i82801DB files that I meant to delete in r3206.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01 17:05:22 +00:00
06ae639596 Tiny style fix for consistency (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01 02:48:12 +00:00
868de9838c Removal of i82801DB (ICH4)
There are no boards that use the i82801DB (ICH4). The code does NOT work.

Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01 02:42:52 +00:00
c4e052cd50 The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01 02:36:59 +00:00
2c6b33ce3e Libpayload fixes to prevent triple-faults when running in QEMU.
Let the linker figure out the correct address and just CALL the
start_main entry point.

Signed-off-by: Klaus Schnass <dev@stuffit.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 21:02:29 +00:00
ab5b3e0d98 Add support for an "NVRAM Dump" screen in coreinfo (optional), as well as for
displaying the current date/time in the lower-right corner (optional).

Also, only build/use coreinfo modules which were selected in kconfig. This
makes coreinfo truly modular, and you can save quite a bit of ROM space
by disabling unwanted parts of coreinfo.

Finally, simplify the Makefile a bit by getting rid of MODULES (and only
using OBJECTS).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 20:30:18 +00:00
30d789bcbd Fix the NVRAM access functions to work correctly for the
upper 128 bytes of NVRAM (if enabled).

For most chipsets this means using I/O ports 0x72/0x73, but at least
on some VIA chipsets (I tested the VIA VT8237R on actual hardware)
these ports won't work and you have to use 0x74/0x75. Thus, make this
a Kconfig option for now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 20:21:49 +00:00
2d758b8bf6 Whitespace fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 15:21:24 +00:00
b642e6d40a Rename drivers/cmos.c to drivers/nvram.c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 15:18:56 +00:00
c16d24e73a Due to popular demand, rename "CMOS" to "NVRAM" (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-31 15:17:39 +00:00
71f846c137 Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.

The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.

It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-30 11:31:15 +00:00
1e185e8561 Add support for the TeleVideo TC7020.
Signed-off-by: Kenji Noguchi <tokyo246@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 17:24:58 +00:00
9c2255c66c Now coreboot performs IRQ routing for some boards.
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*

This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.

Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.

I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.

The pirq.patch for IRQ routing logically consist from of two parts:

First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.

Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.

IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.

Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 16:59:27 +00:00
0e122af465 [libpayload] Work around sign-extending issue
Somewhere characters are getting sign-extended, meaning that the
attributes of the drawing chars (>= 128) are wrong. Cast the value
before sending it to VGA.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 16:13:22 +00:00
42cccdf03b Make a few array entries only as big as they absolutely need to be (trivial).
This decreases the size of the superiotool binary from ca. 1.1 MB to 600 KB.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 01:35:21 +00:00
da0efc4ca5 Fix for irq routing issues.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-28 03:35:11 +00:00
8cc38d2f13 Add initial support for some basic CMOS read/write functions and the
bcd2dec()/dec2bcd() functions we'll need for (among other things)
converting some date/time parameters in CMOS.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-27 23:26:40 +00:00
a0c0093a09 Various tiny fixes (trivial):
- Show PCI IDs as 4-digit numbers always.

 - Cosmetic changes to make UI look more consistent.

 - Drop MODULE_COUNT #define and use ARRAY_SIZE() where needed.

 - Small fix to improve build system (create build/ when not there).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-27 20:46:49 +00:00
408c4e1784 Drop -Os in libpayload for now, it causes run-time problems for some
strange reason (broken curses/VGA display, maybe others).

It'll be re-enabled when we fixed that.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-27 19:11:44 +00:00
c88b537461 Make the getpir output compile (Closes #70).
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-25 19:43:01 +00:00
2216d1b46a Add a recent kconfig version to coreinfo, in order to make the
supported features configurable later (currently unused). Store all
build files and results (coreinfo.elf) in build/ now.

I'm self-acking this as (though non-"trivial") it doesn't affect coreinfo
in its functionality, this is more or less a "cosmetic" change to the
build interface ("make" -> "make menuconfig && make").

This is a kconfig checkout from the Linux kernel (where kconfig is being
actively maintained) from 03/2008. The hash identifying the last commit
to kconfig is 587c90616a5b44e6ccfac38e64d4fecee51d588c.

The amount of changes to kconfig itself has been kept as small as possible
to keep the diff small and to ease updating/porting to newer kconfig versions.
The following changes were performed on the upstream Linux kconfig:

 - s/kernel/coreinfo/, and s/Linux/coreinfo/ in various strings.

 - Consistently use the env. variable KERNELVERSION in all kconfig
   interfaces -- e.g. config/menuconfig/gconfig/xconfig -- as version number.

 - Hardcode our paths/filenames in some places (could be improved upstream).

 - Always write .config and build/config.h, no matter which kconfig
   interface is used (config/menuconfig/gconfig/xconfig). We want to
   include build/config.h in our code.

 - Adapt the kconfig Makefile for our purposes (build/ directory, rules, etc).

In addition, a few items in the coreinfo Makefile are needed for this to work.

This kconfig setup is successfully tested with all targets from 'make help':

  config          - Update current config utilising a line-oriented program
  menuconfig      - Update current config utilising a menu based program
  xconfig         - Update current config utilising a QT based front-end
  gconfig         - Update current config utilising a GTK based front-end
  oldconfig       - Update current config utilising a provided .config as base
  silentoldconfig - Same as oldconfig, but quietly
  randconfig      - New config with random answer to all options
  defconfig       - New config with default answer to all options
  allmodconfig    - New config selecting modules when possible
  allyesconfig    - New config where all options are accepted with yes
  allnoconfig     - New config where all options are answered with no

For 'make defconfig' to work you have to do (which we don't need in coreinfo):

  $ mkdir configs; touch configs/defconfig

You can also use 'make foo_defconfig' in which case kconfig will use a
file called 'configs/foo_defconfig' as basis.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-24 15:47:49 +00:00
0bfb5c4fb2 Make functions static (where possible) to reduce code size (trivial).
Also, disable header() for now, as it's not being used.

Here are some stats on size differences:

 - ls

23820 coreinfo.old.elf
23564 coreinfo.new.elf

 - size *elf

   text    data     bss     dec     hex filename
  15199    2468  181904  199571   30b93 coreinfo.old.elf
  14934    2468  181912  199314   30a92 coreinfo.new.elf

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-23 15:34:04 +00:00
b0e3f39a39 Make cursor positioning work by using both halves of the
VGA cursor position register.
   
Have vga_scroll_up() and vga_clear_line() present row/column
arguments to the VIDEO() macro in the right order.
       
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

-This line, and those below, will be ignored--

M    libpayload/drivers/vga.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-22 15:27:26 +00:00
661e380a75 Cosmetics, fix typos (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-21 18:37:23 +00:00
29014056e7 Quickfix for libpayload's strcpy() to properly NUL-terminate strings (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-21 15:47:38 +00:00
316e07fb04 Following patch adds K8M890 support. It initializes the AGP and graphics UMA.
The V-link setup and HT bridge is redone, because VT8237A has it in another
device. So far following combination of chipsets should now work:

K8T890CE + VT8237R
K8M890(CE) + VT8237R

VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and
notes about K8M890 support were added.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 21:19:50 +00:00
14a3feb068 Fix code to allow usage of -Wall in libpayload and the sample (trivial).
This even fixes two bugs:

 - get_cpu_speed() didn't return a value.

 - The line
     win->_color - PAIR_NUMBER(0);
   should actually be
     win->_color = PAIR_NUMBER(0);

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 20:46:44 +00:00
35845a2acb Smaller fixes to allow using -Wall (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 20:05:22 +00:00
6a441bfb46 Cosmetics, coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 19:54:59 +00:00
5f4c8abb65 Change kconfig references from 'buildrom' to 'libpayload'.
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:58:08 +00:00
0c1cea29e7 Allow 'make menuconfig' to function within libpayload.
Removes reference to BusyBox.

Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:56:05 +00:00
dc69e05d90 Make the list of functions in libpayload.h more complete (trivial).
We need to think about the exact API we want to expose later, though.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:53:30 +00:00
5aa66da9a1 Add -Os to the CFLAGS for size improvements.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:15:16 +00:00
2c7bb9e84f libpayload: Add -Os to the CFLAGS
Adding -Os to the CFLAGS gains us about 25% smaller code (give or take).
Unfortunately, it exposes a strange issue where strcpy() suddenly goes
missing - we think that strcpy() is being provided by libgcc, and that
for some reason, -Os changes the beahavior.  Oh, well - add a quick
strcpy() function and we're good.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:13:28 +00:00
3a406feb17 Cosmetic changes and coding style fixes by running 'indent', with some
manual fixups afterwards (trivial).

No functionality changes, compile-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 01:11:28 +00:00
7249f79792 corinfo: Inital release of the coreinfo code
This is the intial release of the coreinfo payload code.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:11:05 +00:00
c52761be0a libpayload: BSD solutions contributed by Uwe
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20 00:02:07 +00:00
f3029a8fc9 libpayload: External code
This is external and properly licensed code that I pulled into the tree.
          
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19 23:59:13 +00:00
f6145c3c15 libpayload: The initial chunk of code writen by AMD
This is the initial chunk of code written by me and copyrighted
by AMD.  Includes everything but a few files that we pulled from
outside sources.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19 23:56:58 +00:00
c221349746 Following patch will setup KT890 HT automatically. It will find the
max width of the link and also it will take the frequency of K8 HT
already done coreboot (and checks if t can run on it).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19 20:24:33 +00:00
cfcc9ca590 * split model_centaur into model_c3 and model_c7
* simplify and improve cpuid table
* add speedstep support for VIA C7 based CPUs
* also included as many of Uwe's suggestions as possible

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18 23:10:24 +00:00
e98edfa386 Add ICH9 detection to flashrom. Straight from the datasheet, untested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18 00:54:10 +00:00
470d3650ad oops. forgot to add the file.
Support for the Winbond W39V080FA series of chips.
Support for flashing on the Kontron 986LCD-M board.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18 00:36:18 +00:00
012ed48bf2 Support for the Winbond W39V080FA series of chips.
Support for flashing on the Kontron 986LCD-M board.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 22:59:40 +00:00
2ce4e4caa9 The ATI vga rom is only 36K on the Tyan s2891, not 48K.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 17:06:06 +00:00
969a9f69e8 Various smaller fixes in superiotool:
- Also dump the extra registers (e.g. EC regs) in --list-supported.

 - Small fix in the code to allow for building with -pedantic (yes,
   the fix is a bit silly, but it's simple and allows us to use the
   -pedantic flag to keep the code even cleaner and nicer).

 - Install the binary in /usr/sbin, as it's meant to be run as root.

 - Small typo in README.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 13:43:48 +00:00
a2ccf9fe4e Add support for the MSI MS-6119 mainboard.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 13:37:34 +00:00
fa510c7878 Clarify LZMA code license.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 01:37:27 +00:00
4f83d7ed96 oops. sorry, wrong checkin. This patch backs out r3155 and instead contains the
code it should have contained.

This patch updates the PCI IDs for Intel 3100 devices.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:43:04 +00:00
354e2d3dc1 This patch implements support for the Intel 3100 Development Kit
mainboard, aka "Mt. Arvon".   

Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:39:24 +00:00
a9faea8977 This patch implements support for the Intel 3100 integrated
northbridge and RAM controller. 

Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:36:00 +00:00
aaea11b749 Here is an updated patch addressing most of Uwe's and Peter's
comments. Ripping out the ehci/uhci_init() code doesn't seem to have                                                                                                                         
done any harm, and I got rid of a bunch of unused junk in                                                                                                                                    
i3100_smbus.h                                                                                                                                                                                
                                                                                                                                                                                             
I left the *_set_subsystem() arguments unsigned, as that's how the                                                                                                                           
function is declared in include/device/pci.h.                                                                                                                                                
                                                                                                                                                                                             
Signed-off-by: Ed Swierk <eswierk@arastra.com>   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:34:10 +00:00
62eee3ff4f This patch implements support for the Intel 3100 integrated SuperIO and UART.
Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:31:04 +00:00
791265a367 This patch updates the PCI IDs for Intel 3100 devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>                                                                                                                                               
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>                                                                                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 23:27:50 +00:00
a4b901e3ef give the fam10 code a little more space until we have the time to debug this
properly. Everybody knows this by now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 22:20:53 +00:00
dd6877a46d check whether SST FWH chip was successfully erased on flashchip -E, too
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 19:44:13 +00:00
568667da20 Sort list of flash chips alphabetically, add comment (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 02:06:25 +00:00
582ce71cc5 remove nasty warning that happened due to our vendor detection
mechanism.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 23:41:19 +00:00
9dcfc00dc6 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 16:30:39 +00:00
e989be26e6 BIOS_SPEW is log level 9. There is nothing beyound that line.
(Thus the patch is trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 12:26:12 +00:00
5671787b9e Following patch extends the ROM decoding to last 1MB, allowing to use larger
flashes such as SST49LF080A: 1024K x8 (8 Mbit)

Tested on my system, the flash is found and if I use coreboot in second half it
works too.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 00:26:50 +00:00
dd52e17448 Following patch fixes the retrain/reset sequence which caused problem with some
nVidia cards. The enable link should be enough, retrain is done there.

Tested on my system.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 00:19:34 +00:00
1ce63770a1 Re-add code erroneously removed in r3140.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:55:58 +00:00
937ae9d9fe Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:32:03 +00:00
ae8a08df3b Prepare for ICH7/ICH8 SPI support by adding some debugging for all
ICH* chipsets. Functionality (except printing) should be unchanged.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.

Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 17:20:59 +00:00
0b202d0a6e Add a Config-abuild.lb for the rca/rm4100 (trivial)
The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 06:12:24 +00:00
c843636c88 Fix broken flashrom build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 01:24:39 +00:00
4b0a41b5ca Fix up one forgotten revert in r3140.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:33:42 +00:00
8729de48fa Revert the delete of 82802ab.c in r3137.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:02:25 +00:00
912ee57a59 Also print the chip vendor name in --list-supported output (trivial).
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:52:51 +00:00
ee2bb3a21e Also print the required -m option in --list-supported output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:41:07 +00:00
b7b22e3c57 Drop 82802ab.c as it is identical to sharplhf00l04.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 12:43:31 +00:00
3182122c3b Update AMD CPU list based on Revision Guide for AMD NPT Family 0Fh Processors,
Publication #33610, Revision: 3.30, February 2008.

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 02:21:41 +00:00
b681570e7b Formatting fixes, no content changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 23:18:04 +00:00
2ad17532a4 Drop the useless rom.layout file. It's just an example, likely never
been used in the last few years, and the contents are available in
the README already anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 12:28:40 +00:00
098913dadf Add --list-supported option to flashrom which lists the supported
ROM chips, chipsets, and mainboards (Closes #90).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 11:54:51 +00:00
2aa1436777 Add GPIO dumping utility for Intel ICH series southbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 22:26:18 +00:00
0719b8e460 The ATI vga rom is only 36K on the Tyan s2881.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 19:53:30 +00:00
7aad44c496 This patch changes the Config.lb files and adds a Config-lab.lb file for the
tyan s2881 board, in preparation of supporting it in buildrom. Corresponding
changes for the other buildrom-supported boards were committed in r3092.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 18:48:52 +00:00
6a1dc86005 Initial support for the Intel 82830 northbridge and RCA RM4100 board.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-09 13:24:46 +00:00
c4f5365688 Various cosmetic and coding style fixes for ASUS A8V-E SE (trivial).
No functional changes, only cosmetics. This is compile-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-08 19:14:42 +00:00
917158f803 Drop some duplicate documentation from the README. The manpage and
'superiotool --help' already provide the same information (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 17:21:04 +00:00
9ae23628fb Add missing license header to layout.c. The file was written by
Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 16:29:54 +00:00
cbb5ba8633 Rename lxbios to nvramtool, step 3 (rename directory).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:09:01 +00:00
66d83cfa84 Rename lxbios to nvramtool, step 2 (rename files).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:07:46 +00:00
6e565947a5 Rename lxbios to nvramtool.
This is step 1 in a three-step commit:

 1. Apply patch, commit.

 2. Rename some files:
    $ svn mv lxbios.c nvramtool.c
    $ svn mv lxbios.1 nvramtool.c
    $ svn mv lxbios.spec nvramtool.spec
    $ svn ci

 3. Rename lxbios directory:
    $ svn mv lxbios/ nvramtool/
    $ svn ci

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:06:32 +00:00
eec5ff4ccb Small coding style fixes and documentation updates (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 18:49:39 +00:00
a04027efca Create a genacpi directory below util/ which will hold all acpi related
code/data generation utilities.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 15:33:03 +00:00
9b6b63eac0 In pci_device.c, the class for VGA was not tested properly, leading to
no VGA output from coreboot, even after the boot-rom was executed
properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with
CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the
class field of struct device is '3 bytes: (base,sub,prog-if)'.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Torsten Duwe <duwe@lst.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-28 23:10:38 +00:00
17632a205e Temporarily disable the fan control patch from this morning; it turns out to
stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than
desirable. I did not notice before because my board ran fine for about 15
minutes before the CPU overheated.

Thankfully the board has a good failsafe mode - it just switches off when the
CPU gets too hot, without permanent damage.

I'm debugging this and plan to commit a proper fix later in the week.

This is not really trivial, but the tree is dangerous in the current state so
I'm self-acking.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-26 04:36:52 +00:00
0be73bbf30 This patch adds support to dump other registers than the primary
pnp-style configuration registers, using the new option -e/--extra-dump.
This patch only adds dumping of the Environmental Controller
configuration registers for the IT8716f chip.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>

I (Carl-Daniel) checked the data sheets of the whole IT87[012] series 
and although the environment controller is sometimes called fan 
controller, the location of the register is the same for all models.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 22:32:41 +00:00
56cf01f29d This patch adds automatic fan control for the CPU fan on the m57sli
board.

This is done via the ec_init routine in a source file in the
mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
added to notify superio.c to get the ec_init externally.

I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
It works.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 19:36:20 +00:00
8684520b94 This trivial patch removes an unused local variable, thus getting rid of
a compiler warning.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 10:15:10 +00:00
0be722c508 The proprietary VGA rom is only 36K on Tyan s2882, not 48K.
Tested on real hardware.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21 21:00:19 +00:00
bd3f93e330 Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM is
working for now, and more work is needed for it to be fully dynamic. However,
just about any 128MB-512MB DIMM should work.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-21 00:56:14 +00:00
f327d9f954 Route device IRQ through PCI bridge instead in mptable.
Don't enable pin0 for ioapic of io-4.

1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
   for device under them in mptable.

Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20 17:41:38 +00:00
8eff1e3d04 Initial support for MSI MS-7135 (K8N Neo3) mainboard.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20 15:59:30 +00:00
787e4c9fd5 flashrom: Add board_enable for Artec Group DBE61 and DBE62
Also add a comment about NULL subsystem IDs leaving the board entry out
of auto-detection logic.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20 11:11:18 +00:00
b05d4bb77e I'm attaching the patch which should fix both problems. Fix the
undefined u8 type and the bitpos selection in currently unused 
pnp_read_enable function.
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-19 20:30:25 +00:00
bb6f88d1d4 Should be part of changeset 3106.
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:43:09 +00:00
bcd28f22f4 Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
device) and sets the chipset voltage from 1.6V to 1.5V.
 
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:40:02 +00:00
8dcab78164 This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:37:49 +00:00
0b8af012b6 Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from a sio_setup. As side effect I can now
have GAME and MIDI portsenabled.

It has been tested with my board. It produces same results.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:35:27 +00:00
623df6763c Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like
mine W83627EHF.

This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but
maps to original LDN and bit position in register 0x30.

VirtualLDN = origLDN[7:0] | bitpos[10:8]

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:32:46 +00:00
b34eea348c Importing mkelfimage from
ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-15 18:16:06 +00:00
46fc14dcc8 With this small change it is possible to build flashrom again when
specifying custom CFLAGS/LDFLAGS from the make command line like:

  make CFLAGS="..." LDFLAGS="..."

I need to do this when building flashrom in a cross compiler environment
like buildroot for a foreign target.

Signed-off-by: Clark Rawlins <clark@bit63.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-14 23:22:20 +00:00
9792a034e4 flashrom: further cleanups to enable_flash_cs5536
- Remove the "enable write to flash" message, as the caller appears to
   already report that.

 - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
   we get an error there already.

 - Rename a perror string from "read" to "read msr", as we use the latter
   already in this function for another read.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-11 14:32:45 +00:00
5eb25bf48f add $(CROSS_COMPILE) to ar calls.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-09 13:06:45 +00:00
2f7b7fb82a Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-09 02:03:06 +00:00
2995cc69f7 Improve error handling and make RCONF_DEFAULT_MSR address be a constant.
Also, move a big code comment to the top of enable_flash_cs5536().

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08 10:10:57 +00:00
99062ae5ad This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select).
We need to write enable it in the NORF_CTL MSR register for flashrom to
be able to write to it, including JEDEC probe commands.

This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08 09:59:58 +00:00
d2be99c62d Change payload location in 'normal' - this was missed in r3992 and thus breaks buildrom.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07 22:53:53 +00:00
9b0627a3b2 This is a trivial patch. I missed one of the ROM names when I converted them to coreboot.rom
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07 22:42:22 +00:00
2370fd81b4 Make the check for -fno-stack-protector fail silently, if it fails.
This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07 21:50:22 +00:00
b8c2aa2ce8 Change references to qemu in Coreboot-v2 calls to qemu-x86.
The patch was followed by these svn commands:

svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
svn mv --force src/mainboard/emulation/qemu-i386/
src/mainboard/emulation/qemu-x86
svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-07 20:37:37 +00:00
f2b380ad85 This patch changes the Config.lb files and adds Config-lab.lb files for
architectures supported by buildrom.

Myles

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06 22:33:50 +00:00
c23b3a5732 Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors like
Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.

Add support for the PMC Pm25LV family of SPI flash chips.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard  <chris@stockwith.co.uk>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06 22:07:58 +00:00
a7c92a6dc4 This patch changes all rom names that aren't coreboot.rom in Config.lb files.
I think that since the directory specifies the architecture and the
board, it is redundant information to name it something else, and it
makes it more difficult to automate the build process (buildrom).

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-05 21:53:15 +00:00
cb5c9fb9e3 Factor out print_conf() from Geode LX mainboard directories. The
following mainboard files had identical Geode LX specific print_conf()
implementations:
mainboard/amd/db800/mainboard.c
mainboard/amd/norwich/mainboard.c
mainboard/digitallogic/msm800sev/mainboard.c
mainboard/pcengines/alix1c/mainboard.c
Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.

Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-05 09:21:46 +00:00
10aca3cae2 This patch fixes the decoding of the IO address range 0x0820->0x0827 into the
LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
 Changes :
  1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
  2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
  3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..

Signed-off-by: Florentin Demetrescu <echelon@free.fr>

I (Ward) have verified your patch on a rev2 of this board (it works!) as well
as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
side effects that I noticed, so I think this patch should go in.

Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 23:14:40 +00:00
d8a74c95d1 This patch reverses an erroneous change that sneaked in during r2972, and broke
flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-01 23:07:04 +00:00
f3dd1b7e57 v2: Fix Serengeti-Cheetah flags too
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 22:55:47 +00:00
71a82254ef [V2]: Add CFLAGS to targets to suck in any passed in flags
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 19:22:29 +00:00
ca31bc3cd5 Fix mptable util so the output will compile
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 00:04:23 +00:00
d27aa6eff5 Add support for the Abit BE6-II V2.0 board.
Tested on actual hardware by Sergei Antonov <saproj@gmail.com>. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Sergei Antonov <saproj@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 17:25:49 +00:00
e2bbcb10d1 Make the vendor name optional in the -m flashrom parameter when there's only
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 16:21:21 +00:00
3bbf2ff789 Add a new record type "console" for lbtable, and insert one record
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 14:12:54 +00:00
2d94dead69 Forgot to add Spansion S25FL016A to README, trivial.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 07:17:14 +00:00
25a37449c5 This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS were not being
included on the CC line for cache_as_ram_auto.c

Tested on ubuntu, where formerly it failed.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26 16:57:03 +00:00
2db9464299 Correctly disable the ROM area Write Protect bit in the Geode LX.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26 07:35:47 +00:00
873312d699 bsh/ksh-clone and make(1)-syntax don't go well together
(unlike 5 lines later where make syntax is emitted into a file)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 19:31:26 +00:00
8c2a0c1445 This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 18:28:18 +00:00
1a6177b720 Various small fixes and updates for lxbios (trivial).
- Update website URL to http://coreboot.org/Lxbios.

 - Use svn:keywords property to actually expand the $Id$ entries.

 - Update COPYING to the latest version from
   http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 15:08:37 +00:00
f2a2a5ee2e Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 01:52:45 +00:00
14a3af111d Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.

Signed-off-by: Marc Karasek <marc.karasek@sun.com> 
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 16:09:36 +00:00
bb9c1aa54e Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 16:03:19 +00:00
a6941beb43 Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.

This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.

"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 15:19:01 +00:00
468413a337 Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 14:37:31 +00:00
21efd9ffe2 Omitting the wait for SPI ready when there is no data to be read, e.g.
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 23:55:08 +00:00
679c62c083 This patch adds version information to flashrom. Because 'v' and 'V'
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 15:24:22 +00:00
8ce4a19b20 last try i hope. Building with a payload changes the result of the rom
image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-20 01:59:43 +00:00
c2bcc893ea give it 2k more space for abuild. let's look into this anyways, but get rid of
the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-20 00:24:23 +00:00
593f5aab03 Add Bingxun Shi <bingxunshi@gmail.com> to the list of contributors (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:43:48 +00:00
fb348035a3 Small superiotool fix to detect more Winbond W83627EHF chips. The
patch is tested on actual hardware.

As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).

So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:40:17 +00:00
34a576fb98 This patch is for winbond w83627DHG superio support in superiotool.
I have test that on my board, it works ;)

Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:32:07 +00:00
2f0f561f89 Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
Super I/O performing LPC-to-SPI flash translation.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:04:46 +00:00
cd474afd08 Document the --list-supported option. Various small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 18:04:28 +00:00
d84d9ba445 Minor documentation improvements/fixes in the README and manpage (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 17:48:51 +00:00
7223ab7c4a rename linuxbios_* files in utils repository.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:17:44 +00:00
ca374d455c rename linuxbios_* files, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:16:45 +00:00
997afe6ca5 util/ renames
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:34:24 +00:00
f527e70333 rename linuxbios -> coreboot
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:49 +00:00
8df401db3b for some reasons the externals did not get committed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:10 +00:00
f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:08:58 +00:00
7e61e45402 Please bear with me - another rename checkin. This qualifies as trivial, no
code is changed.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 10:35:56 +00:00
c72fcde273 rename linuxbios to coreboot
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-16 16:25:13 +00:00
552cfb7b74 Add new --list-supported switch for printing the list of Super I/Os
supported by superiotool (closes #91).

Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-15 22:30:55 +00:00
6211ae13c3 Fix the documentation of GPIO setup, tell W83627EHF to use external
suspend clock (undocumented in datasheet, documented in 'W83627HG-AW').
Introduce sio_init function for all this.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-12 22:29:17 +00:00
aeea7c1438 Via C3 datasheets don't make any mention of microcode updates, and the
C7 bios programmer's guide explicitly states they're not necessary, and
leaves it at that. Even if they are possible and exist, we don't have
any info on it, nor any updates, so drop these unneeded references.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-12 21:44:57 +00:00
c02d8d88dc Fix these to use a more standard relative path for payload.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 22:37:27 +00:00
23b00b8909 Add the ability to extend CFLAGS as needed for several new distros
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 18:23:47 +00:00
6322baa50c This patch removes '\n' from the help output since this looks a bit strange.
After the patch [...] The line length is still below 80 characters.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 00:32:07 +00:00
ed8dc58efa Add a workaround for a bug in some binutils version which strictly
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 17:59:25 +00:00
1923fc41be This patch introduces 4k CAR size granularity for the AMD x86 CAR code.
For the old supported CAR sizes, the newly generated code is
equivalent, so it should be a no-brainer.

Benefits:
* a nice code size reduction
* less #ifdef clutter for Family 10h
* paranoid checks for CAR size
* clear abstractions

This has been tested by Marc Jones and Jordan Crouse.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 17:48:25 +00:00
2e152be16e Enable MX25L8005 support in flashrom. The #defines were already there.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 13:27:22 +00:00
247a423dee Use macros to improve readability of the device-to-pin IRQ assignments
in GA-2761GXDK mptables.c.
Thanks to Torsten Duwe for initial code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: 蔡明耀 (Morgan Tsai) <my_tsai@sis.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-09 11:37:58 +00:00
188288a020 Fix compilation of Tyan S2735 which was broken by accident in r3038.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08 19:14:16 +00:00
f2ecb74023 Remove some DOS line endings accidentially introduced in r3014.
No code lines affected, so svn blame will not be messed up.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08 17:28:35 +00:00
4d1aa0a9eb This patch is an attempt at introducing 4k CAR size granularity for the
generic x86 CAR code. For the old supported CAR sizes, the newly
generated code is equivalent, so it should be a no-brainer.

Add a copyright header to the code, the header is derived from the one
found in the same piece of code in v3.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> 
Acked-by: Marc Jones <marc.jones@amd.com> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08 17:06:38 +00:00
eaca2c32a3 Ubuntu's gcc doesn't write "install:" in german locales.
Normalize used locale to "C" before parsing output.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-08 10:28:06 +00:00
c7323f1b0c Add support for the SST25VF040B 4 Mbit SPI flash chip.
Straight from the data sheet, not tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-07 13:48:51 +00:00
f4c57a96b4 Improve readability and remove redundancy by wrapping
similar smp_write_intsrc calls in preprocessor macros.
Also add some comments about the actual devices the INTs
belong to.

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-07 11:13:16 +00:00
1f2f800036 Since a VGA console and the need to run any option ROMs are
rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.

This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.

Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-06 01:10:54 +00:00
11e90e06d3 Add board enable for the gigabyte ga_2761gxdk board
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-04 17:22:44 +00:00
b5f9bd6ac9 Print at least the vendor for SPI flash chips if the exact chip ID is
unknown.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-04 16:22:09 +00:00
717f66d1eb Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have
exactly the same ID. Improve model number printing.

Add EN29F002(A)(N)B support while I'm at it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 14:05:08 +00:00
85acc09786 Add continuation ID support to jedec.c
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.

(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)

Add support for EON EN29F002AT.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 01:49:00 +00:00
1704179acd This fixes a few vendor IDs to conform with JEDEC publication 106W
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.

This patch should have no effect on code generation.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 01:18:26 +00:00
1229fe4c9b The following mainboards had a file named microcode_updates.c in their
mainboard directories, but the code was not referenced anywhere.
intel/jarrell
dell/s1850
supermicro/x6dhr_ig2
supermicro/x6dhr_ig
supermicro/x6dhe_g2
supermicro/x6dhe_g
Besides that, the contents of these files were either duplicates of
src/cpu/intel/model_f3x/microcode_M1DF340E.h or
src/cpu/intel/model_f3x/microcode_M1DF3413.h.

svn remove the following files:
src/mainboard/supermicro/x6dhe_g/microcode_updates.c
src/mainboard/supermicro/x6dhe_g2/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig/microcode_updates.c
src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c
src/mainboard/dell/s1850/microcode_updates.c
src/mainboard/intel/jarrell/microcode_updates.c

Abuild tested, as expected no failures.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-30 11:59:10 +00:00
19cf6a3890 All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.

A sector/block size field in struct flashchip would be nice, though.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 11:05:59 +00:00
29df7a9662 Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 10:15:58 +00:00
d0ad60a795 Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 10:14:38 +00:00
9cb314b939 Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-28 00:23:29 +00:00
679e14e348 Add an interrupt entry for the onboard firewire controller,
Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
(verified on an v1.0 board).

Signed-off-by:  Torsten Duwe <duwe@lst.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-21 17:21:03 +00:00
dc5bccffde Change default payload to /tmp/filo.elf (trivial).
It's easier to tell users "copy your payload to /tmp/filo.elf" than have
them guess paths or modify Config.lb files etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-21 16:38:21 +00:00
8f1bd6a6bb More abuild fixes, this should be the last (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 19:30:36 +00:00
17217ac298 Fix for newer iasl versions (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 18:29:59 +00:00
c9a8d11e0c trivial fix for abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 17:59:50 +00:00
56e7046cf7 Small fix to make the abuild happy, add ROM_SIZE to target/*/Config.lb,
using the default from src/mainboard/*/Options.lb (trivial)

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 08:07:37 +00:00
ba8965c039 Changed the stop_this_cpu() to just hlt.
Removed local APIC INIT (don't worry the APIC and AP are still initialized).

The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
The Intel Multiprocessor specification indicated that a vector should be set
and a START should happen following an INIT. Then AP will execute the 
instructions pointed to by the vector. There is no vector or start in
stop_this_cpu(). This seems to put the AP in an in-between state. In the case
of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
debugger.

The better solution seems to be to just put the AP in a hlt and allow the AP
to go into C1. Then APIC managing software running on the BSP can program the
AP as needed.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:52:11 +00:00
2ce8bfd251 Initial AMD Serengeti_Cheetah_FAM10 platform for Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:49:44 +00:00
0da5cdeac2 Additional early AMD8111 southbridge support for Barcelona platforms.
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.


Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:36:46 +00:00
8ae8c88220 Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 01:32:08 +00:00
2006b38fed Whitespace and other code cleanup in peperation for AMD Barcelona support.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19 00:47:09 +00:00
244dd82fd6 Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:22:40 +00:00
e9690bddd5 Add dump support for NSC PC87317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:10:00 +00:00
8ef47da471 Enable IDE legacy port access for all 440BX based boards per default, as
this is needed (at the very least) to make FILO work on these boards.

Disable UDMA/33 per default, which is slower but the safe choice, as we
don't know which IDE devices a user has attached, and some don't support
UDMA/33 very well or at all.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 21:34:53 +00:00
12a3f1edec To make it easier to add new SPI chips to flashchips.c, rename functions
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 14:33:32 +00:00
3b408fd237 Add support for ST M25P80 chips to flashrom. Detection was tested.
Print status register before erase to help debugging block locks.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-16 21:15:27 +00:00
c9a677b4b3 Add dump support for SMSC LPC47M192.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 20:00:58 +00:00
c7e12e2a9d Add dump support for NSC PC97317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 00:04:16 +00:00
aa6dd7407d Add detection and dump support for NSC PC97307.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:56:16 +00:00
48c7032c28 Add dump support for NSC PC8741x.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:41:45 +00:00
850c01cacf Add support for more atmel chips:
AT49F002
AT49F002N
AT49F002T
AT49F002NT

Only tested the read function on AT49F002T.
datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf

Signed-off-by: Frederico Silva <frederico.silva@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-10 16:57:59 +00:00
15674b78be This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
line in it.

I figure that only adding it to the files that already have support
for LZMA payloads makes sure I don't break anything.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-09 17:18:29 +00:00
94a84dee9e Add detection and dump support for NSC PC87309.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-08 00:17:19 +00:00
11887f258d Add/fix some LDN descriptions (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 23:55:20 +00:00
25df0c586a Fix typo. According to National's datasheet PC87317 has SID = 0xd0 and
PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 21:55:12 +00:00
435325e7ac Remove the coherent_ht_car.c file. It is exactly the same as
coherent_ht.c (save one empty line removed) so there's no use
to keep it around.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-05 19:26:55 +00:00
186a3875dc Various coding style fixes, constification, fixed typos (trivial).
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04 21:49:06 +00:00
17e993214f Enable vga option rom support for 1MB rom chip, which is what the h8dmr ships with (trivial).
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04 01:15:29 +00:00
d795b9a9ec Add board-enable for Acorp 6A815EPD.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-02 19:03:23 +00:00
9da69f83d9 Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):
- Implement ISA related support:
   - Initialize the RTC
   - Enable access to all BIOS regions (but _not_ write access to ROM)
   - Enable ISA (not EIO) support
   - Without the *_isa.c file, the Super I/O init is never performed
 - Improve IDE support:
   - Add config option to enable Ultra DMA/33 for each disk
   - Add config option to enable legacy IDE port access
 - Implement hard reset support
 - Implement USB controller support
 - Various code cleanups and improvements

The code partially supports southbridges other than the 82371EB (but
which are very similar), more complete support will follow.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-30 02:08:26 +00:00
8d43b343cf fix abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 15:01:53 +00:00
59b99d9071 Various small fixes (trivial).
- Add missing contributors to the README.

 - Drop obsolete -D option from manpage.

 - Only list contributors who added non-trivial amounts of code as copyright
   holders (and do not list those who merely provided register dump support
   for Super I/Os). Those contributors are still listed in the README,
   of course. See discussion in the thread starting at
   http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html

 - Make a function static.

 - Fix incorrect URL in code comment. Drop obsolete comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 02:43:50 +00:00
8e290d38e4 Flashrom does not work after booting LinuxBIOS on the Iwill DK8-HTX board,
according to mcqmcqmcq@fastmail.fm. Fix it.

Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
Acked-by: mcq <mcqmcqmcq@fastmail.fm>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 02:28:55 +00:00
447aafe5db Restructure/rename/comment a few 82371XX-related PCI IDs (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 01:44:43 +00:00
8708c1b7c3 Update AMD CPU IDs in model_fxx_init.c with information from
the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for
AMD Athlon 64 and AMD Opteron Processors' datasheet.

Also, add information about the CPU socket for each ID (as per datasheet).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 01:25:29 +00:00
020724fc70 Drop the unfinished, non-working Bitworks IMS board.
It never worked in v2 (the v1 port did work AFAIK, though), and it's
not really useful as reference for other boards anymore (as we now
have a dozen or so 440BX boards which work in v2).

This is a specialized, custom board (not sold on the "public market"),
so it's probably not useful for pretty much everyone out there anyway.

We can easily re-add it later (based on one of the other 440BX boards)
should there be interest and/or someone with the hardware to test.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-27 01:24:46 +00:00
254f47ef98 Correction to irq tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-26 21:43:21 +00:00
29cbb367b0 Dump support for SMSC FDC37C67x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 21:43:29 +00:00
d1bfaa92e8 More abuild fixes, the previous ones weren't enough. Hopefully this covers everything.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 03:49:43 +00:00
c29533a37d Small abuild fix for the iwill dk8_htx and latest iasl. Building this still fails for me, but it's an lzma error and probably Debian's fault.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 01:08:20 +00:00
44a115706b abuild fix for the asus a8v-e_se and newest iasl version (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:58:09 +00:00
4617191ca1 abuild fix for the amd serengeti_cheetah and the latest iasl version (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:50:06 +00:00
13f7a00200 Fix abuild for ASUS MEW-AM.
You cannot set 'default ROM_SIZE = 0' in Options.lb (and override it in
targets/*/Config.lb). While it'll work for manual builds, abuild doesn't
cope with that very well. So set a valid value in Options.lb, too.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 00:13:51 +00:00
cc454483b4 Add support for the ASUS MEW-AM board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-24 22:09:38 +00:00
4dea67193e Add dump support for the PC87366.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-24 21:49:39 +00:00
33715eb95c Mark devices which are not available on the board with "N/A" to
make it clearer why they are disabled (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22 14:55:13 +00:00
f811edefd9 Dump support for the SMSC LPC47B27x (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22 03:36:18 +00:00
c8cf4ad422 1. Fix pirq routing table setting for GA-2761GXDK.
2. Southbridge PCIe slots are working correctly now.
3. Disable keyboard & mouse ports for GA-2761GXDK.

Signed-off-by: Morgan Tsai <my_tsai@sis.com> 
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-20 14:11:24 +00:00
74b29b9e33 Detection support for more Super I/Os. Small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-17 17:13:52 +00:00
70ab323ae6 Various cosmetic fixes and improvements (trivial).
- Use 'static' where appropriate.
 - Use 'const' where appropriate.
 - Indentation fixes.
 - Add comment wrt init code which is only valid for VT8237R.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-15 15:52:42 +00:00
e13abe53b4 Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal.
Reason: The existing code does not tell us why it sets the watchdog
clock at all, but since it appears in cache_as_ram_auto.c instead of
the usual place (Config.lb) there has to be some meaning to it.
Simply do what the proprietary bios does: Use the external clock source.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 17:57:04 +00:00
34153ac0b8 Autodetect presence of serial flash and set up the board accordingly.
This enables us to have only one configuration and one set of code for
all revisions of the Gigabyte GA-M57SLI-S4.
Flash is now setup correctly for both SPI and LPC flash.

Detection of SPI flash in flashrom on rev. 2.x boards now hangs
instead of failing. However, that is just an effect of the combination
of incomplete initialization of the SPI controller and paranoid checks
in the flashrom SPI code.
If anyone wants to work on that, he needs a logic analyzer or creative
imagination. Hint: LPC-to-SPI read passthrough, clock signal.

Remaining issues for the M57SLI: Fan/environment control.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 15:09:30 +00:00
31e805dadb * Maintaining SiS south bridge device IDs.
* Strip unnecessary driver modules.

Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 01:34:02 +00:00
4c28034e58 Add detection and dump support for the SMSC FDC37N958FR (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 00:30:36 +00:00
5fd9a78a9d Small fix to make abuild happy (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 23:32:03 +00:00
59ef59ea94 Fix ACPI issues brought up with Intel's latest ASL compiler.
iasl now defaults to put created files into the input file's path, not into the
current directory.

This (trivial) patch fixes the behavior for the northbridge specific ASL code.

Further checkins to be expected.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 21:20:13 +00:00
9fe02e8c65 [LinuxBIOS] flashrom support for AMD Geode CS5536
Attached is a patch that enables AMD Geode CS5536 chipset support.  I
have tested it successfully on a MSM800 board from digital logic.

Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 16:45:22 +00:00
8b942e75d2 Random minor cosmetical or coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 16:24:15 +00:00
cc3ccdb643 Add support for FID/VID changes messages.
Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will
assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how
long. Imho for 100us. Which is more than plenty (2us required) I will try
to justify this once I know what bios to set in SB.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 15:40:21 +00:00
3adc30eed5 Small fixes. Drop unneeded or incorrect lines (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 15:26:56 +00:00
3c225a7cb4 Add dump support for NSC PC87360.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 15:16:06 +00:00
6d6146c377 Fix ATMEL 29C020 detection with flashrom. The JEDEC probe routine had
a delay of 10 us after entering ID mode and this was insufficient for
the 29C020. The data sheet claims we have to wait 10 ms, but tests have
shown that 20 us suffice. Allow for variations in chip delays with a
factor of 2 safety margin.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 14:56:54 +00:00
d591baa22f Drop obsolete failover.c, forgot it in the last commit (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 14:40:45 +00:00
f7f6046f0a Various small fixes to make the Tyan S1846 match the format of
the other supported 440BX boards.

Fix up totally b0rked static device tree in Config.lb.
Drop useless and duplicated failover.c, use global one.
Make CPU init actually work (result: massive speed-up).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 14:31:30 +00:00
9fab090e97 Add support for the Advantech PCM-5820.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 14:26:54 +00:00
a6ddf253ad Fine-tune the V-link bus between K8T890 and VT8237R and set
it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be
needed for VT8237A/S etc. Using VIA recommended values despite they are for
K8T890CF, this is K8T890CE (still dont know what is exactly different).

This patch enables the parity error reporting on V-Link, so it enables NMI
generation for the SERR# errors. The NMI may not be generated, maybe port
61h needs some tuning too.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 10:47:11 +00:00
a422c2d3c6 Grouping register dumps by 8 register values per group for better readability.
Remove trailing spaces within the register dumps.

Signed-off-by: Frieder Ferlemann <Frieder.Ferlemann@web.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 09:09:33 +00:00
9c22e8625f Drop superfluous exit_conf_mode*() calls, we don't want to call them twice.
Small cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12 21:02:44 +00:00
390648df64 Fix the remaining issues with GA-M57SLI Super I/O GPIO configuration.
With this patch, flashing the parallel EEPROM on board revisions 1.x
finally works. Flashing the serial EEPROM of board revisions 2.x is just
one patch away.

Torsten Duwe says:
Flash erase on my board was failing reliably. Now it works!

Andreas B. Mundt says:
For the first time I was able to write with flashrom and LB.
$flashrom -Vv --write linuxbios.rom
[...]
Vendor ID: GIGABYTE, part ID: m57sli
Found chipset "NVIDIA MCP55", enabling flash write... OK.
[...]
SST49LF040B found at physical address 0xfff80000.
Flash part is SST49LF040B (512 KB).
LinuxBIOS last image size (not ROM size) is 4096 bytes.
Manufacturer: GIGABYTE
Mainboard ID: m57sli
This firmware image matches this motherboard.
Programming page: 0007 at address: 0x00070000
Verifying flash... VERIFIED.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Torsten Duwe <duwe@lst.de>
Tested-by: Andreas B. Mundt <andi.mundt@web.de>
Tested-by: Torsten Duwe <duwe@lst.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12 11:14:10 +00:00
18517e8a1f Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO
configuration.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Torsten Duwe <duwe@lst.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12 02:33:31 +00:00
c716254e16 Fix up totally broken Super I/O config on the MS-6178. Add
PIRQ table to make most devices work. Random small fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-08 02:28:43 +00:00
6503cd9d00 Final set of changes to make Alix1c work.
Fix IRQ tables (Thanks to Marc Jones)

Fix IRQ SLOT #

Comment out ram test in early startup. 

make the debug print in lx/raminit.c a debug print, not emerg print

Set the default console log level to 3, but leave in the possibility of 
running with more info (leave maximum at 11)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 23:13:43 +00:00
cce5040153 Add initial support for all known ICH* southbridges to the
i82801xx code for the following parts:

 - AC97 audio/modem
 - Onboard network interface cards (NICs)
 - USB 1.1 controllers
 - SMBus controllers

Some other parts are still missing and will be added later.

Use PCI ID #defines from pci_ids.h everywhere. Constify various structs.
Also, fix some random cosmetic issues in the code.

All of this is relatively trivial and tested by manually building
all boards which currently use the i82801xx code.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 22:09:02 +00:00
f9f1ae8ddb Make the LZMA compression option work in buildrom.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 19:07:17 +00:00
908ff5ecac This patch masks the function prototypes in stdlib.h from ROMCC, so that
ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h
to vt8237r_early_smbus.c, so it'll build on those systems.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 19:02:35 +00:00
c9f8a67139 This patch adds the pci ids of c7 cpus to the existing model_centaur. c3
and c7 init are identical, according to the datasheets, so there's no 
need for another folder. As the comment says, some of these model IDs 
may never be produced, but they are reserved by Via for the c7.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 18:55:06 +00:00
b294582a0f Add PCI IDs for most Intel southbridges of the 82801 series
(ICH/ICH0 up to the ICH9 family) in preparation for further
code improvements for the i82801xx southbridge code.

Small fixes in the 6300ESB PCI IDs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07 00:19:42 +00:00
c931625bab Fix the M57SLI routing table, as apparently set up from LinuxBIOS on
that board. Shift PCIe pin numbers downwards, and PCI int pins upwards.
This puts both PCI slots' int A and PCIe 16x int A into the right
position.

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-05 22:35:01 +00:00
a358892e2c * Change one PCI vendor ID from Nvidia to SiS
* Remove dead code
* Remove unused variables
* Fix bug where array was one element too small
* Fix error value truncation, the old code never entered the error path
* Remove warnings

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-05 22:21:27 +00:00
39462d7156 make agami aruma compile again.
Rudolf's suggestion making the symbol weak is elegant, but let's allow
some more discussion.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 23:37:44 +00:00
3ac07e447f another small abuild fix.. add payload compression "uses" for the a8v-e-se
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 19:03:42 +00:00
4f6aa126e7 Small fix to make abuild happy on the asus/a8v-e_se (trivial)
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 17:29:01 +00:00
2cb7014991 Add dummy function for MCFG on those mainboards that provide ACPI but don't
have PCIe MMCONFIG.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 16:50:27 +00:00
25d712ac16 merge changes to match agami's production environment
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 16:25:05 +00:00
f7daa0bbaf Various cosmetics, coding style fixes, constifications (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 04:04:01 +00:00
a29ec0633a Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.

Use human-readable names for the PCI ID #defines.
Rename *_ISA to *_LPC as per datasheet.
The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.

The fixes in southbridge code are only to keep the build working for now,
any real improvements will only go into the 82801xx code in future.

This is abuild-tested so it shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04 03:21:37 +00:00
02b2365f02 This patch is some small changes to the vt8237r to prepare it for
the Jetway J7F2 patch that should be coming soon, and also moves most
defines into vt8237r.h. I've changed some of the values from u32 to u8,
because that's all they should ever need to be. Also includes
doxygenized comments!

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-03 18:45:42 +00:00
e6409f218c This patch adds support for MCFG table, which allows OS to find the
MMCONFIG for memory mapped PCIe config.

However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.

PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-03 12:50:26 +00:00
ec70af6470 This patch changes the "if else" style of parameter matching to table and also changes the rdpreamble parameter, which will cause that more then one DIMM will work for 939 motherboard.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 23:27:12 +00:00
1a0025675f Asus A8V-E-SE support from Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 23:17:57 +00:00
b45bfabd2a remaining part of the patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 17:05:04 +00:00
aa2a670c57 Delete a file no longer used by the SiS implementation
No functional code changes.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 16:18:25 +00:00
218c26533d 1. vgabios removed, will go to extra repository
2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
   src/include/device/pci_ids.h
4. Trim trailing spaces for all files

Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 16:09:58 +00:00
7162cf7278 fix up iwill board compilation. Untested, trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 12:54:49 +00:00
894562f4eb fix up IBM servers.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 12:35:30 +00:00
bc3f2f0641 get arima hdama building again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 11:06:40 +00:00
66e7d5e5f4 fix juki 511p abuild by adding a Config-abuild.lb. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 10:36:15 +00:00
7d8cd7602f This patch fixes the superio of the khepri 2100e as detected:
> superiotool r2922
> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e

Don't use the non-working trident driver for the blade3d (onboard vga 
in the rom emulator has not been tested either)

It also adds some preliminary CAR support to the board, so it has a chance to
build again.

This board was broken since a couple of months, and the changes are minimal, so
I consider this a trivial change -- It doesn't change anything that was used,
obviously

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 09:48:14 +00:00
9c84a46007 trivial fix for the .data problem
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02 00:31:11 +00:00
9d5c3a8ea4 This patch is a trivial response to a good comment from Uwe, so I am
self-acking before it gets lost.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-01 15:15:14 +00:00
a0181ea036 Use the preferred order of 'static const' instead of 'const static'.
This is the common style in both Linux as well as in LinuxBIOS.

Self-ack as this is pretty trivial and a similar patch was already acked.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 22:26:51 +00:00
246be7dd6d Use the preferred order of 'static const' instead of 'const static'.
This is the common style in both Linux as well as in LinuxBIOS.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 22:22:11 +00:00
e7537f134d As started in
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html ,
but change all apparantly related values that differ on my board with
legacy BIOS.

This makes both PCI cards appear, as well as the firewire device
TSB43AB23.
* PCI 01:07.0 appears fully functional
* PCI 01:08.0 (closer to the board edge) appears, but no interrupts
* PCI 01:0a.0 (FireWire) untested

Since none of these was even present without the patch I suggest to
apply it.

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:49:38 +00:00
a8e2a0b852 Add initial support for the Compaq Deskpro EN SFF P600.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:26:08 +00:00
6d90afe6fd Add initial support for the Biostar M6TBA.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:25:06 +00:00
a910cbe3bf Add initial support for the AZZA PT-6IBD.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:23:57 +00:00
84b2ae0025 Add initial support for the A-Trend ATC-6220.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:22:32 +00:00
7fe1ce14fb Add initial support for the GIGABYTE GA-6BXC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:07:31 +00:00
26f0abd627 Add initial support for the ASUS P3B-F.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 00:00:57 +00:00
be0e24b578 Add initial support for the ASUS P2B-F.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 23:59:47 +00:00
113c2013bb Various smaller fixes to make the ASUS P2B match the format
of all the other boards in this patch series.

Add missing PIRQ table to make most devices work.
Enable VGA support. Add flashrom flashing protection code.
Make CPU init actually work (result: massive speed-up).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 23:57:59 +00:00
68d8a56cc5 Various fixes and improvements of the 82801xx code.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 21:55:11 +00:00
c4590dae6a [LINUXBIOS] Add the CPU_OPT flag to facilitate passing flags into the build
buildROM passes build flags through the CPU_OPT environment variable - 
especially -fno-stack-protector for those of us lucky enough to have
Debian/Ubuntu.  This adds  to the cache_as_ram_auto.inc target
for the GA-2761GXDK so that the resulting cpu0.S is clean.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 17:53:53 +00:00
bbb2ff3ceb Small rename to make abuild happy (trivial).
This is not yet enough to actually successfully build the board, but
now abuild at least _attempts_ to build it.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 17:21:45 +00:00
94ec5eccd9 Drop empty directories (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 17:06:28 +00:00
7cc3bf319a Rename the SiS761GX/SiS966 board to the correct name, GIGABYTE GA-2761GXDK.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 15:58:59 +00:00
418bc919d0 Add support for the VIA VT8237R southbridge.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 03:09:39 +00:00
af6e745173 move target directory to have the same name as the directory in the
mainboard/ path. Also add a Config.lb for abuild. It's required for the
three images variant as abuild doesnt detect this automatically.
Trivial patch - it does not even fix the build yet. Patches welcome.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 02:24:49 +00:00
83b52e7193 fix the readwrite/readonly clashes for the pci_driver structs in the sis
code. This is trivial, I did it for the other components before.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 02:17:49 +00:00
f32325ed8a K8 resource dump utility from Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 01:12:20 +00:00
825c809efe Add support for Intel 440MX systems.
Add support for the Fujitsu MBM29F400TC flash part.

Detection and reading works, writing is not tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 00:56:50 +00:00
1602dd5fdd Thanks to the great efforts of Morgan Tsai of SiS we support the SiS966
southbridge now:

From: Morgan Tsai <my_tsai@sis.com>                                                                                                       

It supports SiS761GX / SiS966 chipset, only for AMD K8 platform so far.
Due to integrated VGA sharing system memory, some code in southbridge
folder have to init northbridge.

Copyright (C) 2007 Morgan Tsai <my_tsai@sis.com>
Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)

Change Log:

Newly support GIGABYTE GA-2761GXDK
CPU type: AMD AM2 socket
Northbridge: SiS 761GX
Southbridge: SiS 966
SuperIO: ITE8716F

Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-29 21:00:14 +00:00
55e6ebaf6a Move ARRAY_SIZE to stdlib.h to make it available to all code (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-27 20:05:21 +00:00
9b80a8d4bc Drop duplicated and unneeded #defines from some northbridges (trivial).
This is generic PCI stuff, not nothbridge-specific in any way.
The respective #defines are already present in src/include/device/pci_def.h.

Abuild-tested, so shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-27 19:45:49 +00:00
65bc460e01 This code gets us to a working linux boot on the alix1c. I have not tested
Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up 
comments, and just in general customizing for the 1c. 

The lxraminit 
change fixes a bug (&& used instead of ||), adds some debug prints which were
VERY useful debugging the alix1c, changes fatal error messages from print_debug
to print_emerg, and adds two functions: 
banner, which just prints out a string with a banner, and 
hcf, which print an emergency message and then pushes null bytes
into the uart forever, just to make sure that no bytes get lost 
for any reason. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-26 14:57:46 +00:00
3d02e1e0d8 Add support for the AXUS TC320 thin client.
This board uses nearly the same devices as the BCOM Winnet100, so most of
the new code here is from the BCOM Winnet100. They differ in the IRQ routing
table only.

BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz SDRAM
clock speed (it runs reliably here since month).

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-26 14:42:21 +00:00
5384dac57e Added Am29LV040B
Looking through the sources of Uniflash utility I found that this chip
is no more no less than low-voltage variant of Am29F040B but with
different ID.

So I created a very quick patch (attached).

Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-25 04:11:11 +00:00
cb00e7ab94 Some fixes for the BCOM WinNET100, mostly in Config.lb:
- Add missing entry for the NIC:

     device pci 0f.0 on end           # Ethernet (onboard)

 - Drop the following lines:

     register "com1" = "{115200}"
     register "com2" = "{38400}"

   Those entries hardcode the BAUD rate (as far as I can tell, please
   correct me if I'm wrong). We don't want that -- instead the config option
   TTYS0_BAUD in Options.lb should be used(?) I verified that dropping those
   lines will not break serial output (COM1, 115200, 8n1).

 - Enable IDE (PCI device 00:12.2) and add the following register lines
   to tell the CS5530 code to actually enable IDE channel 0:

      register "ide0_enable" = "1"
      register "ide1_enable" = "0"     # Not available/needed on this board

   Tested with a 2.5" hard drive and FILO, works fine.

 - Enable USB (PCI device 00:13.0), not sure why it was commented.

 - Enable COM2 as it's used by the smartcard reader.

 - Add CONFIG_COMPRESSED_PAYLOAD_LZMA to Options.lb, in order to fix
   abuild for this board.

 - Add some more comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 20:17:04 +00:00
bf873e4ae3 Another CONSTification...
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 14:42:12 +00:00
50542a884b This change removes all warnings from romcc in my build environment,
making the output of "make -s" finally usable.. (still trivial, doesn't
change any logic or remove any code)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:14:14 +00:00
a9e5821fdd smaller changes to silence build warnings. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:12:15 +00:00
124e4a45ca analog changes for the cpu_driver structures...
make them const before putting them into the read-only segment...
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:10:21 +00:00
f1cf1f7c3a Ever wondered where those "setting incorrect section attributes for
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.

Despite its size, this is a fairly trivial patch created by a simple
search/replace

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 09:08:58 +00:00
0dff6e3fa9 fix a whole bunch of warnings. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 22:17:45 +00:00
643eee0754 drop unused variable (and thus warning). trivial patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 19:23:52 +00:00
8b83836115 Add support for the Intel mFCPGA 478 socket. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 18:59:21 +00:00
862ccfd84f The s2882 ships with a 1MB rom chip. The targets/tyan/s2882/Config.lb file
assumes a 1MB rom chip.

Hence the default position for the VGA bios should also assume a 1MB rom chip,
not a 512KB chip.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 12:06:53 +00:00
35823e97fc Fix typo (trivial)
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 20:56:13 +00:00
e6d093ff00 Add support for a precompressed LZMA payload (trivial).
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 20:55:29 +00:00
2ef39274a3 Flashrom: Add more Vendor IDs and ensure correct sorting in flash.h.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 20:36:16 +00:00
1d4fc0cff9 This patch adds support for K8T890CE northbridge.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 19:59:57 +00:00
bed2f9c2fe Trivial: remove unused variable.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 17:04:39 +00:00
c4a0b911d1 Introduce block and sector erase routines to flashrom, but do not use
them yet.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 16:15:28 +00:00
d56981f778 This is a hack for easier testing of GRUB2 in LinuxBIOSv2
since it is still our most wide-spread codebase. 

The patch is pretty trivial, and nobody except Torsten even looked at
it in a week, so....

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 10:07:46 +00:00
cb56d216fc Put the print in the right place. This is trivial patch but a very
serious issue, so I am self-acking.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-21 04:33:02 +00:00
dd8632846b I am signing off and acking this trivial patch, as I just wasted several
days on a function named pll_reset that, on exit, says "Done
cpuRegInit", and which, in turn, made me think it was a lot farther
along that it was. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-21 03:51:06 +00:00
bd7602314b Remove hardcoded wait from SPI write/erase routines and check the chip
status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 17:56:42 +00:00
69a392b5c6 Documentation fixes and updates (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 00:29:05 +00:00
79aa01a6c3 Add generic SPI flash erase and write support to flashrom. The first
chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 00:24:07 +00:00
dcb9abdf4c Some cosmetic cleanups in the flashrom code and output.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:55:15 +00:00
7dabe5ea0d Drop support for the --human-readable option. It's not any more useful than
the --dump option, it just means lots of additional work for no gain, IMO.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:43:59 +00:00
d937b5243c Print the version number always, not only in verbose mode.
We often want to know the exact version number of superiotool which
was used to gather a certain output/dump.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:42:02 +00:00
7a90c14e9c Add dump support for the Winbond W83697SF.
Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:37:36 +00:00
e447df1b25 Add a debug message to keyboard init. This helped isolate at least one
case of keyboard failure (the keyboard initialization was never hit).

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 22:34:40 +00:00
84453c02f7 Fix wrong values/typos in chipset_enable.c. This has been confirmed by
Ed Swierk in
http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html .

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 22:30:07 +00:00
fb0b3e7787 Fix up totally broken Super I/O setup on the MSI MS-7260 (K9N Neo).
This has not been working at all until now. With this fix, keyboard,
mouse, parallel port, and the Super I/O sensors work fine (tested
on actual hardware).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 01:57:14 +00:00
f8dabccdbf Multiple flashrom fixes:
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.

 - Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
   "System administration commands (usually only for root)".

 - Actually install the manpage upon 'make install'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 23:36:34 +00:00
398b605ddb Add detection support for the Winbond W83977AF as found in the
Advantech PCM-5820 board (confirmed by Erwan Velu <erwan@seanodes.com>
on IRC). Trivial (and tested) patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:56:32 +00:00
e62537a948 Add Gigabyte M61P-S3 SPI flash support to board_enable.c
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:18:43 +00:00
259aaf00f5 Convert the existing it8716f_* functions to generic_spi_* functions by
applying abstraction and wrapping.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:09:06 +00:00
52bc99367c Add resource size and resource granularity reporting to device_util.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 18:21:22 +00:00
dc34cab5cb Fix the detection for the Winbond W83697SF. Unfortunately the revision
has a slightly different format than that of the W83697UF/UG so we have
to hack around it a bit.

This patch has been verified to work on real hardware by
Idwer Vollering <idwer_v@hotmail.com> on IRC (thanks!).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 18:15:25 +00:00
92d3434f87 Dump support for the Winbond W83977TF.
Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 00:34:03 +00:00
8c1c1c0557 Completely rip out / replace the ASUS P2B code (which wasn't really working),
replacing it with a minimal, but working, framework which will be expanded.
Drop a bunch of useless and duplicated files, add missing license headers.

I'm self-acking it this time, the diff is a huge unreadable mess and the old
code is broken anyway...

This code is tested to build fine, and can boot a Linux kernel up to a
login-prompt via FILO (IDE). This is verified on actual hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 00:13:59 +00:00
16f6171eda (forgot to add spi.c)
Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.

The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:45:29 +00:00
a28edc524b Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.

The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:44:47 +00:00
a3e03872f3 This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA)
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:39:48 +00:00
72c0584d37 Fix stupid thinko in the Winbond detection code which prevented some
of the Winbond chips from being detected (trivial fix).

This is verified on real hardware and works fine now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 15:46:59 +00:00
4910809cad Add dump support for the NSC PC8374L (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-14 17:02:15 +00:00
572268eaa7 Fix the resource end in amdk8/northbridge.c.
Without this bugfix, the resource for the PCI/ISA video memory at
0xa0000 - 0xbffff is too big, i.e. it goes up to 0xcffff instead of
just 0xbffff as it should.

Here's the diff from two runs of the tool from 
http://www.linuxbios.org/pipermail/linuxbios/2007-June/022449.html
on the MSI MS-7260 (K9N Neo), with and without the bugfix. After applying,
the resource size is correct again.

--- dumpres_lb_pci_vgacard_without_resfix.txt
+++ dumpres_lb_pci_vgacard_with_resfix.txt
@@ -11,7 +11,7 @@
 MMIO map: #2 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
 MMIO map: #3 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
 MMIO map: #4 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
-MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W     Dstnode:0 DstLink 0
+MMIO map: #5 0x00000a0000 - 0x00000bffff Access: R/W     Dstnode:0 DstLink 0
 MMIO map: #6 0x00fc000000 - 0x00fd1fffff Access: R/W     Dstnode:0 DstLink 0
 MMIO map: #7 0x00fd200000 - 0x00fd1fffff Access: R/W     Dstnode:0 DstLink 0
 MMIO map: #0  0x000000 - 0x003fff Access: R/W  ISA VGA Dstnode:0 DstLink 0

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-14 00:29:25 +00:00
39a5bf74ef Set the superiotool version number from svn at build time.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-13 18:06:12 +00:00
45c1556df9 Dump support for the SMSC LPC47N227.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-13 17:06:21 +00:00
c63643dc90 Changes to flashrom to support the K8N-NEO3, first tested at Google on GSOC day :-)
Also minor changes to remove tab-space combinations where possible. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Index: jedec.c
===================================================================
--- jedec.c	(revision 2847)
+++ jedec.c	(working copy)
@@ -281,7 +281,7 @@
 	// dumb check if erase was successful.
 	for (i = 0; i < total_size; i++) {
 		if (bios[i] != (uint8_t) 0xff) {
-			printf("ERASE FAILED\n");
+			printf("ERASE FAILED @%d, val %02x\n", i, bios[i]);
 			return -1;
 		}
 	}
Index: board_enable.c
===================================================================
--- board_enable.c	(revision 2847)
+++ board_enable.c	(working copy)
@@ -153,7 +153,8 @@
 		return 1;
 	}
 	/* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note:
-	   We can't use writecnt directly, but have to use a strange encoding */
+	 * We can't use writecnt directly, but have to use a strange encoding 
+	 */ 
 	outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
 	do {
 		busy = inb(port) & 0x80;
@@ -202,43 +203,39 @@
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
-#define W836_INDEX 0x2E
-#define W836_DATA  0x2F
-
 /* Enter extended functions */
-static void w836xx_ext_enter(void)
+static void w836xx_ext_enter(uint16_t port)
 {
-	outb(0x87, W836_INDEX);
-	outb(0x87, W836_INDEX);
+	outb(0x87, port);
+	outb(0x87, port);
 }
 
 /* Leave extended functions */
-static void w836xx_ext_leave(void)
+static void w836xx_ext_leave(uint16_t port)
 {
-	outb(0xAA, W836_INDEX);
+	outb(0xAA, port);
 }
 
 /* General functions for reading/writing Winbond Super I/Os. */
-static unsigned char wbsio_read(unsigned char index)
+static unsigned char wbsio_read(uint16_t index, uint8_t reg)
 {
-	outb(index, W836_INDEX);
-	return inb(W836_DATA);
+	outb(reg, index);
+	return inb(index+1);
 }
 
-static void wbsio_write(unsigned char index, unsigned char data)
+static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
 {
-	outb(index, W836_INDEX);
-	outb(data, W836_DATA);
+	outb(reg, index);
+	outb(data, index+1);
 }
 
-static void wbsio_mask(unsigned char index, unsigned char data,
-		       unsigned char mask)
+static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
 {
-	unsigned char tmp;
+	uint8_t tmp;
 
-	outb(index, W836_INDEX);
-	tmp = inb(W836_DATA) & ~mask;
-	outb(tmp | (data & mask), W836_DATA);
+	outb(reg, index);
+	tmp = inb(index+1) & ~mask;
+	outb(tmp | (data & mask), index+1);
 }
 
 /**
@@ -248,37 +245,80 @@
  *  - Agami Aruma
  *  - IWILL DK8-HTX
  */
-static int w83627hf_gpio24_raise(const char *name)
+static int w83627hf_gpio24_raise(uint16_t index, const char *name)
 {
-	w836xx_ext_enter();
+	w836xx_ext_enter(index);
 
 	/* Is this the w83627hf? */
-	if (wbsio_read(0x20) != 0x52) {	/* SIO device ID register */
+	if (wbsio_read(index, 0x20) != 0x52) {	/* Super I/O device ID register */
 		fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
-			name, wbsio_read(0x20));
-		w836xx_ext_leave();
+			name, wbsio_read(index, 0x20));
+		w836xx_ext_leave(index);
 		return -1;
 	}
 
 	/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
-	wbsio_mask(0x2B, 0x10, 0x10);
+	wbsio_mask(index, 0x2B, 0x10, 0x10);
 
-	wbsio_write(0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
+	wbsio_write(index, 0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
 
-	wbsio_mask(0x30, 0x01, 0x01);	/* Activate logical device. */
+	wbsio_mask(index, 0x30, 0x01, 0x01);	/* Activate logical device. */
 
-	wbsio_mask(0xF0, 0x00, 0x10);	/* GPIO24 -> output */
+	wbsio_mask(index, 0xF0, 0x00, 0x10);	/* GPIO24 -> output */
 
-	wbsio_mask(0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
+	wbsio_mask(index, 0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
 
-	wbsio_mask(0xF1, 0x10, 0x10);	/* Raise GPIO24 */
+	wbsio_mask(index, 0xF1, 0x10, 0x10);	/* Raise GPIO24 */
 
-	w836xx_ext_leave();
+	w836xx_ext_leave(index);
 
 	return 0;
 }
 
+static int w83627hf_gpio24_raise_2e(const char *name)
+{
+	return w83627hf_gpio24_raise(0x2d, name);
+}
+
 /**
+ * Winbond W83627THF: GPIO 4, bit 4
+ *
+ * Suited for:
+ *  - MSI K8N-NEO3
+ */
+static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
+{
+	w836xx_ext_enter(index);
+	/* Is this the w83627thf? */
+	if (wbsio_read(index, 0x20) != 0x82) {	/* Super I/O device ID register */
+		fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
+			name, wbsio_read(index, 0x20));
+		w836xx_ext_leave(index);
+		return -1;
+	}
+
+	/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
+
+	wbsio_write(index, 0x07, 0x09);	/* Select logical device 9: GPIO port 4 */
+
+	wbsio_mask(index, 0x30, 0x02, 0x02);	/* Activate logical device. */
+
+	wbsio_mask(index, 0xF4, 0x00, 0x10);	/* GPIO4 bit 4 -> output */
+
+	wbsio_mask(index, 0xF6, 0x00, 0x10);	/* Clear GPIO4 bit 4 inversion */
+
+	wbsio_mask(index, 0xF5, 0x10, 0x10);	/* Raise GPIO4 bit 4 */
+
+	w836xx_ext_leave(index);
+
+	return 0;
+}
+
+static int w83627thf_gpio4_4_raise_4e(const char *name)
+{
+	return w83627thf_gpio4_4_raise(0x4E, name);
+}
+/**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
  * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered there.
@@ -335,12 +375,12 @@
 	pci_write_byte(dev, 0x59, val);
 
 	/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
-	w836xx_ext_enter();
+	w836xx_ext_enter(0x2E);
 
-	if (!(wbsio_read(0x24) & 0x02))	/* flash rom enabled? */
-		wbsio_mask(0x24, 0x08, 0x08);	/* enable MEMW# */
+	if (!(wbsio_read(0x2E, 0x24) & 0x02))	/* flash rom enabled? */
+		wbsio_mask(0x2E, 0x24, 0x08, 0x08);	/* enable MEMW# */
 
-	w836xx_ext_leave();
+	w836xx_ext_leave(0x2E);
 
 	return 0;
 }
@@ -487,9 +527,11 @@
 	{0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
 	 "gigabyte", "m57sli", "GIGABYTE GA-M57SLI", it87xx_probe_serial_flash},
 	{0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise},
+	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
+	{0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	 "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e},
 	{0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
-	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise},
+	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e},
 	{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
 	 NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
 	{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
@@ -509,8 +551,8 @@
  * Match boards on LinuxBIOS table gathered vendor and part name.
  * Require main PCI IDs to match too as extra safety.
  */
-static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
-							     char *part)
+static struct board_pciid_enable *board_match_linuxbios_name(char *vendor, 
+								char *part)
 {
 	struct board_pciid_enable *board = board_pciid_enables;
 
@@ -525,10 +567,11 @@
 			continue;
 
 		if (board->second_vendor &&
-		    !pci_dev_find(board->second_vendor, board->second_device))
+			!pci_dev_find(board->second_vendor, board->second_device))
 			continue;
 		return board;
 	}
+	printf("NOT FOUND %s:%s\n", vendor, part);
 	return NULL;
 }
 
@@ -545,20 +588,20 @@
 			continue;
 
 		if (!pci_card_find(board->first_vendor, board->first_device,
-				   board->first_card_vendor,
-				   board->first_card_device))
+					board->first_card_vendor,
+					board->first_card_device))
 			continue;
 
 		if (board->second_vendor) {
 			if (board->second_card_vendor) {
 				if (!pci_card_find(board->second_vendor,
-						   board->second_device,
-						   board->second_card_vendor,
-						   board->second_card_device))
+						board->second_device,
+						board->second_card_vendor,
+						board->second_card_device))
 					continue;
 			} else {
 				if (!pci_dev_find(board->second_vendor,
-						  board->second_device))
+							board->second_device))
 					continue;
 			}
 		}
@@ -582,7 +625,7 @@
 
 	if (board) {
 		printf("Found board \"%s\": Enabling flash write... ",
-		       board->name);
+			board->name);
 
 		ret = board->enable(board->name);
 		if (ret)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-12 21:22:40 +00:00
6dbc0e12da Superiotool manpage/documentation improvements (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-11 18:30:05 +00:00
90216de462 Set the default video memory to 0 MB for all GX1 boards which don't yet
use that feature in order to not waste RAM.

Also, add missing CONFIG_VIDEO_MB for the eaglelion/5bcm, which should
fix the build for that board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-11 10:25:35 +00:00
f904a596d0 Revert my last cleanup patch.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10 17:42:20 +00:00
5982a0641b Cosmetic changes to make the flashrom output more consistent (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10 16:31:30 +00:00
ae1ab3edec This patch adds the CONFIG_VIDEO_MB option to boards that
currently don't have it but need it to compile with the new Geode GX1
VGA support. This sets the size at 4MB, which was the size previously
defined in the VGA code.

Signed-off-by: Corey Osgood <corey.osgod@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10 15:01:48 +00:00
96fb22d9b0 Minor cosmetic changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-09 23:58:35 +00:00
d744d906a7 Add support for the BCOM WinNET100 (used in the IGEL-316 thin client).
See http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial for hardware
description and build tutorials.

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-09 23:26:19 +00:00
0446dbbd60 Fixup a register dump attached to the wrong Super I/O. Seems something
went wrong in one of the recent commits.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-08 01:59:46 +00:00
14f304ace1 Add detection support for lots more SMSC Super I/Os (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-08 01:11:11 +00:00
557a9018ed Make the reserved video memory on Geode GX1 based systems configurable.
This makes sense on systems with small memories when the VGA feature is
not used (CONFIG_VIDEO_MB = 0 in this case).

On Geode GX1 based systems the following amount of memory should be reserved
when VGA support is enabled:
 - 1MiB for VGA and SVGA resolutions
 - 2MiB for XGA resolution
 - 4MiB for SXGA resolution

Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 22:46:51 +00:00
a166bb1e00 Add missing '\n' to a printk_debug() and some other small fixes
while I'm at it (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 22:25:49 +00:00
44bb777062 Some more ITE chips and small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 21:50:29 +00:00
abeb63df5f Detection support for a bunch of NSC Super I/Os (trivial).
Also, dump support for the NSC PC87351.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 21:48:26 +00:00
37f166982e Fix some issues with spaces in the code and Doxygen style documentation.
Painting the splash graphic is now ifdef'ed.

Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 21:00:02 +00:00
e9d4616a95 Print a short message if no Super I/O chip could be detected (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 20:01:23 +00:00
84bf1e2506 Add a list of contributors to the README (trivial). Also, a small hint
about where to send additional register dumps.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 19:10:24 +00:00
c387b0b89e Add dump support for the Winbond W83627THF/THG.
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 19:04:26 +00:00
09203573c1 Add a manpage for superiotool (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:26:40 +00:00
8a9c03f0de Dump support for the SMSC FDC37B72x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:12:12 +00:00
e1073f1a54 Dump support for the SMSC FDC37B78x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:04:17 +00:00
87c4999672 Dump support for the SMSC FDC37M81x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 14:33:13 +00:00
409b4f2273 Add dump support for the Winbond W83627HF/F/HG/G.
Signed-off-by: Rasmus Wiman <rasmus@wiman.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 21:58:03 +00:00
4ac32176d1 This patch will add support for the Geode GX1/CS5530 VGA feature. It's able
to set up one of five screen resolutions (sorry no autodetection at runtime,
resolution is selected at buildtime) and displays a graphic in the right
bottom corner (splash screen).

Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 21:00:10 +00:00
23740c82e2 Add dump support for the SMSC LPC47M10x (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 15:11:38 +00:00
dc81769c9c Add dump support for the ITE IT8661F. Note that this chip will not yet
be detected, as it needs a non-standard init sequence.

Minor other fix: Drop incorrect 0x2b from LDN 5 of the ITE IT8705F.

Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 13:47:04 +00:00
5debf36d9d Add some more Winbond chips (trivial).
Add notes which IDs were taken from sensors-detect (as where we lack
datasheets, thus cannot verify them) and which we support but sensors-detect
does not (yet). I'll post patches on the lm-sensors list to sync up
the detected chips between superiotool and sensors-detect.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 18:34:36 +00:00
db5f953754 Add detection support for the LPC47B387 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 16:28:56 +00:00
4354103078 Add dump support for the ITE IT8705F/AF.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 15:44:19 +00:00
8b8d03974e * Convert the NSC code to the common code structure all other Super I/Os use.
* Improve the --verbose output a bit more. Print the "Probing..." text for
   all Super I/Os and if a Super I/O is not known, show the data we were
   able to read from the chip (what data this is is very vendor/chip specific).

 * Thus the common no_superio_found() is dropped, it's not useful.
   The "read from 0x20" part was wrong for all Super I/Os other than the
   NSC ones anyway.

 * Winbond: For the 'olddevid' only use bits 3..0, mask away the others.

 * SMSC: Print which ID registers we try to read (in --verbose mode).

 * Minor cosmetic fixes.
   * Rename PC8374 to PC8374L (as per datasheet).
   * Rename probe_idregs_simple() to probe_idregs_nsc().
   * Rename dump_readable_ns8374() to dump_readable_pc8374l().

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 15:23:38 +00:00
573ff508ab [FLASHROM] Fix the help, and print a message when nothing happens
The help implied that writes happen by default, which they don't.  Fix
the text, and say something when we dont specify any commands.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>    
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 06:26:41 +00:00
209148c535 Add a copy of the GPL (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-03 18:56:51 +00:00
ec1edd1cd9 Print superiotool version when run with --verbose.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02 23:32:21 +00:00
0de6f0a36f This patch aims to restructure SPI flash support in a more reasonable
way. It introduces a generic SPI host driver for the IT8716F Super I/O
which will enable easy SPI programming without having to care for the
peculiarities of the SPI host.

To activate probing for the IT8716F, you have to use the gigabyte:m57sli
mainboard override. SPI support will then use the gathered SPI host data
to access the SPI flash.

This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the
GA-M57SLI v2.0, which has a MX25L4005 SPI flash part.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02 15:49:25 +00:00
3617103cc7 Thee lines in i82801xx_pci.c need to be removed. They cause the
i82801DB to reset. See this thread for more info:

http://article.gmane.org/gmane.linux.bios/26791

Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>


Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-01 18:32:00 +00:00
e4d4ebabbd De-uglify the --version output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-01 13:39:02 +00:00
afe8309202 Random minor fixes. Use svn revision as superiotool version number.
Make the -V output more informative.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:45:43 +00:00
945045b1ea Add support for some more Fintek chips and an ALi chip.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:39:10 +00:00
5f45fc234f Fix up the SMSC detection code to probe _both_ old- and new-style
Super I/Os from SMSC. Otherwise not all of them are detected (and there
could theoretically be _two_ of them in a system, so we should probe
for both types anyway).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:02:17 +00:00
7fe8f5da4d Add preliminary SPI flash identification support for SPI chips attached
to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte
M57SLI board. It works only with rev 2.0 of the board, but it will bail
out on earlier versions, so no damage can occur.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-27 14:29:57 +00:00
03f2322175 Don't arbitrarily enable PERR# and SERR# for PCI devices.
It is platform specific.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26 16:41:15 +00:00
c3da36681d Add detection support for lots more Winbond Super I/Os (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26 16:14:16 +00:00
e0ffaa164d Dump support for the Fintek F71805 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26 15:48:09 +00:00
f845e02edb As per suggestion from Yinghai Lu <yinghailu@gmail.com> this patch
fixes the problems with PCI add-on cards not being detected or
initialized on MCP55-based systems (PCI bridge decoding change).

I have tested this on the MSI MS-7260 (K9N Neo) with a PCI VGA card,
which worked fine in any of the three PCI slots.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-25 01:31:35 +00:00
48cac24742 Detection support for the Winbond W83627HF (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 23:24:46 +00:00
2ee78d8b06 Fix compilation warning.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 22:02:31 +00:00
322076cdad Various cosmetic changes and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 20:00:32 +00:00
0f86732a5e Add detection support for quite a number of SMSC Super I/Os. Also, add
dump support for the SMSC DME1737 and the ASUS A8000. Random minor fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 01:40:09 +00:00
6b4ad4304a Minor fixes/improvements in the Fintek code (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-23 13:17:29 +00:00
3a9740db2e Fix another, similar typo as in r2800 (trivial).
Reported by Robert Millan.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22 20:13:27 +00:00
aa8e9bd6d3 Fix typo which causes build error if CK804_USE_NIC is set (trivial).
This is tested with abuild so shouldn't break anything.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22 19:51:48 +00:00
c49b834710 Add SiS device IDs for further update.
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-22 17:51:48 +00:00
d9ab798a2f Fix abuild for the MSI MS-7260 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21 23:13:28 +00:00
970d06b10d Add support for the MSI MS-7260 (K9N Neo) mainboard.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21 15:56:05 +00:00
420f6abc11 Add register dump capability for ITE IT8718F (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21 14:48:04 +00:00
eddc473ce0 Add -D / --dump-readable option which prints the Super I/O register
contents in human-readable form (e.g. "COM1 enabled" etc.) instead
of the hex-table format from -d / --dump.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 23:57:44 +00:00
b4db2209f9 Decouple the ITE code from fintek.c, it doesn't belong there.
Add common 'enter configuration mode' function for most Winbond/Fintek/ITE
chips which use the 0x87 0x87 sequence for that reason.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 23:37:56 +00:00
0702469f16 Fix up and generalize the ITE IT8708F code. It was only working out of
pure luck (and broken code elsewhere). Needs some more fixing.

Add more LDN descriptions to various Super I/Os.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 22:13:48 +00:00
42670a75ef The s2891 ships with a 1MB rom chip. The targets/tyan/s2891/Config.lb file assumes a 1MB rom chip.
Hence the default position for the VGA bios should also assume a 1MB rom chip, instead of a 512KB chip.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 15:01:14 +00:00
2c290e3362 Superiotool: Add dump support to the Winbond W83697HF/F.
Minor coding style changes and code simplifications.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 00:00:49 +00:00
e474956590 Implement usage for --help and put the same information into the README, too.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 16:26:18 +00:00
7e7e9ac607 Add support for the Winbond W83697HF/F and W83627EHF/EF/EHG/EG.
Various minor fixes and improvements (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 15:52:23 +00:00
3acf31e4ea Further code simplifications and improvements.
Add command line option handling code. The following options
are defined at the moment:

-d|--dump      Dump Super I/O registers.
-V|--verbose   Verbose mode.
-v|--version   Show the superiotool version.
-h|--help      Show a short help text.

Per default (no options) we just probe for a Super I/O
and print its vendor, name, ID, version, and config port.

Example:

$ ./superiotool
Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0

$ ./superiotool -d
Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00
def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00

$ ./superiotool -s
./superiotool: invalid option -- s

$ ./superiotool -h
Usage: superiotool [-d] [-V] [-v] [-h]

$ ./superiotool -v
superiotool 0.1


Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 01:55:35 +00:00
3ef9b740de Add support for a precompressed LZMA payload (trivial).
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:57:37 +00:00
786b0c4ed6 Sorry, I mixed up two patches. Reverting this change.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:52:14 +00:00
25a6c0f18c Split out enter_conf_mode_*()/exit_conf_mode_() functions, we'll soon need
them. Reduce code duplication a bit by improved 'no dump available' handling.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:48:42 +00:00
c73ea4d4fc Add support for a precompressed LZMA payload (trivial).
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:43:02 +00:00
de24a0e585 Use uint16_t and friends where appropriate (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:03:14 +00:00
d754d2c6c4 Make the code a bit more generic (trivial). Different Super I/Os
use different config ports.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 23:30:24 +00:00
6ff6af7621 Superiotool: Add support for the SMSC FDC37N769.
Here's what a register dump looks like on my test system:

No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
Super I/O found at 0x03f0: id=0x28, rev=0x01
SMSC FDC37N769
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 
val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00 
def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00 
Probing 0x0370, failed (0xff), data returns 0xff

I'm self-acking this as it's pretty simple stuff, but please let me
know if anything could be improved here, or if you think this
is not trivial enough to warrant self-acking.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 22:24:34 +00:00
d8a18a2adb Add a README for superiotool (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 00:01:27 +00:00
519419b476 Split out a dump_superio() function from ite.c, and make it slightly more
generic, so that we can use it for other Super I/Os, too.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 20:59:01 +00:00
4cb7e71732 Make 'struct superio_registers' globally available, pretty much
all Super I/Os can (and should!) use this (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 18:17:44 +00:00
0120e1a3d8 Split up superiotool.c into multiple source files, one per vendor.
As there will be lots more supported Super I/Os soon, the file is
really getting way too big...

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 18:11:03 +00:00
18c70d7222 More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.
For example: in C51/MCP55 or C51/MCP51

Will allow
1. C51 at 0x10 to 0x14, and MCP at 0 to 4
2. C51 at 1 to 4, and MCP at 7 to 0x0a

The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it
needed), and will prevent us from putting them on bus 0.

Typical values for c51/mcp55 or c51/mcp51:
HT_CHAIN_UNITID_BASE = 0x10 # for C51
HT_CHAIN_END_UNITID_BASE = 0 # for mcp

If only have mcp with c51, 
HT_CHAIN_UNITID_BASE = 0 # for MCP
#HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14 14:58:33 +00:00
3335adb771 This is a full rewrite of all the CS5530/CS5530A code. The previous code was
mostly undocumented, had a broken coding style, contained lots of dead
code and had several other problems, e.g. it enabled write access to the
ROM (why?), it unconditionally enabled primary/secondary IDE (which should
have a config option) and that even _twice_ (which is um... wrong).

The new code

 - has 'ide0_enable' and 'ide1_enable' config options (which actually
   work) to enable/disable the primary/secondary IDE interface in
   Config.lb.

 - Does _not_ enable write access to the ROM (or is there some good
   reason to do that? If so, it should at least have a config option).

 - Contains a bit more documentation.

 - Uses readable (and documented) #defines instead of hardcoded magic values.

 - aaand... it actually compiles ;-) Yep, that's right. The previous code
   wouldn't even build, as it hadn't been fully ported from v1 (still used
   v1 functions which are simply not available in v2).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14 00:09:29 +00:00
741e1e658f I still don't understand a word, but I tried to improve the documentation. (trivial)
Please fix this if you can.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13 13:47:02 +00:00
dde1d709a4 Fix abuild run of the MSI MS-6178 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13 09:55:44 +00:00
a9838cf796 Add a common/global failover.c file which can be used by all
(or at least most) mainboards. This should put and end to
copy-paste'ing the same file again and again for every mainboard.

Fix the build for the MSI MS-6178 target (wrong location of the common
failover.c file).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-13 08:38:24 +00:00
41b88342b9 Add initial support for the Intel 810 based board MSI MS-6178.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-12 22:11:33 +00:00
7798c888e8 Change out/in combinations to pci_read/write_byte in
sis630 chipset enable.

Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-11 15:58:18 +00:00
f9b0f7fd91 Remove useless 'extern' keywords (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:24:29 +00:00
863c1bf525 Add '(C)' where it's missing (for consistency reasons).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:21:05 +00:00
09735cb517 Add missing license header to udelay.c.
I'm self-ack'ing this, as the origin of the code in udelay.c (and thus
the license and copyright owner) is pretty clear.

The code which is now in udelay.c was split out from flash_rom.c in r1428,
and flash_rom.c, in turn, has been around since the beginning and had a
'Copyright 2000 Silicon Integrated System Corporation' line as well as the
usual GPLv2-or-later license header.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:02:45 +00:00
cbc95f32fb Partial changes and fixup.
Removed reset.c and added copyright headers.
Remove debug.c. It is not used and should not be here.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 19:43:31 +00:00
6226f13c11 Welcome to PC Engines and the ALIX 1C!
This is a geode LX board. There are timing settings that are not right
yet, we are still trying to get our board to boot Linux :-)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08 18:32:53 +00:00
9398958cfa Add a copy of the GPL in the flashrom repository as it's an independent
project (being packaged by distros, among other things).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08 14:36:01 +00:00
98ef9cefc8 Small consistency fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 21:20:29 +00:00
2046ff92f0 Various coding style and whitespace fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 21:02:44 +00:00
c4c54a5df3 Add ITE IT8716F support to probe_superio. This helps especially
GA-M57SLI board owners who wish to debug remaining problems or handle
SPI flash of newer board versions.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 20:24:30 +00:00
1ae8e83baa Rename probe_superio.c to superiotool.c.
Flesh out Makefile with all the usual stuff, e.g. install targets etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 20:20:41 +00:00
8c14e45bfd Move probe_superio into the global util/ directory.
Rename it to superiotool while we're at it.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 19:44:36 +00:00
bd26392f42 Add support for the ITE IT8708F.
Here's a dump from my test system which has an IT8708F:

No SuperI/O chip found at 0x002e
probing 0x002e, failed (0x87), data returns 0x87
SuperI/O found at 0x2e: id=0x8708, chipver=0x0
ITE IT8708
idx 07 20 21 22 23 24 25 26 27 28 29 2a 2e 2f 
val 02 87 08 00 00 00 00 00 03 01 01 00 00 00 
def NA 87 08 00 00 NA 3f 00 ff ff ff ff 00 00 
switching to LDN 0x0
idx 30 60 61 70 74 f0 f1 
val 01 03 f0 06 02 00 80 
def 00 03 f0 06 02 00 00 
switching to LDN 0x1
idx 30 60 61 70 f0 
val 01 03 f8 04 00 
def 00 03 f8 04 00 
switching to LDN 0x2
idx 30 60 61 70 f0 f1 f2 f3 
val 01 02 f8 03 00 50 01 7f 
def 00 02 f8 03 00 50 00 7f 
switching to LDN 0x3
idx 30 60 61 62 63 64 65 70 74 f0 
val 01 03 78 07 78 00 80 07 03 0b 
def 00 03 78 07 78 00 80 07 03 03 
switching to LDN 0x4
idx e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 
val 80 61 00 00 00 00 00 00 80 00 30 00 80 00 de 
def NA NA 00 00 00 00 00 00 00 00 00 00 00 NA NA 
switching to LDN 0x5
idx 30 60 61 62 63 70 71 f0 
val 01 00 60 00 64 01 02 0c 
def 01 00 60 00 64 01 02 00 
switching to LDN 0x6
idx 30 70 71 f0 
val 01 0c 02 00 
def 00 0c 02 00 
switching to LDN 0x7
idx 70 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc 
val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 01 00 00 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 7f 20 51 00 0e 00 00 00 00 00 00 00 
def 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA NA NA NA NA 00 00 00 00 00 00 00 00 00 00 00 NA 00 
switching to LDN 0x8
idx 30 60 61 
val 00 02 01 
def 00 02 01 
switching to LDN 0x9
idx 30 60 61 70 f0 
val 00 03 10 0b 06 
def 00 03 10 0b 00 
switching to LDN 0xa
idx 30 60 61 70 f0 
val 00 03 00 0a 40 
def 00 03 00 0a 00 
No SuperI/O chip found at 0x004e
No SuperIO chip found at 0x004e
No SuperIO chip found at 0x004e

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 19:42:42 +00:00
8a5a264748 Fix typo for the ITE IT8712F (trivial).
The default for LDN 5 (keyboard), index 0xF0 is not 0x00
but rather 0x08 as per datasheet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-31 20:51:00 +00:00
2109010290 Add support for the Athlon64 x2 5000+ CPU.
A trivial one-liner for the CPU I happen to have. The sales docs said it's
a "G1 revision", but the Rev F code works just fine.

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30 10:29:15 +00:00
736c1d8618 Add support for the Winbond W29EE011.
Signed-off-by: Markus Boas <ryven@ryven.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30 10:17:50 +00:00
3b78de6887 Add support for the Winbond W29C040P.
Signed-off-by: Markus Boas <ryven@ryven.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30 10:11:08 +00:00
6c71f73786 Change all flashrom license headers to use our standard format.
No changes in content of the files.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-29 17:52:32 +00:00
b1786c2bce This patch makes ITE Super I/O probing/dumping a little bit more generic,
fixes minor coding style issues and prepares the table for supporting
more chips of the ITE IT87xx Super I/O family.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-28 10:43:57 +00:00
7a7890aced This patch rewrites probe_superio almost completely.
Common code sequences have been factored out, the code has been made
more generic, has better handling of corner cases and is actually much
shorter.

It also adds probing for almost all recent (since 1999) ITE Super I/O
chips to probe_superio. I did verify against all ITE datasheets
(including those not available any more) that the probing was
non-destructive.

For the ITE IT8712F, the complete configuration is dumped and as
comparison the default value from the data sheet is printed.
More information can be extracted easily, however this needs loads of
datasheet surfing.

This code has been tested extensively, dumping for other ITE chips will
follow as a separate patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-27 07:28:28 +00:00
ba9ce9f7f9 Cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 16:08:21 +00:00
0a6bb91062 Drop duplicated code (copies of plain JEDEC functions).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 15:20:38 +00:00
2fe239134c Drop a bunch of useless header files, merge them into flash.h.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 13:34:59 +00:00
3a9bbc2cc8 Move code into *.c files, there's no reason to have it in header files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 10:20:40 +00:00
3436698b6a Fix bug in probe_28sf040() causing flash corruption on SST49LF160C verify.
The first byte of the flash chip was read at the start of the function
and later written back to address 0 if the flash chip was not identified
as SST28SF040, which means most of the time. This write caused corruption
of flash contents when verifying a SST49LF160C part.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-13 04:10:32 +00:00
4d43255bef flashrom: Add board enable for the EPoX EP-BX3.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-11 16:59:11 +00:00
7ab22686b8 flashrom: Add missing supported flash chips to the README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-27 03:32:45 +00:00
ae293d74f9 This patch adds support for the M50FLW040A, M50FLW040B, M50FLW080A,
M50FLW080B, M50FW080, M50FW016, M50LPW116, M29W010B flash chips made
by ST to flashrom.

The patch is based on the data sheets of the chips and has not been
tested at all.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-25 17:55:45 +00:00
3a262082ba This patch adds support for ST M50FW040 and ST M29W040B to flashrom.
Only reading from the chips was tested; writing support is untested.

Thanks to Gürkan Sengün <gurkan@linuks.mine.nu> for testing!

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-24 18:18:05 +00:00
451762dabc Fix Agami Aruma target (the only one using the part)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 20:07:54 +00:00
c0a689cc1f trivial: clarify comment on ADM1026_DEVICE address
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 17:02:52 +00:00
6540ae5ea0 Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 16:35:42 +00:00
6cf687783b some agami i2c merges
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 15:56:02 +00:00
3fa1363ee5 [Arg! Forgot to 'svn add', sorry]
Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 13:13:56 +00:00
aa4bedf98e Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.

Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.

So far only the ASUS A8000 has been tested on real hardware!

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-12 13:12:47 +00:00
9bcad23ba1 Flashrom: Add support for Tyan Tomcat K7M.
Same board enable as Asus A7V8-MX. Tested by Reinhard Max.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-04 17:51:49 +00:00
a0aaa752dd Artec Group dbe61 mainboard support.
Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-20 23:45:44 +00:00
dfb3c130d5 Various minor cosmetics and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19 22:47:11 +00:00
c72ff11281 The GPIOs used for UART2 RX and TX were reversed.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19 22:07:16 +00:00
cbb8d8ad24 This patch fixes up a couple mistakes I made with the i82810 and mew-vw to make
the system boot to a command line.

This patch comments out the code to set up the vga framebuffer to allow
the system to boot, without this fix the system hangs during elfboot.

The only line that is absolutely necessary to change is the SMRAM setup,
however I've commented out all vga setup to make it very obvious to both
the kernel/payload and anyone looking at the code that vga isn't
currently working. This setup might also be better handled in
northbridge.c, if it doesn't need to be done before ram init, yet
another reason to comment it all. In the future, LinuxBIOS needs to be
told that the graphics memory area, 1mb or 512kb (at the user or
developer's option), is reserved for the onchip vga, but I'm not sure if
it's taken at the top or bottom of the memory, yet. LB may also need to
set a base address for the AGP aperture and/or be told that range is
reserved as well, whether this was originally the job of the system bios
or vga bios is still a mystery. It also corrects the number of entries
in irq_tables.c, without this fix the kernel would probably complain and
hang due to unmapped IRQs.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19 07:33:39 +00:00
440113f00b small agami aruma configuration updates (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 21:45:21 +00:00
fc53b3c1ca Fix the static device tree of the ASI MB-5BLMP target. This was broken in
more than just one way. This version should be (more) correct.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 19:52:27 +00:00
dd55e86a52 his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 17:00:50 +00:00
d9e56e9cd3 Small bugfix in i82801xx_lpc.c.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 12:04:19 +00:00
c0eb5e0830 Add initial support for the Intel 82810 northbridge.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 12:02:38 +00:00
e99bd105af This patch adds support for the Intel i82810 northbridge and various i82801xx
southbridges, along with the Asus MEW-VM. With this, my machine attempts to
boot linux, but does so very slowly and fails during the boot process, probably
because of the irq tables.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 06:10:57 +00:00
bd88057f73 Add the AMD DB800 (AKA Salsa) mainboard.
The DB800 is the AMD LX Reference Design Kit platform.
For details see: http://www.amd.com/geodelxdb800

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-12 22:54:41 +00:00
bc359473e2 Minor tweaks in the 440BX RAM init code (trivial).
Still hardcoded for Tyan S1846.

This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07 22:16:30 +00:00
538b849695 Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards.
Both are very similar, thus both use the JUKI-511P target.

Linux with patches from Juergen Beisert
(http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html)
boots and work fine (ide, usb, ethernet, serial, keyboard and sound
work normally).

Problems:
 - Filo loads a bzImage only from ide0 (ide1 doesn't work yet).
 - Video doesn't work, yet.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07 20:52:42 +00:00
e29a664b54 Fix up and document the AMD CS5530/CS5530A support in flashrom.
The previous code was pretty unreadable, undocumented and did some totally
unrelated things (such as mucking with the game port or port 0x92).

This version is tested with a 256 KB chip and should work for the
CS5530 and CS5530A.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-06 21:35:45 +00:00
ecbe8e5d5c Add support for the Winbond W83977F-A Super I/O.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-06 10:26:00 +00:00
6602070955 flashrom: Document the newly supported IBM x3455 board and the
now-supported Broadcom HT-1000 chipset (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05 15:02:18 +00:00
5e2a42ae32 Move GPIO settings to board specific code for IBM x3455
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05 12:51:52 +00:00
444e39ee6d Add support for BCM HT1000 chipset to flashrom. Tested on IBM x3455.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05 10:28:39 +00:00
973b0680a1 Switch the Tyan S1846 to a fallback-only boot per default to allow
bigger payloads (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03 23:19:19 +00:00
6e96adbbab Tyan S1846: Minor fixes in static device tree (trivial):
- Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse
   in the output of 'lspnp -v'.

 - The floppy on 2e.f was a typo, should have been 2e.e from the beginning.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03 21:57:55 +00:00
4ce039feee Fix the static device tree of the Tyan S1846. Especially the
Super I/O part was incorrect.

Also, add ide0_enable/ide1_enable variables, and enable both the
primary and secondary IDE interface per default.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03 20:39:47 +00:00
56a9125453 Intel 82371EB: Some code simplifications (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03 16:57:27 +00:00
f027280d39 The UART disable code was causing a hang and was worked around with a
return that skipped the disable code. This patch removes the return and
fixes the UART disable code.

The problem was that the disable code was ORing bits into the Legacy_IO
MSR causing issues with the LPC SIOs init code that would manifest as a
hang because the IO would not be decoded correctly. ANDing to clear the
bits fixes the issue.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-02 23:55:17 +00:00
22c6afcae4 Drop duplicate 82371AB device IDs (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29 19:26:37 +00:00
a5599c10cf Use the common LinuxBIOS license header format.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29 12:06:06 +00:00
1410c2d219 Intel 82371EB: Add IDE init support.
In a mainboard's Config.lb file you can configure whether the primary
and/or secondary IDE interfaces shall be enabled.

Also, various fixups in the rest of the southbridge code, most notably
the early SMBus code, plus some documentation improvements.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29 10:37:52 +00:00
861f964037 Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).

All other delays are so low that we get away with just waiting 1us.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-28 14:37:06 +00:00
f5a6fd253c Various 440BX and Tyan S1846 related minor changes and fixes (trivial):
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
   available on all boards, regardless of what DIMMs you use.
   Tested on the Tyan S1846, works fine.

 - Properly set the PAM registers to allow the region from 768 KB - 1 MB
   to be used as normal RAM (required for the above).

 - Document all of this properly. Add/improve other documentation, too.

 - Simplify and document code in northbridge.c.

 - Cosmetics and coding style.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27 23:31:31 +00:00
4cb85533dd Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
accessible (but not writable), so that reading/loading a payload
from that area can work (for instance).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27 21:43:58 +00:00
4834a4f206 This patch fixes the processor name string for Rev F. CPUs.
It moves the complete naming functionality to
src/cpu/amd/model_fxx/processor_name.c.

The current code sets the processor name string twice for Rev. F CPUs.

In src/cpu/amd/model_fxx/model_fxx_init.c the function
amd_set_name_string_f is called first. Several lines later
init_processor_name is called which doesn't recognize newer CPUs and
actually programs incorrect values, thus overwriting the previously set
CPU name. For example, this resulted in identifying an Opteron 2218 as a
Turion processor.

This patch removes the amd_set_name_string_f function from
src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs
to src/cpu/amd/model_fxx/processor_name.c as described in the Revision
Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00,
October 2006.

Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-26 13:56:34 +00:00
cd3afc0524 Add initial support for the ASUS A8N-E board.
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 20:39:48 +00:00
63b087a8ab Drop the src/southbridge/amd/cs5536_lx directory and its contents, as
the new src/southbridge/amd/cs5536 code completely replaces it.

The Artecgroup dbe61 board currently uses it, but that is broken anyway
at the moment. A fix to use the new CS5536 code for it is being worked on.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 19:46:32 +00:00
da0eec07fb Minor cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 19:17:29 +00:00
4adc7421f5 Various IT8712F fixes:
- Add missing IT8712F_GPIO definition.
 - Add functions for entering and exiting MB PnP mode.
 - Add some more device init lines to pnp_dev_info[].

Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 18:44:50 +00:00
5ecfa2963d Small patch that adds an error message in case the keyboard selftest fails.
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 13:55:45 +00:00
1bccabc16c drop leftover includes (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 09:26:39 +00:00
0c6c4fcaf9 some copyright analysis
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 09:08:36 +00:00
8924fdd22b factor out register mapping code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24 08:48:10 +00:00
a18501dae8 Unify mmap error messages in flashrom (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-23 18:24:58 +00:00
f8eea5cd1c big cosmetic offensive on flashrom. (trivial)
* Give decent names to virt_addr and virt_addr_2
* add some comments
* move virtual addresses to the end of the struct,
  so they dont mess up the initializer.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-23 17:20:56 +00:00
f2d1428120 reverting 2683, NAK by YhLu, patch not necessary.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22 15:04:28 +00:00
344e45748a Add missing license headers, minor cosmetic fixes in existing headers.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-22 10:12:49 +00:00
f8953dc095 Add support for the Winbond W39V040FA chip.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 21:39:08 +00:00
0af4856017 Drop the (non-working, almost non-existant) support for
- the Transmeta TM5800 northbridge

 - the Densitron DPX114 mainboard (the only one using the TM5800)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 21:36:03 +00:00
1e79f12654 Drop romcc related stuff, as this board only uses CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 21:33:24 +00:00
931d922176 The Gigabyte m57sli-s4 board supports Rev. F CPUs.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 20:50:48 +00:00
ca7b4f5c49 fix some typos, clarify comments and drop dead code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 18:38:29 +00:00
ecad5df6b7 This is the last remainder from Yinghai's mega patch. It fixes issues with
devices conflicting with the northbridge devices on PCI bus 0.

Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21 18:11:17 +00:00
c141282193 fix lbtdump after last checkin. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20 17:28:55 +00:00
917bf6b99e Here is a small fix to prevent a segmentation fault in lbtdump.
The format specifier in the printf statements have been changed from
%08lx to %08llx or similar where uint64_t are being displayed.

Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20 17:10:17 +00:00
7f4040af82 Add additional CPU device ID:
CPU: vendor AMD device
30ff2
CPU: family 0f, model 3f, stepping 02

All I know is this makes it boot when it didn't before, YMMV.

Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20 16:36:01 +00:00
a56b998796 Flashrom: add support for ASUS P5A (Socket 7, ALi based).
* Add support for the ALi M1533 to chipset_enable.c
* Add some SMBus poking needed for the ASUS P5A, to board_enable.c

Since PCI subsystem IDs are worthless with this board, people will
have to name the board directly.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20 16:16:13 +00:00
9a2193e6f1 Fix typos (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19 19:22:55 +00:00
cbd53554df Minor cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19 17:28:40 +00:00
0196f82218 Initialize the fans on the adt7463 chip to be dynamically regulated by the
hardware, rather than always on at full speed. Set temperature treshold values
to safe defaults, rather than the not-so-safe power-on defaults.

Signed-off-by: Ward Vandewege <ward@gnu.org>

Acked-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-19 16:07:08 +00:00
3a9db88d5c Add missing license header (closes #53).
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-17 16:00:30 +00:00
819f5810b6 Whitespace fixes (trivial).
Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-17 11:20:18 +00:00
cbe4e1f3d2 Cosmetic changes: push includes to top of file in chip.h files.
Signed-off-by: Roger Zauner <roger@eskimo.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-16 06:58:15 +00:00
4c0d39fc59 Simplify spd_read_byte() functions (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 10:26:16 +00:00
f1ff2c38d2 Various cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 07:11:09 +00:00
c161808985 IEI NOVA-4899R: Add missing license headers.
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 06:57:57 +00:00
4c8c56753c IEI NOVA-4899R: Correctly configure Super I/O PNP devices.
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 06:56:12 +00:00
197daeda5a IEI NOVA-4899R: Fix incorrect irq_tables.c.
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 06:55:03 +00:00
8bcf08b119 IEI NOVA-4899R: Drop unused files.
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-15 06:50:06 +00:00
d83f79f3b8 AMD Norwich: minor cosmetic fixes and drop dead code (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-14 11:33:41 +00:00
4aae668fed Clean up whitespace in preparation for another patch to fix fan control.
This is nothing more than the result of running

  indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs adm1027.c

Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-11 19:23:57 +00:00
298a693c6b The Super I/O needs 0x87 sent twice to 0x2e (or 0x4e) to enable extended
function (power-on strapping). Although this is already done in superio.c,
it's not being done when w83627thf_early_serial.c is executed.
As such, no console_init() without it.

Signed-off-by: Roger Zauner <roger@eskimo.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-11 11:17:58 +00:00
f03e4e97ce Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:59:20 +00:00
d03b7d4289 This fix properly hides the UDC and OTG PCI headers when the cs5536 is
setup as the host on USB port4. In client mode the headers remain
available. Also fixes an outb to 0x80 to use the post_code() function.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:53:11 +00:00
deabf510bf Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
for timer calibration, which takes about one second.

All EPIA-M boards have timer2 so we use it to boot faster.

Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
calibration but add the TSC options so that they can be set in Config.lb.

src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
set HAVE_HARD_RESET=0 for both boards.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:50:27 +00:00
ddf845f620 This patch cleans up and clarifies Geode source code comments.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:22:27 +00:00
03625f4daf This patch cleans up \r left in the print strings. They were required for romcc code but no longer needed in cache as ram code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:13:18 +00:00
a909ee6185 This patch updates the PCI ID of the Geode IDE device to include the revision.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 23:12:18 +00:00
e1dd5e96c8 Fixed a bug within the 440BX RAM size calculation. Since the DRB values
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB.

Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com>
Signed-off-by: Roger Zauner <roger@eskimo.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 22:46:17 +00:00
00dc8595a6 indent is by no means as harmless as one might think ;-)
trivial fix.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 22:21:13 +00:00
f05e85b390 The attached patch sets the MA map type correctly for all DIMMs I was
able to find to test with the Epia.

Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 19:02:19 +00:00
1346a27dee This patch removes auto.c from the Norwich mainboard directory.
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 18:49:58 +00:00
2a133f7851 Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 18:43:57 +00:00
9934b813da Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 18:32:28 +00:00
f8030bd924 Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 18:16:03 +00:00
89d7cd2c83 Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 18:00:24 +00:00
4fcb3ba93f Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 17:58:11 +00:00
b29209f5f7 Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10 17:57:03 +00:00
a846a5effc The superio needs 0x87 sent twice to 0x3f0 to enable extended function
(power-on strapping). Although this is already done in superio.c, it's
not being done when w83977tf_early_serial.c is executed. As such, no
console_init() without it.

Signed-off-by: Roger Zauner <roger@eskimo.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09 17:54:25 +00:00
a59a7788b4 Uncomment compression config variables. This should fix the abuild
problems with the asi/mb_5bmlp (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09 15:11:03 +00:00
c7dc7cc196 Fix coding style of flashrom by running indent on all files:
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]

Some minor fixups were required, and maybe a few more cosmetic
changeѕ are needed.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09 10:17:44 +00:00
33d1af37ae This patch uses auto.c from Uwe's tyan s1846 for both boards, with some
minor changes, to bring them up to par. It also should remove (but might
just clean out) the irq_tables.c from both boards, because they were
just copied from Via Epia to begin with, and weren't usable. As far as I
can tell, these are the only changes needed to the targets for now,
aside from fixups to reset.c when the time comes. Both have been build
tested, but not checked on hardware since I don't have it. I have left
Uwe as the copyright holder since the only changes I've made are trivial.

Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09 08:11:52 +00:00
a440f7fd8c Add initial support for the ASI/BCom MB-5BLMP mainboard, as used in
the IGEL Winnet III thin client.

It boots a Linux kernel, but there are some problems. The login
prompt is never reached, it simply hangs at some point.
One possible reason is the IRQ table, which needs fixing.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-09 07:52:14 +00:00
6b83e46f3b New irq table, and a correct setting for
the 5c register in the southbridge so that interrupts are routed
correctly.
With this patch, ethernet works quite well.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-08 16:04:36 +00:00
50b0b8702c Add missing licenses to several of the files.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-07 22:26:46 +00:00
fa6c11eb40 This is the final patch to enable the msm800sev to build. This patch
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some
files in the mainboard directory. This patch has been tested but there
is a remaining problem which I am tracking down. Expect one more patch
to "get it all working".

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05 03:54:13 +00:00
5ef8b0f62b With this patch, the msm800sev runs FILO and boots a kernel.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>

-This line, and those below, will be ignored--

M    cs5536.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-05 00:10:31 +00:00
75869ff411 This patch as a cache_as_ram_auto.c for the msm800sev.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 23:15:28 +00:00
f64633e2c7 Drop src/mainboard/amd/norwich/debug.c as it is not used.
I'm self-acking as this is pretty trivial. I tested both a normal build
and an abuild-run, and nothing breaks.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 21:52:18 +00:00
3438421fd3 Some minor fixes in it8716f/superio.c:
- Add Ward Vandewege <ward@gnu.org> as copyright holder.
 - Use explicit 'uint16_t' instead of 'unsigned long'.
 - Minor cosmetics.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 21:33:40 +00:00
b93f9cadb2 patch to fix the IDE configuration on EPIA boards. At some point this
broke and stopped FILO
from being able to boot.

The fix is a simple one line change  plus a comment to
src/mainboard/via/epia/auto.c to write to the IDE
configuration register 0x42 .  This has always been done here, however
at some point
something broke it.

The same register was also being set correctly  in ide_init(), however
for some reason
this does not work. Possibly the register needs to be set before the IDE
peripheral is enabled
or maybe it is a timing issue.

The section of code in ide_init() (
src/southbridge/via/vt8231/vt8231_ide.c ) that does
write to register 0x42 has been commented out as it is superfluous
and I have added a comment to indicate the reason, should someone at a
future date wonder
why.

I have also changed the default COM speed from 19200 to 115200 in
src/mainboard/via/epia/Options.lb
There has been mention before about the EPIA board not being able to use
115200 but I have seen
no such problems with my board.

Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
This patch worked for me and allowed me to boot Debian kernel
2.5.16-4-486  on an epia 800 mhz system.  It is able to consistently get
through the initialization and start init now.

However, after that it crashes at various points in the boot process.

Acked-by: Alex Mauer <hawke@hawkesnest.net>

Note from comitter: I am commiting this, although:
1. it's not the exact right way to fix it up, the chip.h for the sb
should change
2. Alex reports problems, which are almost certainly memory issues. 

But it is as close as we've gotten. I can't test it.

Ron Minnich



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 19:43:57 +00:00
08da4f1fce This repairs the other Geode mainboards so they'll build with the new
Geode changes.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 19:09:01 +00:00
a67d4fd1ff This patch re-implements support for the CS5536 companion chip for the
AMD GX and LX processors.   This aguments the previous code, which was
very specific to the OLPC platform with general purpose support and
better integration with the VSA and CPUs.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 19:05:36 +00:00
734daf699c This patch adds support for the northbridge integrated into the AMD
Geode LX platform, including memory and graphics. (rediffed for whitespace)

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 18:58:42 +00:00
9c9083ba4a This patch adds support for the AMD Norwich development platform
based on the Geode LX processor.  The Norwich is the canonical
Geode reference, and will server as a good basis for other
Geode based platforms.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 18:47:52 +00:00
bc8176c552 This patch adds support for the AMD Geode LX CPU. (rediffed)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 18:24:55 +00:00
5941c25fe8 Add WinBond Super IO helpers.
* These helpers severely clear up winbond superio usage.
* Removed board_iwill_dk8_htx as it can be replaced by
  board_agami_aruma (Mondrian Nuessle).
* Renamed board_agami_aruma to w83627hf_gpio24_raise.
* Clarified comments in w83627hf_gpio24_raise, and added
  some things from the old iwill code.
* Moved all board functions name argument to const.
  (warning breaks build)
* Moved iwill entry in board_pciid_enables.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 04:47:04 +00:00
7ea18cf5dd Cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04 00:51:17 +00:00
6818245b1e Add missing license headers to some Geode LX related files.
The following original authors agreed to the license:

 - Ronald G. Minnich <rminnich@gmail.com>
 - Indrek Kruusa <indrek.kruusa@artecdesign.ee>
 - Stefan Reinauer <stepan@coresystems.de>
 - Andrei Birjukov <andrei.birjukov@artecdesign.ee>

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03 21:36:51 +00:00
24c9612490 Enable flashing on the IWILL DK8-HTX board by configuring the Super I/O
to set the right GPIO pins, so write protection is disabled.

Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03 10:09:23 +00:00
d436a4b4bc Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,
as that is not RAM but used for other stuff.

First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.

Use a real payload (FILO) per default now.

Note: this cannot boot a payload, yet, but it gets a lot further now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03 08:50:37 +00:00
941a6f078e Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-30 23:27:27 +00:00
7580f87f7a Add initial support for the following flash chips:
- Atmel AT29C020
 - STMicroelectronics M29F002B
 - STMicroelectronics M29F002T
 - STMicroelectronics M29F002NT

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Roger Zauner <roger@eskimo.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-28 02:22:59 +00:00
989de36703 Add fan control support to ITE IT8716F.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-27 21:24:53 +00:00
0e08333349 Activate EC for access to fan speeds and temperature sensors.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-26 20:55:45 +00:00
dabbf5777b Revert the image size increasing for abuild. It breaks more boards than
it fixes. It seems many of the other boards run out of space for the
payload.

Thus, this patch only increases the image size for the three boards

 - tyan/s2912
 - nvidia/l1_2pvv
 - gigabyte/m57sli

by adding a custom Config-abuild.lb file for each of them.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-25 00:23:39 +00:00
f83c182638 Increase image size for abuild. This should fix the build of these boards:
- tyan/s2912
 - nvidia/l1_2pvv
 - gigabyte/m57sli

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-24 21:54:21 +00:00
cdc5cc6711 trivial: fix filename in comment.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-24 18:40:02 +00:00
b80dbf0caa Add explicit license headers to all files in src/device.
For files derived from the Linux kernel we merely add a small header
which states the origin of the file and the copyright owners of the
modifications to the file.
We know all files from Linux are licensed under the GPLv2.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22 19:08:13 +00:00
6f278ad828 Use __PAYLOAD__ instead of PAYLOAD as replacement template for abuild.
Comment out code which currently doesn't compile. Needs fixing later.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22 19:03:34 +00:00
a94b4c6bc1 Update URL for the PCI IRQ Routing Table Specification (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-22 01:17:36 +00:00
29800b76ee Make the output of getpir look a bit less crappy (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-21 18:17:50 +00:00
9d5eec13a9 This patch makes a some elf debugging information available at log level
debug instead of spew. (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-14 16:34:32 +00:00
f1291cfdfc Exit on return code of read_layout and print error message to stderr
instead of stdout (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-14 16:32:59 +00:00
0594222ece On behalf of AMD:
Drop AMD prototype mainboards that were for internal testing & 
validation use only. 

Note: These boards could never be purchased. No reasons to worry.
Questions welcome via private mail.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12 01:23:12 +00:00
f0cf523a9e add uses CONFIG_COMPRESSED_PAYLOAD_* to allow building the board in
abuild with a payload. Trivial

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12 00:47:22 +00:00
17e27509a0 Fix two boards broken by the large patches of late.
artecgroup/dbe61
Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in
Config.lb.
Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run.

technologic/ts5300
Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the
development addon card anyways.
Changes to target Config.lb so it actually builds.

Signed-off-by: Peter Stuge <peter@stuge.se>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12 00:28:32 +00:00
b615c7bb3a Vendor specific patch, thus self-acked.
* going back to old board specific dsdt for agami aruma.
  This is hopefully dropped again some day, but until then 
  here's a working solution.
* Some minor Agami specific changes.
* drop obsolete bringup workaround hyperclocking.diff
* increase image size again, x86emu wants it.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-12 00:12:41 +00:00
2f7b1deca3 Config file update for Agami Aruma board.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-11 23:38:50 +00:00
f43cb68606 Trivial patch: Make buildrom a little bit more verbose.
It shows the remaining space in an image now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-11 23:36:02 +00:00
78b5e37e8c Rename flash_rom.c to flashrom.c. The tool is called 'flashrom' after
all.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-11 23:31:45 +00:00
46d65e85a1 Jeremy Jackson wrote:
I'm guessing nobody has tried compiling it with 64bit userspace?

Patch makes it compile cleanly and stops a "SEGV instead of working"
issue.

I also added a few checks for errors on system calls.

Signed-off-by: Jeremy Jackson <jerj@coplanar.net>

Reworked and
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-11 18:44:42 +00:00
4880353e03 flashrom: Add VIA CX700 to the list of supported southbridges (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09 22:59:22 +00:00
d6d7a1152c This patch corrects r2587. It makes sure that the VGA is initialized
when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1

Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09 22:50:12 +00:00
4e5cc9dcd0 add support for CX700 builtin southbridge
Signed-off-by: Randall Philipson <rtphilipson@cox.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-09 22:27:45 +00:00
24cc7bf436 increase image size for abuild (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-07 13:27:14 +00:00
0888c3613c Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-07 09:17:00 +00:00
00a018f511 YhLu's patch from January 18th.
hypertransport specific updates 

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 21:06:44 +00:00
da38d60a70 This commit is part of YhLu's patch from January 18th.
Drop a lot of debugging code from northbridge.c

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 20:59:54 +00:00
75812a66bb YhLu's patch from January 18th. This part is mostly cleaning up
dead code and adding a few fixmes.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 20:58:37 +00:00
47cb7c71c9 next part of YhLu's large patch. I am not sure whether the tables.c
changes are correct. If someone could look into this, thank you.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 20:27:40 +00:00
ad9a2c63ef Disable USB console on the m57sli for now.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 20:01:44 +00:00
c29b546eb1 Part IV
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:59:11 +00:00
30b4abeedc Part III of YhLu's patch from January 18th
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:57:42 +00:00
a3cf00e4ba two more directories from YhLu's mcp55 megapatch.
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:51:02 +00:00
21332b80d0 This is part of the outstanding mcp55 commit from January 18th. It will
likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.

Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 19:49:05 +00:00
778a42b129 This patch makes sure that VGA is initialized before it is used. Without
this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough.

Additionally, The VGA option rom will be executed if either
CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1.

Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 18:34:39 +00:00
ba43064d32 Trivial patch:
* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
  and references to it.
* move config option decision to preprocessor instead of code
  since config options can not change during runtime
* slightly more verbose output in built_opt_tbl.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 12:14:51 +00:00
03cafbfdfe Trivial (cosmetic) cleanup:
* Only open /dev/mem once and do it early.
* Drop extern for function prototypes.
* Minimize ts5300 impact in probe_flash()

This cleanup will making ICH7 SPI support quite some easier.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-06 11:58:03 +00:00
8944499617 Fix typo, add datasheet info, minor cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05 19:58:29 +00:00
e775edc4cb Coding style and cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05 18:53:37 +00:00
a01d0ea87c Add early serial support for the Fintek F81705F Super I/O.
Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-05 18:48:21 +00:00
b8c6437811 flashrom: split flash_enable.c into chipset_enable.c and board_enable.c
This splits up the ROM Write enable code into chipset specific and
board specific parts. This of course means that a lot of code is
plainly moved about.

* Allows for linuxbios name matching and pci-subsystem id matching.
  The latter uses a double set to properly distuinguish boards despite
  of some known vendors being lax about it.
* Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what
  that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop.
* Adds flashrom support for Asus A7V400-MX (KM400 + VT8235)
* Island aruma was renamed agami aruma, the board specific code now got
  adjusted. A set of pci-ids was retrieved from source code.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-04 22:45:58 +00:00
17d667b411 Add initial framework for the Tyan S1846.
It's not fully working, among other things because the Intel
440BX northbridge isn't working, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-03 10:45:53 +00:00
23d1e35d4d The *_early_serial.c pre-RAM code should do just that -- enable the serial
port(s), and nothing else. The code in superio.c will initialize the
rest when RAM is available...

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-02 16:57:32 +00:00
cbef76ecf3 Drop useless and partly even incorrect comments (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-01 20:00:32 +00:00
195237f2e1 Coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-01 19:44:21 +00:00
1a9c892d58 Initial Intel 440BX RAM initialization framework.
This does _not_ fully work, yet. You will _not_ be able to boot any
payload with this code, yet.

Add missing license headers.

Base the northbridge.c file on the Intel 855PM version, that comes
closer to what we want.

The raminit.c file is written from scratch and hardcodes several
values for now. This needs to be fixed later by reading the
correct values via SPD.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-01 17:24:03 +00:00
0d9d0bae8a Flashrom: Add support for the ICH7-DH southbridge (untested).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-31 19:48:38 +00:00
3a66263ff6 Add support for the NSC PC87309 Super I/O.
Pre-RAM serial output on COM1 and COM2 has been tested. The rest is not
yet tested on real hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-31 19:45:24 +00:00
5445639f06 This is a trivial cosmetic fix. Without it, the error message might look like:
Image size doesnt match: Success

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-22 14:51:45 +00:00
999bc60d5f fix a stupid cut and paste error.
This is pretty trivial, as it was correct in the original non-CAR code.
Suddently, CAR works nicely.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-20 13:43:50 +00:00
36b601ca3c Add initial pre-RAM serial output support for the VIA VT82C686(A/B)
southbridge (with integrated Super-I/O).

Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-17 14:00:23 +00:00
681d7887f4 The attached patch adds additional PCI IDs for MCP55 LPC devices to
flashrom. 0x0360 is needed to support the DFI LANParty NF590SLI, and I
am deducing the others based on pci_ids.h in the Linux kernel.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-06 23:49:49 +00:00
1b515cbaf4 Document POST codes emitted by LinuxBIOSv2.
The list was created by Richard Smith <smithbone@gmail.com>, see
http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/74.

It is probably not complete, yet.

(Closes #74)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-03 15:01:29 +00:00
47ce57acd7 flashrom: Fix wrong VT8235 flash enable failed warning.
* Fix harmless but worrying warning where the return value of
  pci_write_byte is misinterpreted.
* Hash together VT8231 and VT8235 code into VT823x. VT8231 is the better
  implementation, but lacked the write protect disable code that's
  apparently needed for VT8235.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02 22:16:38 +00:00
a81bb03b79 This patch splits console.c into 3 different files to get a better
overview of the code, facilitate future cleanups and reduce the
diff to Yinghai's tree at the same time.
No functional changes, only moving lines between files.
Copyright headers will be added later. Right now we benefit from
keeping the diff as small as possible.

Most of the work was done by Yinghai Lu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02 14:21:09 +00:00
412b8675c3 Add missing it8716f_early_init.c file, which got lost in the commit of
http://www.openbios.org/pipermail/linuxbios/2007-February/018330.html
in revision 2559.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02 12:29:40 +00:00
53b9c1e798 Add Winbond W39V080A support to Flashrom.
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-03-02 02:25:36 +00:00
811f5c10ee Add support for the Gigabyte m57sli-s4 board to flashrom.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-28 21:50:15 +00:00
d57241fab5 This is (most of) the usb2 debug console code ripped out of
Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] 
Rest of huge MCP55 patch).

I dropped a lot of stuff, like broken indenting, removed copyright messages,
and this printk_ram_* stuff (what the heck is this supposed to be)

This codebase is really a mess. Further tarball contributions without a
_CLEANED UP_ patch will be denied, especially if they are not from an up to
date svn tree.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-28 11:17:02 +00:00
3f5411cfca Add a note that the resulting LinuxBIOS images are licensed under the
terms of the GPL, version 2 (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-27 22:21:59 +00:00
e6fdf97075 This is another fixup round for Yinghai Lu's great patch.
It does the ROM_STREAM -> PAYLOAD rename that afaik was done after
Yinghai sent his work to legal, so it is required to get that code
building.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-27 14:11:18 +00:00
72e87062f4 List more possible payloads in the README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-26 13:52:42 +00:00
2a3223952e Improve ITE IT8716F support.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-24 17:39:11 +00:00
e15c4ca5ca Remove unused defines.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-24 15:18:22 +00:00
8a20213dde Fix some CHIP_NAME() entries to use canonical names.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-19 19:11:20 +00:00
7014ef83b9 Fix typo (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17 17:08:13 +00:00
4bdbb42818 Move HOWTO/ into documentation/ where it belongs (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17 16:24:41 +00:00
f55b58d533 Initial support for the following new mainboards:
* Nvidia l1_2pvv
* Gigabyte m57sli
* Supermicro h8dmr
* Tyan s2912 -- with HTX

The boards will currently _not_ compile, two further patches
from Yinghai Lu are still missing. Please be patient :)

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17 14:28:11 +00:00
3ecf5002b3 Currently the flashrom Makefile tries to detect whether pciutils-devel
is installed, but the test also fails if zlib-devel is missing. This
patch changes the error message accordingly.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-16 14:36:12 +00:00
fb1fddbab8 Add support for the MSI K9ND Master Series (ms9282) board.
Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-09 00:26:10 +00:00
4020dd5ac5 Include src/include/boot/linuxbios_tables.h in the flashrom source
tree to make it compilable independant of the LinuxBIOS source code.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-06 19:53:51 +00:00
4f9cf1373c This patch is a rework of Adam Kaufman's Solaris patch.
* flash.h:
  - add a license header
  - add system definitions
* flash_enable.c:
  - put io priviledge access in one single place
  - add includes required for Solaris.
* lbtable.c, flash_rom.c, 82802ab.c:
  - use MEM_DEV so it works on Solaris
* sst49lfxxxc.c, sharplhf00l04.c, sst_fwhub.c, 82802ab.c
  - drop unneeded include to sys/io.h
* Makefile
  - adapt to Solaris specifics.

Signed-off-by: Adam Kaufman <adam.kaufman@pinnacle.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Adam Kaufman <adam.kaufman@pinnacle.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-06 19:47:50 +00:00
bc7ceb1fd1 Add support for the Winbond W83627EHG Super I/O.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Bingxun Shi  <bingxunshi@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03 15:28:20 +00:00
c5708d19fd Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0,
that's the same as broadcom/bcm5785. 

Signed-off-by: bxshi <bingxunshi@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03 15:23:34 +00:00
de7f81f48a This eliminates an illegal and annoying warning.
'rom' is the current read pointer.
'rom_end' points to last valid byte of the stream. 

Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-03 10:43:48 +00:00
958a1f308a I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
2200 (too many names, sounds like a criminal).

1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
fine.

2) Then I push the reset button.

3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.

An investigation showed that in 3), short after kernel A (v2.6.19.2)
sets
the Bus Master Enable bit of the nVidia's USB1 controller
(pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.

Nothing is plugged to the USB ports. Other two Sun workstations had the
same
behavior. This does not make sense to me unless the controller has a HW
bug.

I believe, this should better be fixed in the kernel USB driver.

For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus
Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.

Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-02 22:40:10 +00:00
ff54db47fd Remove hardcoded gcc versions otherwise the build will break for
most people.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-02 17:08:04 +00:00
18878e036f Fix typo which breaks the build ('defalut' should be 'default').
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 22:43:27 +00:00
c3aaf6a99e This patch adds the MCP55 PCI IDs (without which the southbridge code
won't compile), and breaks an unnecessary dependency on the usbdebug
code.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 01:53:55 +00:00
57e700f4f4 great check-in message:
Linuxbios boots an Opteron motherboard with 1GB memory.

Linuxbios directly loads a recent linux kernel.
The memory layout is like this:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
   BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)

The f0000-f0400 region contains IRQ and ACPI tables.

At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:

# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

As you can see, the 00000000000f0400-0000000040000000
region is not listed.

It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.

The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.

This must be fixed either in linux or linuxbios.

Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:

BIOS-provided physical RAM map:
   BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
   BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
   BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
   BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
   BIOS-e820: 0000000000100000 - 0000000040000000 (usable)

The /proc/iomem contains:

# cat /proc/iomem 
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
    00100000-00203c61 : Kernel code
    00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
    e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
    f4000000-f4ffffff : 0000:03:00.0
    f5000000-f5ffffff : 0000:03:00.0
    f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
    f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
    f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
    f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0

Kexec is happier with the patch.

Regards,

Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 00:44:27 +00:00
0980049a62 This fixes a small typo.
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 00:40:51 +00:00
c65bd562a8 Add support for the NVIDIA MCP55 southbridge.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-01 00:10:05 +00:00
097d9a2d57 Add support for the SST 49LF160C.
Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-27 13:39:06 +00:00
8e4ee4f504 Delete superfluous and incorrect comment (trivial).
See also http://www.openbios.org/pipermail/linuxbios/2007-January/018042.html.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-24 11:09:03 +00:00
298f89850d Add support for the SST-49LF004C, SST-49LF008C, SST-49LF016C in flashrom.
Also add suport for NVIDIA MCP55.

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-22 20:21:17 +00:00
6a5bc46579 trivial enhancement
* add fintek superio support
* add license header
* add clean target in makefile
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-17 10:57:42 +00:00
96206510e3 Change 'ram' to 'RAM' in user-visible output (closes #60).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-01-16 11:56:35 +00:00
9095e30f2d A patch to add initial support for the i82801db southbridge based
heavily on the code for i82801dbm and i82801er

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-28 12:00:58 +00:00
a5fc22fd6b htx card on io apic on htx slot of dk8_htx
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20 20:21:05 +00:00
6c3874e8f8 ck804 pref mem 4G above support
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20 20:15:33 +00:00
c2c8646584 Improve flashrom description in the manpage a bit (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20 14:59:56 +00:00
7adaa11dcf Update flashrom requirements in the README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-20 14:53:22 +00:00
be13dc72d9 Apply linuxbios-rename-other-payload-options.patch
(Patch 2, refs #14)

Signed-off-by: Ed Swierk <eswierk@arastra.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 12:56:28 +00:00
8bb1dc5c77 ouch. always abuild with payloads! trivial fix.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 11:55:58 +00:00
1a7a5b49c5 Apply linuxbios-rename-compressed-payload-options.patch, refs #14
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15 11:42:16 +00:00
208948787e In the file mainboard/intel/i82801dbm/i82801dbm.c the variable
southbridge_intel_i82801dbm_control should be named
southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this
device is included in Config.lb of the mainboard.

Closes #62

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 14:54:00 +00:00
af433f2197 Add support for the SMSC FDC37M60x Super I/O (tested on FDC37M602).
Serial output on serial port 1 is tested and works, the rest probably not yet.

Closes #59.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 14:26:46 +00:00
abad5ef854 Add an install target to the flashrom Makefile which installs flashrom
into /usr/local/bin. Closes #54.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:59:41 +00:00
chn
f3938bbbbf In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o
space offset 0x1000, and later is the acpi registers also mapped at 0x1000. 
This patch fixes this behavior. Closes #44

Signed-off-by: <chn@virtutech.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:43:50 +00:00
a522df039b Add mtrr support for pentium m cpus
For cache to work the x86_setup_mtrrs() must be called. 

Closes #61

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:40:09 +00:00
0fac1e56d7 This is a typo that went into one of the abuild files. it will break abuild
on this board for everyone but me. Closes #58
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de> (trivial patch)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:31:38 +00:00
218e7ed10a Use the common LinuxBIOS license header (trivial). Refs #5.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-05 15:27:46 +00:00
d82baa1a2e Add missing license headers to some files (info based on svn history).
Adapt some existing license headers to use the common LinuxBIOS
format. Please note that this does not make any qualitative
license changes, merely cosmetic syntax changes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-05 14:13:10 +00:00
fe6d118b08 Update list of supported flash chips in the flashrom README (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-04 08:20:40 +00:00
6104bd1634 List the supported flash chips and southbridges in the flashrom
README file (trivial).

Closes #52.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-04 08:15:47 +00:00
dc95add598 Remove
#include <device/device.h>
from all *_early_serial.c ITE Super I/O files, as arch/romcc_io.h already
#defines device_t, thus adding device/device.h breaks the build (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-03 23:46:36 +00:00
5718338edb fix romcc preprocessor bug
Signed-off-by: Eric Biederman <ebiederman@lnxi.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-02 16:48:48 +00:00
2a44fbf2a0 Status update (trivial).
See http://www.linuxbios.org/pipermail/linuxbios/2006-November/017195.html

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-01 15:25:21 +00:00
6b2475dd81 Explicitly set the CLKIN to 24 MHz on all ITE Super I/Os, otherwise
serial output might not always work correctly (trivial).

Thanks Philipp Degler <pdegler@rumms.uni-mannheim.de> for testing and
reporting this issue.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-01 13:14:55 +00:00
39b13f4fa0 Add missing #includes to some ITE Super I/O files.
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-01 09:41:11 +00:00
3d91ecb876 Add convenience macros PAM0..PAM6 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-30 21:26:45 +00:00
7e2436360b add Config.lb files for abuild. This fixes both boards (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-27 16:32:49 +00:00
eba69b6078 Cosmetic fix of the nova4899r CHIP_NAME().
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-26 19:07:20 +00:00
3e15652a10 Add support for the IEI NOVA-4899R 5.25 SBC mainboard (patch submitted by
Luis Correia <luis.f.correia@gmail.com>). The code is loosely based on
the Eaglelion 5bcm mainboard.

Warning: this is work in progress!

As of now, it does boot with serial console only (no vga), and two ethernet
cards work sometimes. This has to do with the IRQ assignments, which are a
complete mess. USB is now apparently working, but I can't make any device
to be recognized.

The PCI slot is still unusable due to the IRQ thing.

Audio, other serial ports, irda, floppy and paralell port support is
unknown aka untested yet.

(closes #32)

Signed-off-by: Luis Correia <luis.f.correia@gmail.com> 
Acked-by: Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-26 19:05:16 +00:00
98b75f0e24 Fix location of the bug tracker in the manpage (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-22 15:27:29 +00:00
998a57c477 Update of the src/include/spd.h file with the following improvements:
* Added information on the relevant datasheet(s) and where to get them.
 * Added missing #defines for some other config bytes.
 * Documented all config bytes a bit better.
 * Renamed some #defines to hopefully make their names clearer. 

(closes #38)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-22 11:41:32 +00:00
3ab63e1401 apply patch from Giampiero Giancipoli <gianci@email.it>:
Fixed write_page_write_jedec() in jedec.c. Added a check-reprogram loop
in the same function, to come around the high page write failure rate on
some boards.

This patch includes the changes suggested by Ron to simplify the control
flow.

It also includes trivial changes by me to make flashrom build on newer 
systems (libpci needs libz now). I also made a small type case compile fix
and proper return code handling in one or two places.

Signed-off-by: Giampiero Giancipoli <gianci@email.it>
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-22 00:29:51 +00:00
440d6f9f8a Add support for ASD AE49F2008
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de> (trivial patch)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-21 23:51:08 +00:00
3a998642f5 flashrom: Only write the flash if the image has the same size
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-21 23:48:51 +00:00
9e2019200f Rename SM_ID to SYNCMOS_ID (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-21 15:09:05 +00:00
71d310fa9e Add support for the SyncMOS S29C51001T, S29C51004T, and S29C31004T
flash chips to flashrom (closes: #50).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-21 15:02:27 +00:00
d083e7927e Cosmetic fixes and typos (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-20 20:32:35 +00:00
0eb7424004 Support for the 256K SyncMos S29C51002T flash.
Signed-off-by: Giampiero Giancipoli <gianci@email.it>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-20 20:03:07 +00:00
c22851011f Fix hardcoding of iasl path. iasl is in the user path in the
pmtools packages of upcoming SUSE 10.2, too, so the problem will 
go away. (new package installed on linuxbios.org, too)

See also
http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-19 19:24:06 +00:00
ed7bab8b0d Add missing bracket in comment, and fix whitespace (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-11 18:46:38 +00:00
ca6312010d * fix the automatic build system by compressing payloads if possible
and leaving enough room for a real payload (not /dev/null)

  This is a wonderful example why "uses" sucks.

* add Config-abuild.lb for those boards that dont build with 
  the default settings and a real payload:
  arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326

* if lzma is installed and a real payload is used, try compressing
  it. 

* fix a small bug in "abuild --help"

This patch is acked by me because its due to infrastructural changes only.
Flames welcome.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-10 13:30:28 +00:00
c0defea8b6 Add an include file which contains the register definitions for the
Intel 440BX northbridge (Closes #39).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Richard Smith <smithbone@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-10 09:04:12 +00:00
f7980d8941 Instead of checking the first byte only, the whole part is checked now. This
will detect any improper erase, closes #31
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-07 13:48:46 +00:00
c65113cec7 Fix some code comments of the Intel PIIX4/PIIX4E/PIIX4M code.
Add detailed instructions on how and where to get the datasheet,
its name, and order number (Closes #34).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-07 11:16:21 +00:00
10fd79ae81 Support for VIA VT82C686 in flashrom utility (trivial)
closes #30
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-07 10:22:20 +00:00
918a7cf8e4 Fix bug in 'sed' invocation in abuild, which causes build errors in
certain situations (Closes #22, refs #14).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-06 10:51:15 +00:00
a7aa29b943 Use the canonical name of the vendors/devices and the
same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05 18:50:49 +00:00
bdb50fe40a Add support for Intel PIIX4/PIIX4E/PIIX4M-based mainboards to flashrom.
Tested on real hardware, reading, detecting and writing various chips works.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05 18:26:08 +00:00
a9e273593f Fix a typo in elfboot.c. Closes #27
Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05 12:18:58 +00:00
1549f2a557 Various minor cosmetic changes in the ITE Super I/Os, mostly whitespace
changes and fixing of comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-04 23:19:00 +00:00
faea4c59ab Sorry, this is the last commit I will do this way, but MSI has waited a
long time and I could not get into the tracker. 

These are patches to enable ms9185 support. Abuild passes. 

Signed-off-by: bxshi <bxshi@msik.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-02 16:02:33 +00:00
9c33b7b81e Remove some unneeded #includes from most mainboard.c files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-02 14:11:34 +00:00
a4c56c33ac Adapt GPL license headers to match the current conventions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-01 14:31:00 +00:00
6fb43c85f1 drop unsupported unfinished mainboard Advantech SOM GX DB533-C
Signed-off-by: Richard Smith <smithbone@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-01 14:21:31 +00:00
f28674ec3c Rename some variables from *ITE* to *ite* for consistency reasons (refs #4).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-01 12:52:49 +00:00
700b38a0d5 small tracker test (trivial change). closes #3
fix bug report address
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-28 16:03:37 +00:00
0caddbd4fe Small tracker test (trivial change). closes #3
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-28 16:00:24 +00:00
f044ede246 This change fixes a long-standing bug, whereby we do not set ret for an
un-inited vector, which we should have done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27 18:22:13 +00:00
cf20187079 svn mv src/northbridge/intel/E7520 src/northbridge/intel/e7520
svn mv src/northbridge/intel/E7525 src/northbridge/intel/e7525

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27 11:40:01 +00:00
586470c646 Rename E7520 to e7520, and E7525 to e7525 in the code. The next commit
will then rename the E7520 and E7525 directories respectively.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27 11:38:22 +00:00
e0e1d42527 Fix the CHIP_NAME() entries of all mainboards to have the same format
and (hopefully) the correct canonical name of the vendor and board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27 11:30:27 +00:00
733681583c enhance web page (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Closes #3


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-25 19:08:12 +00:00
3a1405725e support submitting tests to the test system in abuild. initial support.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Closes #3


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-25 19:02:34 +00:00
3d61074108 Rename src/superio/NSC to src/superio/nsc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 23:08:10 +00:00
d86417bfa3 Change all occurences of NSC to nsc in the code. The next commit
will then rename the src/superio/NSC directory to src/superio/nsc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 23:00:42 +00:00
f327e655ce reduce verbosity on OLPC btest boards.
Signed-off-by: Ronald G. Minnich <rminnich@lanl.gov>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>





git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 18:47:29 +00:00
814b458b63 fix leftover typo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 12:46:55 +00:00
6e5b6a82ad fix typo during rename. Subversion would not let
me fix this before committing first.

Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 09:40:21 +00:00
9d6be3ec42 fix naming convention, turn X.
another commit is following
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 09:37:04 +00:00
1d8261d416 rename Iwill to iwill to keep naming scheme consistent
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 09:25:35 +00:00
b216e8fa65 remove DK8HTX, it's an old duplicate version of dk8_htx
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-24 09:23:23 +00:00
107b8feb68 get rid of the border.
Signed-Off-By: stepan@coresystems.de


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-20 22:21:18 +00:00
10d55b47cf Added a README file for LinuxBIOS.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-20 21:50:01 +00:00
c4225c8452 add proper licensing information. thanks to Uwe Hermann.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-19 19:08:00 +00:00
2132f1a605 fix from Uwe Hermann: updated patch to fix a wiki syntax bug in the output...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-19 19:06:28 +00:00
fd845a04a9 add the CAFE IRQ support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-18 16:00:10 +00:00
69fd463a1b add btest mainboard
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-18 15:46:24 +00:00
31101c9201 add the btest mainboard
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-18 15:23:28 +00:00
0a3f60775b add xsl stylesheet for wiki table generation
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-17 20:58:47 +00:00
c1c3fdc79f add ADLO to v2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-14 21:35:30 +00:00
5ed51d1933 * add vt8237 support (Uwe Hermann)
* add more MCP51 support (me)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-14 21:04:49 +00:00
a112bb0bca s2895 failover build
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-13 21:48:38 +00:00
0ab46b9026 return missed
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-13 20:10:09 +00:00
4bb8887ac4 change things that make no sense on ultra40. serial output now works!
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-13 19:58:52 +00:00
c34e3ab71e DK8 HTX with CAR and acpi, and easy support for HTX
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-12 00:58:20 +00:00
d3eabbd77c replace table based crc with computational one. by Ed Swierk.
X-Signed-Off-By: <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-09 22:35:45 +00:00
aa8e3d409f here's a small patch to add support for the SST 49LF020A to flashrom.
by Uwe Hermann <uwe@hermann-uwe.de>
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-07 22:59:03 +00:00
b6a0a9fb8a Tiny patch to show the size of the detected flash part
from Uwe Hermann <uwe@hermann-uwe.de>
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-07 00:23:51 +00:00
f694db9380 Fix flashrom for sst49lf080a and small print bug,
by Roman Kononov <kononov195-lbl@yahoo.com>.
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-07 00:21:13 +00:00
ebafa4df42 Add serial stream payload support from Ed Swierk <eswierk@arastra.com>
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-07 00:13:24 +00:00
197a4a8dbb MEMCLK to DDRXXX
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-06 16:05:14 +00:00
7110f9261f K8_4RANK to QRANK
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05 06:59:56 +00:00
ab9f49d2fa init.o
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05 06:24:21 +00:00
1792b2e801 make ppc happy for console
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-05 00:27:44 +00:00
6d74d76de4 get_bus_cong using sysconf instead
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 23:57:49 +00:00
d95465d08f add missed asl for ht chain
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 23:09:09 +00:00
31ed8983c3 qemu abuild fix
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 22:57:26 +00:00
5f9624d211 CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in
serengeti_cheeatah


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 22:56:21 +00:00
93a5a194c5 failover_failover apc lds
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 21:05:23 +00:00
15b8ea7473 socket 939
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 21:04:49 +00:00
8d22a5dc69 amdk8_sysconf
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 21:00:01 +00:00
d4b278c02c AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04 20:46:15 +00:00
2e3757d11c rename abuild.sh to abuild.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-25 09:15:52 +00:00
e3315c1fc2 clean up epia targets
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-24 23:02:26 +00:00
984371554b add irq for keyboard and mouse
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-21 20:55:58 +00:00
0bece04105 abuild manpage and other fixes from Uwe Hermann. Thank you!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-21 13:09:22 +00:00
2ad85dbc65 Lots of lx fixes. CLeanup mainly. THings now build
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20 16:39:30 +00:00
e8bfbb387c This driver is a mistake, removing it.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20 16:32:59 +00:00
efba85f00e commit moire changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 19:30:11 +00:00
21acfcb0d5 add target
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 17:38:57 +00:00
5f23b6cd7d add the msm800srv ; put the usb in the right place.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 17:37:32 +00:00
a341ee2646 put this in the right place.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 16:44:14 +00:00
d9560dd88c resize OLPC flash
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 04:03:40 +00:00
a3cf8a28e9 Fix the name for buildrom script
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 03:47:35 +00:00
830a79eeab add an OLPC target for qemu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19 03:43:30 +00:00
4d6810c60c add the _lx flavor of the 5536. This will later be merged into the
cs5536, but I don't want to mess up the OLPC, and we really need the lx
support NOW.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18 22:52:24 +00:00
2cf779d8d1 fix old bug in the src/devices/pci_device.c
add devices for the lx and artecgroup/dbe61
point artecgroup at cs5536_lx as it is so different. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18 22:50:51 +00:00
0740c31cff A fix for hynix dram problems seen at 366/244
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-18 04:23:23 +00:00
50f84bdea8 run preprocessor on hand-crafted config files in abuild, too
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-15 23:14:37 +00:00
7fe2b7cd5c add option to build autobuild images with real payloads
instead of /dev/null. 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-15 17:00:11 +00:00
46bcaa303b fix variable name for ts5300
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-15 14:53:55 +00:00
b2f98af71e fix stupid missing " type
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 20:08:10 +00:00
53f486a3ea fix some really yuck stuff.
now things might work.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 16:31:14 +00:00
cba07dd682 additions and mods for lzma.
Signed-off-by: Carl-Daniel Hailfinger
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14 15:12:36 +00:00
7d9441276f changes for the lx and artecgroup mobo
Signed-off-by: Indrek Kruusa
Approved-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 21:59:09 +00:00
5c16ebde91 new presents from artec group :-)
Signed-off-by:  Indrek Kruusa   



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 21:25:20 +00:00
b9c100bdb7 add file for dcon support
signed-off-by: Jordan Crouse
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 19:30:15 +00:00
e361efd7d7 Add DCON support.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 19:29:31 +00:00
66c335b8cc fix cardbus interrups (signed off by Nick Barker)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 07:55:23 +00:00
613cb6171f - fix irq routing for epia-mii cardbus slot. (signed off by Nick Barker)
- some minor cleanups


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 07:52:41 +00:00
9cf0050d68 Slow down the clock, per Tom Sylla
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 04:33:07 +00:00
9cf642bad3 fix for qemu northbridge, from Ed Swierk
Signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 04:12:35 +00:00
aefa3d74f9 warm boot patch from richard smith.
signed-off-by: Ronald G. Minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 01:57:47 +00:00
5ef4c598fb Fix the irq_tables
signed-off-by: ronald g. minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 01:14:45 +00:00
cdb89be9e8 mods for qemu, these build
signed-off-by: ronald g. minnich


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13 01:10:08 +00:00
94b17c6a3c add romcc manpage from Uwe Hermann
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-08 17:44:42 +00:00
4209 changed files with 439130 additions and 140683 deletions

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@ -1,593 +0,0 @@
This HOWTO contains instructions for using LinuxBIOSv2 on the VIA EPIA-M and MII
mini-itx based motherboards.
Version 1.0 initial write for LinuxBIOSv2 by Nick Barker
Using materials and inspiration from
- EPIA HOWTO for freebios/linuxbios by Mark Wilkinson
- Based on the K7SEM HOWTO by Brenden Bixler,
- which is based on the Sis 630 HOWTO by Ron Minnich.
- Getting Started with freebios2 - a mail posting by Jay Miller
Unfortunately, there is a step in this HOWTO that could be hazardous. The
hazards include (but are not limited to)
1) destroying your motherboard
2) hurting yourself
3) killing yourself
Because of these hazards, you must take full responsibility if you
decide to install LinuxBIOSv2 following these procedures. Neither the
author of this HOWTO or any organisation or individual associated with
the LinuxBIOSv2 project can be held responsible for any adverse consequences
of your attempt to follow these procedures.
WARNING: We assume you've built kernels, know how to open up your PC,
and how to yank the flash part out while power is on and put in a
different part. There is NO WARRANTY, express or implied, with this
software. In fact, if you don't know what you're doing, and you get
careless, you're going to end up with a nice paperweight instead of a
motherboard, an emergency room bill, or a funeral service.
YOU HAVE BEEN WARNED.
Additional information available at: http://www.linuxbios.org/
Linux distribution: Most modern distributions are supported.
Other software notes: You MUST have 'as' version 2.9.5 or later.
You MUST have 'gcc' version other than 2.96.
Pre-requisites
--------------
Before you start there are a few things which you need to arrange:
Since you are going to be re-programming the flash rom on the mainboard, and
it is likely that you first few attempts / images will not be right, then
you need a way of restoring a known working bios onto a board which is otherwise
dead.
Recommended: you might want to get a Bios Saviour (RD1-PL) - this is
a handy little piggy-back flash chip that saves you destroying the original
flash image. This howto assumes that you have this device, though other methods
and devices exist for programming flash roms.
LinuxBIOSv2 sends debugging output through the first serial port. You might want
to arrange a null modem serial cable for connecting this serial port to a
second computer running a terminal emulation program. I use 'microcom' which
is simple and allows all output to be captured into a file for later analysis.
The port is set up to use 115200 baud, 8bit, No parity, 1 stop bit.
Under LinuxBIOSv2 you have a choice of 'payloads'. The payload is the program
which LinuxBIOSv2 hands over to once it has finished initialising everything
on the mainboard at boot time. The payload is included in the flash rom along
with LinuxBIOSv2, and usually its function is to locate and load the operating
system. The 2 most common payloads are FILO, for booting Linux off an IDE
disk, and Etherboot for booting a diskless workstation accross a network.
This howto assumes the use of FILO.
A vga bios image. LinuxBIOS2v2 uses the vga bios of the original Via BIOS to
initialise the vga. It is not directly downloadable, but you can capture it from
a system running with the original bios, so you might as well capture it now:
dd if=/dev/mem of=/video.bios.bin \
bs=1 count=65536 skip=790528
Getting Going
-------------
The steps for loading LinuxBIOSv2 are simple:
1) Get Linux installed on your machine.
2) Download and install LinuxBIOSv2 sources.
3) Understand how to flash your rom.
4) Download, Configure and build the FILO payload
5) Configure and build LinuxBIOSv2.
6) Burn the LinuxBIOSv2 image to the flash.
7) Reset the machine -- did it work?
Options Once it has booted
i) Speeding up the boot
ii) Enhancing ACPI support
iii) On EPIA-MII, booting the computer from on-board compact flash
Step 1)
Get Linux installed on your LinuxBIOSv2 machine.
Don't forget to note which partition is / (/dev/hda3 etc.)
Step 2)
Grab the LinuxBIOSv2 source.
cd to the directory you want the source tree to be.
Note: this will create a sub directory called LinuxBIOSv2 which contains
the LinuxBIOSv2 source code
Download the latest code for LinuxBIOSv2 from the downloads page at
http://www.linuxbios.org
having expanded the tarball, cd into the LinuxBIOSv2 directory and browse around.
The top level directory includes:
'src' - where all of the source files for LinuxBIOSv2 are located.
'targets' - where all of the platform specific configuration files
for each platform supported by LinuxBIOSv2 are kept, and
where the build files and build process occur.
'util' - where various utilities required for the build process
and debugging are kept.
Hereafter, this howto refers to directory locations relative to these directories,
unless an absolute pathlist is given.
Step 3)
Whilst getting LinuxBIOSv2 going on your EPIA-M, you are almost
certainly going to be re-programming the flash rom several times, and
there is a very high probability that at one of these stages you will
get a flash rom that fails to boot your mainboard into Linux.
Before we proceed any further, it is absolutley vital that you have
worked out how to program the flash chip, and how you are going to
get back to your original bios when things go wrong. Otherwise you
will end up with a very expensive paper weight as described earlier.
You can use a professional Data I/O burner, or you can be foolhardy
and simply re-program the flash part of a running machine. However
whilst getting going a BIOS SAVIOUR RD1-PL is a very inexpensive
but effective device for ensuring that you always have a working
BIOS to hand.
The bios saviour is a little device which plugs into the flash rom
socket of the motherboard, and the original flash rom then plugs into
the bios saviour. The bios saviour includes a second flash rom chip,
and either of these chips can be selected as the active chip by a
simple supplied electrical switch mounted on flying leads. Make
sure that this switch is clearly visible, so that you know which
chip you are booting from, and which chip you are about to re-program.
Decide which chip you are going to use for LinuxBIOSv2, and which chip
you are going to keep the original working bios in, and mark them
clearly on this switch.
In the 'util/flash_and_burn' directory is the source for the 'flash_rom'
utility, which is great for re-programming the flash chips on the
EPIA-M / MII. Once you have built this utility:
Make sure that it can detect both flash chips on the bios saviour:
with switch set to chip 1 run 'flash_rom'
flash rom should search through a list of known flash rom
device types until it finds the type of the original chip
from your EPIA-M, and report what it has found.
with the switch set to chip 2, run 'flash_rom' again and confirm
that it can 'see' the second flash chip.
If your are lucky, the actual part number of the 2 chips may
be different, which you can use just prior to re-programming
a chip to make sure you are programming the right chip.
Make sure that you can read / write and verify a flash chip:
with switch set to 1 (original BIOS) run
'flash_rom -r original.rom'
this should read the contents of the original bios into the
file original.rom
confirm that the newly read file matches the original bios
'flash_rom -v original.rom'
set the switch to 2
confirm if you can that flash_rom 'sees' the second chip
'flash_rom' - and look for the detected device type
write the known good bios to the second chip with
'flash_rom -w original.bios'
verify that it has written correctly
'flash_rom -v original.rom'
with switch left at position 2, reboot the machine and make
sure that it comes up corectly. If it does then you now have
a working flash programming environment. If it does not, then
set the switch back to 1, reboot the machine, and investigate
further.
Step 4)
Download FILO from http://felixx.tsn.or.jp/~ts1/filo, and expand
In the FILO source directory, type 'make'
The first invocation of make builds the default Config file, which
should be edited to meet your needs. In particular look at the line:
"AUTOBOOT_FILE ...."
and make sure that it looks sensible for your setup. The line
AUTOBOOT_FILE "hda1:/vmlinuz root=/dev/hda2 console=ttyS0,115200"
reads as:
- find a linux os image on device hda partion 1 called vmlinuz,
- load this image
- execute the image passing kernel command line parameters of:
"root=/dev/hda2 console=ttyS0,115200"
after editing Config, type 'make' again, and this will build the file
'filo.elf' which is the payload we will be using.
Copy this file to somewhere which the LinuxBIOSv2 makefile can easily
find it. I just tend to keep it in the root directory though I'm sure
others will condem me for that practise:
'cp filo.elf /'
Make sure that you have compiled a kernel bzImage, and copied it to
the file location you identified in the FILO Config file.
Step 5)
The next step is to create the build environment for the epia-m. This
step creates the appropriate makefiles and build directories for the
epia-m.
'cd targets'
'./buildtarget via/epia-m'
This step will create a subdirectory in the targets/via/epia-m
directory called epia-m, which is the build directory for LinuxBIOSv2.
The main configuration file for the epia-m is in
'targets/via/epia-m/Config.lb'
If you need to make any changes to the configuration, for example you wish to
locate filo.elf in a place other than '/filo.elf', or during the more advanced
steps of this HOWTO, then these changes are made to this file.
You need to re-run the './buildtartegt via/epia-m' after any such change.
The directory 'targets/via/epia-m' contains other sample Config.lb files, any
of which can be copied through to Config.lb in order to become the current
configuration.
Once you have your Config.lb set up to your needs, and the build environment
created with './buildtarget', it is time to build a rom image.
Change directory into the build directory 'targets/via/epia-m/epia-m'
The configuration as set up by the buildtarget process will create a LinuxBIOS
which is exactly 196608 bytes long, which is exactly 64K bytes short of what
needs to go into the 256K flash rom. The other 64K is for your vga bios
which is simply merged with the linuxbios image. The easiest way to make this
happen is to edit the Makefile and change the line
cat fallback/linuxbios.rom > linuxbios.rom
to
cat /video.bios.bin fallback/linuxbios.rom >linuxbios.rom
Note: the above order of merging the files together is critical
You will need to remember to make this change every time after you have run
the buildtarget program.
Type 'make', and wait for the build process to complete.
If all went well, then you should find a file 'linuxbios.rom' in your
current directory. Check that it is 262144 bytes long - i.e. exactly the right
size for the flash rom chip in your EPIA-M / MII.
Step 6)
NOTE: BE ADVISED THAT THIS STEP CAN KILL YOUR MOTHERBOARD !
IF YOU DO NOT HAVE A MEANS OF RECOVERING FROM FLASHING YOUR BIOS,
YOU MAY/WILL BE LEFT WITH A DEAD MACHINE.
Assuming that you are using a Bios Saviour, make sure that the switch is set
to the position for your LinuxBIOSv2 image.
Type 'flash_rom' to make sure it can see the flash chip, and verify its type if
possible.
Only once you are happy that you are about to re-programme the desired chip, type
'flash_rom -w linuxbios.rom', and wait the few seconds it takes to program it.
Once it has finished, verify that the chip was re-rogrammed correctly - type
'flash_rom -v linuxbios.rom'
Step 7)
Power cycle the machine. LinuxBIOSv2 should come up in a few seconds.
With a connection to the serial port set at 115200, you should see LinuxBIOSv2
come up, launch FILO, and if you have a timeout set in FILO, then it may be
waiting for you to confirm its boot command line.
As long as you have this command line set up correctly, and an os image in the
right place, then FILO should proceed to boot into your Linux os.
If you do, CONGRATULATIONS ! It WORKED ! Pat yourself on the back,
why not try the optional steps now ?
If you don't, time to start capturing the output of the serial port
and talking to the linuxbios mailing list.
Optional steps - for use only if step 7 was successfull.
OK so now we have a BIOS which boots your computer fully into the operating system, and
depending upon your needs that may be all that you want. However LinuxBIOSv2 has a few more
tricks up its sleeve should you find yourself hungry for more.
Speeding up the boot
--------------------
Linuxbios sends its debugging output to the first serial port and, depending upon the amount of debug
output selected, can be the limiting factor in the speed with which it boots your computer - regardless
of whether you have anything attached to the serial port.
Linuxbios uses the notion of debug levels to control what is sent to the serial port. These levels
range from 0 to 9 with 0 being the least verbose and 9 being the most verbose.
These levels are defined in the Config.lb file described earlier. To reduce the output set:
option MAXIMUM_CONSOLE_LOGLEVEL=8
option DEFAULT_CONSOLE_LOGLEVEL=8
to lower values.
Next you will have to run 'buildtarget' again to propagate the effects of the config change.
Then edit your Makefile again to include your video bios in the final merging.
Then run 'make clean' followed by 'make'.
Advanced ACPI
-------------
LinuxBIOSv2 now supports ACPI on the epia-m and epia-m II. In particular the interrupt
processing in Linux can be done through ACPI, and crude power management support
is provided. This includes software power off, and power management events from the
power button.
It is possible to enhance this behaviour to provide the full capabilities of the
original BIOS, which includes different sleep levels and wake from these levels
upon certain events. This is achieved by using a 'grabbed' copy of the ACPI
Differentiated System Descriptor Table or DSDT from the original BIOS.
For copyright reasons this table cannot be included with the source distribution
of LinuxBIOSv2.
You MUST have 'iasl' - Intel's ACPI Asl compiler for Unix/Linux -
http://developer.intel.com/technology/iapc/acpi/downloads.htm.
To replace the LinuxBIOSv2 DSDT with the grabbed one from the original BIOS:
- Start the computer using the original BIOS, and make sure that you
have ACPI set up in the kernel that you are running
- Grab the DSDT table - 'cat /proc/acpi/dsdt >dsdt.aml'
- Convert to asl code - 'iasl -d dsdt.aml' (creates dsdt.dsl)
- Convert it to a C hex table - 'iasl -tc dsdt.dsl' (creates dsdt.hex)
- Replace the file 'src/mainboard/via/epia-m/dsdt.c with dsdt.hex
Now re-build LinuxBIOSv2, re-program the flash and power cycle.
If you wish to return to the LinuxBIOSv2 DSDT, then the original file dsdt.asl can be converted
into a C hex file using 'iasl -tc dsdt.asl'
Boot from Onboard Compact Flash (MII only)
------------------------------------------
LinuxBIOSv2 now supports the onboard compact flash on the MII as an IDE drive,
and it is possible to boot directly from this drive using the following steps.
The first step is to get Filo or whatever payload you are using to recognise
and use this device.
In order that the pcmcia subsystem of the Linux kernel can correctly configure
the device later on in the boot process the CF is set up with its I/O
registers in a contiguous block of 16 bytes at 0x1e0 through 0x1ef. Unfortunately
this is not a standard IDE address which is why we need to 'fix' filo to use it.
(Actually it is half of the address range used by IDE4, and so we need to
be careful to tell the kernel not to probe that address - more on that later).
The first step is to change the filo Config file.
1) Comment out SUPPORT_PCI=1. This line instructs filo to search for PCI based IDE
adapters only, and the CF is not attached to a PCI based IDE controller.
2) Add the following two lines somewhere in the Config file:
IDE2_CMD = 0x1e0
IDE2_CNTRL =0x1ec
The second step is to modify the file drivers/ide.c in the filo source directory.
Find the function 'find_ide_controller_compat' and change it to look like
static int find_ide_controller_compat(struct controller *ctrl, int index)
{
if (index >= IDE_MAX_CONTROLLERS)
return -1;
#ifdef IDE2_CMD
if(index == 2){
ctrl->cmd_base = IDE2_CMD;
ctrl->ctrl_base = IDE2_CNTRL;
return 0;
}
#endif
ctrl->cmd_base = ide_base[index];
ctrl->ctrl_base = ide_base[index] + IDE_REG_EXTENDED_OFFSET;
return 0;
}
Filo will now recognise the CF as the first device on the third IDE controller
(i.e. ide2), and can be referred to as 'hde'
The next step is to create an initrd file for your Linux kernel. What? Why?
The CF socket on your MII is hardwired to the PCMCIA controller and for all intents
and purposes it is a PCMCIA device. This means that once Linux boots it will be under
the control of the pcmcia manager. Now according to the pcmcia-utils documentation,
the pcmcia manager is intended to control and configure devices on an already
running system. Yet if we need the CF to be the root device, it needs to be mounted
very early on in the boot sequence, before the stage where pcmcia devices would normally
be configured. The answer is to use an initrd file to get the pcmcia manager running early
for the CF. If you are unfamiliar with initrd then 'man initrd' will give you more background.
The easiest way to create an initrd is to use the script 'mkcfinitrd' which is at the bottom
of this howto. This is a tailored version of the 'pcinitrd' script from the pcmcia-utils package.
Make sure that 'ash' is available on your system as this is the tiny shell programme used during
the initrd phase of booting.
It is worth mounting the initrd generated, and looking over it to make sure that
it contains all of the modules necessary to load and initialise the CF. It does not
need drivers for whatever you use in the pcmcia socket, as that can be initialised
later on in the boot process as before.
Finally gzip the file created, and move it alongside your kernel.
Next adjust your FILO command line to pick things up from the CF. My linux command
line in filo looks like:
AUTOBOOT_FILE = "hde:/vmlinuz initrd=hde:/initrd.gz root=/dev/hde console=tty0 ide4=noprobe"
The ide4=noprobe option is required to stop the kernel from probing the address used
by the CF. As this address is half that used as the standard address for a fifth (i.e. ide4)
controller, the kernel hangs whilst trying to initialise this device if this option
is not given.
Finally make sure that you have copied the necessary files onto your CF, and re-boot
your computer.
******************* mkcfinitrd script **************************************
#!/bin/sh
#
# Utility for constructing CF initrd for Epia-MII CF Boot
#
# Copyright (C) 2005 Nick Barker -- nick.barker9@btinternet.com
#
# Based on pcinitrd
# Copyright (C) 1999 David A. Hinds -- dahinds@users.sourceforge.net
SIZE=2400
MODULES="pcmcia/pcmcia_core.o pcmcia/ds.o pcmcia/yenta_socket.o"
BLK="kernel/drivers/ide/legacy/ide-cs.o"
KERNEL=`uname -r`
MODDIR=/lib/modules/$KERNEL
BIN="bin/mount bin/umount sbin/insmod sbin/cardmgr"
LIB=`ls /lib/libc.so.? | sort | tail -1`
ETC="/etc/ld.so.cache /etc/pcmcia/config /etc/pcmcia/config.opts"
DEV="/dev/console /dev/null /dev/ram /dev/tty1 /dev/tty2 /dev/tty3 /dev/tty4"
MNT=/tmp/initrd.mnt
# name of the initrd file to make
TARGET=/tmp/initrd
fail()
{
umount $MNT
rmdir $MNT
exit 1
}
trap fail SIGTERM SIGINT
strip_cp()
{
if [ -d $3 ] ; then
DEST=$3/`basename $2`
else
DEST=$3
fi
strip $1 --verbose -o $DEST $2 | sed -e 's/([^ ]*)//g' || fail
}
mkdir --verbose $MNT || exit 1
echo "Creating filesystem on $TARGET"
if [ -b $TARGET ] ; then
rm $TARGET || fail
fi
dd if=$ROOT/dev/zero of=$TARGET bs=1k count=$SIZE
echo "y" | mke2fs $TARGET $SIZE >/dev/null || fail
mount --verbose -t ext2 -o loop $TARGET $MNT || fail
rm -rf $MNT/lost+found
echo "Creating Directories on $TARGET"
for DIR in bin dev etc lib proc tmp mnt ; do
mkdir --verbose $MNT/$DIR || fail
done
for DIR in block misc fs net pcmcia ; do
mkdir --verbose $MNT/lib/$DIR || fail
done
echo "Copying Files to $TARGET"
for F in $DEV ; do
cp -a --verbose /$F $MNT/dev || fail
done
if [ -e /dev/systty ] ; then
cp -a --verbose /dev/systty $MNT/dev || fail
fi
for F in $BIN ; do
strip_cp --strip-all /$F $MNT/bin
done
strip_cp --strip-all /bin/ash $MNT/bin/sh
for F in $LIB ; do
strip_cp --strip-debug /$F $MNT/lib
done
cp --verbose /lib/ld-linux.so.? $MNT/lib || fail
for F in $ETC ; do
cp --verbose /$F $MNT/etc || fail
done
for F in scsi network ftl ide memory serial ; do
touch $MNT/etc/$F ; chmod +x $MNT/etc/$F
done
for MOD in $MODULES ; do
strip_cp --strip-debug $MODDIR/$MOD $MNT/lib/$MOD
done
strip_cp --strip-debug $MODDIR/$BLK $MNT/lib/block/ide-cs.o
echo "Creating linuxrc startup script"
cat > $MNT/linuxrc <<- 'EOF'
#!/bin/sh
mount -t proc /proc /proc
echo ""
echo "==== initrd: starting PCMCIA services ===="
echo ""
PC=/lib/pcmcia
insmod $PC/pcmcia_core.o
insmod $PC/yenta_socket.o
insmod $PC/ds.o
insmod /lib/block/ide-cs.o
if [ "$DEBUG" != "" ] ; then V=-v ; fi
cardmgr $V -q -o -c /etc -m /lib -s /tmp/stab -p /tmp/pid
umount /proc
echo ""
if [ "$DEBUG" != "" ] ; then
/bin/sh < /dev/console
fi
EOF
chmod +x $MNT/linuxrc
df -P $MNT | awk '/tmp/ { printf "%dK/%dK used\n",$3,$2 }'
umount $VERBOSE $MNT
rmdir $MNT
echo "Finished $TARGET"
echo "Now gzip $TARGET to create final initrd.gz"
exit 0
*************************** end mkcfinitrd ***********************************

323
Makefile Normal file
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@ -0,0 +1,323 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
## Copyright (C) 2009-2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile)))
include .xcompile
export top := $(shell pwd)
export src := $(top)/src
export srck := $(top)/util/kconfig
export obj ?= $(top)/build
export objk := $(obj)/util/kconfig
export sconfig := $(top)/util/sconfig
export yapps2_py := $(sconfig)/yapps2.py
export config_g := $(sconfig)/config.g
export KERNELVERSION := 4.0
export KCONFIG_AUTOHEADER := $(obj)/config.h
export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
CONFIG_SHELL := sh
KBUILD_DEFCONFIG := configs/defconfig
UNAME_RELEASE := $(shell uname -r)
HAVE_DOTCONFIG := $(wildcard .config)
MAKEFLAGS += -rR --no-print-directory
# Make is silent per default, but 'make V=1' will show all compiler calls.
Q:=@
ifneq ($(V),1)
ifneq ($(Q),)
.SILENT:
endif
endif
CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
HOSTCC = gcc
HOSTCXX = g++
HOSTCFLAGS := -I$(srck) -I$(objk) -g
HOSTCXXFLAGS := -I$(srck) -I$(objk)
LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
DESTDIR = /opt
DOXYGEN := doxygen
DOXYGEN_OUTPUT_DIR := doxygen
ifeq ($(strip $(HAVE_DOTCONFIG)),)
all: config
else
include $(top)/.config
ARCHDIR-$(CONFIG_ARCH_X86) := i386
ARCHDIR-$(CONFIG_ARCH_POWERPC) := ppc
MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_DIR))
export MAINBOARDDIR
PLATFORM-y += src/arch/$(ARCHDIR-y) src/cpu src/mainboard/$(MAINBOARDDIR)
TARGETS-y :=
BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers util/x86emu
BUILD-y += util/cbfstool
BUILD-$(CONFIG_ARCH_X86) += src/pc80
ifneq ($(CONFIG_LOCALVERSION),"")
COREBOOT_EXTRA_VERSION := -$(shell echo $(CONFIG_LOCALVERSION))
endif
# The primary target needs to be here before we include the
# other files
all: coreboot
#######################################################################
# Build the tools
CBFSTOOL:=$(obj)/util/cbfstool/cbfstool
$(obj)/mainboard/$(MAINBOARDDIR)/config.py: $(yapps2_py) $(config_g)
mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
python $(yapps2_py) $(config_g) $(obj)/mainboard/$(MAINBOARDDIR)/config.py
# needed objects that every mainboard uses
# Creation of these is architecture and mainboard independent
$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(obj)/mainboard/$(MAINBOARDDIR)/config.py
mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
(cd $(obj)/mainboard/$(MAINBOARDDIR) ; PYTHONPATH=$(top)/util/sconfig export PYTHONPATH; python config.py $(MAINBOARDDIR) $(top) $(obj)/mainboard/$(MAINBOARDDIR))
$(obj)/mainboard/$(MAINBOARDDIR)/static.o: $(obj)/mainboard/$(MAINBOARDDIR)/static.c
#
objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o
initobjs:=
drivers:=
smmobjs:=
crt0s:=
ldscripts:=
types:=obj initobj driver smmobj
includemakefiles=$(foreach type,$(2), $(eval $(type)-y:=)) $(eval subdirs-y:=) $(eval include $(1)) $(if $(strip $(3)),$(foreach type,$(2),$(eval $(type)s+=$$(patsubst src/%,$(obj)/%,$$(addprefix $(dir $(1)),$$($(type)-y)))))) $(eval subdirs+=$$(subst $(PWD)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
evaluate_subdirs=$(eval cursubdirs:=$(subdirs)) $(eval subdirs:=) $(foreach dir,$(cursubdirs),$(eval $(call includemakefiles,$(dir)/Makefile.inc,$(types),$(1)))) $(if $(subdirs),$(eval $(call evaluate_subdirs, $(1))))
# collect all object files eligible for building
subdirs:=$(PLATFORM-y) $(BUILD-y)
$(eval $(call evaluate_subdirs, modify))
allobjs:=$(foreach var, $(addsuffix s,$(types)), $($(var)))
alldirs:=$(sort $(abspath $(dir $(allobjs))))
source_with_ext=$(patsubst $(obj)/%.o,src/%.$(1),$(allobjs))
allsrc=$(wildcard $(call source_with_ext,c) $(call source_with_ext,S))
POST_EVALUATION:=y
# fetch rules (protected in POST_EVALUATION) that rely on the variables filled above
subdirs:=$(PLATFORM-y) $(BUILD-y)
$(eval $(call evaluate_subdirs))
define objs_dsl_template
$(obj)/$(1)%.o: src/$(1)%.asl
@printf " IASL $$(subst $$(shell pwd)/,,$$(@))\n"
$(CPP) -D__ACPI__ -P $(CPPFLAGS) -include $(obj)/config.h -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
iasl -p $$(basename $$@) -tc $$(basename $$@).asl
mv $$(basename $$@).hex $$(basename $$@).c
$(CC) -m32 $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$@).c
endef
define objs_c_template
$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
endef
define objs_S_template
$(obj)/$(1)%.o: src/$(1)%.S $(obj)/build.h
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
endef
define initobjs_c_template
$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
endef
define initobjs_S_template
$(obj)/$(1)%.o: src/$(1)%.S $(obj)/build.h
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
endef
define drivers_c_template
$(obj)/$(1)%.o: src/$(1)%.c $(obj)/build.h
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
endef
define drivers_S_template
$(obj)/$(1)%.o: src/$(1)%.S
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
endef
define smmobjs_c_template
$(obj)/$(1)%.o: src/$(1)%.c
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
endef
define smmobjs_S_template
$(obj)/$(1)%.o: src/$(1)%.S
@printf " CC $$(subst $$(obj)/,,$$(@))\n"
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
endef
usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
$(eval $(call usetemplate,objs,dsl))
$(eval $(call usetemplate,objs,c))
$(eval $(call usetemplate,objs,S))
$(eval $(call usetemplate,initobjs,c))
$(eval $(call usetemplate,initobjs,S))
$(eval $(call usetemplate,drivers,c))
$(eval $(call usetemplate,drivers,S))
$(eval $(call usetemplate,smmobjs,c))
$(eval $(call usetemplate,smmobjs,S))
printall:
@echo objs:=$(objs)
@echo initobjs:=$(initobjs)
@echo drivers:=$(drivers)
@echo smmobjs:=$(smmobjs)
@echo alldirs:=$(alldirs)
@echo allsrc=$(allsrc)
OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y))
INCLUDES := -I$(top)/src -I$(top)/src/include -I$(obj) -I$(top)/src/arch/$(ARCHDIR-y)/include
INCLUDES += -I$(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
INCLUDES += -I$(top)/util/x86emu/include
INCLUDES += -include $(obj)/build.h
try-run= $(shell set -e; \
TMP=".$$$$.tmp"; \
if ($(1)) > /dev/null 2>&1; \
then echo "$(2)"; \
else echo "$(3)"; \
fi; rm -rf "$$TMP")
cc-option= $(call try-run,\
$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
STACKPROTECT += $(call cc-option, -fno-stack-protector,)
CFLAGS = $(STACKPROTECT) $(INCLUDES) -Os -nostdinc
CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
CFLAGS += -Wstrict-aliasing -Wshadow
ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
CFLAGS += -Werror
endif
CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CBFS_COMPRESS_FLAG:=l
CBFS_PAYLOAD_COMPRESS_FLAG:=
ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
CBFS_PAYLOAD_COMPRESS_FLAG:=l
endif
coreboot: prepare prepare2 $(obj)/coreboot.rom
endif
prepare:
mkdir -p $(obj)
mkdir -p $(obj)/util/kconfig/lxdialog
test -n "$(alldirs)" && mkdir -p $(alldirs) || true
prepare2: $(obj)/build.h
$(obj)/build.h:
@printf " GEN build.h\n"
rm -f $(obj)/build.h
printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.ht
printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht
printf "\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILE_BY \"$(subst \,@,$(shell PATH=$$PATH:/usr/ucb whoami))\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname -s)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.ht
printf "#include \"config.h\"\n" >> $(obj)/build.ht
mv $(obj)/build.ht $(obj)/build.h
doxy: doxygen
doxygen:
$(DOXYGEN) Doxyfile
doxyclean: doxygen-clean
doxygen-clean:
rm -rf $(DOXYGEN_OUTPUT_DIR)
clean: doxygen-clean
rm -f $(allobjs) $(obj)/coreboot* .xcompile
rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.*
rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
rmdir -p $(alldirs) 2>/dev/null >/dev/null || true
$(MAKE) -C util/sconfig clean
distclean: clean
rm -rf $(obj)
rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
update:
dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
# This include must come _before_ the pattern rules below!
# Order _does_ matter for pattern rules.
include util/kconfig/Makefile
$(obj)/ldoptions: $(obj)/config.h
awk '/^#define ([^"])* ([^"])*$$/ {gsub("\\r","",$$3); print $$2 " = " $$3 ";";}' $< > $@
_OS=$(shell uname -s |cut -c-7)
STACK=
ifeq ($(_OS),MINGW32)
STACK=-Wl,--stack,16384000
endif
ifeq ($(_OS),CYGWIN_)
STACK=-Wl,--stack,16384000
endif
$(obj)/romcc: $(top)/util/romcc/romcc.c
@printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n"
$(HOSTCC) -g -O2 $(STACK) -Wall -o $@ $<
.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot

68
NEWS
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@ -1,68 +0,0 @@
- 2.0.0
- this NEWS file is neglected in favor of the svn commit logs.
See http://snapshots.linuxbios.org/
- 1.1.8
- Store everything in arch
- 1.1.7
- The configuration language has been cleaned up. No more link keyword.
- Everything is now in the device tree.
- The static and dynamic device trees have been unified
- Support for setting the pci subsystem vendor and pci subsystem device has been added.
- 64bit resource support
- Generic smbus support
- 1.1.6
- pnp/superio devices are now handled cleanly with very little code
- Initial support for finding x86 BIST errors
- static resource assignments can now be specified in Config.lb
- special VGA I/O decode now should work
- added generic PCI error reporting enables
- build_opt_tbl now generates a header that allows cmos settings to
be read from romcc compiled code.
- split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED
- romcc now gracesfully handles function pointers instead of dying mysteriously
- First regression test in amdk8/raminit_test
- 1.1.5
- O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
- 1.1.4
Major restructuring of hypertransport handling.
Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
Updates to hard_reset handling when resetting because of the need to change hypertransport link
speeds and widths.
(a) No longer assume the boot is good just because we get to a hard reset point.
(b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
boot counter.
Updates to arima/hdama mptable so it tracks the new bus numbers
- 1.1.3
Major update of the dyanmic device tree to so it can handle
* subtractive resources
* merging with the static device tree
* more device types than just pci
- 1.1.2
Add back in the hard_reset method from freebios1 this allows generic
code to reset the box.
Update the hypertransport setup code to automatically optimize
hypertransport link widths and frequencies, and to call hard_reset
if necessary for the changes to go into effect.
- 1.1.1
Updates to the new configuration system so it works more reliably
Removed a bunch of unused configuration variables
Removed a bunch of unused assembly code
- 1.1.0
A whole bunch of random ppc and opteron work we never put a good label on
- 1.1.0
Intial development release of LinuxBIOS.
Everything is thrown overboard and will be reincluded as necessary so we can
get rid of the legacy baggage. Since LinuxBIOS was started we have developed
some better techniques for some things, but we still hang on to the old ways
because some ports that we want not to break depend on them. So we preserve
them by preserve the 1.0.x series and keeping only the best practices for
the 1.1.x series. When there is a stable port this code base will
become LinuxBIOS 2.0.x and the core will become frozen.

91
README Normal file
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@ -0,0 +1,91 @@
-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------
coreboot is a Free Software project aimed at replacing the proprietary
BIOS you can find in most of today's computers.
It performs just a little bit of hardware initialization and then executes
one of many possible payloads, e.g. a Linux kernel or a bootloader.
Payloads
--------
After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.
See http://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
------------------
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
* http://www.coreboot.org/Supported_Motherboards
* http://www.coreboot.org/Supported_Chipsets_and_Devices
Build Requirements
------------------
* gcc / g++
* make
* python
* perl
Optional:
* doxygen (for generating/viewing documentation)
* iasl (for targets with ACPI support)
* gdb (for better debugging facilities on some targets)
* ncurses (for 'make menuconfig')
Building coreboot
-----------------
Please consult http://www.coreboot.org/Documentation for details.
Testing coreboot Without Modifying Your Hardware
-------------------------------------------------
If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.
Please see http://www.coreboot.org/QEMU for details.
Website and Mailing List
------------------------
Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:
http://www.coreboot.org
You can contact us directly on the coreboot mailing list:
http://www.coreboot.org/Mailinglist
Copyright and License
---------------------
The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files (mostly those derived from the Linux kernel) are licensed under
the "GPL, version 2". For some parts, which were derived from other projects,
other (GPL-compatible) licenses may apply. Please check the individual
source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.

File diff suppressed because it is too large Load Diff

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documentation/Kconfig.tex Normal file
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\documentclass[10pt,letterpaper]{article}
\usepackage[latin1]{inputenc}
\usepackage{amsmath}
\usepackage{amsfonts}
\usepackage{amssymb}
\author{Ron Minnich}
\title{Kconfig usage in coreboot v2}
\begin{document}
\section{Introduction}
This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
\section{Kconfig variations}
Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
For variables set by the user, see src/console/Kconfig.
For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent.
Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
\section{Makefile and Makefile.inc}
There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
Make is not recursive. There is only one make process.
\subsection{subdirs usage}
Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
We define the common rules for which variation to use below.
\subsection{object file specification}
There are several different types of objects specified in the tree. They are:
\begin{description}
\item[obj]objects for the ram part of the code
\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
\item[initobj]seperately-compiled code for the ROM section of coreboot
\end{description}
These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
\section{Example: AMD serengeti cheetah}
\subsection{mainboard/Kconfig}
Defines Vendor variables. Currently defined variables are:
Sources all Kconfig files in the vendor directories.
\input{ mainboardkconfig.tex}
\subsection{mainboard/Makefile.inc}
There is none at this time.
\subsection{mainboard/$<$vendor$>$/Kconfig}
We use the amd as a model. The only action currently taken is to source all Kconfig's in the
subdirectories.
\subsection{mainboard/$<$vendor$>$/Makefile.inc}
We use amd as a model. There is currently no Makefile.inc at this level.
\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
and rules in here determine everything about how a mainboard target is built.
We will use serengeti\_cheetah as a model. It defines these variables.
\input{ mainboardkconfig.tex}
\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
Note that this is the mainboard as of August, 2009, and it may change over time.
\subsubsection{objects}
We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
\begin{verbatim}
driver-y += mainboard.o
#needed by irq_tables and mptable and acpi_tables
obj-y += get_bus_conf.o
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
#./ssdt.o is in northbridge/amd/amdk8/Config.lb
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
\end{verbatim}
\subsubsection{romcc legacy support}
We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
\begin{verbatim}
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
ldscript-y += ../../../../src/arch/i386/lib/id.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
\end{verbatim}
\subsubsection{POST\_EVALUATION}
POST\_EVALUATION rules should be placed after this section:
\begin{verbatim}
ifdef POST_EVALUATION
\end{verbatim}
to ensure that the values of variables are correct.
Here are the post-evaluation rules for this mainboard:
\begin{verbatim}
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
mv dsdt.hex $@
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
mv pci2.hex ssdt2.c
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
mv pci3.hex ssdt3.c
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
mv pci4.hex ssdt4.c
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
\end{verbatim}
The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
\subsubsection{devicetree.cb}
Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
properly, as it defines topology and chips that can be defined no other way.
Let's go through the tree.
\begin{verbatim}
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_F
device apic 0 on end
end
end
\end{verbatim}
This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
somewhere, since it runs memory.
What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
CPU socket. So the tree is rooted at the northbridge, which has a link to an apic cluster, and then the CPU. The CPU contains
its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
{\it northbridge/amd/amdk8/root\_complex}, with its own apic\_cluster device which we turn on,
which connects to a {\it cpu/amd/socket\_F},
which has an apic, which is on.
Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
BIOSes) that the BSP be CPU 0; any CPU will do.
\begin{verbatim}
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
\end{verbatim}
Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
\begin{verbatim}
chip southbridge/amd/amd8132
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
\end{verbatim}
This is the 8132, a bridge to a secondary PCI bus.
\begin{verbatim}
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
end
\end{verbatim}
The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
\begin{verbatim}
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
\end{verbatim}
The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
\begin{verbatim}
device pci 1.1 on end
device pci 1.2 on end
\end{verbatim}
More devices. These statements set up placeholders in the device tree.
\begin{verbatim}
device pci 1.3 on
chip drivers/i2c/i2cmux # pca9556 smbus mux
device i2c 18 on #0 pca9516 1
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 18 on #1 pca9516 2
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-2-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-2-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-3-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-3-1
device i2c 57 on end
end
end
end
end # acpi
\end{verbatim}
These are the i2c devices.
\begin{verbatim}
device pci 1.5 off end
device pci 1.6 off end
\end{verbatim}
More placeholders.
\begin{verbatim}
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0
\end{verbatim}
These "register" commands set controls in the southbridge.
\begin{verbatim}
device pci 18.0 on end
device pci 18.0 on end
\end{verbatim}
These are the other two hypertransport links.
\begin{verbatim}
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
\end{verbatim}
The 18.1 devices are, again, northbridge control for various k8 functions.
\begin{verbatim}
end
\end{verbatim}
That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
\begin{verbatim}
chip northbridge/amd/amdk8
device pci 19.0 on # northbridge
chip southbridge/amd/amd8151
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 1.0 on end
end
end # device pci 19.0
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
\end{verbatim}
\begin{verbatim}
end #pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 off end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end
\end{verbatim}
This is a trick used to debug by creating entries in the device tree.
\subsection{cpu socket}
The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
of all defines and Makefile controls for building the CPU components of a board.
\subsubsection{ cpu/Kconfig}
Defines variables. Current variables are:
\input{cpukconfig.tex}
Sources all Kconfig files in the vendor directories.
\subsubsection{ cpu/Makefile.inc}
Unconditionally sources all Makefile.inc in the vendor directories.
\subsection{cpu/$<$vendor$>$/Kconfig}
The only action currently taken is to source all Kconfig's in the
subdirectories.
\subsection{cpu/$<$vendor$>$/Makefile.inc}
{\em Conditionally} source the socket directories.
Example:
\begin{verbatim}
subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
\end{verbatim}
.
CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
the socket, as much as possible, should control the models, because the models may plug into many sockets.
Socket\_F currently sets:
\input{socketfkconfig.tex}
It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
if needed.
\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
\subsection{northbridge}
\subsubsection{northbridge/Kconfig}
No variables. Source all vendor directory Kconfigs.
\subsubsection{northbridge/Makefile.inc}
No variables. unconditionally include all vendor Makefile.inc
\subsubsection{northbridge/$<$vendor$>$/Kconfig}
No variables. Source all chip directory Kconfigs.
\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
is the name of the part, e.g.
\begin{verbatim}
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
\end{verbatim}
.
\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
Typically a small number of variables. One defines the part name. Here is an example
of the variables defined for the K8.
\begin{verbatim}
config NORTHBRIDGE_AMD_AMDK8
bool
default n
config AGP_APERTURE_SIZE
hex
default 0x4000000
config HAVE_HIGH_TABLES
int
default 1
\end{verbatim}
\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
Typically very small set of rules, and very simple.
Since this file is already conditionally included,
we don't need to test for the chipset CONFIG variable. We
can therefore test other variables (which is part of the reason
we set up conditional inclusion of this file, instead
of unconditionally including it). Here is an example from AMD K8.
Note that we can make a variable conditional on the ACPI tables.
\begin{verbatim}
driver-y += northbridge.o
driver-y += misc_control.o
obj-y += get_sblk_pci1234.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o
\end{verbatim}
\subsection{southbridge}
\subsubsection{southbridge/Kconfig}
No variables. Source all vendor directory Kconfigs.
\subsubsection{southbridge/Makefile.inc}
No variables. {\em Unconditionally} include all vendor Makefile.inc
\subsubsection{southbridge/$<$vendor$>$/Kconfig}
No variables. Source all chip directory Kconfigs.
\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
is the name of the part, e.g.
\begin{verbatim}
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
\end{verbatim}
.
\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
Typically a small number of variables. One defines the part name. Here is an example
of the variables defined for the K8.
\begin{verbatim}
config SOUTHBRIDGE_AMD_AMD8111
bool
default n
\end{verbatim}
\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
Typically very small set of rules, and very simple.
Since this file is already conditionally included,
we don't need to test for the chipset CONFIG variable. We
can therefore test other variables (which is part of the reason
we set up conditional inclusion of this file, instead
of unconditionally including it). Here is an example from AMD 8111.
No conditionals in this one yet.
\begin{verbatim}
driver-y += amd8111.o
driver-y += amd8111_usb.o
driver-y += amd8111_lpc.o
driver-y += amd8111_ide.o
driver-y += amd8111_acpi.o
driver-y += amd8111_usb2.o
driver-y += amd8111_ac97.o
driver-y += amd8111_nic.o
driver-y += amd8111_pci.o
driver-y += amd8111_smbus.o
obj-y += amd8111_reset.o
\end{verbatim}
\subsubsection{vendor and part}
\subsection{southbridge}
\subsubsection{vendor and part}
\subsection{superio}
\subsection{drivers/i2c}
This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
\begin{verbatim}
\end{verbatim}
\subsubsection{vendor and part}
\end{document}

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@ -1,5 +1,5 @@
#
# Makefile for LinuxBIOS paper.
# Makefile for coreboot paper.
# hacked together by Stefan Reinauer <stepan@openbios.org>
#
@ -7,14 +7,29 @@ PDFLATEX=pdflatex -t a4
FIGS=codeflow.pdf hypertransport.pdf
all: LinuxBIOS-AMD64.pdf
all: LinuxBIOS-AMD64.pdf Kconfig.pdf
SVG2PDF=$(shell which svg2pdf)
INKSCAPE=$(shell which inkscape)
CONVERT=$(shell which convert)
codeflow.pdf: codeflow.eps
epstopdf $< -o=$@
codeflow.pdf: codeflow.svg
ifneq ($(strip $(SVG2PDF)),)
svg2pdf $< $@
else ifneq ($(strip $(INKSCAPE)),)
inkscape $< --export-pdf=$@
else ifneq ($(strip $(CONVERT)),)
convert $< $@
endif
hypertransport.pdf: hypertransport.eps
epstopdf $< -o=$@
hypertransport.pdf: hypertransport.svg
ifneq ($(strip $(SVG2PDF)),)
svg2pdf $< $@
else ifneq ($(strip $(INKSCAPE)),)
inkscape $< --export-pdf=$@
else ifneq ($(strip $(CONVERT)),)
convert $< $@
endif
LinuxBIOS-AMD64.toc: $(FIGS) LinuxBIOS-AMD64.tex
# 2 times to make sure we have a current toc.
@ -24,10 +39,33 @@ LinuxBIOS-AMD64.toc: $(FIGS) LinuxBIOS-AMD64.tex
LinuxBIOS-AMD64.pdf: $(FIGS) LinuxBIOS-AMD64.tex LinuxBIOS-AMD64.toc
$(PDFLATEX) LinuxBIOS-AMD64.tex
Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
$(PDFLATEX) $<
# quick, somebody! make me a macro!
mainboardkconfig.tex: ../src/mainboard/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@
skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@
cpukconfig.tex: ../src/cpu/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@
socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
cat beginverbatim.tex > $@
grep '^config' $< | awk '{print $2}' >>$@
cat endverbatim.tex >> $@
clean:
rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
distclean: clean
rm -f LinuxBIOS-AMD64.pdf
rm -f LinuxBIOS-AMD64.pdf Kconfig.pdf

26
documentation/POSTCODES Normal file
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@ -0,0 +1,26 @@
-------------------------------------------------------------------------------
coreboot POST Codes
-------------------------------------------------------------------------------
This is an (incomplete) list of POST codes emitted by coreboot v2.
0x10 Entry into protected mode
0x01 Entry into 'crt0.s' reset code jumps to here
0x11 Start copying LinuxBIOS to RAM with decompression if compressed
0x12 Copy/decompression finished jumping to RAM
0x80 Entry into LinuxBIOS in RAM
0x13 Entry into c_start
0xfe Pre call to hardwaremain()
0x39 Console is initialized
0x40 Console boot message succeeded
0x66 Devices have been enumerated
0x88 Devices have been configured
0x89 Devices have been enabled
0xf8 Entry into elf boot
0xf3 Jumping to payload
Errors (used in several places):
0xee Not supposed to get here
0xff Elfload fail or die() called

View File

@ -28,7 +28,7 @@ The specification looks like this:
chip <name> [path=<path>] ["<configuration>"]
\end{verbatim}
The name is in the standard LinuxBIOS form of type/vendor/name, e.g.
"southbridge/intel/piix4e" or "superio/ITE/it8671f". The class of the
"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the
chip is derived from the first pathname component of the name, and the chip
configuration is derived from the following components.
@ -50,9 +50,9 @@ each individual chip and an array of pointers to these structures.
For each chip, there are two structures. The structures contain control
information for the chip, and register initialization information. The
names of the structures are derived by ``flattening'' the chip name,
as in the current linuxbios. For example, superio/ITE/xyz uses
two structs, one called superio_ITE_xyz_control and one called
superio_ITE_xyz_init. The control struct is initialized from the
as in the current linuxbios. For example, superio/ite/xyz uses
two structs, one called superio_ite_xyz_control and one called
superio_ite_xyz_init. The control struct is initialized from the
chip name and path information, and has a pointer to the
config struct. The config struct is initialized from the quote string

View File

@ -58,7 +58,7 @@ default ::= 'default' ID '=' (``value'' | term)
# as they are specified. To attach a superio to a southbridge, for
# example, one would do this:
# southbridge acer/5432
# superio NSC/123
# superio nsc/123
# end
# end
# the tool generates static initializers for this hierarchy.
@ -173,7 +173,7 @@ A sample file:
target x
# over-ride the default rom size in the mainboard file
option ROM_SIZE=1024*1024
option CONFIG_ROM_SIZE=1024*1024
mainboard amd/solo
end
@ -188,8 +188,8 @@ Sample mainboard file
arch i386 end
cpu k8 end
#
option DEBUG=1
default USE_FALLBACK_IMAGE=1
option CONFIG_DEBUG=1
default CONFIG_USE_FALLBACK_IMAGE=1
option A=(1+2)
option B=0xa
#
@ -204,7 +204,7 @@ ldscript cpu/i386/entry32.lds
###
### Build our reset vector (This is where linuxBIOS is entered)
###
if USE_FALLBACK_IMAGE
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc
ldscript cpu/i386/reset16.lds
else
@ -214,15 +214,15 @@ end
.
.
.
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
###
### Romcc output
###
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit ./failover.inc
makerule ./auto.E dep "$(MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
mainboardinit ./auto.inc
#
@ -234,7 +234,7 @@ end
southbridge amd/amd8111
end
#mainboardinit arch/i386/smp/secondary.inc
superio NSC/pc87360
superio nsc/pc87360
register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
end
dir /pc80
@ -250,8 +250,8 @@ cpu k8 end
##object mainboard.o
driver mainboard.o
object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_MP_TABLE object mptable.o end
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
### Location of the DIMM EEPROMS on the SMBUS
### This is fixed into a narrow range by the DIMM package standard.
###
@ -261,8 +261,8 @@ option SMBUS_MEM_DEVICE_INC=1
#
### The linuxBIOS bootloader.
###
option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
#
\end{verbatim}
@ -272,17 +272,17 @@ handle. Makefile.settings looks like this, for example:
\begin{verbatim}
TOP:=/home/rminnich/src/yapps2/freebios2
TARGET_DIR:=x
export MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
export ARCH:=i386
export _RAMBASE:=0x4000
export ROM_IMAGE_SIZE:=65535
export PAYLOAD_SIZE:=131073
export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
export CONFIG_ARCH:=i386
export CONFIG_RAMBASE:=0x4000
export CONFIG_ROM_IMAGE_SIZE:=65535
export CONFIG_PAYLOAD_SIZE:=131073
export CONFIG_MAX_CPUS:=1
export HEAP_SIZE:=8192
export STACK_SIZE:=8192
export MEMORY_HOLE:=0
export LINUXBIOS_VERSION:=1.1.0
export CC:=$(CROSS_COMPILE)gcc
export CONFIG_HEAP_SIZE:=8192
export CONFIG_STACK_SIZE:=8192
export CONFIG_MEMORY_HOLE:=0
export COREBOOT_VERSION:=1.1.0
export CC:=$(CONFIG_CROSS_COMPILE)gcc
\end{verbatim}

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@ -0,0 +1 @@
\begin{verbatim}

409
documentation/cbfs.txt Normal file
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@ -0,0 +1,409 @@
Received: from www.crouse-house.com ([199.45.160.146]
for coreboot@coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100
From: Jordan Crouse <jordan@cosmicpenguin.net>
Greetings. I apologize for the incompleteness of what I am about to
discuss. I was planning on working on it leisurely, but my employment
circumstances changed and I've been trying to get it completed in a
hurry before I had to leave it behind.
I've been thinking a lot about LAR lately, and ways to make it more
extensible and robust. Marc and I have been trading ideas back and
forth for a number of months, and over time a clear idea of what I
wanted to do started to take shape.
My goal was to add small things to LAR while retaining the overall
scheme. Over time, the scheme evolved slightly, but I think you'll find
that it remains true to the original idea. Below is the beginnings of
an architecture document - I did it in text form, but if met with
aclaim, it should be wikified. This presents what I call CBFS - the
next generation LAR for next generation Coreboot. Its easier to
describe what it is by describing what changed:
A header has been added somewhere in the bootblock similar to Carl
Daniel's scheme. In addition to the coreboot information, the header
reports the size of the ROM, the alignment of the blocks, and the offset
of the first component in the CBFS. The master header provides all
the information LAR needs plus the magic number information flashrom needs.
Each "file" (or component, as I style them) now has a type associated
with it. The type is used by coreboot to identify the type of file that
it is loading, and it can also be used by payloads to group items in the
CBFS by type (i.e - bayou can ask for all components that are payloads).
The header on each "file" (or component, as I like to style them) has
been simplified - We now only store the length, the type, the checksum,
and the offset to the data. The name scheme remains the same. The
addtional information, which is component specific, has been moved to
the component itself (see below).
The components are arranged in the ROM aligned along the specified
alignment from the master header - this is to facilitate partial re-write.
Other then that, the LAR ideas remain pretty much the same.
The plan for moving the metadata to the components is to allow many
different kinds of components, not all of which are groked by coreboot.
However, there are three essential component types that are groked by
coreboot, and they are defined:
stage - the stage is being parsed from the original ELF, and stored in
the ROM as a single blob of binary data. The load address, start
address, compression type and length are stored in the component sub-header.
payload - this is essentially SELF in different clothing - same idea as
SELF, with the sub-header as above.
optionrom - This is in flux - right now, the optionrom is stored
unadulterated and uncompressed, but that is likely to be changed.
Following this email are two replies containing the v3 code and a new
ROM tool to implement this respectively. I told you that I was trying
to get this out before I disappear, and I'm not kidding - the code is
compile tested and not run-tested. I hope that somebody will embrace
this code and take it the rest of the way, otherwise it will die a
pretty short death.
I realize that this will start an awesome flamewar, and I'm looking
forward to it. Thanks for listening to me over the years - and good
luck with coreboot. When you all make a million dollars, send me a few
bucks, will you?
Jordan
Coreboot CBFS Specification
Jordan Crouse <jordan@cosmicpenguin.net>
= Introduction =
This document describes the coreboot CBFS specification (from here
referred to as CBFS). CBFS is a scheme for managing independent chunks
of data in a system ROM. Though not a true filesystem, the style and
concepts are similar.
= Architecture =
The CBFS architecture looks like the following:
/---------------\ <-- Start of ROM
| /-----------\ | --|
| | Header | | |
| |-----------| | |
| | Name | | |-- Component
| |-----------| | |
| |Data | | |
| |.. | | |
| \-----------/ | --|
| |
| /-----------\ |
| | Header | |
| |-----------| |
| | Name | |
| |-----------| |
| |Data | |
| |.. | |
| \-----------/ |
| |
| ... |
| /-----------\ |
| | | |
| | Bootblock | |
| | --------- | |
| | Reset | | <- 0xFFFFFFF0
| \-----------/ |
\---------------/
The CBFS architecture consists of a binary associated with a physical
ROM disk referred hereafter as the ROM. A number of independent of
components, each with a header prepended on to data are located within
the ROM. The components are nominally arranged sequentially, though they
are aligned along a pre-defined boundary.
The bootblock occupies the last 20k of the ROM. Within
the bootblock is a master header containing information about the ROM
including the size, alignment of the components, and the offset of the
start of the first CBFS component within the ROM.
= Master Header =
The master header contains essential information about the ROM that is
used by both the CBFS implementation within coreboot at runtime as well
as host based utilities to create and manage the ROM. The master header
will be located somewhere within the bootblock (last 20k of the ROM). A
pointer to the location of the header will be located at offset
-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
normal x86 system. The pointer will be to physical memory somewhere
between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
to locate the header at run time. Build time utilities will
need to read the pointer and do the appropriate math to locate the header.
The following is the structure of the master header:
struct cbfs_header {
unsigned int magic;
unsigned int size;
unsigned int align;
unsigned int offset;
};
The meaning of each member is as follows:
'magic' is a 32 bit number that identifies the ROM as a CBFS type. The
magic
number is 0x4F524243, which is 'ORBC' in ASCII.
'size' is the size of the ROM in bytes. Coreboot will subtract 'size' from
0xFFFFFFFF to locate the beginning of the ROM in memory.
'align' is the number of bytes that each component is aligned to within the
ROM. This is used to make sure that each component is aligned correctly
with
regards to the erase block sizes on the ROM - allowing one to replace a
component at runtime without disturbing the others.
'offset' is the offset of the the first CBFS component (from the start of
the ROM). This is to allow for arbitrary space to be left at the beginning
of the ROM for things like embedded controller firmware.
= Bootblock =
The bootblock is a mandatory component in the ROM. It is located in the
last
20k of the ROM space, and contains, among other things, the location of the
master header and the entry point for the loader firmware. The bootblock
does not have a component header attached to it.
= Components =
CBFS components are placed in the ROM starting at 'offset' specified in
the master header and ending at the bootblock. Thus the total size
available
for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS
component is to be aligned according to the 'align' value in the header.
Thus, if a component of size 1052 is located at offset 0 with an 'align'
value
of 1024, the next component will be located at offset 2048.
Each CBFS component will be indexed with a unique ASCII string name of
unlimited size.
Each CBFS component starts with a header:
struct cbfs_file {
char magic[8];
unsigned int len;
unsigned int type;
unsigned int checksum;
unsigned int offset;
};
'magic' is a magic value used to identify the header. During runtime,
coreboot will scan the ROM looking for this value. The default magic is
the string 'LARCHIVE'.
'len' is the length of the data, not including the size of the header and
the size of the name.
'type' is a 32 bit number indicating the type of data that is attached.
The data type is used in a number of ways, as detailed in the section
below.
'checksum' is a 32bit checksum of the entire component, including the
header and name.
'offset' is the start of the component data, based off the start of the
header.
The difference between the size of the header and offset is the size of the
component name.
Immediately following the header will be the name of the component,
which will
null terminated and 16 byte aligned. The following picture shows the
structure of the header:
/--------\ <- start
| Header |
|--------| <- sizeof(struct cbfs_file)
| Name |
|--------| <- 'offset'
| Data |
| ... |
\--------/ <- start + 'offset' + 'len'
== Searching Alogrithm ==
To locate a specific component in the ROM, one starts at the 'offset'
specified in the CBFS master header. For this example, the offset will
be 0.
From that offset, the code should search for the magic string on the
component, jumping 'align' bytes each time. So, assuming that 'align' is
16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
If the offset ever exceeds the allowable range for CBFS components, then no
component was found.
Upon recognizing a component, the software then has to search for the
specific name of the component. This is accomplished by comparing the
desired name with the string on the component located at
offset + sizeof(struct cbfs_file). If the string matches, then the
component
has been located, otherwise the software should add 'offset' + 'len' to
the offset and resume the search for the magic value.
== Data Types ==
The 'type' member of struct cbfs_file is used to identify the content
of the component data, and is used by coreboot and other
run-time entities to make decisions about how to handle the data.
There are three component types that are essential to coreboot, and so
are defined here.
=== Stages ===
Stages are code loaded by coreboot during the boot process. They are
essential to a successful boot. Stages are comprised of a single blob
of binary data that is to be loaded into a particular location in memory
and executed. The uncompressed header contains information about how
large the data is, and where it should be placed, and what additional memory
needs to be cleared.
Stages are assigned a component value of 0x10. When coreboot sees this
component type, it knows that it should pass the data to a sub-function
that will process the stage.
The following is the format of a stage component:
/--------\
| Header |
|--------|
| Binary |
| .. |
\--------/
The header is defined as:
struct cbfs_stage {
unsigned int compression;
unsigned long long entry;
unsigned long long load;
unsigned int len;
unsigned int memlen;
};
'compression' is an integer defining how the data is compressed. There
are three compression types defined by this version of the standard:
none (0x0), lzma (0x1), and nrv2b (0x02), though additional types may be
added assuming that coreboot understands how to handle the scheme.
'entry' is a 64 bit value indicating the location where the program
counter should jump following the loading of the stage. This should be
an absolute physical memory address.
'load' is a 64 bit value indicating where the subsequent data should be
loaded. This should be an absolute physical memory address.
'len' is the length of the compressed data in the component.
'memlen' is the amount of memory that will be used by the component when
it is loaded.
The component data will start immediately following the header.
When coreboot loads a stage, it will first zero the memory from 'load' to
'memlen'. It will then decompress the component data according to the
specified scheme and place it in memory starting at 'load'. Following that,
it will jump execution to the address specified by 'entry'.
Some components are designed to execute directly from the ROM - coreboot
knows which components must do that and will act accordingly.
=== Payloads ===
Payloads are loaded by coreboot following the boot process.
Stages are assigned a component value of 0x20. When coreboot sees this
component type, it knows that it should pass the data to a sub-function
that will process the payload. Furthermore, other run time
applications such as 'bayou' may easily index all available payloads
on the system by searching for the payload type.
The following is the format of a stage component:
/-----------\
| Header |
| Segment 1 |
| Segment 2 |
| ... |
|-----------|
| Binary |
| .. |
\-----------/
The header is as follows:
struct cbfs_payload {
struct cbfs_payload_segment segments;
}
The header contains a number of segments corresponding to the segments
that need to be loaded for the payload.
The following is the structure of each segment header:
struct cbfs_payload_segment {
unsigned int type;
unsigned int compression;
unsigned int offset;
unsigned long long load_addr;
unsigned int len;
unsigned int mem_len;
};
'type' is the type of segment, one of the following:
PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code
PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data
PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment
should be zeroed
PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for
the payload
PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point
for the payload
'compression' is the compression scheme for the segment. Each segment can
be independently compressed. There are three compression types defined by
this version of the standard: none (0x0), lzma (0x1), and nrv2b (0x02),
though additional types may be added assuming that coreboot understands
how to handle the scheme.
'offset' is the address of the data within the component, starting from
the component header.
'load_addr' is a 64 bit value indicating where the segment should be placed
in memory.
'len' is a 32 bit value indicating the size of the segment within the
component.
'mem_len' is the size of the data when it is placed into memory.
The data will located immediately following the last segment.
=== Option ROMS ===
The third specified component type will be Option ROMs. Option ROMS will
have component type '0x30'. They will have no additional header, the
uncompressed binary data will be located in the data portion of the
component.
=== NULL ===
There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
the "don't care" component type. This can be used when the component
type is not necessary (such as when the name of the component is unique.
i.e. option_table). It is recommended that all components be assigned a
unique type, but NULL can be used when the type does not matter.

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@ -0,0 +1,234 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
width="256px" height="640px" viewBox="0 0 256 640" enable-background="new 0 0 256 640" xml:space="preserve">
<font horiz-adv-x="1000">
<font-face font-family="MyriadPro-Regular" units-per-em="1000" underline-position="-100" underline-thickness="50"/>
<missing-glyph horiz-adv-x="500" d="M0,0l500,0l0,700l-500,0M250,395l-170,255l340,0M280,350l170,255l0,-510M80,50l170,255l170,-255M50,605l170,-255l-170,-255z"/>
<glyph unicode="A" horiz-adv-x="612" d="M424,212l72,-212l93,0l-230,674l-104,0l-230,-674l90,0l70,212M203,280l66,195C283,516 293,558 303,597l2,0C315,558 325,518 340,474l67,-194z"/>
<glyph unicode="B" horiz-adv-x="542" d="M76,2C105,-2 151,-6 211,-6C321,-6 397,14 443,57C478,89 501,134 501,192C501,292 426,345 362,360l0,3C432,388 476,445 476,511C476,564 454,604 419,630C378,664 322,679 235,679C175,679 114,673 76,664M163,606C177,609 200,612 240,612C328,612 387,580 387,502C387,437 333,388 242,388l-79,0M163,323l72,0C330,323 409,284 409,193C409,95 326,62 236,62C205,62 181,63 163,66z"/>
<glyph unicode="C" horiz-adv-x="580" d="M529,91C494,74 440,63 386,63C223,63 128,168 128,334C128,511 233,612 391,612C447,612 494,600 526,584l22,71C525,667 471,685 388,685C179,685 36,543 36,331C36,109 178,-11 368,-11C450,-11 515,5 546,21z"/>
<glyph unicode="D" horiz-adv-x="666" d="M76,2C120,-3 171,-6 234,-6C365,-6 469,28 533,91C595,153 630,243 630,353C630,462 595,540 534,595C475,649 386,679 261,679C192,679 129,673 76,664M163,601C186,606 220,610 265,610C449,610 539,509 538,350C538,168 438,64 251,64C217,64 185,65 163,68z"/>
<glyph unicode="E" horiz-adv-x="492" d="M424,388l-261,0l0,213l277,0l0,73l-365,0l0,-674l380,0l0,73l-292,0l0,243l261,0z"/>
<glyph unicode="F" horiz-adv-x="487" d="M75,0l88,0l0,305l254,0l0,72l-254,0l0,224l275,0l0,73l-363,0z"/>
<glyph unicode="H" horiz-adv-x="652" d="M75,674l0,-674l88,0l0,316l326,0l0,-316l88,0l0,674l-88,0l0,-282l-326,0l0,282z"/>
<glyph unicode="I" horiz-adv-x="239" d="M75,674l0,-674l88,0l0,674z"/>
<glyph unicode="L" horiz-adv-x="472" d="M75,0l376,0l0,73l-288,0l0,601l-88,0z"/>
<glyph unicode="M" horiz-adv-x="804" d="M660,0l86,0l-42,674l-111,0l-120,-326C443,263 419,189 401,121l-2,0C381,191 359,265 331,348l-115,326l-111,0l-47,-674l83,0l18,289C165,391 170,503 172,587l2,0C193,507 219,421 251,325l110,-321l66,0l119,327C580,424 607,509 631,587l2,0C633,504 639,390 644,296z"/>
<glyph unicode="N" horiz-adv-x="658" d="M158,0l0,288C158,400 157,481 152,566l3,1C188,494 233,417 280,342l214,-342l88,0l0,674l-82,0l0,-282C500,287 502,205 510,115l-3,-1C476,183 436,254 387,333l-215,341l-96,0l0,-674z"/>
<glyph unicode="O" horiz-adv-x="689" d="M348,686C168,686 36,546 36,332C36,128 160,-11 339,-11C511,-11 652,113 652,344C652,545 533,686 348,686M345,615C490,615 560,475 560,340C560,187 482,60 344,60C206,60 128,189 128,334C128,481 200,615 345,615z"/>
<glyph unicode="P" horiz-adv-x="532" d="M76,0l87,0l0,270C183,265 207,264 233,264C318,264 392,289 439,338C473,373 491,421 491,482C491,542 468,591 432,623C392,659 329,679 243,679C173,679 118,673 76,666M163,603C178,607 207,610 245,610C340,610 404,567 404,477C404,386 340,334 235,334C206,334 182,336 163,341z"/>
<glyph unicode="Q" horiz-adv-x="689" d="M657,-26C600,-16 527,0 460,17l0,4C572,61 652,171 652,345C652,544 533,686 349,686C167,686 36,547 36,331C36,113 172,-5 333,-11C346,-11 359,-16 374,-21C452,-48 541,-75 632,-99M344,60C206,60 128,189 128,333C128,479 200,615 347,615C490,615 560,476 560,340C560,187 482,60 344,60z"/>
<glyph unicode="R" horiz-adv-x="538" d="M76,0l87,0l0,292l82,0C324,289 361,254 381,161C399,77 414,20 425,0l90,0C501,26 485,91 463,185C447,255 416,303 365,321l0,3C435,348 491,407 491,495C491,548 471,594 438,624C397,661 336,679 243,679C184,679 120,673 76,665M163,604C178,608 207,611 249,611C341,611 404,573 404,486C404,409 345,358 252,358l-89,0z"/>
<glyph unicode="S" horiz-adv-x="493" d="M42,33C78,9 149,-11 214,-11C373,-11 449,80 449,184C449,283 392,338 278,382C185,418 144,449 144,512C144,558 179,613 271,613C332,613 377,594 398,581l24,71C393,669 342,685 274,685C143,685 56,607 56,502C56,408 124,350 234,310C325,276 361,239 361,177C361,109 309,62 220,62C160,62 104,81 65,106z"/>
<glyph unicode="T" horiz-adv-x="497" d="M204,0l88,0l0,600l206,0l0,74l-499,0l0,-74l205,0z"/>
<glyph unicode="U" horiz-adv-x="647" d="M75,674l0,-397C75,67 179,-11 317,-11C463,-11 572,73 572,280l0,394l-88,0l0,-400C484,126 419,60 320,60C230,60 163,124 163,274l0,400z"/>
<glyph unicode="a" horiz-adv-x="482" d="M413,297C413,393 377,494 229,494C168,494 109,477 69,452l20,-59C123,416 170,429 216,429C315,430 326,357 326,318l0,-10C139,309 35,245 35,128C35,58 85,-11 183,-11C252,-11 304,23 331,61l3,0l7,-61l79,0C415,33 413,74 413,116M328,163C328,155 327,145 324,135C310,94 269,54 205,54C161,54 123,80 123,138C123,232 232,249 328,247z"/>
<glyph unicode="b" horiz-adv-x="569" d="M73,125C73,82 71,33 69,0l75,0l5,79l2,0C188,16 244,-11 314,-11C422,-11 532,75 532,248C532,394 448,494 327,494C249,494 193,460 162,406l-2,0l0,304l-87,0M160,280C160,294 162,306 165,317C183,383 239,425 298,425C393,425 443,342 443,245C443,134 389,59 296,59C232,59 180,101 164,162C161,172 160,183 160,194z"/>
<glyph unicode="c" horiz-adv-x="448" d="M403,83C378,72 345,60 295,60C199,60 127,129 127,241C127,341 187,424 298,424C346,424 379,412 400,401l20,67C396,481 350,494 298,494C140,494 38,385 38,236C38,88 133,-11 279,-11C344,-11 395,6 418,17z"/>
<glyph unicode="," horiz-adv-x="207" d="M78,-117C106,-70 150,41 174,126l-98,-10C65,43 38,-64 16,-124z"/>
<glyph unicode="d" horiz-adv-x="564" d="M403,710l0,-289l-2,0C379,459 330,494 255,494C138,494 37,396 38,235C38,88 129,-11 246,-11C325,-11 383,30 409,84l3,0l4,-84l78,0C492,33 490,82 490,125l0,585M403,203C403,189 402,177 399,165C383,100 329,60 270,60C176,60 127,141 127,239C127,345 181,425 272,425C338,425 386,379 399,324C402,313 403,298 403,287z"/>
<glyph unicode="e" horiz-adv-x="501" d="M462,226C464,236 465,249 465,267C465,356 424,494 265,494C124,494 38,380 38,234C38,88 127,-11 276,-11C353,-11 407,6 438,20l-16,63C390,69 351,58 288,58C199,58 124,107 122,226M123,289C130,350 168,431 258,431C357,431 381,344 380,289z"/>
<glyph unicode="h" horiz-adv-x="555" d="M73,0l88,0l0,292C161,308 162,321 167,334C184,381 228,421 285,421C368,421 397,356 397,278l0,-278l88,0l0,288C485,454 381,494 316,494C283,494 252,485 226,470C199,455 177,432 163,407l-2,0l0,303l-88,0z"/>
<glyph unicode="-" horiz-adv-x="307" d="M30,302l0,-64l247,0l0,64z"/>
<glyph unicode="i" horiz-adv-x="234" d="M161,0l0,484l-88,0l0,-484M117,675C84,675 62,650 62,620C62,590 83,566 115,566C150,566 171,590 171,620C171,651 149,675 117,675z"/>
<glyph unicode="k" horiz-adv-x="469" d="M160,710l-87,0l0,-710l87,0l0,182l45,50l166,-232l108,0l-213,285l186,199l-105,0l-143,-167C190,300 174,279 162,262l-2,0z"/>
<glyph unicode="l" horiz-adv-x="236" d="M73,0l88,0l0,710l-88,0z"/>
<glyph unicode="m" horiz-adv-x="834" d="M73,0l86,0l0,291C159,306 161,322 166,334C180,378 221,422 275,422C342,422 376,367 376,290l0,-290l86,0l0,299C462,315 465,330 469,343C485,385 523,422 574,422C644,422 679,367 679,273l0,-273l86,0l0,284C765,452 670,494 605,494C559,494 528,482 499,460C479,445 459,425 444,397l-2,0C421,454 371,494 306,494C225,494 180,451 153,405l-3,0l-4,79l-77,0C71,444 73,404 73,353z"/>
<glyph unicode="n" horiz-adv-x="555" d="M73,0l88,0l0,291C161,306 163,321 167,332C183,381 228,422 285,422C368,422 397,357 397,279l0,-279l88,0l0,288C485,454 381,494 314,494C234,494 178,449 154,404l-2,0l-5,80l-78,0C72,444 73,404 73,353z"/>
<glyph unicode="o" horiz-adv-x="549" d="M278,494C145,494 38,399 38,238C38,85 140,-11 270,-11C386,-11 511,67 511,246C511,393 417,494 278,494M276,428C380,428 421,325 421,243C421,134 358,55 274,55C188,55 128,135 128,241C128,332 173,428 276,428z"/>
<glyph unicode="p" horiz-adv-x="569" d="M73,-198l87,0l0,263l2,0C191,17 247,-11 311,-11C425,-11 532,75 532,249C532,395 444,494 326,494C247,494 189,460 154,401l-2,0l-5,83l-78,0C71,438 73,388 73,326M160,281C160,292 163,305 166,316C182,382 239,424 299,424C392,424 443,341 443,245C443,134 389,58 296,58C233,58 180,100 164,161C161,172 160,184 160,197z"/>
<glyph unicode="(" horiz-adv-x="284" d="M195,694C132,610 65,481 64,285C64,90 132,-38 195,-121l68,0C193,-21 138,106 138,284C138,466 190,595 263,694z"/>
<glyph unicode=")" horiz-adv-x="284" d="M88,-121C151,-37 218,91 219,287C219,483 151,612 88,694l-68,0C91,594 145,467 145,287C145,107 90,-22 20,-121z"/>
<glyph unicode="." horiz-adv-x="207" d="M110,-11C147,-11 171,16 171,52C171,89 147,115 112,115C77,115 52,88 52,52C52,16 76,-11 110,-11z"/>
<glyph unicode="?" horiz-adv-x="406" d="M220,192l-2,25C215,268 231,313 275,365C323,422 361,471 361,539C361,615 309,686 194,686C141,686 85,670 51,646l24,-63C100,602 140,614 176,614C239,613 271,579 271,528C271,483 246,444 201,391C151,331 133,271 139,218l2,-26M178,-11C215,-11 238,16 238,51C238,88 215,114 179,114C145,114 120,88 120,51C120,16 144,-11 178,-11z"/>
<glyph unicode="r" horiz-adv-x="327" d="M73,0l88,0l0,258C161,272 162,287 164,299C176,365 220,411 282,411C294,411 303,411 312,409l0,83C304,493 297,494 288,494C229,494 175,453 153,388l-3,0l-4,96l-77,0C72,439 73,390 73,333z"/>
<glyph unicode="s" horiz-adv-x="396" d="M40,23C74,3 123,-11 176,-11C289,-11 356,49 356,135C356,207 312,249 229,280C166,305 138,323 138,363C138,399 166,429 218,429C263,429 298,412 317,400l21,64C312,481 269,494 220,494C117,494 53,430 53,352C53,294 94,247 182,215C246,191 271,169 271,127C271,86 241,55 178,55C134,55 88,73 61,89z"/>
<glyph unicode="/" horiz-adv-x="343" d="M66,-39l280,725l-69,0l-278,-725z"/>
<glyph unicode=" " horiz-adv-x="212"/>
<glyph unicode="t" horiz-adv-x="331" d="M93,574l0,-90l-75,0l0,-67l75,0l0,-264C93,96 103,53 127,26C148,3 181,-11 222,-11C256,-11 283,-5 300,1l-4,67C283,64 269,62 245,62C196,62 179,96 179,156l0,261l126,0l0,67l-126,0l0,116z"/>
<glyph unicode="2" horiz-adv-x="513" d="M460,0l0,73l-291,0l0,2l51,48C357,255 444,352 444,472C444,565 385,661 245,661C171,661 106,632 62,595l28,-62C120,558 169,588 228,588C325,588 356,527 356,461C356,363 280,279 114,121l-69,-67l0,-54z"/>
<glyph unicode="u" horiz-adv-x="551" d="M478,484l-88,0l0,-296C390,171 387,155 382,143C366,103 325,62 266,62C187,62 158,125 158,217l0,267l-88,0l0,-283C70,32 161,-11 237,-11C323,-11 375,40 397,79l2,0l5,-79l78,0C479,38 478,82 478,133z"/>
<glyph unicode="v" horiz-adv-x="481" d="M13,484l184,-484l84,0l190,484l-92,0l-94,-271C269,168 255,128 244,88l-3,0C231,128 218,168 202,213l-95,271z"/>
<glyph unicode="x" horiz-adv-x="463" d="M16,484l164,-237l-172,-247l97,0l70,109C194,138 210,164 226,193l2,0C245,164 261,137 280,109l72,-109l99,0l-169,250l165,234l-96,0l-67,-103C267,355 251,330 235,302l-2,0C217,329 202,353 183,380l-69,104z"/>
<glyph unicode="y" horiz-adv-x="471" d="M9,484l178,-446C192,27 194,20 194,15C194,10 191,3 187,-6C166,-51 137,-85 113,-104C87,-126 58,-140 36,-147l22,-73C80,-216 122,-201 166,-164C226,-111 269,-27 332,139l132,345l-93,0l-96,-284C263,165 253,128 244,99l-2,0C234,128 222,166 210,198l-105,286z"/>
<glyph unicode="z" horiz-adv-x="428" d="M18,0l392,0l0,70l-282,0l0,2C150,96 169,121 190,148l216,281l0,55l-368,0l0,-70l262,0l0,-2C278,386 258,363 236,336l-218,-285z"/>
</font>
<g>
<rect y="1.152" fill="#AAAAAA" stroke="#000000" width="256" height="36.887"/>
<text transform="matrix(1 0 0 1 27.7441 23.7046)" font-family="'MyriadPro-Regular'" font-size="14">Enter protected mode</text>
</g>
<g>
<rect y="45.642" fill="#AAAAAA" stroke="#000000" width="256" height="43.62"/>
<text transform="matrix(1 0 0 1 27.7441 71.5605)" font-family="'MyriadPro-Regular'" font-size="14">non-coherent HT enumeration</text>
</g>
<g>
<rect y="98.359" fill="#AAAAAA" stroke="#000000" width="256" height="60.15"/>
<text transform="matrix(1 0 0 1 27.7441 132.5435)" font-family="'MyriadPro-Regular'" font-size="14">coherent HT initialization</text>
</g>
<g>
<rect y="165.983" fill="#AAAAAA" stroke="#000000" width="256" height="68.421"/>
<text transform="matrix(1 0 0 1 27.7441 204.3022)" font-family="'MyriadPro-Regular'" font-size="14">Fallback / Normal?</text>
</g>
<g>
<rect y="243.893" fill="#AAAAAA" stroke="#000000" width="256" height="69.173"/>
<text transform="matrix(1 0 0 1 27.7441 282.5879)" font-family="'MyriadPro-Regular'" font-size="14">RAM initialization</text>
</g>
<g>
<rect y="410.747" fill="#AAAAAA" stroke="#000000" width="256" height="52.632"/>
<text transform="matrix(1 0 0 1 27.7441 432.7725)"><tspan x="0" y="0" font-family="'MyriadPro-Regular'" font-size="14">Create external tables (coreboot table,</tspan><tspan x="0" y="16.8" font-family="'MyriadPro-Regular'" font-size="14">ACPI, MP, PIRQ, DMI)</tspan></text>
</g>
<g>
<rect y="323.526" fill="#AAAAAA" stroke="#000000" width="256" height="77.443"/>
<text transform="matrix(1 0 0 1 27.7441 339.3154)"><tspan x="0" y="0" font-family="'MyriadPro-Regular'" font-size="14">Resource Allocation (PCI, PCIe, I2C, SIO, </tspan><tspan x="0" y="16.8" font-family="'MyriadPro-Regular'" font-size="14">CPU, mainboard...)</tspan></text>
<rect x="27.744" y="362.248" fill="#BCBCBC" width="228.256" height="38.722"/>
</g>
<g>
<rect y="473.781" fill="#AAAAAA" stroke="#000000" width="256" height="80.076"/>
<text transform="matrix(1 0 0 1 27.7441 497.4658)" font-family="'MyriadPro-Regular'" font-size="14">ELF / Payload Loader</text>
<rect x="27.744" y="507.993" fill="#BCBCBC" width="228.256" height="45.864"/>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,31.246 130.359,46.62 132.854,44.7
132.027,51.206 131.201,57.711 124.701,56.845 118.201,55.98 120.608,54.127 110.178,33.439 "/>
</g>
<polygon fill="#231F20" points="131.101,57.636 132.228,59.101 133.828,45.178 133.062,44.181 "/>
<polygon fill="#231F20" points="131.152,57.643 132.28,59.108 118.41,57.093 117.644,56.096 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,81.246 130.359,96.62 132.854,94.7
132.027,101.206 131.201,107.711 124.701,106.845 118.201,105.98 120.608,104.127 110.178,83.439 "/>
</g>
<polygon fill="#231F20" points="131.101,107.636 132.228,109.101 133.828,95.178 133.062,94.181 "/>
<polygon fill="#231F20" points="131.152,107.643 132.28,109.108 118.41,107.093 117.644,106.096 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,151.586 130.359,166.961 132.854,165.041
132.027,171.546 131.201,178.052 124.701,177.186 118.201,176.321 120.608,174.468 110.178,153.78 "/>
</g>
<polygon fill="#231F20" points="131.101,177.977 132.228,179.442 133.828,165.519 133.062,164.522 "/>
<polygon fill="#231F20" points="131.152,177.983 132.28,179.449 118.41,177.434 117.644,176.437 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,227.013 130.359,242.387 132.854,240.467
132.027,246.973 131.201,253.478 124.701,252.612 118.201,251.747 120.608,249.894 110.178,229.207 "/>
</g>
<polygon fill="#231F20" points="131.101,253.403 132.228,254.868 133.828,240.945 133.062,239.948 "/>
<polygon fill="#231F20" points="131.152,253.41 132.28,254.875 118.41,252.86 117.644,251.863 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,303.013 130.359,318.388 132.854,316.468
132.027,322.973 131.201,329.479 124.701,328.612 118.201,327.747 120.607,325.895 110.178,305.207 "/>
</g>
<polygon fill="#231F20" points="131.101,329.404 132.228,330.868 133.829,316.945 133.062,315.948 "/>
<polygon fill="#231F20" points="131.152,329.41 132.28,330.876 118.41,328.86 117.643,327.864 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,395.872 130.359,411.247 132.854,409.327
132.027,415.833 131.201,422.338 124.701,421.473 118.201,420.606 120.608,418.754 110.178,398.066 "/>
</g>
<polygon fill="#231F20" points="131.101,422.264 132.228,423.728 133.828,409.805 133.062,408.808 "/>
<polygon fill="#231F20" points="131.152,422.27 132.28,423.735 118.41,421.72 117.644,420.724 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<g>
<polygon fill="#FFFFFF" stroke="#231F20" stroke-width="0.3876" points="113.028,452.152 130.359,467.528 132.854,465.608
132.027,472.113 131.201,478.619 124.701,477.753 118.201,476.888 120.607,475.035 110.178,454.347 "/>
</g>
<polygon fill="#231F20" points="131.101,478.545 132.228,480.009 133.829,466.085 133.062,465.089 "/>
<polygon fill="#231F20" points="131.152,478.551 132.28,480.017 118.41,478.001 117.643,477.004 "/>
</g>
</g>
</g>
</g>
</g>
</g>
</g>
<text transform="matrix(1 0 0 1 59.3232 385.7627)" font-family="'MyriadPro-Regular'" font-size="14">Drivers</text>
<text transform="matrix(1 0 0 1 55.564 535.3789)" font-family="'MyriadPro-Regular'" font-size="14">Linux, FILO, SeaBIOS, ...</text>
</svg>

After

Width:  |  Height:  |  Size: 17 KiB

View File

@ -0,0 +1 @@
\end{verbatim}

View File

@ -1,527 +0,0 @@
%!PS-Adobe-3.0 EPSF-3.0
%%BoundingBox: 0 0 174 228
%%Pages: 0
%%Creator: Sun Microsystems, Inc.
%%Title: none
%%CreationDate: none
%%LanguageLevel: 2
%%EndComments
%%BeginProlog
%%BeginResource: SDRes
/b4_inc_state save def
/dict_count countdictstack def
/op_count count 1 sub def
userdict begin
0 setgray 0 setlinecap 1 setlinewidth 0 setlinejoin 10 setmiterlimit[] 0 setdash newpath
/languagelevel where {pop languagelevel 1 ne {false setstrokeadjust false setoverprint} if} if
/bdef {bind def} bind def
/c {setrgbcolor} bdef
/l {neg lineto} bdef
/rl {neg rlineto} bdef
/lc {setlinecap} bdef
/lj {setlinejoin} bdef
/lw {setlinewidth} bdef
/ml {setmiterlimit} bdef
/ld {setdash} bdef
/m {neg moveto} bdef
/ct {6 2 roll neg 6 2 roll neg 6 2 roll neg curveto} bdef
/r {rotate} bdef
/t {neg translate} bdef
/s {scale} bdef
/sw {show} bdef
/gs {gsave} bdef
/gr {grestore} bdef
/f {findfont dup length dict begin
{1 index /FID ne {def} {pop pop} ifelse} forall /Encoding ISOLatin1Encoding def
currentdict end /NFont exch definefont pop /NFont findfont} bdef
/p {closepath} bdef
/sf {scalefont setfont} bdef
/ef {eofill}bdef
/pc {closepath stroke}bdef
/ps {stroke}bdef
/pum {matrix currentmatrix}bdef
/pom {setmatrix}bdef
/bs {/aString exch def /nXOfs exch def /nWidth exch def currentpoint nXOfs 0 rmoveto pum nWidth aString stringwidth pop div 1 scale aString show pom moveto} bdef
%%EndResource
%%EndProlog
%%BeginSetup
%%EndSetup
%%Page: 1 1
%%BeginPageSetup
%%EndPageSetup
pum
0.02838 0.02838 s
0 -8033 t
/tm matrix currentmatrix def
tm setmatrix
-2275 -2118 t
1 1 s
0.753 0.753 0.753 c 3288 7132 m 2275 7132 l 2275 5104 l 4301 5104 l
4301 7132 l 3288 7132 l p ef
0 lw 1 lj 0.003 0.003 0.003 c 3288 7132 m 2275 7132 l 2275 5104 l 4301 5104 l
4301 7132 l 3288 7132 l pc
gs
pum
2645 6299 t
327 -238 m 323 -357 l 312 -357 l 308 -346 300 -340 289 -340 ct 285 -340 277 -341 269 -344 ct
243 -353 216 -357 192 -357 ct 148 -357 104 -341 71 -312 ct 34 -279 14 -230 14 -171 ct
14 -122 30 -77 57 -47 ct 89 -12 138 7 190 7 ct 250 7 302 -16 334 -59 ct 325 -69 l
286 -31 251 -15 207 -15 ct 174 -15 144 -26 121 -46 ct 92 -72 76 -120 76 -178 ct
76 -274 125 -336 202 -336 ct 232 -336 259 -325 280 -304 ct 297 -287 305 -272 315 -238 ct
p ef
450 -153 m 464 -152 473 -152 487 -152 ct 528 -152 557 -157 579 -170 ct 611 -187 630 -219 630 -254 ct
630 -276 623 -296 609 -312 ct 587 -335 541 -350 492 -350 ct 352 -350 l 352 -340 l
391 -335 396 -330 396 -292 ct 396 -63 l 396 -19 392 -13 352 -10 ct 352 0 l
500 0 l 500 -10 l 458 -11 450 -19 450 -57 ct p
450 -312 m 450 -326 454 -330 468 -330 ct 540 -330 573 -305 573 -251 ct 573 -199 541 -173 481 -173 ct
470 -173 463 -174 450 -175 ct p ef
958 -272 m 958 -326 964 -334 1007 -340 ct 1007 -350 l 885 -350 l 885 -340 l
926 -336 934 -325 934 -272 ct 934 -129 l 934 -93 931 -73 922 -57 ct 908 -32 874 -15 834 -15 ct
797 -15 771 -28 757 -53 ct 747 -70 743 -89 743 -123 ct 743 -292 l 743 -330 749 -336 792 -340 ct
792 -350 l 642 -350 l 642 -340 l 684 -336 690 -331 690 -292 ct 690 -127 l
690 -35 732 7 822 7 ct 880 7 920 -11 940 -47 ct 953 -69 958 -93 958 -134 ct p ef
1139 -357 m 1110 -357 1088 -348 1068 -330 ct 1037 -300 1017 -239 1017 -177 ct
1017 -120 1035 -58 1060 -28 ct 1079 -5 1106 7 1137 7 ct 1164 7 1186 -1 1206 -20 ct
1236 -49 1256 -110 1256 -174 ct 1256 -283 l 1208 -357 l p
1137 -343 m 1182 -343 1206 -284 1206 -173 ct 1206 -62 1182 -6 1137 -6 ct 1091 -6 1068 -62 1068 -172 ct
1068 -285 l 1092 -343 l p ef
pom
gr
0.753 0.753 0.753 c 7182 7132 m 6169 7132 l 6169 5104 l 8195 5104 l
8195 7132 l 7182 7132 l p ef
0.003 0.003 0.003 c 7182 7132 m 6169 7132 l 6169 5104 l 8195 5104 l 8195 7132 l
7182 7132 l pc
gs
pum
6535 6299 t
327 -238 m 323 -357 l 312 -357 l 308 -346 300 -340 289 -340 ct 285 -340 277 -341 269 -344 ct
243 -353 216 -357 192 -357 ct 148 -357 104 -341 71 -312 ct 34 -279 14 -230 14 -171 ct
14 -122 30 -77 57 -47 ct 89 -12 138 7 190 7 ct 250 7 302 -16 334 -59 ct 325 -69 l
286 -31 251 -15 207 -15 ct 174 -15 144 -26 121 -46 ct 92 -72 76 -120 76 -178 ct
76 -274 125 -336 202 -336 ct 232 -336 259 -325 280 -304 ct 297 -287 305 -272 315 -238 ct
p ef
450 -153 m 464 -152 473 -152 487 -152 ct 528 -152 557 -157 579 -170 ct 611 -187 630 -219 630 -254 ct
630 -276 623 -296 609 -312 ct 587 -335 541 -350 492 -350 ct 352 -350 l 352 -340 l
391 -335 396 -330 396 -292 ct 396 -63 l 396 -19 392 -13 352 -10 ct 352 0 l
500 0 l 500 -10 l 458 -11 450 -19 450 -57 ct p
450 -312 m 450 -326 454 -330 468 -330 ct 540 -330 573 -305 573 -251 ct 573 -199 541 -173 481 -173 ct
470 -173 463 -174 450 -175 ct p ef
958 -272 m 958 -326 964 -334 1007 -340 ct 1007 -350 l 885 -350 l 885 -340 l
926 -336 934 -325 934 -272 ct 934 -129 l 934 -93 931 -73 922 -57 ct 908 -32 874 -15 834 -15 ct
797 -15 771 -28 757 -53 ct 747 -70 743 -89 743 -123 ct 743 -292 l 743 -330 749 -336 792 -340 ct
792 -350 l 642 -350 l 642 -340 l 684 -336 690 -331 690 -292 ct 690 -127 l
690 -35 732 7 822 7 ct 880 7 920 -11 940 -47 ct 953 -69 958 -93 958 -134 ct p ef
1158 -357 m 1063 -309 l 1063 -302 l 1070 -304 1075 -306 1078 -307 ct 1087 -311 1096 -313 1101 -313 ct
1112 -313 1117 -305 1117 -288 ct 1117 -49 l 1117 -31 1113 -19 1104 -14 ct 1097 -10 1089 -8 1067 -7 ct
1067 0 l 1213 0 l 1213 -7 l 1171 -8 1163 -13 1163 -39 ct 1163 -356 l p ef
pom
gr
0.753 0.753 0.753 c 3288 4146 m 2275 4146 l 2275 2118 l 4301 2118 l
4301 4146 l 3288 4146 l p ef
0.003 0.003 0.003 c 3288 4146 m 2275 4146 l 2275 2118 l 4301 2118 l 4301 4146 l
3288 4146 l pc
gs
pum
2645 3309 t
327 -238 m 323 -357 l 312 -357 l 308 -346 300 -340 289 -340 ct 285 -340 277 -341 269 -344 ct
243 -353 216 -357 192 -357 ct 148 -357 104 -341 71 -312 ct 34 -279 14 -230 14 -171 ct
14 -122 30 -77 57 -47 ct 89 -12 138 7 190 7 ct 250 7 302 -16 334 -59 ct 325 -69 l
286 -31 251 -15 207 -15 ct 174 -15 144 -26 121 -46 ct 92 -72 76 -120 76 -178 ct
76 -274 125 -336 202 -336 ct 232 -336 259 -325 280 -304 ct 297 -287 305 -272 315 -238 ct
p ef
450 -153 m 464 -152 473 -152 487 -152 ct 528 -152 557 -157 579 -170 ct 611 -187 630 -219 630 -254 ct
630 -276 623 -296 609 -312 ct 587 -335 541 -350 492 -350 ct 352 -350 l 352 -340 l
391 -335 396 -330 396 -292 ct 396 -63 l 396 -19 392 -13 352 -10 ct 352 0 l
500 0 l 500 -10 l 458 -11 450 -19 450 -57 ct p
450 -312 m 450 -326 454 -330 468 -330 ct 540 -330 573 -305 573 -251 ct 573 -199 541 -173 481 -173 ct
470 -173 463 -174 450 -175 ct p ef
958 -272 m 958 -326 964 -334 1007 -340 ct 1007 -350 l 885 -350 l 885 -340 l
926 -336 934 -325 934 -272 ct 934 -129 l 934 -93 931 -73 922 -57 ct 908 -32 874 -15 834 -15 ct
797 -15 771 -28 757 -53 ct 747 -70 743 -89 743 -123 ct 743 -292 l 743 -330 749 -336 792 -340 ct
792 -350 l 642 -350 l 642 -340 l 684 -336 690 -331 690 -292 ct 690 -127 l
690 -35 732 7 822 7 ct 880 7 920 -11 940 -47 ct 953 -69 958 -93 958 -134 ct p ef
1256 -72 m 1249 -75 l 1229 -44 1222 -40 1199 -40 ct 1072 -40 l 1161 -133 l
1208 -182 1229 -222 1229 -263 ct 1229 -316 1186 -357 1131 -357 ct 1102 -357 1074 -345 1055 -324 ct
1038 -306 1030 -289 1021 -252 ct 1032 -249 l 1053 -301 1072 -318 1109 -318 ct
1153 -318 1183 -288 1183 -243 ct 1183 -202 1159 -153 1115 -106 ct 1020 -6 l
1020 0 l 1227 0 l p ef
pom
gr
0.753 0.753 0.753 c 7182 4146 m 6169 4146 l 6169 2118 l 8195 2118 l
8195 4146 l 7182 4146 l p ef
0.003 0.003 0.003 c 7182 4146 m 6169 4146 l 6169 2118 l 8195 2118 l 8195 4146 l
7182 4146 l pc
gs
pum
6535 3309 t
327 -238 m 323 -357 l 312 -357 l 308 -346 300 -340 289 -340 ct 285 -340 277 -341 269 -344 ct
243 -353 216 -357 192 -357 ct 148 -357 104 -341 71 -312 ct 34 -279 14 -230 14 -171 ct
14 -122 30 -77 57 -47 ct 89 -12 138 7 190 7 ct 250 7 302 -16 334 -59 ct 325 -69 l
286 -31 251 -15 207 -15 ct 174 -15 144 -26 121 -46 ct 92 -72 76 -120 76 -178 ct
76 -274 125 -336 202 -336 ct 232 -336 259 -325 280 -304 ct 297 -287 305 -272 315 -238 ct
p ef
450 -153 m 464 -152 473 -152 487 -152 ct 528 -152 557 -157 579 -170 ct 611 -187 630 -219 630 -254 ct
630 -276 623 -296 609 -312 ct 587 -335 541 -350 492 -350 ct 352 -350 l 352 -340 l
391 -335 396 -330 396 -292 ct 396 -63 l 396 -19 392 -13 352 -10 ct 352 0 l
500 0 l 500 -10 l 458 -11 450 -19 450 -57 ct p
450 -312 m 450 -326 454 -330 468 -330 ct 540 -330 573 -305 573 -251 ct 573 -199 541 -173 481 -173 ct
470 -173 463 -174 450 -175 ct p ef
958 -272 m 958 -326 964 -334 1007 -340 ct 1007 -350 l 885 -350 l 885 -340 l
926 -336 934 -325 934 -272 ct 934 -129 l 934 -93 931 -73 922 -57 ct 908 -32 874 -15 834 -15 ct
797 -15 771 -28 757 -53 ct 747 -70 743 -89 743 -123 ct 743 -292 l 743 -330 749 -336 792 -340 ct
792 -350 l 642 -350 l 642 -340 l 684 -336 690 -331 690 -292 ct 690 -127 l
690 -35 732 7 822 7 ct 880 7 920 -11 940 -47 ct 953 -69 958 -93 958 -134 ct p ef
1085 -174 m 1117 -174 1129 -173 1142 -168 ct 1174 -157 1195 -126 1195 -90 ct
1195 -46 1165 -11 1126 -11 ct 1111 -11 1101 -15 1081 -28 ct 1065 -37 1056 -41 1047 -41 ct
1035 -41 1027 -33 1027 -22 ct 1027 -4 1050 7 1087 7 ct 1128 7 1170 -6 1194 -28 ct
1219 -49 1233 -80 1233 -115 ct 1233 -142 1225 -167 1209 -184 ct 1199 -195 1189 -202 1165 -212 ct
1202 -236 1215 -256 1215 -285 ct 1215 -327 1181 -357 1133 -357 ct 1106 -357 1083 -348 1064 -331 ct
1048 -317 1040 -303 1028 -271 ct 1036 -269 l 1058 -308 1082 -325 1115 -325 ct
1149 -325 1173 -302 1173 -269 ct 1173 -250 1165 -231 1152 -217 ct 1136 -202 1121 -194 1085 -181 ct
p ef
pom
gr
0.753 0.753 0.753 c 7182 10118 m 6169 10118 l 6169 8090 l 8195 8090 l
8195 10118 l 7182 10118 l p ef
0.003 0.003 0.003 c 7182 10118 m 6169 10118 l 6169 8090 l 8195 8090 l 8195 10118 l
7182 10118 l pc
gs
pum
6852 8945 t
236 -357 m 225 -357 l 223 -345 217 -339 208 -339 ct 203 -339 194 -341 185 -345 ct
165 -353 146 -357 129 -357 ct 106 -357 83 -348 65 -333 ct 47 -316 37 -294 37 -267 ct
37 -224 60 -195 120 -163 ct 158 -143 185 -122 198 -102 ct 203 -95 206 -84 206 -71 ct
206 -35 179 -11 141 -11 ct 94 -11 60 -40 34 -105 ct 22 -105 l 38 6 l 49 6 l
50 -3 56 -10 64 -10 ct 70 -10 79 -8 89 -4 ct 109 3 130 7 151 7 ct 212 7 259 -34 259 -88 ct
259 -132 230 -166 160 -204 ct 105 -234 83 -258 83 -286 ct 83 -315 105 -335 138 -335 ct
161 -335 184 -325 202 -306 ct 219 -289 226 -276 234 -244 ct 248 -244 l p ef
300 -350 m 300 -340 l 344 -337 350 -331 350 -292 ct 350 -57 l 350 -18 343 -11 300 -10 ct
300 0 l 476 0 l 517 0 555 -11 575 -29 ct 594 -46 604 -69 604 -95 ct 604 -118 595 -139 578 -155 ct
562 -169 548 -175 514 -184 ct 541 -190 552 -196 565 -207 ct 578 -219 586 -238 586 -260 ct
586 -319 539 -350 448 -350 ct p
404 -172 m 456 -172 480 -169 499 -161 ct 529 -149 543 -128 543 -94 ct 543 -66 532 -45 511 -33 ct
494 -23 472 -19 438 -19 ct 412 -19 404 -24 404 -41 ct p
404 -193 m 404 -314 l 404 -325 408 -330 416 -330 ct 439 -330 l 500 -330 532 -305 532 -258 ct
532 -216 504 -193 454 -193 ct p ef
pom
pum
6455 9607 t
156 -357 m 116 -332 101 -318 81 -294 ct 43 -248 25 -195 25 -133 ct 25 -66 44 -14 91 39 ct
113 65 126 76 154 93 ct 160 85 l 118 51 103 33 89 -6 ct 76 -41 70 -82 70 -134 ct
70 -190 77 -233 92 -266 ct 106 -299 122 -318 160 -349 ct p ef
338 -196 m 390 -224 409 -246 409 -282 ct 409 -325 371 -357 318 -357 ct 260 -357 217 -322 217 -274 ct
217 -239 227 -224 283 -175 ct 226 -132 214 -115 214 -79 ct 214 -28 256 7 316 7 ct
379 7 420 -27 420 -82 ct 420 -122 l 402 -148 l p
328 -141 m 367 -114 380 -95 380 -65 ct 380 -31 356 -7 322 -7 ct 281 -7 254 -38 254 -84 ct
254 -117 266 -140 297 -165 ct p
323 -205 m 275 -236 256 -260 256 -290 ct 256 -321 280 -342 314 -342 ct 350 -342 372 -319 372 -283 ct
372 -252 357 -229 327 -208 ct 325 -207 l 325 -207 l p ef
603 -357 m 508 -309 l 508 -302 l 515 -304 520 -306 523 -307 ct 532 -311 541 -313 546 -313 ct
557 -313 562 -305 562 -288 ct 562 -49 l 562 -31 558 -19 549 -14 ct 542 -10 534 -8 512 -7 ct
512 0 l 658 0 l 658 -7 l 616 -8 608 -13 608 -39 ct 608 -356 l p ef
867 -357 m 772 -309 l 772 -302 l 779 -304 784 -306 787 -307 ct 796 -311 805 -313 810 -313 ct
821 -313 826 -305 826 -288 ct 826 -49 l 826 -31 822 -19 813 -14 ct 806 -10 798 -8 776 -7 ct
776 0 l 922 0 l 922 -7 l 880 -8 872 -13 872 -39 ct 872 -356 l p ef
1132 -357 m 1037 -309 l 1037 -302 l 1044 -304 1049 -306 1052 -307 ct 1061 -311 1070 -313 1075 -313 ct
1086 -313 1091 -305 1091 -288 ct 1091 -49 l 1091 -31 1087 -19 1078 -14 ct 1071 -10 1063 -8 1041 -7 ct
1041 0 l 1187 0 l 1187 -7 l 1145 -8 1137 -13 1137 -39 ct 1137 -356 l p ef
1264 93 m 1303 68 1319 54 1338 30 ct 1376 -15 1394 -68 1394 -130 ct 1394 -198 1375 -249 1328 -303 ct
1306 -329 1293 -340 1265 -357 ct 1259 -349 l 1301 -315 1315 -297 1330 -257 ct
1343 -222 1349 -181 1349 -129 ct 1349 -74 1342 -30 1328 2 ct 1313 35 1297 54 1259 85 ct
p ef
pom
gr
0.753 0.753 0.753 c 3288 10118 m 2275 10118 l 2275 8090 l 4301 8090 l
4301 10118 l 3288 10118 l p ef
0.003 0.003 0.003 c 3288 10118 m 2275 10118 l 2275 8090 l 4301 8090 l 4301 10118 l
3288 10118 l pc
gs
pum
2593 8945 t
106 -153 m 120 -152 129 -152 143 -152 ct 184 -152 213 -157 235 -170 ct 267 -187 286 -219 286 -254 ct
286 -276 279 -296 265 -312 ct 243 -335 197 -350 148 -350 ct 8 -350 l 8 -340 l
47 -335 52 -330 52 -292 ct 52 -63 l 52 -19 48 -13 8 -10 ct 8 0 l 156 0 l 156 -10 l
114 -11 106 -19 106 -57 ct p
106 -312 m 106 -326 110 -330 124 -330 ct 196 -330 229 -305 229 -251 ct 229 -199 197 -173 137 -173 ct
126 -173 119 -174 106 -175 ct p ef
618 -238 m 614 -357 l 603 -357 l 599 -346 591 -340 580 -340 ct 576 -340 568 -341 560 -344 ct
534 -353 507 -357 483 -357 ct 439 -357 395 -341 362 -312 ct 325 -279 305 -230 305 -171 ct
305 -122 321 -77 348 -47 ct 380 -12 429 7 481 7 ct 541 7 593 -16 625 -59 ct 616 -69 l
577 -31 542 -15 498 -15 ct 465 -15 435 -26 412 -46 ct 383 -72 367 -120 367 -178 ct
367 -274 416 -336 493 -336 ct 523 -336 550 -325 571 -304 ct 588 -287 596 -272 606 -238 ct
p ef
695 -57 m 695 -17 688 -11 644 -10 ct 644 0 l 801 0 l 801 -10 l 758 -11 749 -19 749 -57 ct
749 -292 l 749 -331 757 -338 801 -340 ct 801 -350 l 644 -350 l 644 -340 l
689 -337 695 -331 695 -292 ct p ef
840 -135 m 840 -102 l 970 -102 l 970 -135 l p ef
1373 -350 m 1247 -350 l 1247 -340 l 1275 -339 1284 -335 1284 -323 ct 1284 -315 1278 -305 1263 -286 ct
1203 -213 l 1181 -244 l 1148 -289 1136 -312 1136 -324 ct 1136 -334 1144 -339 1161 -339 ct
1176 -340 l 1176 -350 l 1016 -350 l 1016 -340 l 1051 -338 1060 -330 1112 -257 ct
1170 -172 l 1087 -70 l 1039 -14 1037 -12 1010 -10 ct 1010 0 l 1133 0 l
1133 -10 l 1102 -12 1093 -16 1093 -28 ct 1093 -36 1101 -49 1120 -74 ct 1183 -152 l
1234 -78 l 1251 -52 1261 -34 1261 -26 ct 1261 -16 1252 -11 1234 -11 ct 1232 -11 1226 -10 1220 -10 ct
1220 0 l 1377 0 l 1377 -10 l 1349 -13 1341 -18 1318 -49 ct 1217 -194 l
1294 -290 l 1328 -331 1339 -338 1373 -340 ct p ef
pom
pum
2566 9607 t
156 -357 m 116 -332 101 -318 81 -294 ct 43 -248 25 -195 25 -133 ct 25 -66 44 -14 91 39 ct
113 65 126 76 154 93 ct 160 85 l 118 51 103 33 89 -6 ct 76 -41 70 -82 70 -134 ct
70 -190 77 -233 92 -266 ct 106 -299 122 -318 160 -349 ct p ef
338 -196 m 390 -224 409 -246 409 -282 ct 409 -325 371 -357 318 -357 ct 260 -357 217 -322 217 -274 ct
217 -239 227 -224 283 -175 ct 226 -132 214 -115 214 -79 ct 214 -28 256 7 316 7 ct
379 7 420 -27 420 -82 ct 420 -122 l 402 -148 l p
328 -141 m 367 -114 380 -95 380 -65 ct 380 -31 356 -7 322 -7 ct 281 -7 254 -38 254 -84 ct
254 -117 266 -140 297 -165 ct p
323 -205 m 275 -236 256 -260 256 -290 ct 256 -321 280 -342 314 -342 ct 350 -342 372 -319 372 -283 ct
372 -252 357 -229 327 -208 ct 325 -207 l 325 -207 l p ef
603 -357 m 508 -309 l 508 -302 l 515 -304 520 -306 523 -307 ct 532 -311 541 -313 546 -313 ct
557 -313 562 -305 562 -288 ct 562 -49 l 562 -31 558 -19 549 -14 ct 542 -10 534 -8 512 -7 ct
512 0 l 658 0 l 658 -7 l 616 -8 608 -13 608 -39 ct 608 -356 l p ef
794 -174 m 826 -174 838 -173 851 -168 ct 883 -157 904 -126 904 -90 ct 904 -46 874 -11 835 -11 ct
820 -11 810 -15 790 -28 ct 774 -37 765 -41 756 -41 ct 744 -41 736 -33 736 -22 ct
736 -4 759 7 796 7 ct 837 7 879 -6 903 -28 ct 928 -49 942 -80 942 -115 ct 942 -142 934 -167 918 -184 ct
908 -195 898 -202 874 -212 ct 911 -236 924 -256 924 -285 ct 924 -327 890 -357 842 -357 ct
815 -357 792 -348 773 -331 ct 757 -317 749 -303 737 -271 ct 745 -269 l 767 -308 791 -325 824 -325 ct
858 -325 882 -302 882 -269 ct 882 -250 874 -231 861 -217 ct 845 -202 830 -194 794 -181 ct
p ef
1132 -357 m 1037 -309 l 1037 -302 l 1044 -304 1049 -306 1052 -307 ct 1061 -311 1070 -313 1075 -313 ct
1086 -313 1091 -305 1091 -288 ct 1091 -49 l 1091 -31 1087 -19 1078 -14 ct 1071 -10 1063 -8 1041 -7 ct
1041 0 l 1187 0 l 1187 -7 l 1145 -8 1137 -13 1137 -39 ct 1137 -356 l p ef
1264 93 m 1303 68 1319 54 1338 30 ct 1376 -15 1394 -68 1394 -130 ct 1394 -198 1375 -249 1328 -303 ct
1306 -329 1293 -340 1265 -357 ct 1259 -349 l 1301 -315 1315 -297 1330 -257 ct
1343 -222 1349 -181 1349 -129 ct 1349 -74 1342 -30 1328 2 ct 1313 35 1297 54 1259 85 ct
p ef
pom
gr
3288 7132 m 3288 8090 l ps
4301 9104 m 6169 9104 l ps
4301 6118 m 6169 6118 l ps
3288 5104 m 3288 4146 l ps
7182 5104 m 7182 4146 l ps
6169 3132 m 4301 3132 l ps
gs
pum
3360 7489 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
653 -190 m 638 -190 626 -185 615 -175 ct 599 -160 588 -127 588 -94 ct 588 -64 598 -31 611 -15 ct
621 -2 636 3 652 3 ct 666 3 679 0 689 -10 ct 705 -26 716 -58 716 -93 ct 716 -150 l
690 -190 l p
652 -183 m 676 -183 689 -151 689 -92 ct 689 -33 676 -3 652 -3 ct 628 -3 615 -33 615 -92 ct
615 -152 l 628 -183 l p ef
pom
gr
gs
pum
5424 6484 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
653 -190 m 638 -190 626 -185 615 -175 ct 599 -160 588 -127 588 -94 ct 588 -64 598 -31 611 -15 ct
621 -2 636 3 652 3 ct 666 3 679 0 689 -10 ct 705 -26 716 -58 716 -93 ct 716 -150 l
690 -190 l p
652 -183 m 676 -183 689 -151 689 -92 ct 689 -33 676 -3 652 -3 ct 628 -3 615 -33 615 -92 ct
615 -152 l 628 -183 l p ef
pom
gr
gs
pum
7302 4446 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
653 -190 m 638 -190 626 -185 615 -175 ct 599 -160 588 -127 588 -94 ct 588 -64 598 -31 611 -15 ct
621 -2 636 3 652 3 ct 666 3 679 0 689 -10 ct 705 -26 716 -58 716 -93 ct 716 -150 l
690 -190 l p
652 -183 m 676 -183 689 -151 689 -92 ct 689 -33 676 -3 652 -3 ct 628 -3 615 -33 615 -92 ct
615 -152 l 628 -183 l p ef
pom
gr
gs
pum
3413 4473 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
653 -190 m 638 -190 626 -185 615 -175 ct 599 -160 588 -127 588 -94 ct 588 -64 598 -31 611 -15 ct
621 -2 636 3 652 3 ct 666 3 679 0 689 -10 ct 705 -26 716 -58 716 -93 ct 716 -150 l
690 -190 l p
652 -183 m 676 -183 689 -151 689 -92 ct 689 -33 676 -3 652 -3 ct 628 -3 615 -33 615 -92 ct
615 -152 l 628 -183 l p ef
pom
gr
gs
pum
4418 3467 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
664 -190 m 613 -164 l 613 -161 l 616 -162 619 -163 620 -164 ct 625 -166 630 -167 633 -167 ct
639 -167 642 -163 642 -153 ct 642 -26 l 642 -16 639 -10 635 -7 ct 631 -5 627 -4 615 -4 ct
615 0 l 693 0 l 693 -4 l 670 -4 666 -7 666 -20 ct 666 -190 l p ef
pom
gr
gs
pum
2513 5002 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
715 -38 m 712 -40 l 701 -23 698 -21 685 -21 ct 618 -21 l 665 -71 l 690 -97 701 -118 701 -140 ct
701 -168 678 -190 649 -190 ct 633 -190 619 -184 608 -173 ct 599 -163 595 -154 590 -134 ct
596 -133 l 607 -160 618 -169 637 -169 ct 661 -169 677 -153 677 -130 ct 677 -108 664 -81 640 -56 ct
590 -3 l 590 0 l 700 0 l p ef
pom
gr
gs
pum
5397 3044 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
664 -190 m 613 -164 l 613 -161 l 616 -162 619 -163 620 -164 ct 625 -166 630 -167 633 -167 ct
639 -167 642 -163 642 -153 ct 642 -26 l 642 -16 639 -10 635 -7 ct 631 -5 627 -4 615 -4 ct
615 0 l 693 0 l 693 -4 l 670 -4 666 -7 666 -20 ct 666 -190 l p ef
pom
gr
gs
pum
6376 5028 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
664 -190 m 613 -164 l 613 -161 l 616 -162 619 -163 620 -164 ct 625 -166 630 -167 633 -167 ct
639 -167 642 -163 642 -153 ct 642 -26 l 642 -16 639 -10 635 -7 ct 631 -5 627 -4 615 -4 ct
615 0 l 693 0 l 693 -4 l 670 -4 666 -7 666 -20 ct 666 -190 l p ef
pom
gr
gs
pum
4524 6060 t
161 -49 m 156 -38 152 -31 148 -27 ct 138 -16 123 -11 99 -11 ct 80 -11 l 60 -11 56 -12 56 -22 ct
56 -155 l 56 -175 60 -179 82 -181 ct 82 -186 l 3 -186 l 3 -181 l 24 -179 27 -175 27 -155 ct
27 -30 l 27 -11 23 -6 3 -5 ct 3 0 l 155 0 l 168 -49 l p ef
214 -30 m 214 -10 210 -6 189 -5 ct 189 0 l 269 0 l 302 0 331 -9 349 -25 ct
367 -41 378 -66 378 -94 ct 378 -119 369 -141 354 -157 ct 335 -176 304 -186 265 -186 ct
189 -186 l 189 -181 l 211 -179 214 -176 214 -155 ct p
243 -165 m 243 -174 246 -176 257 -176 ct 282 -176 300 -171 313 -162 ct 335 -146 347 -122 347 -92 ct
347 -58 335 -35 313 -22 ct 298 -13 282 -10 257 -10 ct 246 -10 243 -12 243 -22 ct
p ef
468 -174 m 468 -33 l 468 -9 465 -6 442 -5 ct 442 0 l 524 0 l 524 -5 l
501 -6 497 -10 497 -30 ct 497 -174 l 512 -174 l 544 -174 550 -169 557 -138 ct
564 -138 l 562 -186 l 403 -186 l 401 -138 l 408 -138 l 415 -169 421 -174 453 -174 ct
p ef
664 -190 m 613 -164 l 613 -161 l 616 -162 619 -163 620 -164 ct 625 -166 630 -167 633 -167 ct
639 -167 642 -163 642 -153 ct 642 -26 l 642 -16 639 -10 635 -7 ct 631 -5 627 -4 615 -4 ct
615 0 l 693 0 l 693 -4 l 670 -4 666 -7 666 -20 ct 666 -190 l p ef
pom
gr
1.000 0.003 0.003 c 4303 6248 m 4229 6248 4169 6187 4169 6113 ct 4169 6039 4229 5978 4303 5978 ct
4377 5978 4437 6039 4437 6113 ct 4437 6187 4377 6248 4303 6248 ct 4303 6248 l
p ef
0.003 0.003 0.003 c 4303 6248 m 4229 6248 4169 6187 4169 6113 ct 4169 6039 4229 5978 4303 5978 ct
4377 5978 4437 6039 4437 6113 ct 4437 6187 4377 6248 4303 6248 ct 4303 6248 l
pc
1.000 0.003 0.003 c 7216 5229 m 7142 5229 7082 5169 7082 5095 ct 7082 5021 7142 4961 7216 4961 ct
7290 4961 7350 5021 7350 5095 ct 7350 5169 7290 5229 7216 5229 ct 7216 5229 l
p ef
0.003 0.003 0.003 c 7216 5229 m 7142 5229 7082 5169 7082 5095 ct 7082 5021 7142 4961 7216 4961 ct
7290 4961 7350 5021 7350 5095 ct 7350 5169 7290 5229 7216 5229 ct 7216 5229 l
pc
1.000 0.003 0.003 c 6179 3279 m 6105 3279 6045 3219 6045 3145 ct 6045 3071 6105 3011 6179 3011 ct
6253 3011 6313 3071 6313 3145 ct 6313 3219 6253 3279 6179 3279 ct 6179 3279 l
p ef
0.003 0.003 0.003 c 6179 3279 m 6105 3279 6045 3219 6045 3145 ct 6045 3071 6105 3011 6179 3011 ct
6253 3011 6313 3071 6313 3145 ct 6313 3219 6253 3279 6179 3279 ct 6179 3279 l
pc
tm setmatrix
0 0 t
1 1 s
0 8033 t
pom
count op_count sub {pop} repeat countdictstack dict_count sub {end} repeat b4_inc_state restore
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%%Trailer
%%EOF

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@ -0,0 +1,59 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
width="256px" height="512px" viewBox="0 0 256 512" enable-background="new 0 0 256 512" xml:space="preserve">
<font horiz-adv-x="2048">
<font-face font-family="ArialMT" units-per-em="2048" underline-position="-217" underline-thickness="150"/>
<missing-glyph horiz-adv-x="1536" d="M256,0l0,1280l1024,0l0,-1280M288,32l960,0l0,1216l-960,0z"/>
<glyph unicode=" " horiz-adv-x="569"/>
<glyph unicode="(" horiz-adv-x="682" d="M479,-431C380,-306 296,-159 227,9C158,177 124,351 124,531C124,690 150,842 201,987C261,1156 354,1324 479,1491l129,0C527,1352 474,1253 448,1194C407,1102 375,1006 352,906C323,781 309,656 309,530C309,209 409,-111 608,-431z"/>
<glyph unicode=")" horiz-adv-x="682" d="M253,-431l-129,0C323,-111 423,209 423,530C423,655 409,780 380,903C357,1003 326,1099 285,1191C259,1251 205,1351 124,1491l129,0C378,1324 471,1156 531,987C582,842 608,690 608,531C608,351 574,177 505,9C436,-159 352,-306 253,-431z"/>
<glyph unicode="-" horiz-adv-x="682" d="M65,440l0,181l553,0l0,-181z"/>
<glyph unicode="0" horiz-adv-x="1139" d="M85,723C85,896 103,1036 139,1142C174,1247 227,1329 298,1386C368,1443 456,1472 563,1472C642,1472 711,1456 770,1425C829,1393 878,1347 917,1288C956,1228 986,1155 1008,1070C1030,984 1041,868 1041,723C1041,551 1023,412 988,307C953,201 900,119 830,62C759,4 670,-25 563,-25C422,-25 311,26 230,127C133,249 85,448 85,723M270,723C270,482 298,322 355,243C411,163 480,123 563,123C646,123 715,163 772,243C828,323 856,483 856,723C856,964 828,1125 772,1204C715,1283 645,1323 561,1323C478,1323 412,1288 363,1218C301,1129 270,964 270,723z"/>
<glyph unicode="1" horiz-adv-x="1139" d="M763,0l-180,0l0,1147C540,1106 483,1064 413,1023C342,982 279,951 223,930l0,174C324,1151 412,1209 487,1276C562,1343 616,1409 647,1472l116,0z"/>
<glyph unicode="2" horiz-adv-x="1139" d="M1031,173l0,-173l-969,0C61,43 68,85 83,125C108,191 147,256 202,320C256,384 334,458 437,542C596,673 704,776 760,853C816,929 844,1001 844,1069C844,1140 819,1201 768,1250C717,1299 650,1323 568,1323C481,1323 412,1297 360,1245C308,1193 282,1121 281,1029l-185,19C109,1186 156,1291 239,1364C322,1436 433,1472 572,1472C713,1472 824,1433 906,1355C988,1277 1029,1180 1029,1065C1029,1006 1017,949 993,892C969,835 929,776 874,713C818,650 725,564 596,455C488,364 419,303 388,271C357,238 332,206 312,173z"/>
<glyph unicode="3" horiz-adv-x="1139" d="M86,387l180,24C287,309 322,236 372,191C421,146 482,123 553,123C638,123 709,152 768,211C826,270 855,342 855,429C855,512 828,580 774,634C720,687 651,714 568,714C534,714 492,707 441,694l20,158C473,851 483,850 490,850C567,850 636,870 697,910C758,950 789,1012 789,1095C789,1161 767,1216 722,1259C677,1302 620,1324 549,1324C479,1324 421,1302 374,1258C327,1214 297,1148 284,1060l-180,32C126,1213 176,1306 254,1373C332,1439 429,1472 545,1472C625,1472 699,1455 766,1421C833,1386 885,1339 921,1280C956,1221 974,1158 974,1091C974,1028 957,970 923,918C889,866 839,825 772,794C859,774 926,733 974,670C1022,607 1046,528 1046,433C1046,305 999,197 906,108C813,19 695,-26 552,-26C423,-26 317,12 232,89C147,166 98,265 86,387z"/>
<glyph unicode="8" horiz-adv-x="1139" d="M362,795C287,822 232,861 196,912C160,963 142,1023 142,1094C142,1201 180,1290 257,1363C334,1436 436,1472 563,1472C691,1472 794,1435 872,1361C950,1286 989,1196 989,1089C989,1021 971,962 936,912C900,861 846,822 773,795C863,766 932,718 979,653C1026,588 1049,510 1049,419C1049,294 1005,188 916,103C827,18 711,-25 566,-25C421,-25 305,18 216,104C127,189 83,296 83,424C83,519 107,599 156,664C204,728 273,772 362,795M326,1100C326,1031 348,974 393,930C438,886 496,864 567,864C636,864 693,886 738,930C782,973 804,1027 804,1090C804,1156 781,1212 736,1257C690,1302 633,1324 565,1324C496,1324 439,1302 394,1258C349,1214 326,1161 326,1100M268,423C268,372 280,322 305,274C329,226 365,189 413,163C461,136 513,123 568,123C654,123 725,151 781,206C837,261 865,332 865,417C865,504 836,575 779,632C721,689 649,717 562,717C477,717 407,689 352,633C296,577 268,507 268,423z"/>
<glyph unicode="B" horiz-adv-x="1366" d="M150,0l0,1466l550,0C812,1466 902,1451 970,1422C1037,1392 1090,1346 1129,1285C1167,1223 1186,1158 1186,1091C1186,1028 1169,969 1135,914C1101,859 1050,814 981,780C1070,754 1138,710 1186,647C1233,584 1257,510 1257,425C1257,356 1243,293 1214,234C1185,175 1149,129 1106,97C1063,65 1010,41 946,25C881,8 802,0 709,0M344,850l317,0C747,850 809,856 846,867C895,882 933,906 958,940C983,974 995,1017 995,1068C995,1117 983,1160 960,1197C937,1234 903,1259 860,1273C817,1286 742,1293 637,1293l-293,0M344,173l365,0C772,173 816,175 841,180C886,188 923,201 953,220C983,239 1008,266 1027,302C1046,337 1056,378 1056,425C1056,480 1042,527 1014,568C986,608 947,636 898,653C848,669 776,677 683,677l-339,0z"/>
<glyph unicode="C" horiz-adv-x="1479" d="M1204,514l194,-49C1357,306 1284,184 1179,101C1073,17 944,-25 791,-25C633,-25 505,7 406,72C307,136 231,229 180,351C128,473 102,604 102,744C102,897 131,1030 190,1144C248,1257 331,1344 439,1403C546,1462 665,1491 794,1491C941,1491 1064,1454 1164,1379C1264,1304 1334,1199 1373,1064l-191,-45C1148,1126 1099,1203 1034,1252C969,1301 888,1325 790,1325C677,1325 583,1298 508,1244C432,1190 379,1118 348,1027C317,936 302,842 302,745C302,620 320,512 357,419C393,326 449,256 526,210C603,164 686,141 775,141C884,141 976,172 1051,235C1126,298 1177,391 1204,514z"/>
<glyph unicode="D" horiz-adv-x="1479" d="M158,0l0,1466l505,0C777,1466 864,1459 924,1445C1008,1426 1080,1391 1139,1340C1216,1275 1274,1191 1313,1090C1351,988 1370,872 1370,741C1370,630 1357,531 1331,445C1305,359 1272,288 1231,232C1190,175 1146,131 1098,99C1049,66 991,42 923,25C854,8 776,0 687,0M352,173l313,0C762,173 838,182 893,200C948,218 991,243 1024,276C1070,322 1106,384 1132,462C1157,539 1170,633 1170,744C1170,897 1145,1015 1095,1098C1044,1180 983,1235 911,1263C859,1283 775,1293 660,1293l-308,0z"/>
<glyph unicode="I" horiz-adv-x="569" d="M191,0l0,1466l194,0l0,-1466z"/>
<glyph unicode="L" horiz-adv-x="1139" d="M150,0l0,1466l194,0l0,-1293l722,0l0,-173z"/>
<glyph unicode="P" horiz-adv-x="1366" d="M158,0l0,1466l553,0C808,1466 883,1461 934,1452C1006,1440 1066,1417 1115,1384C1164,1350 1203,1303 1233,1242C1262,1181 1277,1115 1277,1042C1277,917 1237,812 1158,726C1079,639 935,596 728,596l-376,0l0,-596M352,769l379,0C856,769 945,792 998,839C1051,886 1077,951 1077,1036C1077,1097 1062,1150 1031,1194C1000,1237 959,1266 908,1280C875,1289 815,1293 727,1293l-375,0z"/>
<glyph unicode="S" horiz-adv-x="1366" d="M92,471l183,16C284,414 304,354 336,307C367,260 416,222 483,193C550,164 625,149 708,149C782,149 847,160 904,182C961,204 1003,234 1031,273C1058,311 1072,353 1072,398C1072,444 1059,484 1032,519C1005,553 961,582 900,605C861,620 774,644 639,677C504,709 410,739 356,768C286,805 234,850 200,905C165,959 148,1020 148,1087C148,1161 169,1230 211,1295C253,1359 314,1408 395,1441C476,1474 565,1491 664,1491C773,1491 869,1474 952,1439C1035,1404 1098,1352 1143,1284C1188,1216 1212,1139 1215,1053l-186,-14C1019,1132 985,1202 928,1249C870,1296 785,1320 672,1320C555,1320 469,1299 416,1256C362,1213 335,1161 335,1100C335,1047 354,1004 392,970C429,936 527,901 685,866C842,830 950,799 1009,772C1094,733 1157,683 1198,623C1239,562 1259,493 1259,414C1259,336 1237,263 1192,194C1147,125 1083,71 1000,33C916,-6 822,-25 717,-25C584,-25 473,-6 384,33C294,72 224,130 173,208C122,285 95,373 92,471z"/>
<glyph unicode="T" horiz-adv-x="1251" d="M531,0l0,1293l-483,0l0,173l1162,0l0,-173l-485,0l0,-1293z"/>
<glyph unicode="U" horiz-adv-x="1479" d="M1120,1466l194,0l0,-847C1314,472 1297,355 1264,268C1231,181 1171,111 1084,57C997,2 882,-25 741,-25C604,-25 491,-1 404,46C317,93 254,162 217,252C180,341 161,464 161,619l0,847l194,0l0,-846C355,493 367,399 391,339C414,278 455,232 513,199C570,166 641,150 724,150C867,150 968,182 1029,247C1090,312 1120,436 1120,620z"/>
<glyph unicode="X" horiz-adv-x="1366" d="M9,0l567,764l-500,702l231,0l266,-376C628,1012 668,952 691,910C724,963 762,1019 807,1077l295,389l211,0l-515,-691l555,-775l-240,0l-369,523C723,553 702,586 680,621C647,568 624,531 610,511l-368,-511z"/>
</font>
<rect x="7.465" y="10.627" fill="#A0A0A0" stroke="#000000" width="80.473" height="80.473"/>
<rect x="150.491" y="10.923" fill="#A0A0A0" stroke="#000000" width="80.474" height="80.178"/>
<rect x="8.479" y="129.379" fill="#A0A0A0" stroke="#000000" width="80.473" height="80.473"/>
<rect x="150.491" y="129.674" fill="#A0A0A0" stroke="#000000" width="80.474" height="80.178"/>
<rect x="8.479" y="241.805" fill="#A0A0A0" stroke="#000000" width="80.473" height="80.473"/>
<rect x="150.491" y="242.1" fill="#A0A0A0" stroke="#000000" width="80.474" height="80.177"/>
<line fill="none" stroke="#000000" x1="48.716" y1="91.101" x2="48.716" y2="129.379"/>
<line fill="none" stroke="#000000" x1="88.953" y1="50.864" x2="150.491" y2="51.012"/>
<line fill="none" stroke="#000000" x1="88.953" y1="169.763" x2="150.491" y2="169.763"/>
<line fill="none" stroke="#000000" x1="190.729" y1="91.101" x2="190.729" y2="129.379"/>
<line fill="none" stroke="#000000" x1="48.716" y1="209.852" x2="48.716" y2="241.805"/>
<line fill="none" stroke="#000000" x1="88.953" y1="282.189" x2="150.491" y2="282.189"/>
<text transform="matrix(1 0 0 1 23.6948 57.3003)" font-family="'ArialMT'" font-size="18">CPU2</text>
<text transform="matrix(1 0 0 1 22.3374 174.46)" font-family="'ArialMT'" font-size="18">CPU0</text>
<text transform="matrix(1 0 0 1 169.082 55.1167)" font-family="'ArialMT'" font-size="18">CPU3</text>
<text transform="matrix(1 0 0 1 169.082 175.8271)" font-family="'ArialMT'" font-size="18">CPU1</text>
<text transform="matrix(1 0 0 1 22.6807 277.1895)"><tspan x="0" y="0" font-family="'ArialMT'" font-size="18">PCI-X</tspan><tspan x="0" y="21.601" font-family="'ArialMT'" font-size="18">(8131)</tspan></text>
<text transform="matrix(1 0 0 1 169.082 275.1895)"><tspan x="0" y="0" font-family="'ArialMT'" font-size="18"> SB</tspan><tspan x="0" y="21.6" font-family="'ArialMT'" font-size="18">(8111)</tspan></text>
<text transform="matrix(1 0 0 1 93.0947 63.8721)" font-family="'ArialMT'" font-size="10">LDT1</text>
<text transform="matrix(1 0 0 1 124.5088 46.7715)" font-family="'ArialMT'" font-size="10">LDT1</text>
<text transform="matrix(1 0 0 1 196.6982 102.9844)" font-family="'ArialMT'" font-size="10">LDT0</text>
<text transform="matrix(1 0 0 1 161.1953 126.0615)" font-family="'ArialMT'" font-size="10">LDT1</text>
<text transform="matrix(1 0 0 1 22.3374 126.0615)" font-family="'ArialMT'" font-size="10">LDT2</text>
<text transform="matrix(1 0 0 1 55.2783 103.5767)" font-family="'ArialMT'" font-size="10">LDT0</text>
<text transform="matrix(1 0 0 1 52.9111 221.3276)" font-family="'ArialMT'" font-size="10">LDT0</text>
<text transform="matrix(1 0 0 1 93.0947 181.6719)" font-family="'ArialMT'" font-size="10">LDT1</text>
<text transform="matrix(1 0 0 1 124.5088 166.2979)" font-family="'ArialMT'" font-size="10">LDT0</text>
<ellipse fill="#FF0606" cx="150.491" cy="51.012" rx="4.438" ry="4.563"/>
<ellipse fill="#FF0606" cx="88.953" cy="169.763" rx="4.438" ry="4.563"/>
<ellipse fill="#FF0606" cx="190.729" cy="129.379" rx="4.438" ry="4.563"/>
</svg>

After

Width:  |  Height:  |  Size: 11 KiB

67
payloads/bayou/Makefile Normal file
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##
## This file is part of the bayou project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
CONFIG_LZMA=y
CONFIG_NRV2B=y
CONFIG_BUILTIN_LAR=y
PBUILDER_CONFIG=bayou.xml
BUILTIN_LAR=builtin.lar
LIBPAYLOAD_DIR := ../libpayload
CC=gcc
FFLAGS-y=
FFLAGS-$(CONFIG_BUILTIN_LAR) += -DCONFIG_BUILTIN_LAR
FFLAGS-$(CONFIG_LZMA) += -DCONFIG_LZMA
FFLAGS-$(CONFIG_NRV2B) += -DCONFIG_NRV2B
OBJECTS-y=main.o payload.o config.o menu.o self.o
OBJECTS-$(CONFIG_LZMA) += lzma.o
OBJECTS-$(CONFIG_NRV2B) += nrv2b.o
OBJECTS-$(CONFIG_BUILTIN_LAR) += builtin-lar.o
CFLAGS= -Wall -Werror -Os $(FFLAGS-y)
LDFLAGS=-Wl,-T,bayou.ldscript -static
LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name)
LPCC=$(LIBPAYLOAD_DIR)/bin/lpgcc
bayou.elf: $(OBJECTS-y)
$(LPCC) $(LDFLAGS) -m32 -o $@ $(OBJECTS-y)
@ strip $@
builtin-lar.o: $(BUILTIN_LAR)
@ objcopy -I binary -B i386 -O elf32-i386 $(BUILTIN_LAR) $@
builtin.lar: util/pbuilder/pbuilder
@ rm -f $@
util/pbuilder/pbuilder -c $(PBUILDER_CONFIG) create $@
util/pbuilder/pbuilder:
make -C util/pbuilder
%.o: %.c
$(LPCC) $(CFLAGS) -c -o $@ $<
clean:
rm -f *.o bayou.elf builtin.lar
make -C util/pbuilder clean

87
payloads/bayou/bayou.h Normal file
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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef BAYOU_H_
#define BAYOU_H_
#include <libpayload.h>
#define BAYOU_MAX_ENTRIES 10
struct bpt_config {
u32 id;
u8 timeout;
u8 entries;
u8 padding[10];
};
struct bpt_pentry {
u8 index;
u8 parent;
u8 type;
u8 flags;
u8 title[64];
u8 nlen;
};
#define BPT_ID 0x30545042
#define BPT_TYPE_CHOOSER 0x01
#define BPT_TYPE_CHAIN 0x02
#define BPT_TYPE_SUBCHAIN 0x03
#define BPT_FLAG_DEFAULT 0x01
#define BPT_FLAG_NOSHOW 0x02
enum bayou_params {
BAYOU_PARAM_NAME = 0,
BAYOU_PARAM_LIST,
BAYOU_PARAM_DESC,
BAYOU_PARAMS_COUNT
};
struct payload {
struct bpt_pentry pentry;
struct larstat stat;
u8 *fptr;
char *params[BAYOU_PARAMS_COUNT];
};
struct bayoucfg {
u8 timeout;
int n_entries;
struct payload entries[BAYOU_MAX_ENTRIES];
};
extern struct bayoucfg bayoucfg;
int verify_self(u8 *ptr);
int self_get_params(u8 *fptr, u8 **params);
int self_load_and_run(struct payload *p, int *ret);
void menu(void);
void run_payload(struct payload *p);
char *payload_get_name(struct payload *p);
struct payload *payload_get_default(void);
void run_payload_timeout(struct payload *p, int timeout);
void payload_parse_params(struct payload *pload, u8 *params, int len);
int get_configuration(struct LAR *lar);
#endif

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
BASE_ADDRESS = 0x19000;
OUTPUT_FORMAT(elf32-i386)
OUTPUT_ARCH(i386)
ENTRY(_entry)
HEAP_SIZE = 16384;
STACK_SIZE = 16384;
SECTIONS
{
. = BASE_ADDRESS;
. = ALIGN(16);
_start = .;
.text : {
*(.text._entry)
*(.text)
*(.text.*)
}
.rodata : {
*(.rodata)
*(.rodata.*)
}
.data : {
*(.data)
*(.data.*)
}
_edata = .;
.bss : {
*(.bss)
*(.bss.*)
*(COMMON)
/* Stack and heap */
. = ALIGN(16);
_heap = .;
. += HEAP_SIZE;
. = ALIGN(16);
_eheap = .;
_estack = .;
. += STACK_SIZE;
. = ALIGN(16);
_stack = .;
}
_end = .;
/DISCARD/ : { *(.comment) *(.note) *(.note.*) }
}

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<!--
## This file is part of the bayou project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-->
<!-- Sample Bayou config file. Adapt as needed, then rename to bayou.xml. -->
<BayouConfig>
<global>
<timeout>10</timeout>
</global>
<payloads>
<payload type="chain" flags="default">
<title>Default Chain</title>
<chain>
<file>payloads/passwd.elf</file>
<lar>passwd</lar>
</chain>
<chain>
<file>payloads/coreinfo.elf</file>
</chain>
</payload>
<payload type="chooser">
<file>payloads/coreinfo.elf</file>
</payload>
</payloads>
</BayouConfig>

165
payloads/bayou/config.c Normal file
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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "bayou.h"
struct bayoucfg bayoucfg;
static int add_payload(struct LAR *lar, struct larent *larent)
{
struct payload *payload;
int plen;
u8 *params = NULL;
u8 *fptr;
if (bayoucfg.n_entries == BAYOU_MAX_ENTRIES)
return -1;
payload = &bayoucfg.entries[bayoucfg.n_entries];
if (strncmp((char *)larent->name, "payload/", 8))
return -1;
if (larstat(lar, (const char *)larent->name, &payload->stat))
return -1;
/* Make sure the LAR entry is valid. */
if (!lfverify(lar, (const char *)larent->name))
return -1;
/* Get a pointer to the start of the file. */
fptr = larfptr(lar, (const char *)larent->name);
if (fptr == NULL)
return -1;
if (!verify_self(fptr))
return -1;
payload->pentry.index = bayoucfg.n_entries;
payload->pentry.parent = 0;
payload->pentry.type = BPT_TYPE_CHOOSER;
payload->pentry.flags = 0;
plen = self_get_params(fptr, &params);
payload_parse_params(payload, params, plen);
payload->fptr = fptr;
bayoucfg.n_entries++;
return 0;
}
static int lar_walk_files(struct LAR *lar,
int (*cb) (struct LAR *, struct larent *))
{
struct larent *larent;
int ret = 0;
rewindlar(lar);
while ((larent = readlar(lar)) != NULL) {
if ((ret = cb(lar, larent)))
break;
}
return ret;
}
/**
* If reading the bayou_payload_table fails for some reason, then construct
* a dummy table. All valid payloads in the lar are added as chooser items.
*/
static void build_dummy_table(struct LAR *lar)
{
bayoucfg.timeout = 0xFF;
bayoucfg.n_entries = 0;
lar_walk_files(lar, add_payload);
}
int get_configuration(struct LAR *lar)
{
struct larstat stat;
struct bpt_config *bptcfg;
u8 *fptr, *ptr;
int i;
/*
* If bayou_payload_table doesn't exist, then dummy up
* a table from the LAR contents.
*/
if (larstat(lar, "bayou_payload_table", &stat) ||
!lfverify(lar, "bayou_payload_table"))
build_dummy_table(lar);
/* Open up the BPT and get the creamy goodness within. */
fptr = larfptr(lar, "bayou_payload_table");
if (fptr == NULL)
build_dummy_table(lar);
bptcfg = (struct bpt_config *)fptr;
bayoucfg.timeout = bptcfg->timeout;
bayoucfg.n_entries = bptcfg->entries;
if (bayoucfg.n_entries > BAYOU_MAX_ENTRIES) {
printf("W: Limiting the number of entries to %d\n",
BAYOU_MAX_ENTRIES);
bayoucfg.n_entries = BAYOU_MAX_ENTRIES;
}
ptr = fptr + sizeof(struct bpt_config);
for (i = 0; i < bayoucfg.n_entries; i++) {
struct bpt_pentry *entry = (struct bpt_pentry *)ptr;
struct payload *p = &(bayoucfg.entries[i]);
int plen;
u8 *params = NULL;
memcpy(&p->pentry, entry, sizeof(struct bpt_pentry));
if (entry->type != BPT_TYPE_CHAIN) {
char *lname = (char *)ptr + sizeof(struct bpt_pentry);
if (larstat(lar, (const char *)lname, &p->stat))
build_dummy_table(lar);
if (!lfverify(lar, (const char *)lname))
build_dummy_table(lar);
fptr = larfptr(lar, (const char *)lname);
if (verify_self(fptr))
p->fptr = fptr;
else
build_dummy_table(lar);
plen = self_get_params(fptr, &params);
payload_parse_params(p, params, plen);
}
ptr += sizeof(struct bpt_pentry) + entry->nlen;
}
return 0;
}

43
payloads/bayou/lzma.c Normal file
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/*
Coreboot interface to memory-saving variant of LZMA decoder
(C)opyright 2006 Carl-Daniel Hailfinger
Released under the GNU GPL v2 or later
Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA
SDK 4.42, which is written and distributed to public domain by Igor Pavlov.
*/
#include <libpayload.h>
#include "lzmadecode.c"
unsigned long ulzma(u8 *src, u8 *dst)
{
unsigned char properties[LZMA_PROPERTIES_SIZE];
UInt32 outSize;
SizeT inProcessed;
SizeT outProcessed;
int res;
CLzmaDecoderState state;
SizeT mallocneeds;
unsigned char scratchpad[15980];
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printf("Incorrect stream properties\n");
}
mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
if (mallocneeds > 15980) {
printf("Decoder scratchpad too small!\n");
}
state.Probs = (CProb *)scratchpad;
res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed,
dst, outSize, &outProcessed);
if (res != 0) {
printf("Decoding error = %d\n", res);
}
return outSize;
}

398
payloads/bayou/lzmadecode.c Normal file
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/*
LzmaDecode.c
LZMA Decoder (optimized for Speed version)
LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
http://www.7-zip.org/
LZMA SDK is licensed under two licenses:
1) GNU Lesser General Public License (GNU LGPL)
2) Common Public License (CPL)
It means that you can select one of these two licenses and
follow rules of that license.
SPECIAL EXCEPTION:
Igor Pavlov, as the author of this Code, expressly permits you to
statically or dynamically link your Code (or bind by name) to the
interfaces of this file without subjecting your linked Code to the
terms of the CPL or GNU LGPL. Any modifications or additions
to this file, however, are subject to the LGPL or CPL terms.
*/
#include "lzmadecode.h"
#define kNumTopBits 24
#define kTopValue ((UInt32)1 << kNumTopBits)
#define kNumBitModelTotalBits 11
#define kBitModelTotal (1 << kNumBitModelTotalBits)
#define kNumMoveBits 5
#define RC_READ_BYTE (*Buffer++)
#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
{ int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
{ UpdateBit0(p); mi <<= 1; A0; } else \
{ UpdateBit1(p); mi = (mi + mi) + 1; A1; }
#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
{ int i = numLevels; res = 1; \
do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
res -= (1 << numLevels); }
#define kNumPosBitsMax 4
#define kNumPosStatesMax (1 << kNumPosBitsMax)
#define kLenNumLowBits 3
#define kLenNumLowSymbols (1 << kLenNumLowBits)
#define kLenNumMidBits 3
#define kLenNumMidSymbols (1 << kLenNumMidBits)
#define kLenNumHighBits 8
#define kLenNumHighSymbols (1 << kLenNumHighBits)
#define LenChoice 0
#define LenChoice2 (LenChoice + 1)
#define LenLow (LenChoice2 + 1)
#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
#define kNumStates 12
#define kNumLitStates 7
#define kStartPosModelIndex 4
#define kEndPosModelIndex 14
#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
#define kNumPosSlotBits 6
#define kNumLenToPosStates 4
#define kNumAlignBits 4
#define kAlignTableSize (1 << kNumAlignBits)
#define kMatchMinLen 2
#define IsMatch 0
#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
#define IsRepG0 (IsRep + kNumStates)
#define IsRepG1 (IsRepG0 + kNumStates)
#define IsRepG2 (IsRepG1 + kNumStates)
#define IsRep0Long (IsRepG2 + kNumStates)
#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
#define LenCoder (Align + kAlignTableSize)
#define RepLenCoder (LenCoder + kNumLenProbs)
#define Literal (RepLenCoder + kNumLenProbs)
#if Literal != LZMA_BASE_SIZE
StopCompilingDueBUG
#endif
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
{
unsigned char prop0;
if (size < LZMA_PROPERTIES_SIZE)
return LZMA_RESULT_DATA_ERROR;
prop0 = propsData[0];
if (prop0 >= (9 * 5 * 5))
return LZMA_RESULT_DATA_ERROR;
{
for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
propsRes->lc = prop0;
/*
unsigned char remainder = (unsigned char)(prop0 / 9);
propsRes->lc = prop0 % 9;
propsRes->pb = remainder / 5;
propsRes->lp = remainder % 5;
*/
}
return LZMA_RESULT_OK;
}
#define kLzmaStreamWasFinishedId (-1)
int LzmaDecode(CLzmaDecoderState *vs,
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
{
CProb *p = vs->Probs;
SizeT nowPos = 0;
Byte previousByte = 0;
UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
int lc = vs->Properties.lc;
int state = 0;
UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
int len = 0;
const Byte *Buffer;
const Byte *BufferLim;
UInt32 Range;
UInt32 Code;
*inSizeProcessed = 0;
*outSizeProcessed = 0;
{
UInt32 i;
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
for (i = 0; i < numProbs; i++)
p[i] = kBitModelTotal >> 1;
}
RC_INIT(inStream, inSize);
while(nowPos < outSize)
{
CProb *prob;
UInt32 bound;
int posState = (int)(
(nowPos
)
& posStateMask);
prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
IfBit0(prob)
{
int symbol = 1;
UpdateBit0(prob)
prob = p + Literal + (LZMA_LIT_SIZE *
(((
(nowPos
)
& literalPosMask) << lc) + (previousByte >> (8 - lc))));
if (state >= kNumLitStates)
{
int matchByte;
matchByte = outStream[nowPos - rep0];
do
{
int bit;
CProb *probLit;
matchByte <<= 1;
bit = (matchByte & 0x100);
probLit = prob + 0x100 + bit + symbol;
RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
}
while (symbol < 0x100);
}
while (symbol < 0x100)
{
CProb *probLit = prob + symbol;
RC_GET_BIT(probLit, symbol)
}
previousByte = (Byte)symbol;
outStream[nowPos++] = previousByte;
if (state < 4) state = 0;
else if (state < 10) state -= 3;
else state -= 6;
}
else
{
UpdateBit1(prob);
prob = p + IsRep + state;
IfBit0(prob)
{
UpdateBit0(prob);
rep3 = rep2;
rep2 = rep1;
rep1 = rep0;
state = state < kNumLitStates ? 0 : 3;
prob = p + LenCoder;
}
else
{
UpdateBit1(prob);
prob = p + IsRepG0 + state;
IfBit0(prob)
{
UpdateBit0(prob);
prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
IfBit0(prob)
{
UpdateBit0(prob);
if (nowPos == 0)
return LZMA_RESULT_DATA_ERROR;
state = state < kNumLitStates ? 9 : 11;
previousByte = outStream[nowPos - rep0];
outStream[nowPos++] = previousByte;
continue;
}
else
{
UpdateBit1(prob);
}
}
else
{
UInt32 distance;
UpdateBit1(prob);
prob = p + IsRepG1 + state;
IfBit0(prob)
{
UpdateBit0(prob);
distance = rep1;
}
else
{
UpdateBit1(prob);
prob = p + IsRepG2 + state;
IfBit0(prob)
{
UpdateBit0(prob);
distance = rep2;
}
else
{
UpdateBit1(prob);
distance = rep3;
rep3 = rep2;
}
rep2 = rep1;
}
rep1 = rep0;
rep0 = distance;
}
state = state < kNumLitStates ? 8 : 11;
prob = p + RepLenCoder;
}
{
int numBits, offset;
CProb *probLen = prob + LenChoice;
IfBit0(probLen)
{
UpdateBit0(probLen);
probLen = prob + LenLow + (posState << kLenNumLowBits);
offset = 0;
numBits = kLenNumLowBits;
}
else
{
UpdateBit1(probLen);
probLen = prob + LenChoice2;
IfBit0(probLen)
{
UpdateBit0(probLen);
probLen = prob + LenMid + (posState << kLenNumMidBits);
offset = kLenNumLowSymbols;
numBits = kLenNumMidBits;
}
else
{
UpdateBit1(probLen);
probLen = prob + LenHigh;
offset = kLenNumLowSymbols + kLenNumMidSymbols;
numBits = kLenNumHighBits;
}
}
RangeDecoderBitTreeDecode(probLen, numBits, len);
len += offset;
}
if (state < 4)
{
int posSlot;
state += kNumLitStates;
prob = p + PosSlot +
((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
kNumPosSlotBits);
RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
if (posSlot >= kStartPosModelIndex)
{
int numDirectBits = ((posSlot >> 1) - 1);
rep0 = (2 | ((UInt32)posSlot & 1));
if (posSlot < kEndPosModelIndex)
{
rep0 <<= numDirectBits;
prob = p + SpecPos + rep0 - posSlot - 1;
}
else
{
numDirectBits -= kNumAlignBits;
do
{
RC_NORMALIZE
Range >>= 1;
rep0 <<= 1;
if (Code >= Range)
{
Code -= Range;
rep0 |= 1;
}
}
while (--numDirectBits != 0);
prob = p + Align;
rep0 <<= kNumAlignBits;
numDirectBits = kNumAlignBits;
}
{
int i = 1;
int mi = 1;
do
{
CProb *prob3 = prob + mi;
RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
i <<= 1;
}
while(--numDirectBits != 0);
}
}
else
rep0 = posSlot;
if (++rep0 == (UInt32)(0))
{
/* it's for stream version */
len = kLzmaStreamWasFinishedId;
break;
}
}
len += kMatchMinLen;
if (rep0 > nowPos)
return LZMA_RESULT_DATA_ERROR;
do
{
previousByte = outStream[nowPos - rep0];
len--;
outStream[nowPos++] = previousByte;
}
while(len != 0 && nowPos < outSize);
}
}
RC_NORMALIZE;
*inSizeProcessed = (SizeT)(Buffer - inStream);
*outSizeProcessed = nowPos;
return LZMA_RESULT_OK;
}

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/*
LzmaDecode.h
LZMA Decoder interface
LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
http://www.7-zip.org/
LZMA SDK is licensed under two licenses:
1) GNU Lesser General Public License (GNU LGPL)
2) Common Public License (CPL)
It means that you can select one of these two licenses and
follow rules of that license.
SPECIAL EXCEPTION:
Igor Pavlov, as the author of this code, expressly permits you to
statically or dynamically link your code (or bind by name) to the
interfaces of this file without subjecting your linked code to the
terms of the CPL or GNU LGPL. Any modifications or additions
to this file, however, are subject to the LGPL or CPL terms.
*/
#ifndef LZMADECODE_H
#define LZMADECODE_H
typedef unsigned char Byte;
typedef unsigned short UInt16;
typedef unsigned int UInt32;
typedef UInt32 SizeT;
#define CProb UInt16
#define LZMA_RESULT_OK 0
#define LZMA_RESULT_DATA_ERROR 1
#define LZMA_BASE_SIZE 1846
#define LZMA_LIT_SIZE 768
#define LZMA_PROPERTIES_SIZE 5
typedef struct _CLzmaProperties
{
int lc;
int lp;
int pb;
}CLzmaProperties;
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
#define kLzmaNeedInitId (-2)
typedef struct _CLzmaDecoderState
{
CLzmaProperties Properties;
CProb *Probs;
} CLzmaDecoderState;
int LzmaDecode(CLzmaDecoderState *vs,
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
#endif /* LZMADECODE_H */

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "bayou.h"
static void print_banner(void)
{
printf("\e[H\e[JBayou Payload Chooser v0.3\n");
}
int main(void)
{
extern unsigned long _binary_builtin_lar_start;
struct LAR *lar;
print_banner();
lar = openlar((void *)&_binary_builtin_lar_start);
if (lar == NULL) {
printf("[CHOOSER]: Unable to scan the attached LAR file\n");
return -1;
}
get_configuration(lar);
if (bayoucfg.n_entries == 0) {
printf("[CHOOSER]: No payloads were found in the LAR\n");
return -1;
}
/*
* If timeout == 0xFF, then show the menu immediately.
* If timeout is zero, then find and run the default item immediately.
* If there is no default item, then show the menu.
* If timeout is anything else, then show a message and wait for a
* keystroke. If there is no keystroke in time then run the default.
* If there is no default then show the menu.
*/
if (bayoucfg.timeout != 0xFF) {
struct payload *d = payload_get_default();
if (d != NULL) {
if (bayoucfg.timeout == 0)
run_payload(d);
else
run_payload_timeout(d, bayoucfg.timeout);
}
}
menu();
return 0;
}

156
payloads/bayou/menu.c Normal file
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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <libpayload.h>
#include <curses.h>
#include "bayou.h"
#define SCREEN_X 80
#define SCREEN_Y 25
static int menu_width = 0;
static struct payload *mpayloads[BAYOU_MAX_ENTRIES];
static int m_entries = 0;
static unsigned int selected = 0;
static WINDOW *menuwin, *status;
void create_menu(void)
{
int i;
for (i = 0; i < bayoucfg.n_entries; i++) {
struct payload *p = &(bayoucfg.entries[i]);
char *name;
if ((p->pentry.parent != 0) ||
(p->pentry.flags & BPT_FLAG_NOSHOW))
continue;
mpayloads[m_entries++] = p;
name = payload_get_name(p);
if (strlen(name) > menu_width)
menu_width = strlen(name);
}
menu_width += 4;
if (menu_width < 30)
menu_width = 30;
menuwin = newwin(m_entries + 3, menu_width,
(SCREEN_Y - (m_entries + 3)) / 2,
(SCREEN_X - menu_width) / 2);
}
void draw_menu(void)
{
struct payload *s;
int i;
wattrset(menuwin, COLOR_PAIR(3));
wclear(menuwin);
wborder(menuwin, ACS_VLINE, ACS_VLINE, ACS_HLINE, ACS_HLINE,
ACS_ULCORNER, ACS_URCORNER, ACS_LLCORNER, ACS_LRCORNER);
wattrset(menuwin, COLOR_PAIR(4) | A_BOLD);
mvwprintw(menuwin, 0, (menu_width - 17) / 2, " Payload Chooser ");
wattrset(menuwin, COLOR_PAIR(3));
for (i = 0; i < m_entries; i++) {
char *name = payload_get_name(mpayloads[i]);
int col = (menu_width - (2 + strlen(name))) / 2;
if (i == selected)
wattrset(menuwin, COLOR_PAIR(5) | A_BOLD);
else
wattrset(menuwin, COLOR_PAIR(3));
mvwprintw(menuwin, 2 + i, col, name);
}
s = mpayloads[selected];
wclear(status);
if (s->params[BAYOU_PARAM_DESC] != NULL) {
char buf[66];
int len = strnlen(s->params[BAYOU_PARAM_DESC], 65);
snprintf(buf, 65, s->params[BAYOU_PARAM_DESC]);
buf[65] = 0;
mvwprintw(status, 0, (80 - len) / 2, buf);
}
wrefresh(menuwin);
wrefresh(status);
}
void loop(void)
{
int key;
while (1) {
key = getch();
if (key == ERR)
continue;
if (key == KEY_DOWN)
selected = (selected + 1) % m_entries;
else if (key == KEY_UP)
selected = (selected - 1) % m_entries;
else if (key == KEY_ENTER) {
run_payload(mpayloads[selected]);
clear();
refresh();
} else
continue;
draw_menu();
}
}
void menu(void)
{
initscr();
init_pair(1, COLOR_WHITE, COLOR_RED);
init_pair(2, COLOR_BLACK, COLOR_WHITE);
init_pair(3, COLOR_BLACK, COLOR_WHITE);
init_pair(4, COLOR_CYAN, COLOR_WHITE);
init_pair(5, COLOR_WHITE, COLOR_RED);
wattrset(stdscr, COLOR_PAIR(1));
wclear(stdscr);
status = newwin(1, 80, 24, 0);
wattrset(status, COLOR_PAIR(2));
wclear(status);
refresh();
create_menu();
draw_menu();
loop();
}

87
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#include <libpayload.h>
// This GETBIT is supposed to work on little endian
// 32bit systems. The algorithm will definitely need
// some fixing on other systems, but it might not be
// a problem since the nrv2b binary behaves the same..
#ifndef ENDIAN
#define ENDIAN 0
#endif
#ifndef BITSIZE
#define BITSIZE 32
#endif
#define GETBIT_8(bb, src, ilen) \
(((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
#define GETBIT_LE16(bb, src, ilen) \
(bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
#define GETBIT_LE32(bb, src, ilen) \
(bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
bb=*(const u32 *)((src)+ilen),ilen+=4,(bb>>31)&1))
#if ENDIAN == 0 && BITSIZE == 8
#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 16
#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 32
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
#endif
unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p)
{
unsigned long ilen = 0, olen = 0, last_m_off = 1;
u32 bb = 0;
unsigned bc = 0;
const u8 *m_pos;
// skip length
src += 4;
/* FIXME: check olen with the length stored in first 4 bytes */
for (;;) {
unsigned int m_off, m_len;
while (GETBIT(bb, src, ilen)) {
dst[olen++] = src[ilen++];
}
m_off = 1;
do {
m_off = m_off * 2 + GETBIT(bb, src, ilen);
} while (!GETBIT(bb, src, ilen));
if (m_off == 2) {
m_off = last_m_off;
} else {
m_off = (m_off - 3) * 256 + src[ilen++];
if (m_off == 0xffffffffU)
break;
last_m_off = ++m_off;
}
m_len = GETBIT(bb, src, ilen);
m_len = m_len * 2 + GETBIT(bb, src, ilen);
if (m_len == 0) {
m_len++;
do {
m_len = m_len * 2 + GETBIT(bb, src, ilen);
} while (!GETBIT(bb, src, ilen));
m_len += 2;
}
m_len += (m_off > 0xd00);
m_pos = dst + olen - m_off;
dst[olen++] = *m_pos++;
do {
dst[olen++] = *m_pos++;
} while (--m_len > 0);
}
*ilen_p = ilen;
return olen;
}

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "bayou.h"
#define TIMEOUT_MESSAGE "Press ESC for the menu (%2d)...\r"
#define TIMEOUT_KEY '\033'
void run_payload(struct payload *p)
{
int ret, i;
/* For chooser entries, just run the payload. */
if (p->pentry.type == BPT_TYPE_CHOOSER) {
self_load_and_run(p, &ret);
return;
}
/* For chained entries, run all the sub-chain items. */
for (i = 0; i < bayoucfg.n_entries; i++) {
struct payload *s = &(bayoucfg.entries[i]);
if (s->pentry.parent == p->pentry.index)
self_load_and_run(s, &ret);
}
}
char *payload_get_name(struct payload *p)
{
if (p->pentry.type == BPT_TYPE_CHAIN)
return (char *)p->pentry.title;
else if (p->pentry.type == BPT_TYPE_CHOOSER) {
if (p->pentry.title[0] != 0)
return (char *)p->pentry.title;
return p->params[BAYOU_PARAM_DESC];
}
return NULL;
}
struct payload *payload_get_default(void)
{
int i;
for (i = 0; i < bayoucfg.n_entries; i++) {
struct payload *s = &(bayoucfg.entries[i]);
if (s->pentry.parent == 0 && s->pentry.flags & BPT_FLAG_DEFAULT)
return s;
}
return NULL;
}
void run_payload_timeout(struct payload *p, int timeout)
{
int t, ch, tval;
for (t = timeout; t >= 0; t--) {
printf(TIMEOUT_MESSAGE, t);
tval = 1000;
ch = getchar_timeout(&tval);
if (ch == TIMEOUT_KEY)
return;
}
run_payload(p);
}
void payload_parse_params(struct payload *pload, u8 *params, int len)
{
char *ptr = (char *)params;
int i = 0;
if (ptr == NULL)
return;
while (ptr < ((char *)params + len)) {
if (!strncmp(ptr, "name=", 5)) {
pload->params[BAYOU_PARAM_NAME] = ptr + 5;
} else if (!strncmp(ptr, "desc=", 5)) {
pload->params[BAYOU_PARAM_DESC] = ptr + 5;
} else if (!strncmp(ptr, "listname=", 9)) {
pload->params[BAYOU_PARAM_LIST] = ptr + 9;
}
ptr += strnlen(ptr, len - i);
if (ptr < ((char *)params + len) && *ptr == 0)
ptr++;
}
}

147
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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "bayou.h"
#include "self.h"
static int nop_decompress(void *dst, void *src, int len)
{
memcpy(dst, src, len);
return len;
}
#ifdef CONFIG_LZMA
extern int ulzma(u8 *, u8 *);
static int lzma_decompress(void *dst, void *src, int len)
{
return ulzma((u8 *) src, (u8 *) dst);
}
#endif
#ifdef CONFIG_NRV2B
extern int unrv2b(u8 *, u8 *, unsigned long *);
static int nrv2b_decompress(void *dst, void *src, int len)
{
unsigned long l = (u32) len;
return unrv2b(src, dst, &l);
}
#endif
static int zeros_decompress(void *dst, void *src, int len)
{
memset(dst, 0, len);
return len;
}
int self_get_params(u8 *fptr, u8 **params)
{
struct self_segment *seg = (struct self_segment *)fptr;
while (seg->type != SELF_TYPE_ENTRY) {
if (seg->type == 0)
return -1;
if (seg->type == SELF_TYPE_PARAMS) {
*params = (u8 *) (fptr + seg->offset);
return seg->len;
}
seg++;
}
*params = NULL;
return 0;
}
int verify_self(u8 *ptr)
{
struct self_segment *seg = (struct self_segment *)ptr;
switch (seg->type) {
case SELF_TYPE_CODE:
case SELF_TYPE_DATA:
case SELF_TYPE_BSS:
case SELF_TYPE_PARAMS:
case SELF_TYPE_ENTRY:
return 1;
}
return 0;
}
int self_load_and_run(struct payload *p, int *ret)
{
struct self_segment *seg = (struct self_segment *)p->fptr;
int (*dcmp) (void *, void *, int);
int dlen;
switch (p->stat.compression) {
#ifdef CONFIG_LZMA
case ALGO_LZMA:
dcmp = lzma_decompress;
break;
#endif
#ifdef CONFIG_NRV2B
case ALGO_NRV2B:
dcmp = nrv2b_decompress;
break;
#endif
case ALGO_ZEROES:
dcmp = zeros_decompress;
break;
case ALGO_NONE:
dcmp = nop_decompress;
default:
printf("E: Unsupported decompression type\n");
return -1;
}
while (1) {
u32 laddr = (u32) (seg->load_addr & 0xFFFFFFFF);
switch (seg->type) {
case SELF_TYPE_CODE:
case SELF_TYPE_DATA:
dlen = dcmp((void *)laddr,
(void *)p->fptr + seg->offset, seg->len);
if (dlen < seg->mem_len) {
memset((void *)(laddr + dlen), 0,
seg->mem_len - dlen);
}
break;
case SELF_TYPE_BSS:
memset((void *)laddr, 0, seg->len);
break;
case SELF_TYPE_ENTRY:
*ret = exec(laddr, 0, NULL);
return 0;
default:
break;
}
seg++;
}
return -1;
}

44
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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SELF_H_
#define SELF_H_
#include <libpayload.h>
struct self_segment {
u32 type;
u32 offset;
u64 load_addr;
u32 len;
u32 mem_len;
};
struct self {
struct larstat stat;
void *fptr;
};
#define SELF_TYPE_CODE 0x45444F43
#define SELF_TYPE_DATA 0x41544144
#define SELF_TYPE_BSS 0x20535342
#define SELF_TYPE_PARAMS 0x41524150
#define SELF_TYPE_ENTRY 0x52544E45
#endif

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##
## This file is part of the bayou project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
CC=gcc
PBUILDOBJS := config.o create.o show.o main.o
INCLUDES := -Iliblar/
CFLAGS=-Wall -Werror -g
all: pbuilder
LZMA_OBJ := lzma/LZMAEncoder.o lzma/LZInWindow.o lzma/RangeCoderBit.o
LZMA_OBJ += lzma/StreamUtils.o lzma/OutBuffer.o lzma/Alloc.o lzma/CRC.o
LZMA_OBJ += lzma/lzma-compress.o
lzma/lzma-compress.o: lzma/minilzma.cc
g++ -o $@ -c -DCOMPACT $<
lzma/%.o: lzma/C/7zip/Compress/LZMA/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/C/7zip/Compress/LZ/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/C/7zip/Compress/RangeCoder/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/C/7zip/Decompress/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/C/7zip/Common/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/C/Common/%.cpp
g++ -o $@ -c $<
lzma/%.o: lzma/%.cc
g++ -o $@ -c $<
pbuilder: $(PBUILDOBJS) $(LZMA_OBJ) liblar/liblar.a
$(CXX) -o $@ $(PBUILDOBJS) $(LZMA_OBJ) -L ./liblar -llar -lexpat
liblar/liblar.a:
make -C liblar
%.o: %.c
$(CC) -c $(CFLAGS) $(INCLUDES) -o $@ $<
clean:
rm -f pbuilder *.o lzma/*.o
make -C liblar clean

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define _GNU_SOURCE
#include <stdlib.h>
#include <string.h>
#include <expat.h>
#include <ctype.h>
#include "pbuilder.h"
#define STATE_NONE 0x00
#define STATE_BAYOUCONFIG 0x01
#define STATE_GLOBAL 0x02
#define STATE_GLOBAL_TIMEOUT 0x03
#define STATE_PAYLOADS 0x04
#define STATE_PAYLOAD 0x05
#define STATE_PAYLOAD_TITLE 0x06
#define STATE_PAYLOAD_FILE 0x07
#define STATE_PAYLOAD_LARNAME 0x08
#define STATE_PAYLOAD_CHAIN 0x09
#define STATE_PAYLOAD_CHAIN_FILE 0x0A
#define STATE_PAYLOAD_CHAIN_LARNAME 0x0B
static struct userdata {
struct config *config;
struct pentry *payload;
struct pentry *chain;
int state;
} userdata;
static char buffer[8192];
static struct {
char *element;
int pstate;
int state;
} states[] = {
{"BayouConfig", STATE_NONE, STATE_BAYOUCONFIG},
{"global", STATE_BAYOUCONFIG, STATE_GLOBAL},
{"timeout", STATE_GLOBAL, STATE_GLOBAL_TIMEOUT},
{"payloads", STATE_BAYOUCONFIG, STATE_PAYLOADS},
{"payload", STATE_PAYLOADS, STATE_PAYLOAD},
{"title", STATE_PAYLOAD, STATE_PAYLOAD_TITLE},
{"lar", STATE_PAYLOAD, STATE_PAYLOAD_LARNAME},
{"file", STATE_PAYLOAD, STATE_PAYLOAD_FILE},
{"chain", STATE_PAYLOAD, STATE_PAYLOAD_CHAIN},
{"file", STATE_PAYLOAD_CHAIN, STATE_PAYLOAD_CHAIN_FILE},
{"lar", STATE_PAYLOAD_CHAIN, STATE_PAYLOAD_CHAIN_LARNAME},
{NULL},
};
static struct pentry *newPayload(struct config *config)
{
struct pentry **tmp, *ret;
tmp = realloc(config->entries,
(config->n_entries + 1) * sizeof(struct pentry *));
if (tmp == NULL)
return NULL;
config->entries = tmp;
ret = config->entries[config->n_entries] = calloc(sizeof(*ret), 1);
if (ret == NULL)
return NULL;
/* Yes, I want this to be ++config->n_entries (the index is 1 based). */
ret->index = ++config->n_entries;
return ret;
}
static void parseFlags(struct pentry *entry, const char *flags)
{
char *p = (char *)flags;
char *n;
while (*p) {
n = strchr(p, ',');
if (n)
*(n++) = 0;
if (!strcmp(p, "default"))
entry->flags |= BPT_FLAG_DEFAULT;
else if (!strcmp(p, "nolist"))
entry->flags |= BPT_FLAG_NOSHOW;
else
warn("W: Unknown payload flag %s\n", p);
if (!n)
break;
for (p = n; *p && isspace(*p); p++) ;
}
}
static struct pentry *addPayload(struct config *config, const char **attr)
{
struct pentry *ret = newPayload(config);
int i = 0;
if (ret == NULL)
die("E: Could not allocate memory for a new payload\n");
while (attr[i] != NULL) {
if (!strcmp(attr[i], "type")) {
if (!strcmp(attr[i + 1], "chain"))
ret->type = BPT_TYPE_CHAIN;
else if (!strcmp(attr[i + 1], "chooser"))
ret->type = BPT_TYPE_CHOOSER;
else
die("E: Invalid payload type %s\n",
attr[i + 1]);
} else if (!strcmp(attr[i], "flags"))
parseFlags(ret, attr[i + 1]);
i += 2;
}
return ret;
}
static struct pentry *addChain(struct config *config, struct pentry *parent)
{
struct pentry *ret = newPayload(config);
if (ret == NULL)
die("E: Could not allocate memory for a new payload\n");
ret->parent = parent->index;
ret->type = BPT_TYPE_SUBCHAIN;
return ret;
}
static void start(void *data, const char *el, const char **attr)
{
int i;
struct userdata *d = (struct userdata *)data;
for (i = 0; states[i].element != NULL; i++) {
if (d->state != states[i].pstate)
continue;
if (!strcmp(el, states[i].element)) {
d->state = states[i].state;
break;
}
}
if (states[i].element == NULL)
die("E: Unknown element %s\n", el);
if (d->state == STATE_PAYLOAD)
d->payload = addPayload(d->config, attr);
if (d->state == STATE_PAYLOAD_CHAIN)
d->chain = addChain(d->config, d->payload);
}
static void data(void *data, const char *val, int len)
{
struct userdata *d = (struct userdata *)data;
int l;
switch (d->state) {
case STATE_GLOBAL_TIMEOUT:
d->config->timeout = atoi(val);
break;
case STATE_PAYLOAD_TITLE:
l = sizeof(d->payload->title) - 1 > len ?
len : sizeof(d->payload->title) - 1;
strncpy((char *)d->payload->title, (char *)val, l);
d->payload->title[l] = '\0';
break;
case STATE_PAYLOAD_FILE:
d->payload->file = strndup(val, len);
break;
case STATE_PAYLOAD_LARNAME:
d->payload->larname = strndup(val, len);
break;
case STATE_PAYLOAD_CHAIN_FILE:
d->chain->file = strndup(val, len);
break;
case STATE_PAYLOAD_CHAIN_LARNAME:
d->chain->larname = strndup(val, len);
break;
default:
break;
}
}
static void end(void *data, const char *el)
{
struct userdata *d = (struct userdata *)data;
int i;
if (d->state == STATE_PAYLOAD_CHAIN)
d->chain = NULL;
if (d->state == STATE_PAYLOAD)
d->payload = NULL;
for (i = 0; states[i].element != NULL; i++) {
if (d->state != states[i].state)
continue;
if (!strcmp(el, states[i].element)) {
d->state = states[i].pstate;
break;
}
}
if (states[i].element == NULL)
die("E: Unable to find the reverse state for %s\n", el);
}
void parseconfig(FILE *stream, struct config *config)
{
XML_Parser p = XML_ParserCreate(NULL);
int eof = 0;
if (p == NULL)
die("E: Could not create the parser\n");
XML_SetElementHandler(p, start, end);
XML_SetCharacterDataHandler(p, data);
userdata.config = config;
XML_SetUserData(p, &userdata);
while (!eof) {
int len = fread(buffer, 1, 8192, stream);
eof = feof(stream);
if (ferror(stream))
die("E: Error reading the stream\n");
if (!XML_Parse(p, buffer, len, eof))
die("E: Error parsing the XML data\n");
}
}

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@ -0,0 +1,200 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <libgen.h>
#include "liblar.h"
#include "pbuilder.h"
void do_lzma_compress(char *in, int in_len, char *out, int *out_len);
int add_bpt_to_lar(struct LAR *lar, struct config *config)
{
char *buffer;
int ret, i, len = sizeof(struct bpt_config);
struct bpt_config *cfg;
struct LARAttr attr;
char *ptr;
for (i = 0; i < config->n_entries; i++) {
len += sizeof(struct bpt_pentry);
if (config->entries[i]->type != BPT_TYPE_CHAIN)
len += ((strlen(config->entries[i]->larname)
+ 15) & ~0x0F);
}
buffer = calloc(len, 1);
if (buffer == NULL)
return -1;
cfg = (struct bpt_config *)buffer;
cfg->id = BPT_ID;
cfg->timeout = config->timeout;
cfg->entries = config->n_entries;
ptr = buffer + sizeof(struct bpt_config);
for (i = 0; i < config->n_entries; i++) {
int nlen = 0;
struct bpt_pentry *pentry = (struct bpt_pentry *)ptr;
pentry->index = config->entries[i]->index;
pentry->parent = config->entries[i]->parent;
pentry->type = config->entries[i]->type;
pentry->flags = config->entries[i]->flags;
strncpy((char *)pentry->title,
(char *)config->entries[i]->title,
sizeof(pentry->title));
if (config->entries[i]->type != BPT_TYPE_CHAIN) {
nlen = strlen(config->entries[i]->larname);
nlen = (nlen + 15) & ~0x0F;
strcpy((char *)(ptr + sizeof(struct bpt_pentry)),
config->entries[i]->larname);
pentry->nlen = nlen;
}
ptr += sizeof(struct bpt_pentry);
if (config->entries[i]->type != BPT_TYPE_CHAIN)
ptr += nlen;
}
LAR_SetAttrs(&attr, "bayou_payload_table", ALGO_NONE);
ret = LAR_AppendBuffer(lar, (unsigned char *)buffer, len, &attr);
free(buffer);
return ret;
}
struct lfile {
char *file;
char *larname;
};
int n_lfiles;
int create_lar_from_config(const char *input, const char *output)
{
struct config config;
FILE *stream;
struct LAR *lar;
struct LARAttr attr;
int i, j, ret = -1;
struct lfile *lfiles;
stream = fopen(input, "r");
if (stream == NULL) {
warn("E: Couldn't open %s for reading\n", input);
return -1;
}
memset(&config, 0, sizeof(config));
parseconfig(stream, &config);
fclose(stream);
lar = LAR_Create(output);
if (lar == NULL) {
warn("E: Couldn't create a new lar file\n");
return -1;
}
LAR_SetCompressionFuncs(lar, ALGO_LZMA, do_lzma_compress, NULL);
lfiles = calloc(sizeof(struct lfile), config.n_entries);
if (lfiles == NULL) {
warn("E: Couldn't allocate memory: %m\n");
return -1;
}
for (i = 0; i < config.n_entries; i++) {
/* Master chain entries don't have files associated with them. */
if (config.entries[i]->type == BPT_TYPE_CHAIN)
continue;
if (access(config.entries[i]->file, R_OK)) {
warn("E: Could not find file %s\n",
config.entries[i]->file);
goto err;
}
if (config.entries[i]->larname == NULL) {
config.entries[i]->larname =
strdup(basename(config.entries[i]->file));
if (config.entries[i]->larname == NULL) {
warn("E: Could not allocate memory for the default name\n");
goto err;
}
}
/*
* Add the file to the list of files to add to the LAR - skip
* any duplicates, but be on the lookout for the same LAR name
* attached to a different file.
*/
for (j = 0; j < n_lfiles; j++) {
if (!strcmp(lfiles[j].larname,
config.entries[i]->larname)) {
if (strcmp(lfiles[j].file,
config.entries[i]->file)) {
warn("E: LAR name '%s' has already been used\n", config.entries[i]->larname);
goto err;
}
break;
}
}
if (j == n_lfiles) {
lfiles[n_lfiles].file = config.entries[i]->file;
lfiles[n_lfiles++].larname = config.entries[i]->larname;
}
}
/* Add all the files to the LAR. */
for (i = 0; i < n_lfiles; i++) {
LAR_SetAttrs(&attr, lfiles[i].larname, ALGO_LZMA);
if (LAR_AppendFile(lar, lfiles[i].file, &attr)) {
warn("E: Could not add %s to the LAR\n",
lfiles[i].file);
goto err;
}
}
ret = add_bpt_to_lar(lar, &config);
err:
LAR_Close(lar);
return ret;
}

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@ -0,0 +1,31 @@
##
## This file is part of the bayou project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
CC = gcc
LAROBJS = self.o lib.o
CFLAGS = -g -Wall
liblar.a: $(LAROBJS)
ar rc $@ $(LAROBJS)
%.o: %.c
$(CC) -c $(CFLAGS) -o $@ $<
clean:
rm -f liblar.a *.o

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@ -0,0 +1,95 @@
/*
* lar - lightweight archiver
*
* Copyright (C) 2006 coresystems GmbH
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2007 Patrick Georgi <patrick@georgi-clan.de>
*
* This file is dual-licensed. You can choose between:
* - The GNU GPL, version 2, as published by the Free Software Foundation
* - The revised BSD license (without advertising clause)
*
* ---------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
* ---------------------------------------------------------------------------
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ---------------------------------------------------------------------------
*/
#include <stdio.h>
#include <stdint.h>
#define MAGIC "LARCHIVE"
#define MAX_PATHLEN 1024
#define BOOTBLOCK_SIZE 20480
#define BOOTBLOCK_NAME "bootblock"
#define BOOTBLOCK_NAME_LEN 16
typedef uint64_t u64;
typedef int64_t s64;
typedef uint32_t u32;
typedef int32_t s32;
typedef uint8_t u8;
/* NOTE -- This and the coreboot lar.h may NOT be in sync. Be careful. */
struct lar_header {
char magic[8];
u32 len;
u32 reallen;
u32 checksum;
u32 compchecksum;
/* Filenames are limited to 2^31-1-sizeof(lar_header)-1 bytes.
* "Nobody will ever need more than 640k" */
u32 offset;
/* Compression:
* 0 = no compression
* 1 = lzma
* 2 = nrv2b
* 3 = zeroes
*/
u32 compression;
u64 entry;
u64 loadaddress;
};
enum compalgo {
ALGO_NONE = 0,
ALGO_LZMA = 1,
ALGO_NRV2B = 2,
ALGO_ZEROES = 3,
/* invalid should always be the last entry. */
ALGO_INVALID
};

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@ -0,0 +1,461 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <arpa/inet.h>
#include "liblar.h"
#include "self.h"
static int lar_compress(struct LAR *lar, int algo, char *src, char *dst,
int len)
{
int ret;
if (!lar->cfuncs[algo])
return -1;
lar->cfuncs[algo] (src, len, dst, &ret);
return ret;
}
static int lar_decompress(struct LAR *lar, int algo, char *src, char *dst,
int slen, int dlen)
{
if (!lar->dfuncs[algo])
return -1;
lar->dfuncs[algo] (src, slen, dst, dlen);
return dlen;
}
static struct LARHeader *lar_get_header(struct LAR *lar, const char *filename)
{
char *buffer;
int offset = 0;
struct LARHeader *lheader = NULL;
struct lar_header *header;
printf("Getting %s\n", filename);
buffer = malloc(sizeof(struct lar_header) + MAX_PATHLEN);
if (buffer == NULL)
return NULL;
while (1) {
int ret;
if (lseek(lar->fd, offset, SEEK_SET) == -1)
goto err;
ret = read(lar->fd, buffer, sizeof(struct lar_header));
if (ret <= 0)
goto err;
header = (struct lar_header *)buffer;
if (strncmp(header->magic, MAGIC, sizeof(MAGIC)))
goto err;
ret = read(lar->fd, buffer + sizeof(struct lar_header),
ntohl(header->offset) - sizeof(struct lar_header));
if (ret <= 0)
goto err;
if (!strcmp(buffer + sizeof(struct lar_header), filename))
break;
offset += ntohl(header->offset) +
((ntohl(header->len) + 15) & ~0xF);
}
lheader = calloc(sizeof(struct LARHeader), 1);
if (lheader == NULL)
goto err;
lheader->hoffset = offset;
lheader->offset = offset + ntohl(header->offset);
lheader->reallen = ntohl(header->reallen);
lheader->len = ntohl(header->len);
lheader->loadaddress = ntohl(header->loadaddress);
lheader->compression = ntohl(header->compression);
lheader->entry = ntohl(header->entry);
lheader->checksum = ntohl(header->checksum);
err:
free(buffer);
return lheader;
}
static int LAR_AppendBlob(struct LAR *lar, unsigned char *buffer,
int len, int rlen, struct LARAttr *attr)
{
int nlen, nsize, lsize, i;
struct lar_header *header;
u8 *lptr;
u32 csum = 0;
if (attr == NULL)
return -1;
nlen = strlen(attr->name) + 1;
if (nlen > MAX_PATHLEN - 1)
nlen = MAX_PATHLEN - 1;
nsize = (nlen + 15) & ~0xF;
lsize = sizeof(struct lar_header) + nsize + len;
lptr = calloc(lsize + 1, 1);
if (lptr == NULL)
return -1;
header = (struct lar_header *)lptr;
memcpy(header->magic, MAGIC, 8);
header->reallen = htonl(rlen);
header->len = htonl(len);
header->offset = htonl(lsize - len);
header->loadaddress = htonl(attr->loadaddr);
header->compression = htonl(attr->compression);
header->entry = htonl(attr->entry);
strncpy(((char *)header) + sizeof(struct lar_header), attr->name, nlen);
for (i = 0; i < sizeof(struct lar_header) + nsize; i += 4)
csum += *((u32 *) (lptr + i));
for (i = 0; i < len; i += 4) {
/*
* The checksum needs to include the 16 byte padding at
* the end of the data before the next lar header. The
* problem is that the padding isn't going to be in the
* buffer, and if we try to read off the end of the buffer,
* we are just asking for trouble. So account for the
* situation where the datalen is not a multiple of four
* and get a safe value to add into the checksum.
* The rest of the padding will be zero, and can be safely
* ignored here.
*/
if ((len - i) < 4) {
u32 val = 0;
int t;
for (t = 0; t < (len - i); t++)
val |= *((u8 *) buffer + (i + t)) << (t * 8);
csum += val;
} else
csum += *((u32 *) (buffer + i));
}
header->checksum = (u32) (~0 - csum);
lseek(lar->fd, 0, SEEK_END);
/* FIXME: Error check here. */
write(lar->fd, header, sizeof(struct lar_header) + nsize);
write(lar->fd, buffer, len);
/* Add in padding to the next 16 byte boundary. */
if (lsize & 0xF) {
int i;
char null = '\0';
for (i = lsize & 0xF; i < 0x10; i++)
write(lar->fd, &null, 1);
}
return 0;
}
int LAR_AppendBuffer(struct LAR *lar, unsigned char *buffer, int len,
struct LARAttr *attr)
{
unsigned char *tbuf;
int rlen, ret = -1;
if (attr->compression == ALGO_NONE)
return LAR_AppendBlob(lar, buffer, len, len, attr);
tbuf = malloc(len);
if (tbuf == NULL)
return -1;
rlen = lar_compress(lar, attr->compression, (char *)buffer,
(char *)tbuf, len);
if (rlen > 0)
ret = LAR_AppendBlob(lar, tbuf, rlen, len, attr);
free(tbuf);
return ret;
}
int LAR_AppendSelf(struct LAR *lar, const char *filename, struct LARAttr *attr)
{
unsigned char *buffer;
int len = elf_to_self(filename, &buffer,
lar->cfuncs[attr->compression]);
int ret;
if (len == -1)
return -1;
ret = LAR_AppendBlob(lar, buffer, len, len, attr);
free(buffer);
return ret;
}
int LAR_AppendFile(struct LAR *lar, const char *filename, struct LARAttr *attr)
{
int fd;
struct stat s;
char *filep;
int ret;
if (iself((char *)filename))
return LAR_AppendSelf(lar, filename, attr);
fd = open(filename, O_RDONLY);
if (fd == -1)
return -1;
if (fstat(fd, &s))
return -1;
filep = (char *)mmap(0, s.st_size, PROT_READ, MAP_SHARED, fd, 0);
if (filep == MAP_FAILED)
return -1;
ret = LAR_AppendBuffer(lar, (unsigned char *)filep, s.st_size, attr);
munmap(filep, s.st_size);
return ret;
}
int LAR_DeleteFile(struct LAR *lar, const char *filename)
{
struct LARHeader *header = lar_get_header(lar, filename);
int len, ret = -1;
char *filep, *buffer;
if (header == NULL)
return -1;
buffer = malloc(4096);
if (buffer == NULL)
return -1;
len = header->offset + header->len;
/* First, map the space and zero it out. */
filep = (char *)mmap(0, len, PROT_READ, MAP_SHARED, lar->fd,
header->hoffset);
if (filep == MAP_FAILED)
return -1;
memset(filep, 0, len);
munmap(filep, len);
/* Now move the rest of the LAR into place. */
/* FIXME: This does not account for the bootblock! */
int dst = header->hoffset;
int src = header->hoffset + len;
while (1) {
int l, w;
if (lseek(lar->fd, src, SEEK_SET))
goto err;
l = read(lar->fd, buffer, 8192);
if (l == -1)
goto err;
if (l == 0)
goto err;
if (lseek(lar->fd, dst, SEEK_SET))
goto err;
w = write(lar->fd, buffer, l);
if (w <= 0)
goto err;
dst += w;
src += w;
}
ret = 0;
err:
free(buffer);
return ret;
}
void LAR_CloseFile(struct LARFile *file)
{
if (file != NULL) {
if (file->buffer != NULL)
free(file->buffer);
free(file);
}
}
struct LARFile *LAR_MapFile(struct LAR *lar, const char *filename)
{
struct LARFile *file;
struct LARHeader *header = lar_get_header(lar, filename);
char *filep;
int ret;
if (header == NULL)
return NULL;
file = calloc(sizeof(struct LARFile), 1);
if (file == NULL)
return NULL;
file->len = header->reallen;
file->buffer = calloc(header->reallen, 1);
if (file->buffer == NULL)
goto err;
/*
* The offset needs to be a multiple of PAGE_SIZE, so just mmap
* from offset 0, its easier then doing the math.
*/
filep = mmap(0, header->offset + header->len,
PROT_READ, MAP_SHARED, lar->fd, 0);
if (filep == MAP_FAILED) {
printf("Map failed: %m\n");
goto err;
}
if (header->compression != ALGO_NONE) {
ret = lar_decompress(lar, header->compression,
filep + header->offset, file->buffer,
header->len, header->reallen);
} else {
memcpy(file->buffer, filep + header->offset, header->len);
ret = header->len;
}
munmap(filep, header->offset + header->len);
if (ret == header->reallen)
return file;
err:
if (file->buffer)
free(file->buffer);
free(file);
return NULL;
}
int LAR_SetCompressionFuncs(struct LAR *lar, int algo,
LAR_CompFunc cfunc, LAR_DecompFunc dfunc)
{
if (algo >= ALGO_INVALID)
return -1;
lar->cfuncs[algo] = cfunc;
lar->dfuncs[algo] = dfunc;
return 0;
}
void LAR_Close(struct LAR *lar)
{
if (lar != NULL) {
if (lar->fd)
close(lar->fd);
free(lar);
}
}
struct LAR *LAR_Open(const char *filename)
{
struct LAR *lar = calloc(sizeof(struct LAR), 1);
if (lar == NULL)
return NULL;
lar->fd = open(filename, O_RDWR);
if (lar->fd > 0)
return lar;
free(lar);
return NULL;
}
struct LAR *LAR_Create(const char *filename)
{
struct LAR *lar = calloc(sizeof(struct LAR), 1);
if (lar == NULL)
return NULL;
lar->fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, S_IRUSR | S_IWUSR);
if (lar->fd > 0)
return lar;
free(lar);
return NULL;
}
void LAR_SetAttrs(struct LARAttr *attrs, char *name, int algo)
{
if (attrs == NULL)
return;
memset(attrs, 0, sizeof(*attrs));
snprintf(attrs->name, sizeof(attrs->name) - 1, name);
attrs->compression = algo;
}

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@ -0,0 +1,75 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _LIBLAR_H_
#define _LIBLAR_H_
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "lar.h"
typedef void (*LAR_CompFunc) (char *, int, char *, int *);
typedef void (*LAR_DecompFunc) (char *, int, char *, int);
struct LAR {
int fd;
LAR_CompFunc cfuncs[ALGO_INVALID];
LAR_DecompFunc dfuncs[ALGO_INVALID];
};
struct LARHeader {
u32 len;
u32 reallen;
u32 checksum;
u32 compression;
u64 loadaddress;
u64 entry;
/* These are the offsets within the file. */
unsigned int offset;
unsigned int hoffset;
};
struct LARAttr {
char name[MAX_PATHLEN];
u64 loadaddr;
int compression;
u64 entry;
};
struct LARFile {
int len;
char *buffer;
};
int LAR_AppendBuffer(struct LAR *lar, unsigned char *buffer, int len,
struct LARAttr *attr);
int LAR_AppendSelf(struct LAR *lar, const char *filename, struct LARAttr *attr);
int LAR_AppendFile(struct LAR *lar, const char *filename, struct LARAttr *attr);
int LAR_DeleteFile(struct LAR *lar, const char *filename);
void LAR_CloseFile(struct LARFile *file);
struct LARFile *LAR_MapFile(struct LAR *lar, const char *filename);
int LAR_SetCompressionFuncs(struct LAR *lar, int algo,
LAR_CompFunc cfunc, LAR_DecompFunc dfunc);
void LAR_Close(struct LAR *lar);
struct LAR *LAR_Open(const char *filename);
struct LAR *LAR_Create(const char *filename);
void LAR_SetAttrs(struct LARAttr *attrs, char *name, int algo);
#endif

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@ -0,0 +1,206 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* Includes code from util/lar from coreboot-v3
*
* Copyright (C) 2006-2007 coresystems GmbH
* Copyright (C) 2007 Patrick Georgi <patrick@georgi-clan.de>
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/stat.h>
#include <elf.h>
#include <sys/mman.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdint.h>
typedef uint64_t u64;
typedef int64_t s64;
typedef uint32_t u32;
typedef int32_t s32;
typedef uint8_t u8;
#include "self.h"
int elf_to_self(const char *filename, unsigned char **buffer,
void (*compress) (char *, int, char *, int *))
{
struct stat s;
Elf32_Phdr *phdr;
Elf32_Ehdr *ehdr;
Elf32_Shdr *shdr;
void *filep;
char *header, *strtab;
unsigned char *sptr;
int headers, segments = 1, isize = 0, osize = 0, doffset = 0, fd, i;
struct self_segment *segs;
if (stat(filename, &s)) {
printf("Unable to stat %s: %m\n", filename);
return -1;
}
fd = open(filename, O_RDONLY);
if (fd == -1) {
printf("Unable to open %s: %m\n", filename);
return -1;
}
/* Map the file so that we can easily parse it. */
filep = (void *)
mmap(0, s.st_size, PROT_READ, MAP_SHARED, fd, 0);
if (filep == MAP_FAILED) {
close(fd);
return -1;
}
ehdr = (Elf32_Ehdr *) filep;
headers = ehdr->e_phnum;
header = (char *)ehdr;
phdr = (Elf32_Phdr *) & (header[ehdr->e_phoff]);
shdr = (Elf32_Shdr *) & (header[ehdr->e_shoff]);
strtab = &header[shdr[ehdr->e_shstrndx].sh_offset];
/* Count number of headers - look for the .notes.pinfo section. */
for (i = 0; i < ehdr->e_shnum; i++) {
char *name;
if (i == ehdr->e_shstrndx)
continue;
if (shdr[i].sh_size == 0)
continue;
name = (char *)(strtab + shdr[i].sh_name);
if (!strcmp(name, ".note.pinfo"))
segments++;
}
/*
* Now, regular headers - we only care about PT_LOAD headers,
* because thats what we're actually going to load.
*/
for (i = 0; i < headers; i++) {
if (phdr[i].p_type != PT_LOAD)
continue;
/* Empty segments are never interesting. */
if (phdr[i].p_memsz == 0)
continue;
isize += phdr[i].p_filesz;
segments++;
}
/* Allocate a block of memory to store the SELF in. */
sptr = calloc((segments * sizeof(struct self_segment)) + isize, 1);
doffset = (segments * sizeof(struct self_segment));
if (sptr == NULL)
goto err;
segs = (struct self_segment *)sptr;
segments = 0;
for (i = 0; i < ehdr->e_shnum; i++) {
char *name;
if (i == ehdr->e_shstrndx)
continue;
if (shdr[i].sh_size == 0)
continue;
name = (char *)(strtab + shdr[i].sh_name);
if (!strcmp(name, ".note.pinfo")) {
segs[segments].type = SELF_TYPE_PARAMS;
segs[segments].load_addr = 0;
segs[segments].len = (u32) shdr[i].sh_size;
segs[segments].offset = doffset;
memcpy((unsigned long *)(sptr + doffset),
&header[shdr[i].sh_offset], shdr[i].sh_size);
doffset += segs[segments].len;
osize += segs[segments].len;
segments++;
}
}
for (i = 0; i < headers; i++) {
if (phdr[i].p_type != PT_LOAD)
continue;
if (phdr[i].p_memsz == 0)
continue;
segs[segments].type = SELF_TYPE_DATA;
segs[segments].load_addr = (u64) phdr[i].p_paddr;
segs[segments].mem_len = (u32) phdr[i].p_memsz;
segs[segments].offset = doffset;
compress((char *)&header[phdr[i].p_offset],
phdr[i].p_filesz,
(char *)(sptr + doffset), (int *)&segs[segments].len);
doffset += segs[segments].len;
osize += segs[segments].len;
segments++;
}
segs[segments].type = SELF_TYPE_ENTRY;
segs[segments++].load_addr = (unsigned long long)ehdr->e_entry;
*buffer = sptr;
munmap(filep, s.st_size);
close(fd);
return (segments * sizeof(struct self_segment)) + osize;
err:
munmap(filep, s.st_size);
close(fd);
return -1;
}
int iself(char *filename)
{
Elf32_Ehdr ehdr;
int fd = open(filename, O_RDONLY);
int ret = 0;
if (fd == -1)
return 0;
if (read(fd, &ehdr, sizeof(ehdr)) == sizeof(ehdr))
ret = !memcmp(ehdr.e_ident, ELFMAG, 4);
close(fd);
return ret;
}

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SELF_H_
#define SELF_H_
struct self_segment {
u32 type;
u32 offset;
u64 load_addr;
u32 len;
u32 mem_len;
};
#define SELF_TYPE_CODE 0x45444F43
#define SELF_TYPE_DATA 0x41544144
#define SELF_TYPE_BSS 0x20535342
#define SELF_TYPE_PARAMS 0x41524150
#define SELF_TYPE_ENTRY 0x52544E45
int elf_to_self(const char *filename, unsigned char **buffer,
void (*compress) (char *, int, char *, int *));
int iself(char *filename);
#endif

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// InBuffer.h
#ifndef __INBUFFER_H
#define __INBUFFER_H
#include "../IStream.h"
#include "../../Common/MyCom.h"
#ifndef _NO_EXCEPTIONS
class CInBufferException
{
public:
HRESULT ErrorCode;
CInBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
};
#endif
class CInBuffer
{
Byte *_buffer;
Byte *_bufferLimit;
Byte *_bufferBase;
CMyComPtr<ISequentialInStream> _stream;
UInt64 _processedSize;
UInt32 _bufferSize;
bool _wasFinished;
bool ReadBlock();
Byte ReadBlock2();
public:
#ifdef _NO_EXCEPTIONS
HRESULT ErrorCode;
#endif
CInBuffer();
~CInBuffer() { Free(); }
bool Create(UInt32 bufferSize);
void Free();
void SetStream(ISequentialInStream *stream);
void Init();
void ReleaseStream() { _stream.Release(); }
bool ReadByte(Byte &b)
{
if(_buffer >= _bufferLimit)
if(!ReadBlock())
return false;
b = *_buffer++;
return true;
}
Byte ReadByte()
{
if(_buffer >= _bufferLimit)
return ReadBlock2();
return *_buffer++;
}
void ReadBytes(void *data, UInt32 size, UInt32 &processedSize)
{
for(processedSize = 0; processedSize < size; processedSize++)
if (!ReadByte(((Byte *)data)[processedSize]))
return;
}
bool ReadBytes(void *data, UInt32 size)
{
UInt32 processedSize;
ReadBytes(data, size, processedSize);
return (processedSize == size);
}
UInt64 GetProcessedSize() const { return _processedSize + (_buffer - _bufferBase); }
bool WasFinished() const { return _wasFinished; }
};
#endif

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@ -0,0 +1,116 @@
// OutByte.cpp
#include "StdAfx.h"
#include "OutBuffer.h"
#include "../../Common/Alloc.h"
bool COutBuffer::Create(UInt32 bufferSize)
{
const UInt32 kMinBlockSize = 1;
if (bufferSize < kMinBlockSize)
bufferSize = kMinBlockSize;
if (_buffer != 0 && _bufferSize == bufferSize)
return true;
Free();
_bufferSize = bufferSize;
_buffer = (Byte *)::MidAlloc(bufferSize);
return (_buffer != 0);
}
void COutBuffer::Free()
{
::MidFree(_buffer);
_buffer = 0;
}
void COutBuffer::SetStream(ISequentialOutStream *stream)
{
_stream = stream;
}
void COutBuffer::Init()
{
_streamPos = 0;
_limitPos = _bufferSize;
_pos = 0;
_processedSize = 0;
_overDict = false;
#ifdef _NO_EXCEPTIONS
ErrorCode = S_OK;
#endif
}
UInt64 COutBuffer::GetProcessedSize() const
{
UInt64 res = _processedSize + _pos - _streamPos;
if (_streamPos > _pos)
res += _bufferSize;
return res;
}
HRESULT COutBuffer::FlushPart()
{
// _streamPos < _bufferSize
UInt32 size = (_streamPos >= _pos) ? (_bufferSize - _streamPos) : (_pos - _streamPos);
HRESULT result = S_OK;
#ifdef _NO_EXCEPTIONS
result = ErrorCode;
#endif
if (_buffer2 != 0)
{
memmove(_buffer2, _buffer + _streamPos, size);
_buffer2 += size;
}
if (_stream != 0
#ifdef _NO_EXCEPTIONS
&& (ErrorCode == S_OK)
#endif
)
{
UInt32 processedSize = 0;
result = _stream->Write(_buffer + _streamPos, size, &processedSize);
size = processedSize;
}
_streamPos += size;
if (_streamPos == _bufferSize)
_streamPos = 0;
if (_pos == _bufferSize)
{
_overDict = true;
_pos = 0;
}
_limitPos = (_streamPos > _pos) ? _streamPos : _bufferSize;
_processedSize += size;
return result;
}
HRESULT COutBuffer::Flush()
{
#ifdef _NO_EXCEPTIONS
if (ErrorCode != S_OK)
return ErrorCode;
#endif
while(_streamPos != _pos)
{
HRESULT result = FlushPart();
if (result != S_OK)
return result;
}
return S_OK;
}
void COutBuffer::FlushWithCheck()
{
HRESULT result = FlushPart();
#ifdef _NO_EXCEPTIONS
ErrorCode = result;
#else
if (result != S_OK)
throw COutBufferException(result);
#endif
}

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// OutBuffer.h
#ifndef __OUTBUFFER_H
#define __OUTBUFFER_H
#include "../IStream.h"
#include "../../Common/MyCom.h"
#ifndef _NO_EXCEPTIONS
struct COutBufferException
{
HRESULT ErrorCode;
COutBufferException(HRESULT errorCode): ErrorCode(errorCode) {}
};
#endif
class COutBuffer
{
protected:
Byte *_buffer;
UInt32 _pos;
UInt32 _limitPos;
UInt32 _streamPos;
UInt32 _bufferSize;
CMyComPtr<ISequentialOutStream> _stream;
UInt64 _processedSize;
Byte *_buffer2;
bool _overDict;
HRESULT FlushPart();
void FlushWithCheck();
public:
#ifdef _NO_EXCEPTIONS
HRESULT ErrorCode;
#endif
COutBuffer(): _buffer(0), _pos(0), _stream(0), _buffer2(0) {}
~COutBuffer() { Free(); }
bool Create(UInt32 bufferSize);
void Free();
void SetMemStream(Byte *buffer) { _buffer2 = buffer; }
void SetStream(ISequentialOutStream *stream);
void Init();
HRESULT Flush();
void ReleaseStream() { _stream.Release(); }
void WriteByte(Byte b)
{
_buffer[_pos++] = b;
if(_pos == _limitPos)
FlushWithCheck();
}
void WriteBytes(const void *data, size_t size)
{
for (size_t i = 0; i < size; i++)
WriteByte(((const Byte *)data)[i]);
}
UInt64 GetProcessedSize() const;
};
#endif

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// StdAfx.h
#ifndef __STDAFX_H
#define __STDAFX_H
#include "../../Common/MyWindows.h"
#include "../../Common/NewHandler.h"
#endif

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// StreamUtils.cpp
#include "StdAfx.h"
#include "../../Common/MyCom.h"
#include "StreamUtils.h"
HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize)
{
if (processedSize != 0)
*processedSize = 0;
while(size != 0)
{
UInt32 processedSizeLoc;
HRESULT res = stream->Read(data, size, &processedSizeLoc);
if (processedSize != 0)
*processedSize += processedSizeLoc;
data = (Byte *)((Byte *)data + processedSizeLoc);
size -= processedSizeLoc;
RINOK(res);
if (processedSizeLoc == 0)
return S_OK;
}
return S_OK;
}
HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize)
{
if (processedSize != 0)
*processedSize = 0;
while(size != 0)
{
UInt32 processedSizeLoc;
HRESULT res = stream->Write(data, size, &processedSizeLoc);
if (processedSize != 0)
*processedSize += processedSizeLoc;
data = (const void *)((const Byte *)data + processedSizeLoc);
size -= processedSizeLoc;
RINOK(res);
if (processedSizeLoc == 0)
break;
}
return S_OK;
}

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// StreamUtils.h
#ifndef __STREAMUTILS_H
#define __STREAMUTILS_H
#include "../IStream.h"
HRESULT ReadStream(ISequentialInStream *stream, void *data, UInt32 size, UInt32 *processedSize);
HRESULT WriteStream(ISequentialOutStream *stream, const void *data, UInt32 size, UInt32 *processedSize);
#endif

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// BinTree.h
#include "../LZInWindow.h"
#include "../IMatchFinder.h"
namespace BT_NAMESPACE {
typedef UInt32 CIndex;
const UInt32 kMaxValForNormalize = (UInt32(1) << 31) - 1;
class CMatchFinder:
public IMatchFinder,
public CLZInWindow,
public CMyUnknownImp,
public IMatchFinderSetNumPasses
{
UInt32 _cyclicBufferPos;
UInt32 _cyclicBufferSize; // it must be historySize + 1
UInt32 _matchMaxLen;
CIndex *_hash;
CIndex *_son;
UInt32 _hashMask;
UInt32 _cutValue;
UInt32 _hashSizeSum;
void Normalize();
void FreeThisClassMemory();
void FreeMemory();
MY_UNKNOWN_IMP
STDMETHOD(SetStream)(ISequentialInStream *inStream);
STDMETHOD_(void, ReleaseStream)();
STDMETHOD(Init)();
HRESULT MovePos();
STDMETHOD_(Byte, GetIndexByte)(Int32 index);
STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 back, UInt32 limit);
STDMETHOD_(UInt32, GetNumAvailableBytes)();
STDMETHOD_(const Byte *, GetPointerToCurrentPos)();
STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes);
STDMETHOD_(void, ChangeBufferPos)();
STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore,
UInt32 matchMaxLen, UInt32 keepAddBufferAfter);
STDMETHOD(GetMatches)(UInt32 *distances);
STDMETHOD(Skip)(UInt32 num);
public:
CMatchFinder();
virtual ~CMatchFinder();
virtual void SetNumPasses(UInt32 numPasses) { _cutValue = numPasses; }
};
}

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// BinTree2.h
#ifndef __BINTREE2_H
#define __BINTREE2_H
#define BT_NAMESPACE NBT2
#include "BinTreeMain.h"
#undef BT_NAMESPACE
#endif

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@ -0,0 +1,16 @@
// BinTree3.h
#ifndef __BINTREE3_H
#define __BINTREE3_H
#define BT_NAMESPACE NBT3
#define HASH_ARRAY_2
#include "BinTreeMain.h"
#undef HASH_ARRAY_2
#undef BT_NAMESPACE
#endif

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// BinTree4.h
#ifndef __BINTREE4_H
#define __BINTREE4_H
#define BT_NAMESPACE NBT4
#define HASH_ARRAY_2
#define HASH_ARRAY_3
#include "BinTreeMain.h"
#undef HASH_ARRAY_2
#undef HASH_ARRAY_3
#undef BT_NAMESPACE
#endif

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// BinTreeMain.h
#include "../../../../Common/Defs.h"
#include "../../../../Common/CRC.h"
#include "../../../../Common/Alloc.h"
#include "BinTree.h"
// #include <xmmintrin.h>
// It's for prefetch
// But prefetch doesn't give big gain in K8.
namespace BT_NAMESPACE {
#ifdef HASH_ARRAY_2
static const UInt32 kHash2Size = 1 << 10;
#define kNumHashDirectBytes 0
#ifdef HASH_ARRAY_3
static const UInt32 kNumHashBytes = 4;
static const UInt32 kHash3Size = 1 << 16;
#else
static const UInt32 kNumHashBytes = 3;
#endif
static const UInt32 kHashSize = 0;
static const UInt32 kMinMatchCheck = kNumHashBytes;
static const UInt32 kStartMaxLen = 1;
#else
#ifdef HASH_ZIP
#define kNumHashDirectBytes 0
static const UInt32 kNumHashBytes = 3;
static const UInt32 kHashSize = 1 << 16;
static const UInt32 kMinMatchCheck = kNumHashBytes;
static const UInt32 kStartMaxLen = 1;
#else
#define kNumHashDirectBytes 2
static const UInt32 kNumHashBytes = 2;
static const UInt32 kHashSize = 1 << (8 * kNumHashBytes);
static const UInt32 kMinMatchCheck = kNumHashBytes + 1;
static const UInt32 kStartMaxLen = 1;
#endif
#endif
#ifdef HASH_ARRAY_2
#ifdef HASH_ARRAY_3
static const UInt32 kHash3Offset = kHash2Size;
#endif
#endif
static const UInt32 kFixHashSize = 0
#ifdef HASH_ARRAY_2
+ kHash2Size
#ifdef HASH_ARRAY_3
+ kHash3Size
#endif
#endif
;
CMatchFinder::CMatchFinder():
_hash(0)
{
}
void CMatchFinder::FreeThisClassMemory()
{
BigFree(_hash);
_hash = 0;
}
void CMatchFinder::FreeMemory()
{
FreeThisClassMemory();
CLZInWindow::Free();
}
CMatchFinder::~CMatchFinder()
{
FreeMemory();
}
STDMETHODIMP CMatchFinder::Create(UInt32 historySize, UInt32 keepAddBufferBefore,
UInt32 matchMaxLen, UInt32 keepAddBufferAfter)
{
if (historySize > kMaxValForNormalize - 256)
{
FreeMemory();
return E_INVALIDARG;
}
_cutValue =
#ifdef _HASH_CHAIN
8 + (matchMaxLen >> 2);
#else
16 + (matchMaxLen >> 1);
#endif
UInt32 sizeReserv = (historySize + keepAddBufferBefore +
matchMaxLen + keepAddBufferAfter) / 2 + 256;
if (CLZInWindow::Create(historySize + keepAddBufferBefore,
matchMaxLen + keepAddBufferAfter, sizeReserv))
{
_matchMaxLen = matchMaxLen;
UInt32 newCyclicBufferSize = historySize + 1;
if (_hash != 0 && newCyclicBufferSize == _cyclicBufferSize)
return S_OK;
FreeThisClassMemory();
_cyclicBufferSize = newCyclicBufferSize; // don't change it
UInt32 hs = kHashSize;
#ifdef HASH_ARRAY_2
hs = historySize - 1;
hs |= (hs >> 1);
hs |= (hs >> 2);
hs |= (hs >> 4);
hs |= (hs >> 8);
hs >>= 1;
hs |= 0xFFFF;
if (hs > (1 << 24))
{
#ifdef HASH_ARRAY_3
hs >>= 1;
#else
hs = (1 << 24) - 1;
#endif
}
_hashMask = hs;
hs++;
#endif
_hashSizeSum = hs + kFixHashSize;
UInt32 numItems = _hashSizeSum + _cyclicBufferSize
#ifndef _HASH_CHAIN
* 2
#endif
;
size_t sizeInBytes = (size_t)numItems * sizeof(CIndex);
if (sizeInBytes / sizeof(CIndex) != numItems)
return E_OUTOFMEMORY;
_hash = (CIndex *)BigAlloc(sizeInBytes);
_son = _hash + _hashSizeSum;
if (_hash != 0)
return S_OK;
}
FreeMemory();
return E_OUTOFMEMORY;
}
static const UInt32 kEmptyHashValue = 0;
STDMETHODIMP CMatchFinder::SetStream(ISequentialInStream *stream)
{
CLZInWindow::SetStream(stream);
return S_OK;
}
STDMETHODIMP CMatchFinder::Init()
{
RINOK(CLZInWindow::Init());
for(UInt32 i = 0; i < _hashSizeSum; i++)
_hash[i] = kEmptyHashValue;
_cyclicBufferPos = 0;
ReduceOffsets(-1);
return S_OK;
}
STDMETHODIMP_(void) CMatchFinder::ReleaseStream()
{
// ReleaseStream();
}
#ifdef HASH_ARRAY_2
#ifdef HASH_ARRAY_3
#define HASH_CALC { \
UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
hash2Value = temp & (kHash2Size - 1); \
hash3Value = (temp ^ (UInt32(cur[2]) << 8)) & (kHash3Size - 1); \
hashValue = (temp ^ (UInt32(cur[2]) << 8) ^ (CCRC::Table[cur[3]] << 5)) & _hashMask; }
#else // no HASH_ARRAY_3
#define HASH_CALC { \
UInt32 temp = CCRC::Table[cur[0]] ^ cur[1]; \
hash2Value = temp & (kHash2Size - 1); \
hashValue = (temp ^ (UInt32(cur[2]) << 8)) & _hashMask; }
#endif // HASH_ARRAY_3
#else // no HASH_ARRAY_2
#ifdef HASH_ZIP
inline UInt32 Hash(const Byte *pointer)
{
return ((UInt32(pointer[0]) << 8) ^ CCRC::Table[pointer[1]] ^ pointer[2]) & (kHashSize - 1);
}
#else // no HASH_ZIP
inline UInt32 Hash(const Byte *pointer)
{
return pointer[0] ^ (UInt32(pointer[1]) << 8);
}
#endif // HASH_ZIP
#endif // HASH_ARRAY_2
STDMETHODIMP CMatchFinder::GetMatches(UInt32 *distances)
{
UInt32 lenLimit;
if (_pos + _matchMaxLen <= _streamPos)
lenLimit = _matchMaxLen;
else
{
lenLimit = _streamPos - _pos;
if(lenLimit < kMinMatchCheck)
{
distances[0] = 0;
return MovePos();
}
}
int offset = 1;
UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
const Byte *cur = _buffer + _pos;
UInt32 maxLen = kStartMaxLen; // to avoid items for len < hashSize;
#ifdef HASH_ARRAY_2
UInt32 hash2Value;
#ifdef HASH_ARRAY_3
UInt32 hash3Value;
#endif
UInt32 hashValue;
HASH_CALC;
#else
UInt32 hashValue = Hash(cur);
#endif
UInt32 curMatch = _hash[kFixHashSize + hashValue];
#ifdef HASH_ARRAY_2
UInt32 curMatch2 = _hash[hash2Value];
#ifdef HASH_ARRAY_3
UInt32 curMatch3 = _hash[kHash3Offset + hash3Value];
#endif
_hash[hash2Value] = _pos;
if(curMatch2 > matchMinPos)
if (_buffer[curMatch2] == cur[0])
{
distances[offset++] = maxLen = 2;
distances[offset++] = _pos - curMatch2 - 1;
}
#ifdef HASH_ARRAY_3
_hash[kHash3Offset + hash3Value] = _pos;
if(curMatch3 > matchMinPos)
if (_buffer[curMatch3] == cur[0])
{
if (curMatch3 == curMatch2)
offset -= 2;
distances[offset++] = maxLen = 3;
distances[offset++] = _pos - curMatch3 - 1;
curMatch2 = curMatch3;
}
#endif
if (offset != 1 && curMatch2 == curMatch)
{
offset -= 2;
maxLen = kStartMaxLen;
}
#endif
_hash[kFixHashSize + hashValue] = _pos;
CIndex *son = _son;
#ifdef _HASH_CHAIN
son[_cyclicBufferPos] = curMatch;
#else
CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
CIndex *ptr1 = son + (_cyclicBufferPos << 1);
UInt32 len0, len1;
len0 = len1 = kNumHashDirectBytes;
#endif
#if kNumHashDirectBytes != 0
if(curMatch > matchMinPos)
{
if (_buffer[curMatch + kNumHashDirectBytes] != cur[kNumHashDirectBytes])
{
distances[offset++] = maxLen = kNumHashDirectBytes;
distances[offset++] = _pos - curMatch - 1;
}
}
#endif
UInt32 count = _cutValue;
while(true)
{
if(curMatch <= matchMinPos || count-- == 0)
{
#ifndef _HASH_CHAIN
*ptr0 = *ptr1 = kEmptyHashValue;
#endif
break;
}
UInt32 delta = _pos - curMatch;
UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
(_cyclicBufferPos - delta):
(_cyclicBufferPos - delta + _cyclicBufferSize);
CIndex *pair = son +
#ifdef _HASH_CHAIN
cyclicPos;
#else
(cyclicPos << 1);
#endif
// _mm_prefetch((const char *)pair, _MM_HINT_T0);
const Byte *pb = _buffer + curMatch;
UInt32 len =
#ifdef _HASH_CHAIN
kNumHashDirectBytes;
if (pb[maxLen] == cur[maxLen])
#else
MyMin(len0, len1);
#endif
if (pb[len] == cur[len])
{
while(++len != lenLimit)
if (pb[len] != cur[len])
break;
if (maxLen < len)
{
distances[offset++] = maxLen = len;
distances[offset++] = delta - 1;
if (len == lenLimit)
{
#ifndef _HASH_CHAIN
*ptr1 = pair[0];
*ptr0 = pair[1];
#endif
break;
}
}
}
#ifdef _HASH_CHAIN
curMatch = *pair;
#else
if (pb[len] < cur[len])
{
*ptr1 = curMatch;
ptr1 = pair + 1;
curMatch = *ptr1;
len1 = len;
}
else
{
*ptr0 = curMatch;
ptr0 = pair;
curMatch = *ptr0;
len0 = len;
}
#endif
}
distances[0] = offset - 1;
if (++_cyclicBufferPos == _cyclicBufferSize)
_cyclicBufferPos = 0;
RINOK(CLZInWindow::MovePos());
if (_pos == kMaxValForNormalize)
Normalize();
return S_OK;
}
STDMETHODIMP CMatchFinder::Skip(UInt32 num)
{
do
{
#ifdef _HASH_CHAIN
if (_streamPos - _pos < kNumHashBytes)
{
RINOK(MovePos());
continue;
}
#else
UInt32 lenLimit;
if (_pos + _matchMaxLen <= _streamPos)
lenLimit = _matchMaxLen;
else
{
lenLimit = _streamPos - _pos;
if(lenLimit < kMinMatchCheck)
{
RINOK(MovePos());
continue;
}
}
UInt32 matchMinPos = (_pos > _cyclicBufferSize) ? (_pos - _cyclicBufferSize) : 0;
#endif
const Byte *cur = _buffer + _pos;
#ifdef HASH_ARRAY_2
UInt32 hash2Value;
#ifdef HASH_ARRAY_3
UInt32 hash3Value;
UInt32 hashValue;
HASH_CALC;
_hash[kHash3Offset + hash3Value] = _pos;
#else
UInt32 hashValue;
HASH_CALC;
#endif
_hash[hash2Value] = _pos;
#else
UInt32 hashValue = Hash(cur);
#endif
UInt32 curMatch = _hash[kFixHashSize + hashValue];
_hash[kFixHashSize + hashValue] = _pos;
#ifdef _HASH_CHAIN
_son[_cyclicBufferPos] = curMatch;
#else
CIndex *son = _son;
CIndex *ptr0 = son + (_cyclicBufferPos << 1) + 1;
CIndex *ptr1 = son + (_cyclicBufferPos << 1);
UInt32 len0, len1;
len0 = len1 = kNumHashDirectBytes;
UInt32 count = _cutValue;
while(true)
{
if(curMatch <= matchMinPos || count-- == 0)
{
*ptr0 = *ptr1 = kEmptyHashValue;
break;
}
UInt32 delta = _pos - curMatch;
UInt32 cyclicPos = (delta <= _cyclicBufferPos) ?
(_cyclicBufferPos - delta):
(_cyclicBufferPos - delta + _cyclicBufferSize);
CIndex *pair = son + (cyclicPos << 1);
// _mm_prefetch((const char *)pair, _MM_HINT_T0);
const Byte *pb = _buffer + curMatch;
UInt32 len = MyMin(len0, len1);
if (pb[len] == cur[len])
{
while(++len != lenLimit)
if (pb[len] != cur[len])
break;
if (len == lenLimit)
{
*ptr1 = pair[0];
*ptr0 = pair[1];
break;
}
}
if (pb[len] < cur[len])
{
*ptr1 = curMatch;
ptr1 = pair + 1;
curMatch = *ptr1;
len1 = len;
}
else
{
*ptr0 = curMatch;
ptr0 = pair;
curMatch = *ptr0;
len0 = len;
}
}
#endif
if (++_cyclicBufferPos == _cyclicBufferSize)
_cyclicBufferPos = 0;
RINOK(CLZInWindow::MovePos());
if (_pos == kMaxValForNormalize)
Normalize();
}
while(--num != 0);
return S_OK;
}
void CMatchFinder::Normalize()
{
UInt32 subValue = _pos - _cyclicBufferSize;
CIndex *items = _hash;
UInt32 numItems = (_hashSizeSum + _cyclicBufferSize
#ifndef _HASH_CHAIN
* 2
#endif
);
for (UInt32 i = 0; i < numItems; i++)
{
UInt32 value = items[i];
if (value <= subValue)
value = kEmptyHashValue;
else
value -= subValue;
items[i] = value;
}
ReduceOffsets(subValue);
}
HRESULT CMatchFinder::MovePos()
{
if (++_cyclicBufferPos == _cyclicBufferSize)
_cyclicBufferPos = 0;
RINOK(CLZInWindow::MovePos());
if (_pos == kMaxValForNormalize)
Normalize();
return S_OK;
}
STDMETHODIMP_(Byte) CMatchFinder::GetIndexByte(Int32 index)
{ return CLZInWindow::GetIndexByte(index); }
STDMETHODIMP_(UInt32) CMatchFinder::GetMatchLen(Int32 index,
UInt32 back, UInt32 limit)
{ return CLZInWindow::GetMatchLen(index, back, limit); }
STDMETHODIMP_(UInt32) CMatchFinder::GetNumAvailableBytes()
{ return CLZInWindow::GetNumAvailableBytes(); }
STDMETHODIMP_(const Byte *) CMatchFinder::GetPointerToCurrentPos()
{ return CLZInWindow::GetPointerToCurrentPos(); }
STDMETHODIMP_(Int32) CMatchFinder::NeedChangeBufferPos(UInt32 numCheckBytes)
{ return CLZInWindow::NeedMove(numCheckBytes) ? 1: 0; }
STDMETHODIMP_(void) CMatchFinder::ChangeBufferPos()
{ CLZInWindow::MoveBlock();}
#undef HASH_CALC
#undef kNumHashDirectBytes
}

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// HC4.h
#ifndef __HC4_H
#define __HC4_H
#define BT_NAMESPACE NHC4
#define HASH_ARRAY_2
#define HASH_ARRAY_3
#include "HCMain.h"
#undef HASH_ARRAY_2
#undef HASH_ARRAY_3
#undef BT_NAMESPACE
#endif

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// HCMain.h
#define _HASH_CHAIN
#include "../BinTree/BinTreeMain.h"
#undef _HASH_CHAIN

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// MatchFinders/IMatchFinder.h
#ifndef __IMATCHFINDER_H
#define __IMATCHFINDER_H
struct IInWindowStream: public IUnknown
{
STDMETHOD(SetStream)(ISequentialInStream *inStream) PURE;
STDMETHOD_(void, ReleaseStream)() PURE;
STDMETHOD(Init)() PURE;
STDMETHOD_(Byte, GetIndexByte)(Int32 index) PURE;
STDMETHOD_(UInt32, GetMatchLen)(Int32 index, UInt32 distance, UInt32 limit) PURE;
STDMETHOD_(UInt32, GetNumAvailableBytes)() PURE;
STDMETHOD_(const Byte *, GetPointerToCurrentPos)() PURE;
STDMETHOD_(Int32, NeedChangeBufferPos)(UInt32 numCheckBytes) PURE;
STDMETHOD_(void, ChangeBufferPos)() PURE;
};
struct IMatchFinder: public IInWindowStream
{
STDMETHOD(Create)(UInt32 historySize, UInt32 keepAddBufferBefore,
UInt32 matchMaxLen, UInt32 keepAddBufferAfter) PURE;
STDMETHOD(GetMatches)(UInt32 *distances) PURE;
STDMETHOD(Skip)(UInt32 num) PURE;
};
struct IMatchFinderSetNumPasses
{
//virtual ~IMatchFinderSetNumPasses(){}
virtual void SetNumPasses(UInt32 numPasses) PURE;
};
#endif

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// LZInWindow.cpp
#include "StdAfx.h"
#include "LZInWindow.h"
#include "../../../Common/MyCom.h"
#include "../../../Common/Alloc.h"
void CLZInWindow::Free()
{
::BigFree(_bufferBase);
_bufferBase = 0;
}
bool CLZInWindow::Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv)
{
_keepSizeBefore = keepSizeBefore;
_keepSizeAfter = keepSizeAfter;
UInt32 blockSize = keepSizeBefore + keepSizeAfter + keepSizeReserv;
if (_bufferBase == 0 || _blockSize != blockSize)
{
Free();
_blockSize = blockSize;
if (_blockSize != 0)
_bufferBase = (Byte *)::BigAlloc(_blockSize);
}
_pointerToLastSafePosition = _bufferBase + _blockSize - keepSizeAfter;
if (_blockSize == 0)
return true;
return (_bufferBase != 0);
}
void CLZInWindow::SetStream(ISequentialInStream *stream)
{
_stream = stream;
}
HRESULT CLZInWindow::Init()
{
_buffer = _bufferBase;
_pos = 0;
_streamPos = 0;
_streamEndWasReached = false;
return ReadBlock();
}
/*
void CLZInWindow::ReleaseStream()
{
_stream.Release();
}
*/
///////////////////////////////////////////
// ReadBlock
// In State:
// (_buffer + _streamPos) <= (_bufferBase + _blockSize)
// Out State:
// _posLimit <= _blockSize - _keepSizeAfter;
// if(_streamEndWasReached == false):
// _streamPos >= _pos + _keepSizeAfter
// _posLimit = _streamPos - _keepSizeAfter;
// else
//
HRESULT CLZInWindow::ReadBlock()
{
if(_streamEndWasReached)
return S_OK;
while(true)
{
UInt32 size = (UInt32)(_bufferBase - _buffer) + _blockSize - _streamPos;
if(size == 0)
return S_OK;
UInt32 numReadBytes;
RINOK(_stream->Read(_buffer + _streamPos, size, &numReadBytes));
if(numReadBytes == 0)
{
_posLimit = _streamPos;
const Byte *pointerToPostion = _buffer + _posLimit;
if(pointerToPostion > _pointerToLastSafePosition)
_posLimit = (UInt32)(_pointerToLastSafePosition - _buffer);
_streamEndWasReached = true;
return S_OK;
}
_streamPos += numReadBytes;
if(_streamPos >= _pos + _keepSizeAfter)
{
_posLimit = _streamPos - _keepSizeAfter;
return S_OK;
}
}
}
void CLZInWindow::MoveBlock()
{
UInt32 offset = (UInt32)(_buffer - _bufferBase) + _pos - _keepSizeBefore;
// we need one additional byte, since MovePos moves on 1 byte.
if (offset > 0)
offset--;
UInt32 numBytes = (UInt32)(_buffer - _bufferBase) + _streamPos - offset;
memmove(_bufferBase, _bufferBase + offset, numBytes);
_buffer -= offset;
}

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// LZInWindow.h
#ifndef __LZ_IN_WINDOW_H
#define __LZ_IN_WINDOW_H
#include "../../IStream.h"
class CLZInWindow
{
Byte *_bufferBase; // pointer to buffer with data
ISequentialInStream *_stream;
UInt32 _posLimit; // offset (from _buffer) when new block reading must be done
bool _streamEndWasReached; // if (true) then _streamPos shows real end of stream
const Byte *_pointerToLastSafePosition;
protected:
Byte *_buffer; // Pointer to virtual Buffer begin
UInt32 _blockSize; // Size of Allocated memory block
UInt32 _pos; // offset (from _buffer) of curent byte
UInt32 _keepSizeBefore; // how many BYTEs must be kept in buffer before _pos
UInt32 _keepSizeAfter; // how many BYTEs must be kept buffer after _pos
UInt32 _streamPos; // offset (from _buffer) of first not read byte from Stream
void MoveBlock();
HRESULT ReadBlock();
void Free();
public:
CLZInWindow(): _bufferBase(0) {}
virtual ~CLZInWindow() { Free(); }
// keepSizeBefore + keepSizeAfter + keepSizeReserv < 4G)
bool Create(UInt32 keepSizeBefore, UInt32 keepSizeAfter, UInt32 keepSizeReserv = (1<<17));
void SetStream(ISequentialInStream *stream);
HRESULT Init();
// void ReleaseStream();
Byte *GetBuffer() const { return _buffer; }
const Byte *GetPointerToCurrentPos() const { return _buffer + _pos; }
HRESULT MovePos()
{
_pos++;
if (_pos > _posLimit)
{
const Byte *pointerToPostion = _buffer + _pos;
if(pointerToPostion > _pointerToLastSafePosition)
MoveBlock();
return ReadBlock();
}
else
return S_OK;
}
Byte GetIndexByte(Int32 index) const { return _buffer[(size_t)_pos + index]; }
// index + limit have not to exceed _keepSizeAfter;
// -2G <= index < 2G
UInt32 GetMatchLen(Int32 index, UInt32 distance, UInt32 limit) const
{
if(_streamEndWasReached)
if ((_pos + index) + limit > _streamPos)
limit = _streamPos - (_pos + index);
distance++;
const Byte *pby = _buffer + (size_t)_pos + index;
UInt32 i;
for(i = 0; i < limit && pby[i] == pby[(size_t)i - distance]; i++);
return i;
}
UInt32 GetNumAvailableBytes() const { return _streamPos - _pos; }
void ReduceOffsets(Int32 subValue)
{
_buffer += subValue;
_posLimit -= subValue;
_pos -= subValue;
_streamPos -= subValue;
}
bool NeedMove(UInt32 numCheckBytes)
{
UInt32 reserv = _pointerToLastSafePosition - (_buffer + _pos);
return (reserv <= numCheckBytes);
}
};
#endif

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// StdAfx.h
#ifndef __STDAFX_H
#define __STDAFX_H
#endif

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// LZMA.h
#ifndef __LZMA_H
#define __LZMA_H
namespace NCompress {
namespace NLZMA {
const UInt32 kNumRepDistances = 4;
const int kNumStates = 12;
const Byte kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5};
const Byte kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};
const Byte kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};
const Byte kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};
class CState
{
public:
Byte Index;
void Init() { Index = 0; }
void UpdateChar() { Index = kLiteralNextStates[Index]; }
void UpdateMatch() { Index = kMatchNextStates[Index]; }
void UpdateRep() { Index = kRepNextStates[Index]; }
void UpdateShortRep() { Index = kShortRepNextStates[Index]; }
bool IsCharState() const { return Index < 7; }
};
const int kNumPosSlotBits = 6;
const int kDicLogSizeMin = 0;
const int kDicLogSizeMax = 32;
const int kDistTableSizeMax = kDicLogSizeMax * 2;
const UInt32 kNumLenToPosStates = 4;
inline UInt32 GetLenToPosState(UInt32 len)
{
len -= 2;
if (len < kNumLenToPosStates)
return len;
return kNumLenToPosStates - 1;
}
namespace NLength {
const int kNumPosStatesBitsMax = 4;
const UInt32 kNumPosStatesMax = (1 << kNumPosStatesBitsMax);
const int kNumPosStatesBitsEncodingMax = 4;
const UInt32 kNumPosStatesEncodingMax = (1 << kNumPosStatesBitsEncodingMax);
const int kNumLowBits = 3;
const int kNumMidBits = 3;
const int kNumHighBits = 8;
const UInt32 kNumLowSymbols = 1 << kNumLowBits;
const UInt32 kNumMidSymbols = 1 << kNumMidBits;
const UInt32 kNumSymbolsTotal = kNumLowSymbols + kNumMidSymbols + (1 << kNumHighBits);
}
const UInt32 kMatchMinLen = 2;
const UInt32 kMatchMaxLen = kMatchMinLen + NLength::kNumSymbolsTotal - 1;
const int kNumAlignBits = 4;
const UInt32 kAlignTableSize = 1 << kNumAlignBits;
const UInt32 kAlignMask = (kAlignTableSize - 1);
const UInt32 kStartPosModelIndex = 4;
const UInt32 kEndPosModelIndex = 14;
const UInt32 kNumPosModels = kEndPosModelIndex - kStartPosModelIndex;
const UInt32 kNumFullDistances = 1 << (kEndPosModelIndex / 2);
const int kNumLitPosStatesBitsEncodingMax = 4;
const int kNumLitContextBitsMax = 8;
const int kNumMoveBits = 5;
}}
#endif

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// LZMA/Encoder.h
#ifndef __LZMA_ENCODER_H
#define __LZMA_ENCODER_H
#include "../../../Common/MyCom.h"
#include "../../../Common/Alloc.h"
#include "../../ICoder.h"
#include "../LZ/IMatchFinder.h"
#include "../RangeCoder/RangeCoderBitTree.h"
#include "LZMA.h"
namespace NCompress {
namespace NLZMA {
typedef NRangeCoder::CBitEncoder<kNumMoveBits> CMyBitEncoder;
class CBaseState
{
protected:
CState _state;
Byte _previousByte;
UInt32 _repDistances[kNumRepDistances];
void Init()
{
_state.Init();
_previousByte = 0;
for(UInt32 i = 0 ; i < kNumRepDistances; i++)
_repDistances[i] = 0;
}
};
struct COptimal
{
CState State;
bool Prev1IsChar;
bool Prev2;
UInt32 PosPrev2;
UInt32 BackPrev2;
UInt32 Price;
UInt32 PosPrev; // posNext;
UInt32 BackPrev;
UInt32 Backs[kNumRepDistances];
void MakeAsChar() { BackPrev = UInt32(-1); Prev1IsChar = false; }
void MakeAsShortRep() { BackPrev = 0; ; Prev1IsChar = false; }
bool IsShortRep() { return (BackPrev == 0); }
};
extern Byte g_FastPos[1 << 11];
inline UInt32 GetPosSlot(UInt32 pos)
{
if (pos < (1 << 11))
return g_FastPos[pos];
if (pos < (1 << 21))
return g_FastPos[pos >> 10] + 20;
return g_FastPos[pos >> 20] + 40;
}
inline UInt32 GetPosSlot2(UInt32 pos)
{
if (pos < (1 << 17))
return g_FastPos[pos >> 6] + 12;
if (pos < (1 << 27))
return g_FastPos[pos >> 16] + 32;
return g_FastPos[pos >> 26] + 52;
}
const UInt32 kIfinityPrice = 0xFFFFFFF;
const UInt32 kNumOpts = 1 << 12;
class CLiteralEncoder2
{
CMyBitEncoder _encoders[0x300];
public:
void Init()
{
for (int i = 0; i < 0x300; i++)
_encoders[i].Init();
}
void Encode(NRangeCoder::CEncoder *rangeEncoder, Byte symbol);
void EncodeMatched(NRangeCoder::CEncoder *rangeEncoder, Byte matchByte, Byte symbol);
UInt32 GetPrice(bool matchMode, Byte matchByte, Byte symbol) const;
};
class CLiteralEncoder
{
CLiteralEncoder2 *_coders;
int _numPrevBits;
int _numPosBits;
UInt32 _posMask;
public:
CLiteralEncoder(): _coders(0) {}
~CLiteralEncoder() { Free(); }
void Free()
{
MyFree(_coders);
_coders = 0;
}
bool Create(int numPosBits, int numPrevBits)
{
if (_coders == 0 || (numPosBits + numPrevBits) != (_numPrevBits + _numPosBits))
{
Free();
UInt32 numStates = 1 << (numPosBits + numPrevBits);
_coders = (CLiteralEncoder2 *)MyAlloc(numStates * sizeof(CLiteralEncoder2));
}
_numPosBits = numPosBits;
_posMask = (1 << numPosBits) - 1;
_numPrevBits = numPrevBits;
return (_coders != 0);
}
void Init()
{
UInt32 numStates = 1 << (_numPrevBits + _numPosBits);
for (UInt32 i = 0; i < numStates; i++)
_coders[i].Init();
}
CLiteralEncoder2 *GetSubCoder(UInt32 pos, Byte prevByte)
{ return &_coders[((pos & _posMask) << _numPrevBits) + (prevByte >> (8 - _numPrevBits))]; }
};
namespace NLength {
class CEncoder
{
CMyBitEncoder _choice;
CMyBitEncoder _choice2;
NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumLowBits> _lowCoder[kNumPosStatesEncodingMax];
NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumMidBits> _midCoder[kNumPosStatesEncodingMax];
NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumHighBits> _highCoder;
public:
void Init(UInt32 numPosStates);
void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState);
void SetPrices(UInt32 posState, UInt32 numSymbols, UInt32 *prices) const;
};
const UInt32 kNumSpecSymbols = kNumLowSymbols + kNumMidSymbols;
class CPriceTableEncoder: public CEncoder
{
UInt32 _prices[kNumPosStatesEncodingMax][kNumSymbolsTotal];
UInt32 _tableSize;
UInt32 _counters[kNumPosStatesEncodingMax];
public:
void SetTableSize(UInt32 tableSize) { _tableSize = tableSize; }
UInt32 GetPrice(UInt32 symbol, UInt32 posState) const { return _prices[posState][symbol]; }
void UpdateTable(UInt32 posState)
{
SetPrices(posState, _tableSize, _prices[posState]);
_counters[posState] = _tableSize;
}
void UpdateTables(UInt32 numPosStates)
{
for (UInt32 posState = 0; posState < numPosStates; posState++)
UpdateTable(posState);
}
void Encode(NRangeCoder::CEncoder *rangeEncoder, UInt32 symbol, UInt32 posState, bool updatePrice)
{
CEncoder::Encode(rangeEncoder, symbol, posState);
if (updatePrice)
if (--_counters[posState] == 0)
UpdateTable(posState);
}
};
}
class CEncoder :
public ICompressCoder,
public ICompressSetOutStream,
public ICompressSetCoderProperties,
public ICompressWriteCoderProperties,
public CBaseState,
public CMyUnknownImp
{
COptimal _optimum[kNumOpts];
CMyComPtr<IMatchFinder> _matchFinder; // test it
NRangeCoder::CEncoder _rangeEncoder;
CMyBitEncoder _isMatch[kNumStates][NLength::kNumPosStatesEncodingMax];
CMyBitEncoder _isRep[kNumStates];
CMyBitEncoder _isRepG0[kNumStates];
CMyBitEncoder _isRepG1[kNumStates];
CMyBitEncoder _isRepG2[kNumStates];
CMyBitEncoder _isRep0Long[kNumStates][NLength::kNumPosStatesEncodingMax];
NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumPosSlotBits> _posSlotEncoder[kNumLenToPosStates];
CMyBitEncoder _posEncoders[kNumFullDistances - kEndPosModelIndex];
NRangeCoder::CBitTreeEncoder<kNumMoveBits, kNumAlignBits> _posAlignEncoder;
NLength::CPriceTableEncoder _lenEncoder;
NLength::CPriceTableEncoder _repMatchLenEncoder;
CLiteralEncoder _literalEncoder;
UInt32 _matchDistances[kMatchMaxLen * 2 + 2 + 1];
bool _fastMode;
// bool _maxMode;
UInt32 _numFastBytes;
UInt32 _longestMatchLength;
UInt32 _numDistancePairs;
UInt32 _additionalOffset;
UInt32 _optimumEndIndex;
UInt32 _optimumCurrentIndex;
bool _longestMatchWasFound;
UInt32 _posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];
UInt32 _distancesPrices[kNumLenToPosStates][kNumFullDistances];
UInt32 _alignPrices[kAlignTableSize];
UInt32 _alignPriceCount;
UInt32 _distTableSize;
UInt32 _posStateBits;
UInt32 _posStateMask;
UInt32 _numLiteralPosStateBits;
UInt32 _numLiteralContextBits;
UInt32 _dictionarySize;
UInt32 _dictionarySizePrev;
UInt32 _numFastBytesPrev;
UInt32 _matchPriceCount;
UInt64 nowPos64;
bool _finished;
ISequentialInStream *_inStream;
UInt32 _matchFinderCycles;
int _matchFinderIndex;
#ifdef COMPRESS_MF_MT
bool _multiThread;
#endif
bool _writeEndMark;
bool _needReleaseMFStream;
IMatchFinderSetNumPasses *setMfPasses;
void ReleaseMatchFinder()
{
setMfPasses = 0;
_matchFinder.Release();
}
HRESULT ReadMatchDistances(UInt32 &len, UInt32 &numDistancePairs);
HRESULT MovePos(UInt32 num);
UInt32 GetRepLen1Price(CState state, UInt32 posState) const
{
return _isRepG0[state.Index].GetPrice0() +
_isRep0Long[state.Index][posState].GetPrice0();
}
UInt32 GetPureRepPrice(UInt32 repIndex, CState state, UInt32 posState) const
{
UInt32 price;
if(repIndex == 0)
{
price = _isRepG0[state.Index].GetPrice0();
price += _isRep0Long[state.Index][posState].GetPrice1();
}
else
{
price = _isRepG0[state.Index].GetPrice1();
if (repIndex == 1)
price += _isRepG1[state.Index].GetPrice0();
else
{
price += _isRepG1[state.Index].GetPrice1();
price += _isRepG2[state.Index].GetPrice(repIndex - 2);
}
}
return price;
}
UInt32 GetRepPrice(UInt32 repIndex, UInt32 len, CState state, UInt32 posState) const
{
return _repMatchLenEncoder.GetPrice(len - kMatchMinLen, posState) +
GetPureRepPrice(repIndex, state, posState);
}
/*
UInt32 GetPosLen2Price(UInt32 pos, UInt32 posState) const
{
if (pos >= kNumFullDistances)
return kIfinityPrice;
return _distancesPrices[0][pos] + _lenEncoder.GetPrice(0, posState);
}
UInt32 GetPosLen3Price(UInt32 pos, UInt32 len, UInt32 posState) const
{
UInt32 price;
UInt32 lenToPosState = GetLenToPosState(len);
if (pos < kNumFullDistances)
price = _distancesPrices[lenToPosState][pos];
else
price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] +
_alignPrices[pos & kAlignMask];
return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
}
*/
UInt32 GetPosLenPrice(UInt32 pos, UInt32 len, UInt32 posState) const
{
UInt32 price;
UInt32 lenToPosState = GetLenToPosState(len);
if (pos < kNumFullDistances)
price = _distancesPrices[lenToPosState][pos];
else
price = _posSlotPrices[lenToPosState][GetPosSlot2(pos)] +
_alignPrices[pos & kAlignMask];
return price + _lenEncoder.GetPrice(len - kMatchMinLen, posState);
}
UInt32 Backward(UInt32 &backRes, UInt32 cur);
HRESULT GetOptimum(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
HRESULT GetOptimumFast(UInt32 position, UInt32 &backRes, UInt32 &lenRes);
void FillDistancesPrices();
void FillAlignPrices();
void ReleaseMFStream()
{
if (_matchFinder && _needReleaseMFStream)
{
_matchFinder->ReleaseStream();
_needReleaseMFStream = false;
}
}
void ReleaseStreams()
{
ReleaseMFStream();
ReleaseOutStream();
}
HRESULT Flush(UInt32 nowPos);
class CCoderReleaser
{
CEncoder *_coder;
public:
CCoderReleaser(CEncoder *coder): _coder(coder) {}
~CCoderReleaser()
{
_coder->ReleaseStreams();
}
};
friend class CCoderReleaser;
void WriteEndMarker(UInt32 posState);
public:
CEncoder();
void SetWriteEndMarkerMode(bool writeEndMarker)
{ _writeEndMark= writeEndMarker; }
HRESULT Create();
MY_UNKNOWN_IMP3(
ICompressSetOutStream,
ICompressSetCoderProperties,
ICompressWriteCoderProperties
)
HRESULT Init();
// ICompressCoder interface
HRESULT SetStreams(ISequentialInStream *inStream,
ISequentialOutStream *outStream,
const UInt64 *inSize, const UInt64 *outSize);
HRESULT CodeOneBlock(UInt64 *inSize, UInt64 *outSize, Int32 *finished);
HRESULT CodeReal(ISequentialInStream *inStream,
ISequentialOutStream *outStream,
const UInt64 *inSize, const UInt64 *outSize,
ICompressProgressInfo *progress);
// ICompressCoder interface
STDMETHOD(Code)(ISequentialInStream *inStream,
ISequentialOutStream *outStream,
const UInt64 *inSize, const UInt64 *outSize,
ICompressProgressInfo *progress);
// ICompressSetCoderProperties2
STDMETHOD(SetCoderProperties)(const PROPID *propIDs,
const PROPVARIANT *properties, UInt32 numProperties);
// ICompressWriteCoderProperties
STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStream);
STDMETHOD(SetOutStream)(ISequentialOutStream *outStream);
STDMETHOD(ReleaseOutStream)();
virtual ~CEncoder() {}
};
}}
#endif

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// StdAfx.h
#ifndef __STDAFX_H
#define __STDAFX_H
#include "../../../Common/MyWindows.h"
#endif

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// Compress/RangeCoder/RangeCoder.h
#ifndef __COMPRESS_RANGECODER_H
#define __COMPRESS_RANGECODER_H
#include "../../Common/InBuffer.h"
#include "../../Common/OutBuffer.h"
namespace NCompress {
namespace NRangeCoder {
const int kNumTopBits = 24;
const UInt32 kTopValue = (1 << kNumTopBits);
class CEncoder
{
UInt32 _cacheSize;
Byte _cache;
public:
UInt64 Low;
UInt32 Range;
COutBuffer Stream;
bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
void SetStream(ISequentialOutStream *stream) { Stream.SetStream(stream); }
void Init()
{
Stream.Init();
Low = 0;
Range = 0xFFFFFFFF;
_cacheSize = 1;
_cache = 0;
}
void FlushData()
{
// Low += 1;
for(int i = 0; i < 5; i++)
ShiftLow();
}
HRESULT FlushStream() { return Stream.Flush(); }
void ReleaseStream() { Stream.ReleaseStream(); }
void Encode(UInt32 start, UInt32 size, UInt32 total)
{
Low += start * (Range /= total);
Range *= size;
while (Range < kTopValue)
{
Range <<= 8;
ShiftLow();
}
}
void ShiftLow()
{
if ((UInt32)Low < (UInt32)0xFF000000 || (int)(Low >> 32) != 0)
{
Byte temp = _cache;
do
{
Stream.WriteByte((Byte)(temp + (Byte)(Low >> 32)));
temp = 0xFF;
}
while(--_cacheSize != 0);
_cache = (Byte)((UInt32)Low >> 24);
}
_cacheSize++;
Low = (UInt32)Low << 8;
}
void EncodeDirectBits(UInt32 value, int numTotalBits)
{
for (int i = numTotalBits - 1; i >= 0; i--)
{
Range >>= 1;
if (((value >> i) & 1) == 1)
Low += Range;
if (Range < kTopValue)
{
Range <<= 8;
ShiftLow();
}
}
}
void EncodeBit(UInt32 size0, UInt32 numTotalBits, UInt32 symbol)
{
UInt32 newBound = (Range >> numTotalBits) * size0;
if (symbol == 0)
Range = newBound;
else
{
Low += newBound;
Range -= newBound;
}
while (Range < kTopValue)
{
Range <<= 8;
ShiftLow();
}
}
UInt64 GetProcessedSize() { return Stream.GetProcessedSize() + _cacheSize + 4; }
};
class CDecoder
{
public:
CInBuffer Stream;
UInt32 Range;
UInt32 Code;
bool Create(UInt32 bufferSize) { return Stream.Create(bufferSize); }
void Normalize()
{
while (Range < kTopValue)
{
Code = (Code << 8) | Stream.ReadByte();
Range <<= 8;
}
}
void SetStream(ISequentialInStream *stream) { Stream.SetStream(stream); }
void Init()
{
Stream.Init();
Code = 0;
Range = 0xFFFFFFFF;
for(int i = 0; i < 5; i++)
Code = (Code << 8) | Stream.ReadByte();
}
void ReleaseStream() { Stream.ReleaseStream(); }
UInt32 GetThreshold(UInt32 total)
{
return (Code) / ( Range /= total);
}
void Decode(UInt32 start, UInt32 size)
{
Code -= start * Range;
Range *= size;
Normalize();
}
UInt32 DecodeDirectBits(int numTotalBits)
{
UInt32 range = Range;
UInt32 code = Code;
UInt32 result = 0;
for (int i = numTotalBits; i != 0; i--)
{
range >>= 1;
/*
result <<= 1;
if (code >= range)
{
code -= range;
result |= 1;
}
*/
UInt32 t = (code - range) >> 31;
code -= range & (t - 1);
result = (result << 1) | (1 - t);
if (range < kTopValue)
{
code = (code << 8) | Stream.ReadByte();
range <<= 8;
}
}
Range = range;
Code = code;
return result;
}
UInt32 DecodeBit(UInt32 size0, UInt32 numTotalBits)
{
UInt32 newBound = (Range >> numTotalBits) * size0;
UInt32 symbol;
if (Code < newBound)
{
symbol = 0;
Range = newBound;
}
else
{
symbol = 1;
Code -= newBound;
Range -= newBound;
}
Normalize();
return symbol;
}
UInt64 GetProcessedSize() {return Stream.GetProcessedSize(); }
};
}}
#endif

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// Compress/RangeCoder/RangeCoderBit.cpp
#include "StdAfx.h"
#include "RangeCoderBit.h"
namespace NCompress {
namespace NRangeCoder {
UInt32 CPriceTables::ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
static CPriceTables g_PriceTables;
CPriceTables::CPriceTables() { Init(); }
void CPriceTables::Init()
{
const int kNumBits = (kNumBitModelTotalBits - kNumMoveReducingBits);
for(int i = kNumBits - 1; i >= 0; i--)
{
UInt32 start = 1 << (kNumBits - i - 1);
UInt32 end = 1 << (kNumBits - i);
for (UInt32 j = start; j < end; j++)
ProbPrices[j] = (i << kNumBitPriceShiftBits) +
(((end - j) << kNumBitPriceShiftBits) >> (kNumBits - i - 1));
}
/*
// simplest: bad solution
for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
ProbPrices[i] = kBitPrice;
*/
/*
const double kDummyMultMid = (1.0 / kBitPrice) / 2;
const double kDummyMultMid = 0;
// float solution
double ln2 = log(double(2));
double lnAll = log(double(kBitModelTotal >> kNumMoveReducingBits));
for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
ProbPrices[i] = UInt32((fabs(lnAll - log(double(i))) / ln2 + kDummyMultMid) * kBitPrice);
*/
/*
// experimental, slow, solution:
for(UInt32 i = 1; i < (kBitModelTotal >> kNumMoveReducingBits) - 1; i++)
{
const int kCyclesBits = 5;
const UInt32 kCycles = (1 << kCyclesBits);
UInt32 range = UInt32(-1);
UInt32 bitCount = 0;
for (UInt32 j = 0; j < kCycles; j++)
{
range >>= (kNumBitModelTotalBits - kNumMoveReducingBits);
range *= i;
while(range < (1 << 31))
{
range <<= 1;
bitCount++;
}
}
bitCount <<= kNumBitPriceShiftBits;
range -= (1 << 31);
for (int k = kNumBitPriceShiftBits - 1; k >= 0; k--)
{
range <<= 1;
if (range > (1 << 31))
{
bitCount += (1 << k);
range -= (1 << 31);
}
}
ProbPrices[i] = (bitCount
// + (1 << (kCyclesBits - 1))
) >> kCyclesBits;
}
*/
}
}}

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// Compress/RangeCoder/RangeCoderBit.h
#ifndef __COMPRESS_RANGECODER_BIT_H
#define __COMPRESS_RANGECODER_BIT_H
#include "RangeCoder.h"
namespace NCompress {
namespace NRangeCoder {
const int kNumBitModelTotalBits = 11;
const UInt32 kBitModelTotal = (1 << kNumBitModelTotalBits);
const int kNumMoveReducingBits = 2;
const int kNumBitPriceShiftBits = 6;
const UInt32 kBitPrice = 1 << kNumBitPriceShiftBits;
class CPriceTables
{
public:
static UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];
static void Init();
CPriceTables();
};
template <int numMoveBits>
class CBitModel
{
public:
UInt32 Prob;
void UpdateModel(UInt32 symbol)
{
/*
Prob -= (Prob + ((symbol - 1) & ((1 << numMoveBits) - 1))) >> numMoveBits;
Prob += (1 - symbol) << (kNumBitModelTotalBits - numMoveBits);
*/
if (symbol == 0)
Prob += (kBitModelTotal - Prob) >> numMoveBits;
else
Prob -= (Prob) >> numMoveBits;
}
public:
void Init() { Prob = kBitModelTotal / 2; }
};
template <int numMoveBits>
class CBitEncoder: public CBitModel<numMoveBits>
{
public:
void Encode(CEncoder *encoder, UInt32 symbol)
{
/*
encoder->EncodeBit(this->Prob, kNumBitModelTotalBits, symbol);
this->UpdateModel(symbol);
*/
UInt32 newBound = (encoder->Range >> kNumBitModelTotalBits) * this->Prob;
if (symbol == 0)
{
encoder->Range = newBound;
this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
}
else
{
encoder->Low += newBound;
encoder->Range -= newBound;
this->Prob -= (this->Prob) >> numMoveBits;
}
if (encoder->Range < kTopValue)
{
encoder->Range <<= 8;
encoder->ShiftLow();
}
}
UInt32 GetPrice(UInt32 symbol) const
{
return CPriceTables::ProbPrices[
(((this->Prob - symbol) ^ ((-(int)symbol))) & (kBitModelTotal - 1)) >> kNumMoveReducingBits];
}
UInt32 GetPrice0() const { return CPriceTables::ProbPrices[this->Prob >> kNumMoveReducingBits]; }
UInt32 GetPrice1() const { return CPriceTables::ProbPrices[(kBitModelTotal - this->Prob) >> kNumMoveReducingBits]; }
};
template <int numMoveBits>
class CBitDecoder: public CBitModel<numMoveBits>
{
public:
UInt32 Decode(CDecoder *decoder)
{
UInt32 newBound = (decoder->Range >> kNumBitModelTotalBits) * this->Prob;
if (decoder->Code < newBound)
{
decoder->Range = newBound;
this->Prob += (kBitModelTotal - this->Prob) >> numMoveBits;
if (decoder->Range < kTopValue)
{
decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
decoder->Range <<= 8;
}
return 0;
}
else
{
decoder->Range -= newBound;
decoder->Code -= newBound;
this->Prob -= (this->Prob) >> numMoveBits;
if (decoder->Range < kTopValue)
{
decoder->Code = (decoder->Code << 8) | decoder->Stream.ReadByte();
decoder->Range <<= 8;
}
return 1;
}
}
};
}}
#endif

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// Compress/RangeCoder/RangeCoderBitTree.h
#ifndef __COMPRESS_RANGECODER_BIT_TREE_H
#define __COMPRESS_RANGECODER_BIT_TREE_H
#include "RangeCoderBit.h"
#include "RangeCoderOpt.h"
namespace NCompress {
namespace NRangeCoder {
template <int numMoveBits, int NumBitLevels>
class CBitTreeEncoder
{
CBitEncoder<numMoveBits> Models[1 << NumBitLevels];
public:
void Init()
{
for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
Models[i].Init();
}
void Encode(CEncoder *rangeEncoder, UInt32 symbol)
{
UInt32 modelIndex = 1;
for (int bitIndex = NumBitLevels; bitIndex != 0 ;)
{
bitIndex--;
UInt32 bit = (symbol >> bitIndex) & 1;
Models[modelIndex].Encode(rangeEncoder, bit);
modelIndex = (modelIndex << 1) | bit;
}
};
void ReverseEncode(CEncoder *rangeEncoder, UInt32 symbol)
{
UInt32 modelIndex = 1;
for (int i = 0; i < NumBitLevels; i++)
{
UInt32 bit = symbol & 1;
Models[modelIndex].Encode(rangeEncoder, bit);
modelIndex = (modelIndex << 1) | bit;
symbol >>= 1;
}
}
UInt32 GetPrice(UInt32 symbol) const
{
symbol |= (1 << NumBitLevels);
UInt32 price = 0;
while (symbol != 1)
{
price += Models[symbol >> 1].GetPrice(symbol & 1);
symbol >>= 1;
}
return price;
}
UInt32 ReverseGetPrice(UInt32 symbol) const
{
UInt32 price = 0;
UInt32 modelIndex = 1;
for (int i = NumBitLevels; i != 0; i--)
{
UInt32 bit = symbol & 1;
symbol >>= 1;
price += Models[modelIndex].GetPrice(bit);
modelIndex = (modelIndex << 1) | bit;
}
return price;
}
};
template <int numMoveBits, int NumBitLevels>
class CBitTreeDecoder
{
CBitDecoder<numMoveBits> Models[1 << NumBitLevels];
public:
void Init()
{
for(UInt32 i = 1; i < (1 << NumBitLevels); i++)
Models[i].Init();
}
UInt32 Decode(CDecoder *rangeDecoder)
{
UInt32 modelIndex = 1;
RC_INIT_VAR
for(int bitIndex = NumBitLevels; bitIndex != 0; bitIndex--)
{
// modelIndex = (modelIndex << 1) + Models[modelIndex].Decode(rangeDecoder);
RC_GETBIT(numMoveBits, Models[modelIndex].Prob, modelIndex)
}
RC_FLUSH_VAR
return modelIndex - (1 << NumBitLevels);
};
UInt32 ReverseDecode(CDecoder *rangeDecoder)
{
UInt32 modelIndex = 1;
UInt32 symbol = 0;
RC_INIT_VAR
for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
{
// UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
// modelIndex <<= 1;
// modelIndex += bit;
// symbol |= (bit << bitIndex);
RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
}
RC_FLUSH_VAR
return symbol;
}
};
template <int numMoveBits>
void ReverseBitTreeEncode(CBitEncoder<numMoveBits> *Models,
CEncoder *rangeEncoder, int NumBitLevels, UInt32 symbol)
{
UInt32 modelIndex = 1;
for (int i = 0; i < NumBitLevels; i++)
{
UInt32 bit = symbol & 1;
Models[modelIndex].Encode(rangeEncoder, bit);
modelIndex = (modelIndex << 1) | bit;
symbol >>= 1;
}
}
template <int numMoveBits>
UInt32 ReverseBitTreeGetPrice(CBitEncoder<numMoveBits> *Models,
UInt32 NumBitLevels, UInt32 symbol)
{
UInt32 price = 0;
UInt32 modelIndex = 1;
for (int i = NumBitLevels; i != 0; i--)
{
UInt32 bit = symbol & 1;
symbol >>= 1;
price += Models[modelIndex].GetPrice(bit);
modelIndex = (modelIndex << 1) | bit;
}
return price;
}
template <int numMoveBits>
UInt32 ReverseBitTreeDecode(CBitDecoder<numMoveBits> *Models,
CDecoder *rangeDecoder, int NumBitLevels)
{
UInt32 modelIndex = 1;
UInt32 symbol = 0;
RC_INIT_VAR
for(int bitIndex = 0; bitIndex < NumBitLevels; bitIndex++)
{
// UInt32 bit = Models[modelIndex].Decode(rangeDecoder);
// modelIndex <<= 1;
// modelIndex += bit;
// symbol |= (bit << bitIndex);
RC_GETBIT2(numMoveBits, Models[modelIndex].Prob, modelIndex, ; , symbol |= (1 << bitIndex))
}
RC_FLUSH_VAR
return symbol;
}
}}
#endif

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// Compress/RangeCoder/RangeCoderOpt.h
#ifndef __COMPRESS_RANGECODER_OPT_H
#define __COMPRESS_RANGECODER_OPT_H
#define RC_INIT_VAR \
UInt32 range = rangeDecoder->Range; \
UInt32 code = rangeDecoder->Code;
#define RC_FLUSH_VAR \
rangeDecoder->Range = range; \
rangeDecoder->Code = code;
#define RC_NORMALIZE \
if (range < NCompress::NRangeCoder::kTopValue) \
{ code = (code << 8) | rangeDecoder->Stream.ReadByte(); range <<= 8; }
#define RC_GETBIT2(numMoveBits, prob, mi, A0, A1) \
{ UInt32 bound = (range >> NCompress::NRangeCoder::kNumBitModelTotalBits) * prob; \
if (code < bound) \
{ A0; range = bound; \
prob += (NCompress::NRangeCoder::kBitModelTotal - prob) >> numMoveBits; \
mi <<= 1; } \
else \
{ A1; range -= bound; code -= bound; prob -= (prob) >> numMoveBits; \
mi = (mi + mi) + 1; }} \
RC_NORMALIZE
#define RC_GETBIT(numMoveBits, prob, mi) RC_GETBIT2(numMoveBits, prob, mi, ; , ;)
#endif

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// StdAfx.h
#ifndef __STDAFX_H
#define __STDAFX_H
#endif

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/*
LzmaDecode.c
LZMA Decoder (optimized for Speed version)
LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10)
http://www.7-zip.org/
LZMA SDK is licensed under two licenses:
1) GNU Lesser General Public License (GNU LGPL)
2) Common Public License (CPL)
It means that you can select one of these two licenses and
follow rules of that license.
SPECIAL EXCEPTION:
Igor Pavlov, as the author of this Code, expressly permits you to
statically or dynamically link your Code (or bind by name) to the
interfaces of this file without subjecting your linked Code to the
terms of the CPL or GNU LGPL. Any modifications or additions
to this file, however, are subject to the LGPL or CPL terms.
*/
#include "LzmaDecode.h"
#ifndef Byte
#define Byte unsigned char
#endif
#define kNumTopBits 24
#define kTopValue ((UInt32)1 << kNumTopBits)
#define kNumBitModelTotalBits 11
#define kBitModelTotal (1 << kNumBitModelTotalBits)
#define kNumMoveBits 5
#define RC_READ_BYTE (*Buffer++)
#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
{ int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
#ifdef _LZMA_IN_CB
#define RC_TEST { if (Buffer == BufferLim) \
{ SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \
BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}
#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
#else
#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
#endif
#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
{ UpdateBit0(p); mi <<= 1; A0; } else \
{ UpdateBit1(p); mi = (mi + mi) + 1; A1; }
#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
{ int i = numLevels; res = 1; \
do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
res -= (1 << numLevels); }
#define kNumPosBitsMax 4
#define kNumPosStatesMax (1 << kNumPosBitsMax)
#define kLenNumLowBits 3
#define kLenNumLowSymbols (1 << kLenNumLowBits)
#define kLenNumMidBits 3
#define kLenNumMidSymbols (1 << kLenNumMidBits)
#define kLenNumHighBits 8
#define kLenNumHighSymbols (1 << kLenNumHighBits)
#define LenChoice 0
#define LenChoice2 (LenChoice + 1)
#define LenLow (LenChoice2 + 1)
#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
#define kNumStates 12
#define kNumLitStates 7
#define kStartPosModelIndex 4
#define kEndPosModelIndex 14
#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
#define kNumPosSlotBits 6
#define kNumLenToPosStates 4
#define kNumAlignBits 4
#define kAlignTableSize (1 << kNumAlignBits)
#define kMatchMinLen 2
#define IsMatch 0
#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
#define IsRepG0 (IsRep + kNumStates)
#define IsRepG1 (IsRepG0 + kNumStates)
#define IsRepG2 (IsRepG1 + kNumStates)
#define IsRep0Long (IsRepG2 + kNumStates)
#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
#define LenCoder (Align + kAlignTableSize)
#define RepLenCoder (LenCoder + kNumLenProbs)
#define Literal (RepLenCoder + kNumLenProbs)
#if Literal != LZMA_BASE_SIZE
StopCompilingDueBUG
#endif
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
{
unsigned char prop0;
if (size < LZMA_PROPERTIES_SIZE)
return LZMA_RESULT_DATA_ERROR;
prop0 = propsData[0];
if (prop0 >= (9 * 5 * 5))
return LZMA_RESULT_DATA_ERROR;
{
for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
propsRes->lc = prop0;
/*
unsigned char remainder = (unsigned char)(prop0 / 9);
propsRes->lc = prop0 % 9;
propsRes->pb = remainder / 5;
propsRes->lp = remainder % 5;
*/
}
#ifdef _LZMA_OUT_READ
{
int i;
propsRes->DictionarySize = 0;
for (i = 0; i < 4; i++)
propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
if (propsRes->DictionarySize == 0)
propsRes->DictionarySize = 1;
}
#endif
return LZMA_RESULT_OK;
}
#define kLzmaStreamWasFinishedId (-1)
int LzmaDecode(CLzmaDecoderState *vs,
#ifdef _LZMA_IN_CB
ILzmaInCallback *InCallback,
#else
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
#endif
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
{
CProb *p = vs->Probs;
SizeT nowPos = 0;
Byte previousByte = 0;
UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
int lc = vs->Properties.lc;
#ifdef _LZMA_OUT_READ
UInt32 Range = vs->Range;
UInt32 Code = vs->Code;
#ifdef _LZMA_IN_CB
const Byte *Buffer = vs->Buffer;
const Byte *BufferLim = vs->BufferLim;
#else
const Byte *Buffer = inStream;
const Byte *BufferLim = inStream + inSize;
#endif
int state = vs->State;
UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
int len = vs->RemainLen;
UInt32 globalPos = vs->GlobalPos;
UInt32 distanceLimit = vs->DistanceLimit;
Byte *dictionary = vs->Dictionary;
UInt32 dictionarySize = vs->Properties.DictionarySize;
UInt32 dictionaryPos = vs->DictionaryPos;
Byte tempDictionary[4];
#ifndef _LZMA_IN_CB
*inSizeProcessed = 0;
#endif
*outSizeProcessed = 0;
if (len == kLzmaStreamWasFinishedId)
return LZMA_RESULT_OK;
if (dictionarySize == 0)
{
dictionary = tempDictionary;
dictionarySize = 1;
tempDictionary[0] = vs->TempDictionary[0];
}
if (len == kLzmaNeedInitId)
{
{
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
UInt32 i;
for (i = 0; i < numProbs; i++)
p[i] = kBitModelTotal >> 1;
rep0 = rep1 = rep2 = rep3 = 1;
state = 0;
globalPos = 0;
distanceLimit = 0;
dictionaryPos = 0;
dictionary[dictionarySize - 1] = 0;
#ifdef _LZMA_IN_CB
RC_INIT;
#else
RC_INIT(inStream, inSize);
#endif
}
len = 0;
}
while(len != 0 && nowPos < outSize)
{
UInt32 pos = dictionaryPos - rep0;
if (pos >= dictionarySize)
pos += dictionarySize;
outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
if (++dictionaryPos == dictionarySize)
dictionaryPos = 0;
len--;
}
if (dictionaryPos == 0)
previousByte = dictionary[dictionarySize - 1];
else
previousByte = dictionary[dictionaryPos - 1];
#else /* if !_LZMA_OUT_READ */
int state = 0;
UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
int len = 0;
const Byte *Buffer;
const Byte *BufferLim;
UInt32 Range;
UInt32 Code;
#ifndef _LZMA_IN_CB
*inSizeProcessed = 0;
#endif
*outSizeProcessed = 0;
{
UInt32 i;
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
for (i = 0; i < numProbs; i++)
p[i] = kBitModelTotal >> 1;
}
#ifdef _LZMA_IN_CB
RC_INIT;
#else
RC_INIT(inStream, inSize);
#endif
#endif /* _LZMA_OUT_READ */
while(nowPos < outSize)
{
CProb *prob;
UInt32 bound;
int posState = (int)(
(nowPos
#ifdef _LZMA_OUT_READ
+ globalPos
#endif
)
& posStateMask);
prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
IfBit0(prob)
{
int symbol = 1;
UpdateBit0(prob)
prob = p + Literal + (LZMA_LIT_SIZE *
(((
(nowPos
#ifdef _LZMA_OUT_READ
+ globalPos
#endif
)
& literalPosMask) << lc) + (previousByte >> (8 - lc))));
if (state >= kNumLitStates)
{
int matchByte;
#ifdef _LZMA_OUT_READ
UInt32 pos = dictionaryPos - rep0;
if (pos >= dictionarySize)
pos += dictionarySize;
matchByte = dictionary[pos];
#else
matchByte = outStream[nowPos - rep0];
#endif
do
{
int bit;
CProb *probLit;
matchByte <<= 1;
bit = (matchByte & 0x100);
probLit = prob + 0x100 + bit + symbol;
RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
}
while (symbol < 0x100);
}
while (symbol < 0x100)
{
CProb *probLit = prob + symbol;
RC_GET_BIT(probLit, symbol)
}
previousByte = (Byte)symbol;
outStream[nowPos++] = previousByte;
#ifdef _LZMA_OUT_READ
if (distanceLimit < dictionarySize)
distanceLimit++;
dictionary[dictionaryPos] = previousByte;
if (++dictionaryPos == dictionarySize)
dictionaryPos = 0;
#endif
if (state < 4) state = 0;
else if (state < 10) state -= 3;
else state -= 6;
}
else
{
UpdateBit1(prob);
prob = p + IsRep + state;
IfBit0(prob)
{
UpdateBit0(prob);
rep3 = rep2;
rep2 = rep1;
rep1 = rep0;
state = state < kNumLitStates ? 0 : 3;
prob = p + LenCoder;
}
else
{
UpdateBit1(prob);
prob = p + IsRepG0 + state;
IfBit0(prob)
{
UpdateBit0(prob);
prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
IfBit0(prob)
{
#ifdef _LZMA_OUT_READ
UInt32 pos;
#endif
UpdateBit0(prob);
#ifdef _LZMA_OUT_READ
if (distanceLimit == 0)
#else
if (nowPos == 0)
#endif
return LZMA_RESULT_DATA_ERROR;
state = state < kNumLitStates ? 9 : 11;
#ifdef _LZMA_OUT_READ
pos = dictionaryPos - rep0;
if (pos >= dictionarySize)
pos += dictionarySize;
previousByte = dictionary[pos];
dictionary[dictionaryPos] = previousByte;
if (++dictionaryPos == dictionarySize)
dictionaryPos = 0;
#else
previousByte = outStream[nowPos - rep0];
#endif
outStream[nowPos++] = previousByte;
#ifdef _LZMA_OUT_READ
if (distanceLimit < dictionarySize)
distanceLimit++;
#endif
continue;
}
else
{
UpdateBit1(prob);
}
}
else
{
UInt32 distance;
UpdateBit1(prob);
prob = p + IsRepG1 + state;
IfBit0(prob)
{
UpdateBit0(prob);
distance = rep1;
}
else
{
UpdateBit1(prob);
prob = p + IsRepG2 + state;
IfBit0(prob)
{
UpdateBit0(prob);
distance = rep2;
}
else
{
UpdateBit1(prob);
distance = rep3;
rep3 = rep2;
}
rep2 = rep1;
}
rep1 = rep0;
rep0 = distance;
}
state = state < kNumLitStates ? 8 : 11;
prob = p + RepLenCoder;
}
{
int numBits, offset;
CProb *probLen = prob + LenChoice;
IfBit0(probLen)
{
UpdateBit0(probLen);
probLen = prob + LenLow + (posState << kLenNumLowBits);
offset = 0;
numBits = kLenNumLowBits;
}
else
{
UpdateBit1(probLen);
probLen = prob + LenChoice2;
IfBit0(probLen)
{
UpdateBit0(probLen);
probLen = prob + LenMid + (posState << kLenNumMidBits);
offset = kLenNumLowSymbols;
numBits = kLenNumMidBits;
}
else
{
UpdateBit1(probLen);
probLen = prob + LenHigh;
offset = kLenNumLowSymbols + kLenNumMidSymbols;
numBits = kLenNumHighBits;
}
}
RangeDecoderBitTreeDecode(probLen, numBits, len);
len += offset;
}
if (state < 4)
{
int posSlot;
state += kNumLitStates;
prob = p + PosSlot +
((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
kNumPosSlotBits);
RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
if (posSlot >= kStartPosModelIndex)
{
int numDirectBits = ((posSlot >> 1) - 1);
rep0 = (2 | ((UInt32)posSlot & 1));
if (posSlot < kEndPosModelIndex)
{
rep0 <<= numDirectBits;
prob = p + SpecPos + rep0 - posSlot - 1;
}
else
{
numDirectBits -= kNumAlignBits;
do
{
RC_NORMALIZE
Range >>= 1;
rep0 <<= 1;
if (Code >= Range)
{
Code -= Range;
rep0 |= 1;
}
}
while (--numDirectBits != 0);
prob = p + Align;
rep0 <<= kNumAlignBits;
numDirectBits = kNumAlignBits;
}
{
int i = 1;
int mi = 1;
do
{
CProb *prob3 = prob + mi;
RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
i <<= 1;
}
while(--numDirectBits != 0);
}
}
else
rep0 = posSlot;
if (++rep0 == (UInt32)(0))
{
/* it's for stream version */
len = kLzmaStreamWasFinishedId;
break;
}
}
len += kMatchMinLen;
#ifdef _LZMA_OUT_READ
if (rep0 > distanceLimit)
#else
if (rep0 > nowPos)
#endif
return LZMA_RESULT_DATA_ERROR;
#ifdef _LZMA_OUT_READ
if (dictionarySize - distanceLimit > (UInt32)len)
distanceLimit += len;
else
distanceLimit = dictionarySize;
#endif
do
{
#ifdef _LZMA_OUT_READ
UInt32 pos = dictionaryPos - rep0;
if (pos >= dictionarySize)
pos += dictionarySize;
previousByte = dictionary[pos];
dictionary[dictionaryPos] = previousByte;
if (++dictionaryPos == dictionarySize)
dictionaryPos = 0;
#else
previousByte = outStream[nowPos - rep0];
#endif
len--;
outStream[nowPos++] = previousByte;
}
while(len != 0 && nowPos < outSize);
}
}
RC_NORMALIZE;
#ifdef _LZMA_OUT_READ
vs->Range = Range;
vs->Code = Code;
vs->DictionaryPos = dictionaryPos;
vs->GlobalPos = globalPos + (UInt32)nowPos;
vs->DistanceLimit = distanceLimit;
vs->Reps[0] = rep0;
vs->Reps[1] = rep1;
vs->Reps[2] = rep2;
vs->Reps[3] = rep3;
vs->State = state;
vs->RemainLen = len;
vs->TempDictionary[0] = tempDictionary[0];
#endif
#ifdef _LZMA_IN_CB
vs->Buffer = Buffer;
vs->BufferLim = BufferLim;
#else
*inSizeProcessed = (SizeT)(Buffer - inStream);
#endif
*outSizeProcessed = nowPos;
return LZMA_RESULT_OK;
}

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/*
LzmaDecode.h
LZMA Decoder interface
LZMA SDK 4.21 Copyright (c) 1999-2005 Igor Pavlov (2005-06-08)
http://www.7-zip.org/
LZMA SDK is licensed under two licenses:
1) GNU Lesser General Public License (GNU LGPL)
2) Common Public License (CPL)
It means that you can select one of these two licenses and
follow rules of that license.
SPECIAL EXCEPTION:
Igor Pavlov, as the author of this code, expressly permits you to
statically or dynamically link your code (or bind by name) to the
interfaces of this file without subjecting your linked code to the
terms of the CPL or GNU LGPL. Any modifications or additions
to this file, however, are subject to the LGPL or CPL terms.
*/
#ifndef __LZMADECODE_H
#define __LZMADECODE_H
/* #define _LZMA_IN_CB */
/* Use callback for input data */
/* #define _LZMA_OUT_READ */
/* Use read function for output data */
/* #define _LZMA_PROB32 */
/* It can increase speed on some 32-bit CPUs,
but memory usage will be doubled in that case */
/* #define _LZMA_LOC_OPT */
/* Enable local speed optimizations inside code */
/* #define _LZMA_SYSTEM_SIZE_T */
/* Use system's size_t. You can use it to enable 64-bit sizes supporting*/
#ifndef UInt32
#ifdef _LZMA_UINT32_IS_ULONG
#define UInt32 unsigned long
#else
#define UInt32 unsigned int
#endif
#endif
#ifndef SizeT
#ifdef _LZMA_SYSTEM_SIZE_T
#include <stddef.h>
#define SizeT size_t
#else
#define SizeT UInt32
#endif
#endif
#ifdef _LZMA_PROB32
#define CProb UInt32
#else
#define CProb unsigned short
#endif
#define LZMA_RESULT_OK 0
#define LZMA_RESULT_DATA_ERROR 1
#ifdef _LZMA_IN_CB
typedef struct _ILzmaInCallback
{
int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
} ILzmaInCallback;
#endif
#define LZMA_BASE_SIZE 1846
#define LZMA_LIT_SIZE 768
#define LZMA_PROPERTIES_SIZE 5
typedef struct _CLzmaProperties
{
int lc;
int lp;
int pb;
#ifdef _LZMA_OUT_READ
UInt32 DictionarySize;
#endif
}CLzmaProperties;
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
#define kLzmaNeedInitId (-2)
typedef struct _CLzmaDecoderState
{
CLzmaProperties Properties;
CProb *Probs;
#ifdef _LZMA_IN_CB
const unsigned char *Buffer;
const unsigned char *BufferLim;
#endif
#ifdef _LZMA_OUT_READ
unsigned char *Dictionary;
UInt32 Range;
UInt32 Code;
UInt32 DictionaryPos;
UInt32 GlobalPos;
UInt32 DistanceLimit;
UInt32 Reps[4];
int State;
int RemainLen;
unsigned char TempDictionary[4];
#endif
} CLzmaDecoderState;
#ifdef _LZMA_OUT_READ
#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
#endif
int LzmaDecode(CLzmaDecoderState *vs,
#ifdef _LZMA_IN_CB
ILzmaInCallback *inCallback,
#else
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
#endif
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
#endif

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// ICoder.h
#ifndef __ICODER_H
#define __ICODER_H
#include "IStream.h"
// "23170F69-40C1-278A-0000-000400xx0000"
#define CODER_INTERFACE(i, x) \
DEFINE_GUID(IID_ ## i, \
0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x04, 0x00, x, 0x00, 0x00); \
struct i: public IUnknown
CODER_INTERFACE(ICompressProgressInfo, 0x04)
{
STDMETHOD(SetRatioInfo)(const UInt64 *inSize, const UInt64 *outSize) PURE;
};
CODER_INTERFACE(ICompressCoder, 0x05)
{
STDMETHOD(Code)(ISequentialInStream *inStream,
ISequentialOutStream *outStream,
const UInt64 *inSize,
const UInt64 *outSize,
ICompressProgressInfo *progress) PURE;
};
CODER_INTERFACE(ICompressCoder2, 0x18)
{
STDMETHOD(Code)(ISequentialInStream **inStreams,
const UInt64 **inSizes,
UInt32 numInStreams,
ISequentialOutStream **outStreams,
const UInt64 **outSizes,
UInt32 numOutStreams,
ICompressProgressInfo *progress) PURE;
};
namespace NCoderPropID
{
enum EEnum
{
kDictionarySize = 0x400,
kUsedMemorySize,
kOrder,
kPosStateBits = 0x440,
kLitContextBits,
kLitPosBits,
kNumFastBytes = 0x450,
kMatchFinder,
kMatchFinderCycles,
kNumPasses = 0x460,
kAlgorithm = 0x470,
kMultiThread = 0x480,
kNumThreads,
kEndMarker = 0x490
};
}
CODER_INTERFACE(ICompressSetCoderProperties, 0x20)
{
STDMETHOD(SetCoderProperties)(const PROPID *propIDs,
const PROPVARIANT *properties, UInt32 numProperties) PURE;
};
/*
CODER_INTERFACE(ICompressSetCoderProperties, 0x21)
{
STDMETHOD(SetDecoderProperties)(ISequentialInStream *inStream) PURE;
};
*/
CODER_INTERFACE(ICompressSetDecoderProperties2, 0x22)
{
STDMETHOD(SetDecoderProperties2)(const Byte *data, UInt32 size) PURE;
};
CODER_INTERFACE(ICompressWriteCoderProperties, 0x23)
{
STDMETHOD(WriteCoderProperties)(ISequentialOutStream *outStreams) PURE;
};
CODER_INTERFACE(ICompressGetInStreamProcessedSize, 0x24)
{
STDMETHOD(GetInStreamProcessedSize)(UInt64 *value) PURE;
};
CODER_INTERFACE(ICompressSetCoderMt, 0x25)
{
STDMETHOD(SetNumberOfThreads)(UInt32 numThreads) PURE;
};
CODER_INTERFACE(ICompressGetSubStreamSize, 0x30)
{
STDMETHOD(GetSubStreamSize)(UInt64 subStream, UInt64 *value) PURE;
};
CODER_INTERFACE(ICompressSetInStream, 0x31)
{
STDMETHOD(SetInStream)(ISequentialInStream *inStream) PURE;
STDMETHOD(ReleaseInStream)() PURE;
};
CODER_INTERFACE(ICompressSetOutStream, 0x32)
{
STDMETHOD(SetOutStream)(ISequentialOutStream *outStream) PURE;
STDMETHOD(ReleaseOutStream)() PURE;
};
CODER_INTERFACE(ICompressSetInStreamSize, 0x33)
{
STDMETHOD(SetInStreamSize)(const UInt64 *inSize) PURE;
};
CODER_INTERFACE(ICompressSetOutStreamSize, 0x34)
{
STDMETHOD(SetOutStreamSize)(const UInt64 *outSize) PURE;
};
CODER_INTERFACE(ICompressFilter, 0x40)
{
STDMETHOD(Init)() PURE;
STDMETHOD_(UInt32, Filter)(Byte *data, UInt32 size) PURE;
// Filter return outSize (UInt32)
// if (outSize <= size): Filter have converted outSize bytes
// if (outSize > size): Filter have not converted anything.
// and it needs at least outSize bytes to convert one block
// (it's for crypto block algorithms).
};
CODER_INTERFACE(ICryptoProperties, 0x80)
{
STDMETHOD(SetKey)(const Byte *data, UInt32 size) PURE;
STDMETHOD(SetInitVector)(const Byte *data, UInt32 size) PURE;
};
CODER_INTERFACE(ICryptoSetPassword, 0x90)
{
STDMETHOD(CryptoSetPassword)(const Byte *data, UInt32 size) PURE;
};
CODER_INTERFACE(ICryptoSetCRC, 0xA0)
{
STDMETHOD(CryptoSetCRC)(UInt32 crc) PURE;
};
//////////////////////
// It's for DLL file
namespace NMethodPropID
{
enum EEnum
{
kID,
kName,
kDecoder,
kEncoder,
kInStreams,
kOutStreams,
kDescription
};
}
#endif

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// IStream.h
#ifndef __ISTREAM_H
#define __ISTREAM_H
#include "../Common/MyUnknown.h"
#include "../Common/Types.h"
// "23170F69-40C1-278A-0000-000300xx0000"
#define STREAM_INTERFACE_SUB(i, b, x) \
DEFINE_GUID(IID_ ## i, \
0x23170F69, 0x40C1, 0x278A, 0x00, 0x00, 0x00, 0x03, 0x00, x, 0x00, 0x00); \
struct i: public b
#define STREAM_INTERFACE(i, x) STREAM_INTERFACE_SUB(i, IUnknown, x)
STREAM_INTERFACE(ISequentialInStream, 0x01)
{
STDMETHOD(Read)(void *data, UInt32 size, UInt32 *processedSize) PURE;
/*
Out: if size != 0, return_value = S_OK and (*processedSize == 0),
then there are no more bytes in stream.
if (size > 0) && there are bytes in stream,
this function must read at least 1 byte.
This function is allowed to read less than number of remaining bytes in stream.
You must call Read function in loop, if you need exact amount of data
*/
};
STREAM_INTERFACE(ISequentialOutStream, 0x02)
{
STDMETHOD(Write)(const void *data, UInt32 size, UInt32 *processedSize) PURE;
/*
if (size > 0) this function must write at least 1 byte.
This function is allowed to write less than "size".
You must call Write function in loop, if you need to write exact amount of data
*/
};
STREAM_INTERFACE_SUB(IInStream, ISequentialInStream, 0x03)
{
STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
};
STREAM_INTERFACE_SUB(IOutStream, ISequentialOutStream, 0x04)
{
STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition) PURE;
STDMETHOD(SetSize)(Int64 newSize) PURE;
};
STREAM_INTERFACE(IStreamGetSize, 0x06)
{
STDMETHOD(GetSize)(UInt64 *size) PURE;
};
STREAM_INTERFACE(IOutStreamFlush, 0x07)
{
STDMETHOD(Flush)() PURE;
};
#endif

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// Common/Alloc.cpp
#include "StdAfx.h"
#ifdef _WIN32
#include "MyWindows.h"
#else
#include <stdlib.h>
#endif
#include "Alloc.h"
/* #define _SZ_ALLOC_DEBUG */
/* use _SZ_ALLOC_DEBUG to debug alloc/free operations */
#ifdef _SZ_ALLOC_DEBUG
#include <stdio.h>
int g_allocCount = 0;
int g_allocCountMid = 0;
int g_allocCountBig = 0;
#endif
void *MyAlloc(size_t size) throw()
{
if (size == 0)
return 0;
#ifdef _SZ_ALLOC_DEBUG
fprintf(stderr, "\nAlloc %10d bytes; count = %10d", size, g_allocCount++);
#endif
return ::malloc(size);
}
void MyFree(void *address) throw()
{
#ifdef _SZ_ALLOC_DEBUG
if (address != 0)
fprintf(stderr, "\nFree; count = %10d", --g_allocCount);
#endif
::free(address);
}
#ifdef _WIN32
void *MidAlloc(size_t size) throw()
{
if (size == 0)
return 0;
#ifdef _SZ_ALLOC_DEBUG
fprintf(stderr, "\nAlloc_Mid %10d bytes; count = %10d", size, g_allocCountMid++);
#endif
return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
}
void MidFree(void *address) throw()
{
#ifdef _SZ_ALLOC_DEBUG
if (address != 0)
fprintf(stderr, "\nFree_Mid; count = %10d", --g_allocCountMid);
#endif
if (address == 0)
return;
::VirtualFree(address, 0, MEM_RELEASE);
}
static SIZE_T g_LargePageSize =
#ifdef _WIN64
(1 << 21);
#else
(1 << 22);
#endif
typedef SIZE_T (WINAPI *GetLargePageMinimumP)();
bool SetLargePageSize()
{
GetLargePageMinimumP largePageMinimum = (GetLargePageMinimumP)
::GetProcAddress(::GetModuleHandle(TEXT("kernel32.dll")), "GetLargePageMinimum");
if (largePageMinimum == 0)
return false;
SIZE_T size = largePageMinimum();
if (size == 0 || (size & (size - 1)) != 0)
return false;
g_LargePageSize = size;
return true;
}
void *BigAlloc(size_t size) throw()
{
if (size == 0)
return 0;
#ifdef _SZ_ALLOC_DEBUG
fprintf(stderr, "\nAlloc_Big %10d bytes; count = %10d", size, g_allocCountBig++);
#endif
if (size >= (1 << 18))
{
void *res = ::VirtualAlloc(0, (size + g_LargePageSize - 1) & (~(g_LargePageSize - 1)),
MEM_COMMIT | MEM_LARGE_PAGES, PAGE_READWRITE);
if (res != 0)
return res;
}
return ::VirtualAlloc(0, size, MEM_COMMIT, PAGE_READWRITE);
}
void BigFree(void *address) throw()
{
#ifdef _SZ_ALLOC_DEBUG
if (address != 0)
fprintf(stderr, "\nFree_Big; count = %10d", --g_allocCountBig);
#endif
if (address == 0)
return;
::VirtualFree(address, 0, MEM_RELEASE);
}
#endif

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// Common/Alloc.h
#ifndef __COMMON_ALLOC_H
#define __COMMON_ALLOC_H
#include <stddef.h>
void *MyAlloc(size_t size) throw();
void MyFree(void *address) throw();
#ifdef _WIN32
bool SetLargePageSize();
void *MidAlloc(size_t size) throw();
void MidFree(void *address) throw();
void *BigAlloc(size_t size) throw();
void BigFree(void *address) throw();
#else
#define MidAlloc(size) MyAlloc(size)
#define MidFree(address) MyFree(address)
#define BigAlloc(size) MyAlloc(size)
#define BigFree(address) MyFree(address)
#endif
#endif

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// Common/CRC.cpp
#include "StdAfx.h"
#include "CRC.h"
static const UInt32 kCRCPoly = 0xEDB88320;
UInt32 CCRC::Table[256];
void CCRC::InitTable()
{
for (UInt32 i = 0; i < 256; i++)
{
UInt32 r = i;
for (int j = 0; j < 8; j++)
if (r & 1)
r = (r >> 1) ^ kCRCPoly;
else
r >>= 1;
CCRC::Table[i] = r;
}
}
class CCRCTableInit
{
public:
CCRCTableInit() { CCRC::InitTable(); }
} g_CRCTableInit;
void CCRC::UpdateByte(Byte b)
{
_value = Table[((Byte)(_value)) ^ b] ^ (_value >> 8);
}
void CCRC::UpdateUInt16(UInt16 v)
{
UpdateByte(Byte(v));
UpdateByte(Byte(v >> 8));
}
void CCRC::UpdateUInt32(UInt32 v)
{
for (int i = 0; i < 4; i++)
UpdateByte((Byte)(v >> (8 * i)));
}
void CCRC::UpdateUInt64(UInt64 v)
{
for (int i = 0; i < 8; i++)
UpdateByte((Byte)(v >> (8 * i)));
}
void CCRC::Update(const void *data, size_t size)
{
UInt32 v = _value;
const Byte *p = (const Byte *)data;
for (; size > 0 ; size--, p++)
v = Table[((Byte)(v)) ^ *p] ^ (v >> 8);
_value = v;
}

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// Common/CRC.h
#ifndef __COMMON_CRC_H
#define __COMMON_CRC_H
#include <stddef.h>
#include "Types.h"
class CCRC
{
UInt32 _value;
public:
static UInt32 Table[256];
static void InitTable();
CCRC(): _value(0xFFFFFFFF){};
void Init() { _value = 0xFFFFFFFF; }
void UpdateByte(Byte v);
void UpdateUInt16(UInt16 v);
void UpdateUInt32(UInt32 v);
void UpdateUInt64(UInt64 v);
void Update(const void *data, size_t size);
UInt32 GetDigest() const { return _value ^ 0xFFFFFFFF; }
static UInt32 CalculateDigest(const void *data, size_t size)
{
CCRC crc;
crc.Update(data, size);
return crc.GetDigest();
}
static bool VerifyDigest(UInt32 digest, const void *data, size_t size)
{
return (CalculateDigest(data, size) == digest);
}
};
#endif

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// Common/Defs.h
#ifndef __COMMON_DEFS_H
#define __COMMON_DEFS_H
template <class T> inline T MyMin(T a, T b)
{ return a < b ? a : b; }
template <class T> inline T MyMax(T a, T b)
{ return a > b ? a : b; }
template <class T> inline int MyCompare(T a, T b)
{ return a < b ? -1 : (a == b ? 0 : 1); }
inline int BoolToInt(bool value)
{ return (value ? 1: 0); }
inline bool IntToBool(int value)
{ return (value != 0); }
#endif

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// MyCom.h
#ifndef __MYCOM_H
#define __MYCOM_H
#include "MyWindows.h"
#define RINOK(x) { HRESULT __result_ = (x); if(__result_ != S_OK) return __result_; }
template <class T>
class CMyComPtr
{
T* _p;
public:
// typedef T _PtrClass;
CMyComPtr() { _p = NULL;}
CMyComPtr(T* p) {if ((_p = p) != NULL) p->AddRef(); }
CMyComPtr(const CMyComPtr<T>& lp)
{
if ((_p = lp._p) != NULL)
_p->AddRef();
}
~CMyComPtr() { if (_p) _p->Release(); }
void Release() { if (_p) { _p->Release(); _p = NULL; } }
operator T*() const { return (T*)_p; }
// T& operator*() const { return *_p; }
T** operator&() { return &_p; }
T* operator->() const { return _p; }
T* operator=(T* p)
{
if (p != 0)
p->AddRef();
if (_p)
_p->Release();
_p = p;
return p;
}
T* operator=(const CMyComPtr<T>& lp) { return (*this = lp._p); }
bool operator!() const { return (_p == NULL); }
// bool operator==(T* pT) const { return _p == pT; }
// Compare two objects for equivalence
void Attach(T* p2)
{
Release();
_p = p2;
}
T* Detach()
{
T* pt = _p;
_p = NULL;
return pt;
}
#ifdef _WIN32
HRESULT CoCreateInstance(REFCLSID rclsid, REFIID iid, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
{
return ::CoCreateInstance(rclsid, pUnkOuter, dwClsContext, iid, (void**)&_p);
}
#endif
/*
HRESULT CoCreateInstance(LPCOLESTR szProgID, LPUNKNOWN pUnkOuter = NULL, DWORD dwClsContext = CLSCTX_ALL)
{
CLSID clsid;
HRESULT hr = CLSIDFromProgID(szProgID, &clsid);
ATLASSERT(_p == NULL);
if (SUCCEEDED(hr))
hr = ::CoCreateInstance(clsid, pUnkOuter, dwClsContext, __uuidof(T), (void**)&_p);
return hr;
}
*/
template <class Q>
HRESULT QueryInterface(REFGUID iid, Q** pp) const
{
return _p->QueryInterface(iid, (void**)pp);
}
};
//////////////////////////////////////////////////////////
class CMyComBSTR
{
public:
BSTR m_str;
CMyComBSTR() { m_str = NULL; }
CMyComBSTR(LPCOLESTR pSrc) { m_str = ::SysAllocString(pSrc); }
// CMyComBSTR(int nSize) { m_str = ::SysAllocStringLen(NULL, nSize); }
// CMyComBSTR(int nSize, LPCOLESTR sz) { m_str = ::SysAllocStringLen(sz, nSize); }
CMyComBSTR(const CMyComBSTR& src) { m_str = src.MyCopy(); }
/*
CMyComBSTR(REFGUID src)
{
LPOLESTR szGuid;
StringFromCLSID(src, &szGuid);
m_str = ::SysAllocString(szGuid);
CoTaskMemFree(szGuid);
}
*/
~CMyComBSTR() { ::SysFreeString(m_str); }
CMyComBSTR& operator=(const CMyComBSTR& src)
{
if (m_str != src.m_str)
{
if (m_str)
::SysFreeString(m_str);
m_str = src.MyCopy();
}
return *this;
}
CMyComBSTR& operator=(LPCOLESTR pSrc)
{
::SysFreeString(m_str);
m_str = ::SysAllocString(pSrc);
return *this;
}
unsigned int Length() const { return ::SysStringLen(m_str); }
operator BSTR() const { return m_str; }
BSTR* operator&() { return &m_str; }
BSTR MyCopy() const
{
int byteLen = ::SysStringByteLen(m_str);
BSTR res = ::SysAllocStringByteLen(NULL, byteLen);
memmove(res, m_str, byteLen);
return res;
}
void Attach(BSTR src) { m_str = src; }
BSTR Detach()
{
BSTR s = m_str;
m_str = NULL;
return s;
}
void Empty()
{
::SysFreeString(m_str);
m_str = NULL;
}
bool operator!() const { return (m_str == NULL); }
};
//////////////////////////////////////////////////////////
class CMyUnknownImp
{
public:
ULONG __m_RefCount;
CMyUnknownImp(): __m_RefCount(0) {}
};
#define MY_QUERYINTERFACE_BEGIN STDMETHOD(QueryInterface) \
(REFGUID iid, void **outObject) {
#define MY_QUERYINTERFACE_ENTRY(i) if (iid == IID_ ## i) \
{ *outObject = (void *)(i *)this; AddRef(); return S_OK; }
#define MY_QUERYINTERFACE_END return E_NOINTERFACE; }
#define MY_ADDREF_RELEASE \
STDMETHOD_(ULONG, AddRef)() { return ++__m_RefCount; } \
STDMETHOD_(ULONG, Release)() { if (--__m_RefCount != 0) \
return __m_RefCount; delete this; return 0; }
#define MY_UNKNOWN_IMP_SPEC(i) \
MY_QUERYINTERFACE_BEGIN \
i \
MY_QUERYINTERFACE_END \
MY_ADDREF_RELEASE
#define MY_UNKNOWN_IMP STDMETHOD(QueryInterface)(REFGUID, void **) { \
MY_QUERYINTERFACE_END \
MY_ADDREF_RELEASE
#define MY_UNKNOWN_IMP1(i) MY_UNKNOWN_IMP_SPEC( \
MY_QUERYINTERFACE_ENTRY(i) \
)
#define MY_UNKNOWN_IMP2(i1, i2) MY_UNKNOWN_IMP_SPEC( \
MY_QUERYINTERFACE_ENTRY(i1) \
MY_QUERYINTERFACE_ENTRY(i2) \
)
#define MY_UNKNOWN_IMP3(i1, i2, i3) MY_UNKNOWN_IMP_SPEC( \
MY_QUERYINTERFACE_ENTRY(i1) \
MY_QUERYINTERFACE_ENTRY(i2) \
MY_QUERYINTERFACE_ENTRY(i3) \
)
#define MY_UNKNOWN_IMP4(i1, i2, i3, i4) MY_UNKNOWN_IMP_SPEC( \
MY_QUERYINTERFACE_ENTRY(i1) \
MY_QUERYINTERFACE_ENTRY(i2) \
MY_QUERYINTERFACE_ENTRY(i3) \
MY_QUERYINTERFACE_ENTRY(i4) \
)
#define MY_UNKNOWN_IMP5(i1, i2, i3, i4, i5) MY_UNKNOWN_IMP_SPEC( \
MY_QUERYINTERFACE_ENTRY(i1) \
MY_QUERYINTERFACE_ENTRY(i2) \
MY_QUERYINTERFACE_ENTRY(i3) \
MY_QUERYINTERFACE_ENTRY(i4) \
MY_QUERYINTERFACE_ENTRY(i5) \
)
#endif

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// Common/MyGuidDef.h
#ifndef GUID_DEFINED
#define GUID_DEFINED
#include "Types.h"
typedef struct {
UInt32 Data1;
UInt16 Data2;
UInt16 Data3;
unsigned char Data4[8];
} GUID;
#ifdef __cplusplus
#define REFGUID const GUID &
#else
#define REFGUID const GUID *
#endif
#define REFCLSID REFGUID
#define REFIID REFGUID
#ifdef __cplusplus
inline bool operator==(REFGUID g1, REFGUID g2)
{
for (int i = 0; i < (int)sizeof(g1); i++)
if (((const unsigned char *)&g1)[i] != ((const unsigned char *)&g2)[i])
return false;
return true;
}
inline bool operator!=(REFGUID g1, REFGUID g2) { return !(g1 == g2); }
#endif
#ifdef __cplusplus
#define MY_EXTERN_C extern "C"
#else
#define MY_EXTERN_C extern
#endif
#endif // GUID_DEFINED
#ifdef DEFINE_GUID
#undef DEFINE_GUID
#endif
#ifdef INITGUID
#define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
MY_EXTERN_C const GUID name = { l, w1, w2, { b1, b2, b3, b4, b5, b6, b7, b8 } }
#else
#define DEFINE_GUID(name, l, w1, w2, b1, b2, b3, b4, b5, b6, b7, b8) \
MY_EXTERN_C const GUID name
#endif

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// Common/MyInitGuid.h
#ifndef __COMMON_MYINITGUID_H
#define __COMMON_MYINITGUID_H
#ifdef _WIN32
#include <initguid.h>
#else
#define INITGUID
#include "MyGuidDef.h"
#endif
#endif

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// MyUnknown.h
#ifndef __MYUNKNOWN_H
#define __MYUNKNOWN_H
#ifdef _WIN32
#ifdef _WIN32_WCE
#if (_WIN32_WCE > 300)
#include <basetyps.h>
#else
#define MIDL_INTERFACE(x) struct
#endif
#else
#include <basetyps.h>
#endif
#include <unknwn.h>
#else
#include "MyWindows.h"
#endif
#endif

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// MyWindows.h
#ifndef __MYWINDOWS_H
#define __MYWINDOWS_H
#ifdef _WIN32
#include <windows.h>
#define CHAR_PATH_SEPARATOR '\\'
#define WCHAR_PATH_SEPARATOR L'\\'
#define STRING_PATH_SEPARATOR "\\"
#define WSTRING_PATH_SEPARATOR L"\\"
#else
#define CHAR_PATH_SEPARATOR '/'
#define WCHAR_PATH_SEPARATOR L'/'
#define STRING_PATH_SEPARATOR "/"
#define WSTRING_PATH_SEPARATOR L"/"
#include <stddef.h> // for wchar_t
#include <string.h>
#include "MyGuidDef.h"
typedef char CHAR;
typedef unsigned char UCHAR;
#undef BYTE
typedef unsigned char BYTE;
typedef short SHORT;
typedef unsigned short USHORT;
#undef WORD
typedef unsigned short WORD;
typedef short VARIANT_BOOL;
typedef int INT;
typedef Int32 INT32;
typedef unsigned int UINT;
typedef UInt32 UINT32;
typedef INT32 LONG; // LONG, ULONG and DWORD must be 32-bit
typedef UINT32 ULONG;
#undef DWORD
typedef UINT32 DWORD;
typedef Int64 LONGLONG;
typedef UInt64 ULONGLONG;
typedef struct LARGE_INTEGER { LONGLONG QuadPart; }LARGE_INTEGER;
typedef struct _ULARGE_INTEGER { ULONGLONG QuadPart;} ULARGE_INTEGER;
typedef const CHAR *LPCSTR;
typedef CHAR TCHAR;
typedef const TCHAR *LPCTSTR;
typedef wchar_t WCHAR;
typedef WCHAR OLECHAR;
typedef const WCHAR *LPCWSTR;
typedef OLECHAR *BSTR;
typedef const OLECHAR *LPCOLESTR;
typedef OLECHAR *LPOLESTR;
typedef struct _FILETIME
{
DWORD dwLowDateTime;
DWORD dwHighDateTime;
}FILETIME;
#define HRESULT LONG
#define FAILED(Status) ((HRESULT)(Status)<0)
typedef ULONG PROPID;
typedef LONG SCODE;
#define S_OK ((HRESULT)0x00000000L)
#define S_FALSE ((HRESULT)0x00000001L)
#define E_NOTIMPL ((HRESULT)0x80004001L)
#define E_NOINTERFACE ((HRESULT)0x80004002L)
#define E_ABORT ((HRESULT)0x80004004L)
#define E_FAIL ((HRESULT)0x80004005L)
#define STG_E_INVALIDFUNCTION ((HRESULT)0x80030001L)
#define E_OUTOFMEMORY ((HRESULT)0x8007000EL)
#define E_INVALIDARG ((HRESULT)0x80070057L)
#ifdef _MSC_VER
#define STDMETHODCALLTYPE __stdcall
#else
#define STDMETHODCALLTYPE
#endif
#define STDMETHOD_(t, f) virtual t STDMETHODCALLTYPE f
#define STDMETHOD(f) STDMETHOD_(HRESULT, f)
#define STDMETHODIMP_(type) type STDMETHODCALLTYPE
#define STDMETHODIMP STDMETHODIMP_(HRESULT)
#define PURE = 0
#define MIDL_INTERFACE(x) struct
struct IUnknown
{
//virtual ~IUnknown() {}
STDMETHOD(QueryInterface) (REFIID iid, void **outObject) PURE;
STDMETHOD_(ULONG, AddRef)() PURE;
STDMETHOD_(ULONG, Release)() PURE;
};
typedef IUnknown *LPUNKNOWN;
#define VARIANT_TRUE ((VARIANT_BOOL)-1)
#define VARIANT_FALSE ((VARIANT_BOOL)0)
enum VARENUM
{
VT_EMPTY = 0,
VT_NULL = 1,
VT_I2 = 2,
VT_I4 = 3,
VT_R4 = 4,
VT_R8 = 5,
VT_CY = 6,
VT_DATE = 7,
VT_BSTR = 8,
VT_DISPATCH = 9,
VT_ERROR = 10,
VT_BOOL = 11,
VT_VARIANT = 12,
VT_UNKNOWN = 13,
VT_DECIMAL = 14,
VT_I1 = 16,
VT_UI1 = 17,
VT_UI2 = 18,
VT_UI4 = 19,
VT_I8 = 20,
VT_UI8 = 21,
VT_INT = 22,
VT_UINT = 23,
VT_VOID = 24,
VT_HRESULT = 25,
VT_FILETIME = 64
};
typedef unsigned short VARTYPE;
typedef WORD PROPVAR_PAD1;
typedef WORD PROPVAR_PAD2;
typedef WORD PROPVAR_PAD3;
typedef struct tagPROPVARIANT
{
VARTYPE vt;
PROPVAR_PAD1 wReserved1;
PROPVAR_PAD2 wReserved2;
PROPVAR_PAD3 wReserved3;
union
{
CHAR cVal;
UCHAR bVal;
SHORT iVal;
USHORT uiVal;
LONG lVal;
ULONG ulVal;
INT intVal;
UINT uintVal;
LARGE_INTEGER hVal;
ULARGE_INTEGER uhVal;
VARIANT_BOOL boolVal;
SCODE scode;
FILETIME filetime;
BSTR bstrVal;
};
} PROPVARIANT;
typedef PROPVARIANT tagVARIANT;
typedef tagVARIANT VARIANT;
typedef VARIANT VARIANTARG;
MY_EXTERN_C BSTR SysAllocStringByteLen(LPCSTR psz, UINT len);
MY_EXTERN_C BSTR SysAllocString(const OLECHAR *sz);
MY_EXTERN_C void SysFreeString(BSTR bstr);
MY_EXTERN_C UINT SysStringByteLen(BSTR bstr);
MY_EXTERN_C UINT SysStringLen(BSTR bstr);
MY_EXTERN_C DWORD GetLastError();
MY_EXTERN_C HRESULT VariantClear(VARIANTARG *prop);
MY_EXTERN_C HRESULT VariantCopy(VARIANTARG *dest, VARIANTARG *src);
MY_EXTERN_C LONG CompareFileTime(const FILETIME* ft1, const FILETIME* ft2);
#define CP_ACP 0
#define CP_OEMCP 1
typedef enum tagSTREAM_SEEK
{
STREAM_SEEK_SET = 0,
STREAM_SEEK_CUR = 1,
STREAM_SEEK_END = 2
} STREAM_SEEK;
#endif
#endif

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// Common/NewHandler.h
#ifndef __COMMON_NEWHANDLER_H
#define __COMMON_NEWHANDLER_H
class CNewException {};
#ifdef _WIN32
void
#ifdef _MSC_VER
__cdecl
#endif
operator delete(void *p) throw();
#endif
#endif

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// StdAfx.h
#ifndef __STDAFX_H
#define __STDAFX_H
// #include "MyWindows.h"
#include "NewHandler.h"
#endif

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// Common/Types.h
#ifndef __COMMON_TYPES_H
#define __COMMON_TYPES_H
typedef unsigned char Byte;
typedef short Int16;
typedef unsigned short UInt16;
typedef int Int32;
typedef unsigned int UInt32;
#ifdef _MSC_VER
typedef __int64 Int64;
typedef unsigned __int64 UInt64;
#else
typedef long long int Int64;
typedef unsigned long long int UInt64;
#endif
#endif

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GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
Copyright (C) 1991, 1999 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
[This is the first released version of the Lesser GPL. It also counts
as the successor of the GNU Library Public License, version 2, hence
the version number 2.1.]
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
Licenses are intended to guarantee your freedom to share and change
free software--to make sure the software is free for all its users.
This license, the Lesser General Public License, applies to some
specially designated software packages--typically libraries--of the
Free Software Foundation and other authors who decide to use it. You
can use it too, but we suggest you first think carefully about whether
this license or the ordinary General Public License is the better
strategy to use in any particular case, based on the explanations below.
When we speak of free software, we are referring to freedom of use,
not price. Our General Public Licenses are designed to make sure that
you have the freedom to distribute copies of free software (and charge
for this service if you wish); that you receive source code or can get
it if you want it; that you can change the software and use pieces of
it in new free programs; and that you are informed that you can do
these things.
To protect your rights, we need to make restrictions that forbid
distributors to deny you these rights or to ask you to surrender these
rights. These restrictions translate to certain responsibilities for
you if you distribute copies of the library or if you modify it.
For example, if you distribute copies of the library, whether gratis
or for a fee, you must give the recipients all the rights that we gave
you. You must make sure that they, too, receive or can get the source
code. If you link other code with the library, you must provide
complete object files to the recipients, so that they can relink them
with the library after making changes to the library and recompiling
it. And you must show them these terms so they know their rights.
We protect your rights with a two-step method: (1) we copyright the
library, and (2) we offer you this license, which gives you legal
permission to copy, distribute and/or modify the library.
To protect each distributor, we want to make it very clear that
there is no warranty for the free library. Also, if the library is
modified by someone else and passed on, the recipients should know
that what they have is not the original version, so that the original
author's reputation will not be affected by problems that might be
introduced by others.
Finally, software patents pose a constant threat to the existence of
any free program. We wish to make sure that a company cannot
effectively restrict the users of a free program by obtaining a
restrictive license from a patent holder. Therefore, we insist that
any patent license obtained for a version of the library must be
consistent with the full freedom of use specified in this license.
Most GNU software, including some libraries, is covered by the
ordinary GNU General Public License. This license, the GNU Lesser
General Public License, applies to certain designated libraries, and
is quite different from the ordinary General Public License. We use
this license for certain libraries in order to permit linking those
libraries into non-free programs.
When a program is linked with a library, whether statically or using
a shared library, the combination of the two is legally speaking a
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That's all there is to it!

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@ -0,0 +1,3 @@
The contents of this directory are extracted from
the official LZMA SDK, version lzma442.tar.bz2 ,
for the use in mkcromfs.

View File

@ -0,0 +1,63 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
LZMA_OBJ := $(obj)/util/lzma/LZMAEncoder.o $(obj)/util/lzma/LZInWindow.o
LZMA_OBJ += $(obj)/util/lzma/RangeCoderBit.o $(obj)/util/lzma/StreamUtils.o
LZMA_OBJ += $(obj)/util/lzma/OutBuffer.o $(obj)/util/lzma/Alloc.o
LZMA_OBJ += $(obj)/util/lzma/CRC.o
$(obj)/util/lzma/lzma: $(obj)/util/lzma/ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $(LZMA_OBJ) $(obj)/util/lzma/minilzma.o
$(obj)/util/lzma/lzma-compress.o: $(src)/util/lzma/minilzma.cc
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c -DCOMPACT $<
$(obj)/util/lzma/:
$(Q)printf " BUILD LZMA\n"
$(Q)mkdir -p $(obj)/util/lzma/
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/7zip/Compress/LZMA/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/7zip/Compress/LZ/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/7zip/Compress/RangeCoder/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/7zip/Decompress/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/7zip/Common/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/C/Common/%.cpp
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
$(obj)/util/lzma/%.o: $(src)/util/lzma/%.cc
$(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<

View File

@ -0,0 +1,318 @@
/*
* minimal lzma implementation
*
* Copyright (C) 2002 Eric Biederman
* Copyright (C) 2005 Joel Yliluoma
* Copyright (C) 2007 coresystems GmbH
* (Adapted by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2007 Patrick Georgi <patrick@georgi-clan.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#include "C/Common/MyInitGuid.h"
#include "C/7zip/Compress/LZMA/LZMAEncoder.h"
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
#include <cstring>
#include <cstdio>
#include <cstdlib>
#include <cctype>
#include <vector>
#include <algorithm>
#include <stdint.h>
const std::vector<unsigned char> LZMACompress
(const std::vector<unsigned char>& buf);
const std::vector<unsigned char> LZMADeCompress
(const std::vector<unsigned char>& buf);
static inline uint16_t R16(const void* p)
{
const unsigned char* data = (const unsigned char*)p;
return (data[0] << 0) | (data[1] << 8);
}
static inline uint32_t R32(const void* p)
{
const unsigned char* data = (const unsigned char*)p;
return R16(data) | (R16(data+2) << 16);
}
#define L (uint64_t)
static inline uint64_t R64(const void* p)
{
const unsigned char* data = (const unsigned char*)p;
return (L R32(data)) | ((L R32(data+4)) << 32);
}
#undef L
static UInt32 SelectDictionarySizeFor(unsigned datasize)
{
#if 1
return datasize;
#else
#ifdef __GNUC__
/* gnu c can optimize this switch statement into a fast binary
* search, but it cannot do so for the list of the if statements.
*/
switch(datasize)
{
case 0 ... 512 : return 512;
case 513 ... 1024: return 2048;
case 1025 ... 4096: return 8192;
case 4097 ... 16384: return 32768;
case 16385 ... 65536: return 528288;
case 65537 ... 528288: return 1048576*4;
case 528289 ... 786432: return 1048576*16;
default: return 1048576*32;
}
#else
if(datasize <= 512) return 512;
if(datasize <= 1024) return 1024;
if(datasize <= 4096) return 4096;
if(datasize <= 16384) return 32768;
if(datasize <= 65536) return 528288;
if(datasize <= 528288) return 1048576*4;
if(datasize <= 786432) reutrn 1048576*16;
return 32*1048576;
#endif
#endif
}
class CInStreamRam: public ISequentialInStream, public CMyUnknownImp
{
const std::vector<unsigned char>& input;
size_t Pos;
public:
MY_UNKNOWN_IMP
CInStreamRam(const std::vector<unsigned char>& buf) : input(buf), Pos(0)
{
}
virtual ~CInStreamRam() {}
STDMETHOD(Read)(void *data, UInt32 size, UInt32 *processedSize);
};
STDMETHODIMP CInStreamRam::Read(void *data, UInt32 size, UInt32 *processedSize)
{
UInt32 remain = input.size() - Pos;
if (size > remain) size = remain;
std::memcpy(data, &input[Pos], size);
Pos += size;
if(processedSize != NULL) *processedSize = size;
return S_OK;
}
class COutStreamRam: public ISequentialOutStream, public CMyUnknownImp
{
std::vector<Byte> result;
size_t Pos;
public:
MY_UNKNOWN_IMP
COutStreamRam(): result(), Pos(0) { }
virtual ~COutStreamRam() { }
void Reserve(unsigned n) { result.reserve(n); }
const std::vector<Byte>& Get() const { return result; }
HRESULT WriteByte(Byte b)
{
if(Pos >= result.size()) result.resize(Pos+1);
result[Pos++] = b;
return S_OK;
}
STDMETHOD(Write)(const void *data, UInt32 size, UInt32 *processedSize);
};
STDMETHODIMP COutStreamRam::Write(const void *data, UInt32 size, UInt32 *processedSize)
{
if(Pos+size > result.size()) result.resize(Pos+size);
std::memcpy(&result[Pos], data, size);
if(processedSize != NULL) *processedSize = size;
Pos += size;
return S_OK;
}
const std::vector<unsigned char> LZMACompress(const std::vector<unsigned char>& buf)
{
if(buf.empty()) return buf;
const UInt32 dictionarysize = SelectDictionarySizeFor(buf.size());
NCompress::NLZMA::CEncoder *encoderSpec = new NCompress::NLZMA::CEncoder;
CMyComPtr<ICompressCoder> encoder = encoderSpec;
const PROPID propIDs[] =
{
NCoderPropID::kAlgorithm,
NCoderPropID::kDictionarySize,
NCoderPropID::kNumFastBytes,
};
const unsigned kNumProps = sizeof(propIDs) / sizeof(propIDs[0]);
PROPVARIANT properties[kNumProps];
properties[0].vt = VT_UI4; properties[0].ulVal = (UInt32)2;
properties[1].vt = VT_UI4; properties[1].ulVal = (UInt32)dictionarysize;
properties[2].vt = VT_UI4; properties[2].ulVal = (UInt32)64;
if (encoderSpec->SetCoderProperties(propIDs, properties, kNumProps) != S_OK)
{
Error:
return std::vector<unsigned char> ();
}
COutStreamRam *const outStreamSpec = new COutStreamRam;
CMyComPtr<ISequentialOutStream> outStream = outStreamSpec;
CInStreamRam *const inStreamSpec = new CInStreamRam(buf);
CMyComPtr<ISequentialInStream> inStream = inStreamSpec;
outStreamSpec->Reserve(buf.size());
if (encoderSpec->WriteCoderProperties(outStream) != S_OK) goto Error;
for (unsigned i = 0; i < 8; i++)
{
UInt64 t = (UInt64)buf.size();
outStreamSpec->WriteByte((Byte)((t) >> (8 * i)));
}
HRESULT lzmaResult = encoder->Code(inStream, outStream, 0, 0, 0);
if (lzmaResult != S_OK) goto Error;
return outStreamSpec->Get();
}
#undef RC_NORMALIZE
#include "C/7zip/Decompress/LzmaDecode.h"
#include "C/7zip/Decompress/LzmaDecode.c"
const std::vector<unsigned char> LZMADeCompress
(const std::vector<unsigned char>& buf)
{
if(buf.size() <= 5+8) return std::vector<unsigned char> ();
uint_least64_t out_sizemax = R64(&buf[5]);
std::vector<unsigned char> result(out_sizemax);
CLzmaDecoderState state;
LzmaDecodeProperties(&state.Properties, &buf[0], LZMA_PROPERTIES_SIZE);
state.Probs = new CProb[LzmaGetNumProbs(&state.Properties)];
SizeT in_done;
SizeT out_done;
LzmaDecode(&state, &buf[13], buf.size()-13, &in_done,
&result[0], result.size(), &out_done);
delete[] state.Probs;
result.resize(out_done);
return result;
}
#ifndef COMPACT
int main(int argc, char *argv[])
{
char *s;
FILE *f, *infile, *outfile;
int c;
if (argc != 4) {
std::fprintf(stderr, "'lzma e file1 file2' encodes file1 into file2.\n"
"'lzma d file2 file1' decodes file2 into file1.\n");
return EXIT_FAILURE;
}
if (argc == 4) {
if ((s = argv[1], s[1] || strpbrk(s, "DEde") == NULL)
|| (s = argv[2], (infile = fopen(s, "rb")) == NULL)
|| (s = argv[3], (outfile = fopen(s, "wb")) == NULL)) {
std::fprintf(stderr, "??? %s\n", s);
return EXIT_FAILURE;
}
}
struct stat fs;
int si;
if (fstat(fileno(infile), &fs)) {
std::perror(strerror(errno));
return EXIT_FAILURE;
}
si=fs.st_size;
char *Buf=(char *)malloc(si);
fread(Buf,si, 1, infile);
std::vector<unsigned char> result;
if (toupper(*argv[1]) == 'E')
result = LZMACompress(std::vector<unsigned char>(Buf,Buf+si));
else
result = LZMADeCompress(std::vector<unsigned char>(Buf,Buf+si));
fwrite(&result[0], result.size(), 1, outfile);
fclose(infile);
fclose(outfile);
return EXIT_SUCCESS;
}
#else
extern "C" {
/**
* Compress a buffer with lzma
* Don't copy the result back if it is too large.
* @param in a pointer to the buffer
* @param in_len the length in bytes
* @param out a pointer to a buffer of at least size in_len
* @param out_len a pointer to the compressed length of in
*/
void do_lzma_compress(char *in, int in_len, char *out, int *out_len) {
std::vector<unsigned char> result;
result = LZMACompress(std::vector<unsigned char>(in, in + in_len));
*out_len = result.size();
if (*out_len < in_len)
std::memcpy(out, &result[0], *out_len);
}
void do_lzma_uncompress(char *dst, int dst_len, char *src, int src_len) {
std::vector<unsigned char> result;
result = LZMADeCompress(std::vector<unsigned char>(src, src + src_len));
if (result.size() <= dst_len)
std::memcpy(dst, &result[0], result.size());
else
{
fprintf(stderr, "Not copying %d bytes to %d-byte buffer!\n",
result.size(), dst_len);
exit(1);
}
}
}
#endif

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@ -0,0 +1,82 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdio.h>
#include <string.h>
#include <getopt.h>
#include "pbuilder.h"
static void usage(void)
{
printf("./pbuilder [-c config] [create|show] [LAR]\n");
}
int main(int argc, char **argv)
{
char *config = NULL;
while (1) {
signed ch = getopt(argc, argv, "c:");
if (ch == -1)
break;
switch (ch) {
case 'c':
config = optarg;
break;
default:
usage();
return -1;
}
}
if (optind >= argc) {
usage();
return 0;
}
if (!strcmp(argv[optind], "create")) {
if (config == NULL) {
warn("E: No config was provided\n");
usage();
return -1;
}
if (optind + 1 >= argc) {
warn("E: No LAR name was given\n");
usage();
return -1;
}
create_lar_from_config((const char *)config,
(const char *)argv[optind + 1]);
} else if (!strcmp(argv[optind], "show")) {
if (optind + 1 >= argc) {
warn("E: No LAR name was given\n");
usage();
return -1;
}
pbuilder_show_lar((const char *)argv[optind + 1]);
} else {
usage();
return -1;
}
return 0;
}

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@ -0,0 +1,77 @@
/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdio.h>
#ifndef PBUILDER_H_
#define PBUILDER_H_
#include <stdint.h>
#include <stdio.h>
#define warn(fmt, args...) fprintf(stderr, fmt, ##args)
#define die(fmt, args...) \
do { fprintf(stderr, fmt, ##args); exit(-1); } \
while(0)
struct pentry {
uint8_t index;
uint8_t parent;
uint8_t type;
uint8_t flags;
uint8_t title[64];
char *file;
char *larname;
};
struct config {
int timeout;
int n_entries;
struct pentry **entries;
};
struct bpt_config {
uint32_t id;
uint8_t timeout;
uint8_t entries;
uint8_t padding[10];
};
struct bpt_pentry {
uint8_t index;
uint8_t parent;
uint8_t type;
uint8_t flags;
uint8_t title[64];
uint8_t nlen;
};
#define BPT_ID 0x30545042
#define BPT_TYPE_CHOOSER 0x01
#define BPT_TYPE_CHAIN 0x02
#define BPT_TYPE_SUBCHAIN 0x03
#define BPT_FLAG_DEFAULT 0x01
#define BPT_FLAG_NOSHOW 0x02
int pbuilder_show_lar(const char *input);
int create_lar_from_config(const char *input, const char *output);
void parseconfig(FILE * stream, struct config *config);
#endif

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/*
* This file is part of the bayou project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdio.h>
#include "liblar.h"
#include "pbuilder.h"
void show_subchain(struct bpt_config *cfg, char *fptr, int index)
{
int i;
char *ptr = fptr + sizeof(struct bpt_config);
for (i = 0; i < cfg->entries; i++) {
struct bpt_pentry *entry = (struct bpt_pentry *)ptr;
if (entry->parent == index)
printf(" + %.64s\n",
ptr + sizeof(struct bpt_pentry));
ptr += (sizeof(struct bpt_pentry) + entry->nlen);
}
}
int show_payloads(struct bpt_config *cfg, char *fptr)
{
int i;
char *ptr = fptr + sizeof(struct bpt_config);
for (i = 0; i < cfg->entries; i++) {
struct bpt_pentry *entry = (struct bpt_pentry *)ptr;
if (entry->parent != 0) {
ptr += (sizeof(struct bpt_pentry) + entry->nlen);
continue;
}
printf(" ");
if (entry->flags & BPT_FLAG_DEFAULT)
printf("D");
else
printf(" ");
if (entry->flags & BPT_FLAG_NOSHOW)
printf("N");
else
printf(" ");
switch (entry->type) {
case BPT_TYPE_CHOOSER:
printf(" MENU ");
break;
case BPT_TYPE_CHAIN:
printf(" CHAIN");
break;
}
if (entry->title[0] != 0)
printf(" %.64s\n", entry->title);
else
printf(" - no title -\n");
if (entry->type == BPT_TYPE_CHOOSER)
printf(" %.60s\n",
ptr + sizeof(struct bpt_pentry));
else
show_subchain(cfg, fptr, entry->index);
ptr += (sizeof(struct bpt_pentry) + entry->nlen);
}
return 0;
}
int pbuilder_show_lar(const char *input)
{
int ret = -1;
struct LAR *lar;
struct bpt_config *cfg;
struct LARFile *lfile;
lar = LAR_Open(input);
if (lar == NULL) {
warn("E: Couldn't open LAR %s\n", input);
return -1;
}
lfile = LAR_MapFile(lar, "bayou_payload_table");
if (lfile == NULL) {
warn("E: Couldn't find the bayou payload table. Nothing to do.\n");
goto err;
}
cfg = (struct bpt_config *)lfile->buffer;
if (cfg->id != BPT_ID) {
warn("E: BPT ID does not match\n");
goto err;
}
printf("Bayou Payload Configuration\n");
printf("Timeout = %d seconds\n", cfg->timeout);
printf("Payload List:\n");
show_payloads(cfg, lfile->buffer);
ret = 0;
err:
LAR_CloseFile(lfile);
LAR_Close(lar);
return ret;
}

339
payloads/coreinfo/COPYING Normal file
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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Lesser General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.
Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

116
payloads/coreinfo/Kconfig Normal file
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##
## This file is part of the coreinfo project.
##
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#
# For a description of the syntax of this configuration file,
# see http://lxr.linux.no/source/Documentation/kbuild/kconfig-language.txt.
#
mainmenu "coreinfo Configuration"
menu "General settings"
# TODO: Needs changes in coreinfo, won't update without keypress currently.
config SHOW_DATE_TIME
bool "Show current date/time in the menu"
default y
help
Show the current date and time in the lower-right corner of
the coreinfo menu.
This option will increase the ELF file size by ca. 250 bytes.
config PAYLOAD_INFO_NAME
string "Payload name"
default "coreinfo"
help
The name of this payload for use in (e.g.) Bayou.
config PAYLOAD_INFO_LISTNAME
string "Payload menu entry name"
default "System Information"
help
The name of this payload's menu entry for use in (e.g.) Bayou.
config PAYLOAD_INFO_DESC
string "Payload description"
default "Display information about the system"
help
The description of this payload for use in (e.g.) Bayou.
config PAYLOAD_INFO_VERSION
string "Payload version"
default "0.1"
help
The version number of this payload.
endmenu
menu "Modules"
config MODULE_COREBOOT
bool "Enable the coreboot module"
default y
help
This option will increase the ELF file size by ca. 2250 bytes.
config MODULE_MULTIBOOT
bool "Enable the multiboot module"
default y
help
This option will increase the ELF file size by ca. 1790 bytes.
config MODULE_CPUINFO
bool "Enable the cpuinfo module"
default y
help
This option will increase the ELF file size by ca. 2650 bytes.
config MODULE_PCI
bool "Enable the PCI info module"
default y
help
This option will increase the ELF file size by ca. 1750 bytes.
config MODULE_NVRAM
bool "Enable the NVRAM dump module"
default y
help
This option will increase the ELF file size by ca. 350 bytes.
config MODULE_BOOTLOG
bool "Enable the coreboot bootlog module"
default y
config MODULE_RAMDUMP
bool "Enable the RAM dump module"
default y
config MODULE_LAR
bool "Enable the coreboot LAR module"
default y
config MODULE_CBFS
bool "Enable the coreboot CBFS module"
default y
help
This option will increase the ELF file size by ca. 1440 bytes.
endmenu

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##
## This file is part of the coreinfo project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
export src := $(shell pwd)
export srctree := $(src)
export srck := $(src)/util/kconfig
export obj := $(src)/build
export objk := $(src)/build/util/kconfig
export KERNELVERSION := 0.1.0
export KCONFIG_AUTOHEADER := $(obj)/config.h
export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
CONFIG_SHELL := sh
KBUILD_DEFCONFIG := configs/defconfig
UNAME_RELEASE := $(shell uname -r)
HAVE_DOTCONFIG := $(wildcard .config)
MAKEFLAGS += -rR --no-print-directory
# Make is silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
Q := @
endif
HOSTCC = gcc
HOSTCXX = g++
HOSTCFLAGS := -I$(srck) -I$(objk)
HOSTCXXFLAGS := -I$(srck) -I$(objk)
LIBPAYLOAD_DIR := ../libpayload
XCC := CC=$(CC) $(LIBPAYLOAD_DIR)/bin/lpgcc
AS = $(LIBPAYLOAD_DIR)/bin/lpas
STRIP ?= strip
INCLUDES = -Ibuild
CFLAGS := -Wall -Werror -Os $(INCLUDES)
OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \
nvram_module.o bootlog_module.o ramdump_module.o lar_module.o \
multiboot_module.o cbfs_module.o coreinfo.o
OBJS = $(patsubst %,$(obj)/%,$(OBJECTS))
TARGET = $(obj)/coreinfo.elf
ifeq ($(strip $(HAVE_DOTCONFIG)),)
all: config
else
include $(src)/.config
all: $(TARGET)
$(TARGET): $(src)/.config $(OBJS) prepare
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(XCC) -o $@ $(OBJS)
$(Q)printf " STRIP $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(STRIP) -s $@
$(obj)/%.S.o: $(src)/%.S
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AS) -o $@ $<
$(obj)/%.o: $(src)/%.c
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(XCC) $(CFLAGS) -c -o $@ $<
endif
prepare:
$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
clean:
$(Q)rm -rf build/*.elf build/*.o
distclean: clean
$(Q)rm -rf build
$(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
include util/kconfig/Makefile
.PHONY: $(PHONY) prepare clean distclean

3
payloads/coreinfo/README Normal file
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This is a silly little program that demonstrates how cool libpayload is
and also serves a purpose. Its fun and educational!

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/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "coreinfo.h"
#ifdef CONFIG_MODULE_BOOTLOG
#define CONFIG_COREBOOT_PRINTK_BUFFER_ADDR 0x90000
#define CONFIG_COREBOOT_PRINTK_BUFFER_SIZE 65536
static char *buf;
static s32 cursor = 0;
static s32 cursor_max;
static int bootlog_module_init(void)
{
int i;
volatile unsigned long *ptr =
(void *)(CONFIG_COREBOOT_PRINTK_BUFFER_ADDR + 16); /* FIXME */
buf = malloc(CONFIG_COREBOOT_PRINTK_BUFFER_SIZE);
if (!buf) {
/* TODO */
}
memcpy(buf, (char *)ptr, CONFIG_COREBOOT_PRINTK_BUFFER_SIZE);
cursor_max = CONFIG_COREBOOT_PRINTK_BUFFER_SIZE;
for (i = 0; i < 20; i++) {
do {
cursor_max--;
} while (*(buf + cursor_max) != '\n');
}
cursor_max++; /* Stay _behind_ the newline. */
/* TODO: Maybe a _cleanup hook where we call free()? */
return 0;
}
static int bootlog_module_redraw(WINDOW *win)
{
int x = 0, y = 0;
char *tmp = buf + cursor;
print_module_title(win, "Coreboot Bootlog");
/* FIXME: Handle lines longer than 80 characters. */
while (y <= 18) {
mvwaddch(win, y + 2, x, isprint(*tmp) ? *tmp : ' ');
x++;
tmp++;
if (*tmp == '\n') {
y++;
x = 0;
tmp++; /* Skip the newline. */
}
}
return 0;
}
/* TODO: Simplify code. */
static int bootlog_module_handle(int key)
{
int i;
switch (key) {
case KEY_DOWN:
if (cursor == cursor_max)
return 0;
while (*(buf + cursor) != '\n')
cursor++;
cursor++; /* Skip the newline. */
break;
case KEY_UP:
if (cursor == 0)
return 0;
cursor--; /* Skip the newline. */
do {
cursor--;
} while (*(buf + cursor) != '\n');
cursor++; /* Stay _behind_ the newline. */
break;
case KEY_NPAGE:
if (cursor == cursor_max)
return 0;
for (i = 0; i < 20; i++) {
while (*(buf + cursor) != '\n')
cursor++;
cursor++; /* Skip the newline. */
}
break;
case KEY_PPAGE:
if (cursor == 0)
return 0;
for (i = 0; i < 20; i++) {
do {
cursor--;
} while (*(buf + cursor) != '\n');
}
cursor++; /* Stay _behind_ the newline. */
break;
}
if (cursor > cursor_max)
cursor = cursor_max;
if (cursor < 0)
cursor = 0;
return 1;
}
struct coreinfo_module bootlog_module = {
.name = "Bootlog",
.init = bootlog_module_init,
.redraw = bootlog_module_redraw,
.handle = bootlog_module_handle,
};
#else
struct coreinfo_module bootlog_module = {
};
#endif

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/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "coreinfo.h"
#include "arch/endian.h"
#ifdef CONFIG_MODULE_CBFS
#define ALIGN(_v, _a) (((_v) + ((_a) - 1)) & ~((_a) - 1))
#define HEADER_MAGIC 0x4F524243
#define HEADER_ADDR 0xfffffffc
#define LARCHIVE_MAGIC 0x455649484352414cLL /* "LARCHIVE" */
#define COMPONENT_DELETED 0x00
#define COMPONENT_STAGE 0x10
#define COMPONENT_PAYLOAD 0x20
#define COMPONENT_OPTIONROM 0x30
#define COMPONENT_NULL 0xffffffff
struct cbheader {
u32 magic;
u32 version;
u32 romsize;
u32 bootblocksize;
u32 align;
u32 offset;
u32 pad[2];
} __attribute__ ((packed));
struct cbfile {
u64 magic;
u32 len;
u32 type;
u32 checksum;
u32 offset;
char filename[0];
} __attribute__ ((packed));
static int filecount = 0, selected = 0;
static char **filenames;
static struct cbheader *header = NULL;
static struct cbfile *getfile(struct cbfile *f)
{
while (1) {
if (f < (struct cbfile *)(0xffffffff - ntohl(header->romsize)))
return NULL;
if (f->magic == 0)
return NULL;
if (f->magic == LARCHIVE_MAGIC)
return f;
f = (void *)f + ntohl(header->align);
}
}
static struct cbfile *firstfile(void)
{
return getfile((void *)(0 - ntohl(header->romsize) +
ntohl(header->offset)));
}
static struct cbfile *nextfile(struct cbfile *f)
{
f = (void *)f + ALIGN(ntohl(f->len) + ntohl(f->offset),
ntohl(header->align));
return getfile(f);
}
static struct cbfile *findfile(const char *filename)
{
struct cbfile *f;
for (f = firstfile(); f; f = nextfile(f)) {
if (strcmp(filename, f->filename) == 0)
return f;
}
return NULL;
}
static int cbfs_module_init(void)
{
struct cbfile *f;
int index = 0;
header = *(void **)HEADER_ADDR;
if (header->magic != ntohl(HEADER_MAGIC)) {
header = NULL;
return 0;
}
for (f = firstfile(); f; f = nextfile(f))
filecount++;
filenames = malloc(filecount * sizeof(char *));
if (filenames == NULL)
return 0;
for (f = firstfile(); f; f = nextfile(f))
filenames[index++] = strdup((const char *)f->filename);
return 0;
}
static int cbfs_module_redraw(WINDOW * win)
{
struct cbfile *f;
int i, row = 2;
print_module_title(win, "CBFS Listing");
if (!header) {
mvwprintw(win, 11, 61 / 2, "Bad or missing CBFS header");
return 0;
}
/* Draw a line down the middle. */
for (i = 2; i < 21; i++)
mvwaddch(win, i, 30, ACS_VLINE);
/* Draw the names down the left side. */
for (i = 0; i < filecount; i++) {
if (i == selected)
wattrset(win, COLOR_PAIR(3) | A_BOLD);
else
wattrset(win, COLOR_PAIR(2));
if (i == filecount - 1)
mvwprintw(win, 2 + i, 1, "<free space>");
else
mvwprintw(win, 2 + i, 1, "%.25s", filenames[i]);
}
f = findfile(filenames[selected]);
if (!f) {
mvwprintw(win, 11, 32, "ERROR: CBFS component not found");
return 0;
}
wattrset(win, COLOR_PAIR(2));
/* mvwprintw(win, row++, 32, "Offset: 0x%x", f->offset); *//* FIXME */
mvwprintw(win, row, 32, "Type: ");
switch (ntohl(f->type)) {
case COMPONENT_STAGE:
mvwprintw(win, row++, 38, "stage");
break;
case COMPONENT_PAYLOAD:
mvwprintw(win, row++, 38, "payload");
break;
case COMPONENT_OPTIONROM:
mvwprintw(win, row++, 38, "optionrom");
break;
case COMPONENT_NULL:
mvwprintw(win, row++, 38, "free");
break;
case COMPONENT_DELETED:
mvwprintw(win, row++, 38, "deleted");
break;
default:
mvwprintw(win, row++, 38, "Unknown (0x%x)", ntohl(f->type));
break;
}
mvwprintw(win, row++, 32, "Size: %d", ntohl(f->len));
mvwprintw(win, row++, 32, "Checksum: 0x%x", ntohl(f->checksum));
return 0;
}
static int cbfs_module_handle(int key)
{
int ret = 0;
if (filecount == 0)
return 0;
switch (key) {
case KEY_DOWN:
if (selected + 1 < filecount) {
selected++;
ret = 1;
}
break;
case KEY_UP:
if (selected > 0) {
selected--;
ret = 1;
}
break;
}
return ret;
}
struct coreinfo_module cbfs_module = {
.name = "CBFS",
.init = cbfs_module_init,
.redraw = cbfs_module_redraw,
.handle = cbfs_module_handle
};
#else
struct coreinfo_module cbfs_module = {
};
#endif

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/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <coreboot_tables.h>
#include "coreinfo.h"
#ifdef CONFIG_MODULE_COREBOOT
#define MAX_MEMORY_COUNT 5
static struct {
int mem_count;
int mem_actual;
struct cb_memory_range range[MAX_MEMORY_COUNT];
char vendor[32];
char part[32];
char strings[10][64];
struct cb_serial serial;
struct cb_console console;
} cb_info;
static int tables_good = 0;
int coreboot_module_redraw(WINDOW *win)
{
int row = 2;
int i;
print_module_title(win, "Coreboot Tables");
if (tables_good) {
mvwprintw(win, row++, 1, "No Coreboot tables were found");
return 0;
}
mvwprintw(win, row++, 1, "Vendor: %s", cb_info.vendor);
mvwprintw(win, row++, 1, "Part: %s", cb_info.part);
mvwprintw(win, row++, 1, "Version: %s%s",
cb_info.strings[CB_TAG_VERSION - 0x4],
cb_info.strings[CB_TAG_EXTRA_VERSION - 0x4]);
mvwprintw(win, row++, 1, "Built: %s (%s@%s.%s)",
cb_info.strings[CB_TAG_BUILD - 0x4],
cb_info.strings[CB_TAG_COMPILE_BY - 0x04],
cb_info.strings[CB_TAG_COMPILE_HOST - 0x04],
cb_info.strings[CB_TAG_COMPILE_DOMAIN - 0x04]);
if (cb_info.serial.tag != 0x0) {
mvwprintw(win, row++, 1, "Serial Port I/O base: 0x%x",
cb_info.serial.ioport);
}
if (cb_info.console.tag != 0x0) {
mvwprintw(win, row++, 1, "Default Output Console: ");
switch (cb_info.console.type) {
case CB_TAG_CONSOLE_SERIAL8250:
wprintw(win, "Serial Port");
break;
case CB_TAG_CONSOLE_VGA:
wprintw(win, "VGA");
break;
case CB_TAG_CONSOLE_BTEXT:
wprintw(win, "BTEXT");
break;
case CB_TAG_CONSOLE_LOGBUF:
wprintw(win, "Log Buffer");
break;
case CB_TAG_CONSOLE_SROM:
wprintw(win, "Serial ROM");
break;
case CB_TAG_CONSOLE_EHCI:
wprintw(win, "USB Debug");
break;
}
}
row++;
mvwprintw(win, row++, 1, "-- Memory Map --");
for (i = 0; i < cb_info.mem_count; i++) {
switch (cb_info.range[i].type) {
case CB_MEM_RAM:
mvwprintw(win, row++, 3, " RAM: ");
break;
case CB_MEM_RESERVED:
mvwprintw(win, row++, 3, "Reserved: ");
break;
case CB_MEM_TABLE:
mvwprintw(win, row++, 3, " Table: ");
}
wprintw(win, "%16.16llx - %16.16llx",
UNPACK_CB64(cb_info.range[i].start),
UNPACK_CB64(cb_info.range[i].start) +
UNPACK_CB64(cb_info.range[i].size) - 1);
}
return 0;
}
static void parse_memory(unsigned char *ptr)
{
struct cb_memory *mem = (struct cb_memory *)ptr;
int max = (MEM_RANGE_COUNT(mem) > MAX_MEMORY_COUNT)
? MAX_MEMORY_COUNT : MEM_RANGE_COUNT(mem);
int i;
for (i = 0; i < max; i++) {
struct cb_memory_range *range =
(struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
memcpy(&cb_info.range[i], range, sizeof(*range));
}
cb_info.mem_count = max;
cb_info.mem_actual = MEM_RANGE_COUNT(mem);
}
static void parse_mainboard(unsigned char *ptr)
{
struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
}
static void parse_strings(unsigned char *ptr)
{
struct cb_string *string = (struct cb_string *)ptr;
int index = string->tag - CB_TAG_VERSION;
strncpy(cb_info.strings[index], (const char *)string->string, 63);
cb_info.strings[index][63] = 0;
}
static void parse_serial(unsigned char *ptr)
{
memcpy(&cb_info.serial, (struct cb_serial *)ptr,
sizeof(struct cb_serial));
}
static void parse_console(unsigned char *ptr)
{
memcpy(&cb_info.console, (struct cb_console *)ptr,
sizeof(struct cb_console));
}
static int parse_header(void *addr, int len)
{
struct cb_header *header;
unsigned char *ptr = (unsigned char *)addr;
int i;
for (i = 0; i < len; i += 16, ptr += 16) {
header = (struct cb_header *)ptr;
if (!strncmp((const char *)header->signature, "LBIO", 4))
break;
}
/* We walked the entire space and didn't find anything. */
if (i >= len)
return -1;
if (!header->table_bytes)
return 0;
/* FIXME: Check the checksum. */
if (ipchksum((uint16_t *) header, sizeof(*header)))
return -1;
if (ipchksum((uint16_t *) (ptr + sizeof(*header)), header->table_bytes)
!= header->table_checksum)
return -1;
/* Now, walk the tables. */
ptr += header->header_bytes;
for (i = 0; i < header->table_entries; i++) {
struct cb_record *rec = (struct cb_record *)ptr;
switch (rec->tag) {
case CB_TAG_FORWARD:
return parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, 1);
break;
case CB_TAG_MEMORY:
parse_memory(ptr);
break;
case CB_TAG_MAINBOARD:
parse_mainboard(ptr);
break;
case CB_TAG_VERSION:
case CB_TAG_EXTRA_VERSION:
case CB_TAG_BUILD:
case CB_TAG_COMPILE_TIME:
case CB_TAG_COMPILE_BY:
case CB_TAG_COMPILE_HOST:
case CB_TAG_COMPILE_DOMAIN:
case CB_TAG_COMPILER:
case CB_TAG_LINKER:
case CB_TAG_ASSEMBLER:
parse_strings(ptr);
break;
case CB_TAG_SERIAL:
parse_serial(ptr);
break;
case CB_TAG_CONSOLE:
parse_console(ptr);
break;
default:
break;
}
ptr += rec->size;
}
return 1;
}
static int coreboot_module_init(void)
{
int ret = parse_header((void *)0x00000, 0x1000);
if (ret != 1)
ret = parse_header((void *)0xf0000, 0x1000);
/* Return error if we couldn't find it at either address. */
tables_good = (ret == 1) ? 0 : -1;
return tables_good;
}
struct coreinfo_module coreboot_module = {
.name = "Coreboot",
.init = coreboot_module_init,
.redraw = coreboot_module_redraw,
};
#else
struct coreinfo_module coreboot_module = {
};
#endif

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/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "coreinfo.h"
#define SCREEN_Y 25
#define SCREEN_X 80
#define KEY_ESC 27
extern struct coreinfo_module cpuinfo_module;
extern struct coreinfo_module pci_module;
extern struct coreinfo_module coreboot_module;
extern struct coreinfo_module multiboot_module;
extern struct coreinfo_module nvram_module;
extern struct coreinfo_module bootlog_module;
extern struct coreinfo_module ramdump_module;
extern struct coreinfo_module lar_module;
extern struct coreinfo_module cbfs_module;
struct coreinfo_module *system_modules[] = {
#ifdef CONFIG_MODULE_CPUINFO
&cpuinfo_module,
#endif
#ifdef CONFIG_MODULE_PCI
&pci_module,
#endif
#ifdef CONFIG_MODULE_NVRAM
&nvram_module,
#endif
#ifdef CONFIG_MODULE_RAMDUMP
&ramdump_module,
#endif
};
struct coreinfo_module *firmware_modules[] = {
#ifdef CONFIG_MODULE_COREBOOT
&coreboot_module,
#endif
#ifdef CONFIG_MODULE_MULTIBOOT
&multiboot_module,
#endif
#ifdef CONFIG_MODULE_BOOTLOG
&bootlog_module,
#endif
#ifdef CONFIG_MODULE_LAR
&lar_module,
#endif
#ifdef CONFIG_MODULE_CBFS
&cbfs_module,
#endif
};
struct coreinfo_cat {
char name[15];
int cur;
int count;
struct coreinfo_module **modules;
} categories[] = {
{
.name = "System",
.modules = system_modules,
.count = ARRAY_SIZE(system_modules),
},
{
.name = "Firmware",
.modules = firmware_modules,
.count = ARRAY_SIZE(firmware_modules),
}
};
static WINDOW *modwin, *menuwin;
static int curwin;
void print_module_title(WINDOW *win, const char *title)
{
int i;
wattrset(win, COLOR_PAIR(2));
mvwprintw(win, 0, 1, title);
wmove(win, 1, 1);
for (i = 0; i < 78; i++)
waddch(win, ACS_HLINE);
}
static void print_submenu(struct coreinfo_cat *cat)
{
int i, j;
char menu[80];
char *ptr = menu;
wmove(menuwin, 0, 0);
for (j = 0; j < SCREEN_X; j++)
waddch(menuwin, ' ');
if (!cat->count)
return;
for (i = 0; i < cat->count; i++)
ptr += sprintf(ptr, "[%c: %s] ", 'A' + i,
cat->modules[i]->name);
mvwprintw(menuwin, 0, 0, menu);
}
#ifdef CONFIG_SHOW_DATE_TIME
static void print_time_and_date(void)
{
struct tm tm;
while (nvram_updating())
mdelay(10);
rtc_read_clock(&tm);
mvwprintw(menuwin, 0, 57, "%02d/%02d/%04d - %02d:%02d:%02d",
tm.tm_mon, tm.tm_mday, 1900 + tm.tm_year, tm.tm_hour,
tm.tm_min, tm.tm_sec);
}
#endif
static void print_menu(void)
{
int i, j;
char menu[80];
char *ptr = menu;
wmove(menuwin, 1, 0);
for (j = 0; j < SCREEN_X; j++)
waddch(menuwin, ' ');
for (i = 0; i < ARRAY_SIZE(categories); i++) {
if (categories[i].count == 0)
continue;
ptr += sprintf(ptr, "F%d: %s ", i + 1, categories[i].name);
}
mvwprintw(menuwin, 1, 0, menu);
#ifdef CONFIG_SHOW_DATE_TIME
print_time_and_date();
#endif
}
static void center(int row, const char *str)
{
int j, len = strlen(str);
wmove(stdscr, row, 0);
for (j = 0; j < SCREEN_X; j++)
waddch(stdscr, ' ');
mvprintw(row, (SCREEN_X - len) / 2, str);
}
/* FIXME: Currently unused. */
#if 0
static void header(int row, const char *str)
{
char buf[SCREEN_X];
char *ptr = buf;
int i;
int len = strlen(str) + 4;
for (i = 0; i < (SCREEN_X - len) / 2; i++)
ptr += sprintf(ptr, "=");
ptr += sprintf(ptr, "[ %s ]", str);
for (i = ((SCREEN_X - len) / 2) + len; i < SCREEN_X; i++)
ptr += sprintf(ptr, "=");
mvprintw(row, 0, buf);
}
#endif
static void redraw_module(struct coreinfo_cat *cat)
{
if (cat->count == 0)
return;
wclear(modwin);
cat->modules[cat->cur]->redraw(modwin);
wrefresh(modwin);
}
static void handle_category_key(struct coreinfo_cat *cat, int key)
{
if (key >= 'a' && key <= 'z') {
int index = key - 'a';
if (index < cat->count) {
cat->cur = index;
redraw_module(cat);
return;
}
}
if (cat->count && cat->modules[cat->cur]->handle) {
if (cat->modules[cat->cur]->handle(key))
redraw_module(cat);
}
}
static void loop(void)
{
int key;
center(0, CONFIG_PAYLOAD_INFO_NAME " " CONFIG_PAYLOAD_INFO_VERSION);
refresh();
print_menu();
print_submenu(&categories[curwin]);
redraw_module(&categories[curwin]);
halfdelay(10);
while (1) {
#ifdef CONFIG_SHOW_DATE_TIME
print_time_and_date();
wrefresh(menuwin);
#endif
key = getch();
if (key == ERR)
continue;
if (key >= KEY_F(1) && key <= KEY_F(9)) {
unsigned char ch = key - KEY_F(1);
if (ch <= ARRAY_SIZE(categories)) {
if (ch == ARRAY_SIZE(categories))
continue;
if (categories[ch].count == 0)
continue;
curwin = ch;
print_submenu(&categories[curwin]);
redraw_module(&categories[curwin]);
continue;
}
}
if (key == KEY_ESC)
return;
handle_category_key(&categories[curwin], key);
}
}
int main(void)
{
int i, j;
initscr();
init_pair(1, COLOR_WHITE, COLOR_GREEN);
init_pair(2, COLOR_BLACK, COLOR_WHITE);
init_pair(3, COLOR_WHITE, COLOR_WHITE);
modwin = newwin(SCREEN_Y - 3, SCREEN_X, 1, 0);
menuwin = newwin(2, SCREEN_X, SCREEN_Y - 2, 0);
wattrset(stdscr, COLOR_PAIR(1) | A_BOLD);
wattrset(modwin, COLOR_PAIR(2));
wattrset(menuwin, COLOR_PAIR(1) | A_BOLD);
werase(modwin);
for (i = 0; i < ARRAY_SIZE(categories); i++) {
for (j = 0; j < categories[i].count; j++)
categories[i].modules[j]->init();
}
loop();
return 0;
}
PAYLOAD_INFO(name, CONFIG_PAYLOAD_INFO_NAME);
PAYLOAD_INFO(listname, CONFIG_PAYLOAD_INFO_LISTNAME);
PAYLOAD_INFO(desc, CONFIG_PAYLOAD_INFO_DESC);

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