mb/system76/rpl: gaze18, serw13: Fix USB2 on USB-C port

Use USB2_PORT_MID instead of USB2_PORT_TYPE_C, as was done for addw3.

Change-Id: I7df2bbf1ba70c4e08319b760b2784e15c880a105
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -8,6 +8,9 @@
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS
+--ignore PREFER_ALIGNED
+--ignore PREFER_PACKED
+--ignore PREFER_PRINTF
 --ignore SPLIT_STRING
 --ignore BLOCK_COMMENT_STYLE
 --ignore AVOID_EXTERNS

.clang-format

@@ -1,228 +1,21 @@
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-#   https://clang-format-configurator.site/
+ContinuationIndentWidth:			8
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-
+AlwaysBreakBeforeMultilineStrings:		true
----
+AllowShortLoopsOnASingleLine:			false
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-...
-

.editorconfig

@@ -9,7 +9,3 @@ charset = utf-8
 insert_final_newline = true
 end_of_line = lf
 trim_trailing_whitespace = true
-
-[*.sh]
-indent_style = space
-indent_size = 2

.gitignore

@@ -9,7 +9,6 @@ defconfig
 build/
 coreboot-builds/
 coreboot-builds*/
-generated/
 
 site-local
 

.gitmodules

@@ -1,70 +1,67 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk
-[submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
-	path = src/vendorcode/amd/opensil/genoa_poc/opensil
-	url = ../opensil_genoa_poc.git

.gitreview

@@ -2,4 +2,4 @@
 host=review.coreboot.org
 port=29418
 project=coreboot
-defaultbranch=main
+defaultbranch=master

AUTHORS

@@ -10,212 +10,73 @@
 
 3mdeb Embedded Systems Consulting
 9elements Agency GmbH
-Aamir Bohra
-Aaron Durbin
-Abe Levkoy
-Abel Briggs
 Abhinav Hardikar
-AdaCore
-Adam Liu
-Adam Mills
 Advanced Computing Lab, LANL
 Advanced Micro Devices, Inc.
+AdaCore
 AG Electronics Ltd.
-Ahamed Husni
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-Al Hirani
-Alan Huang
-AlanKY Lee
-Alec Wang
-Alex James
-Alex Levin
-Alex Miao
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-Alex1 Kao
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-Andrew McRae
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-Andrey Pronin
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-Andy Pont
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-Ben McMillen
-Ben Zhang
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-Bhanu Prakash Maiya
 Bill Xie
-Bin Meng
 Bitland Tech Inc.
-Bob Moragues
-Bora Guvendik
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-Brandon Breitenstein
-Brian Norris
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 Cavium Inc.
-Chao Gui
-Chen-Tsung Hsieh
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-Chien-Chih Tseng
-Chris Wang
-Christian Gmeiner
-Christian Walter
 Christoph Grenz
-Christopher Meis
-Chuangwei Technology Co., Ltd
-Chun-Jie Chen
-Cirrus Logic, Inc.
-CK HU
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 Code Aurora Forum
-Compal Electronics, Inc.
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-CoolStar
 coresystems GmbH
 Corey Osgood
 Curt Brune
-Curtis Chen
 Custom Ideas
-Cyberus Technology GmbH
-Da Lao
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-Daniel Campello
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 Dave Airlie
 David Brownell
 David Greenman
 David Hendricks
-David Lin
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 David Mueller
 David S. Peterson
-David Wu
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-Deepti Deshatty
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 Denis Dowling
 DENX Software Engineering
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 Digital Design Corporation
-Dinesh Gehlot
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-Dmitry Ponamorev
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 DMP Electronics Inc.
-Dominik Behr
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-Dtrain Hsu
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 Dynon Avionics
-Ed Sharma
-Eddy Lu
-Edward Hill
 Edward O'Callaghan
-Edward-JW Yang
 Egbert Eich
-Elias Souza
-Eloy Degen
 ELSOFT AG
 Eltan B.V
-Eltan B.V.
 Elyes Haouas
-Eran Mitrani
 Eric Biederman
-Eric Lai
-Eric Peers
-EricKY Cheng
-EricR Lai
-Erik van den Bogaert
 Eswar Nallusamy
-Ethan Tsao
-Eugene Myers
-Evan Green
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-Fabian Groffen
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-Fabio Aiuto
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 Facebook, Inc.
-Felix Friedlander
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 Free Software Foundation, Inc.
 Freescale Semiconductor, Inc.
-Furquan Shaikh
-Gaggery Tsai
-Gang C Chen 
-Garmin Chang
 Gary Jennejohn
 George Trudeau
 Gerald Van Baren
@@ -223,563 +84,164 @@ Gerd Hoffmann
 Gergely Kiss
 Google LLC
 Greg Watson
-Grzegorz Bernacki
 Guennadi Liakhovetski
-Guodong Liu
-Gwendal Grignou
 Hal Martin
-Hao Chou
-Hao Wang
 HardenedLinux
-Harsha B R
-Harshit Sharma
-Henry C Chen
-Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
-Himanshu Sahdev
+Hewlett Packard Enterprise Development LP
-Housong Zhang
-Hsiao Chien Sung
-Hsin-hsiung wang
-Hsin-Te Yuan
-Hsuan Ting Chen
-Huaqin Technology Co., Ltd
 Huaqin Telecom Inc.
-Hui Liu
-Huijuan Xie
-Hung-Te Lin
-Ian Douglas Scott
-Ian Feng
 IBM Corporation
 Idwer Vollering
-Igor Bagnucki
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-Ikjoon Jang
 Imagination Technologies
 Infineon Technologies
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-INSPUR Co., Ltd
 Intel Corporation
-Inventec Corp
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-Isaac Lee
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-Ivan Chen
 Ivan Vatlin
-Ivy Jian
-Jack Rosenthal
-Jacob Garber
-Jairaj Arava
-Jakub Czapiga
-James Chao
-James Lo
 James Ye
-Jamie Chen
-Jamie Ryu
-Jan Dabros
-Jan Samek
-Jan Tatje
-Jason Glenesk
-Jason Nein
-Jason V Le
-Jason Z Chen
 Jason Zhao
-jason-ch chen
-Jason-jh Lin
-Jay Patel
-Jeff Chase
-Jeff Daly
-Jeff Li
-Jérémy Compostella
-Jeremy Soller
-Jes Klinke
-Jesper Lin
-Jessy Jiang
-Jett Rink
-Jg Daolongzhu
-Jian Tong
-Jianeng Ceng
-Jianjun Wang
-Jim Lai
-Jimmy Su
-Jincheng Li
-Jingle Hsu
-Jitao Shi
 Joe Pillow
-Joe Tessler
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-Joey Peng
 Johanna Schander
-John Su
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-johnson wang
-Jon Murphy
 Jonas 'Sortie' Termansen
-Jonas Loeffelholz
 Jonathan A. Kollasch
 Jonathan Neuschäfer
-Jonathan Zhang
-Jonathon Hall
 Jordan Crouse
 Jörg Mische
 Joseph Smith
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-Karthik Ramasubramanian
 Keith Hui
 Keith Packard
-Kenneth Chan
-Kevin Chang
-Kevin Cheng
-Kevin Chiu
-Kevin Chowski
 Kevin Cody-Little
-Kevin Keijzer
 Kevin O'Connor
-Kevin3 Yang
-kewei xu
-Kilari Raasi
-Kirk Wang
-Konrad Adamczyk
 Kontron Europe GmbH
-Kornel Dulęba
-Krishna P Bhat D
-Krystian Hebel
 Kshitij
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-Lawrence Chang
 Leah Rowe
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-linear
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-Magf
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 Marvell Semiconductor Inc.
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-mgabryelski1
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+Michael Niewöhner
-Michael Walle
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 Mika Westerberg
-Mike Banon
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-Pratikkumar Prajapati
-Pratikkumar V Prajapati
 Protectli
 Purism SPC
-Purism, SPC
+Qualcomm Technologies
-Qii Wang
-Qualcomm Technologies, Inc.
-Quanta Computer INC
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 Raptor Engineering, LLC
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-Ravi Mistry
-Ravindra
-Ravishankar Sarawadi
-Ray Han Lim Ng
-Raymond Chung
 Red Hat, Inc
-ReddestDream
-Rehan Ghori
 Reinhard Meyer
-Reka Norman
-Ren Kuo
 Renze Nicolai
-Reto Buerki
-Rex Chou
-Rex-BC Chen
-Ricardo Quesada
-Ricardo Ribalda
 Richard Spiegel
 Richard Woodruff
-Rick Lee
-Ricky Chang
-Riku Viitanen
-Ritul Guru
-Rizwan Qureshi
-Rnhmjoj
-Rob Barnes
 Rob Landley
-Robert Chen
 Robert Reeves
-Robert Zieba
 Robinson P. Tryon
 Rockchip, Inc.
-Rocky Phagura
-Roger Lu
-Roja Rani Yarubandi
 Romain Lievin
 Roman Zippel
-Ron Lee
-Ron Minnich
-Ronak Kanabar
 Ronald G. Minnich
-Rory Liu
 Rudolf Marek
-Rui Zhou
-Ruihai Zhou
-Runyang Chen
 Russell King
 Ruud Schramp
-Ruwen Liu
-Ryan Chuang
-Ryan Lin
 Sage Electronic Engineering, LLC
-Sajida Bhanu
-Sam Lewis
-Sam McNally
 Sam Ravnborg
 Samsung Electronics
 Samuel Holland
-Sandeep Maheswaram
-Sathya Prakash M R
-Satya Priya Kakitapalli
-Saurabh Mishra
 SciTech Software, Inc.
-Scott Chao
+Sebastian Grzywna
-SDC Systems Ltd
-Sean Rhodes
-Sebastian 'Swift Geek' Grzywna
 secunet Security Networks AG
-Selma Bensaid
-Semihalf
-Sen Chu
 Sencore Inc
 Sergej Ivanov
-Sergii Dmytruk
-Serin Yeh
-Seven Lee
-SH Kim
-Shahina Shaik
-Shaocheng Wang
-Shaoming Chen
-Shaunak Saha
-Shelley Chen
-Shelly Chang
-Sheng-Liang Pan
-Shiyu Sun
-Shon Wang
-Shou-Chieh Hsu
-Shreesh Chhabbi
-Shuo Liu
 Siemens AG
 SiFive, Inc
-Silicom Ltd.
 Silicon Integrated System Corporation
 Silverback Ltd.
-Simon Glass
-Simon Yang
-Simon Zhou
-Sindhoor Tilak
-Solomon Alan-Dei
-Song Fan
-Sridhar Siricilla
-Srinidhi N Kaushik
-Srinivasa Rao Mandadapu
-ST Microelectronics
-Stanley Wu
-Star Labs Online Ltd
-Stefan Binding
-Stefan Ott
 Stefan Reinauer
 Stefan Tauner
-Stephen Edworthy
 Steve Magnani
 Steve Shenton
-Subrata Banik
+ST Microelectronics
-Sudheer Amrabadi
-Sugnan Prabhu S
-Sukumar Ghorai
-Sumeet R Pawnikar
-Sunwei Li
 SUSE LINUX AG
 Sven Schnelle
 Syed Mohammed Khasim
-System76, Inc.
+System76
-szarpaj
-T Michael Turney
-TangYiwei
-Taniya Das
-Tao Xia
-Tarun Tuli
-Teddy Shih
-Terry Chen
 Texas Instruments
 The Android Open Source Project
 The ChromiumOS Authors
 The Linux Foundation
 The Regents of the University of California
-Thejaswani Putta
-Thomas Heijligen
 Thomas Winischhofer
-Tim Chen
-Tim Chu
-Tim Crawford
-Tim Van Patten
-Tim Wawrzynczak
-Timofey Komarov
 Timothy Pearson
-tinghan shen
 Tobias Diedrich
-Tom Hiller
-Tommie Lin
-Tony Huang
-Tracy Wu
-Trevor Wu
 Tristan Corrick
 Tungsten Graphics, Inc.
 Tyan Computer Corp.
-Tyler Wang
-Tzung-Bi Shih
-U.S. National Security Agency
 ucRobotics Inc.
-Uday Bhat
 University of Heidelberg
-Usha P
 Uwe Hermann
-Uwe Poeche
-V Sowmya
-Václav Straka
-Vadim Bendebury
-Van Chen
-Varshit B Pandya
-Veerabhadrarao Badiganti
-Venkat Thogaru
-Venkata Krishna Nimmagadda
 VIA Technologies, Inc
-Victor Ding
-Vidya Gopalakrishnan
 Vikram Narayanan
-Vikrant L Jadeja
-Vinod Polimera
 Vipin Kumar
-Vitaly Rodionov
 Vladimir Serbinenko
 Vlado Cibic
-Vsujithk
 Wang Qing Pei
-Wanghao11
 Ward Vandewege
-Wayne Wang
-Weimin Wu
-Weiyi Lu
-Wenbin Mei
-Wentao Qin
-Werner Zeh
 Wilbert Duijvenvoorde
-William Wei
-Wilson Chou
-Wim Vervoorn
 Win Enterprises
-Wisley Chen
-Wistron Corp
 Wiwynn Corp.
-Wiwynn Corporation
-Wizard Shen
-Wojciech Macek
 Wolfgang Denk
-Won Chung
-Wonkyu Kim
-Wuxy 
-Xin Ji
-Xixi Chen
-Xuxin Xiong
 YADRO
-Yan Liu
 Yann Collet
-Yaroslav Kurlaev
-YH Lin
-Yidi Lin
-Yilin Yang
 Yinghai Lu
-Yolk Shih
-Yong Zhi
-Yongkun Yu
-Yongqiang Niu
-Yu-hsuan Hsu
-Yu-Ping Wu
-Yuanliding
-Yuchen He
-Yuchen Huang
-Yunlong Jia
 Zachary Yedidia
-Zanxi Chen
-Zhanyong Wang
-Zheng Bao
-Zhenguo Li
-Zhi7 Li
-Zhiqiang Ma
-Zhixing Ma
-Zhiyong Tao
-zhongtian wu
-Zhuohao Lee
-Ziang Wang
-Zoey Wu
-Zoltan Baldaszti
-小田喜陽彦
-陳建宏

Documentation/Makefile

@@ -4,21 +4,47 @@
 # hacked together by Stefan Reinauer <stepan@openbios.org>
 #
 
-BUILDDIR ?= _build
+PDFLATEX=pdflatex -t a4
-SPHINXOPTS ?= -j auto
 
-export SPHINXOPTS
+FIGS=codeflow.pdf hypertransport.pdf
 
-all: sphinx
+all: corebootPortingGuide.pdf
 
-$(BUILDDIR):
+SVG2PDF=$(shell which svg2pdf)
-	mkdir -p $(BUILDDIR)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
 
-sphinx: $(BUILDDIR)
+codeflow.pdf: codeflow.svg
-	$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
+ifneq ($(strip $(SVG2PDF)),)
+	svg2pdf $< $@
+else ifneq ($(strip $(INKSCAPE)),)
+	inkscape $< --export-pdf=$@
+else ifneq ($(strip $(CONVERT)),)
+	convert $< $@
+endif
+
+hypertransport.pdf: hypertransport.svg
+ifneq ($(strip $(SVG2PDF)),)
+	svg2pdf $< $@
+else ifneq ($(strip $(INKSCAPE)),)
+	inkscape $< --export-pdf=$@
+else ifneq ($(strip $(CONVERT)),)
+	convert $< $@
+endif
+
+corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
+	# 2 times to make sure we have a current toc.
+	$(PDFLATEX) corebootBuildingGuide.tex
+	$(PDFLATEX) corebootBuildingGuide.tex
+
+corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
+	$(PDFLATEX) corebootBuildingGuide.tex
+
+sphinx:
+	$(MAKE) -f Makefile.sphinx html
 
 clean-sphinx:
-	$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx clean
 
 clean: clean-sphinx
 	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -26,25 +52,5 @@ clean: clean-sphinx
 distclean: clean
 	rm -f corebootPortingGuide.pdf
 
-livesphinx: $(BUILDDIR)
+livesphinx:
-	$(MAKE) -f Makefile.sphinx livehtml BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"
-
-test:
-	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
-
-help:
-	@echo "all            - Builds all documentation targets"
-	@echo "sphinx         - Builds html documentation in _build directory"
-	@echo "clean          - Cleans intermediate files"
-	@echo "clean-sphinx   - Removes sphinx output files"
-	@echo "distclean      - Removes PDF files as well"
-	@echo "test           - Runs documentation tests"
-	@echo
-	@echo "  Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
-	@echo
-	@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
-
-.phony: help livesphinx sphinx test
-.phony: distclean clean clean-sphinx

Documentation/acpi/index.md

@@ -10,13 +10,3 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
-
-## Windows-specific ACPI documentation
-
-- [Windows-specific documentation](windows.md)
-
-##  ACPI specification - Useful links
-
-- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)

Documentation/acpi/windows.md

@@ -1,9 +0,0 @@
-# Testing ACPI changes under Windows
-
-When testing ACPI changes in coreboot against Windows 8 or newer, beware that
-during a normal boot after a clean shutdown, Windows will use the fast startup
-mechanism which results in it not evaluating the changed ACPI code but instead
-using some cached version which won't include the changes that were supposed to
-be tested. In order for Windows to actually use the new ACPI tables, either
-disable the fast startup or just tell Windows to do a reboot which will make it
-read and use the ACPI tables in memory instead of an outdated cached version.

Documentation/acronyms.md

@@ -1,5 +1,7 @@
 # Firmware and Computer Acronyms, Initialisms and Definitions
 
+** Note that this document even more of a work in progress than most **
+** of the coreboot documentation **
 
 ## _0-9
 
@@ -18,25 +20,24 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   initialization that happens from the PSP.  Significantly, Memory
   Initialization.
 * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
-* Ack - Acknowledgment / Acknowledged
+* Ack - Acknowledgment
 * ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
 * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)
 * ACPI - The [**Advanced Configuration and Power
   Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
   is an industry standard for letting the OS control power management.
-  * [https://uefi.org/specifications](https://uefi.org/specifications)
+  * [http://www.acpi.info/](http://www.acpi.info/)
   * [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
 * ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
 * ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
 * AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)
-* AESKL - Intel: AES Key Locker
 * AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
 * AGP - The [**Accelerated Graphics
-  Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
+  Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
   older (1997-2004) point-to-point bus for video cards to communicate
   with the processor.
 * AHCI - The [**Advanced Host Controller
-  Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
+  Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
   is a standard register set for communicating with a SATA controller.
   * [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
   * [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
@@ -50,11 +51,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   An open standard to connect and manage functional blocks in an SoC
   (System on a Chip)
 * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
-* AMD-Vi AMD: The AMD name for their IOMMU implementation
 * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
   SBI: Sideband Interface
 * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
-* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute)
+* ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
 * AOAC - AMD: Always On, Always Connected
 * AP - Application processor - The main processor on the board (as
   opposed to the embedded controller or other processors that may be on
@@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * APCB - AMD: AMD PSP Customization Block
 * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
 * APIC - [**Advanced Programmable Interrupt
-  Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
+  Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
   this is an advanced version of a PIC that can handle interrupts from
   and for multiple CPUs. Modern systems usually have several APICs:
   Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
@@ -90,7 +90,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ASPM - PCI: [**Active State Power
   Management**](https://en.wikipedia.org/wiki/Active_State_Power_Management)
 * ATA - [**Advanced Technology Attachment**](https://en.wikipedia.org/wiki/Parallel_ATA)
-* ATS - PCIe: Address Translation Services
 * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI)
 * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX)
 * AVX -  [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions)
@@ -98,7 +97,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## B
 
-* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
+* BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
   base address registers in the PCI config space of a PCI device
 * Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
   after Émile Baudot
@@ -117,7 +116,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   the entire 4GiB of the 32-bit address space. Also known as flat mode
   or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
 * BIOS - [**Basic Input/Output
-  System**](https://en.wikipedia.org/wiki/BIOS)
+  System**](http://en.wikipedia.org/wiki/BIOS)
 * BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
   itself when it is first started. Usually, any nonzero value indicates
   that the selftest failed.
@@ -183,7 +182,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   generally used to describe a section of NVRAM (Non-volatile RAM), in
   this case a section battery-backed memory in the RTC (Real Time Clock)
   that is typically used to store BIOS settings.
-  *[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
+  *[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
 * CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
 * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
 * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
@@ -191,14 +190,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CPPC - AMD: Collaborative Processor Performance Controls
 * CPS - Characters Per Second
 * CPU - [**Central Processing
-  Unit**](https://en.wikipedia.org/wiki/Central_processing_unit)
+  Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
 * CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
 * Cr50 - Google: The first generation Google Security Chip (GSC) used on
   ChromeOS devices.
 * CRB - Customer Reference Board
 * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
   (End-of-Line) marker.
-* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
+* crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
 * crt0s - crt0 Source code
 * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
 * CSE - Intel: Converged Security Engine
@@ -207,7 +206,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CSME - Intel: Converged Security and Management Engine
 * CTLE - Intel: Continuous Time Linear Equalization
 * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
-* CXMT - ChangXin Memory Technologies
 * CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
 
 
@@ -226,9 +224,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   still has power.
 * D3 Cold - ACPI Device power state: Power is completely removed from
   the device.
-* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware)
+* DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
 * DB - DaughterBoard
-* DbC - USB: Debug Capability on the USB host controller
 * DC - Electricity: Direct Current
 * DCP - Digital Content Protection
 * DCR - **Decode Control Register** This is a way of identifying the
@@ -237,14 +234,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DDI -  Intel: Digital Display Interface
 * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
 * DEVAPC - Mediatek: Device Access Permission Control
-* DF - Data Fabric
 * DFP - USB: Downstream Facing port
 * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
 * DID - Device Identifier
 * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
 * DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
 * DMA - [**Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows
+  Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
   certain hardware subsystems within a computer to access system memory
   for reading and/or writing independently of the main CPU. Examples of
   systems that use DMA: Hard Disk Controller, Disk Drive Controller,
@@ -252,7 +248,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   computers, as it allows devices of different speeds to communicate
   without subjecting the CPU to a massive interrupt load.
 * DMI - Direct Media Interface is a link/bus between CPU and PCH.
-* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface)
+* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
 * DMIC - Digital Microphone
 * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
 * DMZ - Demilitarized Zone
@@ -261,7 +257,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DOS - Disk Operating System
 * DP - DisplayPort
 * DPM - Mediatek: DRAM Power Manager
-* DPTC - AMD: Dynamic Power and Thermal Control
 * DPTF - Intel: Dynamic Power and Thermal Framework
 * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
 * DRTM - Dynamic Root of Trust for Measurement
@@ -287,8 +282,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
   vs Integrated TPMs or fTPMs (Firmware TPMs).
 * DTS - U-Boot: Device Tree Source
-* DUT - Device Under Test
-* DvC - USB: Debug Capability on the USB Device (Device Capability)
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
@@ -301,13 +294,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## E
 
-* EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd-audio-eapd/)
 * EBDA - Extended BIOS Data Area
-* EBG - Intel: Emmitsburg PCH
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* EDK2 - EFI Development Kit 2
+* edk2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was
@@ -317,7 +308,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
   electrical erasable programmable ROM).
 * EFI - [**Extensible Firmware Interface**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface)
-* EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process.
 * EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29#EHCI) - USB 2.0
 * EHL - Intel: [**Elkhart Lake**](https://en.wikichip.org/wiki/intel/cores/elkhart_lake)
 * EIDE - Enhanced Integrated Drive Electronics
@@ -329,7 +319,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EOL - End of Life
 * EPP - Intel: Energy-Performance Preference
 * EPROM - Erasable Programmable Read-Only Memory
-* EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS)
 * ESD - Electrostatic discharge
 * eSPI - Enhanced System Peripheral Interface
 * EVT - Production Timeline: Engineering Validation Test
@@ -340,7 +329,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FADT - ACPI Table: Fixed ACPI Description Table
 * FAE - Field Application Engineer
 * FAT - File Allocation Table
-* FBVDDQ - Nvidia Power: Framebuffer Voltage
 * FCH - AMD: Firmware Control Hub
 * FCS - Production Timeline: First Customer Shipment
 * FDD - Floppy Disk Drive
@@ -358,7 +346,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPDT - ACPI: Firmware Performance Data Table
 * FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
 * Framebuffer - The
-  [**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part
+  [**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
   of RAM in a computer which is allocated to hold the graphics
   information for one frame or picture. This information typically
   consists of color values for every pixel on the screen. A framebuffer
@@ -370,15 +358,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990.
 * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
-* FSM - Finite State Machine
 * FSP - Intel: Firmware Support Package
-* FSR - Intel: Firmware Status Register
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
 * fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
   based in firmware instead of actual hardware.  It typically runs in
   some sort of TEE (Trusted Execution Environment).
-* FWCM Intel: firmware Connection Manager
-* FWID - Firmware Identifier
 
 
 ## G
@@ -399,10 +383,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GMA - Intel: [**Graphics Media
   Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
 * GNB - Graphics NorthBridge
-* GND - Power: Ground
 * GNVS - Global Non-Volatile Storage
 * GPD - PCH GPIO in Deep Sleep well (D5 power)
-* GPE - ACPI: General Purpose Event
 * GPI - GPIOs: GPIO Input
 * GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_Input/Output) (Pin)
 * GPMR - Intel: General Purpose Memory Range
@@ -414,30 +396,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GPU - [**Graphics Processing Unit**](https://en.wikipedia.org/wiki/Graphics_processing_unit)
 * GSoC - [**Google Summer of Code**](https://en.wikipedia.org/wiki/Google_Summer_of_Code)
 * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
-* GSPI - Generic SPI - These are SPI controllers available for general
-  use, not dedicated to flash, for example.
-* GTDT - ACPI: Generic Timer Description Table
-* GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
 * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
 
 
 ## H
 
-* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline
 * HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio)
 * HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection)
 * HDD - Hard Disk Drive
 * HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI)
 * HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range)
 * HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI)
-* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline.
 * HID - [**Human Interface
   Device**](https://en.wikipedia.org/wiki/Human_interface_device)
 * HOB - UEFI: Hand-Off Block
-* HPD - Hot-Plug Detect
 * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
-* HSP - AMD: Hardware Security Processor
-* HSPHY - USB: USB3 High-Speed PHY
 * HSTI - Hardware Security Test Interface
 * HSW - Intel: Haswell
 * Hybrid S3 - System Power State:  This is where the operating system
@@ -446,7 +419,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   resume quickly from S3 if the system stays powered, and resume from
   the disk if power is lost.
 * Hypertransport - AMD: The
-  [**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus
+  [**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
   is an older (2001-2017) high-speed electrical interconnection protocol
   specification between CPU, Memory, and (occasionally) peripheral
   devices.  This was originally called the Lightning Data Transport
@@ -467,7 +440,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   - Also known as SenseWire
 * IA - Intel Architecture
 * IA-64 - Intel Itanium 64-bit architecture
-* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions
 * IBB – Initial Boot Block
 * IBV - Independent BIOS Vendor
 * IC - Integrated Circuit
@@ -484,8 +456,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IF - AMD: [**Infinity
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
-* IFD - Intel: Intel Flash Descriptor
-* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions
 * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
   into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
   This never worked well for anything beyond fan control and caused
@@ -497,7 +467,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IoC - Security: Indicator of Compromise
 * IOC - Intel: I/O Cache
 * IOE - Intel: I/O Expander
-* IOHC - AMD: I/O Hub Controller
 * IOM - Intel: I/O Manager
 * IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit)
 * IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
@@ -520,7 +489,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IVHD - ACPI: I/O Virtualization Hardware Definition
 * IVMD - ACPI: I/O Virtualization Memory Definition
 * IVRS - I/O Virtualization Reporting Structure
-* IWYU - Include What you Use - A tool to help with include file use
 
 
 ## J
@@ -561,7 +529,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * LAPIC - Local APIC
 * LBA - Logical Block Address
 * LCD - Liquid Crystal Display
-* LCAP - PCIe: Link Capabilities
+* LCAP - PCIe:Link Capabilities
 * LED - Light Emitting Diode
 * LF - Line Feed - The standard Unix EOL (End-of-Line) marker.
 * LGTM - Looks Good To Me
@@ -574,7 +542,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   count**](http://www.intel.com/design/chipsets/industry/lpc.htm) bus
   was a replacement for the ISA bus, created by serializing a number of
   parallel signals to get rid of those connections.
-* LPM - USB: Link Power Management
 * LPT - Line Print Terminal, Local Print Terminal, or Line Printer. -
   The Parallel Port
 * LRU - Least Recently Used - a rule used in operating systems that
@@ -591,21 +558,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * M.2 - An interface specification for small peripheral cards.
 * MAC Address - Media Access Control Address
-* MAFS - (eSPI) Master Attached Flash Sharing: Flash components are
-  attached to the controller device and may be accessed by by the
-  peripheral devices through the eSPI flash access channel.
-* MBP - Intel UEFI: ME-to-BIOS Payload
 * MBR - Master Boot Record
 * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
 * MCR - Machine Check Registers
-* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MCU - Memory Control Unit
 * MCU - [**MicroController
   Unit**](https://en.wikipedia.org/wiki/Microcontroller)
-* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization.
+* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MDFIO - Intel: Multi-Die Fabric IO
 * MDN - AMD: Mendocino
-* mDP - Mini DisplayPort connector
 * ME - Intel: Management Engine
 * MEI - Intel: ME Interface (Previously known as HECI)
 * Memory training - the process of finding the best speeds, voltages,
@@ -622,7 +583,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MKBP - Matrix Keyboard Protocol
 * MMC - [**MultiMedia
   Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
-* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO)
+* MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
   allows peripherals' memory or registers to be accessed directly
   through the memory bus.  When the memory bus size was very small, this
   was initially done by hiding any memory at that address, effectively
@@ -649,23 +610,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MSB - Most Significant Bit
 * MSI - Message Signaled Interrupt
 * MSR - Machine-Specific Register
-* MTS or MT/s - MegaTransfers per second
+* MT/s - MegaTransfers per second
 * MTL - Intel: Meteor Lake
 * MTL - ARM: MHU Transport Layer
-* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR)
+* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
   allows to set the cache behaviour on memory access in x86. Basically,
   it tells the CPU how to cache certain ranges of memory
   (e.g. write-through, write-combining, write-back...). Memory ranges
   are specified over physical address ranges. In Linux, they are visible
   over `/proc/mtrr` and they can be modified there. For further
   information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
-* MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module)
 
 
 ## N
 
 * Nack - Negative Acknowledgement
-* NB - North Bridge
 * NBCI - Nvidia: NoteBook Common Interface
 * NC - GPIOs: No Connect
 * NDA - Non-Disclosure Agreement.
@@ -685,7 +644,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * NVME - Non-Volatile Memory Express - An SSD interface that allows
   access to the flash memory through a PCIe bus.
 * NVPCF - Nvidia Platform and Control Framework
-* NVVDD - Nvidia Power: Core voltage
 * NX - No Execute
 
 
@@ -731,23 +689,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PCD - UEFI: Platform Configuration Database
 * PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
 * PCI - [**Peripheral Control
-  Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
+  Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
   - Replaced generally by PCIe (PCI Express)
 * PCI Configuration Space - The [**PCI Config
-  space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
+  space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
   [address space](https://en.wikipedia.org/wiki/Address_space) for all
   PCI devices.  Originally, this address space was accessed through an
   index/data pair by writing the address that you wanted to read/write
   into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
   This has been updated to an MMIO method which increases each PCI
   function's configuration space from 256 bytes to 4K.
-* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express)
+* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
 * PCMCIA: Personal Computer Memory Card International Association
 * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
 * PCR: TPM: Platform Configuration Register
-* PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor.
+* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage.  Setting it low drives it to ground through a resistor.
-  The resistor allows the pin to be set to the reference voltage as
-  needed.
 * PD - Power Delivery - This is a specification for communicating power
   needs and availability between two devices, typically over USB type C.
 * PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU
@@ -755,9 +711,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PEI - UEFI: Pre-EFI Initialization
 * PEIM - UEFI: PEI Module
 * PEP - Intel: Power Engine Plug-in
-* PEXVDD - Nvidia Power: PCIExpress Voltage
+* PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
-* PHX - AMD: Phoenix SoC
-* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The
   hardware that implements the send/receive functionality of a
   communication protocol.
 * PI - Platform Initialization
@@ -776,7 +730,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PIT - Generally refers to the 8253/8254 [**Programmable Interval
   Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
 * PLCC - [**Plastic leaded chip
-  carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
+  carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
 * PLL - [**Phase-Locked
   Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
 * PM - Platform Management
@@ -798,21 +752,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * POTS - [**Plain Old Telephone
   Service**](https://en.wikipedia.org/wiki/Plain_old_telephone_service)
 * PPI - UEFI: PEIM-to-PEIM Interface
-* PPR - Processor Programming Reference
+* PPR: Processor Programming Reference
 * PPT - AMD: Package Power Tracking
-* PROM - Programmable Read Only Memory
+* PROM: Programmable Read Only Memory
 * Proto - Production Timeline: The first initial production to test key
   concepts.
 * PSE - Page Size Extention
-* PSF - Intel: Primary Sideband Fabric
 * PSP - AMD: Platform Security Processor
 * PSPP - AMD: PCIE Speed Power Policy
-* PSR - Intel: Platform Service Record
+* PU - GPIOs: Pull-Up - Setting the pin low drives it to ground.  Setting it high drives it to the reference voltage through a resistor.
-* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP
-* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
-* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
-  resistor. The resistor allows the signal to still be set to ground
-  when needed.
 * PVT - Production Timeline: (Production Validation Test
 * PWM - Pulse Width Modulation
 * PXE - Pre-boot Execution Environment
@@ -835,7 +783,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be
   used.
 * RAPL - Running Average Power Limit
-* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions
 * RCS - [**Revision control
   system**](https://en.wikipedia.org/wiki/Revision_Control_System)
 * Real mode - The original 20-bit addressing mode of the 8086 & 8088
@@ -843,7 +790,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Segment:Offset index pair.  In 2022, this is still the mode that
   x86-64 processors are in at the reset vector!
 * RDMA - [**Remote Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
+  Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
   a concept whereby two or more computers communicate via DMA directly
   from main memory of one system to the main memory of another.
 * RFC - Request for Comment
@@ -856,11 +803,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ROM - Read Only Memory
 * RoT - Root of Trust
 * RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake)
-* RPP - Intel: Raptor Point PCH
 * RRG - AMD (ATI): Register Reference Guide
 * RSDP - Root System Description Pointer
 * RTC - Real Time Clock
-* RTD3 - Power State: Runtime D3
 * RTFM - Read the Fucking Manual
 * RTOS - Real-Time Operating System
 * RVP - Intel: Reference Validation Platform
@@ -896,11 +841,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   contents of memory.  Any critical processor state is restored.
 * S5 - ACPI System Power State: System is “completely powered off”, but
   still has power going to the board.
-* SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the
-  peripheral device.  Only valid for server platforms.
-* SAGV - Intel: System Agent Geyserville. The original internal name
-  for the feature eventually released as Speedstep which controls the
-  processor voltage and frequencies.
 * SAR - The [**Specific Absorption
   Rate**](https://en.wikipedia.org/wiki/Specific_absorption_rate) is the
   measurement for the amount of Radio Frequency (RF) energy absorbed by
@@ -924,7 +864,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   SAS (Serial Attached SCSI).  The initial version is now often referred
   to as Parallel SCSI.
 * SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card
-* SDHCI - SD Host Controller Interface
 * SDRAM - Synchronous DRAM
 * SDLE: AMD: Stardust Dynamic Load Emulator
 * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
@@ -948,7 +887,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SMBus -  [**System Management
   Bus**](https://en.wikipedia.org/wiki/System_Management_Bus)
   * [http://www.smbus.org/](http://www.smbus.org/)
-* SME - AMD: Secure Memory Encryption
 * SMI - System management interrupt
 * SMM - [**System management
   mode**](https://en.wikipedia.org/wiki/System_Management_Mode)
@@ -962,7 +900,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SO-DIMM: Small Outline Dual In-Line Memory Module
 * SoC - System on a Chip
 * SOIC - [**Small-Outline Integrated
-  Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
+  Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
 * SPD - [**Serial Presence
   Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
 * SPI - [**Serial Peripheral
@@ -970,7 +908,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SPL - AMD: Security Patch Level
 * SPM - Mediatek: System Power Manager
 * SPMI - MIPI: System Power Management Interface
-* SPR - Sapphire Rapids
 * SRAM - Static Random Access Memory
 * SSD - Solid State Drive
 * SSDT - Secondary System Descriptor Table - ACPI table
@@ -987,7 +924,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SSI-TEB - Physical board format: [**SSI Thin Electronics
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
 * SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
-* SSPHY - USB: USB3 Super-Speed PHY
 * STAPM - AMD: Skin Temperature Aware Power Management
 * STB - AMD: Smart Trace Buffer
 * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
@@ -995,16 +931,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   peripherals.  Most common are: A PS/2 Keyboard and mouse port, LPT
   Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any
   of a number of various other devices.
-* SVC - ARM: Supervisor Call
 * SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
-* SWCM - Intel: Software Connection Manager
 
 
 ## T
 
 * TBT - Thunderbolt
 * TBT - Intel: Turbo Boost Technology
-* tBUF - I2C: The bus free time between a STOP and START condition
 * TCC - Intel: Thermal Control Circuit
 * TCP - Transmission Control Protocol
 * TCPC - Type C Port Controller
@@ -1028,8 +961,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TOLUM - Top of Low Usable Memory
 * ToM - Top of Memory
 * TPM - Trusted Platform Module
-* TS - TimeStamp
+* TS - TimeStamp -
-* TSN - Time-Sensitive Networking
 * TSC - [**Time Stamp
   Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
 * TSEG - TOM (Top of Memory) Segment
@@ -1046,9 +978,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode)
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
-* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives
 * UEFI - Unified Extensible Firmware Interface
-* UFC - User Facing Camera
 * UFP - USB: Upstream Facing Port
 * UFS - Universal Flash storage
 * UHCI - USB: [**Universal Host Controller
@@ -1064,7 +994,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UPS - Uninterruptible Power Supply
 * USART - Universal Synchronous/Asynchronous Receiver/Transmitter
 * USB - Universal Serial Bus
-* USF - Intel: Universal Scalable Firmware
 
 
 ## V
@@ -1072,8 +1001,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VBIOS - Video BIOS
 * VBNV - Vboot Non-Volatile storage
 * VBT - [**Video BIOS
-  Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
+  Table**](https://01.org/linuxgraphics/gfx-docs/drm/ch04s02.html#id-1.4.3.4.16)
-* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip.
 * VESA - Video Electronics Standards Association
 * VGA: Video Graphics Array
 * VID: Vendor Identifier
@@ -1081,17 +1009,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VLB - VESA Local Bus
 * VOIP - Voice over IP
 * Voodoo mode - a silly name for Big Real mode.
-* VMX - Intel: CPU flag for Hardware Virtualization
 * VPD - Vital Product Data
 * VPN - Virtual Private Network
-* VPU - Intel: Versatile Processor Unit
 * VR - Voltage Regulator
 * VRAM - Video Random Access Memory
-* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ.
 * VRM - Voltage Regulator Module
 * VT-d - Intel: Virtualization Technology for Directed I/O
-* VTT Memory/Power: Tracking Termination Voltage
-* vUART - Virtual UART
 
 
 ## W
@@ -1105,11 +1028,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   devices that open 360 degrees, or on the outside of the cover.  For
   tablets, it's on the the side away from the screen.
 * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
-* WFC - World Facing Camera
 * WLAN - Wireless LAN (Local Area Network)
 * WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
-* WPT - Intel: Wildcat Point - PCH for Broadwell
 * WO - Write-only
 * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
 * WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
@@ -1130,9 +1051,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   supporting 1.x, 2.0, and 3.x devices.
 
 
-## Y
 
-* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video
+## Y
 
 
 ## Z

Documentation/community/code_of_conduct.md

@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
-## Legal action
-
-Threatening or starting legal action against the project, sibling
-projects hosted on coreboot.org infrastructure, project or infrastructure
-maintainers leads to an immediate ban from coreboot.org and related
-systems.
-
-The ban can be reconsidered, but it's the default action because the
-people who pour lots of time and money into the projects aren't interested
-in seeing their resources used against them.
-
 ## Scope
 
 We expect all community participants (contributors, paid or otherwise;

Documentation/community/forums.md

@@ -14,7 +14,7 @@ read its
 ## Real time chat
 
 We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
-also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
+also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
 [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
 [OSF Slack](https://osfw.slack.com/), which has channels on many open source
 firmware related topics. Slack requires that people come from specific domains

Documentation/conf.py

@@ -55,7 +55,7 @@ else:
 #
 # This is also used if you do content translation via gettext catalogs.
 # Usually you set "language" from the command line for these cases.
-language = 'en'
+language = None
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
@@ -87,13 +87,101 @@ html_theme = 'sphinx_rtd_theme'
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
 
-html_css_files = [
+html_context = {
-    'theme_overrides.css',  # override wide tables in RTD theme
+      'css_files': [
-]
+        '_static/theme_overrides.css',  # override wide tables in RTD theme
+      ],
+}
 
 # Output file base name for HTML help builder.
 htmlhelp_basename = 'corebootdoc'
 
+# -- Options for LaTeX output ---------------------------------------------
+
+latex_elements = {
+     # The paper size ('letterpaper' or 'a4paper').
+     #
+     # 'papersize': 'letterpaper',
+
+     # The font size ('10pt', '11pt' or '12pt').
+     #
+     # 'pointsize': '10pt',
+
+     # Additional stuff for the LaTeX preamble.
+     #
+     # 'preamble': '',
+
+     # Latex figure (float) alignment
+     #
+     # 'figure_align': 'htbp',
+}
+
+# Grouping the document tree into LaTeX files. List of tuples
+# (source start file, target name, title,
+#  author, documentclass [howto, manual, or own class]).
+latex_documents = [
+    (master_doc, 'coreboot.tex', u'coreboot Documentation',
+     u'the coreboot project', 'manual'),
+]
+
+# The name of an image file (relative to this directory) to place at the top of
+# the title page.
+#
+# latex_logo = None
+
+# For "manual" documents, if this is true, then toplevel headings are parts,
+# not chapters.
+#
+# latex_use_parts = False
+
+# If true, show page references after internal links.
+#
+# latex_show_pagerefs = False
+
+# If true, show URL addresses after external links.
+#
+# latex_show_urls = False
+
+# Documents to append as an appendix to all manuals.
+#
+# latex_appendices = []
+
+# If false, will not define \strong, \code,	itleref, \crossref ... but only
+# \sphinxstrong, ..., \sphinxtitleref, ... To help avoid clash with user added
+# packages.
+#
+# latex_keep_old_macro_names = True
+
+# If false, no module index is generated.
+#
+# latex_domain_indices = True
+
+
+# -- Options for manual page output ---------------------------------------
+
+# One entry per manual page. List of tuples
+# (source start file, name, description, authors, manual section).
+man_pages = [
+    (master_doc, 'coreboot', u'coreboot Documentation',
+     [author], 1)
+]
+
+# If true, show URL addresses after external links.
+#
+# man_show_urls = False
+
+
+# -- Options for Texinfo output -------------------------------------------
+
+# Grouping the document tree into Texinfo files. List of tuples
+# (source start file, target name, title, author,
+#  dir menu entry, description, category)
+texinfo_documents = [
+    (master_doc, 'coreboot', u'coreboot Documentation',
+     author, 'coreboot', 'One line description of project.',
+     'Miscellaneous'),
+]
+
 enable_auto_toc_tree = True
 
 class MyCommonMarkParser(CommonMarkParser):
@@ -103,6 +191,23 @@ class MyCommonMarkParser(CommonMarkParser):
         n = nodes.literal(mdnode.literal, mdnode.literal)
         self.current_node.append(n)
 
+# Documents to append as an appendix to all manuals.
+#
+# texinfo_appendices = []
+
+# If false, no module index is generated.
+#
+# texinfo_domain_indices = True
+
+# How to display URL addresses: 'footnote', 'no', or 'inline'.
+#
+# texinfo_show_urls = 'footnote'
+
+# If true, do not generate a @detailmenu in the "Top" node's menu.
+#
+# texinfo_no_detailmenu = False
+
+
 def setup(app):
     from recommonmark.transform import AutoStructify
     # Load recommonmark on old Sphinx

Documentation/contributing/coding_style.md

@@ -6,14 +6,14 @@ kernel coding style. In fact, most of this document has been copied from
 the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst)
 
 The guidelines in this file should be seen as a strong suggestion, and
-should overrule personal preference. They may be ignored in individual
+should overrule personal preference. But they may be ignored in
-instances when there are good practical reasons to do so, and reviewers
+individual instances when there are good practical reasons to do so, and
-are in agreement.
+reviewers are in agreement.
 
 Any style questions that are not mentioned in here should be decided
 between the author and reviewers on a case-by-case basis. When modifying
 existing files, authors should try to match the prevalent style in that
-file -- otherwise, they should generally match similar existing files in
+file -- otherwise, they should try to match similar existing files in
 coreboot.
 
 Bulk style changes to existing code ("cleanup patches") should avoid
@@ -24,8 +24,7 @@ be honored. (Note that `checkpatch.pl` is not part of this style guide,
 and neither is `clang-format`. These tools can be useful to find
 potential issues or simplify formatting in new submissions, but they
 were not designed to directly match this guide and may have false
-positives. They should not be bulk-applied to change existing code
+positives. They should not be bulk-applied to change existing code.)
-except in cases where they directly match the style guide.)
 
 ## Indentation
 
@@ -43,8 +42,7 @@ Now, some people will claim that having 8-character indentations makes
 the code move too far to the right, and makes it hard to read on a
 80-character terminal screen. The answer to that is that if you need
 more than 3 levels of indentation, you're screwed anyway, and should
-fix your program.  Note that coreboot has expanded the 80 character
+fix your program.
-limit to 96 characters to allow for modern wider screens.
 
 In short, 8-char indents make things easier to read, and have the added
 benefit of warning you when you're nesting your functions too deep.
@@ -89,9 +87,7 @@ Outside of comments, documentation and except in Kconfig, spaces are
 never used for indentation, and the above example is deliberately
 broken.
 
-Get a decent editor and don't leave whitespace at the end of lines. This
+Get a decent editor and don't leave whitespace at the end of lines.
-will actually keep the patch from being tested in the CI, so patches
-with ending whitespace cannot be merged.
 
 ## Breaking long lines and strings
 
@@ -507,14 +503,18 @@ comments to note or warn about something particularly clever (or ugly),
 but try to avoid excess. Instead, put the comments at the head of the
 function, telling people what it does, and possibly WHY it does it.
 
-coreboot style for comments is the C89 "/* ... */" style. You may also
+When commenting the kernel API functions, please use the kernel-doc
-use C99-style "// ..." comments for single-line comments.
+format. See the files Documentation/kernel-doc-nano-HOWTO.txt and
+scripts/kernel-doc for details.
+
+coreboot style for comments is the C89 "/* ... */" style. You may
+use C99-style "// ..." comments.
 
 The preferred style for *short* (multi-line) comments is:
 
 ```c
 /* This is the preferred style for short multi-line
-   comments in the coreboot source code.
+   comments in the Linux kernel source code.
    Please use it consistently. */
 ```
 
@@ -523,7 +523,7 @@ The preferred style for *long* (multi-line) comments is:
 ```c
 /*
  * This is the preferred style for multi-line
- * comments in the coreboot source code.
+ * comments in the Linux kernel source code.
  * Please use it consistently.
  *
  * Description:  A column of asterisks on the left side,
@@ -578,8 +578,7 @@ To do the latter, you can stick the following in your .emacs file:
 ```
 
 This will make emacs go better with the kernel coding style for C files
-below ~/src/linux-trees.  Obviously, this should be updated to match
+below ~/src/linux-trees.
-your own paths for coreboot.
 
 But even if you fail in getting emacs to do sane formatting, not
 everything is lost: use "indent".
@@ -627,6 +626,38 @@ config ADFS_FS_RW
 For full documentation on the configuration files, see the file
 Documentation/kbuild/kconfig-language.txt.
 
+Data structures
+---------------
+
+Data structures that have visibility outside the single-threaded
+environment they are created and destroyed in should always have
+reference counts. In the kernel, garbage collection doesn't exist (and
+outside the kernel garbage collection is slow and inefficient), which
+means that you absolutely _have_ to reference count all your uses.
+
+Reference counting means that you can avoid locking, and allows multiple
+users to have access to the data structure in parallel - and not having
+to worry about the structure suddenly going away from under them just
+because they slept or did something else for a while.
+
+Note that locking is _not_ a replacement for reference counting.
+Locking is used to keep data structures coherent, while reference
+counting is a memory management technique. Usually both are needed, and
+they are not to be confused with each other.
+
+Many data structures can indeed have two levels of reference counting,
+when there are users of different "classes". The subclass count counts
+the number of subclass users, and decrements the global count just once
+when the subclass count goes to zero.
+
+Examples of this kind of "multi-level-reference-counting" can be found
+in memory management ("struct mm_struct": mm_users and mm_count),
+and in filesystem code ("struct super_block": s_count and
+s_active).
+
+Remember: if another thread can find your data structure, and you don't
+have a reference count on it, you almost certainly have a bug.
+
 Macros, Enums and RTL
 ---------------------
 
@@ -696,19 +727,35 @@ The cpp manual deals with macros exhaustively. The gcc internals manual
 also covers RTL which is used frequently with assembly language in the
 kernel.
 
-Printing coreboot messages
+Printing kernel messages
 ------------------------
 
-coreboot developers like to be seen as literate. Do mind the spelling of
+Kernel developers like to be seen as literate. Do mind the spelling of
-coreboot messages to make a good impression. Do not use crippled words
+kernel messages to make a good impression. Do not use crippled words
 like "dont"; use "do not" or "don't" instead. Make the messages
 concise, clear, and unambiguous.
 
-coreboot messages do not have to be terminated with a period.
+Kernel messages do not have to be terminated with a period.
 
 Printing numbers in parentheses (%d) adds no value and should be
 avoided.
 
+There are a number of driver model diagnostic macros in
+<linux/device.h> which you should use to make sure messages are
+matched to the right device and driver, and are tagged with the right
+level: dev_err(), dev_warn(), dev_info(), and so forth. For messages
+that aren't associated with a particular device, <linux/printk.h>
+defines pr_debug() and pr_info().
+
+Coming up with good debugging messages can be quite a challenge; and
+once you have them, they can be a huge help for remote troubleshooting.
+Such messages should be compiled out when the DEBUG symbol is not
+defined (that is, by default they are not included). When you use
+dev_dbg() or pr_debug(), that's automatic. Many subsystems have
+Kconfig options to turn on -DDEBUG. A related convention uses
+VERBOSE_DEBUG to add dev_vdbg() messages to the ones already enabled
+by DEBUG.
+
 Allocating memory
 -----------------
 
@@ -745,7 +792,12 @@ The inline disease
 There appears to be a common misperception that gcc has a magic "make
 me faster" speedup option called "inline". While the use of inlines
 can be appropriate (for example as a means of replacing macros, see
-Chapter 12), it very often is not.
+Chapter 12), it very often is not. Abundant use of the inline keyword
+leads to a much bigger kernel, which in turn slows the system as a whole
+down, due to a bigger icache footprint for the CPU and simply because
+there is less memory available for the pagecache. Just think about it; a
+pagecache miss causes a disk seek, which easily takes 5 milliseconds.
+There are a LOT of cpu cycles that can go into these 5 milliseconds.
 
 A reasonable rule of thumb is to not put inline at functions that have
 more than 3 lines of code in them. An exception to this rule are the
@@ -808,7 +860,7 @@ eDP display panel encounters an I2C error, it should print a "cannot read EDID"
 message and return an error code. The calling display initialization function
 knows that without the EDID there is no way to initialize the display correctly,
 so it will also immediately return with an error code without running its
-remaining code that would initialize the SoC's display controller. Execution
+remaining code that would initialize the SoC's display controller. Exeuction
 returns further up the function stack to the mainboard initialization code
 which continues booting despite the failed display initialization, since
 display functionality is non-essential to the system. (Code is encouraged but
@@ -871,7 +923,7 @@ in the same directory that is not part of a normal include path gets included
 .c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks,
 including includes to other headers that don't follow that provision. Where a
 specific include order is required for technical reasons, it should be clearly
-documented with comments. This should not be the norm.
+documented with comments.
 
 Files should generally include every header they need a definition from
 directly (and not include any unnecessary extra headers). Excepted from
@@ -1006,29 +1058,6 @@ This rule only applies to explicit GCC extensions listed in the
 should never rely on incidental GCC translation behavior that is not
 explicitly documented as a feature and could change at any moment.
 
-Refactoring
------------
-Because refactoring existing code can add bugs to tested code, any
-refactors should be done only with serious consideration. Refactoring
-for style differences should only be done if the existing style
-conflicts with a documented coreboot guideline. If you believe that the
-style should be modified, the pros and cons can be discussed on the
-mailing list and in the coreboot leadership meeting.
-
-Similarly, the original author should be respected. Changing working
-code simply because of a stylistic disagreement is *prohibited*. This is
-not saying that refactors that are objectively better (simpler, faster,
-easier to understand) are not allowed, but there has to be a definite
-improvement, not simply stylistic changes.
-
-Basically, when refactoring code, there should be a clear benefit to
-the project and codebase. The reviewers and submitters get to make the
-call on how to interpret this.
-
-When refactoring, adding unit tests to verify that the post-change
-functionality matches or improves upon pre-change functionality is
-encouraged.
-
 References
 ----------
 

Documentation/contributing/gerrit_guidelines.md

@@ -9,7 +9,7 @@ friction in the community.
 
 Note that as with many rules, there are exceptions. Some have been noted
 in the 'More Detail' section. If you feel there is an exception not listed
-here, please discuss it in the mailing list to get this document updated.
+here, please discuss it in the mailing list to get this document  updated.
 Don't just assume that it's okay, even if someone on IRC says it is.
 
 
@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * In general, patches should remain open for review for at least 24 hours
 since the last significant modification to the change. The purpose is to
@@ -127,54 +127,6 @@ those platforms. While it would be nice to update any other platforms, you
 must at least provide a path that will allow other platforms to continue
 working.
 
-Sign-off Procedure
-------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
 
 Recommendations for gerrit activity
 -----------------------------------
@@ -221,10 +173,7 @@ This helps verify that the patch train won’t tie up the jenkins builders
 for no reason if there are failing patches in the train. For running
 parallel builds, you can specify the number of cores to use by setting the
 the CPUS environment variable. Example:
-
+        make what-jenkins-does CPUS=8
-```Bash
-make what-jenkins-does CPUS=8
-```
 
 * Use a topic when pushing a train of patches. This groups the commits
 together so people can easily see the connection at the top level of
@@ -232,10 +181,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
 commits with the i915-kernel-x60 set, use the command:
-
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```Bash
-git push origin HEAD:refs/for/main%topic=i915-kernel-x60
-```
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -245,10 +191,7 @@ Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
 isn't as obvious as the commit message. These patches can also be pushed with
 the wip flag:
-
+	git push origin HEAD:refs/for/master%wip
-```Bash
-git push origin HEAD:refs/for/main%wip
-```
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
@@ -257,16 +200,10 @@ sorts of patches are frequently posted as ideas or RFCs for the community to
 look at. Note that private changes can still be fetched from Gerrit by anybody
 who knows their commit ID, so don't use this for sensitive changes. To push
 a private change, use the command:
-
+        git push origin HEAD:refs/for/master%private
-```Bash
-git push origin HEAD:refs/for/main%private
-```
 
 * Multiple push options can be combined:
-
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```Bash
-git push origin HEAD:refs/for/main%private,wip,topic=experiment
-```
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -292,7 +229,7 @@ changed.
 helps others and shows that these mainboards are currently being
 maintained. At some point, boards that are not up to date in the
 board-status repo will probably end up getting removed from the coreboot
-main branch.
+master branch.
 
 * Abandon patches that are no longer useful, or that you don’t intend to
 keep working on to get submitted.
@@ -340,15 +277,13 @@ git/gerrit tags by prepending the lines with 'Original-'.  Marking
 the original text this way makes it much easier to tell what changes
 happened in which repository. This applies to these lines, not the actual
 commit message itself:
-
+        Commit-Id:
-	* Commit-Id:
+        Change-Id:
-	* Change-Id:
+        Signed-off-by:
-	* Signed-off-by:
+        Reviewed-on:
-	* Reviewed-on:
+        Tested-by:
-	* Tested-by:
+        Reviewed-by:
-	* Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
@@ -434,7 +369,3 @@ Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
 
 [ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes

Documentation/contributing/gsoc.md

@@ -1,16 +1,5 @@
 # Google Summer of Code
 
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
 
 ## Contacts
 
@@ -19,6 +8,9 @@ please have a look at our [community forums] and reach out to us. Working closel
 with the community is highly encouraged, as we've seen that our most successful
 contributors are generally very involved.
 
+Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
+2022. Please feel free to reach out to them directly if you have any questions.
+
 
 ## Why work on coreboot for GSoC?
 
@@ -59,8 +51,6 @@ contributors are generally very involved.
 
   * [Glossary][GSoC Glossary]
 
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
 
 ## Contributor requirements & commitments
 
@@ -101,7 +91,7 @@ amount of spare time. If this is not the case, then you should not apply.
       process and common issues.
 
     * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
+      Check the [easy project list][Project ideas] or ask for simple tasks on
       the [mailing list] or on our other [community forums] if you need ideas.
 
 
@@ -283,4 +273,3 @@ questions.
 [GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
 [GSoC Rules]: https://summerofcode.withgoogle.com/rules
 [GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips

Documentation/contributing/project_ideas.md

@@ -20,12 +20,12 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Small projects
+## Easy projects
 
 This is a collection of tasks which don't require deep knowledge on
 coreboot itself. If you are a beginner and want to get familiar with the
 the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
+dirty with some easy tasks, then these are for you.
 
   * Resolve static analysis issues reported by [scan-build] and
     [Coverity scan]. More details on the page for
@@ -36,7 +36,7 @@ dirty with some small tasks, then these are for you.
 [scan-build]: https://coreboot.org/scan-build/
 [Coverity scan]: https://scan.coverity.com/projects/coreboot
 [Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
+[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
 
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
@@ -63,6 +63,7 @@ non-Linux builds or Docker for different Linux distributions.
 * hardware requirements: Nothing special
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Support Power9/Power8 in coreboot
 There are some basic PPC64 stubs in coreboot, and there's open hardware
@@ -87,7 +88,7 @@ across architectures.
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
 to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
+yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a
 combination of payload and architecture to support.
@@ -129,6 +130,7 @@ their bug reports.
   going on from the resulting logs.
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Extend Ghidra to support analysis of firmware images
 [Ghidra](https://ghidra-sre.org) is a recently released cross-platform

Documentation/corebootBuildingGuide.tex

@@ -386,7 +386,7 @@ want to submit all commits in the currently checked-out branch for
 review on gerrit:
 { \small
 \begin{verbatim}
-$ git config remote.origin.push HEAD:refs/for/main
+$ git config remote.origin.push HEAD:refs/for/master
 \end{verbatim}
 }
 
@@ -399,10 +399,10 @@ $ make gitconfig
 
 \subsection{Work flow}
 
-It is recommended that you make a new branch when you start to work, not pushing changes to main.
+It is recommended that you make a new branch when you start to work, not pushing changes to master.
 { \small
 \begin{verbatim}
-$ git checkout main -b mybranch
+$ git checkout master -b mybranch
 \end{verbatim}
 }
 After you have done your changes, run:
@@ -452,7 +452,7 @@ make a new local commit that fixes the issues reported by the
 reviewers, then rebase the change by preserving the same Change-ID. We
 recommend you to use the git rebase command in interactive mode,
 
-Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/main.
+Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master.
 
 %
 % Working with Gerrit
@@ -474,9 +474,9 @@ click \url{https://review.coreboot.org}
 |Search for status:open                                     |
 +-----------------------------------------------------------+
 |Subject      Status   Owner  Project  Branch Updated CR V  |
-|cpu: Rename..      Alexandru coreboot main   1:20 PM +1    |
+|cpu: Rename..      Alexandru coreboot master 1:20 PM +1    |
-|cpu: Only a..      Alexandru coreboot main   1:17 PM    X  |
+|cpu: Only a..      Alexandru coreboot master 1:17 PM    X  |
-|arch/x86: D..      Alexandru coreboot main   1:09 PM       |
+|arch/x86: D..      Alexandru coreboot master 1:09 PM       |
 |                                                           |
 |                                                  Next ->  |
 |Press '?' to view keyboard shortcuts | Powered by Gerrit   |
@@ -637,7 +637,7 @@ Gerrit makes reviews easier by showing changes in a side-by-side
 display, and allowing inline comments to be added by any reviewer.
 
 Gerrit simplifies Git based project maintainership by permitting any
-authorized user to submit changes to the upstream Git repository, rather
+authorized user to submit changes to the master Git repository, rather
 than requiring all approved changes to be merged in by hand by the
 project maintainer. This functionality enables a more centralized
 usage of Git.

Documentation/distributions.md

@@ -8,25 +8,6 @@ and those providing after-market firmware to extend the usefulness of devices.
 
 ## Hardware shipping with coreboot
 
-### ChromeOS Devices
-
-All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
-Chromebit, etc) released from 2012 onward use coreboot for their main system
-firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
-running on the Embedded Controller (EC) – a small microcontroller which provides
-functions like battery management, keyboard support, and sensor interfacing –
-is open source as well.
-
-### Nitrokey
-
-[Nitrokey](https://nitrokey.com) is a german IT security hardware vendor which
-offers a range of laptops, PCs, HSMs, and networking devices with coreboot and
-[Dasharo](https://dasharo.com/). The devices come with neutralized Intel
-Management Engine (ME) and with pre-installed [Heads](http://osresearch.net) or
-EDK2 payload providing measured boot and verified boot protection. For
-additional security the systems can be physically sealed and pictures of those
-sealings are sent via encrypted email.
-
 ### NovaCustom laptops
 
 [NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
@@ -36,6 +17,15 @@ Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
 and the firmware is equipped with important security features such as measured
 boot, verified boot, TPM integration and UEFI Secure Boot.
 
+### ChromeOS Devices
+
+All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
+Chromebit, etc) released from 2012 onward use coreboot for their main system
+firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
+running on the Embedded Controller (EC) – a small microcontroller which provides
+functions like battery management, keyboard support, and sensor interfacing –
+is open source as well.
+
 ### PC Engines APUs
 
 [PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
@@ -43,23 +33,6 @@ ships with coreboot and support upstream maintenance for the devices through a
 third party, [3mdeb](https://3mdeb.com). They provide current and tested
 firmware binaries on [GitHub](https://pcengines.github.io).
 
-### Protectli
-
-[Protectli](https://protectli.com) is dedicated to providing reliable,
-cost-effective, and secure computer equipment with coreboot-based firmware
-tailored for their hardware. It comes with the [Dasharo](#dasharo)
-firmware, maintained by [3mdeb](https://3mdeb.com/). Protectli hardware has
-verified support for many popular operating systems, such as Linux distributions,
-FreeBSD, and Windows. Support includes Debian, Ubuntu, OPNsense, pfSense,
-ProxMox VE, VMware ESXi, Windows 10 and 11, and many more.
-
-### Purism
-
-[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
-security; part of that effort is to minimize the amount of proprietary and/or
-binary code. Their laptops ship with a blob-free OS and coreboot firmware
-with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
-
 ### Star Labs
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
@@ -74,8 +47,23 @@ servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
 distribution of coreboot, edk2, and System76 firmware applications.
 
+### Purism
+
+[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
+security; part of that effort is to minimize the amount of proprietary and/or
+binary code. Their laptops ship with a blob-free OS and coreboot firmware
+with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
+
 ## After-market firmware
 
+### Libreboot
+
+[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
+provides ready-made firmware images for supported devices: those which can be
+built entirely from source code. Their copy of the coreboot repository is
+therefore stripped of all devices that require binary components to boot.
+
+
 ### Dasharo
 
 [Dasharo](https://dasharo.com/) is an open-source based firmware distribution
@@ -83,8 +71,18 @@ focusing on clean and simple code, long-term maintenance, transparent
 validation, privacy-respecting implementation, liberty for the owners, and
 trustworthiness for all.
 
-Contributions are welcome,
+
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
+### MrChromebox
+
+[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
+images for the vast majority of x86-based Chromebooks and Chromeboxes, using
+edk2 as the payload to provide a modern UEFI bootloader. Why replace
+coreboot with coreboot? Mr Chromebox's images are built using upstream
+coreboot (vs Google's older, static tree/branch), include many features and
+fixes not found in the stock firmware, and offer much broader OS compatibility
+(i.e., they run Windows as well as Linux). They also offer updated CPU
+microcode, as well as firmware updates for the device's embedded controller
+(EC). This firmware "takes the training wheels off" your ChromeOS device :)
 
 ### Heads
 
@@ -99,25 +97,6 @@ Heads is not just another Linux distribution – it combines physical hardening
 of specific hardware platforms and flash security features with custom coreboot
 firmware and a Linux boot loader in ROM.
 
-### Libreboot
-
-[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
-provides ready-made firmware images for supported devices: those which can be
-built entirely from source code. Their copy of the coreboot repository is
-therefore stripped of all devices that require binary components to boot.
-
-### MrChromebox
-
-[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
-images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
-coreboot with coreboot? Mr Chromebox's images are built using upstream
-coreboot (vs Google's older, static tree/branch), include many features and
-fixes not found in the stock firmware, and offer much broader OS compatibility
-(i.e., they run Windows as well as Linux). They also offer updated CPU
-microcode, as well as firmware updates for the device's embedded controller
-(EC). This firmware "takes the training wheels off" your ChromeOS device :)
-
 ### Skulls
 
 [Skulls](https://github.com/merge/skulls) provides firmware images for

Documentation/external_docs.md

@@ -24,33 +24,11 @@ Please add any helpful or informational links and sections as you see fit.
 
 * [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
 * [Interface BUS](http://www.interfacebus.com/)
+* Open course material for a variety of topics such as assembly, firmware,
+  security, debugging, and more.
+  * [Open Security Training](https://opensecuritytraining.info/Training.html),
+  * [Open Security Training 2](https://p.ost2.fyi/)
 
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
 
 ## Firmware Specifications & Information
 
@@ -113,7 +91,6 @@ as well (such as
   * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
   * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
   * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-  * [coreboot on Eagle Stream](https://www.intel.com/content/www/us/en/content-details/778593/coreboot-practice-on-eagle-stream.html)
 
 * Rockchip
   * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)

Documentation/getting_started/build_system.md

@@ -7,10 +7,10 @@ to the point of providing its own custom language.
 The overhead of learning this new syntax is (hopefully) offset by its lower
 complexity.
 
-The build system is defined in the toplevel `Makefile` and `toolchain.mk`
+The build system is defined in the toplevel `Makefile` and `toolchain.inc`
 and is supposed to be generic (and is in fact used with a number of other
 projects).  Project specific configuration should reside in files called
-`Makefile.mk`.
+`Makefile.inc`.
 
 In general, the build system provides a number of "classes" that describe
 various parts of the build. These cover the various build targets in coreboot
@@ -36,7 +36,7 @@ TODO: explain how to create new classes and how to evaluate them.
 ### subdirs
 `subdirs` contains subdirectories (relative to the current directory) that
 should also be handled by the build system. The build system expects these
-directories to contain a file called `Makefile.mk`.
+directories to contain a file called `Makefile.inc`.
 
 Subdirectories are not read at the point where the `subdirs` statement
 resides but later, after the current directory is handled (and potentially
@@ -62,23 +62,6 @@ supported options are:
 
 `position` and `align` are mutually exclusive.
 
-### Adding Makefile fragments
-
-You can use the `add_intermediate` helper to add new post-processing steps for
-the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.mk`
-
-```
-$(call add_intermediate, add_mrc_data)
-	$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
-```
-
-Note that the second line must start with a tab, not spaces.
-
-```eval_rst
-See also :doc:`../tutorial/managing_local_additions`.
-```
-
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
 need to extend the specification of files to provide more precise control
@@ -100,4 +83,4 @@ The default implementation just returns `COREBOOT` (the default region) for
 all files.
 
 vboot provides its own implementation of `regions-for-file` that can be used
-as reference in `src/vboot/Makefile.mk`.
+as reference in `src/vboot/Makefile.inc`.

Documentation/getting_started/devicetree.md

@@ -79,7 +79,7 @@ with no properties as a direct child of the SoC.
 ## Device drivers
 
 Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info.
+See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
 
 ## Notes
 

Documentation/getting_started/faq.md

@@ -1,312 +0,0 @@
-# coreboot FAQ
-
-## General coreboot questions
-
-
-### What is coreboot?
-
-coreboot is a free and open software project designed to initialize
-computers and embedded systems in a fast, secure, and auditable fashion.
-The focus is on minimal hardware initialization: to do only what is
-absolutely needed, then pass control to other software (a payload, in
-coreboot parlance) in order to boot the operating system securely.
-
-
-### What is a coreboot payload?
-
-coreboot itself does not deal with boot media such as hard-drives,
-SSDs, or USB flash-drives, beyond initializing the underlying hardware.
-So in order to actually boot an operating system, another piece of
-software which does do those things must be used. coreboot supports
-a large number of diverse payloads; see below for more details.
-
-
-### Is coreboot the same as UEFI?
-
-No. coreboot and UEFI are both system firmware that handle the
-initialization of the hardware, but are otherwise not similar.
-coreboot’s goal is to **just** initialize the hardware and exit.
-This makes coreboot smaller and simpler, leading to faster boot times,
-and making it easier to find and fix bugs. The result is a higher
-overall security.
-
-
-### What's the difference between coreboot and UEFI?
-
-UEFI is actually a firmware specification, not a specific software
-implementation. Intel, along with the rest of the Tianocore project,
-has released an open-source implementation of the overall framework,
-EDK2, but it does not come with hardware support. Most hardware running
-UEFI uses a proprietary implementation built on top of EDK2.
-
-coreboot does not implement the UEFI specification, but it can be used to
-initialize the system, then launch a UEFI payload such as EDK2 in order
-to provide UEFI boot services.
-
-The UEFI specification also defines and allows for many things that are
-outside of coreboot’s scope, including (but not limited to):
-
-* Boot device selection
-* Updating the firmware
-* A CLI shell
-* Network communication
-* An integrated setup menu
-
-
-### Can coreboot boot operating systems that require UEFI?
-
-Yes, but... again, coreboot **just** initializes the hardware. coreboot
-itself doesn’t load operating systems from storage media other than the
-flash chip. Unlike UEFI, coreboot does not, and will not contain a Wi-Fi
-driver or communicate directly with any sort of network. That sort of
-functionality is not related to hardware initialization.
-
-To boot operating systems that require UEFI, coreboot can be compiled with
-EDK2 as the payload. This allows coreboot to perform the hardware init,
-with EDK2 supplying the UEFI boot interface and runtime services to
-the operating system.
-
-
-### What non-UEFI payloads does coreboot support?
-
-* SeaBIOS, behaves like a classic BIOS, allowing you to boot operating
-  systems that rely on the legacy interrupts.
-
-* GRUB can be used as a coreboot payload, and is currently the most
-  common approach to full disk encryption (FDE).
-
-* A Linux kernel and initramfs stored alongside coreboot in the boot
-  ROM can also be used as a payload. In this scenario coreboot
-  initializes hardware, loads Linux from boot ROM into RAM, and
-  executes it. The embedded Linux environment can look for a target OS
-  kernel to load from local storage or over a network and execute it
-  using kexec. This is sometimes called LinuxBoot.
-
-* U-boot, depthcharge, FILO, etc.
-
-There’s [https://doc.coreboot.org/payloads.html](https://doc.coreboot.org/payloads.
-html) with a list, although it’s not complete.
-
-
-### What does coreboot leave in memory after it's done initializing the hardware?
-
-While coreboot tries to remove itself completely from memory after
-finishing, some tables and data need to remain for the OS. coreboot
-reserves an area in memory known as CBMEM, to save this data after it
-has finished booting. This contains things such as the boot log, tables
-that get passed to the payload, SMBIOS, and ACPI tables for the OS.
-
-In addition to CBMEM, on X86 systems, coreboot will typically set up
-SMM, which will remain resident after coreboot exits.
-
-
-## Platforms
-
-### What’s the best coreboot platform for a user?
-
-The choice of the best coreboot platform for a user can vary depending
-on their specific needs, preferences, and use cases.
-
-Typically, people who want a system with a minimum of proprietary
-firmware are restricted to older systems like the Lenovo X220, or more
-expensive, non-x86 solutions like TALOS, from Raptor Engineering.
-
-There are a number of companies selling modern systems, but those all
-require more proprietary binaries in addition to coreboot (e.g., Intel
-FSP). However, unlike the older ThinkPads, many of these newer devices
-use open-source embedded controller (EC) firmware, so there are
-tradeoffs with either option.
-
-The coreboot project mantains a list of companies selling machines
-which use coreboot on the [website](https://coreboot.org/users.html).
-
-
-### What’s the best platform for coreboot development?
-
-Similar to the best platform for users, the best platform for
-developers very much depends on what a developer is trying to do.
-
-* QEMU is generally the easiest platform for coreboot development, just
-  because it’s easy to run anywhere. However, it’s possible for things
-  to work properly in QEMU but fail miserably on actual hardware.
-
-While laptops tend to be harder to develop than desktop platforms, a
-majority of newer platforms on coreboot tend to be laptops. The
-development difficulty is due to a few different factors:
-
-1. The EC (Embedded Controller) is a specialized microcontroller that
-   typically handles keyboard and sometimes mouse input for a laptop.
-   It also controls many power management functions such as fans, USB-C
-   power delivery, etc. ECs run mainboard-specific firmware, which is
-   typically undocumented.
-2. ThinkPads (X230, 30-series, 20-series, T430, T540, T520). Sandy
-   Bridge and Ivy Bridge are well-supported. Some may have
-   difficult-to-reach SPI flash chips. Boards with two flash chips (e.g.
-   30-series ThinkPads) are harder to externally reflash as one needs to
-   make sure the non-targeted flash chip remains disabled at all times.
-   The X230 is notoriously sensitive to external reflashing issues.
-3. Laptops often lack a convenient method to obtain firmware boot logs.
-   One can use EHCI debug on older systems and Chromebook-specific
-   solutions for Chromebooks, but one often has to resort to flashconsole
-   (writing coreboot logs to the flash chip where coreboot resides). On
-   the other hand, several desktop mainboards still have a RS-232 serial
-   port.
-
-Some of the easiest physical systems to use for coreboot development
-are Chromebooks. Newer Chromebooks allow for debug without opening the
-case. Look for SuzyQ Cables or SuzyQables or instructions on how to
-build one. These cables only work on a specific port in a specific
-orientation. Google [supplies
-specifications](https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/ccd.md#SuzyQ-SuzyQable)
-for these cables.
-
-
-### What platforms does coreboot support?
-
-The most accurate way to determine what systems coreboot supports is by
-browsing the src/mainboard tree or running “make menuconfig” and going
-through the “Mainboard” submenu. You can also search Gerrit to see if
-there are any unmerged ports for your board.
-
-There is also the board status page
-([https://coreboot.org/status/board-status.html](https://coreboot.org/status/board-status.html)),
-however this does not currently show supported board variants.
-
-
-## coreboot Development
-
-### Can coreboot be ported to [this board]?
-
-The best way to determine if coreboot can be ported to a system is to
-see if the processor and chipset is supported. The next step is to see
-whether the system is locked to the proprietary firmware which comes
-with the board.
-
-Intel Platforms:
-
-* coreboot only supports a few northbridges (back when northbridges
-  were on a separate package), and there's next to no support for
-  "server" platforms (multi-socket and similar things). Here's a list
-  of more recent supported Intel processors:
-    * Alder Lake (2021 - Core Gen 12)
-    * Apollo Lake (2016 - Atom)
-    * Baytrail (2014 - Atom)
-    * Braswell (2016 - Atom)
-    * Broadwell (2014 - Core Gen 5)
-    * Comet Lake (2019 - Core Gen 10)
-    * Cannon Lake (2018 - Core Gen 8/9)
-    * Denverton (2017)
-    * Elkhart lake (2021 - Atom)
-    * Haswell (2013 - Core Gen 4)
-    * Ivy Bridge (2012 - Core Gen 3)
-    * Jasper Lake (2021 - Atom)
-    * Kaby Lake (2016 - Core Gen 7/8)
-    * Meteor Lake (2023 - Gen 1 Ultra-mobile)
-    * Sandy Bridge (2011 - Core Gen 2)
-    * Sky Lake (2015 - Core Gen 6)
-    * Tiger Lake (2020 - Core Gen 11)
-    * Whiskey Lake (2018 - Core Gen 8)
-
-* Intel Boot Guard is a security feature which tries to prevent loading
-  unauthorized firmware by the mainboard. If supported by the platform,
-  and the platform is supported by intelmetool, you should check if Boot
-  Guard is enabled. If it is, then getting coreboot to run will be
-  difficult or impossible even if it is ported. You can run
-  `intelmetool -b` on supported platforms to see if Boot Guard is
-  enabled (although it can fail because it wants to probe the ME
-  beforehand).
-
-AMD Ryzen-based platforms:
-
-* The AMD platforms Ryzen-based platforms unfortunately are currently
-  not well supported outside of the Chromebooks (and AMD reference
-  boards) currently in the tree.
-  The responsible teams are trying to fix this, but currently it's
-  **very** difficult to do a new port. Recent supported SoCs:
-    * Stoney Ridge
-    * Picasso
-    * Cezanne
-    * Mendocino
-    * Phoenix
-
-General notes:
-
-* Check the output of `lspci` to determine what processor/chipset
-  family your system has. Processor/chipset support is the most
-  important to determine if a board can be ported.
-* Check the output of `superiotool` to see if it detects the Super I/O
-  on the system. You can also check board schematics and/or boardviews
-  if you can find them, or physically look at the mainboard for a chip
-  from one of the common superio vendors.
-* Check what EC your system has (mostly applicable to laptops, but some
-  desktops have EC-like chips). You will likely need to refer to the
-  actual board or schematics/boardviews for this. Physical observation
-  is the most accurate identification procedure; software detection can
-  then be used to double-check if the chip is correct, but one should
-  not rely on software detection alone to identify an EC.
-
-
-### How do I port coreboot to [this board]?
-
-A critical piece for anyone attempting to do a board port is to make
-sure that you have a method to recover your system from a failed flash.
-
-We need an updated motherboard porting guide, but currently the guide
-on the [wiki](https://www.coreboot.org/Motherboard_Porting_Guide) looks
-to be the best reference.
-
-At the moment, the best answer to this question is to ask for help on
-one of the [various community
-forums](https://doc.coreboot.org/community/forums.html).
-
-
-### What about the Intel ME?
-
-There seems to be a lot of FUD about what the ME can and can’t do.
-coreboot currently does not have a clear recommendation on how to
-handle the ME. We understand that there are serious concerns about the
-ME, and would like to flatly recommend removing as much as possible,
-however modifying the ME can cause serious stability issues.
-
-Additionally, coreboot and the Intel ME are completely separate entites
-which in many cases simply happen to occupy the same flash chip. It is
-not necessary to run coreboot to modify the ME, and running coreboot
-does not imply anything about the ME's operational state.
-
-
-#### A word of caution about the modifying ME
-
-Messing with the ME firmware can cause issues, and this is outside the
-scope of the coreboot project.
-
-If you do decide to modify the ME firmware, please make sure coreboot
-works **before** messing with it. Even if the vendor boot firmware
-works when the ME isn't operating normally, it's possible that coreboot
-doesn't handle it the same way and something breaks. If someone asks
-for help with coreboot and we think the ME state may be a factor, we'll
-ask them to try reproducing the issue with the ME running normally to
-reduce the number of variables involved. This is especially important
-when flashing coreboot for the first time, as it's best for newbies to
-start with small steps: start by flashing coreboot to the BIOS region
-and leaving the remaining regions untouched, then tinker around with
-coreboot options (e.g. other payloads, bootsplash, RAM overclock...),
-or try messing with the ME firmware **without changing coreboot**.
-
-Most people don't understand the implications of messing with the ME
-firmware, especially the use of `me_cleaner`. We admit that we don't
-know everything about the ME, but we try to understand it as much as
-possible. The ME is designed to operate correctly with the HAP (or
-AltMeDisable) bit set, and it will gracefully enter a debug state (not
-normal, but not an error). However, when using `me_cleaner` to remove
-parts of the ME firmware, the ME will often end up in an error state
-because parts of its FW are missing. It is known that removing some of
-these parts ([`EFFS` and `FCRS` on Cougar Point,
-c.f.](https://review.coreboot.org/c/coreboot/+/27798/6/src/mainboard/asus/p8h61-m_lx/Kconfig#63))
-can cause problems. We do not know whether the state the ME ends up in
-after applying `me_cleaner` is as secure as the state the ME goes to
-when only the HAP bit is set: the removed FW modules could contain
-steps to lock down important settings for security reasons.
-
-To sum up, **we do not recommend messing with the ME firmware**. But if
-you have to, please use `ifdtool` to set the HAP bit initially before
-progressing to `me_cleaner` if necessary.

Documentation/getting_started/index.md

@@ -7,4 +7,3 @@
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
 * [Adding devices to a device tree](devicetree.md)
-* [Frequently Asked Questions](faq.md)

Documentation/getting_started/kconfig.md

@@ -69,6 +69,9 @@ These variables are typically set in the makefiles or on the make command line.
 These variables were added to Kconfig specifically for coreboot and are not
 included in the Linux version.
 
+- KCONFIG_STRICT=value. Define to enable warnings as errors.   This is enabled
+  in coreboot, and should not be changed.
+
 - KCONFIG_NEGATIVES=value. Define to show negative values in the autoconf.h file
   (build/config.h). This is enabled in coreboot, and should not be changed.
 
@@ -99,9 +102,6 @@ included in the Linux version.
 - KCONFIG_SPLITCONFIG=”directory name for individual SYMBOL.h files”.
   coreboot sets this to $(obj)/config.
 
-- KCONFIG_WERROR=value. Define to enable warnings as errors. This is enabled
-  in coreboot, and should not be changed.
-
 #### Used only for ‘make menuconfig’
 - MENUCONFIG_MODE=single_menu.  Set to "single_menu" to enable.  All other
   values disable the option.  This makes submenus appear below the menu option
@@ -963,7 +963,7 @@ variable.  This is not set in coreboot, which uses the default CONFIG_ prefix
 for all of its symbols.
 
 The coreboot makefile forces the config.h file to be included into all coreboot
-C files. This is done in Makefile.mk on the compiler command line using the
+C files. This is done in Makefile.inc on the compiler command line using the
 “-include $(obj)/config.h” command line option.
 
 Example of various symbol types in the config.h file:
@@ -1160,6 +1160,10 @@ saved .config file. As always, a 'select' statement overrides any specified
 - coreboot has added the glob operator '*' for the 'source' keyword.
 - coreboot’s Kconfig always defines variables except for strings. In other
   Kconfig implementations, bools set to false/0/no are not defined.
+- coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to
+  error out if there are any issues in the Kconfig files.  In the Linux kernel,
+  Kconfig will generate a warning, but will still output an updated .config or
+  config.h file.
 
 
 ## Kconfig Editor Highlighting

Documentation/index.md

@@ -1,8 +1,9 @@
 # Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
-It is built from Markdown files in the [Documentation] directory in the
+It is built from Markdown files in the
-source code.
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
 
 ## Spelling of coreboot
 
@@ -142,13 +143,13 @@ say hello!
 ## Getting the source code
 
 coreboot is primarily developed in the
-[git](https://review.coreboot.org/plugins/gitiles/coreboot) version control
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
 system, using [Gerrit](https://review.coreboot.org) to manage
 contributions and code review.
 
-In general we try to keep the `main` branch in the repository functional
+In general we try to keep the `master` branch in the repository functional
 for all hardware we support. So far, the only guarantee we can make is
-that the main branch will (nearly) always build for all boards in a
+that the master branch will (nearly) always build for all boards in a
 standard configuration.
 
 However, we're continually working on improvements to our infrastructure to
@@ -192,12 +193,9 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Software Bill of Materials](sbom/sbom.md)
 * [Project infrastructure & services](infrastructure/index.md)
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Acronyms & Definitions](acronyms.md)
 * [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)
-
-[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Documentation/

Documentation/infrastructure/admin.md

@@ -1,52 +0,0 @@
-# Operating our services
-
-## Mailing list moderation
-
-Our [mailing lists] experience the same barrage of spam mails than any
-other email address. We do have a spam filter in front of it, and
-since the lists require registration, spam ends up in the moderation
-queue. But not only spam ends up there, sometimes users send inquiries
-without registering first. It's a custom of the project to let these
-through, so that such emails can be discussed. This requires manual
-intervention.
-
-This section describes the tasks related to mailing list management.
-
-### Registration
-
-To participate in mailing list moderation, you need to become a list
-moderator or owner. This is up for the existing owners to handle and
-if you want to contribute in that area, it might be best to bring it
-up at the leadership meeting.
-
-After gaining leadership approval, list admins can add you to the
-appropriate group in the [mailing list backend] by selecting the list,
-then User / group-name, and add your email address there.
-
-### Regular tasks
-
-Most of our lists are auto-subscribing, so users can register
-themselves and finish the process by responding to the double-opt-in
-email. Some lists are manually managed though. The [mailing list
-backend] shows the number of open subscription requests for these
-lists on the mailing list's main page.
-
-It also provides a list of held messages, where they can be accepted,
-rejected or dropped. Spam should be dropped, that's clear. Emails with
-huge attachments (e.g. screenshots) should be rejected, which gives
-you an opportunity to explain the reason (in case of large
-attachments, something like "Please re-send without attachments, offer
-the files through some other mechanism please: Our emails are
-distributed to hundreds of readers, and sending the files to everybody
-is inconsiderate of traffic and storage constraints.")
-
-Legit emails (often simple requests of the form "is this or that
-supported") can be accepted, which means they'll be sent out.
-
-If you notice recurring spam sources (e.g. marketers) you can put them
-on the [global ban list] to filter them out across all lists. It takes
-entries in regular expression format.
-
-[mailing lists]: https://mail.coreboot.org/hyperkitty/
-[mailing list backend]: https://mail.coreboot.org/postorius/
-[global ban list]: https://mail.coreboot.org/postorius/bans/

Documentation/infrastructure/builders.md

@@ -24,7 +24,8 @@ issues.
 
 Currently active Jenkins admins:
 *   Patrick Georgi:
-    *   Email: [patrick@coreboot.org](mailto:patrick@coreboot.org)
+    *   Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
+    *   IRC: pgeorgi
 *   Martin Roth:
     *   Email: [gaumless@gmail.com](mailto:gaumless@gmail.com)
     *   IRC: martinr
@@ -73,7 +74,7 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
 
 There are a number of builds handled by the coreboot jenkins builders,
 for a number of different projects - coreboot, flashrom, memtest86+,
-em100, etc.  Many of these have builders for their current main branch
+em100, etc.  Many of these have builders for their current master branch
 as well as Gerrit and [Coverity](coverity.md) builds.
 
 
@@ -90,14 +91,14 @@ machines.  These tasks run overnight in the US timezones.
 You can see all the builds in the main jenkins interface:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
-Most of the time on the builders is taken up by the coreboot main and
+Most of the time on the builders is taken up by the coreboot master and
 coreboot gerrit builds.
 
 * [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
 ([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
 
 
-* [coreboot main build](https://qa.coreboot.org/job/coreboot/)
+* [coreboot master build](https://qa.coreboot.org/job/coreboot/)
  ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
 
 

Documentation/infrastructure/index.md

@@ -5,7 +5,7 @@ This section contains documentation about our infrastructure
 ## Services
 
 * [Project services](services.md)
-* [Administrator's handbook](admin.md)
+
 
 ## Jenkins builders and builds
 * [Setting up Jenkins build machines](builders.md)

Documentation/lib/flashmap.md

@@ -73,7 +73,7 @@ compiler](https://chromium-review.googlesource.com/#/c/255031) inside coreboot
 utility folder that can be used to generate final firmware images (i.e.
 `coreboot.rom`) formatted by Flashmap.
 
-The FMD implementation is in coreboot `util/cbfstool` folder. Here's an
+The FMD implementation is in coreboot `utils/cbfstool` folder. Here's an
 informal language description:
 
 ```

Documentation/lib/fw_config.md

@@ -106,8 +106,8 @@ protection)* with the `ectool` command in a ChromeOS environment.
 For more information on the firmware configuration field on ChromeOS devices see the Chromium
 documentation for [Firmware Config][1] and [Board Info][2].
 
-[1]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/firmware_config.md
+[1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md
-[2]: http://chromium.googlesource.com/chromiumos/docs/+/HEAD/design_docs/cros_board_info.md
+[2]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md
 
 ## Firmware Configuration Table
 

Documentation/lib/payloads/fit.md

@@ -180,5 +180,5 @@ The generated file includes a compressed initrd **initramfs.cpio.xz**, which
 will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**,
 which will be decompressed by the FIT loader and an uncompressed devicetree blob.
 
-[uImage.FIT]: https://github.com/u-boot/u-boot/blob/master/doc/usage/fit/howto.rst
+[uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto.txt
 [U-Boot]: https://www.denx.de/wiki/U-Boot

Documentation/mainboard/asrock/h77pro4-m.md

@@ -45,9 +45,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
 - Rear eSATA connector (multiplexed with one ASM1061 port)
 - Gigabit Ethernet
 - Console output on the serial port
-- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
+- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
-Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
-- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
 extlinux
 - Internal flashing with flashrom-1.2, see
 [Internal Programming](#internal-programming)

Documentation/mainboard/asus/p2b-ls.md

@@ -1,108 +0,0 @@
-# ASUS P2B-LS
-
-This page describes how to run coreboot on the ASUS P2B-LS mainboard.
-
-## Variants
-
-- P2B-LS
-- P2B-L (Same circuit board with SCSI components omitted)
-- P2B-S (Same circuit board with ethernet components omitted)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | no                        |
-+---------------------+---------------------------+
-| Dual BIOS feature   | no                        |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-[flashrom] works out of the box since 0.9.2.
-Because of deficiency in vendor firmware, user needs to override the laptop
-warning as prompted. Once coreboot is in place there will be no further issue.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- Ethernet (-LS, -L; Intel 82558)
-- SCSI (-LS, -S; Adaptec AIC7890)
-- USB
-- ISA add-on cards
-- PCI add-on cards
-- AGP graphics card
-- Floppy
-- Serial ports 1 and 2
-- Reboot
-- Soft off
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted.
-  With SeaBIOS as payload, setting keyboard initialization timeout to
-  500ms may fix the issue.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-- Termination is enabled for all SCSI ports (if equipped). Support to
-  disable termination is pending. Note that the SCSI-68 port is
-  always terminated, even with vendor firmware.
-
-## Untested
-
-- Parallel port
-- EDO memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- S3 suspend to RAM
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p3b-f.md

@@ -1,106 +0,0 @@
-# ASUS P3B-F
-
-This page describes how to run coreboot on the ASUS P3B-F mainboard.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | See below                 |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6.
-If you are using older versions of flashrom, below has to be done (with ACPI disabled!)
-before flashrom can detect the flash chip:
-
-```bash
-  #  rmmod w83781d
-  #  modprobe i2c-dev
-  #  i2cset 0 0x48 0x80 0x80
-```
-
-Upon power up, flash chip is inaccessible until flashrom has been run once.
-Since flashrom does not support reversing board enabling steps,
-once it detects the flash chip, there will be no write protection until
-the next power cycle.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- USB
-- PCI add-on cards
-- AGP graphics cards
-- Serial ports 1 and 2
-- Reboot
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS
-  as payload, setting keyboard initialization timeout to 2500ms may help.
-
-- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not
-  yet ready by the time SeaBIOS attempts to boot from them.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-## Untested
-
-- Floppy
-- Parallel port
-- EDO memory
-- ECC memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098))
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p8z77-m.md

@@ -1,137 +0,0 @@
-# ASUS P8Z77-M
-
-This page describes how to run coreboot on the [ASUS P8Z77-M].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+----------------+
-| Type                | Value          |
-+=====================+================+
-| Model               | W25Q64FVA1Q    |
-+---------------------+----------------+
-| Size                | 8 MiB          |
-+---------------------+----------------+
-| Package             | DIP-8          |
-+---------------------+----------------+
-| Socketed            | yes            |
-+---------------------+----------------+
-| Write protection    | yes            |
-+---------------------+----------------+
-| Dual BIOS feature   | no             |
-+---------------------+----------------+
-| Internal flashing   | yes            |
-+---------------------+----------------+
-```
-
-The flash chip is located between the blue SATA ports.
-
-The main SPI flash cannot be written internally because Asus disables BIOSWE and
-enables ``BLE/SMM_BWP`` flags in ``BIOS_CNTL`` for their latest bioses.
-To install coreboot for the first time, the flash chip must be removed and
-flashed with an external programmer; flashing in-circuit doesn't work.
-The flash chip is socketed, so it's easy to remove and reflash.
-
-## Working
-
-- All USB2 ports (mouse, keyboard and thumb drive)
-- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
-- Gigabit Ethernet (RTL8111F)
-- SATA3, SATA2 (all ports, hot-swap not tested)
-       (Blue SATA2)  (Blue SATA2)  (White SATA3)
-        port 5        port 3        port 1
-        port 6        port 4        port 2
-
-- CPU Temp sensors and hardware monitor (some values don't make sense)
-- Native and MRC memory initialization
-  (please see [Native raminit compatibility] and [MRC memory compatibility])
-
-- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
-  (VGA/DVI-D/HDMI tested and working)
-- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3
-  (Arch based))
-- Serial port
-- PCI slot
-  Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested)
-  Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from
-  SeaBIOS)
-- S3 suspend from Linux
-- 2-channel analog audio (WAV playback by mplayer via back panel line out port)
-- Windows 10 with libgfxinit high resolution framebuffer and VBT
-
-## Known issues
-
-- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could
-  be reconfigured by the blob.
-
-- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config.
-  Otherwise integrated graphics would fail with a black screen.
-
-- PCI POST card is not functional because the PCI bridge early init is not yet done.
-
-- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for
-  an x8, and is electrically an x4 only.
-
-## Untested
-
-- Wake-on-LAN
-- USB3 on header
-- TPM header
-- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
-- HDMI and S/PDIF audio out
-
-## Not working
-
-- PS/2 keyboard or mouse
-- 4 and 6 channel analog audio out: Rear left and right audio is a muted
-  copy of front left and right audio, and the other two channels are silent.
-
-## Native (and MRC) raminit compatibility
-
-- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
-
-- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable
-  with obvious pattern of bit errors during memtest86+ runs.
-
-- Samsung PC3-10600U 2x2GB kit works at full rated speed.
-
-- Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
-
-## Extra onboard buttons
-
-The board has two onboard buttons, and each has a related LED nearby.
-What controls the LEDs and what the buttons control are unknown,
-therefore they currently do nothing under coreboot.
-
-- BIOS_FLBK
-  OEM firmware uses this button to facilitate a simple update mechanism
-  via a USB drive plugged into the bottom USB port of the USB/LAN stack.
-
-- MemOK!
-  OEM firmware uses this button for memory tuning related to overclocking.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6779D                                 |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-- [Flash chip datasheet][W25Q64FVA1Q]
-
-[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/
-[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/2170p.md

@@ -1,91 +0,0 @@
-# HP EliteBook 2170p
-
-This page is about the notebook [HP EliteBook 2170p].
-
-## Release status
-
-HP EliteBook 2170p was released in 2012 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-1. EC firmware
-2. Intel ME firmware
-
-EC firmware can be retrieved from the HP firmware update image, or the firmware
-backup of the laptop. EC Firmware is part of the coreboot build process.
-The guide on extracting EC firmware and using it to build coreboot is in
-document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops).
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-## Programming
-
-The flash chip is located between the memory slots, WWAN card and CPU,
-covered by the base enclosure, which needs to be removed according to
-the [Maintenance and Service Guide] to access the flash chip. Unlike
-other variants, the flash chip on 2170p is socketed, so it can be taken
-off and operated with an external programmer.
-
-Pin 1 of the flash chip is at the side near the CPU.
-
-![Flash Chip in 2170p](2170p_flash.jpg)
-
-For more details have a look at the general [flashing tutorial].
-
-## Debugging
-
-The board can be debugged with serial port on the dock or EHCI debug.
-The EHCI debug port is the left USB3 port.
-
-## Test status
-
-### Known issues
-
-- GRUB payload freezes if at_keyboard module is in the GRUB image
-  ([bug #141])
-
-### Untested
-
-- Fingerprint Reader
-- Dock: Parallel port, PS/2 mouse, S-Video port
-
-### Working
-
-- Integrated graphics init with libgfxinit
-- SATA
-- Audio: speaker and microphone
-- Ethernet
-- WLAN
-- WWAN
-- Bluetooth
-- SD Card Reader
-- SmartCard Reader
-- USB
-- DisplayPort
-- Keyboard, touchpad and trackpoint
-- EC ACPI support and thermal control
-- Dock: all USB ports, DVI-D, Serial debug, PS/2 keyboard
-- TPM
-- Internal flashing when IFD is unlocked
-- Using `me_cleaner`
-
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Panther Point QM77                         |
-+------------------+--------------------------------------------------+
-| EC               | SMSC KBC1126                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[HP EliteBook 2170p]: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03387961.pdf
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -14,99 +14,30 @@ The following things are still missing from this coreboot port:
 ## Flashing coreboot
 
 ```eval_rst
-+---------------------+-------------------------+
++---------------------+------------+
-| Type                | Value                   |
+| Type                | Value      |
-+=====================+=========================+
++=====================+============+
-| Socketed flash      | no                      |
+| Socketed flash      | no         |
-+---------------------+-------------------------+
++---------------------+------------+
-| Model               | MX25L6406E/MX25L6408E   |
+| Model               | MX25L6406E |
-+---------------------+-------------------------+
++---------------------+------------+
-| Size                | 8 MiB                   |
+| Size                | 8 MiB      |
-+---------------------+-------------------------+
++---------------------+------------+
-| In circuit flashing | yes                     |
+| In circuit flashing | yes        |
-+---------------------+-------------------------+
++---------------------+------------+
-| Package             | SOIC-8                  |
+| Package             | SOIC-8     |
-+---------------------+-------------------------+
++---------------------+------------+
-| Write protection    | bios region             |
+| Write protection    | No         |
-+---------------------+-------------------------+
++---------------------+------------+
-| Dual BIOS feature   | No                      |
+| Dual BIOS feature   | No         |
-+---------------------+-------------------------+
++---------------------+------------+
-| Internal flashing   | yes                     |
+| Internal flashing   | yes        |
-+---------------------+-------------------------+
++---------------------+------------+
-```
-
-### Flash layout
-The original layout of the flash should look like this:
-```
-00000000:00000fff fd
-00510000:007fffff bios
-00003000:0050ffff me
-00001000:00002fff gbe
 ```
 
 ### Internal programming
 
 The SPI flash can be accessed using [flashrom].
-```console
-$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
-```
-
-After shorting the FDO jumper you gain access to the full flash, but you
-still cannot write in the bios region due to SPI protected ranges.
-
-**Position of FDO jumper close to the IO and second fan connector**
-![][compaq_8200_jumper]
-
-[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg
-
-To write to the bios region you can use an [IFD Hack] originally developed
-for MacBooks, but with modified values described in this guide.
-You should read both guides before attempting the procedure.
-
-Since you can still write in the flash descriptor, you can shrink
-the ME and then move the bios region into where the ME originally was.
-coreboot does not by default restrict writing to any part of the flash, so
-you will first flash a small coreboot build and after it boots, flash
-the full one.
-
-The temporary flash layout with the neutered ME firmware should look like this:
-```
-00000000:00000fff fd
-00023000:001fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-00200000:007fffff pd
-```
-
-It is very important to use these exact numbers or you will need to fix it
-using external flashing, but you should already be familiar with the risks
-if you got this far.
-
-The temporary ROM chip size to set in menuconfig is 2 MB but the default
-CBFS size is too large for that, you can use up to about 0x1D0000.
-
-When building both the temporary and the permanent installation, don't forget
-to also add the gigabit ethernet configuration when adding the flash descriptor
-and ME firmware.
-
-You can pad the ROM to the required 8MB with zeros using:
-```console
-$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
-$ cat coreboot.rom 6M.bin > coreboot8.rom
-```
-
-If you want to continue using the neutered ME firmware use this flash layout
-for stage 2:
-```
-00000000:00000fff fd
-00023000:007fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-```
-
-If you want to use the original ME firmware use the original flash layout.
-
-More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md).
 
 ### External programming
 
@@ -143,7 +74,7 @@ as otherwise there's not enough space near the flash.
 | Coprocessor      | Intel ME                                         |
 +------------------+--------------------------------------------------+
 ```
-[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
+
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -1,65 +0,0 @@
-# HP Compaq Elite 8300 USDT
-
-This page describes how to run coreboot on the [Compaq Elite 8300 USDT] desktop
-from [HP].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+-------------+
-| Type                | Value       |
-+=====================+=============+
-| Socketed flash      | no          |
-+---------------------+-------------+
-| Model               | W25Q128BVFG |
-+---------------------+-------------+
-| Size                | 16 MiB      |
-+---------------------+-------------+
-| In circuit flashing | yes         |
-+---------------------+-------------+
-| Package             | SOIC-16     |
-+---------------------+-------------+
-| Write protection    | No          |
-+---------------------+-------------+
-| Dual BIOS feature   | No          |
-+---------------------+-------------+
-```
-
-### Internal programming
-
-Internal programming is possible. Shorting the Flash Descriptor Override
-(FDO) jumper bypasses all write protections.
-
-### External programming
-
-Remove the lid. The flash chip can be found on the edge opposite to the CPU.
-There is a spot for a "ROM RCVRY" header next to the flash chip but it is
-unpopulated. If you don't feel like using a clip, you can easily solder
-a standard pin header there yourself and use it for programming.
-
-Programming powers some parts of the board. Programming when
-Wake on LAN is active works great.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | NPCD379HAKFX                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-### SuperIO
-
-This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
-fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
-
-[Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
-[HP]: https://www.hp.com/

Documentation/mainboard/hp/elitebook_820_g2.md

@@ -1,141 +0,0 @@
-# HP EliteBook 820 G2
-
-This page is about the notebook [HP EliteBook 820 G2].
-
-## Release status
-
-HP EliteBook 820 G2 was released in 2015 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-
-1. EC firmware
-2. Intel ME firmware
-3. Broadwell mrc.bin and refcode.elf
-
-HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller.
-The EC firmware is stored in the flash chip, but we don't need to touch it
-or use it in the coreboot build process.
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-The Broadwell memory reference code binary and reference code blob is needed
-when building coreboot. Read the document [Blobs used in Intel Broadwell boards]
-on how to get these blobs.
-
-## Programming
-
-Before flashing, remove the battery and the hard drive cover according to the
-[Maintenance and Service Guide] of this laptop.
-
-HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB
-private flash. To install coreboot, we need to program both flash chips.
-Read [HP Sure Start] for detailed information.
-
-![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg)
-
-To access the system flash, we need to connect the AC adapter to the machine,
-then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
-made with an STM32 development board is tested to work.
-
-To access the private flash chip, we can use a ch341a based flash programmer and
-flash the chip with the AC adapter disconnected.
-
-To flash coreboot on a board running OME firmware, create a backup for both flash
-chips, then do the following:
-
-1. Erase the private flash to disable the IFD protection
-2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside
-   the protected flash region
-
-To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
-then run:
-
-    flashrom -p <programmer> --erase
-
-To modify the IFD, write the following flash layout to a file:
-
-    00000000:00000fff fd
-    00001000:00002fff gbe
-    00003000:005fffff me
-    00600000:00bfffff bios
-    00eb5000:00ffffff pd
-
-Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
-is in ``factory-sys.rom``, run:
-
-    ifdtool -n layout.txt factory-sys.rom
-
-Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
-
-Flash the IFD of the system flash:
-
-    flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
-
-Then flash the coreboot image:
-
-    # first extend the 12M coreboot.rom to 16M
-    fallocate -l 16M build/coreboot.rom
-    flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
-
-After coreboot is installed, the coreboot firmware can be updated with internal flashing:
-
-    flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
-
-## Debugging
-
-The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
-
-## Test status
-
-### Untested
-
-- NFC module
-- Fingerprint reader
-- Smart Card reader
-
-### Working
-
-- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory
-- SATA and M.2 SATA disk
-- PCIe SSD
-- Webcam
-- Touch screen
-- Audio output from speaker and headphone jack
-- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards])
-- WLAN
-- WWAN
-- SD card reader
-- Internal LCD, DisplayPort and VGA video outputs
-- Dock
-- USB
-- Keyboard and touchpad
-- EC ACPI
-- S3 resume
-- TPM
-- Arch Linux with Linux 5.11.16
-- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1
-- Graphics initialization with libgfxinit
-- Payload: SeaBIOS 1.16.2
-- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05
-- Internal flashing under coreboot
-
-## Technology
-
-```eval_rst
-+------------------+-----------------------------+
-| SoC              | Intel Broadwell             |
-+------------------+-----------------------------+
-| EC               | SMSC MEC1324                |
-+------------------+-----------------------------+
-| Coprocessor      | Intel Management Engine     |
-+------------------+-----------------------------+
-```
-
-[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
-[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf
-[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
-[HP Sure Start]: hp_sure_start.md

Documentation/mainboard/index.md

@@ -23,14 +23,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
-- [P2B-LS](asus/p2b-ls.md)
-- [P3B-F](asus/p3b-f.md)
 - [P5Q](asus/p5q.md)
 - [P8C WS](asus/p8c_ws.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8H77-V](asus/p8h77-v.md)
-- [P8Z77-M](asus/p8z77-m.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
 - [wifigo_v1](asus/wifigo_v1.md)
@@ -75,23 +72,19 @@ The boards in this section are not real mainboards, but emulators.
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
-- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
 - [Z220 Workstation SFF](hp/z220_sff.md)
 
 ### EliteBook series
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [HP Sure Start](hp/hp_sure_start.md)
-- [EliteBook 2170p](hp/2170p.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)
-- [EliteBook 820 G2](hp/elitebook_820_g2.md)
 
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
-- [DQ67SW](intel/dq67sw.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -125,7 +118,8 @@ The boards in this section are not real mainboards, but emulators.
 ### Ivy Bridge series
 
 - [T430](lenovo/t430.md)
-- [T530 / W530](lenovo/w530.md)
+- [T530](lenovo/w530.md)
+- [W530](lenovo/w530.md)
 - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
 - [T431s](lenovo/t431s.md)
 - [X230s](lenovo/x230s.md)
@@ -174,8 +168,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [FW2B / FW4B](protectli/fw2b_fw4b.md)
 - [FW6A / FW6B / FW6C](protectli/fw6.md)
-- [VP2420](protectli/vp2420.md)
-- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
 
 ## Roda
 
@@ -206,33 +198,25 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Adder Workstation 1](system76/addw1.md)
 - [Adder Workstation 2](system76/addw2.md)
-- [Adder Workstation 3](system76/addw3.md)
 - [Bonobo Workstation 14](system76/bonw14.md)
-- [Bonobo Workstation 15](system76/bonw15.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
 - [Darter Pro 8](system76/darp8.md)
-- [Darter Pro 9](system76/darp9.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Galago Pro 6](system76/galp6.md)
-- [Galago Pro 7](system76/galp7.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
 - [Gazelle 17](system76/gaze17.md)
-- [Gazelle 18](system76/gaze18.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Lemur Pro 11](system76/lemp11.md)
-- [Lemur Pro 12](system76/lemp12.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
 - [Oryx Pro 9](system76/oryp9.md)
 - [Oryx Pro 10](system76/oryp10.md)
-- [Oryx Pro 11](system76/oryp11.md)
-- [Serval Workstation 13](system76/serw13.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/dq67sw.md

@@ -1,170 +0,0 @@
-# Intel DQ67SW
-
-The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel Q67 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1333                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton/Winbond W83677HG-i                       |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82579LM Gigabit Ethernet                   |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header                                  |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- Integrated GPU with libgfxinit
-- PCIe graphics in the PEG slot
-- Additional PCIe slots
-- PCI slot
-- All rear (4x) and internal (8x) USB2 ports
-- Rear USB3 ports (2x)
-- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
-- Two rear eSATA connectors (3 Gb/s)
-- SATA at 6 Gb/s
-- Gigabit Ethernet
-- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
-- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
-- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
-    - slackware64 (Linux 5.15)
-    - Windows 10 (22H2)
-- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
-- Poweroff
-- Resume from S3
-- Console output on the serial port
-
-### Not working
-
-- Automatic fan control. One can still use OS-based fan control programs,
-  such as fancontrol on Linux or SpeedFan on Windows.
-- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
-  works, but once Windows Update installs drivers, it crashes and enters a
-  bootloop.
-
-### Untested
-
-- Firewire (LSI L-FW3227-100)
-- EHCI debug
-- S/PDIF audio
-- Audio jacks other than the green one
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | yes        |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | see below  |
-+---------------------+------------+
-| In circuit flashing | see below  |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-
-    00000000:00000fff fd
-    00580000:007fffff bios
-    00003000:0057ffff me
-    00001000:00002fff gbe
-
-Unfortunately the SPI interface to the chip is locked down by the vendor
-firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
-the PCI configuration space of the LPC Interface Bridge, is set.
-
-It is possible to program the chip is to attach an external programmer
-with an SOIC-8 clip.
-
-```eval_rst
-Another way is to boot the vendor firmware in UEFI mode and exploit the
-unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
-
-On this specific board it is possible to prevent the BLE bit from being set
-when it resumes from S3. One entry in the S3 Boot Script must be modified,
-e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
-that supports this specific type of S3 Boot Script, for example from strobo5:
-
-    $ git clone -b headerless https://github.com/strobo5/chipsec.git
-    $ cd chipsec
-    $ python setup.py build_ext -i
-    $ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
-
-The boot script contains an entry that writes 0x02 to memory at address
-0xe00f80dc. This address points at the PCIe configuration register at offset
-0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
-Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
-prevents this by making it write a 0 instead.
-
-```eval_rst
-After suspending and resuming the board, the BIOS region can be flashed with
-a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
-so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-## Hardware monitoring and fan control
-
-Currently there is no automatic, OS-independent fan control.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## References
-
-[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
-May 2011,
-Document number 324645-006
-
-[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
-December 2008,
-Document number 321090
-

Documentation/mainboard/lenovo/vboot.md

@@ -9,7 +9,7 @@ updates using an A/B partitioning scheme once enabled.
 ## Enabling vboot
 You can enable [vboot] in Kconfig's *Security* section. Besides a verified
 boot you can also enable a measured boot by setting
-`CONFIG_TPM_MEASURED_BOOT`. Both options need a working TPM, which is
+`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
 present on all recent Lenovo devices.
 
 ## Updating and recovery

Documentation/mainboard/ocp/deltalake.md

@@ -222,4 +222,4 @@ and [u-root] as initramfs.
 [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
 [u-root]: https://u-root.org/
 [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
-[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD/src/mainboard/ocp/deltalake/vpd.h
+[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/ocp/deltalake/vpd.h

Documentation/mainboard/protectli/vp2420.md

@@ -1,87 +0,0 @@
-# Protectli Vault VP2420
-
-This page describes how to run coreboot on the [Protectli VP2420].
-
-![](VP2420_back.jpg)
-![](VP2420_front.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. Firmware can be easily
-flashed with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is soldered in
-under RAM, easily accessed after taking out the memory. Specifically, it's a
-KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](VP2420_internal.jpg)
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 4 Ethernet ports
-- HDMI, DisplayPort
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector
-- SMBus (reading SPD from DIMMs)
-- Initialization with Elkhart Lake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Celeron J6412                              |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Elkhart Lake                               |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8613E                                      |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
-- [VP2420 Product Page](https://protectli.com/product/vp2420/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-- [flashrom](https://flashrom.org/Flashrom)

Documentation/mainboard/protectli/vp46xx.md

@@ -1,135 +0,0 @@
-# Protectli Vault VP46xx series
-
-This page describes how to run coreboot on the [Protectli VP46xx].
-
-![](vp46xx_front.jpg)
-![](vp46xx_back.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule. VP4630 and VP4650 use CometLake2 FSP and VP4670
-use CometLake1 FSP (see [variants](#variants) section), so be sure to select
-the correct board in the coreboot's menuconfig, otherwise the platform will not
-succeed on memory initialization.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. The first version
-supporting the chipset is flashrom v1.2. Firmware an be easily flashed
-with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB socketed SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is near the M.2
-WiFi slot connector. Remove the chip from socket and use a clip to program the
-chip. Specifically, it's a KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](vp46xx_flash.jpg)
-
-## Known issues
-
-- After flashing with external programmer it is always required to reset RTC
-  with a jumper or disconnect the coin cell temporarily. Only then the platform
-  will boot after flashing.
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 6 Ethernet ports
-- HDMI, DisplayPort and USB-C Display Port with libgfxinit and FSP GOP
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector (Fintek F81232 USB to
-  UART adapter present on board)
-- SMBus (reading SPD from DIMMs)
-- Initialization with CometLake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- LPC TPM module (using Protectli custom-designed module with Infineon SLB9660)
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Variants
-
-There are 3 variants of VP46xx boards: VP4630, VP4650 and VP4670. They differ
-only in used SoC and some units may come with different Super I/O chips, either
-ITE IT8786E or IT8784E, but the configuration is the same on this platform.
-
-- VP4630:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i3-10110U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4650:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i5-10210U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4670:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-10810U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
-- [VP4630 Product Page](https://protectli.com/product/vp4630/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-
-[Protectli VP46xx]: https://protectli.com/vault-6-port/
-[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
 
 ## Flashing coreboot
 
@@ -63,6 +63,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -38,7 +38,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
 
 ## Flashing coreboot
 
@@ -60,6 +60,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_adl.md

@@ -5,8 +5,6 @@
 - CPU (full processor specs available at https://ark.intel.com)
     - Intel i7-1260P (Alder Lake)
     - Intel i3-1220P (Alder Lake)
-    - Intel i3-1315U (Raptor Lake)
-    - Intel i7-1360P (Raptor Lake)
 - EC
     - ITE IT5570E
     - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
@@ -35,15 +33,14 @@
     - RTS5129 MicroSD card reader
 - USB
     - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left) (Alder Lake)
+    - USB 3.1 Gen 2 (left)
-    - Thunderbolt 4.0 (left) (Raptor Lake)
     - USB 3.1 Gen 2 Type-A (left)
     - USB 3.1 Gen 1 Type-A (right)
     - USB 2.0 Type-A (right)
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
 
 ### Preliminaries
 
@@ -61,21 +58,12 @@ These files exist in the correct location in the StarLabsLtd/blobs repo on GitHu
 
 The following commands will build a working image:
 
-
-Alder Lake:
 ```bash
 make distclean
 make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
 make
 ```
 
-Raptor Lake:
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_rpl
-make
-```
-
 ## Flashing coreboot
 
 ```eval_rst
@@ -96,6 +84,5 @@ make
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
 
 ## Flashing coreboot
 
@@ -62,6 +62,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -9,7 +9,6 @@ Controller etc.
 - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
 - [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
 - [X11SSM-F](x11ssm-f/x11ssm-f.md)
-- [X11SSW-F](x11ssw-f/x11ssw-f.md)
 
 ## Required proprietary blobs
 

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md

@@ -1,76 +0,0 @@
-# Supermicro X11SSW-F
-
-This section details how to run coreboot on the [Supermicro X11SSW-F].
-
-## Flashing coreboot
-
-Flashing was performed through the BMC web interface, when a valid license was entered.
-
-## Tested and working
-
-- SeaBIOS version 1.16.2 Payload loading Ubuntu 22.04, kernel 5.4.0-162-generic
-- ECC ram (Linux' ie31200 driver works)
-- USB ports
-- Ethernet
-- SATA ports
-- RS232 external
-- Left PCIe slot
-- BMC (IPMI)
-- VGA on Aspeed
-
-## Untested
-- Right PCIe slot
-- NVMe
-- TPM on TPM expansion header
-
-## Known issues
-
-- See general issue section
-- LNXTHERM missing
-- S3 resume not working
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Kaby Lake                                  |
-+------------------+--------------------------------------------------+
-| PCH              | Intel C236                                       |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel SPS (server version of the ME)             |
-+------------------+--------------------------------------------------+
-| Super I/O        | ASPEED AST2400                                   |
-+------------------+--------------------------------------------------+
-| Ethernet         | 2x Intel I210-AT 1 GbE                           |
-|                  | 1x dedicated BMC                                 |
-+------------------+--------------------------------------------------+
-| PCIe slots       | 1x 3.0 x16 (Left Riser)                          |
-|                  | 1x 3.0 x4  (Right Riser in x16)                  |
-|                  | 1x 3.0 x4  (NVMe)                                |
-+------------------+--------------------------------------------------+
-| USB slots        | 2x USB 2.0 (ext)                                 |
-|                  | 2x USB 3.0 (ext)                                 |
-|                  | 1x USB 3.0 (int)                                 |
-|                  | 1x dual USB 3.0 header                           |
-|                  | 2x dual USB 2.0 header                           |
-+------------------+--------------------------------------------------+
-| SATA slots       | 6x S-ATA III                                     |
-+------------------+--------------------------------------------------+
-| Other slots      | 1x RS232 (ext)                                   |
-|                  | 1x RS232 header                                  |
-|                  | 1x TPM header                                    |
-|                  | 1x Power SMB header                              |
-|                  | 6x PWM Fan connector                             |
-|                  | 1x Chassis Intrusion Header                      |
-+------------------+--------------------------------------------------+
-```
-
-## Extra links
-
-- [Supermicro X11SSW-F]
-- [Board manual]
-
-[Supermicro X11SSW-F]: https://www.supermicro.com/en/products/motherboard/x11ssw-f
-[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1784.pdf
-[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
-[IPMI]: ../../../../drivers/ipmi_kcs.md

Documentation/mainboard/system76/addw3.md

@@ -1,71 +0,0 @@
-# System76 Adder Workstation 3 (addw3)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP displays
-    - 15.6" 1920x1080@144Hz LCD
-    - 17.3" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
-- Networking
-  - Intel I219-V gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 280W (20V, 14A) DC-in port
-    - Included: Chicony A18-280P1A
-  - 73Wh 4-cell Lithium-Ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 (PCIe NVMe Gen 4) SSDs
-  - MicroSD card reader
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 1 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 2.71cm x 35.95cm x 23.8cm, 2.05kg
-  - 17": 2.82cm x 39.69cm x 26.2cm, 2.85kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U65) is above the battery connector.

Documentation/mainboard/system76/bonw15.md

@@ -1,65 +0,0 @@
-# System76 Bonobo Workstation 15 (bonw15)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4080
-    - NVIDIA GeForce RTX 4090
-  - eDP 17.3" 3840x2160@144Hz LCD (BOE NE173QUM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 2x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Onboard Intel Killer Ethernet E3100X 2.5 GbE
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 330W (19.5V, 16.42A) AC adapter (Chicony A20-330P1A)
-    - Rectangular connector; not a barrel connector
-  - 99Wh 8-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 3x M.2 PCIe NVMe Gen 4 SSDs
-- USB
-  - 2x USB Type-C with Thunderbolt 4
-  - 2x USB 3.2 Gen 2 Type-A
-- Dimensions
-  - 2.49cm x 39.6cm x 27.8cm, 3.29kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U58) is next to the left M.2 port.

Documentation/mainboard/system76/darp9.md

@@ -1,62 +0,0 @@
-# Syste76 Darter Pro 9 (darp9)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1340P
-  - Intel Core i7-1360P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 15.6" 1920x1080@60Hz LCD
-  - 1x HDMI
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Gigabit Ethernet (Realtek RTL8111H)
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U22) is above the left DIMM slot.

Documentation/mainboard/system76/galp7.md

@@ -1,58 +0,0 @@
-# System76 Galago Pro 7 (galp7)
-
-## Specs
-
-- CPU
-  - Intel Core i5-13500H
-  - Intel Core i7-13700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@144Hz LCD (Sharp LQ140M1JW49)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/mainboard/system76/gaze18.md

@@ -1,72 +0,0 @@
-# System76 Gazelle 18 (gaze18)
-
-## Specs
-
-- CPU
-  - Intel i9-13900H
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - NVIDIA GeForce RTX 3050 (70W TDP)
-  - Intel Irix Xe Graphics
-  - eDP displays
-    - 17.3" 1920x1080@144Hz LCD
-    - 15.6" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Realtek RTL8111H gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 150W AC barrel adapter
-    - Included: LiteOn PA-1151-76, using a C5 power cord
-  - 54Wh 4-cell battery (NP50BAT-4-54)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP audio
-- Storage
-  - 1x M.2 (PCIe NVMe Gen 4)
-  - 1x M.2 (PCIe NVMe Gen 3)
-  - MicroSD card reader
-    - Realtek RTS5227S
-- USB
-  - 2x USB 3.2 Gen 2 Type-C
-    - Does not support USB-C charging (USB-PD) or Thunderbolt
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
-  - 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U24) is right of the M.2 SSD connectors.

Documentation/mainboard/system76/lemp12.md

@@ -1,62 +0,0 @@
-# System76 Lemur Pro 12 (lemp12)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1335U
-  - Intel Core i7-1355U
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.0" 1920x1080@60Hz LCD (Innolux N140HCE-EN2)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Channel 0: 8-GB onboard DDR5 (Samsung M425R1GB4BB0-CQKOD)
-  - Channel 1: 8/16/32-GB DDR5 SO-DIMM @ 4800 MHz
-- Networking
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 65W (19V, 3.42A) AC adapter (AcBel ADA012)
-  - USB-C charging, compatible with 65W+ charger
-  - 73Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5 mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thudnerbolt 4
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 1.65cm x 32.2cm x 21.68cm, 1.15kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp11.md

@@ -1,66 +0,0 @@
-# System76 Oryx Pro 11 (oryp11)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - 16" 1920x1200@165Hz LCD
-  - External outputs:
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86)
-  - 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73)
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 2.1 Gen 1 Type-A
-- Dimensions
-  - 35.95cm x 27.3cm x 1.99cm, 2.7kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the memory slots.

Documentation/mainboard/system76/serw13.md

@@ -1,69 +0,0 @@
-# System76 Serval Workstation 13 (serw13)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP options:
-    - 15.6" 1920x1080@165Hz LCD (BOE NV156FHM-NY8)
-    - 17.6" 3840x2160@144Hz LCD (AUO B173ZAN03.0)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 280W (20V, 14A) AC adapter (Chicony A18-280P1A)
-  - 80Wh 6-cell Lithium-ion battery ()
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 15": 2.49cm x 35.8cm x 24.0cm, 2.4kg
-  - 17": 2.49cm x 39.6cm x 26.2cm, 2.8kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U46) is left of the memory slots.

Documentation/releases/boards_supported_on_branches.md

@@ -12,9 +12,9 @@ desired.
 
 Currently, [jenkins](https://qa.coreboot.org), our continuous
 integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, 4.18, and 4.19 branches.  Builders for other branches can be
+4.16, and 4.18 branches.  Builders for other branches can be created on
-added upon request.  Likewise, some releases are only marked with tags,
+request.  Likewise, some releases are only marked with tags, and
-and branches would need to be created to push new code.  These branches
+branches would need to be created to push new code to.  These branches
 can also be created on request.
 
 Patches can be backported from the master branch to any of these other
@@ -23,17 +23,6 @@ critical security fixes, but other patches will need to handled by
 anyone using that release.
 
 
-## [4.19 Release](coreboot-4.19-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| intel/icelake_rvp             | INTEL_ICELAKE          | 2018-10-26 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
 ## [4.18 Release](coreboot-4.18-relnotes.md)
 Branch created, builder configured
 
@@ -42,53 +31,29 @@ Branch created, builder configured
 | Vendor/Board                  | Processor              | Date added | Brd type  |
 +===============================+========================+============+===========+
 | amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
 +-------------------------------+------------------------+------------+-----------+
 ```

Documentation/releases/coreboot-24.02-relnotes.md

@@ -1,282 +0,0 @@
-Upcoming release - coreboot 24.02
-========================================================================
-
-The 24.02 release is scheduled for February 19, 2024. The next release,
-which will be 24.05, is scheduled for mid-May.
-
-The coreboot project is happy to announce our next release for February
-2024. Over the past three months, our contributors have focused on
-refining the coreboot codebase, generally prioritizing cleanup and
-quality enhancements. We extend our gratitude to all the contributors
-who have dedicated their time and expertise. Thank you for your
-invaluable contributions to this vital phase of maintenance and
-optimization.
-
-
-### Release number format update
-
-The previous release was the last to use the incrementing 4.xx release
-name scheme. For this and future releases, coreboot has switched to a
-Year.Month.Sub-version naming scheme. As such, the next release,
-scheduled for May of 2024 will be numbered 24.05, with the sub-version
-of 00 implied. If we need to do a fix or incremental release, we'll
-append the values .01, .02 and so on to the initial release value.
-
-
-### The master branch is being deleted
-
-The coreboot project changed from master to main roughly 6 months ago,
-and has been keeping the two branches in sync since then to ease the
-transition. As of this release, we are getting rid of the master branch
-completely. Please make sure any scripts you're using that reference the
-'master' branch have been switched to 'main'.
-
-
-
-Significant or interesting changes
-----------------------------------
-
-### acpi: Add Arm IO Remapping Table structures
-
-Input Output Remapping Table (IORT) represents the IO topology of an Arm
-based system.
-
-Document number: ARM DEN 0049E.e, Sep 2022
-
-
-### acpi: Add PPTT support
-
-This patch adds code to generate Processor Properties Topology Tables
-(PPTT) compliant to the ACPI 6.4 specification.
-
- - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is
-   selected. Its purpose is to return a pointer to a topology tree,
-   which describes the relationship between CPUs and caches. The hook
-   can be provided by, for example, mainboard code.
-
-Background: We are currently working on mainboard code for qemu-sbsa and
-Neoverse N2. Both require a valid PPTT table. Patch was tested against
-the qemu-sbsa board.
-
-
-### acpi: Add support for WDAT table
-
-This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
-Action Table) table specification. The WDAT is a special ACPI table
-introduced by Microsoft that describes the watchdog for the OS.
-
-Platforms that need to implement the WDAT table must describe the
-hardware watchdog management operations as described in the
-specification. See “Links to ACPI-Related Documents”
-(http://uefi.org/acpi) under the heading “Watchdog Action Table”.
-
-
-### lib/jpeg: Replace decoder with Wuffs' implementation
-
-To quote its repo[0]: Wuffs is a memory-safe programming language (and a
-standard library written in that language) for Wrangling Untrusted File
-Formats Safely. Wrangling includes parsing, decoding and encoding.
-
-It compiles its library, written in its own language, to a C/C++ source
-file that can then be used independently without needing support for the
-language. That library is now imported to src/vendorcode/wuffs/.
-
-This change modifies our linters to ignore that directory because it's
-supposed to contain the wuffs compiler's result verbatim.
-
-Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that
-implements our JPEG API. I further changed it a bit regarding data
-placement, dropped stuff from our API that wasn't ever used, or isn't
-used anymore, and generally made it fit coreboot a bit better. Features
-are Nigel's, bugs are mine.
-
-This commit also adapts our jpeg fuzz test to work with the modified
-API. After limiting it to deal only with approximately screen sized
-inputs, it fuzzed for 25 hours CPU time without a single hang or crash.
-This is a notable improvement over running the test with our old decoder
-which crashes within a minute.
-
-Finally, I tried the new parser with a pretty-much-random JPEG file I
-got from the internet, and it just showed it (once the resolution
-matched), which is also a notable improvement over the old decoder which
-is very particular about the subset of JPEG it supports.
-
-In terms of code size, a QEmu build's ramstage increases
-from 128060 bytes decompressed (64121 bytes after LZMA)
-  to 172304 bytes decompressed (82734 bytes after LZMA).
-
-[0] https://github.com/google/wuffs
-
-
-
-Additional coreboot changes
----------------------------
-
-* Rename Makefiles from .inc to .mk to better identify them
-* SPI: Add GD25LQ255E and IS25WP256D chip support
-* device: Add support for multiple PCI segment groups
-* device: Drop unused multiple downstream link support
-* device: Rename bus and link_list to upstream and downstream
-* Updated devicetree files for modern Intel platforms to use chipset.cb
-* Updated xeon-sp to use the coreboot allocator
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-* Add buildgcc support for Apple M1/M2 devices
-* crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
-* util/crossgcc: Update CMake from 3.26.4 to 3.27.7
-* util/kconfig: Uprev to Linux 6.7 kconfig
-
-
-### Git submodule pointers
-
-* /3rdparty/amd_blobs: Update from commit id e4519efca7 to 64cdd7c8ef
-  (5 commits)
-* /3rdparty/arm-trusted-firmware: Update from commit id 88b2d81345 to
-  17bef2248d (701 commits)
-* /3rdparty/fsp: Update from commit id 481ea7cf0b to 507ef01cce (16 commits)
-* /3rdparty/intel-microcode: Update from commit id 6788bb07eb to
-  ece0d294a2 (1 commits)
-* /3rdparty/vboot: Update from commit id 24cb127a5e to 3d37d2aafe (121
-  commits)
-
-
-### External payloads
-* payload/grub2: Update from 2.06 to 2.12
-* payload/seabios: Update from 1.16.2 to 1.16.3
-
-
-
-Platform Updates
-----------------
-
-### Added mainboards:
-* Google: Dita
-* Google: Xol
-* Lenovo: ThinkPad X230 eDP Mod (2K/FHD)
-
-
-### Removed Mainboards
-* Google ->  Primus4ES
-
-
-
-Statistics from the 4.22 to the 24.02 release
---------------------------------------------
-
-* Total Commits: 814
-* Average Commits per day: 8.65
-* Total lines added: 105203
-* Average lines added per commit: 129.24
-* Number of patches adding more than 100 lines: 46
-* Average lines added per small commit: 41.34
-* Total lines removed: 16505
-* Average lines removed per commit: 20.28
-* Total difference between added and removed: 88698
-* Total authors: 111
-* New authors: 19
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-* AMD chromebooks will not currently work with the signed vboot image.
-
-
-## Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-
-### coreboot-wide or architecture-wide issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 522 | 'region_overlap()' issues due to an integer overflow.           |
-+-----+-----------------------------------------------------------------+
-| 519 | make gconfig - could not find glade file                        |
-+-----+-----------------------------------------------------------------+
-| 518 | make xconfig - g++: fatal error: no input files                 |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Payload-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Platform-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 517 | lenovo x230 boot stuck with connected external monitor          |
-+-----+-----------------------------------------------------------------+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
-
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,7 +1,7 @@
-coreboot 4.19 release
+Upcoming release - coreboot 4.19
 ========================================================================
 
-The 4.19 release was completed on the 16th of January 2023.
+The 4.19 release is planned for the 16th of January 2023.
 
 Since the last release, the coreboot project has merged over 1600
 commits from over 150 authors. Of those authors, around 25 were
@@ -15,10 +15,6 @@ It takes constant effort to just stay afloat, let alone improve the
 codebase. Thank you very much to everyone who has contributed, both in
 this release and in previous times.
 
-Note that the first set of tarballs posted for the 4.19 release had
-bad timestamps. This has been fixed. Hashes for all tarballs are at
-the bottom of this document.
-
 The 4.20 release is planned for the 20th of April, 2023.
 
 
@@ -221,47 +217,17 @@ Significant Known and Open Issues
 ---------------------------------
 
 Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
+
-+-----+-----------------------------------------------------------------+
 | #   | Subject                                                         |
-+=====+=================================================================+
+|-----|-----------------------------------------------------------------|
 | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
 | 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
 | 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
 | 445 | Thinkpad X200 wifi issue                                        |
-+-----+-----------------------------------------------------------------+
 | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
 | 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
 | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
 | 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
 | 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
 | 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```
-
-Hashes for tarballs & signatures
---------------------------------
-
-Old tarballs:
-
-- a1f9ec1252a3cc19f0b4ba1a2b9d66ea9327499cbeecebd85377db7d5c68555d  coreboot-4.19.tar.xz
-- 6ceaa39429a2094d75e4c8a94615ae60664ddad7b4115570b65b9bb516cbd96d  coreboot-4.19.tar.xz.sig
-- 881a3477221d1b77e161759344df14eccda115086af3ef54e66485ae0eb2e5d9  coreboot-blobs-4.19.tar.xz
-- 16f4f1f7acc6203ce915ffea64edce8512bd9eb9e94e65db22a0cb5282a6e157  coreboot-blobs-4.19.tar.xz.sig
-
-New tarballs:
-
-- 65ccb2f46535b996e0066a1b76f81c8cf1ff3e27df84b3f97d8ad7b3e7cf0a43  coreboot-4.19.tar.xz
-- d3c52a209b8ccb49049960318f04f158dd47db52ebe6019d6a3dffe3196d9cbe  coreboot-4.19.tar.xz.sig
-- 30214caed07b25f11e47bec022ff6234841376e36689eb674de2330a3e980cbc  coreboot-blobs-4.19.tar.xz
-- 023d511d074703beab98c237c3e964dc7c598af86d5a0e2091195c68980b6c5d  coreboot-blobs-4.19.tar.xz.sig

Documentation/releases/coreboot-4.20-relnotes.md

@@ -0,0 +1,67 @@
+Upcoming release - coreboot 4.20
+========================================================================
+
+The 4.20 release is planned for the 20th of April 2023.
+
+
+The 4.21 release is planned for around the 17th of July, 2023
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+* This document may also be edited at the google doc copy:
+  https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
+
+Significant or interesting changes
+----------------------------------
+
+### Add changes that need a full description here
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+
+### Intel Quark SoC & Galileo mainboard
+
+The SoC Intel Quark is unmaintained and different efforts to revive it
+have so far failed.  The only user of this SoC ever was the Galileo
+board.
+
+Thus, to reduce the maintanence overhead for the community, support for
+the following components will be removed from the master branch and will
+be maintained on the release 4.20 branch.
+
+  * Intel Quark SoC
+  * Intel Galileo mainboard
+
+
+Statistics from the 4.19 to the 4.20 release
+--------------------------------------------
+
+* To be filled in immediately before the release by the release team
+
+
+Significant Known and Open Issues
+---------------------------------
+
+* To be filled in immediately before the release by the release team
+

Documentation/releases/coreboot-4.20.1-relnotes.md

@@ -1,265 +0,0 @@
-coreboot 4.20 release
-========================================================================
-
-The 4.20 release was done on May 15, 2023. Unfortunately, a licensing
-issues was found immediately after the release was completed, and it
-was decided to hold the release until that was fixed.
-
-Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
-4.20_branch will contain all code for 4.20, 4.20.1, and any further
-changes required for this release.
-
-The coreboot community has done a tremendous amount of work on the
-codebase over the last three and a half months. We've had over 1600
-commits in that time period, doing ongoing cleanup and improvement.
-
-It can be hard to remember at times how much the codebase really has
-improved, but looking back at coreboot code from previous years, it's
-really impressive the changes that have happened. We'd like to thank
-everyone who has been involved in these changes. It's great to work
-with everyone involved, from the people who make the small cleanup
-patches and review all of the incoming changes to the people working
-on new chipsets and SoCs. We'd additionally like to thank all of those
-individuals who make the effort to become involved and report issues
-or push even a single patch to fix a bug that they've noticed.
-
-Many thanks to everyone involved!
-
-We plan to get the 4.21 release done in mid August, 2023.
-
-
-Significant or interesting changes
-----------------------------------
-
-
-### cpu/mp_init.c: Only enable CPUs once they execute code
-
-On some systems the BSP cannot know how many CPUs are present in the
-system. A typical use case is a multi socket system. Setting the enable
-flag only on CPUs that actually exist makes it more flexible.
-
-
-### cpu/x86/smm: Add PCI resource store functionality
-
-In certain cases data within protected memory areas like SMRAM could
-be leaked or modified if an attacker remaps PCI BARs to point within
-that area. Add support to the existing SMM runtime to allow storing
-PCI resources in SMRAM and then later retrieving them.
-
-This helps prevent moving BARs around to get SMM to access memory in
-areas that shouldn't be accessed.
-
-
-### acpi: Add SRAT x2APIC table support
-
-For platforms using X2APIC mode add SRAT x2APIC table
-generation. This allows the setup of proper SRAT tables.
-
-
-### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
-
-This patch supports projects to use _DSM to control USB3 U1/U2
-transition per port.
-
-More details can be found in
-https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
-
-The ACPI and USB driver of linux kernel need corresponding functions
-to support this feature. Please see
-https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
-
-
-### drivers/efi: Add EFI variable store option support
-
-Add a driver to read and write EFI variables stored in a region device.
-This is particularly useful for EDK2 as payload and allows it to reuse
-existing EFI tools to set/get options used by the firmware.
-
-The write implementation is fault tolerant and doesn't corrupt the
-variable store. A faulting write might result in using the old value
-even though a 'newer' had been completely written.
-
-Implemented basic unit tests for header corruption, writing existing
-data and append new data into the store.
-
-Initial firmware region state:
-Initially the variable store region isn't formatted. Usually this is
-done in the EDK2 payload when no valid firmware volume could be found.
-It might be useful to do this offline or in coreboot to have a working
-option store on the first boot or when it was corrupted.
-
-Performance improvements:
-Right now the code always checks if the firmware volume header is valid.
-This could be optimised by caching the test result in heap. For write
-operations it would be good to cache the end of the variable store in
-the heap as well, instead of walking the whole store. For read
-operations caching the entire store could be considered.
-
-Reclaiming memory:
-The EFI variable store is append write only. To update an existing
-variable, first a new is written to the end of the store and then the
-previous is marked invalid. This only works on PNOR flash that allow to
-clear set bits, but keep cleared bits state.
-This mechanisms allows a fault tolerant write, but it also requires to
-"clean" the variable store from time to time. This cleaning would remove
-variables that have been marked "deleted".
-Such cleaning mechanism in turn must be fault tolerant and thus must use
-a second partition in the SPI flash as backup/working region.
-For now, cleaning is done in coreboot.
-
-Fault checking:
-The driver should check if a previous write was successful and if not
-mark variables as deleted on the next operation.
-
-
-### drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
-
-Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
-and prints EWL type 3 primarily associated with MRC training failures.
-
-
-### Toolchain updates
-
-* Upgrade MPC from version 1.2.1 to 1.3.1
-* Upgrade MPFR from version 4.1.1 to 4.2.0
-* Upgrade CMake from version 3.25.0 to 3.26.3
-* Upgrade LLVM from version 15.0.6 to 15.0.7
-* Upgrade GCC from version 11.2.0 to 11.3.0
-* Upgrade binutils from version 2.37 to 2.40
-
-
-Additional coreboot changes
----------------------------
-
-* Remove Yabits payload. Yabits is deprecated and archived.
-* Add DDR2 support to Intel GM45 code.
-* Fix superiotool compilation issues when using musl-libc.
-* Drop the Python 2 package from the coreboot-sdk.
-* Drop the Zephyr SDK from coreboot-sdk since the packaged version
-  was quite old and wasn’t really used.
-* Add inteltool support for the Intel "Emmitsburg" PCH.
-* Work to improve cache hit percentage when rebuilding using ccache.
-* Adding Sound-Open-Firmware drivers to chromebooks to enable audio on
-  non-chrome operating systems.
-* Improve and expand ACPI generation code.
-* Fix some issues for the RISC-V code.
-* Continue upstreaming the POWER9 architecture.
-* Add documentation for SBOM (Software Bill of Materials).
-* Add SimNow console logging support for AMD.
-* Do initial work on Xeon SPR
-* CMOS defaults greater than 128 bytes long now extend to bank 1.
-
-
-New Mainboards
---------------
-
-* Asrock: B75M-ITX
-* Dell: Latitude E6400
-* Google: Aurash
-* Google: Boxy
-* Google: Constitution
-* Google: Gothrax
-* Google: Hades
-* Google: Myst
-* Google: Screebo
-* Google: Starmie
-* Google: Taranza
-* Google: Uldren
-* Google: Yavilla
-* HP: EliteBook 2170p
-* Intel: Archer City CRB
-* Intel: DQ67SW
-* Protectli: VP2420
-* Protectli: VP4630/VP4650
-* Protectli: VP4670
-* Siemens: MC EHL4
-* Siemens: MC EHL5
-* System76: lemp11
-* System76: oryp10
-* System76: oryp9
-
-
-Removed Mainboards
-------------------
-
-* Intel Icelake U DDR4/LPDDR4 RVP
-* Intel Icelake Y LPDDR4 RVP
-* Scaleway TAGADA
-
-
-Updated SoCs
-------------
-
-* Removed soc/intel/icelake
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-have so far failed.  The only user of this SoC ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.19 to the 4.20 release
---------------------------------------------
-
-Total Commits: 1630
-Average Commits per day: 13.72
-Total lines added: 102592
-Average lines added per commit: 62.94
-Number of patches adding more than 100 lines: 128
-Average lines added per small commit: 37.99
-Total lines removed: 34824
-Average lines removed per commit: 21.36
-Total difference between added and removed: 67768
-Total authors: ~170
-New authors: ~35
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```

Documentation/releases/coreboot-4.21-relnotes.md

@@ -1,407 +0,0 @@
-Upcoming release - coreboot 4.21
-========================================================================
-
-The 4.21 release is scheduled for August 21st, 2023
-
-In the past quarter year, the coreboot project has gotten over 1200 new
-patches from around 140 authors, 20 of whom contributed for the first
-time.
-
-Thank you to all of our donors, the code contributors, the people who
-take time to review all of those patches and all of the people who care
-about the coreboot project. There have been a number of new companies
-starting to use coreboot recently, and we appreciate all of the
-contributions and support.
-
-### Upcoming switch from master branch to main branch
-
-Historically, the initial branch that was created in a new git
-repository was named ‘master’. In line with many other projects,
-coreboot has decided to switch away from this name and use the name
-‘main’ instead. You can read about the initial reasoning on the SFC’s
-website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
-
-At some point before the 4.22 release, coreboot will be switching from
-the master branch to the main branch. This shouldn’t be a difficult
-change for most people, as everyone will just have to rebase on top of
-a different branch name.
-
-We’ve already created the main branch, and it is currently synced with
-the master branch. Please update any scripts to point to main instead
-of master.
-
-At the point of the changeover, we will move all patches in gerrit to
-the main branch and disable pushes to the master branch.
-
-After the switch, we will sync the main branch to the master branch for
-a while to give people a little more time to update any scripts that
-are currently pointed at the master branch. Note that this update will
-probably be done just once per day, and the frequency of updates will
-be decreased over time. We plan to stop updating the master branch
-following the 4.22 release.
-
-Significant or interesting changes
-----------------------------------
-
-### lib: Support localized text of memory_training_desc in ux_locales.c
-
-Most of the text in coreboot is for logging, and does not use
-localization. There are however, some bits of text that can be
-presented to the user, and this patch supplies a method to localize
-them.
-
-To support the localized text, we need to get the locale id by vboot
-APIs and read raw string content file: preram_locales located at either
-RO or RW.
-
-The preram_locales file follows the format:
-
-    [PRERAM_LOCALES_VERSION_BYTE (\x01)]
-    [string_name_1] [\x00]
-    [locale_id_1] [\x00] [localized_string_1] [\x00]
-    [locale_id_2] [\x00] [localized_string_2] …
-    [\x01]
-    [string_name_2] [\x00] ...
-
-This code will search for the correct localized string that its string
-name is `memory_training_desc` and its locale ID matches the ID vb2api
-returns. If no valid string found, we will try to display in English
-(locale ID 0).
-
-
-### Improved the bootsplash support
-
-The JPEG decoder, that was added many years ago to display a bootsplash
-in coreboot, has a few quirks. People used to do some voodoo with GIMP
-to convert images to the right format, but we can also achieve the same
-with ImageMagick's `convert`. The currently known constraints are:
-
-* The framebuffer's color format is ignored,
-* only YCC 4:2:0 color sampling is supported, and
-* width and height have to be a multiple of 16 pixels.
-
-Beside that, we can only display the bootsplash if it completely fits
-into the framebuffer. As the latter's size is often decided at runtime,
-we can't do much more than offering an option to set a specific size.
-
-The build system has been extended so that the necessary adjustments to
-the picture can be done by it and several options have been added to
-Kconfig.
-
-
-### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
-
-This is a complete rewrite of the UHCI root-hub driver, based on the
-xHCI one. We are doing things by the book as far as possible. One
-special case is uhci_rh_reset_port() which does the reset sequencing
-that usually the hardware would do.
-
-This abandons some quirks of the old driver:
-* Ports are not disabled/re-enabled for every attachment anymore.
-* We solely rely on the Connect Status Change bit to track changes.
-* Further status changes are now deferred to the next polling round.
-
-
-### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
-
-Translate the coreboot framebuffer info from coreboot tables to the
-Linux zero page.
-
-To support full 64-bit addresses, there is a new field `ext_lfb_base`
-since Linux 4.1. It is unclear, however, how a loader is supposed to
-know if the kernel is compatible with this. Filling these previously
-reserved bits doesn't hurt, but an old kernel would probably ignore
-them and not know that it's handling a clipped, invalid address. So we
-play safe, and only allow 64-bit addresses for kernels after the 2.15
-version bump of the boot protocol.
-
-
-### arch/x86: Don't allow hw floating point operations
-
-Even though coreboot does not allow floating point operations, some
-compilers like clang generate code using hw floating point registers,
-e.g. SSE %XMMx registers on 64bit code by default. Floating point
-operations need to be enabled in hardware for this to work (CR4). Also
-in SMM we explicitly need to save and restore floating point registers
-for this reason. If we instruct the compiler to not generate code with
-FPU ops, this simplifies our code as we can skip that step.
-
-With clang this reduces the binary size a bit. For instance ramstage
-for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
-decompressed to 212768 bytes.
-
-Since we now explicitly compile both ramstage and smihandler code
-without floating point operations and associated registers we don't
-need to save/restore floating point registers in SMM.
-
-The EFER MSR is in the SMM save state and RSM properly restores it.
-Returning to 32bit mode was only done so that fxsave was done in the
-same mode as fxrstor, but this is no longer done.
-
-
-### Caching of PCIe 5.0 HSPHY firmware in SPI flash
-
-This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
-flash. A new flashmap region is created for that purpose. The goal of
-caching is to reduce the dependency on the CSME (Converged Security and
-Management Engine) and the HECI (Host Embedded Controller Interface) IP
-LOAD command which may fail when the CSME is disabled, e.g. soft
-disabled by HECI command or HAP (High Assurance Platform mode). By
-caching that firmware, this allows the PCIe 5.0 root ports to keep
-functioning even if CSME/HECI is not functional.
-
-
-### Extracting of TPM logs using cbmem tool
-
-CBMEM can contain logs in different forms (at most one is present):
- * coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
-   LB_TAG_TPM_CB_LOG)
- * TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
- * TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
-
-The last two follow specifications by Trusted Computing Group, but
-until now cbmem couldn't print them.
-
-These changes make the cbmem utility check for existence of TPM1.2/TPM2
-logs in CBMEM and add code necessary for parsing and printing of their
-entries.
-
-`cbmem -L` for CONFIG_TPM1=y case
-
-```
-TCPA log:
-	Specification: 1.21
-	Platform class: PC Client
-TCPA log entry 1:
-	PCR: 2
-	Event type: Action
-	Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
-	Event data: FMAP: FMAP
-```
-
-`cbmem -L` for CONFIG_TPM2=y case
-
-```
-TPM2 log:
-	Specification: 2.00
-	Platform class: PC Client
-TPM2 log entry 1:
-	PCR: 2
-	Event type: Action
-	Digests:
-		 SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
-	Event data: FMAP: FMAP
-```
-
-
-### soc/amd: read domain resource window configuration from hardware
-
-Read the MMIO and IO decode windows for the PCI root complex and the
-PCI bus number range decoded to the PCI root complex from the data
-fabric registers and pass the information to the resource allocator so
-it has the correct constraints to do its job. Also generate the
-corresponding ACPI resource producers in the SSDT so that the OS knows
-about this too. This is required for the upcoming USB 4 support.
-
-
-Additional coreboot changes
----------------------------
-
-* Added SPDX headers to more files to help automated license checking.
-  The linter has been enabled to check the Makefiles as well.
-* Cleaned up Kconfig files and source code.
-* Enabled acpigen to generate tables for SPCR (Serial Port Console
-  Redirection) and GTDT (Generic Timer Description Table).
-* The resource allocation above the 4GiB boundary has been improved.
-* Most of the code has been adjusted to make use of C99 flexible arrays
-  instead of one-element or zero-length arrays.
-* Additional Dockerfiles based on Arch and Alpine Linux have been added
-  to build-test with alternate build environments, including musl-libc.
-  They are very basic at the moment and not equal to the coreboot-sdk.
-  They will be extended in the future.
-* Added support for ITE IT8784E to superiotool.
-* Added support for Intel 700 chipset series to inteltool and a build
-  issue with musl–libc has been fixed.
-* Added support for Intel 800 chipset series to ifdtool.
-* The coreboot-sdk container has been extended so that it allows
-  extracting the MRC binary from Haswell-based ChromeOS firmware images.
-* From now on POST code preprocessor macros should have a POSTCODE
-  prefix following the name of the POST code.
-* The NASM compiler provided by the coreboot toolchain wasn’t properly
-  integrated into xcompile and thus it wasn’t used by the build system.
-  Instead, it was required to install NASM on the host in order to use
-  it. This has been fixed.
-* The time measurement done in abuild got improved and also an issue
-  has been fixed when the variant name contains hyphens.
-* The RISC-V code was enabled to build with Clang.
-* Initial work has been done to transform Camelcase options to
-  Snakecase.
-* The buildgcc script is now able to just fetch the tarballs if desired,
-  which is needed for reproducible build environments for example.
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain
-
-* binutils
-  * Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
-* Upgrade IASL from 20221020 to 20230628
-* Upgrade LLVM from 15.0.7 to 16.0.6
-* Upgrade NASM from 2.15.05 to 2.16.01
-  * Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
-* Upgrade CMake from 3.26.3 to 3.26.4
-* Upgrade GCC from 11.3.0 to 11.4.0
-  * Added gcc-11.4.0_rv32iafc.patch
-
-
-### Git submodule pointers
-
-#### /3rdparty
-* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
-* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
-(851 commits)
-* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
-* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
-* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
-commits)
-* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
-commits)
-* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
-* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
-* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
-
-#### /util
-* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
-* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
-commit)
-
-
-### External payloads
-
-* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
-* Upgrade EDK2-MrChromebox from version 202304 to version 202306
-* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
-* Update tint from version 0.05 to version 0.07
-* Update U-Boot from version 2021.07 to version v2023.07
-
-
-Added mainboards:
------------------
-* ByteDance ByteDance bd_egs
-* Google: Craaskov
-* Google: Expresso
-* Google: Karis
-* Google: Karis4ES
-* Google: Pirrha
-* Google: Ponyta
-* Google: Screebo4ES
-* Google: Ovis
-* Google: Ovis4ES
-* Google: Rex EC ISH
-* Google: Rex4ES
-* HP Compaq Elite 8300 USDT
-* HP EliteBook 820 G2
-* IBM SBP1
-* Intel Raptorlake silicon with Alderlake-P RVP
-* Inventec Transformers
-* MSI PRO Z790-P (WIFI)
-* MSI PRO Z790-P (WIFI) DDR4
-* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
-* System76 addw3
-* System76 bonw15
-* System76 darp9
-* System76 galp7
-* System76 gaze17 3050
-* System76 gaze17 3060-b
-* System76 gaze18
-* System76 lemp12
-* System76 oryp11
-* System76 serw13
-
-
-Removed Mainboards
-------------------
-
-* Intel Galileo
-
-
-Updated SoCs
-------------
-
-* Removed src/soc/intel/quark
-
-
-Statistics from the 4.20 to the 4.21 release
---------------------------------------------
-
-* Total Commits: 1252
-* Average Commits per day: 12.59
-* Total lines added: 317734
-* Average lines added per commit: 253.78
-* Number of patches adding more than 100 lines: 86
-* Average lines added per small commit: 36.22
-* Total lines removed: 261063
-* Average lines removed per commit: 208.52
-* Total difference between added and removed: 56671
-
-* Total authors: 143
-* New authors: 21
-
-
-Significant Known and Open Issues
----------------------------------
-
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* IRC: https://web.libera.chat/#coreboot
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.22-relnotes.md

@@ -1,349 +0,0 @@
-coreboot 4.22 & 4.22.01 releases
-========================================================================
-
-The next release is planned for the 19th of February, 2024
-
-These notes cover the latest updates and improvements to coreboot over
-the past three months. A big thank you to the returning contributors as
-well as the 14 individuals who committed code for the first time. We
-greatly appreciate everyone's dedication and expertise. As with past
-releases, this one reflects a commitment to open source innovation,
-security enhancements, and expanding hardware support.
-
-
-### 4.22.01 release
-
-The week between tagging a release and announcing it publicly is used
-to test the tagged version and make sure everything is working as we
-expect. This is done instead of freezing the tree and doing release
-candidates before the release.
-
-For the 4.22 release cycle we found an uninitialized variable error on
-the sandybridge/ivybridge platforms and rolled that into the 4.22.01
-release package.
-
-### coreboot version naming update
-
-This release is the last release to use the incrementing 4.xx release
-name scheme. For future releases, coreboot is switching to a
-Year.Month.Sub-version naming scheme. As such, the next release,
-scheduled for February of 2024 will be numbered 24.02, with the
-sub-version of 00 implied. If we need to do a fix or future release of
-the 24.02 release, we'll append the values .01, .02 and so on to the
-initial release value.
-
-
-### coreboot default branch update
-
-Immediately after the 4.21 release, the coreboot project changed the
-default git branch from 'master' to 'main'. For the first couple of
-months after the change, The master branch was synced with the main
-branch several times a day, allowing people time to update any scripts.
-As of 2023-11-01, the sync rate has slowed to once a week. This will
-continue until the next release, at which time the master branch will
-be removed.
-
-
-
-Significant or interesting changes
-----------------------------------
-
-### x86: support .data section for pre-memory stages
-
-x86 pre-memory stages did not support the `.data` section and as a
-result developers were required to include runtime initialization code
-instead of relying on C global variable definitions.
-
-Other platforms do not have that limitation. Hence, resolving it helps
-to align code and reduce compilation-based restrictions (cf. the use of
-`ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot
-code).
-
-There were three types of binary to consider:
-1. eXecute-In-Place pre-memory stages
-2. `bootblock` stage is a bit different as it uses Cache-As-Ram but
-   the memory mapping and its entry code different
-3. pre-memory stages loaded in and executed from Cache-As-RAM
-   (cf. `CONFIG_NO_XIP_EARLY_STAGES`).
-
-eXecute-In-Place pre-memory stages (#1) rely on a new ELF segment as
-the code segment Virtual Memory Address and Load Memory Address are
-identical but the data needs to be linked in cache-As-RAM (VMA) to be
-stored right after the code (LMA).
-
-`bootblock` (#2) also uses this new segment to store the data right
-after the code and it loads it to Cache-As-RAM at runtime. However, the
-code involved is different.
-
-Not eXecute-In-Place pre-memory stages (#3) did not need any special
-work other than enabling a .data section as the code and data VMA / LMA
-translation vector is the same.
-
-Related important commits:
-- c9cae530e5 ("cbfstool: Make add-stage support multiple ignore sections")
-- 79f2e1fc8b ("cbfstool: Make add-stage support multiple loadable segments")
-- b7832de026 ("x86: Add .data section support for pre-memory stages")
-
-
-### x86: Support CBFS cache for pre-memory stages and ramstage
-
-The CBFS cache scratchpad offers a generic way to decompress CBFS files
-through the cbfs_map() function without having to reserve a per-file
-specific memory region.
-
-CBFS cache x86 support has been added to pre-memory stages and
-ramstage.
-
-1. **pre-memory stages**: The new `PRERAM_CBFS_CACHE_SIZE` Kconfig can
-   be used to set the pre-memory stages CBFS cache size. A cache size
-   of zero disables the CBFS cache feature for all pre-memory stages.
-   The default value is 16 KiB which seems a reasonable minimal value
-   enough to satisfy basic needs such as the decompression of a small
-   configuration file. This setting can be adjusted depending on the
-   platform's needs and capabilities.
-
-   Note that we have set this size to zero for all the platforms
-   without enough space in Cache-As-RAM to accommodate the default
-   size.
-
-2. **ramstage**: The new `RAMSTAGE_CBFS_CACHE_SIZE` Kconfig can be used
-   to set the ramstage CBFS cache size. A cache size of zero disables
-   the CBFS cache feature for ramstage. Similarly to pre-memory stages
-   support, the default size is 16 KiB.
-
-   As we want to support the S3 suspend/resume use case, the CBFS cache
-   memory cannot be released to the operating system and therefore
-   cannot be an unreserved memory region. The ramstage CBFS cache
-   scratchpad is defined as a simple C static buffer as it allows us to
-   keep the simple and robust design of the static initialization of
-   the `cbfs_cache` global variable (cf. src/lib/cbfs.c).
-
-   However, since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR`
-   Kconfig) already define a `_cbfs_cache` region we also introduced a
-   `POSTRAM_CBFS_CACHE_IN_BSS` Kconfig to gate the use of a static
-   buffer as the CBFS cache scratchpad.
-
-
-### Allow romstage to be combined into the bootblock
-
-Having a separate romstage is only desirable:
- - with advanced setups like vboot or normal/fallback
- - boot medium is slow at startup (some ARM SOCs)
- - bootblock is limited in size (Intel APL 32K)
-
-When this is not the case there is no need for the extra complexity
-that romstage brings. Including the romstage sources inside the
-bootblock substantially reduces the total code footprint. Often the
-resulting code is 10-20k smaller.
-
-This is controlled via a Kconfig option.
-
-
-### soc/intel/cmn/gfx: Add API to report presence of external display
-
-This implements an API to report the presence of an external display on
-Intel silicon. The API uses information from the transcoder and
-framebuffer to determine if an external display is connected.
-
-For example, if the transcoder is attached to any DDI ports other than
-DDI-A (eDP), and the framebuffer is initialized, then it is likely that
-an external display is present.
-
-This information can be used by payloads to determine whether or not to
-power on the display, even if eDP is not initialized.
-
-
-### device/pci_rom: Set VBIOS checksum when filling VFCT table
-
-AMD's Windows display drivers validate the checksum of the VBIOS data
-in the VFCT table (which gets modified by the FSP GOP driver), so
-ensure it is set correctly after copying the VBIOS into the table if
-the FSP GOP driver was run. Without the correct checksum, the Windows
-GPU drivers will fail to load with a code 43 error in Device Manager.
-
-
-
-Additional coreboot changes
----------------------------
-
-* Move all 'select' statements from Kconfig.name files to Kconfig
-* acpigen now generates variable-length PkgLength fields instead of a
-  fixed 3-byte size to improve compatibility and to bring it in line
-  with IASL
-* Work to allow Windows to run on more Chromebooks
-* General cleanup and reformatting
-* Add initial AMD openSIL implementation
-* Add ACPI table generation for ARM64
-* Stop resetting CMOS during s3 resume even if marked as invalid
-* Comply with ACPI specification by making _STR Unicode strings
-* Fix SMM get_save_state calculation, which was broken when STM was
-  enabled
-* SNB+MRC boards: Migrate MRC settings to devicetree
-* Work on chipset devicetrees for all platforms
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain updates
-
-* Upgrade GMP from 6.2.1 to 6.3.0
-* Upgrade binutils from 2.40 to 2.41
-* Upgrade MPFR from 4.2.0 to 4.2.1
-
-
-### Git submodule pointers
-
-* amd_blobs: Update from commit id 6a1e1457af to e4519efca7 (16
-  commits)
-* arm-trusted-firmware: Update from commit id 37366af8d4 to 88b2d81345
-  (214 commits)
-* fsp: Update from commit id 3beceb01f9 to 481ea7cf0b (15 commits)
-* intel-microcode: Update from commit id 6f36ebde45 to 6788bb07eb (1
-  commit)
-* vboot: Update from commit id 0c11187c75 to 24cb127a5e (24 commits)
-* genoa_poc/opensil: New submodule updated to 0411c75e17 (41 commits)
-
-
-### External payloads
-
-* U-Boot: Use github mirror and the latest version
-* edk2: Update default branch for MrChromebox repo to 2023-09
-
-
-
-Platform Updates
-----------------
-
-### Added 17 mainboards
-
-* AMD Onyx
-* Google: Anraggar
-* Google: Brox
-* Google: Chinchou
-* Google: Ciri
-* Google: Deku
-* Google: Deku4ES
-* Google: Dexi
-* Google: Dochi
-* Google: Nokris
-* Google: Quandiso
-* Google: Rex4ES EC ISH
-* Intel: Meteorlake-P RVP with Chrome EC for non-Prod Silicon
-* Purism Librem 11
-* Purism Librem L1UM v2
-* Siemens FA EHL
-* Supermicro X11SSW-F
-
-
-### Added 1 SoC
-
-* src/soc/amd/genoa
-
-
-
-Statistics from the 4.21 to the 4.22 release
---------------------------------------------
-
-* Total Commits: 977
-* Average Commits per day: 10.98
-* Total lines added: 62993
-* Average lines added per commit: 64.48
-* Number of patches adding more than 100 lines: 60
-* Average lines added per small commit: 37.55
-* Total lines removed: 30042
-* Average lines removed per commit: 30.75
-* Total difference between added and removed: 32951
-* Total authors: 135
-* New authors: 14
-
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-### Payload-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 496 | Missing malloc check in libpayload                              |
-+-----+-----------------------------------------------------------------+
-| 484 | No USB keyboard support with secondary payloads                 |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-```
-
-
-### Platform-specific issues
-
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 509 | SD Card hotplug not working on Apollo Lake                      |
-+-----+-----------------------------------------------------------------+
-| 507 | Windows GPU driver fails on Google guybrush & skyrim boards     |
-+-----+-----------------------------------------------------------------+
-| 506 | APL/GML don't boot OS when CPU microcode included "from tree"   |
-+-----+-----------------------------------------------------------------+
-| 505 | Harcuvar CRB - 15 of 16 cores present in the operating system   |
-+-----+-----------------------------------------------------------------+
-| 499 | T440p - EDK2 fails with RESOURCE_ALLOCATION_TOP_DOWN enabled    |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney Chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio not present in Windows after libgfxinit   |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-```
-
-
-
-Plans for the next release
---------------------------
-
-* Finish adding chipset device trees for all SOCs
-* Improve code for options/setup
-* Start reformatting C files with clang-format
-* Add warning/error step for Makefiles at the end
-
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Website: https://www.coreboot.org
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [24.02 - February 2024](coreboot-24.02-relnotes.md)
+* [4.20 - April 2023](coreboot-4.20-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,28 +15,25 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.22 - November 2023](coreboot-4.22-relnotes.md)
+* [4.19 - January 2023](coreboot-4.19-relnotes.md)
-* [4.21   - August 2023](coreboot-4.21-relnotes.md)
+* [4.18 - October 2022](coreboot-4.18-relnotes.md)
-* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
+* [4.17 - May 2022](coreboot-4.17-relnotes.md)
-* [4.19   - January 2023](coreboot-4.19-relnotes.md)
+* [4.16 - February 2022](coreboot-4.16-relnotes.md)
-* [4.18   - October 2022](coreboot-4.18-relnotes.md)
+* [4.15 - November 2021](coreboot-4.15-relnotes.md)
-* [4.17   - May 2022](coreboot-4.17-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
-* [4.16   - February 2022](coreboot-4.16-relnotes.md)
+* [4.13 - November 2020](coreboot-4.13-relnotes.md)
-* [4.15   - November 2021](coreboot-4.15-relnotes.md)
+* [4.12 - May 2020](coreboot-4.12-relnotes.md)
-* [4.14   - May 2021](coreboot-4.14-relnotes.md)
+* [4.11 - November 2019](coreboot-4.11-relnotes.md)
-* [4.13   - November 2020](coreboot-4.13-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
-* [4.12   - May 2020](coreboot-4.12-relnotes.md)
+* [4.9 - December 2018](coreboot-4.9-relnotes.md)
-* [4.11   - November 2019](coreboot-4.11-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
-* [4.10   - July 2019](coreboot-4.10-relnotes.md)
+* [4.7 - January 2018](coreboot-4.7-relnotes.md)
-* [4.9    - December 2018](coreboot-4.9-relnotes.md)
+* [4.6 - April 2017](coreboot-4.6-relnotes.md)
-* [4.8.1  - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.5 - October 2016](coreboot-4.5-relnotes.md)
-* [4.7    - January 2018](coreboot-4.7-relnotes.md)
+* [4.4 - May 2016](coreboot-4.4-relnotes.md)
-* [4.6    - April 2017](coreboot-4.6-relnotes.md)
+* [4.3 - January 2016](coreboot-4.3-relnotes.md)
-* [4.5    - October 2016](coreboot-4.5-relnotes.md)
+* [4.2 - October 2015](coreboot-4.2-relnotes.md)
-* [4.4    - May 2016](coreboot-4.4-relnotes.md)
+* [4.1 - July 2015](coreboot-4.1-relnotes.md)
-* [4.3    - January 2016](coreboot-4.3-relnotes.md)
-* [4.2    - October 2015](coreboot-4.2-relnotes.md)
-* [4.1    - July 2015](coreboot-4.1-relnotes.md)
 
 
 [checklist]: checklist.md

Documentation/rmodules.md

@@ -1,81 +0,0 @@
-# Relocatable Modules (rmodules)
-
-Relocatable modules are currently only used on x86.  Relocatable
-modules are executables. Exectuables which can be executed anywhere in
-memory. Anywhere means that the module does not need to be executed
-at a defined memory address which is known at build/link time. For
-coreboot stages like bootblock and romstage it is known at build
-time at which addresses they are executed.  For some exectuables it
-is however not known at which specific address they are executed in
-runtime (for example postcar and ramstage). Relocateable modules
-usually allocate the space for the modules just before they are
-supposed to be executed. After enough space is allocated, CBMEM will
-return the location of the allocated space. Now the relocation can be
-done by fixing up all relocation entries in the relocatable module
-based on the location of the binary (which was returned by CBMEM
-at runtime).
-
-# Implementation Details
-
-## build time
-
-At build time the rmodtool (util/cbfstool/rmodtool.c) is used to
-create relocatable modules. The rmodtool basically takes an ELF
-file as an input and writes an ELF as output. It basically does
-a simple conversion from one ELF file to another slighty changed
-ELF file. First the tool makes sure that the ELF file fits a few
-requirements. For example there can only be one segment (loadable
-program header) in the input ELF file. After that it goes through
-the ELF relocation table and takes any entry that applies to the one
-segment we want to load at runtime. The rmodtool will then write all
-these relocation entires in a new ELF section called ".reloc". After
-that the ELF relocation table will be cleared.
-
-One can split the rmodules in two different kinds:
-1. coreboot stages (postcar, ramstage)
-2. simple binaries (smm, smmstub, sipi\_vector)
-
-They are actually handled the same by the build system and only differ
-in the fact, that they are either coreboot stages or they are not.
-
-In the end the ELF files will have three different ELF sections,
-which are all created by the rmodtool.
-1. relocation header (.header)
-2. program (.program)
-3. relocation entries (.relocs)
-
-## runtime
-
-Either rmodule\_load (lib/rmodule.c) is used directly or through the
-rmodule\_stage\_load (lib/rmodule.c) wrapper. It is used to load the
-stages (postcar and ramstage) or small programs like (sipi\_vector,
-smm, smmstub) into memory before jumping to them. In the case of a
-coreboot stage, CBMEM is used to allocate space for the stage in memory
-via the rmodule\_cbfs\_allocater (lib/rmodule.c). At this point the
-location of the stage in memory is known and all relocation (address
-fixups) need to be done now. This is basically just a simple loop that
-goes through each relocation entry. Each relocation entry is just an
-address pointing to a location that needs relocation. The relocation
-itself is just a simple addition, that adds an offset from where the
-image was "supposed" to be at link time, to where it is now relocated.
-
-## module\_parameters
-
-module\_parameters is a section inside the rmodule ELF file. Its
-basically a way to pass runtime information to an rmodule
-before jumping to it. The caller will use rmodule\_parameters()
-(lib/rmodule.c) to get the runtime address of the module\_parameters
-and the callee (the rmodule itself) usually appends the section to
-specific types via compiler attributes. For example:
-```
-static const
-volatile __attribute((aligned(4), __section__(".module_parameters")))
-struct smm_runtime smm_runtime;
-```
-
-# x86 why rmodules
-//TODO
-x86: postcar and ramstage cannot conflict with payload regarding
-memory placement. Therefore payload location is usually fixed and
-postcar/ramstage can be placed at a location in memory that is
-figured out at runtime.

Documentation/sbom/sbom.md

@@ -1,156 +0,0 @@
-# Software Bill of Materials (SBOM)
-
-SBOM is a collection of information of each software component
-you are supplying/building. Similar to a package manager on Linux
-based systems, it holds information of as many software parts as
-possible. This information can be a version, name of the software, URL,
-license information and more. A SBOM can be saved in various formats.
-In coreboot it's saved as "uSWID" file. uSWID is not a standard or
-specification but it doesn't need to be, since it's basically just an
-array/list of CoSWID (Concise Software Identification) files which in
-turn are specified by a RFC specification. CoSWID files are saved in a
-CBOR format. CBOR is like JSON if JSON were a binary format. Similar
-to a package manager the CoSWID format can link multiple softwares
-together. For example on most modern Intel systems FSP is included as
-a dependency of coreboot. That kind of relationship between software
-components (among others) can be expressed in an uSWID file. That makes
-firmware/software much more transparent. One could for example create a
-software that takes a coreboot firmware image as input and
-automatically creates a graph with all software components the coreboot
-image contains and their relationship to each other.
-
-
-## SWID/CoSWID
-
-SWID is a standard hidden behind an ISO paywall.
-It generally identifies/describes Software components. Since SWID files
-are written in XML, they can get too large for devices with network and
-storage constraints. CoSWID is basically SWID but in CBOR binary
-format, which makes it far smaller compared to its big brother. Also,
-CoSWID is a RFC specification (so publicly accessible). Therefore
-CoSWID is the standard used in coreboot SBOM. But one CoSWID file/tag
-can only describe one single software, but since software is usually
-composed of multiple parts (especially in firmware with many binary
-blobs) uSWID was born as a container format to hold multiple CoSWID
-files. It also has a magic value, that makes software capable of
-extracting uSWID/CoSWID data without the need to understand the
-underlying format of the binary (in coreboot it's the CBFS and in EDK2
-it's the COFF). To get a simple overview of how a SWID/CoSWID file
-looks like, just take a look at the various "templates" in src/sbom/.
-There are of course other SBOM specifications out there, but most of
-them are rather blown up and don't support a binary format at all.
-
-
-## coreboot implementation
-
-Quick overview of how things are generated:
-
-![Generation of an SBOM File in coreboot][sbom_generation]
-
-[sbom_generation]: sbom_generation.svg
-
-After all SBOM data has been fetched from all the software components,
-the 'goswid' tool links them all together into one sbom.uswid file.
-Therefore the goswid tool is basically a linker that takes multiple
-CoSWID/SWID files and converts them into one uSWID file. Although the
-image shows only Files in JSON format it is also possible to supply
-them in XML or CBOR format.
-
-The final SBOM file is located inside the CBFS.
-For each software component in coreboot SBOM, there is an option in
-Kconfig (usually called `CONFIG_INCLUDE_[software-name]_SBOM`) to either
-include or not include SBOM metadata for the specified software.
-Furthermore there is a `CONFIG_SBOM_[software-name]_PATH` option which
-contains a path to a SWID/CoSWID file in a format of choice
-(being either JSON, XML or CBOR). `CONFIG_SBOM_[software-name]_PATH`
-option usually defaults to a very generic CoSWID file in JSON format
-(which are stored in src/sbom/). That at least gives minimal
-information like the name of the software and maybe a version.
-But it is always preferred, that the `CONFIG_SBOM_[software-name]_PATH`
-is set to a custom CoSWID/SWID file that contains much more information
-(like version/commit-hash, license, URL, dependencies, ...).
-Therefore using the defaults is by any means to be avoided, since they
-hold very little information or even worse wrong information.
-Furthermore some of these Kconfig options have a suboption
-(usually called `CONFIG_SBOM_[software-name]_GENERATE`) to generate
-some basic SBOM data for the specified software component, in order to
-get at least some bit of information about it by analyzing the binary
-(for binary blobs) or querying information via git (for open source
-projects). This is for example currently done for all payloads. For
-each payload the commit hash used in the build is taken and put into
-the SBOM file. For open-source projects (like all payloads) crucial
-information like the current commit-hash of the payload can easily be
-put into the SBOM file. Extracting information out of binary blobs is a
-bit trickier for obvious reasons. For closed source binary blobs it is
-therefore recommended that vendors and software-engineers create a SBOM
-file as part of their build process and add a path to that SBOM file
-via Kconfig options in coreboot (`CONFIG_SBOM_[software-name]_PATH`).
-That way the final SBOM has much more useful and correct data.
-
-
-## Build coreboot with SBOM
-
-Directly under the 'General setup' Kconfig menu is a
-'Software Bill of Materials (SBOM)' submenu where all options are to
-enable/disable SBOM integration in to the corebeoot build.
-Therefore one can just enable/disable them via `make menuconfig`.
-
-
-## What to do as Developer of a binary blob (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format
-as part of your software build process
-
-2. Supply that generated File along with your binary blob (preferably
-not inside the blob)
-
-3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your
-defconfig pointing to your [software-name] generated File.
-
-
-## What to do as Developer of an open source project (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID file in either JSON, XML or CBOR format
-as part of your software's build process. For example in form of a
-Makefile target.
-
-2. Change src/sbom/Makefile.mk (in order to know where to find the
-CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
-builds said software. For example for GRUB2 that could mean to add a
-Makefile target in payloads/external/GRUB2/Makefile.
-
-
-## Problems
-
-What to do if the binary blob that is included in coreboot's build
-already has a SBOM file embedded in the binary? One could supply the
-path of the software binary itself (e.g. me.bin) as SBOM file path for
-the software in question. Which would basically mean to set
-`CONFIG_SBOM_[software-name]_PATH=/path/to/me.bin`. This is possible
-since the 'goswid' tooling is able to extract uSWID information out of
-an unknown binary format because of uSWIDs magic value. But even if
-coreboot can extract the uSWID data there is still the question of what
-to do next. One can do one of the following:
-
-  - Do not include the Software's SBOM data in the final SBOM of
-    coreboot. Data would not be duplicated, but therefore not included
-    in coreboot SBOM file.
-
-  - Extract the uSWID/CoSWID information from the binary and also
-    include it in the coreboot SBOM. That would mean, that SBOM data
-    is duplicated.
-
-The first solution should in general be preferred, since its no
-problem if SBOM data is located at multiple locations/binaries if they
-don't have a direct dependency on each other. It would be good if
-software that cannot run on its own only supplies the SBOM data along
-with it as kind of extra file instead of embedded in an unknown binary
-blob. coreboot can then just take it and include it in its own SBOM
-file. If on the other hand the binary can function on its own (e.g. EC
-or BMC binary), it is generally preferred that the software supplies
-its own SBOM data and coreboot just simply doesn't include it in its
-own SBOM file. That would make a more or less clear distinction and
-avoids duplication in case the BMC or EC is updated (without updating
-coreboot). The distinction is not always easy and this problem is
-currently not considered in the implementation, since none of the
-software components currently create a SBOM file on their own.

Documentation/sbom/sbom_generation.plantuml

@@ -1,61 +0,0 @@
-@startuml
-
-map "src/sbom/compiler-gcc.json" as gcc {
-    software-name => GCC
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/intel-me.json" as me {
-    software-name => Intel Mangement Engine
-    ... => ...
-}
-map "src/sbom/intel-microcode.json" as ucode {
-    software-name => Intel Microcode
-    ... => ...
-}
-map "src/sbom/generic-ec.json" as ec {
-    software-name => ecxyz
-    ... => ...
-}
-map "src/sbom/generic-fsp.json" as fsp {
-    software-name => Firmware Support Package
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/payload-[...].json" as payload {
-    software-name => ...
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/coreboot.json" as coreboot {
-    software-name => coreboot
-    version => x.y.z
-    url => coreboot.rocks
-    ... => ...
-}
-object "sbom.uswid" as uswid {
-    merged SBOM data in binary format
-}
-object goswid {
-    # ./goswid
-        --compiler gcc.json
-        --parent coreboot.json
-        --requires fsp.json,payload.json
-        intel-me.json
-        intel-ec.json
-        intel-ucode.json
-        --output sbom.uswid
-}
-
-left to right direction
-gcc --> goswid
-me --> goswid
-ucode --> goswid
-goswid <-- ec
-goswid <-- fsp
-goswid <-- payload
-
-coreboot -up> goswid
-goswid -up> uswid
-
-@enduml

Documentation/security/vboot/list_vboot.md

@@ -1,8 +1,7 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman for Phoenix SoC using FSP
+- Birman for Phoenix SoC
-- Birman for Phoenix SoC using openSIL
 - Birman for Glinda SoC
 - Chausie
 - Majolica
@@ -34,44 +33,19 @@
 - Panther (ASUS Chromebox CN60)
 - Tricky (Dell Chromebox 3010)
 - Zako (HP Chromebox G1)
-- Brox
 - Agah
 - Anahera
 - Anahera4ES
-- Anraggar
-- Aurash
-- Banshee
 - Brask
 - Brya 0
-- Craask
-- Craaskov
-- Constitution
-- Crota
-- Dochi
 - Felwinter
-- Gaelin
 - Gimble
 - Gimble4ES
-- Gladios
-- Gothrax
-- Hades
 - Kano
-- Kinox
-- Kuldax
-- Joxer
-- Lisbon
-- Marasov
-- Mithrax
-- Moli
 - Nivviks
 - Nereid
-- Nokris
-- Omnigul
-- Osiris
-- Pirrha
 - Primus
-- Pujjo
+- Primus4ES
-- Quandiso
 - Redrix
 - Redrix4ES
 - Skolas
@@ -79,14 +53,26 @@
 - Taeko
 - Taeko4ES
 - Taniks
-- Uldren
 - Vell
 - Volmar
+- Banshee
+- Crota
+- Moli
+- Kinox
+- Craask
+- Osiris
+- Mithrax
+- Kuldax
+- Joxer
+- Pujjo
 - Xivu
+- Gaelin
 - Yaviks
-- Yavilla
+- Lisbon
 - Zydron
-- Xol
+- Gladios
+- Marasov
+- Omnigul
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -94,12 +80,9 @@
 - Kingler
 - Steelix
 - Voltorb
-- Ponyta
 - Krabby
 - Tentacruel
 - Magikarp
-- Chinchou
-- Starmie
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -119,7 +102,6 @@
 - Foster
 - Gale (Google WiFi)
 - Geralt
-- Ciri
 - Asuka (Dell Chromebook 13 3380)
 - Caroline (Samsung Chromebook Pro)
 - Cave (Asus Chromebook Flip C302SA)
@@ -133,9 +115,9 @@
 - Scarlet
 - Nefario
 - Rainier
-- Dewatt (Acer Chromebook Spin 514)
 - Guybrush
-- Nipperkin (HP Elite c645 G2 Chromebook)
+- Nipperkin
+- Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
 - Dratini (HP Pro c640 Chromebook)
 - Hatch
@@ -188,7 +170,6 @@
 - Pico
 - Link (Google Chromebook Pixel (2013))
 - Mistral
-- Myst
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
 - Nyan Blaze (HP Chromebook 14 G3)
@@ -221,25 +202,14 @@
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
-- Deku
-- Deku4ES
-- Karis
-- Karis4ES
-- Ovis
-- Ovis4ES
 - Rex 0
-- Rex EC ISH
-- Rex4ES
-- Rex4ES EC ISH
-- Screebo
-- Screebo4ES
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
-- Crystaldrift
-- Frostflow (ASUS Chromebook CM34 Flip)
-- Markarth (Acer Chromebook Plus 514)
 - Skyrim
-- Winterhold (Dell Latitude 3445 Chromebook)
+- Winterhold
+- Frostflow
+- Crystaldrift
+- Markarth
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -267,35 +237,35 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Chronicler (FMV Chromebook 14F)
-- Collis (Asus Chromebook Flip CX3)
-- Copano (ASUS Chromebook Flip CX5400)
 - Delbin (ASUS Chromebook Flip CX5)
-- Drobit (ASUS Chromebook CX9400)
+- Eldrid
-- Eldrid (HP Chromebook x360 14c)
-- Elemi (HP Pro c640 G2 Chromebook)
 - Halvor
-- Lindar (Lenovo 5i-14/Slim 5 Chromebook)
+- Lindar
 - Malefor
 - Terrador
 - Todor
 - Trondo
-- Voema (Acer Chromebook Spin 514)
-- Volet (Acer Chromebook 515)
 - Volteer
 - Volteer2
 - Volteer2_Ti50
 - Voxel (Acer Chromebook Spin 713 (CP713-3W))
-- Berknip (HP Pro c645 Chromebook Enterprise)
+- Elemi (HP Pro c640 G2 Chromebook)
+- Voema
+- Drobit (ASUS Chromebook CX9400)
+- Copano (ASUS Chromebook Flip CX5400)
+- Collis
+- Volet
+- Chronicler
 - Dalboz
-- Dirinboz (HP Chromebook 14a-nd0097nr)
-- Ezkinil (Acer Chromebook Spin 514)
-- Gumboz (HP Chromebook x360 14a)
-- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
-- Shuboz
-- Trembyle
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
+- Ezkinil (Acer Chromebook Spin 514)
+- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
+- Trembyle
+- Berknip (HP Pro c645 Chromebook Enterprise)
 - Woomax (ASUS Chromebook Flip CM5)
+- Dirinboz (HP Chromebook 14a-nd0097nr)
+- Shuboz
+- Gumboz (HP Chromebook x360 14a)
 
 ## HP
 - Z220 CMT Workstation
@@ -309,7 +279,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP
 - Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
@@ -318,6 +287,8 @@
 - Coffeelake S U-DIMM DDR4 RVP8
 - Cometlake U DDR4 RVP
 - Elkhartlake LPDDR4x CRB
+- Emerald Lake 2 CRB
+- Galileo
 - Glkrvp
 - Jasperlake DDR4/LPDDR4 RVP
 - Jasperlake DDR4/LPDDR4 RVP with Chrome EC
@@ -327,9 +298,7 @@
 - Kabylake DDR4 RVP11
 - Kunimitsu
 - Meteorlake-P RVP
-- Meteorlake-P RVP with Chrome EC for Prod Silicon
+- Meteorlake-P RVP with Chrome EC
-- Meteorlake-P RVP with Chrome EC for non-Prod Silicon
-- Meteorlake-P RVP with Microchip EC
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -370,17 +339,10 @@
 ## MSI
 - PRO Z690-A (WIFI) DDR4
 - PRO Z690-A (WIFI)
-- PRO Z790-P (WIFI) DDR4
-- PRO Z790-P (WIFI)
 
 ## OpenCellular
 - Elgon (GBCv2)
 
-## Protectli
-- VP4630/VP4650
-- VP4670
-- VP2420
-
 ## SAMSUNG
 - Lumpy
 - Stumpy
@@ -397,17 +359,11 @@
 ## Star Labs
 - Star Labs Lite Mk III (N5000)
 - Star Labs Lite Mk IV (N5030)
-- Star Labs LabTop Mk III (i7-8550u)
-- Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-- Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-- Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
-- Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
 
 ## Supermicro
 - X11SSH-TF
 - X11SSM-F
 - X11SSH-F/LN4F
-- X11SSW-F
 
 ## UP
 - Squared

Documentation/security/vboot/measured_boot.md

@@ -1,52 +1,16 @@
 # Measured Boot
-Measured boot feature was initially implemented as an extension of Google
+coreboot measured boot is implemented as Google Verified Boot extension. This
-Verified Boot. However, the two features were decoupled since then and use of
+means in order to use it, vboot needs to be available for your platform. The
-measured boot no longer requires enabling vboot.
+goal of this implementation is to implement an easy to understand and
-
+transparent measured boot mechanism.
-In most cases TPM eventlog is initialized during bootblock before TPM gets set
-up, hence digests are not measured into TPM immediately, but are only cached in
-the event log. Later, as part of TPM setup, the cached events are applied onto
-TPM device. The behaviour is different if TPM_MEASURED_BOOT_INIT_BOOTBLOCK
-kconfig is set, which moves TPM initialization into bootblock.
-
-## SRTM
-A measured-based trust chain is one that begins with an initial entity that
-takes the first measurement, referred to as the "Core Root of Trust for
-Measurement" (CRTM), before control is granted to the measured entity. This
-process of measurement and then passing control is referred to as a transitive
-trust. When the CRTM can only ever be executed once during the power life-cycle
-of the system, it is referred to as a "Static CRTM" (S-CRTM). Thus the trust
-chain constructed from the S-CRTM is referred to as the Static Root of Trust for
-Measurement (SRTM) trust chain. The theory is that as long as a proper
-transitive trust is conducted as more code is allowed to execute, a trustworthy
-record showing the provenance of the executing system may be provided to
-establish the trustworthiness of the system.
 
 ## IBB/CRTM
-The "Initial Boot Block" (IBB) is a one-time executed code block loaded at the
+The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first
-reset vector. Under measured boot mode, the IBB measures itself before measuring
+code block loaded at reset vector and measured by a DRTM solution.
-the next code block making it an S-CRTM for the measured boot trust chain, an
+In case SRTM mode is active, the IBB measures itself before measuring the next
-SRTM trust chain. Since the IBB measures itself and executes out of DRAM, it is
+code block. In coreboot, cbfs files which are part of the IBB are identified
-said to have a "Root of Trust" (RoT) that is rooted in software.
+by a metadata tag. This makes it possible to have platform specific IBB
-
+measurements without hardcoding them.
-## S-CRTM Hardening
-To address attacks that took advantage of the IBB being self-referential with
-both the "Root of Trust for Verification" (RTV) and "Root of Trust for
-Measurement" (RTM) being rooted in software, hardening was implemented by CPU
-manufactures. This was accomplished by introducing RoT, typically an RTV, to an
-external entity provided by the manufacture that could be validated by the CPU
-at boot. Examples of this are Intel's BootGuard and AMD's Hardware Validated
-Boot (also known as Platform Secure Boot). These solutions work by having the
-IBB invoke the manufacture provided RoT as early as possible, for which the CPU
-has already validated or validates when invoked. The RoT will then validate the
-IBB, thus moving the root for the respective trust chain, typically the
-verification trust chain, into hardware.
-
-It should be noted that when Intel BootGuard was originally designed, it
-provided a measurement mode that resulted in the ACM (Authenticated Code
-Module) becoming the S-CRTM for the SRTM trust chain. Unfortunately, this was
-never deployed and thus relying on "Root of Trust for Verification" (RTV)
-signature check as the only assertion rooted in hardware.
 
 ## Known Limitations
 At the moment measuring IBB dynamically and FMAP partitions are not possible but
@@ -55,59 +19,43 @@ will be added later to the implementation.
 Also SoCs making use of VBOOT_RETURN_FROM_VERSTAGE are not able to use the
 measured boot extension because of platform constraints.
 
+## SRTM Mode
+The "Static Root of Trust for Measurement" is the easiest way doing measurements
+by measuring code before it is loaded.
+
 ### Measurements
-To construct the coreboot SRTM trust chain, the CBFS files which are part of the
+SRTM mode measurements are done starting with the IBB as root of trust.
-IBB, are identified by a metadata tag. This makes it possible to have platform
+Only CBFS contents are measured at the moment.
-specific IBB measurements without hard-coding them.
 
 #### CBFS files (stages, blobs)
 * CBFS data is measured as raw data before decompression happens.
 * CBFS header is excluded from measurements.
-* Measurements are stored in PCR 2 (by default, use PCR_SRTM kconfig option to
+* Measurements are stored in PCR 2.
-  change).
 
 #### Runtime Data
 * CBFS data which changes by external input dynamically. Never stays the same.
-* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and
+* It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
-  measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
+  measured into a different PCR 3 in order to avoid PCR pre-calculation issues.
-  in order to avoid PCR pre-calculation issues.
 
 ![][srtm]
 
 [srtm]: srtm.png
 
-### TPM eventlog
+### TCPA eventlog
-There are three supported formats of event logs:
+coreboot makes use of its own TCPA log implementation. Normally the eventlog
-* coreboot-specific format.
+specification can be found via the TCG homepage:
-* [TPM1.2 Specification][TPM12] (chapter 11).
-* [TPM2.0 Specification][TPM20] (chapter 10).
 
-#### coreboot-specific format
+[UEFI Specification](https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/)
-```c
-struct tcpa_entry {
-	uint32_t pcr;           /* PCR number. */
-	char digest_type[10];   /* Hash algorithm name. */
-	uint8_t digest[64];     /* Digest (tail can be unused). */
-	uint32_t digest_length; /* Number of digest bytes used. */
-	char name[50];          /* Description of what was hashed. */
-} __packed;
 
-struct tcpa_table {
+[BIOS Specification](https://www.trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf)
-	uint16_t max_entries;
-	uint16_t num_entries;
-	struct tcpa_entry entries[0];
-} __packed;
-```
 
-Single hash per PCR. No magic number or any other way of recognizing it.
+Both of them are not representing firmware measurements in a generalized way.
-Endianness isn't specified.
+Therefore we have to implement our own solution.
 
-In principle can hold any hash with 512 bits or less. In practice,
+We decided to provide an easy to understand TCPA log which can be read out
-SHA-1 (for TPM1) and SHA-256 (TPM2) are used.
+from the operating system and firmware itself.
 
-Can be parsed by `cbmem`.
+#### Table Format
-
-##### Console dump format
 The first column describes the PCR index used for measurement.
 The second column is the hash of the raw data. The third column contains
 the hash algorithm used in the operation. The last column provides
@@ -115,53 +63,6 @@ information about what is measured. First the namespace from where the data
 came from, CBFS or FMAP, then the name used to look up the data
 (region or file name).
 
-#### TPM 1.2 format
-Single hash per PCR (always SHA-1). First entry serves as a header, provides
-ID and version. Always little endian. Event data describes what is being hashed
-as a NUL-terminated string instead of providing the actual raw data.
-
-Can be parsed by at least `cbmem` and Linux (exports in both text and binary
-forms).
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x31544243 ("CBT1" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
-#### TPM 2.0 format
-One or more hashes per PCR, but implementation is limited to single hash (SHA-1,
-SHA-256, SHA-384 or SHA-512). First entry is overall compatible with TPM 1.2 and
-serves as a header with ID, version and number of hashing algorithms used.
-Always little endian. Event data describes what is being hashed as a
-NUL-terminated string instead of providing the actual raw data.
-
-By default SHA-1 is used for TPM1 and SHA-256 for TPM2. Other options are
-selectable via kconfig menu.
-
-Can be parsed by at least `cbmem`, Linux (exports only binary form) and
-[Skiboot][skiboot].
-
-[skiboot]: https://github.com/open-power/skiboot/
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x32544243 ("CBT2" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
 #### Example:
 ```bash
 PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock]
@@ -186,7 +87,7 @@ PCR-2 178561f046e2adbc621b12b47d65be82756128e2a1fe5116b53ef3637da700e8 SHA256 [F
 PCR-2 091706f5fce3eb123dd9b96c15a9dcc459a694f5e5a86e7bf6064b819a8575c7 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/payload]
 ```
 
-#### Dump TPM eventlog in the OS:
+#### Dump TCPA eventlog in the OS:
 ```bash
 cbmem -L
 ```
@@ -201,64 +102,38 @@ cbfstool coreboot.rom extract -r COREBOOT -n fallback/romstage -U -f /dev/stdout
 cbfstool coreboot.rom read -n SI_ME -f /dev/stdout | sha256sum
 ```
 
-## DRTM
+## DRTM Mode
-Certain hardware platforms, for example those with Intel TXT or AMD-V, provide
+The "Dynamic Root of Trust for Measurement" is realised by platform features
-a mechanism to dynamically execute a CRTM, referred to as the "Dynamic
+like Intel TXT or Boot Guard. The features provide a way of loading a signed
-CRTM" (D-CRTM), at any point and repeatedly during a single power life-cycle of
+"Authenticated Code Module" aka signed blob. Most of these features are also
-a system. The trust chain constructed by this D-CRTM is referred to as the
+a "Trusted Execution Environment", e.g. Intel TXT.
-"Dynamic Root of Trust for Measurement" (DRTM) trust chain. On platforms with
-Intel TXT and AMD-V, the D-CRTM is the CPU itself, which is the reason for these
-capabilities being referred to as having a "Root of Trust" (RoT) rooted in
-hardware.
 
-To provide as an authority assertion and for the DRTM trust chain attestations
+DRTM gives you the ability of measuring the IBB from a higher Root of Trust
-to co-exist with the SRTM trust chain, the TPM provides localities, localities
+instead of doing it yourself without any hardware support.
-1 - 4, which restrict access to a subset of the Platform Configuration
-Registers (PCR), specifically the DRTM PCRs 17 - 22. The mechanism to assert
-authority for access to these localities is platform specific, though the
-intention was for it to be a hardware mechanism. On Intel x86 platforms this is
-controlled through communication between the CPU and the PCH to determine if
-the "Dynamic Launch" instruction, `GETSEC[SENTER]`, was executed and that the
-CPU is in SMX mode. For AMD x86 platforms, this controlled with the APU with a
-similar enforcement that the "Dynamic Launch" instruction, `SKINIT`, was
-executed.
 
-## Platform Configuration Registers
+## Platform Configuration Register
-PCRs are allocated as follows:
+Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 4 PCR
-* PCRs 0-15 are SRTM PCRs.
+banks in order to store the measurements. coreboot uses the SHA-1 or SHA-256
-  - PCRs 0-7 are reserved for firmware usage.
+hash algorithm depending on the TPM specification for measurements. PCR-4 to
-* PCR 16 is the debug PCR.
+PCR-7 are left empty.
-* PCRs 17-22 are DRTM PCRs (PCR 22 is resettable from locality 1).
-* PCR 23 is the application/user PCR and is resettable from locality 0.
 
-coreboot uses 3 or 4 PCRs in order to store the measurements. PCRs 4-7 are left
+### PCR-0
-empty.
+_Hash:_ SHA1
 
-The firmware computes the hash and passes it to TPM.
+_Description:_ Google vboot GBB flags.
 
-The bank used by the TPM depends on the selected eventlog format. CBFS hashes
+### PCR-1
-use the same algorithm as the bank. However, GBB flags are always hashed by
+_Hash:_ SHA1/SHA256
-SHA-1 and GBB HWID by SHA-256. This results in these hashes being truncated or
-extended with zeroes in eventlog and on passing them to TPM.
 
-### If CHROMEOS kconfig option is set
+_Description:_ Google vboot GBB HWID.
-vboot-specific (non-standard) PCR usage.
 
-* PCR-0 - SHA1 of Google vboot GBB flags.
+### PCR-2
-* PCR-1 - SHA256 of Google vboot GBB HWID.
+_Hash:_ SHA1/SHA256
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
 
-### If CHROMEOS kconfig option is NOT set
+_Description:_ Core Root of Trust for Measurement which includes all stages,
-See [TPM1.2 Specification][TPM12] (section 3.3.3) and
+data and blobs.
-[TPM2.0 Specification][TPM20] (section 3.3.4) for PCR assignment information.
 
-* PCR-0 - Unused.
+### PCR-3
-* PCR-1 - SHA1 of Google vboot GBB flags, SHA256 of Google vboot GBB HWID.
+_Hash:_ SHA1/SHA256
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
 
-[TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf
+_Description:_ Runtime data like hwinfo.hex or MRC cache.
-[TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_v23_pub.pdf

Documentation/soc/amd/psp_integration.md

@@ -127,11 +127,11 @@ implementations currently use combo tables.
 +--------------+---------------+------------------+----------------------------+
 | Address Mode | 0x0F[7:6]     | 2                | 00: x86 Physical address   |
 |              |               |                  | 01: offset from start of   |
-|              |               |                  | BIOS (flash offset)        |
+|              |               |                  |     BIOS (flash offset)    |
 |              |               |                  | 02: offset from start of   |
-|              |               |                  | directory header           |
+|              |               |                  |     directory header       |
 |              |               |                  | 03: offset from start of   |
-|              |               |                  | partition                  |
+|              |               |                  |     partition              |
 +--------------+---------------+------------------+----------------------------+
 
 ```

Documentation/soc/intel/broadwell/blobs.md

@@ -29,25 +29,6 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede
 otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
 in the list of PCI devices.
 
-For the refcode binary extracted from Purism Librem 13 v1 (SHA256:
-8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4,
-.program section starts at file offset 0x2040), we can see the
-following code sequence:
-
-    1e06b:       c6 43 0c 00             movb   $0x0,0xc(%ebx)
-    1e06f:       c6 83 7e 03 00 00 00    movb   $0x0,0x37e(%ebx)
-    1e076:       c6 83 70 03 00 00 01    movb   $0x1,0x370(%ebx)
-    1e07d:       66 89 43 0a             mov    %ax,0xa(%ebx)
-    1e081:       c6 83 da 01 00 00 01    movb   $0x1,0x1da(%ebx)
-    1e088:       c6 83 86 03 00 00 01    movb   $0x1,0x386(%ebx)
-
-The code at 0x1e06f sets the field that is to enable the GbE to the
-hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5)
-to 0x01 to make the refcode support Intel GbE:
-
-    cp refcode.elf refcode_gbe.elf
-    printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc
-
 ## Use Broadwell SoC code for Haswell ULT boards
 
 Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT

Documentation/soc/intel/index.md

@@ -12,4 +12,3 @@ This section contains documentation about coreboot on specific Intel SOCs.
 - [Firmware Interface Table](fit.md)
 - [Apollolake](apollolake/index.md)
 - [CSE FW Update](cse_fw_update/cse_fw_update.md)
-- [Xeon Scalable processor](xeon_sp/index.md)

Documentation/soc/intel/xeon_sp/community_preview_guide.md

@@ -1,120 +0,0 @@
-Xeon Scalable processor coreboot Community Preview Guide
-================================================
-
-## Background
-
-Sapphire Rapids coreboot was already merged into coreboot mainline.
-Granite Rapids coreboot upstreaming is coming.
-
-For Granite Rapids coreboot, we are going to perform a phased
-upstreaming strategy according to the maturity of the code. A community
-preview branch is opensource at:
-https://review.coreboot.org/plugins/gitiles/intel-dev-pub/.
-
-The community preview branch initially contains codes on legacy feature
-enabling and matured patch set for platform support. More platform
-support code will come with the platform development. The subsequent
-upstreaming work will be based on this branch. It provides 2 board
-targets,
-
-1. Avenue City CRB (Granite Rapids-AP)
-2. Beechnut City CRB (Granite Rapids-SP)
-
-The above targets can pass build with Granite Rapids n-1 FSP headers,
-which is a set of stub FSP headers used for compilation sanity check.
-
-## Build steps
-
-### Prepare workspace
-
-```
-# Create workspace
-
-mkdir workspace && cd workspace
-
-# Prepare coreboot codebase
-
-git clone https://review.coreboot.org/intel-dev-pub ln -s intel-dev-pub/
-coreboot
-
-# Prepare stub binaries and update their path in
-# configs/builder/config.intel.crb.avc.n-1
-
-# Granite Rapids coreboot uses FSP 2.4, where FSP-I is newly introduced
-# as an optional module to provide FSP based SMM capability. For FSP 2.4
-# and FSP-I, please further refer to:
-# https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
-
-CONFIG_IFD_BIN_PATH=<path of intel flash descriptor blob>
-CONFIG_CPU_UCODE_BINARIES=<path of ucode>
-CONFIG_FSP_T_FILE=<path of FSP-T binary>
-CONFIG_FSP_M_FILE=<path of FSP-M binary>
-CONFIG_FSP_S_FILE=<path of FSP-S binary>
-CONFIG_FSP_I_FILE=<path of FSP-I binary>
-CONFIG_PAYLOAD_FILE=<path of payload binary>
-```
-
-### Download necessary submodules
-```
-git submodule update --init --checkout 3rdparty/vboot
-```
-
-### Or take below alternative if the network connection is not good
-```
-git clone https://github.com/coreboot/vboot.git 3rdparty/vboot/
-```
-
-### Build toolchain
-```
-make crossgcc-i386 CPUS=$(nproc)
-```
-
-### Build BIOS (Avenue City CRB)
-```
-make distclean
-
-make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc.n-1
-
-make olddefconfig
-
-make clean
-
-make UPDATED_SUBMODULES=1 -j`nproc`
-```
-
-### Build BIOS (Beechnut City CRB)
-```
-make distclean
-
-make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc.n-1
-
-make olddefconfig
-
-make clean
-
-make UPDATED_SUBMODULES=1 -j`nproc`
-```
-
-### Obtain the preview patch list
-
-```
-# The tag ‘upstream’ points to the upstream commit that the preview
-# branch is based on.
-
-git format-patch upstream..HEAD
-```
-
-## About Granite Rapids n-1 FSP Headers
-
-This is a set of stub FSP headers for Granite Rapids server, which will
-be forward compatible with the formal Granite Rapids FSP headers which
-will be opensource at a later stage. For the n-1 FSP headers, there are
-no corresponding n-1 FSP binaries. To pass build, users need to use stub
-binaries which could be generated in arbitrary ways.  Granite Rapids n-1
-FSP headers are at: `src/vendorcode/intel/fsp/fsp2_0/graniterapids_n-1`.
-
-For the formal Granite Rapids FSP headers and binaries, they will be
-published at in
-https://github.com/coreboot/coreboot/tree/main/src/vendorcode/intel/fsp/fsp2_0
-(headers only) and https://github.com/intel/FSP (headers and binaries)
-at a later stage.