mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Change-Id: I2df115c323a4fa50ffac191461060df9059381f7
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS

.gitignore

@@ -33,7 +33,6 @@ tags
 .clang_complete
 .cache
 compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/

.gitmodules

@@ -1,67 +1,63 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/Makefile

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 #
 # Makefile for coreboot paper.
 # hacked together by Stefan Reinauer <stepan@openbios.org>
@@ -10,9 +9,9 @@ FIGS=codeflow.pdf hypertransport.pdf
 
 all: corebootPortingGuide.pdf
 
-SVG2PDF=$(shell command -v svg2pdf)
-INKSCAPE=$(shell command -v inkscape)
-CONVERT=$(shell command -v convert)
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
 
 codeflow.pdf: codeflow.svg
 ifneq ($(strip $(SVG2PDF)),)

Documentation/Makefile.sphinx

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 # Makefile for Sphinx documentation
 #
 

Documentation/RFC/intel-gpio-cleanup.md

@@ -51,7 +51,7 @@ index 28e78fb366..0cce41b316 100644
 @@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
                 /* Patch GPIO settings for SoC specifically */
                 soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
+ 
 -               if (CONFIG(DEBUG_GPIO))
 +               if (soc_pad_conf != pad_conf)
                         printk(BIOS_DEBUG,

Documentation/acpi/devicetree.md

@@ -0,0 +1,290 @@
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+### Naming and referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+	device domain 0 on
+		...
+		device pci 00.2 alias iommu off end
+		...
+	end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+	device domain 0
+		...
+		device ref iommu on end
+		...
+	end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+	# NOTE: not inside domain 0!
+	device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
+## Device drivers
+
+Let's take a look at an example entry from
+``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
+
+```
+device pci 15.0 on
+	chip drivers/i2c/generic
+		register "hid" = ""ELAN0000""
+		register "desc" = ""ELAN Touchpad""
+		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+		register "wake" = "GPE0_DW0_21"
+		device i2c 15 on end
+	end
+end # I2C #0
+```
+
+When this entry is processed during ramstage, it will create a device in the
+ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
+generation routines in coreboot actually generate the raw bytecode that
+represents the device's structure, but looking at ASL code is easier to
+understand; see below for what the disassembled bytecode looks like:
+
+```
+Scope (\_SB.PCI0.I2C0)
+{
+    Device (D015)
+    {
+        Name (_HID, "ELAN0000")  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            Return (0x0F)
+        }
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                0x00, ResourceConsumer, , Exclusive, )
+            Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+            {
+                0x0000002D,
+            }
+        })
+        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
+        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+        {
+            0x15, // GPE #21
+            0x03  // Sleep state S3
+        })
+    }
+}
+```
+
+You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
+names/methods in the Device's scope.
+
+## Utilizing a device driver
+
+The device driver must be enabled for your build.  There will be a CONFIG option
+in the Kconfig file in the directory that the driver is in (e.g.,
+``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
+CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
+mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
+to be compiled into your build.
+
+## Diving into the above example:
+
+Let's take a look at how the devicetree language corresponds to the generated
+ASL.
+
+First, note this:
+
+```
+    chip drivers/i2c/generic
+```
+
+This means that the device driver we're using has a corresponding structure,
+located at ``src/drivers/i2c/generic/chip.h``, named **struct
+drivers_i2c_generic_config** and it contains many properties you can specify to
+be included in the ACPI table.
+
+### hid
+
+```
+    register "hid" = ""ELAN0000""
+```
+
+This corresponds to **const char *hid** in the struct.  In the ACPI ASL, it
+translates to:
+
+```
+    Name (_HID, "ELAN0000") // _HID: Hardware ID
+```
+
+under the device.  **This property is used to match the device to its driver
+during enumeration in the OS.**
+
+### desc
+
+```
+    register "desc" = ""ELAN Touchpad""
+```
+
+corresponds to **const char *desc** and in ASL:
+
+```
+    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
+```
+
+### irq
+
+It also adds the interrupt,
+
+```
+    Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+    {
+        0x0000002D,
+    }
+```
+
+which comes from:
+
+```
+    register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+```
+
+The GPIO pin IRQ settings control the "Level", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (level means it is a level-triggered
+interrupt as opposed to edge-triggered; active low means the interrupt is
+triggered when the signal is low).
+
+Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
+will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
+source.  Also note that the IRQ names are SoC-specific, and you will need to
+find the names in your SoC's header file.  The ACPI_* macros are defined in
+``src/arch/x86/include/acpi/acpi_device.h``.
+
+Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
+This is often done in a mainboard-specific file named ``gpio.c``.
+
+### wake
+
+The last register is:
+
+```
+    register "wake" = "GPE0_DW0_21"
+```
+
+which indicates that the method of waking the system using the touchpad will be
+through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
+this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
+elsewhere in the devicetree.
+
+The last bit of the definition of that device includes:
+
+```
+    device i2c 15 on end
+```
+
+which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
+meaning it will be exposed in the ACPI table.  The PCI device that the
+controller is located in determines which I2C bus the device is expected to be
+found on.  In this example, this is I2C bus 0.  This also determines the ACPI
+"Scope" that the device names and methods will live under, in this case
+"\_SB.PCI0.I2C0".
+
+## Other auto-generated names
+
+(see [ACPI specification
+6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
+for more details on ACPI methods)
+
+### _S0W (S0 Device Wake State)
+_S0W indicates the deepest S0 sleep state this device can wake itself from,
+which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
+
+### _PRW (Power Resources for Wake)
+_PRW indicates the power resources and events required for wake.  There are no
+dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
+as well as the deepest sleep state supporting waking the system (3), which is
+S3.
+
+### _STA (Status)
+The _STA method is generated automatically, and its values, 0xF, indicates the
+following:
+
+    Bit [0] – Set if the device is present.
+    Bit [1] – Set if the device is enabled and decoding its resources.
+    Bit [2] – Set if the device should be shown in the UI.
+    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
+
+### _CRS (Current resource settings)
+The _CRS method is generated automatically, as the driver knows it is an I2C
+controller, and so specifies how to configure the controller for proper
+operation with the touchpad.
+
+```
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                    0x00, ResourceConsumer, , Exclusive, )
+```
+
+## Notes
+
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/index.md

@@ -11,9 +11,6 @@ upwards.
 
 - [GPIO toggling in ACPI AML](gpio.md)
 
+## devicetree
 
-##  ACPI specification - Useful links
-
-- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
+- [Adding devices to a device tree](devicetree.md)

Documentation/acronyms.md

@@ -11,7 +11,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 `acpihelp _XXX`
 * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)
 * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space.
-  Better abbreviated as 4GiB
 * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)
 
 ## A
@@ -46,10 +45,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ALIB - AMD: ACPI-ASL Library
 * ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor)
 * ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit)
-* AMBA - ARM: [**Advanced Microcontroller Bus
-  Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture):
-  An open standard to connect and manage functional blocks in an SoC
-  (System on a Chip)
 * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
 * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
   SBI: Sideband Interface
@@ -58,8 +53,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * AOAC - AMD: Always On, Always Connected
 * AP - Application processor - The main processor on the board (as
   opposed to the embedded controller or other processors that may be on
-  the system), any cores in the processor chip that aren't the BSP (Boot
-  Strap Processor).
+  the system), any cores in processor chip that isn’t the BSP - Boot
+  Strap Processor.
 * APCB - AMD: AMD PSP Customization Block
 * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
 * APIC - [**Advanced Programmable Interrupt
@@ -90,7 +85,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ASPM - PCI: [**Active State Power
   Management**](https://en.wikipedia.org/wiki/Active_State_Power_Management)
 * ATA - [**Advanced Technology Attachment**](https://en.wikipedia.org/wiki/Parallel_ATA)
-* ATS - PCIe: Address Translation Services
 * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI)
 * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX)
 * AVX -  [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions)
@@ -129,7 +123,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   stored as a single object, this was co-opted by the open source
   communities to mean any proprietary binary file that is not available
   as source code.
-* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering)
 * BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management_Interface#Baseboard_management_controller)
 * BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format)
 * BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials)
@@ -172,8 +165,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity)
 * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim)
 * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)
-* CL - ChangeList - Another name for a patch or commit.  This seems to be
-  Perforce notation.
+* CL - Change List - A git patch in gerrit
 * CLK - Clock - Used when there isn't enough room for 2 additional
   characters - similar to RST, for people who hate vowels.
 * CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake)
@@ -188,7 +180,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
 * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
 * CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device)
-* CPPC - AMD: Collaborative Processor Performance Controls
 * CPS - Characters Per Second
 * CPU - [**Central Processing
   Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
@@ -205,14 +196,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CSI - MIPI: [**Camera Serial
   Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface)
 * CSME - Intel: Converged Security and Management Engine
-* CTLE - Intel: Continuous Time Linear Equalization
 * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
-* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
+* CZN - AMD: Cezanne - CPU Family 19h, Model 50h
 
 
 ## D
 
-* D$ - Data Cache
 * D-States - [**ACPI Device power
   states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface#Device_states)
   D0-D3 - These are device specific power states, with each higher
@@ -234,9 +223,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel)
 * DDI -  Intel: Digital Display Interface
 * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
-* DEVAPC - Mediatek: Device Access Permission Control
-* DF - Data Fabric
-* DFP - USB: Downstream Facing port
 * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
 * DID - Device Identifier
 * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
@@ -249,7 +235,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Graphics Card, Sound Card. DMA is an essential feature of all modern
   computers, as it allows devices of different speeds to communicate
   without subjecting the CPU to a massive interrupt load.
-* DMI - Direct Media Interface is a link/bus between CPU and PCH.
 * DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
 * DMIC - Digital Microphone
 * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
@@ -258,7 +243,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton)
 * DOS - Disk Operating System
 * DP - DisplayPort
-* DPM - Mediatek: DRAM Power Manager
 * DPTF - Intel: Dynamic Power and Thermal Framework
 * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
 * DRTM - Dynamic Root of Trust for Measurement
@@ -266,10 +250,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   data-in pin is generally referred to as D, and the data-out pin is Q,
   thus the IO Data signal lines are referred to as DQ lines.
 * DQS - Memory: Data Q Strobe - Data valid signal for DDR memory.
-* DRM - [**Digital Rights
-  Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
-* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or
-  an Upstream Facing (UFP).
+* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
 * DRQ - DMA Request
 * DRTU - Intel: Diagnostics and Regulatory Testing Utility
 * DSDT - The [**Differentiated System Descriptor
@@ -281,16 +262,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line)
 * DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor)
 * DTB - U-Boot: Device Tree Binary
-* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
-  vs Integrated TPMs or fTPMs (Firmware TPMs).
+* dTPM - Discrete Trusted Platform Module
 * DTS - U-Boot: Device Tree Source
-* DUT - Device Under Test
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
-* DW - DesignWare: A portfolio of silicon IP blocks for sale by the
-  Synopsys company.  Includes blocks like USB, MIPI, PCIe, HDMI, SATA,
-  I2c, memory controllers and more.
+* DW - DesignWare
 * DXE - UEFI:  [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface#DXE_%E2%80%93_Driver_Execution_Environment_)
 * DXIO - AMD: Distributed CrossBar I/O
 
@@ -298,21 +275,19 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 ## E
 
 * EBDA - Extended BIOS Data Area
-* EBG - Intel: Emmitsburg PCH
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* edk2 - EFI Development Kit 2
+* EDK2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was
   backwards compatible with FPM (Fast Page Mode) memory.
-* eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP)
+* EDP - [**Embedded DisplayPort**](DisplayPort)
 * EDS - Intel: External Design Specification
 * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
   electrical erasable programmable ROM).
 * EFI - [**Extensible Firmware Interface**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface)
-* EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process.
 * EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29#EHCI) - USB 2.0
 * EHL - Intel: [**Elkhart Lake**](https://en.wikichip.org/wiki/intel/cores/elkhart_lake)
 * EIDE - Enhanced Integrated Drive Electronics
@@ -364,11 +339,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
 * FSP - Intel: Firmware Support Package
-* FSR - Intel: Firmware Status Register
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
-* fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
-  based in firmware instead of actual hardware.  It typically runs in
-  some sort of TEE (Trusted Execution Environment).
+* FTPM - Firmware TPM
 
 
 ## G
@@ -384,14 +356,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Real Time Clock, and maybe a few other registers running.
 * GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
 * GATT - Graphics Aperture Translation Table
-* GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table)
 * GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake)
 * GMA - Intel: [**Graphics Media
   Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
 * GNB - Graphics NorthBridge
 * GNVS - Global Non-Volatile Storage
 * GPD - PCH GPIO in Deep Sleep well (D5 power)
-* GPE - ACPI: General Purpose Event
 * GPI - GPIOs: GPIO Input
 * GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_Input/Output) (Pin)
 * GPMR - Intel: General Purpose Memory Range
@@ -403,8 +373,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GPU - [**Graphics Processing Unit**](https://en.wikipedia.org/wiki/Graphics_processing_unit)
 * GSoC - [**Google Summer of Code**](https://en.wikipedia.org/wiki/Google_Summer_of_Code)
 * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
-* GSPI - Generic SPI - These are SPI controllers available for general
-  use, not dedicated to flash, for example.
 * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
 
 
@@ -419,9 +387,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * HID - [**Human Interface
   Device**](https://en.wikipedia.org/wiki/Human_interface_device)
 * HOB - UEFI: Hand-Off Block
-* HPD - Hot-Plug Detect
 * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
-* HSP - AMD: Hardware Security Processor
 * HSTI - Hardware Security Test Interface
 * HSW - Intel: Haswell
 * Hybrid S3 - System Power State:  This is where the operating system
@@ -441,7 +407,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## I
 
-* I$ - Instruction Cache
 * I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for
   communication generally between different ICs on a circuit board.
   * [https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html](https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html)
@@ -463,11 +428,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI
   slot has a signal called IDSEL. It is used to differentiate between
   the different slots.
-* IDT - [Interrupt Descriptor Table](https://en.wikipedia.org/wiki/Interrupt_descriptor_table)
 * IF - AMD: [**Infinity
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
-* IFD - Intel: Intel Flash Descriptor
 * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
   into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
   This never worked well for anything beyond fan control and caused
@@ -501,7 +464,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IVHD - ACPI: I/O Virtualization Hardware Definition
 * IVMD - ACPI: I/O Virtualization Memory Definition
 * IVRS - I/O Virtualization Reporting Structure
-* IWYU - Include What you Use - A tool to help with include file use
 
 
 ## J
@@ -542,7 +504,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * LAPIC - Local APIC
 * LBA - Logical Block Address
 * LCD - Liquid Crystal Display
-* LCAP - PCIe: Link Capabilities
+* LCAP - PCIe:Link Capabilities
 * LED - Light Emitting Diode
 * LF - Line Feed - The standard Unix EOL (End-of-Line) marker.
 * LGTM - Looks Good To Me
@@ -555,7 +517,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   count**](http://www.intel.com/design/chipsets/industry/lpc.htm) bus
   was a replacement for the ISA bus, created by serializing a number of
   parallel signals to get rid of those connections.
-* LPM - USB: Link Power Management
 * LPT - Line Print Terminal, Local Print Terminal, or Line Printer. -
   The Parallel Port
 * LRU - Least Recently Used - a rule used in operating systems that
@@ -572,19 +533,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * M.2 - An interface specification for small peripheral cards.
 * MAC Address - Media Access Control Address
-* MAFS - (eSPI) Master Attached Flash Sharing: Flash components are
-  attached to the controller device and may be accessed by by the
-  peripheral devices through the eSPI flash access channel.
-* MBP - Intel UEFI: ME-to-BIOS Payload
 * MBR - Master Boot Record
 * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
 * MCR - Machine Check Registers
 * MCU - Memory Control Unit
 * MCU - [**MicroController
   Unit**](https://en.wikipedia.org/wiki/Microcontroller)
-* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MDFIO - Intel: Multi-Die Fabric IO
-* MDN - AMD: Mendocino
 * ME - Intel: Management Engine
 * MEI - Intel: ME Interface (Previously known as HECI)
 * Memory training - the process of finding the best speeds, voltages,
@@ -623,7 +578,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   OS software writers to produce SMP-capable machines and OSes in a
   vendor-independent manner. Version 1.1 of the spec was released in
   1994, and the 1.4 version was released in 1995.  This has been
-  generally superseded by the ACPI tables.
+  generally been
+  https://en.wikipedia.org/wiki/MultiProcessor_Specification by the ACPI
+  tables.
 * MRC - Intel: Memory Reference Code
 * MSB - Most Significant Bit
 * MSI - Message Signaled Interrupt
@@ -631,19 +588,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MT/s - MegaTransfers per second
 * MTL - Intel: Meteor Lake
 * MTL - ARM: MHU Transport Layer
-* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
-  allows to set the cache behaviour on memory access in x86. Basically,
-  it tells the CPU how to cache certain ranges of memory
-  (e.g. write-through, write-combining, write-back...). Memory ranges
-  are specified over physical address ranges. In Linux, they are visible
-  over `/proc/mtrr` and they can be modified there. For further
-  information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
+* MTRR - [**Memory Type and Range
+  Register**](http://en.wikipedia.org/wiki/MTRR)
 
 
 ## N
 
 * Nack - Negative Acknowledgement
-* NB - North Bridge
 * NBCI - Nvidia: NoteBook Common Interface
 * NC - GPIOs: No Connect
 * NDA - Non-Disclosure Agreement.
@@ -670,8 +621,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state
 * ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state.
-* ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer)
-* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufacturer)
+* ODM - Original Design Manufacturer
+* OEM - Original Equipment Manufacturer
 * OHCI - [**Open Host Controller
   Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB%29)
   - non-proprietary USB Host controller for USB 1.1 (May also refer to
@@ -692,9 +643,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PAT - [**Page Attribute
   Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can
   be used independently or in combination with MTRR to setup memory type
-  access ranges. Allows more finely-grained control than MTRR. Compared to MTRR,
-  which sets memory types by physical address ranges, PAT sets them at Page
-  level.
+  access ranges. Allows more finely-grained control than MTRR.
 * PAT - Intel: [**Performance Acceleration
   Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_technology)
 * PATA - Parallel Advanced Technology Attachment - A renaming of ATA
@@ -720,11 +669,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   function's configuration space from 256 bytes to 4K.
 * PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
 * PCMCIA: Personal Computer Memory Card International Association
-* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
+* PCO - AMD: Picasso
 * PCR: TPM: Platform Configuration Register
-* PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor.
-  The resistor allows the pin to be set to the reference voltage as
-  needed.
+* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage.  Setting it low drives it to ground through a resistor.
 * PD - Power Delivery - This is a specification for communicating power
   needs and availability between two devices, typically over USB type C.
 * PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU
@@ -732,7 +679,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PEI - UEFI: Pre-EFI Initialization
 * PEIM - UEFI: PEI Module
 * PEP - Intel: Power Engine Plug-in
-* PHX - AMD: Phoenix SoC
 * PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
   hardware that implements the send/receive functionality of a
   communication protocol.
@@ -774,19 +720,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * POTS - [**Plain Old Telephone
   Service**](https://en.wikipedia.org/wiki/Plain_old_telephone_service)
 * PPI - UEFI: PEIM-to-PEIM Interface
-* PPR - Processor Programming Reference
+* PPR: Processor Programming Reference
 * PPT - AMD: Package Power Tracking
-* PROM - Programmable Read Only Memory
+* PROM: Programmable Read Only Memory
 * Proto - Production Timeline: The first initial production to test key
   concepts.
 * PSE - Page Size Extention
-* PSF - Intel: Primary Sideband Fabric
 * PSP - AMD: Platform Security Processor
 * PSPP - AMD: PCIE Speed Power Policy
-* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
-* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
-  resistor. The resistor allows the signal to still be set to ground
-  when needed.
+* PU - GPIOs: Pull-Up - Setting the pin low drives it to ground.  Setting it high drives it to the reference voltage through a resistor.
 * PVT - Production Timeline: (Production Validation Test
 * PWM - Pulse Width Modulation
 * PXE - Pre-boot Execution Environment
@@ -832,7 +774,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * RRG - AMD (ATI): Register Reference Guide
 * RSDP - Root System Description Pointer
 * RTC - Real Time Clock
-* RTD3 - Power State: Runtime D3
 * RTFM - Read the Fucking Manual
 * RTOS - Real-Time Operating System
 * RVP - Intel: Reference Validation Platform
@@ -868,11 +809,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   contents of memory.  Any critical processor state is restored.
 * S5 - ACPI System Power State: System is “completely powered off”, but
   still has power going to the board.
-* SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the
-  peripheral device.  Only valid for server platforms.
-* SAGV - Intel: System Agent Geyserville. The original internal name
-  for the feature eventually released as Speedstep which controls the
-  processor voltage and frequencies.
 * SAR - The [**Specific Absorption
   Rate**](https://en.wikipedia.org/wiki/Specific_absorption_rate) is the
   measurement for the amount of Radio Frequency (RF) energy absorbed by
@@ -896,13 +832,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   SAS (Serial Attached SCSI).  The initial version is now often referred
   to as Parallel SCSI.
 * SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card
-* SDHCI - SD Host Controller Interface
 * SDRAM - Synchronous DRAM
 * SDLE: AMD: Stardust Dynamic Load Emulator
 * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
   Memory)
 * SEV - AMD: Secure Encrypted Virtualization
-* SF - Snoop Filter
 * Shadow RAM - RAM which content is copied from ROM residing at the same
   address for speedup purposes.
 * Shim - A small piece of code whose only purpose is to act as an
@@ -939,9 +873,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SPI - [**Serial Peripheral
   Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface)
 * SPL - AMD: Security Patch Level
-* SPM - Mediatek: System Power Manager
 * SPMI - MIPI: System Power Management Interface
-* SPR - Sapphire Rapids
 * SRAM - Static Random Access Memory
 * SSD - Solid State Drive
 * SSDT - Secondary System Descriptor Table - ACPI table
@@ -957,9 +889,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
 * SSI-TEB - Physical board format: [**SSI Thin Electronics
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
-* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
 * STAPM - AMD: Skin Temperature Aware Power Management
-* STB - AMD: Smart Trace Buffer
 * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
   (SIO) device provides a system with any of a number of different
   peripherals.  Most common are: A PS/2 Keyboard and mouse port, LPT
@@ -979,8 +909,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TDMA - Time-Division Multiple Access
 * TDP - [**Thermal Design
   Power**](https://en.wikipedia.org/wiki/Thermal_design_power)
-* TEE - [**Trusted Execution
-  Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment)
+* TEE - Trusted Execution Environment
 * TFTP - Network Protocol: Trivial File Transfer Protocol
 * TGL - Intel: Tigerlake
 * THC - Touch Host Controller
@@ -990,17 +919,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TLA - Three Letter Acronym
 * TLB - [**Translation Lookside
   Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer)
-* TME - Intel: Total Memory Encryption
 * TOCTOU - Time-Of-Check to Time-Of-Use
 * TOLUM - Top of Low Usable Memory
 * ToM - Top of Memory
 * TPM - Trusted Platform Module
-* TS - TimeStamp
-* TSN - Time-Sensitive Networking
+* TS - TimeStamp -
 * TSC - [**Time Stamp
   Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
 * TSEG - TOM (Top of Memory) Segment
-* TSR - Temperature Sensor
 * TWAIN - Technology without an interesting name.
 * TX - Transmit
 * TXE - Intel: Trusted eXecution Engine
@@ -1014,8 +940,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
 * UEFI - Unified Extensible Firmware Interface
-* UFC - User Facing Camera
-* UFP - USB: Upstream Facing Port
 * UFS - Universal Flash storage
 * UHCI - USB: [**Universal Host Controller
   Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29%23UHCI)
@@ -1037,7 +961,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VBIOS - Video BIOS
 * VBNV - Vboot Non-Volatile storage
 * VBT - [**Video BIOS
-  Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
+  Table**](https://01.org/linuxgraphics/gfx-docs/drm/ch04s02.html#id-1.4.3.4.16)
 * VESA - Video Electronics Standards Association
 * VGA: Video Graphics Array
 * VID: Vendor Identifier
@@ -1064,9 +988,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   devices that open 360 degrees, or on the outside of the cover.  For
   tablets, it's on the the side away from the screen.
 * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
-* WFC - World Facing Camera
 * WLAN - Wireless LAN (Local Area Network)
-* WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
 * WO - Write-only
 * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)

Documentation/community/forums.md

@@ -31,7 +31,7 @@ topics, including community and technical matters that benefit from
 an official decision.
 
 We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
+best with [Google Meet](https://meet.google.com/syn-toap-agu),
 using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
 for the agenda and meeting minutes. Neither the video conference nor
 the document require a Google account to participate, although editing

Documentation/contributing/coding_style.md

@@ -66,7 +66,7 @@ case 'm':
 case 'K':
 case 'k':
 	mem <<= 10;
-	__fallthrough;
+	/* fall through */
 default:
 	break;
 }
@@ -818,9 +818,9 @@ Function return values and names
 
 Functions can return values of many different kinds, and one of the most
 common is a value indicating whether the function succeeded or failed.
-Such a value can be represented as an error-code integer (`CB_ERR_xxx`
-(negative number) = failure, `CB_SUCCESS` (0) = success) or a "succeeded"
-boolean (0 = failure, non-zero = success).
+Such a value can be represented as an error-code integer (-Exxx =
+failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
+= success).
 
 Mixing up these two sorts of representations is a fertile source of
 difficult-to-find bugs. If the C language included a strong distinction
@@ -832,84 +832,21 @@ If the name of a function is an action or an imperative command,
 the function should return an error-code integer.  If the name
 is a predicate, the function should return a "succeeded" boolean.
 
-For example, "add work" is a command, and the `add_work()` function
-returns 0 for success or `CB_ERR` for failure. In the same way, "PCI
-device present" is a predicate, and the `pci_dev_present()` function
+For example, "add work" is a command, and the add_work() function
+returns 0 for success or -EBUSY for failure. In the same way, "PCI
+device present" is a predicate, and the pci_dev_present() function
 returns 1 if it succeeds in finding a matching device or 0 if it
 doesn't.
 
+All EXPORTed functions must respect this convention, and so should all
+public functions. Private (static) functions need not, but it is
+recommended that they do.
+
 Functions whose return value is the actual result of a computation,
 rather than an indication of whether the computation succeeded, are not
 subject to this rule. Generally they indicate failure by returning some
 out-of-range result. Typical examples would be functions that return
-pointers; they use NULL to report failure.
-
-Error handling, assertions and die()
------------------------------
-
-As firmware, coreboot has no means to let the user interactively fix things when
-something goes wrong. We either succeed to boot or the device becomes a brick
-that must be recovered through complicated external means (e.g. a flash
-programmer). Therefore, coreboot code should strive to continue booting
-wherever possible.
-
-In most cases, errors should be handled by logging a message of at least
-`BIOS_ERR` level, returning out of the function stack for the failed feature,
-and then continuing execution. For example, if a function reading the EDID of an
-eDP display panel encounters an I2C error, it should print a "cannot read EDID"
-message and return an error code. The calling display initialization function
-knows that without the EDID there is no way to initialize the display correctly,
-so it will also immediately return with an error code without running its
-remaining code that would initialize the SoC's display controller. Exeuction
-returns further up the function stack to the mainboard initialization code
-which continues booting despite the failed display initialization, since
-display functionality is non-essential to the system. (Code is encouraged but
-not required to use `enum cb_err` error codes to return these errors.)
-
-coreboot also has the `die()` function that completely halts execution. `die()`
-should only be used as a last resort, since it results in the worst user
-experience (bricked system). It is generally preferrable to continue executing
-even after a problem was encountered that might be fatal (e.g. SPI clock
-couldn't be configured correctly), because a slight chance of successfully
-booting is still better than not booting at all. The only cases where `die()`
-should be used are:
-
-1. There is no (simple) way to continue executing. For example, when loading the
-   next stage from SPI flash fails, we don't have any more code to execute. When
-   memory initialization fails, we have no space to load the ramstage into.
-
-2. Continuing execution would pose a security risk. All security features in
-   coreboot are optional, but when they are configured in the user must be able
-   to rely on them. For example, if CBFS verification is enabled and the file
-   hash when loading the romstage doesn't match what it should be, it is better
-   to stop execution than to jump to potentially malicious code.
-
-In addition to normal error logging with `printk()`, coreboot also offers the
-`assert()` macro. `assert()` should be used judiciously to confirm that
-conditions are true which the programmer _knows_ to be true, in order to catch
-programming errors and incorrect assumptions. It is therefore different from a
-normal `if ()`-check that is used to actually test for things which may turn
-out to be true or false based on external conditions. For example, anything
-that involves communicating with hardware, such as whether an attempt to read
-from SPI flash succeeded, should _not_ use `assert()` and should instead just
-be checked with a normal `if ()` and subsequent manual error handling. Hardware
-can always fail for various reasons and the programmer can never 100% assume in
-advance that it will work as expected. On the other hand, if a function takes a
-pointer parameter `ctx` and the contract for that function (as documented in a
-comment above its declaration) specifies that this parameter should point to a
-valid context structure, then adding an `assert(ctx)` line to that function may
-be a good idea. The programmer knows that this function should never be called
-with a NULL pointer (because that's how it is specified), and if it was actually
-called with a NULL pointer that would indicate a programming error on account of
-the caller.
-
-`assert()` can be configured to either just print an error message and continue
-execution (default), or call `die()` (when `CONFIG_FATAL_ASSERTS` is set).
-Developers are encouraged to always test their code with this option enabled to
-make assertion errors (and therefore bugs) more easy to notice. Since assertions
-thus do not always stop execution, they should never be relied upon to be the
-sole guard against conditions that really _need_ to stop execution (e.g.
-security guarantees should never be enforced only by `assert()`).
+pointers; they use NULL or the ERR_PTR mechanism to report failure.
 
 Headers and includes
 ---------------
@@ -1065,7 +1002,7 @@ The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
 <https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8>
+<https://www.google.com/search?q=isbn+0-13-110362-8.
 
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.

Documentation/contributing/gerrit_guidelines.md

@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * In general, patches should remain open for review for at least 24 hours
 since the last significant modification to the change. The purpose is to
@@ -127,54 +127,6 @@ those platforms. While it would be nice to update any other platforms, you
 must at least provide a path that will allow other platforms to continue
 working.
 
-Sign-off Procedure
-------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
 
 Recommendations for gerrit activity
 -----------------------------------
@@ -221,10 +173,7 @@ This helps verify that the patch train won’t tie up the jenkins builders
 for no reason if there are failing patches in the train. For running
 parallel builds, you can specify the number of cores to use by setting the
 the CPUS environment variable. Example:
-
-```Bash
-make what-jenkins-does CPUS=8
-```
+        make what-jenkins-does CPUS=8
 
 * Use a topic when pushing a train of patches. This groups the commits
 together so people can easily see the connection at the top level of
@@ -232,10 +181,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
 commits with the i915-kernel-x60 set, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -245,10 +191,7 @@ Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
 isn't as obvious as the commit message. These patches can also be pushed with
 the wip flag:
-
-```Bash
-git push origin HEAD:refs/for/master%wip
-```
+	git push origin HEAD:refs/for/master%wip
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
@@ -257,16 +200,10 @@ sorts of patches are frequently posted as ideas or RFCs for the community to
 look at. Note that private changes can still be fetched from Gerrit by anybody
 who knows their commit ID, so don't use this for sensitive changes. To push
 a private change, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%private
-```
+        git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:
-
-```Bash
-git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -340,15 +277,13 @@ git/gerrit tags by prepending the lines with 'Original-'.  Marking
 the original text this way makes it much easier to tell what changes
 happened in which repository. This applies to these lines, not the actual
 commit message itself:
-
-	* Commit-Id:
-	* Change-Id:
-	* Signed-off-by:
-	* Reviewed-on:
-	* Tested-by:
-	* Reviewed-by:
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
+        Commit-Id:
+        Change-Id:
+        Signed-off-by:
+        Reviewed-on:
+        Tested-by:
+        Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
@@ -434,7 +369,3 @@ Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
 
 [ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes

Documentation/contributing/gsoc.md

@@ -1,16 +1,5 @@
 # Google Summer of Code
 
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
 
 ## Contacts
 
@@ -19,6 +8,9 @@ please have a look at our [community forums] and reach out to us. Working closel
 with the community is highly encouraged, as we've seen that our most successful
 contributors are generally very involved.
 
+Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
+2022. Please feel free to reach out to them directly if you have any questions.
+
 
 ## Why work on coreboot for GSoC?
 
@@ -59,8 +51,6 @@ contributors are generally very involved.
 
   * [Glossary][GSoC Glossary]
 
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
 
 ## Contributor requirements & commitments
 
@@ -101,7 +91,7 @@ amount of spare time. If this is not the case, then you should not apply.
       process and common issues.
 
     * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
+      Check the [easy project list][Project ideas] or ask for simple tasks on
       the [mailing list] or on our other [community forums] if you need ideas.
 
 
@@ -283,4 +273,3 @@ questions.
 [GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
 [GSoC Rules]: https://summerofcode.withgoogle.com/rules
 [GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips

Documentation/contributing/project_ideas.md

@@ -20,12 +20,12 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Small projects
+## Easy projects
 
 This is a collection of tasks which don't require deep knowledge on
 coreboot itself. If you are a beginner and want to get familiar with the
 the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
+dirty with some easy tasks, then these are for you.
 
   * Resolve static analysis issues reported by [scan-build] and
     [Coverity scan]. More details on the page for
@@ -36,7 +36,7 @@ dirty with some small tasks, then these are for you.
 [scan-build]: https://coreboot.org/scan-build/
 [Coverity scan]: https://scan.coverity.com/projects/coreboot
 [Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
+[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
 
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
@@ -63,6 +63,7 @@ non-Linux builds or Docker for different Linux distributions.
 * hardware requirements: Nothing special
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Support Power9/Power8 in coreboot
 There are some basic PPC64 stubs in coreboot, and there's open hardware
@@ -86,8 +87,8 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
+yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a
 combination of payload and architecture to support.
@@ -129,6 +130,7 @@ their bug reports.
   going on from the resulting logs.
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Extend Ghidra to support analysis of firmware images
 [Ghidra](https://ghidra-sre.org) is a recently released cross-platform

Documentation/distributions.md

@@ -37,15 +37,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
+use Tianocore as the payload and include an NVRAM option to disable the
+Intel Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
+distribution of coreboot, EDK2, and System76 firmware applications.
 
 ### Purism
 
@@ -71,14 +71,12 @@ focusing on clean and simple code, long-term maintenance, transparent
 validation, privacy-respecting implementation, liberty for the owners, and
 trustworthiness for all.
 
-Contributions are welcome,
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
 
 ### MrChromebox
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/drivers/cbfs_smbios.md

@@ -1,143 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS Serial Number
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information and type 2 Baseboard Information called Serial Number. It
-is a null-terminated string field assumed to be unique per platform. Certain
-mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
-data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
-provide an option to populate the Serial Numbers from CBFS for boards that
-can't generate the it from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `Serial number in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the serial number:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
-```
-
-Where `serial_file.txt` is the unterminated string representation of the SMBIOS
-type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
-partitions you will have to specify the RW regions where the file is going to
-be added too. By default the RW CBFS partitions are truncated, so the files
-would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the Serial Number from running system (if it exists) using one
-of the following commands:
-
-```shell
-# Type 1
-echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
-# OR Type 2
-echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
-```
-
-Ensure the file does not end with whitespaces like LF and/or CR. The above
-commands will not add any whitespaces. The driver automatically terminates the
-Serial Number with the NULL character. If the CBFS file is not present, the
-driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
-option.
-
-Please note that this driver provides `smbios_mainboard_serial_number` hook
-overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
-build option. If you wish to populate only type 2 Serial Number field your
-board code needs to implement `smbios_system_serial_number`, otherwise the weak
-implementation of `smbios_system_serial_number` will call
-`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
-implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
-has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
-if the board does not implement its own `smbios_system_serial_number`.
-
-There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
-populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
-implementation (returns empty string). If you wish to populate type 3 Serial
-Number, your board code should override the default
-`smbios_chassis_serial_number` weak implementation.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,21 +298,21 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
 
-### OEM Variables
+## OEM Variables
 Platform vendors can define an array of OEM-specific values as OEM variables
 to be used under DPTF policy. There are total six OEM variables available.
 These can be used in AP policy for more specific actions. These OEM variables

Documentation/drivers/dt_entries.md

@@ -1,309 +0,0 @@
-# Driver Devicetree Entries
-
-Let's take a look at an example entry from
-``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
-
-```
-device pci 15.0 on
-	chip drivers/i2c/generic
-		register "hid" = ""ELAN0000""
-		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
-		register "wake" = "GPE0_DW0_21"
-		device i2c 15 on end
-	end
-end # I2C #0
-```
-
-When this entry is processed during ramstage, it will create a device in the
-ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
-generation routines in coreboot actually generate the raw bytecode that
-represents the device's structure, but looking at ASL code is easier to
-understand; see below for what the disassembled bytecode looks like:
-
-```
-Scope (\_SB.PCI0.I2C0)
-{
-    Device (D015)
-    {
-        Name (_HID, "ELAN0000")  // _HID: Hardware ID
-        Name (_UID, Zero)  // _UID: Unique ID
-        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
-        Method (_STA, 0, NotSerialized)  // _STA: Status
-        {
-            Return (0x0F)
-        }
-        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-        {
-            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-            {
-                0x0000002D,
-            }
-        })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
-        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
-        {
-            0x15, // GPE #21
-            0x03  // Sleep state S3
-        })
-    }
-}
-```
-
-You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
-names/methods in the Device's scope.
-
-## Utilizing a device driver
-
-The device driver must be enabled for your build.  There will be a CONFIG option
-in the Kconfig file in the directory that the driver is in (e.g.,
-``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
-CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
-mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
-to be compiled into your build.
-
-## Diving into the above example:
-
-Let's take a look at how the devicetree language corresponds to the generated
-ASL.
-
-First, note this:
-
-```
-    chip drivers/i2c/generic
-```
-
-This means that the device driver we're using has a corresponding structure,
-located at ``src/drivers/i2c/generic/chip.h``, named **struct
-drivers_i2c_generic_config** and it contains many properties you can specify to
-be included in the ACPI table.
-
-### hid
-
-```
-    register "hid" = ""ELAN0000""
-```
-
-This corresponds to **const char \*hid** in the struct.  In the ACPI ASL, it
-translates to:
-
-```
-    Name (_HID, "ELAN0000") // _HID: Hardware ID
-```
-
-under the device.  **This property is used to match the device to its driver
-during enumeration in the OS.**
-
-### desc
-
-```
-    register "desc" = ""ELAN Touchpad""
-```
-
-corresponds to **const char \*desc** and in ASL:
-
-```
-    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
-```
-
-### irq
-
-It also adds the interrupt,
-
-```
-    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-    {
-        0x0000002D,
-    }
-```
-
-which comes from:
-
-```
-    register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-```
-
-The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
-means it is a level-triggered interrupt as opposed to
-edge-triggered; active low means the interrupt is triggered when the signal is
-low).
-
-Also note that the IRQ names are SoC-specific, and you will need to
-find the names in your SoC's header file.  The ACPI_* macros are defined in
-``src/arch/x86/include/acpi/acpi_device.h``.
-
-Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
-This is often done in a mainboard-specific file named ``gpio.c``.
-
-AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
-GPIO controller needs to be used directly. You can do this by setting the
-`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
-
-i.e.,
-```
-register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
-```
-
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
-mainboards in the tree to implement this are google/skyrim and google/guybrush.
-This feature has also been used in downstream forks without issue for some time
-now on several other boards.
-
-### wake
-
-The last register is:
-
-```
-    register "wake" = "GPE0_DW0_21"
-```
-
-which indicates that the method of waking the system using the touchpad will be
-through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
-this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
-elsewhere in the devicetree.
-
-### device
-
-The last bit of the definition of that device includes:
-
-```
-    device i2c 15 on end
-```
-
-which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
-meaning it will be exposed in the ACPI table.  The PCI device that the
-controller is located in determines which I2C bus the device is expected to be
-found on.  In this example, this is I2C bus 0.  This also determines the ACPI
-"Scope" that the device names and methods will live under, in this case
-"\_SB.PCI0.I2C0".
-
-## Wake sources
-
-The ACPI spec defines two methods to describe how a device can wake the system.
-Only one of these methods should be used, otherwise duplicate wake events will
-be generated.
-
-### Using GPEs as a wake source
-
-The `wake` property specified above is used to tell the ACPI subsystem that the
-device can use a GPE to wake the system. The OS can control whether to enable
-or disable the wake source by unmasking/masking off the GPE.
-
-The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
-generally done by a mainboard specific `gpio.c` file that defines the GPIO
-using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
-`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
-file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
-`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
-GPEs (the rest are available as `tier-2` GPEs).
-
-Windows has a large caveat when using this method. If you use the `gpio_irq`
-property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
-to define a `GPE`, Windows will
-[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
-complaining about an invalid ACPI configuration.
-> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
-
-In order to avoid this error, you should use the `irq` property instead. AMD
-platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
-feasible. The other option is to use a wake capable GPIO as described below.
-
-### Using GPIO interrupts as a wake source
-
-The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
-`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
-`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
-
-This method has a few caveats:
-* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
-  the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
-  system. Instead you need to use the `gpio_irq` property, or a `GPE` as
-  described above.
-* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
-  means the platform specific GPIO controller driver must implement the
-  `irq_set_wake` callback. For AMD systems this wasn't
-  [implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
-  until linux v5.15. If the controller doesn't define this callback, it's
-  possible for the firmware to manually set the `wake` bit on the GPIO. This is
-  often done in a mainboard-specific file named `gpio.c`. This is not
-  recommended because then it's not possible for the OS to disable the wake
-  source.
-* As of
-  [linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
-  the ACPI subsystem doesn't take the interrupt `wake` bit into account when
-  deciding on which power state to put the device in before suspending the
-  system. This means that if you define a power resource for a device via
-  `has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
-  device into D3Cold. i.e., power off the device.
-
-## Other auto-generated names
-
-(see [ACPI specification
-6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
-for more details on ACPI methods)
-
-### _S0W (S0 Device Wake State)
-\_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
-D3Hot means the `PR3` power resources are still on and the device is still
-responsive on the bus. For i2c devices this is generally the same state as `D0`.
-
-### \_PRW (Power Resources for Wake)
-\_PRW indicates the power resources and events required for wake.  There are no
-dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
-as well as the deepest sleep state supporting waking the system (3), which is
-S3.
-
-### \_STA (Status)
-The \_STA method is generated automatically, and its values, 0xF, indicates the
-following:
-
-    Bit [0] – Set if the device is present.
-    Bit [1] – Set if the device is enabled and decoding its resources.
-    Bit [2] – Set if the device should be shown in the UI.
-    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
-
-### \_CRS (Current resource settings)
-The \_CRS method is generated automatically, as the driver knows it is an I2C
-controller, and so specifies how to configure the controller for proper
-operation with the touchpad.
-
-```
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                    0x00, ResourceConsumer, , Exclusive, )
-```
-
-## Notes
-
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)

Documentation/drivers/index.md

@@ -4,14 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code across platforms.
 
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/external_docs.md

@@ -1,136 +0,0 @@
-# External Resources
-
-This is a list of resources that could be useful to coreboot developers.
-These are not endorsed or officially recommended by the coreboot project,
-but simply listed here in the hopes that someone will find something
-useful.
-
-Please add any helpful or informational links and sections as you see fit.
-
-## Articles
-
-* External Interrupts in the x86 system.
-  * [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
-  * [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
-  * [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
-* System address map initialization in x86/x64 architecture.
-  * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
-  * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
-  * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-
-
-## General Information
-
-* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-* [Interface BUS](http://www.interfacebus.com/)
-
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
-
-## Firmware Specifications & Information
-
-* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-
-
-### ACPI
-
-* [ACPI Specs](https://uefi.org/acpi/specs)
-* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-
-
-### Security
-
-* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-
-
-## Hardware information
-
-* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-* [Sandpile](https://www.sandpile.org/)
-* [CPU-World](https://www.cpu-world.com/index.html)
-* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-
-
-### Hardware Specifications & Standards
-
-* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
-* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
-  [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
-* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
-* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
-* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
-* [USB](https://www.usb.org/documents) - USB Implementers Forum
-* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
-
-
-### Chip Vendor Documentation
-
-* AMD
-  * [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
-  * [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
-* ARM
-  * [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
-* Intel
-  * [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
-  * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
-  * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
-  * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-
-* Rockchip
-  * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
-
-
-## Software
-
- * [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
- * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
- * [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
- * [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
- * [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
- * [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
-* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
-* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
-
-
-## Infrastructure software
-
-* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-* [GNU Make](https://www.gnu.org/software/make/manual/)

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/index.md

@@ -6,4 +6,3 @@
 * [Kconfig](kconfig.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/index.md

@@ -1,8 +1,9 @@
 # Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
-It is built from Markdown files in the [Documentation] directory in the
-source code.
+It is built from Markdown files in the
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
 
 ## Spelling of coreboot
 
@@ -25,7 +26,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 
@@ -142,7 +143,7 @@ say hello!
 ## Getting the source code
 
 coreboot is primarily developed in the
-[git](https://review.coreboot.org/plugins/gitiles/coreboot) version control
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
 system, using [Gerrit](https://review.coreboot.org) to manage
 contributions and code review.
 
@@ -192,12 +193,8 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Software Bill of Materials](sbom/sbom.md)
 * [Project infrastructure & services](infrastructure/index.md)
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Acronyms & Definitions](acronyms.md)
-* [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)
-
-[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/

Documentation/lib/fw_config.md

@@ -383,7 +383,7 @@ training.  This example expects that the default value of this `register` is set
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
+	if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
 		mupd->ExampleFeature = false;
 }
 ```

Documentation/mainboard/amd/pademelon/pademelon.md

@@ -1,80 +0,0 @@
-# Pademelon board
-
-## Specs (with Merlin Falcon SOC)
-
-* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
-  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
-* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
-  code is specific for Merlin Falcon SOC. Some specs will change if not
-  using Merlin Falcon.
-* One half mini PCI-Express slot on back side of mainboard
-* One PCI Express® 3.0 x8 slot
-* Two SATA3 ports with 6Gb/s data transfer rate
-* Two USB 2.0 ports at rear panel
-* Two USB 3.0 ports at rear panel
-* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
-* 6-channel High-Definition audio from Realtek ALC662 codec
-* One soldered down SPI flash with dediprog header
-
-## Mainboard
-
-![mainboard][pademelon]
-
-Three items are marked in this picture
-1. dediprog header
-2. memory dimms, address 0xA0 and 0xA4
-3. SATA cables connected to motherboard
-
-## Back panel
-
-![back panel][pademelon_io]
-
-* The lower serial port is UART A (debug serial)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+--------------------+
-| Type                | Value              |
-+=====================+====================+
-| Socketed flash      | no                 |
-+---------------------+--------------------+
-| Model               | Macronix MX256435E |
-+---------------------+--------------------+
-| Size                | 8 MiB              |
-+---------------------+--------------------+
-| Flash programming   | dediprog header    |
-+---------------------+--------------------+
-| Package             | SOIC-8             |
-+---------------------+--------------------+
-| Write protection    | No                 |
-+---------------------+--------------------+
-```
-
-## Technology
-
-```eval_rst
-+---------------+------------------------------+
-| Fan control   | Using fintek F81803A         |
-+---------------+------------------------------+
-| CPU           | Merlin Falcon (see reference)|
-+---------------+------------------------------+
-```
-
-## Description of pictures within this document
-
-```eval_rst
-+----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
-+----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
-+----------------------------+----------------------------------------+
-```
-
-## Reference
-
-[Merlin Falcon BKDG][merlinfalcon]
-
-[merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -0,0 +1,80 @@
+# Padmelon board
+
+## Specs (with Merlin Falcon SOC)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
+  code is specific for Merlin Falcon SOC. Some specs will change if not
+  using Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0 ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Mainboard
+
+![mainboard][padmelon]
+
+Three items are marked in this picture
+1. dediprog header
+2. memory dimms, address 0xA0 and 0xA4
+3. SATA cables connected to motherboard
+
+## Back panel
+
+![back panel][padmelon_io]
+
+* The lower serial port is UART A (debug serial)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------+
+| Type                | Value              |
++=====================+====================+
+| Socketed flash      | no                 |
++---------------------+--------------------+
+| Model               | Macronix MX256435E |
++---------------------+--------------------+
+| Size                | 8 MiB              |
++---------------------+--------------------+
+| Flash programming   | dediprog header    |
++---------------------+--------------------+
+| Package             | SOIC-8             |
++---------------------+--------------------+
+| Write protection    | No                 |
++---------------------+--------------------+
+```
+
+## Technology
+
+```eval_rst
++---------------+------------------------------+
+| Fan control   | Using fintek F81803A         |
++---------------+------------------------------+
+| CPU           | Merlin Falcon (see reference)|
++---------------+------------------------------+
+```
+
+## Description of pictures within this document
+
+```eval_rst
++----------------------------+----------------------------------------+
+|padmelon.jpg                | Motherboard with components identified |
++----------------------------+----------------------------------------+
+|padmelon_io.jpg             | Back panel picture                     |
++----------------------------+----------------------------------------+
+```
+
+## Reference
+
+[Merlin Falcon BKDG][merlinfalcon]
+
+[merlinfalcon]: ../../../soc/amd/family15h.md
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asrock/h77pro4-m.md

@@ -45,9 +45,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
 - Rear eSATA connector (multiplexed with one ASM1061 port)
 - Gigabit Ethernet
 - Console output on the serial port
-- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
-Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
-- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
+- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
 extlinux
 - Internal flashing with flashrom-1.2, see
 [Internal Programming](#internal-programming)

Documentation/mainboard/asus/p2b-ls.md

@@ -1,108 +0,0 @@
-# ASUS P2B-LS
-
-This page describes how to run coreboot on the ASUS P2B-LS mainboard.
-
-## Variants
-
-- P2B-LS
-- P2B-L (Same circuit board with SCSI components omitted)
-- P2B-S (Same circuit board with ethernet components omitted)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | no                        |
-+---------------------+---------------------------+
-| Dual BIOS feature   | no                        |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-[flashrom] works out of the box since 0.9.2.
-Because of deficiency in vendor firmware, user needs to override the laptop
-warning as prompted. Once coreboot is in place there will be no further issue.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- Ethernet (-LS, -L; Intel 82558)
-- SCSI (-LS, -S; Adaptec AIC7890)
-- USB
-- ISA add-on cards
-- PCI add-on cards
-- AGP graphics card
-- Floppy
-- Serial ports 1 and 2
-- Reboot
-- Soft off
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted.
-  With SeaBIOS as payload, setting keyboard initialization timeout to
-  500ms may fix the issue.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-- Termination is enabled for all SCSI ports (if equipped). Support to
-  disable termination is pending. Note that the SCSI-68 port is
-  always terminated, even with vendor firmware.
-
-## Untested
-
-- Parallel port
-- EDO memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- S3 suspend to RAM
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p3b-f.md

@@ -1,106 +0,0 @@
-# ASUS P3B-F
-
-This page describes how to run coreboot on the ASUS P3B-F mainboard.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | See below                 |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6.
-If you are using older versions of flashrom, below has to be done (with ACPI disabled!)
-before flashrom can detect the flash chip:
-
-```bash
-  #  rmmod w83781d
-  #  modprobe i2c-dev
-  #  i2cset 0 0x48 0x80 0x80
-```
-
-Upon power up, flash chip is inaccessible until flashrom has been run once.
-Since flashrom does not support reversing board enabling steps,
-once it detects the flash chip, there will be no write protection until
-the next power cycle.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- USB
-- PCI add-on cards
-- AGP graphics cards
-- Serial ports 1 and 2
-- Reboot
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS
-  as payload, setting keyboard initialization timeout to 2500ms may help.
-
-- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not
-  yet ready by the time SeaBIOS attempts to boot from them.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-## Untested
-
-- Floppy
-- Parallel port
-- EDO memory
-- ECC memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098))
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p8z77-m.md

@@ -1,137 +0,0 @@
-# ASUS P8Z77-M
-
-This page describes how to run coreboot on the [ASUS P8Z77-M].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+----------------+
-| Type                | Value          |
-+=====================+================+
-| Model               | W25Q64FVA1Q    |
-+---------------------+----------------+
-| Size                | 8 MiB          |
-+---------------------+----------------+
-| Package             | DIP-8          |
-+---------------------+----------------+
-| Socketed            | yes            |
-+---------------------+----------------+
-| Write protection    | yes            |
-+---------------------+----------------+
-| Dual BIOS feature   | no             |
-+---------------------+----------------+
-| Internal flashing   | yes            |
-+---------------------+----------------+
-```
-
-The flash chip is located between the blue SATA ports.
-
-The main SPI flash cannot be written internally because Asus disables BIOSWE and
-enables ``BLE/SMM_BWP`` flags in ``BIOS_CNTL`` for their latest bioses.
-To install coreboot for the first time, the flash chip must be removed and
-flashed with an external programmer; flashing in-circuit doesn't work.
-The flash chip is socketed, so it's easy to remove and reflash.
-
-## Working
-
-- All USB2 ports (mouse, keyboard and thumb drive)
-- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
-- Gigabit Ethernet (RTL8111F)
-- SATA3, SATA2 (all ports, hot-swap not tested)
-       (Blue SATA2)  (Blue SATA2)  (White SATA3)
-        port 5        port 3        port 1
-        port 6        port 4        port 2
-
-- CPU Temp sensors and hardware monitor (some values don't make sense)
-- Native and MRC memory initialization
-  (please see [Native raminit compatibility] and [MRC memory compatibility])
-
-- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
-  (VGA/DVI-D/HDMI tested and working)
-- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3
-  (Arch based))
-- Serial port
-- PCI slot
-  Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested)
-  Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from
-  SeaBIOS)
-- S3 suspend from Linux
-- 2-channel analog audio (WAV playback by mplayer via back panel line out port)
-- Windows 10 with libgfxinit high resolution framebuffer and VBT
-
-## Known issues
-
-- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could
-  be reconfigured by the blob.
-
-- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config.
-  Otherwise integrated graphics would fail with a black screen.
-
-- PCI POST card is not functional because the PCI bridge early init is not yet done.
-
-- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for
-  an x8, and is electrically an x4 only.
-
-## Untested
-
-- Wake-on-LAN
-- USB3 on header
-- TPM header
-- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
-- HDMI and S/PDIF audio out
-
-## Not working
-
-- PS/2 keyboard or mouse
-- 4 and 6 channel analog audio out: Rear left and right audio is a muted
-  copy of front left and right audio, and the other two channels are silent.
-
-## Native (and MRC) raminit compatibility
-
-- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
-
-- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable
-  with obvious pattern of bit errors during memtest86+ runs.
-
-- Samsung PC3-10600U 2x2GB kit works at full rated speed.
-
-- Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
-
-## Extra onboard buttons
-
-The board has two onboard buttons, and each has a related LED nearby.
-What controls the LEDs and what the buttons control are unknown,
-therefore they currently do nothing under coreboot.
-
-- BIOS_FLBK
-  OEM firmware uses this button to facilitate a simple update mechanism
-  via a USB drive plugged into the bottom USB port of the USB/LAN stack.
-
-- MemOK!
-  OEM firmware uses this button for memory tuning related to overclocking.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6779D                                 |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-- [Flash chip datasheet][W25Q64FVA1Q]
-
-[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/
-[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using edk2 + a PCIe GPU under Windows crashes with an
+- Using TianoCore + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
-- PS/2 mouse using edk2
-- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

Documentation/mainboard/facebook/monolith.md

@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
+All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

Documentation/mainboard/hp/2170p.md

@@ -1,91 +0,0 @@
-# HP EliteBook 2170p
-
-This page is about the notebook [HP EliteBook 2170p].
-
-## Release status
-
-HP EliteBook 2170p was released in 2012 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-1. EC firmware
-2. Intel ME firmware
-
-EC firmware can be retrieved from the HP firmware update image, or the firmware
-backup of the laptop. EC Firmware is part of the coreboot build process.
-The guide on extracting EC firmware and using it to build coreboot is in
-document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops).
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-## Programming
-
-The flash chip is located between the memory slots, WWAN card and CPU,
-covered by the base enclosure, which needs to be removed according to
-the [Maintenance and Service Guide] to access the flash chip. Unlike
-other variants, the flash chip on 2170p is socketed, so it can be taken
-off and operated with an external programmer.
-
-Pin 1 of the flash chip is at the side near the CPU.
-
-![Flash Chip in 2170p](2170p_flash.jpg)
-
-For more details have a look at the general [flashing tutorial].
-
-## Debugging
-
-The board can be debugged with serial port on the dock or EHCI debug.
-The EHCI debug port is the left USB3 port.
-
-## Test status
-
-### Known issues
-
-- GRUB payload freezes if at_keyboard module is in the GRUB image
-  ([bug #141])
-
-### Untested
-
-- Fingerprint Reader
-- Dock: Parallel port, PS/2 mouse, S-Video port
-
-### Working
-
-- Integrated graphics init with libgfxinit
-- SATA
-- Audio: speaker and microphone
-- Ethernet
-- WLAN
-- WWAN
-- Bluetooth
-- SD Card Reader
-- SmartCard Reader
-- USB
-- DisplayPort
-- Keyboard, touchpad and trackpoint
-- EC ACPI support and thermal control
-- Dock: all USB ports, DVI-D, Serial debug, PS/2 keyboard
-- TPM
-- Internal flashing when IFD is unlocked
-- Using `me_cleaner`
-
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Panther Point QM77                         |
-+------------------+--------------------------------------------------+
-| EC               | SMSC KBC1126                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[HP EliteBook 2170p]: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03387961.pdf
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -14,99 +14,30 @@ The following things are still missing from this coreboot port:
 ## Flashing coreboot
 
 ```eval_rst
-+---------------------+-------------------------+
-| Type                | Value                   |
-+=====================+=========================+
-| Socketed flash      | no                      |
-+---------------------+-------------------------+
-| Model               | MX25L6406E/MX25L6408E   |
-+---------------------+-------------------------+
-| Size                | 8 MiB                   |
-+---------------------+-------------------------+
-| In circuit flashing | yes                     |
-+---------------------+-------------------------+
-| Package             | SOIC-8                  |
-+---------------------+-------------------------+
-| Write protection    | bios region             |
-+---------------------+-------------------------+
-| Dual BIOS feature   | No                      |
-+---------------------+-------------------------+
-| Internal flashing   | yes                     |
-+---------------------+-------------------------+
-```
-
-### Flash layout
-The original layout of the flash should look like this:
-```
-00000000:00000fff fd
-00510000:007fffff bios
-00003000:0050ffff me
-00001000:00002fff gbe
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L6406E |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
 ```
 
 ### Internal programming
 
 The SPI flash can be accessed using [flashrom].
-```console
-$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
-```
-
-After shorting the FDO jumper you gain access to the full flash, but you
-still cannot write in the bios region due to SPI protected ranges.
-
-**Position of FDO jumper close to the IO and second fan connector**
-![][compaq_8200_jumper]
-
-[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg
-
-To write to the bios region you can use an [IFD Hack] originally developed
-for MacBooks, but with modified values described in this guide.
-You should read both guides before attempting the procedure.
-
-Since you can still write in the flash descriptor, you can shrink
-the ME and then move the bios region into where the ME originally was.
-coreboot does not by default restrict writing to any part of the flash, so
-you will first flash a small coreboot build and after it boots, flash
-the full one.
-
-The temporary flash layout with the neutered ME firmware should look like this:
-```
-00000000:00000fff fd
-00023000:001fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-00200000:007fffff pd
-```
-
-It is very important to use these exact numbers or you will need to fix it
-using external flashing, but you should already be familiar with the risks
-if you got this far.
-
-The temporary ROM chip size to set in menuconfig is 2 MB but the default
-CBFS size is too large for that, you can use up to about 0x1D0000.
-
-When building both the temporary and the permanent installation, don't forget
-to also add the gigabit ethernet configuration when adding the flash descriptor
-and ME firmware.
-
-You can pad the ROM to the required 8MB with zeros using:
-```console
-$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
-$ cat coreboot.rom 6M.bin > coreboot8.rom
-```
-
-If you want to continue using the neutered ME firmware use this flash layout
-for stage 2:
-```
-00000000:00000fff fd
-00023000:007fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-```
-
-If you want to use the original ME firmware use the original flash layout.
-
-More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md).
 
 ### External programming
 
@@ -143,7 +74,7 @@ as otherwise there's not enough space near the flash.
 | Coprocessor      | Intel ME                                         |
 +------------------+--------------------------------------------------+
 ```
-[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
+
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/folio_9480m.md

@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, edk2
+- Payload: SeaBIOS, Tianocore
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

Documentation/mainboard/index.md

@@ -11,7 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [G43T-AM3](acer/g43t-am3.md)
 
 ## AMD
-- [pademelon](amd/pademelon/pademelon.md)
+- [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
@@ -23,14 +23,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
-- [P2B-LS](asus/p2b-ls.md)
-- [P3B-F](asus/p3b-f.md)
 - [P5Q](asus/p5q.md)
 - [P8C WS](asus/p8c_ws.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8H77-V](asus/p8h77-v.md)
-- [P8Z77-M](asus/p8z77-m.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
 - [wifigo_v1](asus/wifigo_v1.md)
@@ -81,7 +78,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [HP Sure Start](hp/hp_sure_start.md)
-- [EliteBook 2170p](hp/2170p.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)
@@ -89,7 +85,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
-- [DQ67SW](intel/dq67sw.md)
+- [IceLake RVP](intel/icelake_rvp.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -150,6 +146,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 
@@ -173,8 +170,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [FW2B / FW4B](protectli/fw2b_fw4b.md)
 - [FW6A / FW6B / FW6C](protectli/fw6.md)
-- [VP2420](protectli/vp2420.md)
-- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
 
 ## Roda
 
@@ -191,7 +186,6 @@ The boards in this section are not real mainboards, but emulators.
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
-- [StarBook Mk VI](starlabs/starbook_adl.md)
 - [Flashing devices](starlabs/common/flashing.md)
 
 ## Supermicro
@@ -211,9 +205,9 @@ The boards in this section are not real mainboards, but emulators.
 - [Darter Pro 8](system76/darp8.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
-- [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Lemur Pro 11](system76/lemp11.md)
@@ -222,7 +216,6 @@ The boards in this section are not real mainboards, but emulators.
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
 - [Oryx Pro 9](system76/oryp9.md)
-- [Oryx Pro 10](system76/oryp10.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/dq67sw.md

@@ -1,170 +0,0 @@
-# Intel DQ67SW
-
-The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel Q67 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1333                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton/Winbond W83677HG-i                       |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82579LM Gigabit Ethernet                   |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header                                  |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- Integrated GPU with libgfxinit
-- PCIe graphics in the PEG slot
-- Additional PCIe slots
-- PCI slot
-- All rear (4x) and internal (8x) USB2 ports
-- Rear USB3 ports (2x)
-- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
-- Two rear eSATA connectors (3 Gb/s)
-- SATA at 6 Gb/s
-- Gigabit Ethernet
-- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
-- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
-- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
-    - slackware64 (Linux 5.15)
-    - Windows 10 (22H2)
-- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
-- Poweroff
-- Resume from S3
-- Console output on the serial port
-
-### Not working
-
-- Automatic fan control. One can still use OS-based fan control programs,
-  such as fancontrol on Linux or SpeedFan on Windows.
-- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
-  works, but once Windows Update installs drivers, it crashes and enters a
-  bootloop.
-
-### Untested
-
-- Firewire (LSI L-FW3227-100)
-- EHCI debug
-- S/PDIF audio
-- Audio jacks other than the green one
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | yes        |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | see below  |
-+---------------------+------------+
-| In circuit flashing | see below  |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-
-    00000000:00000fff fd
-    00580000:007fffff bios
-    00003000:0057ffff me
-    00001000:00002fff gbe
-
-Unfortunately the SPI interface to the chip is locked down by the vendor
-firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
-the PCI configuration space of the LPC Interface Bridge, is set.
-
-It is possible to program the chip is to attach an external programmer
-with an SOIC-8 clip.
-
-```eval_rst
-Another way is to boot the vendor firmware in UEFI mode and exploit the
-unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
-
-On this specific board it is possible to prevent the BLE bit from being set
-when it resumes from S3. One entry in the S3 Boot Script must be modified,
-e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
-that supports this specific type of S3 Boot Script, for example from strobo5:
-
-    $ git clone -b headerless https://github.com/strobo5/chipsec.git
-    $ cd chipsec
-    $ python setup.py build_ext -i
-    $ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
-
-The boot script contains an entry that writes 0x02 to memory at address
-0xe00f80dc. This address points at the PCIe configuration register at offset
-0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
-Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
-prevents this by making it write a 0 instead.
-
-```eval_rst
-After suspending and resuming the board, the BIOS region can be flashed with
-a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
-so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-## Hardware monitoring and fan control
-
-Currently there is no automatic, OS-independent fan control.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## References
-
-[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
-May 2011,
-Document number 324645-006
-
-[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
-December 2008,
-Document number 321090
-

Documentation/mainboard/intel/icelake_rvp.md

@@ -0,0 +1,40 @@
+# Intel Ice Lake RVP (Reference Validation Platform)
+
+This page describes how to run coreboot on the Intel icelake_rvp board.
+
+Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+## Building coreboot
+
+* Follow build instructions mentioned in Ice Lake document
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+* The default options for this board should result in a fully working image:
+```bash
+	# echo "CONFIG_VENDOR_INTEL=y" > .config
+	# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
+	# make olddefconfig && make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```

Documentation/mainboard/kontron/mal10.md

@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- edk2
+- Tianocore
 - Linux as payload
 
 ## Flashing coreboot

Documentation/mainboard/ocp/deltalake.md

@@ -26,12 +26,12 @@ host up to 4 Delta Lake servers (blades) in one sled.
 
 The Yosemite-V3 system is in mass production. Meta, Intel and partners
 jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
-solution. The OSF solution reached production quality for some use cases
-in July, 2021.
+solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
+OSF solution reached production quality for some use cases in July, 2021.
 
 ## How to build
 
-OSF code base is publicly available at
+OSF code base is public at
 https://github.com/opencomputeproject/OpenSystemFirmware
 
 Run following commands to build Delta Lake OSF image from scratch:
@@ -42,21 +42,19 @@ The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
 Linux kernel and u-root code from their upstream repo, and sync down needed
 binary blobs. [osf-builder] also provides the top level build system.
 
-Besides coreboot, the Delta Lake OSF solution includes following components:
-- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
-  is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
-- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
-- ME ignition binary: downloaded from
+Delta Lake server OSF solution requires following binary blobs:
+- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
+  can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
+- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
+  coreboot.org mirrors this repo and by default the correct binary is included.
+- ME binary: Ignition binary can be downloaded from
 	https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
 - ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
 - Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
-  U-root as initramfs, is used in the joint development. It is built
+  U-root as initramfs, is used in the joint development. It can be built
   following [All about u-root].
 
-The Delta Lake OSF solution is updated periodically to newer versions of
-upstream coreboot code base and other components.
-
-## How to verify Delta Lake OSF image
+## Flashing coreboot
 
 To do in-band FW image update, use [flashrom]:
     flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
@@ -72,21 +70,6 @@ To power off/on the host:
 To connect to console through SOL (Serial Over Lan):
     sol-util slotx
 
-## How to work on coreboot for Delta Lake
-After the OSF image for Delta Lake is built and verified, under
-OpenSystemFirmware/Wiwynn/deltalake directory:
-    cd src/osf-builder/projects/craterlake/coreboot
-
-Run "git remote -v" to confirm the origin is from coreboot upstream repo.
-
-Run "git branch -v" to know the confirmed working coreboot commit ID for the
-Delta Lake OSF solution.
-
-Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
-image for Delta Lake, verify that it works.
-
-Now you are in a familiar coreboot environment, happy coding!
-
 ## Firmware configurations
 [ChromeOS VPD] is used to store most of the firmware configurations.
 RO_VPD region holds default values, while RW_VPD region holds customized

Documentation/mainboard/opencellular/rotundu.md

@@ -0,0 +1,76 @@
+# Rutundu
+
+This page describes how to run coreboot on the [Rotundu] compute board
+from [OpenCellular].
+
+## TODO
+
+* Configure UART
+* EC interface
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q128    |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit.
+Directly connecting a Pomona test-clip on the flash is also possible.
+
+**Closeup view of SOIC-8 flash IC**
+
+![][rotundu_flash]
+
+[rotundu_flash]: rotundu_flash.jpg
+
+**SPI header**
+
+![][rotundu_header2]
+
+[rotundu_header2]: rotundu_header2.jpg
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][rotundu_j16]
+
+[rotundu_j16]: rotundu_j16.png
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Baytrail                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Rotundu]: https://github.com/Telecominfraproject/OpenCellular
+[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/protectli/vp2420.md

@@ -1,87 +0,0 @@
-# Protectli Vault VP2420
-
-This page describes how to run coreboot on the [Protectli VP2420].
-
-![](VP2420_back.jpg)
-![](VP2420_front.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. Firmware can be easily
-flashed with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is soldered in
-under RAM, easily accessed after taking out the memory. Specifically, it's a
-KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](VP2420_internal.jpg)
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 4 Ethernet ports
-- HDMI, DisplayPort
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector
-- SMBus (reading SPD from DIMMs)
-- Initialization with Elkhart Lake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Celeron J6412                              |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Elkhart Lake                               |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8613E                                      |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
-- [VP2420 Product Page](https://protectli.com/product/vp2420/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-- [flashrom](https://flashrom.org/Flashrom)

Documentation/mainboard/protectli/vp46xx.md

@@ -1,135 +0,0 @@
-# Protectli Vault VP46xx series
-
-This page describes how to run coreboot on the [Protectli VP46xx].
-
-![](vp46xx_front.jpg)
-![](vp46xx_back.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule. VP4630 and VP4650 use CometLake2 FSP and VP4670
-use CometLake1 FSP (see [variants](#variants) section), so be sure to select
-the correct board in the coreboot's menuconfig, otherwise the platform will not
-succeed on memory initialization.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. The first version
-supporting the chipset is flashrom v1.2. Firmware an be easily flashed
-with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB socketed SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is near the M.2
-WiFi slot connector. Remove the chip from socket and use a clip to program the
-chip. Specifically, it's a KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](vp46xx_flash.jpg)
-
-## Known issues
-
-- After flashing with external programmer it is always required to reset RTC
-  with a jumper or disconnect the coin cell temporarily. Only then the platform
-  will boot after flashing.
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 6 Ethernet ports
-- HDMI, DisplayPort and USB-C Display Port with libgfxinit and FSP GOP
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector (Fintek F81232 USB to
-  UART adapter present on board)
-- SMBus (reading SPD from DIMMs)
-- Initialization with CometLake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- LPC TPM module (using Protectli custom-designed module with Infineon SLB9660)
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Variants
-
-There are 3 variants of VP46xx boards: VP4630, VP4650 and VP4670. They differ
-only in used SoC and some units may come with different Super I/O chips, either
-ITE IT8786E or IT8784E, but the configuration is the same on this platform.
-
-- VP4630:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i3-10110U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4650:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i5-10210U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4670:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-10810U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
-- [VP4630 Product Page](https://protectli.com/product/vp4630/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-
-[Protectli VP46xx]: https://protectli.com/vault-6-port/
-[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/purism/librem_14.md

@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

Documentation/mainboard/purism/librem_mini.md

@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

Documentation/mainboard/starlabs/common/building.md

@@ -1,30 +0,0 @@
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-
-#### StarBook series:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-#### StarLite series:
-* Intel Flash Descriptor file (descriptor.bin)
-* IFWI Image (ifwi.rom)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image, where the last two words represent the
-series and processor i.e. `lite_glkr`:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -38,7 +38,26 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+
+The below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,26 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* IFWI Image (ifwi.rom)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/starbook_adl.md

@@ -1,88 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-1260P (Alder Lake)
-    - Intel i3-1220P (Alder Lake)
-- EC
-    - ITE IT5570E
-    - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 14-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 2 x DDR4 SODIMM
-- Networking
-    - AX210 2230 WiFi / Bluetooth
-- Sound
-    - Realtek ALC269-VB6
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-    - USB 2.0 Type-A (right)
-
-## Building coreboot
-
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | W25Q256.V  |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/system76/galp6.md

@@ -1,61 +0,0 @@
-# System76 Galago Pro 6 (galp6)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1240P
-  - Intel Core i7-1260P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/mainboard/system76/gaze17.md

@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B256E           |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/mainboard/system76/oryp10.md

@@ -1,69 +0,0 @@
-# System76 Oryx Pro 10 (oryp10)
-
-## Specs
-
-- CPU
-  - Intel Core i7-12700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
-    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
-  - eDP options:
-    - 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
-    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
-    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
-  - 80Wh 6-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1306 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
-  - 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
-
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the DIMM slots.

Documentation/mainboard/system76/oryp9.md

@@ -7,40 +7,17 @@
 - EC
   - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
 - Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
-    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
-  - eDP options:
-    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
-    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
 - Memory
   - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
 - Networking
   - Gigabit Ethernet
   - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
 - Power
-  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
-  - 80Wh 6-cell Lithium-ion battery
 - Sound
-  - Realtek ALC1220 codec
-  - TI TAS5825M smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
 - Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (RTS5227S)
 - USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
 - Dimensions
-  - 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
-  - 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
+  - 35.8cm x 24.0cm x 2.49cm, 2.4kg
 
 ## Flashing coreboot
 

Documentation/payloads.md

@@ -23,11 +23,13 @@ When chainloaded from GRUB2, the following menuentry could be used:
         module /vgaroms/seavgabios.bin
     }
 
-## edk2
+## Tianocore
 
-[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
-cross-platform firmware development environment for the UEFI and UEFI
-Platform Initialization (PI) specifications.
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 

Documentation/releases/boards_supported_on_branches.md

@@ -12,94 +12,16 @@ desired.
 
 Currently, [jenkins](https://qa.coreboot.org), our continuous
 integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, 4.18, and 4.19 branches.  Builders for other branches can be
-added upon request.  Likewise, some releases are only marked with tags,
-and branches would need to be created to push new code.  These branches
+and 4.16 branches.  Builders for other branches can be created on
+request.  Likewise, some releases are only marked with tags, and
+branches would need to be created to push new code to.  These branches
 can also be created on request.
 
 Patches can be backported from the master branch to any of these other
-branches as needed. The coreboot project may take care of backporting
+branches as needed. The coreboot project will take care of backporting
 critical security fixes, but other patches will need to handled by
 anyone using that release.
 
-
-## [4.19 Release](coreboot-4.19-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| intel/icelake_rvp             | INTEL_ICELAKE          | 2018-10-26 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
-## [4.18 Release](coreboot-4.18-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
-| asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
-| bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-+-------------------------------+------------------------+------------+-----------+
-| gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-| gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-+-------------------------------+------------------------+------------+-----------+
-| hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
-| jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-+-------------------------------+------------------------+------------+-----------+
-| lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
-| lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-+-------------------------------+------------------------+------------+-----------+
-| msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
-| pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
-
-## [4.17 Release](coreboot-4.17-relnotes.md)
-No Branch or builder
-
-* No platforms maintained on this release
-
-
 ## [4.16 Release](coreboot-4.16-relnotes.md)
 Branch created, builder configured
 
@@ -120,449 +42,249 @@ Branch created, builder configured
 
 ## [4.13 Release](coreboot-4.13-relnotes.md)
 Tag only
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.12 Release](coreboot-4.12-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.11 Release](coreboot-4.11-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.10 Release](coreboot-4.10-relnotes.md)
 Branch created
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.9 Release](coreboot-4.9-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-+-----------------------------+------------------------+------------+----------+
 | artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-+-----------------------------+------------------------+------------+----------+
 | winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.7 Release](coreboot-4.7-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-+-----------------------------+------------------------+------------+----------+
 | rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
 | wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.6](coreboot-4.6-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.5](coreboot-4.5-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.4](coreboot-4.4-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.3](coreboot-4.3-relnotes.md)
@@ -574,51 +296,28 @@ Branch created
 ## [4.2](coreboot-4.2-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.1](coreboot-4.1-relnotes.md)

Documentation/releases/checklist.md

@@ -4,73 +4,56 @@
 
 # coreboot Release Process
 
-This document describes our release process and all prerequisites to
-implement it successfully.
-
+This document describes our release process and all prerequisites to implement
+it successfully.
 
 ## Purpose of coreboot releases
-Our releases aren't primarily a vehicle for code that is stable across
-all boards: The logistics of testing the more than 100 boards that are
-spread out all continents (except Antarctica, probably) on a given tree
-state are prohibitive for project of our size.
+Our releases aren't primarily a vehicle for code that is stable across all
+boards: The logistics of testing the more than 100 boards that are spread out
+all continents (except Antarctica, probably) on a given tree state are
+prohibitive for project of our size.
 
-Instead, the releases are regular breakpoints that serve multiple
-purposes: They support cooperation between multiple groups (corporations
-or otherwise) in that it's easier to keep source trees synchronized
-based on a limited set of commits. They allow a quick assessment of the
-age of any given build or source tree based on its git version (4.8-1234
-was merged into master a few months after 4.8, which came out in April
-of 2018. 4.0-21718's age is harder to guess).
+Instead, the releases are regular breakpoints that serve multiple purposes:
+They support cooperation between multiple groups (corporations or otherwise)
+in that it's easier to keep source trees synchronized based on a limited set
+of commits. They allow a quick assessment of the age of any given build or
+source tree based on its git version (4.8-1234 was merged into master a few
+months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
+guess).
 
-And finally we use releases to as points in time where we remove old
-code: Once we decide that a certain part of coreboot gets in the way of
-future development, we announce on the next release that we intend to
-remove that part - and everything that depends on it - after the
-following release. So removing feature FOO will be announced in release
-X for release X+1. The first commit after X+1 is fair game for such
-removal.
+And finally we use releases to as points in time where we remove old code:
+Once we decide that a certain part of coreboot gets in the way of future
+development, we announce on the next release that we intend to remove that
+part - and everything that depends on it - after the following release.
+So removing feature FOO will be announced in release X for release
+X+1. The first commit after X+1 is fair game for such removal.
 
-Together with our 3 months release horizon, this provides time to plan
+Together with our 6 months release horizon, this provides time to plan
 any migrations necessary to keep older boards in the tree by bringing
 them up to current standards.
 
-## coreboot release team
-To avoid issues of blocking the release on a single person, a release
-team has been formed. Please see the `COREBOOT RELEASES` section of the
-MAINTAINERS file for the current members.
-
-These individuals work together to make sure releases are done on time,
-follow the steps of this document, and update the release processes and
-scripts.
-
-
 ## Needed credentials & authorizations
-
-### coreboot admins only
 * Website access is required to post the release files to the website.
-
-### All release team members
-* IRC topic access is required to update the topic.
+* IRC admin access is required to update the topic.
 * Git access rights are needed to post the tag.
 * Blog post access is needed to do the blog post.
 * A PGP key is required to sign the release tarballs and git tag.
 
-Most of the steps in the release process can be done by anyone on the
-release team. Only adding the files to the website needs to be done
-by a coreboot administrator.
+This set of required credentials implies that releases can only be done
+by a coreboot admin.
 
 ## When to release
-Releases are done roughly on a 3-month schedule. If a release is
-delayed, the next release will still be 3 months after the last release.
+Releases are done roughly on a 6-month schedule, ideally around end
+of April and end of October (can be a bit earlier or delay into May
+or November).
 
+We initially followed a 3 month release schedule, but we found that to
+be more frequent than was needed, so we scaled it back to twice a year.
 
 ## Checklist
-
 ### ~2 weeks prior to release
 - [ ] Announce upcoming release to mailing list, ask people to test and
       to update release notes.
-- [ ] Start marking patches that should to go into the release with a
-      tag "coreboot_release_X.yy"
 
 ### ~1 week prior to release
 - [ ] Send reminder email to mailing list, ask for people to test,
@@ -83,53 +66,28 @@ delayed, the next release will still be 3 months after the last release.
 - [ ] Finalize release notes as much as possible
 - [ ] Prepare release notes template for following release
 - [ ] Update `Documentation/releases/index.md`
-- [ ] Check which branches need to be released. Any branch with changes
-      should get a new release. Announce these branch releases and
-      prepare release notes.
-
-### Day before release
-- [ ] Make sure patches with tags for the release are merged.
-- [ ] Announce to IRC that the release will be tomorrow and ask for
-      testing.
 - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
       boards supported by vboot.
 
 ### Day of release
-- [ ] Review the full documentation about doing the release below.
-- [ ] Select a commit ID to base the release upon.
+- [ ] Select a commit ID to base the release upon, announce to IRC,
+      ask for testing.
 - [ ] Test the commit selected for release.
-- [ ] Submit last pre-release release notes.
-- [ ] Run the release script.
+- [ ] Submit release notes
+- [ ] Create new release notes doc template for the next version.
+- [ ] Fill in the release date, remove "Upcoming release" and other filler
+      from the current release notes.
+- [ ] Run release script.
 - [ ] Test the release from the actual release tarballs.
-- [ ] Push signed Tag to repo. *This is the actual release step.*
-      Once this patch is pushed, the release itself has been done.
-      everything after this step is packaging and delivering the
-      release.
-
+- [ ] Push signed Tag to repo.
 - [ ] Announce that the release tag is done on IRC.
-- [ ] Update the topic in the IRC channel that the release is done.
-
-- [ ] Do the final release notes - Fill in the release date, remove
-      "Upcoming release" and other filler from the current release
-      notes.
-- [ ] ADMIN: Upload release files to web server.
-- [ ] ADMIN: Upload the final release notes to the web server.
-- [ ] ADMIN: Upload crossgcc sources to web server.
-- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images
-      based on the release ID and push them to dockerhub. These
-      can be used as release builders.
-
-### Week following the release
+- [ ] Upload release files to web server.
+- [ ] Also extract the release notes and place them on the web server.
+- [ ] Upload crossgcc sources to web server.
 - [ ] Update download page to point to files, push to repo.
-- [ ] Write and publish blog post with release final notes. Branch
-      releases notes should be included in the same post.
-- [ ] Remove code that was announced it was going to be removed.
-- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
-
-### Creating a branch
-- [ ] Branches are named 4.xx_branch to differentiate from the tags.
-      Instructions on creating branches are listed below.
-
+- [ ] Write and publish blog post with release notes.
+- [ ] Update the topic in the IRC channel that the release is done.
+- [ ] Announce the release to the mailing list.
 
 ## Pre-Release tasks
 Announce the upcoming release to the mailing list release 2 weeks ahead
@@ -144,30 +102,29 @@ People should be encouraged to provide additions to the release notes.
 
 The final release notes will reside in coreboot's Documentation/releases
 directory, so asking for additions to that through the regular Gerrit
-process works as well. Note that git requires lots of conflict
-resolution on heavily edited text files though.
+process works as well. Note that git requires lots of conflict resolution
+on heavily edited text files though.
 
 Frequently, we will want to wait until particular things are in the
-release. Once those are in, you can select the commit ID that you want
-to use for your release. For the 4.6 release, we waited until we had
+release.  Once those are in, you can select the commit ID that you want
+to use for your release.  For the 4.6 release, we waited until we had
 time to do the release, then pulled in a few patches that we wanted
-to have in the release. The release was based on the final of those
+to have in the release.  The release was based on the final of those
 patches to be pulled in.
 
 When a release candidate has been selected, announce the commit ID to
 the #coreboot IRC channel, and request that it get some testing, just
 to make sure that everything is sane.
 
-
 ## Generate the release
 After the commit for the release has been selected and verified, run the
-release script - util/release/build-release. This will download a new
+release script - util/release/build-release.  This will download a new
 tree, checkout the commit that you specified, download the submodules,
 create a tag, then generate and sign the tarballs.
 
-**Be prepared to type in your PGP key’s passphrase.**
+Be prepared to type in your PGP key’s passphrase.
 
-```text
+````
 usage: util/release/build-release <version> [commit id] [username] [gpg key id]
 Tags a new coreboot version and creates a tar archive
 
@@ -175,41 +132,37 @@ version:    New version name to tag the tree with
 commit id:  check out this commit-id after cloning the coreboot tree
 username:   clone the tree using ssh://USERNAME - defaults to https://
 gpg key id: used to tag the version, and generate a gpg signature
-```
+````
 
-After running the script, you should have a new directory for the
-release, along with 4 files: 2 tarballs, and 2 signature files.
+After running the script, you should have a new directory for the release,
+along with 4 files - 2 tarballs, and 2 signature files.
 
-```text
+````
 drwxr-xr-x   9 martin martin      4096 Apr 30 19:57 coreboot-4.6
 -rw-r--r--   1 martin martin  29156788 Apr 30 19:58 coreboot-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
 -rw-r--r--   1 martin martin   5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
-```
+````
 
 Here’s the command that was used to generate the 4.6 release:
-```bash
-util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
-```
-
+````
+% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
+````
 
 ## Test the release from the tarballs
 * Run “make what-jenkins-does” and verify that everything is building.
 * Build and test qemu
-```bash
-cp configs/config.emulation_qemu_x86_i440fx .config
-make olddefconfig
-make
-qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
-```
+  ````
+  cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
+  qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+  ````
 * Build and test any other platforms you can.
-* Compare the directory from the tarballs to the coreboot repo to make
-  sure nothing went wrong.
+* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
 * Push the tag to git
 
 A good tag will look like this:
-````text
+````
 % git show 4.6
 tag 4.6
 Tagger: Martin Roth <martinroth@google.com>
@@ -230,44 +183,33 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
 ...
 ````
 
-When you used the script to generate the release, a signed tag was
-generated in the tree that was downloaded. From the coreboot-X.Y tree,
-just run: `git push origin X.Y`. In case you pushed the wrong tag
-already, you have to force push the new one.
+When you used the script to generate the release, a signed tag was generated in the
+tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
+In case you pushed the wrong tag already, you have to force push the new one.
 
 You will need write access for tags to the coreboot git repo to do this.
 
-
 ## After the release is tagged in git
 Announce that the release has been tagged - this lets people know that
-they should update their trees to grab the new tag. Until they do this,
+they should update their trees to grab the new tag.  Until they do this,
 the version number in build.h will still be based on the previous tag.
 
 Copy the tarballs and .sig files generated by the script to
 the coreboot server, and put them in the release directory at
 `/srv/docker/www.coreboot.org-staticfiles/releases/`
 
-````bash
-# Update the sha256sum file
-sha256sum -b coreboot-*.tar.xz > sha256suma.txt
-
-# make sure the two new files are present (and nothing else has changed)
-diff sha256sum.txt sha256suma.txt
-
-mv sha256suma.txt sha256sum.txt
+````
+% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
+% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
+% mv sha256suma.txt sha256sum.txt
 ````
 
 People can now see the release tarballs on the website at
 <https://www.coreboot.org/releases/>
 
-The downloads page is the official place to download the releases from,
-and it needs to be updated with links to the new release tarballs and
-.sig files. It can be found at:
-<https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
-
-Here is an example commit to change it:
-<https://review.coreboot.org/c/homepage/+/19515>
+The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
 
+Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
 
 ## Upload crossgcc sources
 Sometimes the source files for older revisions of
@@ -277,32 +219,24 @@ sources used by the crossgcc scripts that are part of coreboot releases.
 
 Run
 
-````bash
-util/crossgcc/buildgcc -u
+````
+% util/crossgcc/buildgcc -u
 ````
 
 This will output the set of URLs that the script uses to download the
 sources. Download them yourself and copy them into the crossgcc-sources
 directory on the server.
 
-
 ## After the release is complete
-Post the final release notes on <https://blogs.coreboot.org>
-
+Post the release notes on <https://blogs.coreboot.org>
 
 ## Making a branch
 At times we will need to create a branch, generally for patch fixes.
-When making a branch, do NOT name it the same as the release tag: X.Y -
-this creates trouble when trying to check it out, as git can’t tell
-whether you want the tag or the branch. Instead, name it X.Y\_branch:
-```bash
-git checkout 4.8
-git checkout -b 4.8_branch
-git push origin 4.8_branch
-```
+When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git can’t tell whether you want the tag or the branch.
+Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
 
 You can then cherry-pick changes and push them up to the branch:
-````bash
+````
 git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
 git push origin HEAD:refs/for/4.8_branch
 ````

Documentation/releases/coreboot-4.15-relnotes.md

@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single edk2 package/target.
+that we're only building from a single Tianocore package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

Documentation/releases/coreboot-4.17-relnotes.md

@@ -296,36 +296,6 @@ noting, but not needing a full description.
 * sandybridge & gm45: Support setting PCI bars above 4G
 
 
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the V4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the V4
-allocator.
-
-
 Plans for Code Deprecation
 --------------------------
 

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,190 +1,51 @@
-coreboot 4.18 release
-========================================================================
+Upcoming release - coreboot 4.18
+================================
 
-The 4.18 release was quite late, but was completed on October 16, 2022.
+The 4.18 release is planned for August 2022.
 
-In the 4 months since the 4.17 release, the coreboot project has merged
-more than 1800 commits from over 200 different authors. Over 50 of those
-authors submitted their first patches.
+Update this document with changes that should be in the release notes.
 
-Welcome and thank you to all of our new contributors, and of course the
-work of all of the seasoned contributors is greatly appreciated.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
 
 
-Significant or interesting changes
-----------------------------------
-
-### sconfig: Allow to specify device operations
-
-Currently we only have runtime mechanisms to assign device operations to
-a node in our devicetree (with one exception: the root device). The most
-common method is to map PCI IDs to the device operations with a `struct
-pci_driver`. Another accustomed way is to let a chip driver assign them.
-
-For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
-ID lists grew very large and are incredibly error-prone. Often, IDs are
-missing and sometimes IDs are added almost mechanically without checking
-the code for compatibility. Maintaining these lists in a central place
-also reduces flexibility.
-
-Now, for onboard devices it is actually unnecessary to assign the device
-operations at runtime. We already know exactly what operations should be
-assigned. And since we are using chipset devicetrees, we have a perfect
-place to put that information.
-
-This patch adds a simple mechanism to `sconfig`. It allows us to speci-
-fy operations per device, e.g.
-
-device pci 00.0 alias system_agent on
-	ops system_agent_ops
-end
-
-The operations are given as a C identifier. In this example, we simply
-assume that a global `struct device_operations system_agent_ops` exists.
 
 
-### Set touchpads to use detect (vs probed) flag
-
-Historically, ChromeOS devices have worked around the problem of OEMs
-using several different parts for touchpads/touchscreens by using a
-ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
-to indicate that the device may or may not be present, and that the
-driver should probe to confirm device presence.
-
-Since release 4.18, coreboot  supports detection for i2c devices at
-runtime when creating the device entries for the ACPI/SSDT tables,
-rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
-in the tree from using the 'probed' flag to the 'detect' flag.
-
-Touchscreens require more involved power sequencing, which will be done
-at some future time, after which they will switch over as well.
 
 
-### Add SBOM (Software Bill of Materials) Generation
-
-Firmware is typically delivered as one large binary image that gets
-flashed. Since this final image consists of binaries and data from a
-vast number of different people and companies, it's hard to determine
-what all the small parts included in it are. The goal of the software
-bill of materials (SBOM) is to take a firmware image and make it easy to
-find out what it consists of and where those pieces came from.
-
-Basically, this answers the question, who supplied the code that's
-running on my system right now? For example, buyers of a system can use
-an SBOM to perform an automated vulnerability check or license analysis,
-both of which can be used to evaluate risk in a product. Furthermore,
-one can quickly check to see if the firmware is subject to a new
-vulnerability included in one of the software parts (with the specified
-version) of the firmware.
-
-Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
-
-- Add Makefile.inc to generate and build coswid tags
-- Add templates for most payloads, coreboot, intel-microcode,
-  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
-  intel ME and compiler (gcc,clang,other)
-- Add Kconfig entries to optionally supply a path to CoSWID tags
-  instead of using the default CoSWID tags
-- Add CBFS entry called SBOM to each build via Makefile.inc
-- Add goswid utility tool to generate SBOM data
 
 
-Additional coreboot changes
----------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Allocator v4 is not yet ready, but received significant work.
-* Console: create an [smbus console driver](https://doc.coreboot.org/technotes/console.html)
-* pciexp_device: Numerous updates and fixes
-* Update checkpatch to match Linux v5.19
-* Continue updating ACPI to ASL 2.0 syntax
-* arch/x86: Add a common romstage entry point
-* Documentation: Add a list of [acronyms](https://doc.coreboot.org/acronyms.html)
-* Start hooking up ops in devicetree
-* Large amounts of general code cleanup and improvement, as always
-* Work to make sure all files have licenses
-
-
-Payloads
---------
-
-### EDK II (TianoCore)
-
-coreboot uses TianoCore interchangeably with EDK II, and whilst the
-meaning is generally clear, it's not the payload it uses.
-Consequentially, TianoCore has been renamed to EDK II (2).
-
-The option to use the already deprecated CorebootPayloadPkg has been
-removed.
-
-Recent changes to both coreboot and EDK means that UefiPayloadPkg seems
-to work on all hardware. It has been tested on:
-
-* Intel Core 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 8th, 9th, 10th,
-  11th and 12th generation processors
-* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
-* AMD Stoney Ridge and Picasso
-
-CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
-
-The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
-`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
-
-
-New Mainboards
---------------
-
-* AMD Birman
-* AMD Pademelon renamed from Padmelon
-* Google Evoker
-* Google Frostflow
-* Google Gaelin4ADL
-* Google Geralt
-* Google Joxer
-* Google Lisbon
-* Google Magikarp
-* Google Morthal
-* Google Pujjo
-* Google Rex 0
-* Google Shotzo
-* Google Skolas
-* Google Tentacruel
-* Google Winterhold
-* Google Xivu
-* Google Yaviks
-* Google Zoglin
-* Google Zombie
-* Google Zydron
-* MSI PRO Z690-A WIFI DDR4
-* Siemens MC APL7
-
-
-Removed Mainboards
-------------------
-
-* Google Brya4ES
-
-
-Updated SoCs
-------------
-
-* Added Intel Meteor Lake
-* Added Mediatek Mt8188
-* Renamed AMD Sabrina to Mendocino
-* Added AMD Morgana
 
 
 Plans for Code Deprecation
 --------------------------
 
+
+### Intel Icelake
+
+Intel Icelake code will be removed following the 4.19 release, planned
+for November 2022. This consists of the Intel Icelake SOC and Intel
+Icelake RVP mainboard
+
+Intel Icelake is unmaintained. Also, the only user of this platform ever
+was the CRB board. From the looks of it the code never was ready for
+production as only engineering sample CPUIDs are supported. This reduces
+the maintanence overhead for the coreboot project.
+
+
 ### LEGACY_SMP_INIT
 
 Legacy SMP init will be removed from the coreboot master branch
 immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch or tag.
+version of the code should find it on the 4.18 branch.
 
 This also includes the codepath for SMM_ASEG. This code is used to start
 APs and do some feature programming on each AP, but also set up SMM.
@@ -193,96 +54,3 @@ cover all use cases of LEGACY_SMP_INIT, with little code changes. The
 reason for deprecation is that having 2 codepaths to do the virtually
 the same increases maintenance burden on the community a lot, while also
 being rather confusing.
-
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from commit d2d9021543 to f4c97ea131
------------------------------------------------
-
-- Total Commits: 1822
-- Average Commits per day: 13.38
-- Total lines added: 150578
-- Average lines added per commit: 82.64
-- Number of patches adding more than 100 lines: 128
-- Average lines added per small commit: 38.44
-- Total lines removed: 33849
-- Average lines removed per commit: 18.58
-- Total difference between added and removed: 116729
-- Total authors: 202
-- New authors: 52
-
-
-Known Issues
-------------
-
-A couple of issues were discovered immediately following the release
-that will be fixed in a follow-on point release in the upcoming weeks.
-
-A pair of changes ([CB:67754](https://review.coreboot.org/67754) and
-[CB:67662](https://review.coreboot.org/67662)) which merged shortly
-before the 4.18 release have created an issue on Intel Apollo Lake
-platform boards which prevents SMM/SMI from functioning; this affects
-only Apollo Lake (but not Gemini Lake) devices.
-See [CB:68599](https://review.coreboot.org/68599) for the fix.
-
-Another issue applies to all Intel-based boards with onboard I2C TPMs
-when verified boot is not enabled. The I2C buses don’t get initialized
-until after the TPM, causing timeouts, TPM initialization failures, and
-long boot times.  See [CB:68550](https://review.coreboot.org/68550) for
-the fix.

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,246 +0,0 @@
-coreboot 4.19 release
-========================================================================
-
-The 4.19 release was completed on the 16th of January 2023.
-
-Since the last release, the coreboot project has merged over 1600
-commits from over 150 authors. Of those authors, around 25 were
-first-time committers to the coreboot project.
-
-As always, we are very grateful to all of the contributors for helping
-to keep the project going. The coreboot project is different from many
-open source projects in that we need to keep constantly updating the
-codebase to stay relevant with the latest processors and technologies.
-It takes constant effort to just stay afloat, let alone improve the
-codebase. Thank you very much to everyone who has contributed, both in
-this release and in previous times.
-
-The 4.20 release is planned for the 20th of April, 2023.
-
-
-Significant or interesting changes
-----------------------------------
-
-
-### Show all Kconfig options in saved config file; compress same
-
-The coreboot build system automatically adds a 'config' file to CBFS
-that lists the exact Kconfig configuration that the image was built
-with. This is useful to reproduce a build after the fact or to check
-whether support for a specific feature is enabled in the image.
-
-This file has been generated using the 'savedefconfig' Kconfig command,
-which generates the minimal .config file that is needed to produce the
-required config in a coreboot build. This is fine for reproduction, but
-bad when you want to check if a certain config was enabled, since many
-options get enabled by default or pulled in through another option's
-'select' statement and thus don't show up in the defconfig.
-
-Instead coreboot now includes a larger .config instead. In order to save
-some space, all of the comments disabling options are removed from the
-file, except for those included in the defconfig.
-
-We can also LZMA compress the file since it is never read by firmware
-itself and only intended for later re-extraction via cbfstool, which
-always has LZMA support included.
-
-
-### Toolchain updates
-
-* Upgrade LLVM from 15.0.0 to 15.0.6
-* Upgrade CMake from 3.24.2 to 3.25.0
-* Upgrade IASL from 20220331 to 20221020
-* Upgrade MPFR from 4.1.0 to 4.1.1
-
-
-### Finished the conversion to ASL 2.0 syntax
-
-Until recently, coreboot still contained lots of code using the legacy
-ASL syntax. However, all ASL code was ported over to make use of the ASL
-2.0 syntax and from this point on new ASL code should make use of it.
-
-
-Additional coreboot changes
----------------------------
-
-* Significant work was done to enable and build-test clang builds.
-* Added touchscreen power sequencing and runtime detection.
-* A number of patches were added to clean up and improve SMBIOS.
-* Work is in progress to unify and extend coreboot post codes.
-* Clean up for header includes is in progress with help from IWYU.
-* IOAPIC code has been reworked.
-* Support was added to superiotool for the NCT6687D-W chip.
-* Work is progressing to switch return values to enum cb_err instead of
-  bool or other pass/fail indicators.
-* Clang builds are now working for most boards and are being
-  build-tested.
-* 64-bit coreboot support is in progress and is working on a number of
-  platforms.
-* A driver for EC used on various Clevo laptops was added.
-* Native Intel Lynxpoint code was added to replace the MRC.bin.
-* Work continued for the process of adding ops structures to the
-  devicetree.
-* The crossgcc tool can now download the source packages, which are
-  needed to build the coreboot toolchain, from coreboot’s own mirror if
-  desired.
-* A document with useful external resources related to firmware
-  development was added at Documentation/external_docs.md.
-
-
-New Mainboards
---------------
-
-* AMD: Mayan for Phoenix SoC
-* GIGABYTE: GA-H61M-DS2
-* Google: Crystaldrift
-* Google: Gladios
-* Google: Dibbi
-* Google: Gaelin
-* Google: Marasov
-* Google: Markarth
-* Google: Omnigul
-* Google: Voltorb
-* Intel: Meteorlake-P RVP
-* MSI: PRO Z690-A (WIFI)
-* Siemens: MC_EHL3
-* Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
-* System76: darp8
-* System76: galp6
-
-
-Removed Mainboards
-------------------
-
-* AMD: Inagua
-* AMD: Olive Hill
-* AMD: Parmer
-* AMD: Persimmon
-* AMD: Southstation
-* AMD: Thatcher
-* AMD: Unionstation
-* ASROCK: E350M1
-* ASROCK: IMB-A180
-* ASUS: A88XM-E
-* ASUS: AM1I-A
-* ASUS: F2A85-M
-* ASUS: F2A85-M LE
-* ASUS: F2A85-M PRO
-* BAP: ODE_e20xx
-* Biostar: A68N-5200
-* Biostar: AM1ML
-* ELMEX: pcm205400
-* ELMEX: pcm205401
-* GizmoSphere: Gizmo
-* GizmoSphere: Gizmo2
-* Google: Morthal
-* HP: ABM
-* HP: Pavilion m6 1035dx
-* Jetway: NF81_T56N_LF
-* Lenovo: AMD G505s
-* LiPPERT: FrontRunner-AF aka ADLINK CoreModule2-GF
-* LiPPERT: Toucan-AF aka cExpress-GFR (+W83627DHG SIO)
-* MSI: MS-7721 (FM2-A75MA-E35)
-* PC Engines: APU1
-
-
-Updated SoCs
-------------
-
-* Added soc/amd/glinda
-* Renamed soc/amd/morgana to soc/amd/phoenix
-* Removed cpu/amd/agesa/family14
-* Removed cpu/amd/agesa/family15tn
-* Removed cpu/amd/agesa/family16kb
-
-
-Updated Chipsets
-----------------
-
-* Removed northbridge/amd/agesa/family14
-* Removed northbridge/amd/agesa/family15tn
-* Removed northbridge/amd/agesa/family16kb
-* Removed southbridge/amd/agesa/hudson
-* Removed southbridge/amd/cimx/sb800
-
-
-Payloads
---------
-
-* Updated GRUB from 2.04 to 2.06
-* Updated SeaBIOS 1.16.0 to 1.16.1
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained and the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of the
-code, it was never ready for production as only engineering sample
-CPUIDs are supported.
-
-Intel Icelake code will be removed following 4.19 and any maintenance
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed. Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.18 to the 4.19 release
---------------------------------------------
-
-- Total Commits: 1608
-- Average Commits per day: 17.39
-- Total lines added: 93786
-- Average lines added per commit: 58.32
-- Number of patches adding more than 100 lines: 80
-- Average lines added per small commit: 38.54
-- Total lines removed: 768014
-- Total difference between added and removed: -674228
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 445 | Thinkpad X200 wifi issue                                        |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```

Documentation/releases/coreboot-4.20-relnotes.md

@@ -1,226 +0,0 @@
-Upcoming release - coreboot 4.20
-========================================================================
-
-The 4.20 release is being done on May 15, 2023.
-
-The coreboot community has done a tremendous amount of work on the
-codebase over the last three and a half month. We've had over 1600
-commits in that time period, doing ongoing cleanup and improvement.
-
-It can be hard to remember at times how much the codebase really has
-improved, but looking back at coreboot code from previous years, it's
-really impressive the changes that have happened. We'd like to thank
-everyone who has been involved in these changes. It's great to work
-with everyone involved, from the people who make the small cleanup
-patches and review all of the incoming changes to the people working
-on new chipsets and SoCs. We'd additionally like to thank all of those
-individuals who make the effort to become involved and report issues
-or push even a single patch to fix a bug that they've noticed.
-
-Many thanks to everyone involved!
-
-We plan to get the 4.21 release done in mid August, 2023,
-
-Significant or interesting changes
-----------------------------------
-
-### cpu/mp_init.c: Only enable CPUs once they execute code
-
-On some systems the BSP cannot know how many CPUs are present in the
-system. A typical use case is a multi socket system. Setting the enable
-flag only on CPUs that actually exist makes it more flexible.
-
-### cpu/x86/smm: Add PCI resource store functionality
-
-In certain cases data within protected memmory areas like SMRAM could
-be leaked or modified if an attacker remaps PCI BARs to point within
-that area. Add support to the existing SMM runtime to allow storing
-PCI resources in SMRAM and then later retrieving them.
-
-This helps prevent moving BARs around to get SMM to access memory in
-areas that shouldn't be accessed.
-
-### acpi: Add SRAT x2APIC table support
-
-For platforms using X2APIC mode add SRAT x2APIC table
-generation. This allows to setup proper SRAT tables.
-
-### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
-
-This patch supports projects to use _DSM to control USB3 U1/U2
-transition per port.
-
-More details can be found in
-https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
-
-The ACPI and USB driver of linux kernel need corresponding functions
-to support this feature. Please see
-https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
-
-### drivers/efi: Add EFI variable store option support
-
-Add a driver to read and write EFI variables stored in a region device.
-This is particularly useful for EDK2 as payload and allows to reuse
-existing EFI tools to set/get options used by the firmware.
-
-The write implementation is fault tolerant and doesn't corrupt the
-variable store. A faulting write might result in using the old value
-even though a 'newer' had been completely written.
-
-Implemented basic unit tests for header corruption, writing existing
-data and append new data into the store.
-
-Initial firmware region state:
-Initially the variable store region isn't formatted. Usually this is
-done in the EDK2 payload when no valid firmware volume could be found.
-It might be useful to do this offline or in coreboot to have a working
-option store on the first boot or when it was corrupted.
-
-Performance improvements:
-Right now the code always checks if the firmware volume header is valid.
-This could be optimised by caching the test result in heap. For write
-operations it would be good to cache the end of the variable store in
-the heap as well, instead of walking the whole store. For read
-operations caching the entire store could be considered.
-
-Reclaiming memory:
-The EFI variable store is append write only. To update an existing
-variable, first a new is written to the end of the store and then the
-previous is marked invalid. This only works on PNOR flash that allow to
-clear set bits, but keep cleared bits state.
-This mechanisms allows a fault tolerant write, but it also requires to
-"clean" the variable store for time to time. This cleaning would remove
-variables that have been marked "deleted".
-Such cleaning mechanism in turn must be fault tolerant and thus must use
-a second partition in the SPI flash as backup/working region.
-For now to cleaning is done in coreboot.
-
-Fault checking:
-The driver should check if a previous write was successful and if not
-mark variables as deleted on the next operation.
-
-
-### drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
-
-Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
-and prints EWL type 3 primarily associated with MRC training failures.
-
-### Toolchain updates
-
-* Upgrade MPC from version 1.2.1 to 1.3.1
-* Upgrade MPFR from version 4.1.1 to 4.2.0
-* Upgrade CMake from version 3.25.0 to 3.26.3
-* Upgrade LLVM from version 15.0.6 to 15.0.7
-* Upgrade GCC from version 11.2.0 to 11.3.0
-* Upgrade binutils from version 2.37 to 2.40
-
-Additional coreboot changes
----------------------------
-
-* Remove Yabits payload. Yabits is deprecated and archived.
-* Add DDR2 support to Intel GM45 code.
-* Fix superiotool compilation issues when using musl-libc.
-* Drop the Python 2 package from the coreboot-sdk.
-* Drop the Zephyr SDK from coreboot-sdk since the packaged version
-  was quite old and wasn’t really used.
-* Add inteltool support for the Intel "Emmitsburg" PCH.
-* Work to improve cache hit percentage when rebuilding using ccache.
-* Adding Sound-Open-Firmware drivers to chromebooks to enable audio on
-  non-chrome operating systems.
-* Improve and expand ACPI generation code.
-* Fix some issues for the RISC-V code.
-* Continue upstreaming the POWER9 architecture.
-* Add documentation for SBOM (Software Bill of Materials).
-* Add SimNow console logging support for AMD.
-* Do initial work on Xeon SPR
-* CMOS defaults greater than 128 bytes long now extend to bank 1.
-
-New Mainboards
---------------
-* Asrock: B75M-ITX
-* Dell: Latitude E6400
-* Google: Aurash
-* Google: Boxy
-* Google: Constitution
-* Google: Gothrax
-* Google: Hades
-* Google: Myst
-* Google: Screebo
-* Google: Starmie
-* Google: Taranza
-* Google: Uldren
-* Google: Yavilla
-* HP: EliteBook 2170p
-* Intel: Archer City CRB
-* Intel: DQ67SW
-* Protectli: VP2420
-* Protectli: VP4630/VP4650
-* Protectli: VP4670
-* Siemens: MC EHL4
-* Siemens: MC EHL5
-* System76: lemp11
-* System76: oryp10
-* System76: oryp9
-
-Removed Mainboards
-------------------
-* Intel Icelake U DDR4/LPDDR4 RVP
-* Intel Icelake Y LPDDR4 RVP
-* Scaleway TAGADA
-
-Updated SoCs
-------------
-* Removed soc/intel/icelake
-
-Plans to move platform support to a branch
-------------------------------------------
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-have so far failed.  The only user of this SoC ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-Statistics from the 4.19 to the 4.20 release
---------------------------------------------
-
-Total Commits: ~1625
-Average Commits per day: ~13.71
-Total lines added: ~101911
-Average lines added per commit: ~62.71
-Number of patches adding more than 100 lines: ~126
-Average lines added per small commit: ~37.98
-Total lines removed: ~34756
-Average lines removed per commit: ~21.39
-Total difference between added and removed: ~67155
-Total authors: ~170
-New authors: ~35
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-| #   | Subject                                                         |
-|-----|-----------------------------------------------------------------|
-| 478 | X200 booting Linux takes a long time with TSC                   |
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-| 446 | Optiplex 9010 No Post                                           |
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-| 427 | x200: Two battery charging issues                               |
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-| 412 | x230 reboots on suspend                                         |
-| 393 | T500 restarts rather than waking up from suspend                |
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |

Documentation/releases/coreboot-4.21-relnotes.md

@@ -1,51 +0,0 @@
-Upcoming release - coreboot 4.21
-========================================================================
-
-The 4.21 release is planned for mid-August, 2023
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-Significant or interesting changes
-----------------------------------
-
-### Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-Platform Updates
-----------------
-
-* To be filled in immediately before the release by the release team
-
-Plans to move platform support to a branch
-------------------------------------------
-
-* Seciton to be filled in or removed after discussion
-
-Statistics from the 4.20 to the 4.21 release
---------------------------------------------
-
-* To be filled in immediately before the release by the release team
-
-
-Significant Known and Open Issues
----------------------------------
-
-* To be filled in immediately before the release by the release team
-

Documentation/releases/coreboot-4.6-relnotes.md

@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the edk2 UEFI implementation which
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the edk2 which has not been updated.
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the edk2
+the hope is that by the end of the summer, we finally support the EDK2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/
 

Documentation/releases/coreboot-4.7-relnotes.md

@@ -84,7 +84,7 @@ General changes
 
 * Integrate me_cleaner
 * Add flashconsole implementation
-* Build edk2 UEFI payload from upstream source
+* Build Tianocore UEFI payload from upstream source
 * Remove CMOS NVRAM configurable baud rates
 * A common mrc_cache driver to store romstage settings in SPI flash
 

Documentation/releases/coreboot-4.8.1-relnotes.md

@@ -71,7 +71,7 @@ detection
 Payloads
 --------
 * Bumped SeaBIOS to 1.11.1
-* Improved edk2 integration
+* Improved TianoCore integration
 
 Security
 --------

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.21 - August 2023](coreboot-4.21-relnotes.md)
+* [4.18 - Aug 2022](coreboot-4.18-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,11 +15,8 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.20 - May 2023](coreboot-4.20-relnotes.md)
-* [4.19 - January 2023](coreboot-4.19-relnotes.md)
-* [4.18 - October 2022](coreboot-4.18-relnotes.md)
 * [4.17 - May 2022](coreboot-4.17-relnotes.md)
-* [4.16 - February 2022](coreboot-4.16-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)

Documentation/sbom/sbom.md

@@ -1,156 +0,0 @@
-# Software Bill of Materials (SBOM)
-
-SBOM is a collection of information of each software component
-you are supplying/building. Similar to a package manager on Linux
-based systems, it holds information of as many software parts as
-possible. This information can be a version, name of the software, URL,
-license information and more. A SBOM can be saved in various formats.
-In coreboot it's saved as "uSWID" file. uSWID is not a standard or
-specification but it doesn't need to be, since it's basically just an
-array/list of CoSWID (Concise Software Identification) files which in
-turn are specified by a RFC specification. CoSWID files are saved in a
-CBOR format. CBOR is like JSON if JSON were a binary format. Similar
-to a package manager the CoSWID format can link multiple softwares
-together. For example on most modern Intel systems FSP is included as
-a dependency of coreboot. That kind of relationship between software
-components (among others) can be expressed in an uSWID file. That makes
-firmware/software much more transparent. One could for example create a
-software that takes a coreboot firmware image as input and
-automatically creates a graph with all software components the coreboot
-image contains and their relationship to each other.
-
-
-## SWID/CoSWID
-
-SWID is a standard hidden behind an ISO paywall.
-It generally identifies/describes Software components. Since SWID files
-are written in XML, they can get too large for devices with network and
-storage constraints. CoSWID is basically SWID but in CBOR binary
-format, which makes it far smaller compared to its big brother. Also,
-CoSWID is a RFC specification (so publicly accessible). Therefore
-CoSWID is the standard used in coreboot SBOM. But one CoSWID file/tag
-can only describe one single software, but since software is usually
-composed of multiple parts (especially in firmware with many binary
-blobs) uSWID was born as a container format to hold multiple CoSWID
-files. It also has a magic value, that makes software capable of
-extracting uSWID/CoSWID data without the need to understand the
-underlying format of the binary (in coreboot it's the CBFS and in EDK2
-it's the COFF). To get a simple overview of how a SWID/CoSWID file
-looks like, just take a look at the various "templates" in src/sbom/.
-There are of course other SBOM specifications out there, but most of
-them are rather blown up and don't support a binary format at all.
-
-
-## coreboot implementation
-
-Quick overview of how things are generated:
-
-![Generation of an SBOM File in coreboot][sbom_generation]
-
-[sbom_generation]: sbom_generation.svg
-
-After all SBOM data has been fetched from all the software components,
-the 'goswid' tool links them all together into one sbom.uswid file.
-Therefore the goswid tool is basically a linker that takes multiple
-CoSWID/SWID files and converts them into one uSWID file. Although the
-image shows only Files in JSON format it is also possible to supply
-them in XML or CBOR format.
-
-The final SBOM file is located inside the CBFS.
-For each software component in coreboot SBOM, there is an option in
-Kconfig (usually called `CONFIG_INCLUDE_[software-name]_SBOM`) to either
-include or not include SBOM metadata for the specified software.
-Furthermore there is a `CONFIG_SBOM_[software-name]_PATH` option which
-contains a path to a SWID/CoSWID file in a format of choice
-(being either JSON, XML or CBOR). `CONFIG_SBOM_[software-name]_PATH`
-option usually defaults to a very generic CoSWID file in JSON format
-(which are stored in src/sbom/). That at least gives minimal
-information like the name of the software and maybe a version.
-But it is always preferred, that the `CONFIG_SBOM_[software-name]_PATH`
-is set to a custom CoSWID/SWID file that contains much more information
-(like version/commit-hash, license, URL, dependencies, ...).
-Therefore using the defaults is by any means to be avoided, since they
-hold very little information or even worse wrong information.
-Furthermore some of these Kconfig options have a suboption
-(usually called `CONFIG_SBOM_[software-name]_GENERATE`) to generate
-some basic SBOM data for the specified software component, in order to
-get at least some bit of information about it by analyzing the binary
-(for binary blobs) or querying information via git (for open source
-projects). This is for example currently done for all payloads. For
-each payload the commit hash used in the build is taken and put into
-the SBOM file. For open-source projects (like all payloads) crucial
-information like the current commit-hash of the payload can easily be
-put into the SBOM file. Extracting information out of binary blobs is a
-bit trickier for obvious reasons. For closed source binary blobs it is
-therefore recommended that vendors and software-engineers create a SBOM
-file as part of their build process and add a path to that SBOM file
-via Kconfig options in coreboot (`CONFIG_SBOM_[software-name]_PATH`).
-That way the final SBOM has much more useful and correct data.
-
-
-## Build coreboot with SBOM
-
-Directly under the 'General setup' Kconfig menu is a
-'Software Bill of Materials (SBOM)' submenu where all options are to
-enable/disable SBOM integration in to the corebeoot build.
-Therefore one can just enable/disable them via `make menuconfig`.
-
-
-## What to do as Developer of a binary blob (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format
-as part of your software build process
-
-2. Supply that generated File along with your binary blob (preferably
-not inside the blob)
-
-3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your
-defconfig pointing to your [software-name] generated File.
-
-
-## What to do as Developer of an open source project (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID file in either JSON, XML or CBOR format
-as part of your software's build process. For example in form of a
-Makefile target.
-
-2. Change src/sbom/Makefile.inc (in order to know where to find the
-CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
-builds said software. For example for GRUB2 that could mean to add a
-Makefile target in payloads/external/GRUB2/Makefile.
-
-
-## Problems
-
-What to do if the binary blob that is included in coreboot's build
-already has a SBOM file embedded in the binary? One could supply the
-path of the software binary itself (e.g. me.bin) as SBOM file path for
-the software in question. Which would basically mean to set
-`CONFIG_SBOM_[software-name]_PATH=/path/to/me.bin`. This is possible
-since the 'goswid' tooling is able to extract uSWID information out of
-an unknown binary format because of uSWIDs magic value. But even if
-coreboot can extract the uSWID data there is still the question of what
-to do next. One can do one of the following:
-
-  - Do not include the Software's SBOM data in the final SBOM of
-    coreboot. Data would not be duplicated, but therefore not included
-    in coreboot SBOM file.
-
-  - Extract the uSWID/CoSWID information from the binary and also
-    include it in the coreboot SBOM. That would mean, that SBOM data
-    is duplicated.
-
-The first solution should in general be preferred, since its no
-problem if SBOM data is located at multiple locations/binaries if they
-don't have a direct dependency on each other. It would be good if
-software that cannot run on its own only supplies the SBOM data along
-with it as kind of extra file instead of embedded in an unknown binary
-blob. coreboot can then just take it and include it in its own SBOM
-file. If on the other hand the binary can function on its own (e.g. EC
-or BMC binary), it is generally preferred that the software supplies
-its own SBOM data and coreboot just simply doesn't include it in its
-own SBOM file. That would make a more or less clear distinction and
-avoids duplication in case the BMC or EC is updated (without updating
-coreboot). The distinction is not always easy and this problem is
-currently not considered in the implementation, since none of the
-software components currently create a SBOM file on their own.

Documentation/sbom/sbom_generation.plantuml

@@ -1,61 +0,0 @@
-@startuml
-
-map "src/sbom/compiler-gcc.json" as gcc {
-    software-name => GCC
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/intel-me.json" as me {
-    software-name => Intel Mangement Engine
-    ... => ...
-}
-map "src/sbom/intel-microcode.json" as ucode {
-    software-name => Intel Microcode
-    ... => ...
-}
-map "src/sbom/generic-ec.json" as ec {
-    software-name => ecxyz
-    ... => ...
-}
-map "src/sbom/generic-fsp.json" as fsp {
-    software-name => Firmware Support Package
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/payload-[...].json" as payload {
-    software-name => ...
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/coreboot.json" as coreboot {
-    software-name => coreboot
-    version => x.y.z
-    url => coreboot.rocks
-    ... => ...
-}
-object "sbom.uswid" as uswid {
-    merged SBOM data in binary format
-}
-object goswid {
-    # ./goswid
-        --compiler gcc.json
-        --parent coreboot.json
-        --requires fsp.json,payload.json
-        intel-me.json
-        intel-ec.json
-        intel-ucode.json
-        --output sbom.uswid
-}
-
-left to right direction
-gcc --> goswid
-me --> goswid
-ucode --> goswid
-goswid <-- ec
-goswid <-- fsp
-goswid <-- payload
-
-coreboot -up> goswid
-goswid -up> uswid
-
-@enduml