Save NVIDIA device subsystem ID before turning off the GPU, and restore
it after turning on the GPU. This prevents to GPU from having the
default 10de:0000 SSID on RTD3 _ON.
Fixes formatting and device scope.
Tested on gaze16-3050 by checking lspci after RTD3 _OFF.
$ cat /sys/bus/pci/devices/0000\:01\:00.0/power/runtime_status
suspended
$ lspci -s 01:00.0 -vnn | grep Subsystem
Subsystem: CLEVO/KAPOK Computer GA107M [GeForce RTX 3050 Mobile] [1558:5015]
Change-Id: Ic5a91f96a5741abb605906f404b1632eaec73590
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Windows will write to the century byte (0x32), causing the option table
checksum to be invalid and reset all options to their default values.
Move options and checksum to start after the century byte.
Add missing default for `boot_option`.
Add `debug_level`.
Reserve space for `power_on_after_fail`. It cannot be safely added
to existing boards because they do not boot with it set to `Disable`,
which is what coreboot will read with the new entry. A CMOS reset would
be required for coreboot to write `Enable` to the bits.
Change-Id: I2b61e6f5096e1109851c67a9206d0c4f586ad869
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.
Tested by checking lspci output on System76 darp7 (TGL-U).
References:
- b1fa231d76 ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001
Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
DisplayPort_Output conflicts with RTC_BOOT_BYTE. Move it to 392 and
adjust the checksum to start there as well.
Modify enum index for debug_level and boot_option to match other boards
across coreboot.
Change-Id: I4d1fe4fda22ef848950c518229321d3d2bc3db12
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Copy the VBT ROMs from firmware-open into coreboot. Removes the need to
specify `CONFIG_INTEL_GMA_VBT_FILE` in the config.
Change-Id: I578be0274028126203dd1d3edcd3da7d687e463f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
GPIOs for 15/17 models appear to be the same. It may be possible to use
a single variant like how it was done for gaze15.
Change-Id: Iae8ef8a733ed8c46151705d7ae240fbfa013662f
Set these values in Kconfig like other boards so they do not need to be
set in the config file passed to defconfig.
Change-Id: I70640824581c117e5237edf74a7cbab6705e5e68
Partially revert 37c69a0123 to restore USB-C and likely TBT
functionality on galp3-c.
Fixes: 37c69a0123 ("Update whl-u to match cml-u")
Change-Id: I6fc189b3185d51cd8e67ae2d1eedef65a6049a12
This reverts commit c1e0229094.
This change breaks the touchpad on oryp6. We will change these as-needed
if it proves to resolve issues, not just because Microsoft says so.
