Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE
corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration.
BUG=b:329026602
TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up
using EC generated events like AC connect/disconnect.
Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
After commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser),
embedded rST should use `{eval-rst}` instead of `eval_rst`. This was
missed during manual rebasing of that patch before it was merged.
Change-Id: I648a95488df25d70e1b581872a19272c51f33b7b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of using some aritmetics that sometimes works, use the largest
alignment necessary (page tables) and align downwards in the linker
script.
This fixes linking failing when linking in page tables inside the
bootblock.
This can result in a slight increase in bootblock size of at most 4096 -
512 bytes.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80346
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move it downwards allows for a larger bootblock, which comes in handy if
romstage or page tables are linked inside the bootblock.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80347
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to preprocess linker scripts the target architecture needs to
be specified. With clang this needs to be set via a cli argument.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
fsp_mrc_version() function does not need to perform a CBFS access to
to get an address to the FSP-M blob as the caller,
do_fsp_memory_init(), already has it loaded. In addition to make the
code simpler, it avoids an unnecessary decompression of the FSP blob
if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set.
TEST=Verified on Meteor Lake rex
Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81256
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This patch makes the GPL-restricted commonlib helpers available in
libpayload when CONFIG_LP_GPL is selected, as a convenience to GPL
payloads that use them a lot.
Cq-Depend: chromium:5375721
Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This is just a start. We are playing catch up.
7 down, 70+ to go.
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch adds timestamp start/end entries around the eSOL
implementation to track the panel initialization time while rendering
the eSOL screen.
TEST=Able to build and boot google/omnigul.
555: started early sign-off life (eSOL) notification 643,694 (40)
556: finished early sign-off life (eSOL) notification 1,072,143 (428,449)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch adds timestamp entries for eSOL (early Sign-Off Life).
This is critical to tracking the panel initialization time while
rendering the eSOL screen.
TEST=Able to build and boot google/omnigul.
555: started early sign-off life (eSOL) notification 643,694 (40)
556: finished early sign-off life (eSOL) notification 1,072,143 (428,449)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81386
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The memmap_early_dram struct is now only used inside the non-CAR
memmap.c, so move the struct definition there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Only the VGA MMIO range used the VGA_MMIO_* defines, but instead of
using constants for the end of the region before that and the beginning
of the region after that, the VGA_MMIO_* defines can be used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the code for reporting the memory map below cbmem_top is basically
identical for all non-CAR AMD SoCs, factor this out into a common
read_lower_soc_memmap_resources implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The latest Clevo boards connect the TAS5825M to one of the I2C
connections instead of the SMBus connection. The I2C ops are compatible
with SMBus, so always use them.
Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12
(uses I2C3). TAS5825M init is successful and speaker output works.
Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.
TEST=intel/archercity CRB
Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Since there's no code using those defines drop them.
TEST=intel/archercity CRB
Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81369
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
TEST=Identical binary test on all AMD SOC platform
Change-Id: Iece4ba65e0476543a8d472168d93801714330dde
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78281
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To bring genoa_poc more in line with the other AMD SoCs, move the
reporting of the memory map up to cbmem_top from the openSIL-specific
add_opensil_memmap function to read_soc_memmap_resources. This is a
preparation for making this code common for all newer AMD SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A trailing "|" at the end of the regex added a zero length alternative
match, causing all files to match and be filtered out. This was causing
`make lint-stable` to ignore all missing license headers, preventing the
pre-commit git hook and Jenkins from detecting these. Also, a missing
"|" separator between cmos.default and .apcb would cause those files to
be unintentionally scanned.
Change-Id: I70cc3a5adf7edee059883cd3cbe02029776b02ef
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Other files in the commits that added these files were licensed under
GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that
as the license.
Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the concerned chip.h file is included in a source file, it causes
compilation error saying unknown type name bool. Fix it by including the
stdbool.h file in the chip.h file.
BUG=None
TEST=Build Brox by including the chip.h file in one of the source files.
Change-Id: I4159e2c281c3e89dc45555ce38ad8637a3bf8587
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.
The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.
Add constants for this new CSR.
Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Print that the MPIO chip of one of the MPIO-related PCI device functions
is unused and is skipped, if the type is IFTYPE_UNUSED and the
corresponding PCI device function isn't enabled. This allows to
differentiate between this case and the case where the type isn't
IFTYPE_UNUSED.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When the chip of one of the MPIO-related PCI device functions has the
type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace
'engine' with 'chip' in the warning.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE
macro parameter when the device is enabled; otherwise report the port as
disabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Since we're already passing a pointer to the corresponding device to
per_device_config, we don't need to pass the chip_info as separate
parameter. Before moving the PCIe port function device below the MPIO
chip, the chip_info struct was from a different device, so that change
allows this simplification.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Move the gpp_bridge_* device functions that are bridges to the external
PCIe ports below the corresponding mpio chip. This avoids the need for
dummy devices and does things in a slightly more coreboot-native way.
TEST=PCIe lane config reported by openSIL is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Certain SSDs are not detected in the default time window, so
change this to 50ms to allow these SSDs to be detected.
Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CPU port is not used so disable it.
Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881.
This was originally assumed to be an FSP/Descriptor/PMC mismatch
but it turns out that the problem was coreboot incorrectly
detecting ASPM support on devices.
Revert so that a proper fix can be applied.
Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the size of the ME partition to match the descriptor
Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No variants were ever built with CNVi cards, so disable
this device.
Change-Id: I3725465eae0c7ade3dafa03add151353818ee761
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Different SoC generations might have different FSP header files. It is
recommended to put these uncommon header files in soc_util.h so that
Xeon-SP codes refer to soc_util.h to include them in a clean way.
TEST=intel/archercity CRB
Change-Id: Icfc20921efe00bc69b0c16c665f65f5baae4c309
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81229
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in TWL.
BUG=b:296433836
Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This fixes the warning when an integer is cast to a pointer of a
different size.
Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used with UDK_202111_BINDING Kconfig.
Compilation error:
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\'A\') does not meet UEFI
Specification Data Type requirements"
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\"A\") does not meet UEFI
Specification Data Type requirements"
BUG=b:296433836
TEST=Able to build google/crassk with UDK_202111_BINDING.
Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
