Commit Graph

39609 Commits

Author SHA1 Message Date
Tim Crawford
ef76014e23 soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.

A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").

The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.

TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.

Tested by checking lspci output on System76 darp7 (TGL-U).

References:
- b1fa231d76 ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001

Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-17 20:03:48 +00:00
Tim Crawford
5d09435cb4 mb/system76: Fix CMOS layouts
DisplayPort_Output conflicts with RTC_BOOT_BYTE. Move it to 392 and
adjust the checksum to start there as well.

Modify enum index for debug_level and boot_option to match other boards
across coreboot.

Change-Id: I4d1fe4fda22ef848950c518229321d3d2bc3db12
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-08-16 17:03:15 -06:00
Tim Crawford
181b9f3cdd mb/system76/*: Add VBT ROMs
Copy the VBT ROMs from firmware-open into coreboot. Removes the need to
specify `CONFIG_INTEL_GMA_VBT_FILE` in the config.

Change-Id: I578be0274028126203dd1d3edcd3da7d687e463f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-08-12 13:28:25 -06:00
Jeremy Soller
f1caea884c mainboard/system76: Use PME virtual wire for SWI on eSPI mainboards
Change-Id: I7b5dcddb326bfb94336e7d9f75df3f609abad30f
2021-07-20 16:11:03 -06:00
Jeremy Soller
a4f9ee038e mainboard/system76/gaze16: Add System76 Gazelle (gaze16)
Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c
Co-authored-by: Tim Crawford <tcrawford@system76.com>
2021-07-20 16:11:03 -06:00
Jeremy Soller
909f958c9e soc/intel/tigerlake: Add additional PEG interrupt routing
Change-Id: Ie164b6f933428b30c4723b054a8204eed33f3052
2021-07-20 16:11:03 -06:00
Jeremy Soller
e37a3ced0e soc/intel/tigerlake: Add PCH-H USB ACPI devices
Change-Id: Ia1c1c3d172366ddcc8c194cb2e0b0c2fb2acf678
2021-07-20 16:11:03 -06:00
Jeremy Soller
4bf74a81d5 soc/intel/tigerlake: Add PCH-H SPI_DMI_DESTINATION_ID
Change-Id: I9a316b91b31166831f23eaf9e271a7d67ac4ccff
2021-07-20 16:11:03 -06:00
Jeremy Soller
1447784b89 soc/intel/tigerlake: Set UserBd to recommended default for PCH-H
Change-Id: Ie8a28d8e03d7176df5409e6cb507a0a802ff026f
2021-07-20 16:11:03 -06:00
Jeremy Soller
726051be69 soc/intel/tigerlake: Set correct PCH-H PCR_PSF3_T0_SHDW_PMC_REG_BASE
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676
2021-07-20 16:11:03 -06:00
Jeremy Soller
51636f7e46 soc/intel/tigerlake: Add TGL-H PEG ports
Change-Id: I2d61532c9803972473a8cd45127d55b8cdeab06e
2021-07-20 16:11:03 -06:00
Jeremy Soller
1e605551e8 soc/intel/tigerlake: Add PCH-H PMC GPE group definitions
Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6
2021-07-20 16:11:03 -06:00
Jeremy Soller
cca90d8090 soc/intel/tigerlake: Add PCH-H root ports
Change-Id: I89e300adce2edeb9d9c2bba1782c212ee656a532
2021-07-20 16:11:03 -06:00
Jeremy Soller
14d84624eb soc/intel/tigerlake: Add PCH-H GPIO definitions
Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659
2021-07-20 16:11:03 -06:00
Jeremy Soller
933ddc8316 soc/intel/tigerlake: Add PCH-H chipset devicetree
Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7
2021-07-20 16:11:03 -06:00
Jeremy Soller
4daaff096c soc/intel/tigerlake: Add PCH-H Kconfig option
Change-Id: I7ac81d1b411e1f3b5c28acc701fa72c5d2c15026
2021-07-20 16:11:03 -06:00
Jeremy Soller
d2fc13e494 soc/intel/tigerlake: Add TGL-H power limits
Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
2021-07-20 16:11:03 -06:00
Jeremy Soller
e5fbcd5c8e soc/intel: Add TGL-H CPUID
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6
2021-07-20 16:11:03 -06:00
Jeremy Soller
805b903073 Add TGL-H PCI IDs
Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22
2021-07-20 16:11:03 -06:00
Tim Crawford
03f477d395 mb/system76/gaze14: Reduce from 4 to 2 variants
GPIOs for 15/17 models appear to be the same. It may be possible to use
a single variant like how it was done for gaze15.

Change-Id: Iae8ef8a733ed8c46151705d7ae240fbfa013662f
2021-05-10 14:52:09 -06:00
Tim Crawford
e67769d719 soc/intel/tgl: Add config to disable IME
Unlike CNL, default to false due to the S0ix issue.

Change-Id: I6da4f59759c25dc0247d2beaaa7d793d6f4e6795
2021-05-10 14:51:56 -06:00
Tim Crawford
9962529199 soc/intel/cnl: Add config to disable IME
Replace hard-coded define with a Kconfig option. Default to true to
preserve current beahvior.

Change-Id: I684470c831bcc03a4d4f78e22367a88dc2e3def6
2021-05-10 14:51:56 -06:00
Tim Crawford
cc18a3e941 mb/system76/kbl-u: Fix compiling
Restore the acpi/ directory, and fix dsdt.asl and devicetree.cb to build
after the merge.

Change-Id: I9b3f22db7b61e45523a0ecd022d4ba3eb117c329
2021-05-05 15:59:53 -06:00
Tim Crawford
292e37c4dc mb/system76: gpio: Make comments inline
Change-Id: I6f5008d19ebb9976310df80e6eb35b9600085b19
2021-05-05 15:59:53 -06:00
Tim Crawford
844b15fa94 mb/system76: Replace legacy PAD_CFG_NC with PAD_NC
Change-Id: I072201439f43721b02a397145488d622f27d55d6
2021-05-05 15:59:53 -06:00
Tim Crawford
df9b7145e0 mb/system76: Set SMBIOS name and mb version
Set these values in Kconfig like other boards so they do not need to be
set in the config file passed to defconfig.

Change-Id: I70640824581c117e5237edf74a7cbab6705e5e68
2021-05-05 15:59:53 -06:00
Tim Crawford
8db396fdc6 mb/system76: Drop removed config
SOC_INTEL_COMMON_ACPI_EC_PTS_WAK was removed in c7817bc128.

Change-Id: If873bf207505a5ccfdba7656eabdfba9171899a9
2021-05-05 15:59:53 -06:00
Tim Crawford
46719bd5b6 mb/system76: Switch to SPDX in all files
Change-Id: If9152d2b86e033b83acdbd63d006958557150817
2021-05-05 15:59:53 -06:00
Tim Crawford
ee224859e1 mb/system76/whl-u: Fix USB-C/TBT
Partially revert 37c69a0123 to restore USB-C and likely TBT
functionality on galp3-c.

Fixes: 37c69a0123 ("Update whl-u to match cml-u")
Change-Id: I6fc189b3185d51cd8e67ae2d1eedef65a6049a12
2021-04-20 10:37:54 -06:00
Tim Crawford
9ca667855e mb/system76: acpi: Remove unused define
The EC_COLOR_KEYBOARD define is not used by the EC ASL. A Kconfig
selection is used instead.

Change-Id: I83610f54f49285d16a34c1fe45aadcfefcbc84e4
2021-03-29 10:56:40 -06:00
Jeremy Soller
e2fbdbcf58 gaze15: Add ELAN touchpad settings
Change-Id: I279e05880177ad19a107dcf4d7071b1b1b9bb3a1
2021-03-19 11:10:51 -06:00
Jeremy Soller
285cdbd313 Fix TPM error message
Change-Id: Id5456c0d6abee6d79761fae0bed78cc6def351f3
2021-03-11 15:19:48 -07:00
Jeremy Soller
3bbeddab3d Fix lemp9 backlight ACPI issues
Change-Id: I59764f35f5057597031f89b367824fc8c3213280
2021-03-11 15:19:48 -07:00
Jeremy Soller
62f0b28987 oryp7: Do not allow memory overclocking due to increase in stability issues
Change-Id: I3c3bdfbc9008d80d1b18cc40e93280f0b5cb38f7
2021-03-03 15:09:46 -07:00
Jeremy Soller
54c1380774 Set oryp7 touchpad IRQ to edge triggered
Change-Id: Ib7e52e899f6d5b6b0fdfe1cbbce7d79b55ac357b
2021-02-26 14:53:29 -07:00
Tim Crawford
b8559b8b61 Revert "mb/system76: Configure HID IRQs as level triggered"
This reverts commit c1e0229094.

This change breaks the touchpad on oryp6. We will change these as-needed
if it proves to resolve issues, not just because Microsoft says so.
2021-02-26 14:51:42 -07:00
Jeremy Soller
0c2cc3e73e oryp7
Change-Id: Id5b960a8a8929063e0b0e56e079324c80f2b6638
2021-02-22 09:50:50 -07:00
Tim Crawford
6c748392f2 mb/system76/gaze15: Fix build
Change-Id: Idd6774b885c9f841b7595b88b2139daa906690aa
2021-02-10 13:59:49 -07:00
Tim Crawford
c1e0229094 mb/system76: Configure HID IRQs as level triggered
Per upstream [1], HID over I2C must be level triggered.

[1]: https://review.coreboot.org/c/coreboot/+/50452

Change-Id: Ie0eafe4b7a3b3472db8c5eae0bcb5116432a200b
2021-02-10 13:59:49 -07:00
Jeremy Soller
5a303e242e galp5: Set DGPU GPIO delays to prevent RTD3 crashes
Change-Id: I7deb8a22b767164357bc408f666603d65cedc439
2021-02-09 07:53:45 -07:00
Tim Crawford
e5cb4d2fc5 mb/system76: Use PAD_NC for unconnected pins
- Fix indentation level
- Document pins
- Use PAD_NC

Change-Id: Ieeec4a8e56725574225b815d4d05605733d18a24
2021-02-01 08:24:25 -07:00
Tim Crawford
eb025e0d6d mb/system76: Remove use of cnl_configure_pads()
Replace FSP hack with mainboard_ops .init() on CFL/CML.

Change-Id: If0949b4f7b748ddab35bcc0b7291ae6ac2f01cd8
2021-02-01 08:23:49 -07:00
Tim Crawford
4b98a9be54 mb/system76: Remove options selected by SOC
The SOCs already select these two options:

- HAVE_SMI_HANDLER
- SOC_INTEL_COMMON_BLOCK_HDA

Change-Id: Icb71516d72e592cc177ff40930acb9c0c185362f
2021-01-28 07:32:14 -07:00
Tim Crawford
67d15c2b28 mb/system76: Clean up dsdt.asl
- Use ACPI_DSDT_REV_2 instead of hard-coded value
- Update thelio-b1 to match other boards

Change-Id: I62bf9bfc4114c581bd0ec02d5a081d582a7aef32
2021-01-28 07:32:14 -07:00
Tim Crawford
f32ef3e031 mb/system76: acpi: Replace One with literal
Change-Id: I6ad551a228a43d6775b3290473e9c8951f9856b1
2021-01-28 07:32:14 -07:00
Tim Crawford
72bc5f2b46 mb/system76: Don't set SaGv for H series boards
Per the FSP integration guides, Geyserville only affects ULX/ULT CPUs.

Change-Id: I25edc19ae9d3ea949a214c04d8af11c2cc1f3082
2021-01-28 07:32:14 -07:00
Tim Crawford
8661b99e6c mb/system76: Update devicetrees based on upstream
Upstream is moving towards having registers set within their relevant
device. Do this now to reduce the diff for upstreaming and later syncing
changes back.

Does not touch the TGL boards or lemp9, which have most of the changes.

- Move registers to devices
- Remove unneeded registers
- Remove extra comments

Change-Id: I8cd54d428493981538722e9fe6a8f3ff2918a041
2021-01-26 09:17:21 -07:00
Tim Crawford
3b2ff0c148 mb/system76: Simplify romstage.c
- Remove the comments, which were copied from the header
- Remove the dq entries for LPDDR, which are not used
- Allow higher memory speeds on oryp5

Change-Id: Ied41e9aad832c19344f92845b0d8d4bdab7e1ac8
2021-01-26 09:16:28 -07:00
Jeremy Soller
edd97f35bd Correct darp7 PL2
Change-Id: I51f047b62a8a2eadcaf89a4c6e6041d5bb9d1331
2021-01-21 09:01:11 -07:00
Tim Crawford
53ff179883 src/drivers/smmstore: Fix SMMSTOREv1 clear command
The `clear` command for SMMSTORE version 1 does not require a parameter.

Change-Id: I992b7ce5962bf7ee62b7e1970ae7aa1b975ef42e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2021-01-19 13:36:59 -07:00