mb/system76/tgl-u: darp7: Re-add CPU PCIe RTD3

Change-Id: I2df115c323a4fa50ffac191461060df9059381f7 Signed-off-by: Tim Crawford <tcrawford@system76.com>
mb/system76/tgl-u: galp5: Re-add CPU PCIe RTD3
2023-01-19 09:15:55 -07:00 · 2023-01-19 09:15:44 -07:00 · 2023-01-19 09:15:33 -07:00 · 2023-01-19 09:13:54 -07:00 · 2023-01-17 07:54:54 -07:00 · 2023-01-17 07:54:54 -07:00
255 changed files with 10424 additions and 173 deletions
--- a/.gitmodules
+++ b/.gitmodules
@ -1,63 +1,63 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@ -202,16 +202,20 @@ The boards in this section are not real mainboards, but emulators.
 - [Bonobo Workstation 14](system76/bonw14.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
+- [Darter Pro 8](system76/darp8.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
+- [Lemur Pro 11](system76/lemp11.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
+- [Oryx Pro 9](system76/oryp9.md)

 ## Texas Instruments

--- a/Documentation/mainboard/system76/darp8.md
+++ b/Documentation/mainboard/system76/darp8.md
@ -0,0 +1,82 @@
+# Syste76 Darter Pro 8 (darp8)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1240P
+  - Intel Core i7-1260P
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 15.6" 1920x1080@60Hz LCD
+  - 1x HDMI
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (OZ711LV2)
+- USB
+  - 1x USB-C Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 2.0 Type-A
+- Dimensions
+  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | GigaDevice          |
+---------------------+---------------------+
+| Model               | GD25B256E           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Winbond             |
+---------------------+---------------------+
+| Model               | W25Q256.V           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U19) is above the left DIMM slot.
--- a/Documentation/mainboard/system76/gaze17.md
+++ b/Documentation/mainboard/system76/gaze17.md
@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | GigaDevice          |
+---------------------+---------------------+
+| Model               | GD25B256E           |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.
--- a/Documentation/mainboard/system76/lemp11.md
+++ b/Documentation/mainboard/system76/lemp11.md
@ -0,0 +1,62 @@
+# System76 Lemur Pro 11 (lemp11)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1235U
+  - Intel Core i7-1255U
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 14.0" 1920x1080@60Hz LCD
+  - 1x HDMI 2.1
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
+  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
+- Networking
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5 mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 3.2 (Gen 1) Type-A
+- Dimensions
+    - 1.65cm x 32.2cm x 21.68cm, 1.15kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Macronix            |
+---------------------+---------------------+
+| Model               | MX25L25673G         |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U41) is left of the DIMM slot.
--- a/Documentation/mainboard/system76/oryp9.md
+++ b/Documentation/mainboard/system76/oryp9.md
@ -0,0 +1,44 @@
+# System76 Oryx Pro 9 (oryp9)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+- Sound
+- Storage
+- USB
+- Dimensions
+  - 35.8cm x 24.0cm x 2.49cm, 2.4kg
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+---------------------+
+| Type                | Value               |
+=====================+=====================+
+| Socketed flash      | no                  |
+---------------------+---------------------+
+| Vendor              | Macronix            |
+---------------------+---------------------+
+| Model               | MX25L25673G         |
+---------------------+---------------------+
+| Size                | 32 MiB              |
+---------------------+---------------------+
+| Package             | WSON-8              |
+---------------------+---------------------+
+| Internal flashing   | yes                 |
+---------------------+---------------------+
+| External flashing   | yes                 |
+---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.
--- a/src/drivers/gfx/nvidia/Kconfig
+++ b/src/drivers/gfx/nvidia/Kconfig
@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
--- a/src/drivers/gfx/nvidia/Makefile.inc
+++ b/src/drivers/gfx/nvidia/Makefile.inc
@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c
--- a/src/drivers/gfx/nvidia/acpi/coffeelake.asl
+++ b/src/drivers/gfx/nvidia/acpi/coffeelake.asl
@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"
--- a/src/drivers/gfx/nvidia/acpi/common/dsm.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/dsm.asl
@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}
--- a/src/drivers/gfx/nvidia/acpi/common/gpu.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/gpu.asl
@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
--- a/src/drivers/gfx/nvidia/acpi/common/nvjt.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl
@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}
--- a/src/drivers/gfx/nvidia/acpi/common/power.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/power.asl
@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
--- a/src/drivers/gfx/nvidia/acpi/common/utility.asl
+++ b/src/drivers/gfx/nvidia/acpi/common/utility.asl
@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}
--- a/src/drivers/gfx/nvidia/acpi/tigerlake.asl
+++ b/src/drivers/gfx/nvidia/acpi/tigerlake.asl
@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"
--- a/src/drivers/gfx/nvidia/chip.h
+++ b/src/drivers/gfx/nvidia/chip.h
@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */
--- a/src/drivers/gfx/nvidia/gpu.h
+++ b/src/drivers/gfx/nvidia/gpu.h
@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */
--- a/src/drivers/gfx/nvidia/nvidia.c
+++ b/src/drivers/gfx/nvidia/nvidia.c
@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus Graphics Device")
+	.enable_dev = nvidia_enable
+};
--- a/src/drivers/gfx/nvidia/romstage.c
+++ b/src/drivers/gfx/nvidia/romstage.c
@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1
--- a/src/mainboard/system76/addw1/Kconfig
+++ b/src/mainboard/system76/addw1/Kconfig
@ -3,6 +3,7 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
--- a/src/mainboard/system76/addw1/Makefile.inc
+++ b/src/mainboard/system76/addw1/Makefile.inc
@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
--- a/src/mainboard/system76/addw1/acpi/mainboard.asl
+++ b/src/mainboard/system76/addw1/acpi/mainboard.asl
@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>

 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }

 Scope (\_GPE) {
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@ -58,6 +58,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device
--- a/src/mainboard/system76/addw1/ramstage.c
+++ b/src/mainboard/system76/addw1/ramstage.c
@ -2,6 +2,12 @@

 #include <device/device.h>
 #include <variant/gpio.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}

 static void mainboard_init(void *chip_info)
 {
--- a/src/mainboard/system76/addw1/romstage.c
+++ b/src/mainboard/system76/addw1/romstage.c
@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>

 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@ -20,8 +22,20 @@ static const struct cnl_mb_cfg memcfg = {

 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	// Allow higher memory speeds
-	memupd->FspmConfig.SaOcSupport = 1;
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Disable higher memory speeds
+	memupd->FspmConfig.SaOcSupport = 0;

 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }
--- a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
+++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c
@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865d1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
--- a/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h
+++ b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h
@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
--- a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb
+++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb
@ -12,7 +12,7 @@ chip soc/intel/cannonlake
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
-				register "generic.probed" = "1"
+				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
--- a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c
+++ b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c
@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x155865e1, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC
 	AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D)
 	AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A)
--- a/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h
+++ b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h
@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif
--- a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb
+++ b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb
@ -13,7 +13,7 @@ chip soc/intel/cannonlake
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A14_IRQ)"
-				register "generic.probed" = "1"
+				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
--- a/src/mainboard/system76/adl-p/Kconfig
+++ b/src/mainboard/system76/adl-p/Kconfig
@ -0,0 +1,86 @@
+if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+	select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_MEASURED_BOOT
+
+config MAINBOARD_DIR
+	default "system76/adl-p"
+
+config VARIANT_DIR
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Darter Pro" if BOARD_SYSTEM76_DARP8
+	default "Galago Pro" if BOARD_SYSTEM76_GALP6
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config MAINBOARD_VERSION
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 512
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif
--- a/src/mainboard/system76/adl-p/Kconfig.name
+++ b/src/mainboard/system76/adl-p/Kconfig.name
@ -0,0 +1,14 @@
+config BOARD_SYSTEM76_DARP8
+	bool "darp8"
+
+config BOARD_SYSTEM76_GALP6
+	bool "galp6"
+
+config BOARD_SYSTEM76_LEMP11
+	bool "lemp11"
+
+config BOARD_SYSTEM76_ORYP9
+	bool "oryp9"
+
+config BOARD_SYSTEM76_ORYP10
+	bool "oryp10"
--- a/src/mainboard/system76/adl-p/Makefile.inc
+++ b/src/mainboard/system76/adl-p/Makefile.inc
@ -0,0 +1,14 @@
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
+
+SPD_SOURCES = samsung-P4AAF165WA-BCWDE
--- a/src/mainboard/system76/adl-p/acpi/backlight.asl
+++ b/src/mainboard/system76/adl-p/acpi/backlight.asl
@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}
--- a/src/mainboard/system76/adl-p/acpi/mainboard.asl
+++ b/src/mainboard/system76/adl-p/acpi/mainboard.asl
@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
+	}
+}
--- a/src/mainboard/system76/adl-p/acpi/sleep.asl
+++ b/src/mainboard/system76/adl-p/acpi/sleep.asl
@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* HACK: Inform EC to apply PMC hack for S0ix issue */
+		\_SB.PCI0.LPCB.EC0.PTS (0)
+		/* S0ix Entry */
+		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}
--- a/src/mainboard/system76/adl-p/board_info.txt
+++ b/src/mainboard/system76/adl-p/board_info.txt
@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
--- a/src/mainboard/system76/adl-p/bootblock.c
+++ b/src/mainboard/system76/adl-p/bootblock.c
@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_early_gpios();
+}
--- a/src/mainboard/system76/adl-p/cmos.default
+++ b/src/mainboard/system76/adl-p/cmos.default
@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+me_state=Enable
--- a/src/mainboard/system76/adl-p/cmos.layout
+++ b/src/mainboard/system76/adl-p/cmos.layout
@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 983 984
--- a/src/mainboard/system76/adl-p/devicetree.cb
+++ b/src/mainboard/system76/adl-p/devicetree.cb
@ -0,0 +1,96 @@
+chip soc/intel/alderlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	register "s0ix_enable" = "1"
+
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+	# Thermal
+	register "tcc_offset" = "8"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP, DDIB is HDMI
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref tbt_pcie_rp0 on end
+		device ref shared_sram on end
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 on
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+
+		device ref heci1 on end
+		device ref sata on
+			register "sata_salp_support" = "1"
+			register "sata_ports_enable[1]" = "1" # SSD1
+			# FIXME: DevSlp breaks S0ix
+			#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0e01" # AP/EC command
+			register "gen3_dec" = "0x00fc0f01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref hda on
+			register "pch_hda_idisp_codec_enable" = "1"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end
--- a/src/mainboard/system76/adl-p/dsdt.asl
+++ b/src/mainboard/system76/adl-p/dsdt.asl
@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
--- a/src/mainboard/system76/adl-p/include/mainboard/gpio.h
+++ b/src/mainboard/system76/adl-p/include/mainboard/gpio.h
@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_early_gpios(void);
+void mainboard_configure_gpios(void);
+
+#endif
--- a/src/mainboard/system76/adl-p/ramstage.c
+++ b/src/mainboard/system76/adl-p/ramstage.c
@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
+	params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
+
+	params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
+	params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
+	params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
+	params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
+
+	params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
+	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
+
+	params->SataPortsSolidStateDrive[1] = 1;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	mainboard_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
--- a/src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex
+++ b/src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex
@ -0,0 +1,33 @@
+# Samsung P4AAF165WA-BCWDE
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
+F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 DE DE
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 50 34 41 41 46 31 36
+35 57 41 2D 42 43 57 44 45 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--- a/src/mainboard/system76/adl-p/variants/darp8/board_info.txt
+++ b/src/mainboard/system76/adl-p/variants/darp8/board_info.txt
@ -0,0 +1,2 @@
+Board name: darp8
+Release year: 2022
--- a/src/mainboard/system76/adl-p/variants/darp8/data.vbt
+++ b/src/mainboard/system76/adl-p/variants/darp8/data.vbt
--- a/src/mainboard/system76/adl-p/variants/darp8/gpio.c
+++ b/src/mainboard/system76/adl-p/variants/darp8/gpio.c
@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SATAGP0_PCIE_SSD2
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST), // GPIO_LANRTD3
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), // SATAGP1_SATA_SSD1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LID_SW#
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_NC(GPP_B2, NONE),
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	//PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+	//PAD_CFG_GPI(GPP_B10, NONE, DEEP),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
+	PAD_NC(GPP_B15, NONE),
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST), // M2_SSD1_RST#
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#_R
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	//PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+	//PAD_CFG_GPI(GPP_B20, NONE, DEEP),
+	//PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+	//PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_TP
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA_TP
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK_R
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA_R
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPO(GPP_D4, 1, DEEP), // GPIO_LAN_EN
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD2_CLKREQ#
+	PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap
+	PAD_CFG_GPI(GPP_D11, NATIVE, DEEP), // Board ID
+	PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
+	PAD_CFG_GPO(GPP_D15, 1, DEEP), // GPP_D2_SDCARD_RST#
+	PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPI(GPP_D19, NONE, DEEP), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // GPP_E10_STRAP
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // GPP_E11_STRAP
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_CFG_GPI(GPP_E16, NONE, DEEP), // SDCARD_WAKE#
+	PAD_NC(GPP_E17, NONE),
+	//PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
+	//PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
+	PAD_NC(GPP_F11, NONE), // BOARD_ID3
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP), // BOARD_ID1
+	PAD_NC(GPP_F15, NONE), // BOARD_ID2
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ6#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE),
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
+	PAD_NC(GPP_H13, NONE),
+	//PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	//PAD_CFG_GPI(GPP_H16, NONE, DEEP),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE), // DMIC_CLK
+	PAD_NC(GPP_R7, NONE), // DMIC_DAT
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/darp8/gpio_early.c
+++ b/src/mainboard/system76/adl-p/variants/darp8/gpio_early.c
@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/darp8/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/darp8/hda_verb.c
@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256,
+	0x15587716,
+	12,
+	AZALIA_SUBVENDOR(0, 0x15587716),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
@ -0,0 +1,177 @@
+chip soc/intel/alderlake
+	# HACK: Limit PL4 to PL2 to prevent power-off when system is booted on
+	# battery power. This seems to only happen with the i7 units.
+	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 56,
+		.tdp_pl4 = 56, // FIXME: Set to 65
+	}"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x7716 inherit
+
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
+				register "srcclk_pin" = "0" # SSD2_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Motherboard
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Multi Board
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen 2)
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunderbolt)
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Motherboard
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH2
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UJ_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH0""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST#_R
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp8 on
+			# PCIe RP#8 x1, Clock 6 (GLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x4, Clock 4 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
+				register "srcclk_pin" = "4" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC2
+						use usb2_port6 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
--- a/src/mainboard/system76/adl-p/variants/darp8/romstage.c
+++ b/src/mainboard/system76/adl-p/variants/darp8/romstage.c
@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+		.rcomp = { .resistor = 100, },
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
--- a/src/mainboard/system76/adl-p/variants/galp6/board_info.txt
+++ b/src/mainboard/system76/adl-p/variants/galp6/board_info.txt
@ -0,0 +1,2 @@
+Board name: galp6
+Release year: 2022
--- a/src/mainboard/system76/adl-p/variants/galp6/data.vbt
+++ b/src/mainboard/system76/adl-p/variants/galp6/data.vbt
--- a/src/mainboard/system76/adl-p/variants/galp6/gpio.c
+++ b/src/mainboard/system76/adl-p/variants/galp6/gpio.c
@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_GPI(GPP_A12, NONE, DEEP), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	// GPP_A14 (DGPU_PWR_EN) configured in bootblock
+	PAD_NC(GPP_A15, NONE), // USB_OC2#
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE), // I2C2_SDA (Pantone)
+	PAD_NC(GPP_B6, NONE), // I2C2_SCL (Pantone)
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	// GPP_D5 (SSD1_CLKREQ#) programmed by FSP
+	PAD_NC(GPP_D6, NONE),
+	// GPP_D7 (WLAN_CLKREQ#) programmed by FSP
+	// GPP_D8 (PEG_CLKREQ#) programmed by FSP
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), //  WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD1_PWR_EN#
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE), // DEVSLP1
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE), // strap
+	PAD_NC(GPP_E11, NONE), // strap
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+	//PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
+	//PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	// GPP_F5 (CNVI_CLKREQ) programmed by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#
+	PAD_CFG_GPI(GPP_F11, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_CFG_GPI(GPP_F14, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_F16, 1, DEEP), // GPU_EVENT#
+	PAD_NC(GPP_F17, NONE), // GPIO_CARD_PWR
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // dGPU_OVRM
+	// GPP_F19 (LAN_CLKREQ#) programmed by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE),
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // T_SDA (Touchpad)
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // T_SCL (Touchpad)
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (TBT)
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (TBT)
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART2_RXD) configured in bootblock
+	// GPP_H11 (UART2_TXD) configured in bootblock
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	// GPP_H14 missing
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	// GPP_H16 missing
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	// GPP_H23 (CARD_CLKREQ#) programmed by FSP
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+	PAD_NC(GPP_R5, NONE),
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPC_DMIC_CLK
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPC_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c
+++ b/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c
@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART2_RXD (actually UART0)
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART2_TXD (actually UART0)
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c
@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15584041, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15584041),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
@ -0,0 +1,187 @@
+chip soc/intel/alderlake
+	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+		.tdp_pl1_override = 28,
+		.tdp_pl2_override = 60,
+		.tdp_pl4 = 90,
+	}"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x4041 inherit
+
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD1)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST#
+				register "srcclk_pin" = "0" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB3_2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB3_2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref sata off end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp10 on
+			# PCIe RP#10 x1, Clock 6 (GLAN)
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
+				register "srcclk_pin" = "6" # LAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC2
+						use usb2_port6 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
--- a/src/mainboard/system76/adl-p/variants/galp6/romstage.c
+++ b/src/mainboard/system76/adl-p/variants/galp6/romstage.c
@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
--- a/src/mainboard/system76/adl-p/variants/lemp11/board_info.txt
+++ b/src/mainboard/system76/adl-p/variants/lemp11/board_info.txt
@ -0,0 +1,2 @@
+Board name: lemp11
+Release year: 2022
--- a/src/mainboard/system76/adl-p/variants/lemp11/data.vbt
+++ b/src/mainboard/system76/adl-p/variants/lemp11/data.vbt
--- a/src/mainboard/system76/adl-p/variants/lemp11/gpio.c
+++ b/src/mainboard/system76/adl-p/variants/lemp11/gpio.c
@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT#
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE,  DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	//PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
+	//PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST#
+	PAD_NC(GPP_H1, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
+	PAD_NC(GPP_H13, NONE),
+	//PAD_NC(GPP_H14, NONE),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	//PAD_NC(GPP_H16, NONE),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE), // DMIC_CLK
+	PAD_NC(GPP_R7, NONE), // DMIC_DAT
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c
+++ b/src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c
@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256,
+	0x15587718,
+	12,
+	AZALIA_SUBVENDOR(0, 0x15587718),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
@ -0,0 +1,161 @@
+chip soc/intel/alderlake
+	register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 46,
+		.tdp_pl4 = 65,
+	}"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x7718 inherit
+
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
+				register "srcclk_pin" = "0" # SSD0_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 3G/LTE""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST#
+				register "srcclk_pin" = "1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC1
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
--- a/src/mainboard/system76/adl-p/variants/lemp11/romstage.c
+++ b/src/mainboard/system76/adl-p/variants/lemp11/romstage.c
@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+		.rcomp = { .resistor = 100, },
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MIXED,
+		.cbfs_index = 0,
+		.smbus[1] = { .addr_dimm[0] = 0x52, },
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
--- a/src/mainboard/system76/adl-p/variants/oryp10/board_info.txt
+++ b/src/mainboard/system76/adl-p/variants/oryp10/board_info.txt
@ -0,0 +1,2 @@
+Board name: oryp10
+Release year: 2022
--- a/src/mainboard/system76/adl-p/variants/oryp10/data.vbt
+++ b/src/mainboard/system76/adl-p/variants/oryp10/data.vbt
--- a/src/mainboard/system76/adl-p/variants/oryp10/gpio.c
+++ b/src/mainboard/system76/adl-p/variants/oryp10/gpio.c
@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
+	PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // Top swap override
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+	//PAD_NC(GPP_E18, NATIVE), // TBTA_LSX2_TXD
+	//PAD_NC(GPP_E19, NATIVE), // TBTA_LSX2_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // Strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
+	PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	//PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	//PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), // GLAN_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/oryp10/gpio_early.c
+++ b/src/mainboard/system76/adl-p/variants/oryp10/gpio_early.c
@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/oryp10/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/oryp10/hda_verb.c
@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155867f5, /* Subsystem ID */
+	152, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155867f5),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+
+	// Enable DMIC microphone on ALC1220
+	0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
+
+	// ALC1306 smart amp
+	0x02050027, 0x02040010, 0x02050029, 0x02040000,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003f,
+	0x0205002b, 0x02041000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040004,
+	0x0205002b, 0x02040600, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204c0c0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204ffd0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003a,
+	0x0205002b, 0x02040dfe, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040442, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040005,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040006,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040008,
+	0x0205002b, 0x0204b000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204002e,
+	0x0205002b, 0x02040800, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400c3, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204d4a0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400cc, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204400a, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x020400c1, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040320, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040039,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003b,
+	0x0205002b, 0x0204ffff, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x0204005d, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02049142, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x020400c0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fcf0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040080, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040880, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fce0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fca0, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003c,
+	0x0205002b, 0x0204fc20, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040080,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040062,
+	0x0205002b, 0x02048000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040063,
+	0x0205002b, 0x02045f5f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040064,
+	0x0205002b, 0x02042000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040065,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040066,
+	0x0205002b, 0x02044004, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040067,
+	0x0205002b, 0x02040802, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040068,
+	0x0205002b, 0x0204890f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040069,
+	0x0205002b, 0x0204e021, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040070,
+	0x0205002b, 0x02048012, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040071,
+	0x0205002b, 0x02043450, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040072,
+	0x0205002b, 0x02040123, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040073,
+	0x0205002b, 0x02044543, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040074,
+	0x0205002b, 0x02042100, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040075,
+	0x0205002b, 0x02044321, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040076,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040046,
+	0x0205002b, 0x0204c22e, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040050,
+	0x0205002b, 0x02048200, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040051,
+	0x0205002b, 0x02040707, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040052,
+	0x0205002b, 0x02044090, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040090, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x0204721f, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040012,
+	0x0205002b, 0x0204dfdf, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204009e,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040004,
+	0x0205002b, 0x02040500, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006a,
+	0x0205002b, 0x02040006, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204006c,
+	0x0205002b, 0x02040000, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x02040060,
+	0x0205002b, 0x02042213, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003a,
+	0x0205002b, 0x02041dfe, 0x0205002c, 0x0204b424,
+	0x02050027, 0x02040010, 0x02050029, 0x0204003f,
+	0x0205002b, 0x02043000, 0x0205002c, 0x0204b424,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/system76/adl-p/variants/oryp10/include/variant/gpio.h
+++ b/src/mainboard/system76/adl-p/variants/oryp10/include/variant/gpio.h
@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif
--- a/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb
@ -0,0 +1,205 @@
+chip soc/intel/alderlake
+	# HACK: Limit PL4 to prevent power off on battery power.
+	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 115,
+		.tdp_psyspl2 = 135,
+		.tdp_pl4 = 72,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x65f5 inherit
+
+		device ref pcie5 on
+			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
+		end
+		device ref igpu on
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+		end
+		device ref pcie4_0 on
+			# CPU PCIe RP#1 x4, Clock 0 (SSD1)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie4_1 on
+			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(3)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Per-KB""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref sata off end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to 3.3VS?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe RP#8 x1, Clock 5 (GLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# TYPEC2
+						use usb2_port9 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
--- a/src/mainboard/system76/adl-p/variants/oryp10/romstage.c
+++ b/src/mainboard/system76/adl-p/variants/oryp10/romstage.c
@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.rcomp = { .resistor = 100, },
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
--- a/src/mainboard/system76/adl-p/variants/oryp9/board_info.txt
+++ b/src/mainboard/system76/adl-p/variants/oryp9/board_info.txt
@ -0,0 +1,2 @@
+Board name: oryp9
+Release year: 2022
--- a/src/mainboard/system76/adl-p/variants/oryp9/data.vbt
+++ b/src/mainboard/system76/adl-p/variants/oryp9/data.vbt
--- a/src/mainboard/system76/adl-p/variants/oryp9/gpio.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/gpio.c
@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_NC(GPD7, NONE),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
+	PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
+	PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_NC(GPP_B14, NONE), // Top swap override
+	PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
+	//PAD_NC(GPP_E18, NATIVE), // TBTA_LSX2_TXD
+	//PAD_NC(GPP_E19, NATIVE), // TBTA_LSX2_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE), // Strap
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
+	PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	//PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	//PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), // GLAN_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
+	PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
+	PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/oryp9/gpio_early.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/gpio_early.c
@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
--- a/src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155867f5, /* Subsystem ID */
+	13, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155867f5),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+	// Enable DMIC microphone on ALC1220
+	0x02050036,
+	0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/system76/adl-p/variants/oryp9/include/variant/gpio.h
+++ b/src/mainboard/system76/adl-p/variants/oryp9/include/variant/gpio.h
@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif
--- a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
@ -0,0 +1,211 @@
+chip soc/intel/alderlake
+	# HACK: Limit PL4 to prevent power off on battery power.
+	register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 115,
+		.tdp_psyspl2 = 135,
+		.tdp_pl4 = 72,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x65f5 inherit
+
+		device ref pcie5 on
+			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
+		end
+		device ref igpu on
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+		end
+		device ref pcie4_0 on
+			# CPU PCIe RP#1 x4, Clock 0 (SSD1)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie4_1 on
+			# CPU PCIe RP#3 x4, Clock 4 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(3)]" = "{
+				.clk_src = 4,
+				.clk_req = 4,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Per-KB""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port8 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port9 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB2""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref sata off end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to 3.3VS?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe RP#8 x1, Clock 5 (GLAN)
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# TYPEC2
+						use usb2_port9 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref smbus on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+		end
+	end
+end
--- a/src/mainboard/system76/adl-p/variants/oryp9/romstage.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/romstage.c
@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+		.rcomp = { .resistor = 100, },
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
--- a/src/mainboard/system76/adl-p/variants/oryp9/tas5825m.c
+++ b/src/mainboard/system76/adl-p/variants/oryp9/tas5825m.c
--- a/src/mainboard/system76/bonw14/Kconfig
+++ b/src/mainboard/system76/bonw14/Kconfig
@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
--- a/src/mainboard/system76/bonw14/Makefile.inc
+++ b/src/mainboard/system76/bonw14/Makefile.inc
@ -8,3 +8,4 @@ romstage-y += romstage.c
 ramstage-y += ramstage.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@ -106,7 +106,7 @@ chip soc/intel/cannonlake
 				register "generic.hid" = ""SYNA1202""
 				register "generic.desc" = ""Synaptics Touchpad""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
-				register "generic.probed" = "1"
+				register "generic.detect" = "1"
 				register "hid_desc_reg_offset" = "0x20"
 				device i2c 2c on end
 			end
@ -217,7 +217,16 @@ chip soc/intel/cannonlake
 		device pci 1f.3 on      # Intel HDA
 			register "PchHdaAudioLinkHda" = "1"
 		end
-		device pci 1f.4 on  end # SMBus
+		device pci 1f.4 on      # SMBus
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end
+			chip drivers/i2c/tas5825m
+				register "id" = "1"
+				device i2c 4f on end # (8bit address: 0x9e)
+			end
+		end
 		device pci 1f.5 on  end # PCH SPI
 		device pci 1f.6 off end # GbE
 	end
--- a/src/mainboard/system76/bonw14/hda_verb.c
+++ b/src/mainboard/system76/bonw14/hda_verb.c
@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek, ALC1220 */
 	0x10ec1220, /* Vendor ID */
 	0x15587714, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
 	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
--- a/src/mainboard/system76/bonw14/ramstage.c
+++ b/src/mainboard/system76/bonw14/ramstage.c
@ -2,6 +2,12 @@

 #include <device/device.h>
 #include <mainboard/gpio.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}

 static void mainboard_init(void *chip_info)
 {
--- a/src/mainboard/system76/bonw14/tas5825m-normal.c
+++ b/src/mainboard/system76/bonw14/tas5825m-normal.c
--- a/src/mainboard/system76/bonw14/tas5825m-sub.c
+++ b/src/mainboard/system76/bonw14/tas5825m-sub.c
--- a/src/mainboard/system76/bonw14/tas5825m.c
+++ b/src/mainboard/system76/bonw14/tas5825m.c
@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+#include "tas5825m-normal.c"
+#include "tas5825m-sub.c"
+
+int tas5825m_setup(struct device *dev, int id)
+{
+	if (id == 0)
+		return tas5825m_setup_normal(dev);
+	if (id == 1)
+		return tas5825m_setup_sub(dev);
+	return -1;
+}
--- a/src/mainboard/system76/cml-u/Kconfig
+++ b/src/mainboard/system76/cml-u/Kconfig
@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_MEASURED_BOOT
+	select TPM_RDRESP_NEED_DELAY

 config MAINBOARD_DIR
 	default "system76/cml-u"
--- a/src/mainboard/system76/cml-u/acpi/backlight.asl
+++ b/src/mainboard/system76/cml-u/acpi/backlight.asl
@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}
--- a/src/mainboard/system76/cml-u/acpi/mainboard.asl
+++ b/src/mainboard/system76/cml-u/acpi/mainboard.asl
@ -6,6 +6,9 @@

 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

 Scope (\_GPE) {
--- a/src/mainboard/system76/cml-u/dsdt.asl
+++ b/src/mainboard/system76/cml-u/dsdt.asl
@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}

 	#include <southbridge/intel/common/acpi/sleepstates.asl>
--- a/src/mainboard/system76/cml-u/ramstage.c
+++ b/src/mainboard/system76/cml-u/ramstage.c
@ -2,6 +2,12 @@

 #include <device/device.h>
 #include <mainboard/gpio.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}

 static void mainboard_init(void *chip_info)
 {
--- a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c
+++ b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c
@ -6,8 +6,9 @@ const u32 cim_verb_data[] = {
 	/* Realtek ALC293 */
 	0x10ec0293, /* Vendor ID */
 	0x15581404, /* Subsystem ID */
-	12, /* Number of entries */
+	13, /* Number of entries */
 	AZALIA_SUBVENDOR(0, 0x15581404),
+	AZALIA_RESET(1),
 	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
 	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
 	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
--- a/Show More
+++ b/Show More