mb/system76/gaze17: 3060: Fix RTD3 configs

The gaze17, like the oryp9, ties all resets for RTD3 to BUF_PLT_RST#
instead of using dedicated lines and ties the enable GPIO to 3.3VS.

Disable RTD3 config for the CPU PCIe RP and disable L23 for the PCH SSD
slot to fix suspend with Western Digital drives.

Change-Id: Iab3796d98ce74e09e74abb48b437e74a60c7b6b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.gitignore

@@ -40,3 +40,5 @@ tarballs/
 *~
 *.kate-swp
 *.kdev4
+
+doxygen/*

.gitmodules

@@ -1,63 +1,63 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

Documentation/distributions.md

@@ -8,15 +8,6 @@ and those providing after-market firmware to extend the usefulness of devices.
 
 ## Hardware shipping with coreboot
 
-### NovaCustom laptops
-
-[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
-[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
-[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
-Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
-and the firmware is equipped with important security features such as measured
-boot, verified boot, TPM integration and UEFI Secure Boot.
-
 ### ChromeOS Devices
 
 All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
@@ -63,15 +54,6 @@ provides ready-made firmware images for supported devices: those which can be
 built entirely from source code. Their copy of the coreboot repository is
 therefore stripped of all devices that require binary components to boot.
 
-
-### Dasharo
-
-[Dasharo](https://dasharo.com/) is an open-source based firmware distribution
-focusing on clean and simple code, long-term maintenance, transparent
-validation, privacy-respecting implementation, liberty for the owners, and
-trustworthiness for all.
-
-
 ### MrChromebox
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware

Documentation/doxygen/Doxyfile.coreboot_platform

@@ -0,0 +1,319 @@
+# Doxyfile 1.8.11
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING      = UTF-8
+PROJECT_NAME           = "coreboot for $(DOXYGEN_PLATFORM)"
+PROJECT_NUMBER         =
+PROJECT_BRIEF          = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO           = Documentation/coreboot_logo.png
+OUTPUT_DIRECTORY       = $(DOXYGEN_OUTPUT_DIR)
+CREATE_SUBDIRS         = YES
+ALLOW_UNICODE_NAMES    = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       =
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+TCL_SUBST              =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
+AUTOLINK_SUPPORT       = YES
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+GROUP_NESTED_COMPOUNDS = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
+EXTRACT_PACKAGE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+HIDE_COMPOUND_REFERENCE= NO
+SHOW_INCLUDE_FILES     = YES
+SHOW_GROUPED_MEMB_INC  = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = YES
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            =
+CITE_BIB_FILES         =
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_AS_ERROR          = NO
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = $(DOXYFILES)
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          =
+RECURSIVE              = NO
+EXCLUDE                =
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       =
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+USE_MDFILE_AS_MAINPAGE =
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+SOURCE_TOOLTIPS        = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+CLANG_ASSISTED_PARSING = NO
+CLANG_OPTIONS          =
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_STYLESHEET  =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
+HTML_COLORSTYLE_GAMMA  = 80
+HTML_TIMESTAMP         = NO
+HTML_DYNAMIC_SECTIONS  = NO
+HTML_INDEX_NUM_ENTRIES = 100
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen documentation"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = NO
+CHM_FILE               =
+HHC_LOCATION           =
+GENERATE_CHI           = NO
+CHM_INDEX_ENCODING     =
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+GENERATE_QHP           = NO
+QCH_FILE               =
+QHP_NAMESPACE          = org.doxygen.Project
+QHP_VIRTUAL_FOLDER     = doc
+QHP_CUST_FILTER_NAME   =
+QHP_CUST_FILTER_ATTRS  =
+QHP_SECT_FILTER_ATTRS  =
+QHG_LOCATION           =
+GENERATE_ECLIPSEHELP   = NO
+ECLIPSE_DOC_ID         = org.doxygen.Project
+DISABLE_INDEX          = NO
+GENERATE_TREEVIEW      = YES
+ENUM_VALUES_PER_LINE   = 4
+TREEVIEW_WIDTH         = 250
+EXT_LINKS_IN_WINDOW    = NO
+FORMULA_FONTSIZE       = 10
+FORMULA_TRANSPARENT    = YES
+USE_MATHJAX            = NO
+MATHJAX_FORMAT         = HTML-CSS
+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_EXTENSIONS     =
+MATHJAX_CODEFILE       =
+SEARCHENGINE           = YES
+SERVER_BASED_SEARCH    = NO
+EXTERNAL_SEARCH        = NO
+SEARCHENGINE_URL       =
+SEARCHDATA_FILE        = searchdata.xml
+EXTERNAL_SEARCH_ID     =
+EXTRA_SEARCH_MAPPINGS  =
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+LATEX_FOOTER           =
+LATEX_EXTRA_STYLESHEET =
+LATEX_EXTRA_FILES      =
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+LATEX_SOURCE_CODE      = NO
+LATEX_BIB_STYLE        = plain
+LATEX_TIMESTAMP        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+RTF_SOURCE_CODE        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_SUBDIR             =
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+GENERATE_DOCBOOK       = NO
+DOCBOOK_OUTPUT         = docbook
+DOCBOOK_PROGRAMLISTING = NO
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = YES
+EXPAND_ONLY_PREDEF     = YES
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             = __attribute__(x)=
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+EXTERNAL_PAGES         = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+DIA_PATH               =
+HIDE_UNDOC_RELATIONS   = NO
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = YES
+UML_LIMIT_NUM_FIELDS   = 10
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+PLANTUML_INCLUDE_PATH  =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES

Documentation/getting_started/architecture.md

@@ -3,7 +3,7 @@
 ## Overview
 ![][architecture]
 
-[architecture]: comparison_coreboot_uefi.svg
+[architecture]: comparision_coreboot_uefi.svg
 
 ## Stages
 coreboot consists of multiple stages that are compiled as separate binaries and

Documentation/ifdtool/layout.md

@@ -2,7 +2,7 @@
 
 A coreboot image for an Intel SoC contains two separate definitions of the
 layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and
-sizes of various regions of flash and the [coreboot FMAP](../../lib/flashmap.md).
+sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md).
 
 The FMAP should define all of the of the regions defined by the IFD to ensure
 that those regions are accounted for by coreboot and will not be accidentally

Documentation/index.md

@@ -189,6 +189,5 @@ Contents:
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
 * [Project infrastructure & services](infrastructure/index.md)
-* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Documentation License](documentation_license.md)

Documentation/infrastructure/builders.md

@@ -49,7 +49,7 @@ These times are taken from the week of Feb 21 - Feb 28, 2022
   *  Fastest Passing coreboot gerrit build: 6 min, 47 sec
   *  Slowest Passing coreboot gerrit build: 14 min
 
-* Gleefulbuilder - 64 threads, 64GiB RAM
+* Gleefulbuilder - 64 thread, 64GiB RAM
   *  Fastest Passing coreboot gerrit build: 10 min
   *  Slowest Passing coreboot gerrit build: 46 min
 
@@ -91,8 +91,8 @@ hour.
 
 On a system with 32 cores, it was tested with this command:
 
-```sh
-stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
+```
+$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
 ```
 
 You can watch the temperature with the sensors package or with ‘acpi -t’
@@ -102,8 +102,8 @@ You can check for thermal throttling by running this command and seeing
 if the values go down on any of the cores after it's been running for a
 while.
 
-```sh
-while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
+```
+$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
 ```
 
 If the machine throttles or resets, you probably need to upgrade the
@@ -142,7 +142,7 @@ These instructions keep changing, so just check the latest information.
 
 As a regular user - *Not root*, run:
 
-```sh
+```
 sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
 sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
 sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
@@ -158,7 +158,7 @@ To make configuration and the later commands easier, these should go in
 your shell's .rc file.  Note that you only need to set them if you're
 using something other than the default.
 
-```sh
+```
 # Set the port used on your machine to connect to jenkins.
 export COREBOOT_JENKINS_PORT=49151
 
@@ -180,13 +180,13 @@ continuing to the next step.
 
 From the coreboot directory, run
 
-```sh
+```
 make -C util/docker help
 ```
 
 This will show you the available targets and variables needed:
 
-```text
+```
 Commands for working with docker images:
   coreboot-sdk                 - Build coreboot-sdk container
   upload-coreboot-sdk          - Upload coreboot-sdk to hub.docker.com
@@ -221,7 +221,7 @@ Variables:
 
 ### Install the coreboot jenkins builder
 
-```sh
+```
 make -C util/docker docker-jenkins-server
 ```
 
@@ -252,12 +252,11 @@ the ccache gets populated, the build time will drop.
 
 
 ### How to log in to the docker instance for debugging
-
-```sh
-make -C util/docker docker-jenkins-attach
-su coreboot
-cd ~/slave-root/workspace
-bash
+```
+    $ make -C util/docker docker-jenkins-attach
+    $ su coreboot
+    $ cd ~/slave-root/workspace
+    $ bash
 ```
 
 
@@ -274,18 +273,18 @@ then update to get a fresh installation.
 
 To delete the old containers & images:
 
-```sh
-docker stop $COREBOOT_JENKINS_CONTAINER
-docker rm $COREBOOT_JENKINS_CONTAINER
-docker images # lists all existing images
-docker rmi XXXX # Use the image ID found in the above command.
+```
+$ docker stop $COREBOOT_JENKINS_CONTAINER
+$ docker rm $COREBOOT_JENKINS_CONTAINER
+$ docker images # lists all existing images
+$ docker rmi XXXX # Use the image ID found in the above command.
 ```
 
 To get and run the new coreboot-jenkins image, change the value in the
 `DOCKER_COMMIT` variable to the new image value.
 
-```sh
-make -C util/docker docker-jenkins-server
+```
+$ make -C util/docker docker-jenkins-server
 ```
 
 #### Getting ready to push the docker images
@@ -299,15 +298,15 @@ Get an admin to add the account to the coreboot team on hub.docker.com
 Make sure your credentials are configured on your host machine by
 running
 
-```sh
-docker login
+```
+$ docker login
 ```
 
 This will prompt you for your docker username, password, and your email
 address, and write out to ~/.docker/config.json.  Without this file, you
 won’t be able to push the images.
 
-#### Updating the Dockerfiles
+#### Updating the Dockerfiles:
 
 The coreboot-sdk Dockerfile will need to be updated when any additional
 dependencies are added.  Both the coreboot-sdk and the
@@ -318,15 +317,15 @@ files are stored in the coreboot repo under coreboot/util/docker.
 Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/)
 page before updating the files.
 
-#### Rebuilding the coreboot-sdk docker image to update the toolchain
+#### Rebuilding the coreboot-sdk docker image to update the toolchain:
 
-```sh
-make -C util/docker coreboot-sdk
+```
+$ make -C util/docker coreboot-sdk
 ```
 
 This takes a relatively long time.
 
-#### Test the coreboot-sdk docker image
+#### Test the coreboot-sdk docker image:
 
 There are two methods of running the docker image - interactively as a
 shell, or doing the build directly.  Running interactively as a shell is
@@ -334,44 +333,44 @@ useful for early testing, because it allows you to update the image
 (without any changes getting saved) and re-test builds.  This saves the
 time of having to rebuild the image for every issue you find.
 
-#### Running the docker image interactively
+#### Running the docker image interactively:
 
 Run:
 
-```sh
-make -C util/docker docker-jenkins-server
-make -C util/docker docker-jenkins-attach
+```
+$ make -C util/docker docker-jenkins-server
+$ make -C util/docker docker-jenkins-attach
 ```
 
-#### Running the build directly
+#### Running the build directly:
 
 From the coreboot directory:
 
-```sh
-make -C util/docker docker-build-coreboot
+```
+$ make -C util/docker docker-build-coreboot
 ```
 
 You’ll also want to test building the other projects and payloads:
 ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo,
 nvramcui, tint...
 
-#### Pushing the coreboot-sdk image to hub.docker.com for use
+#### Pushing the coreboot-sdk image to hub.docker.com for use:
 
 When you’re satisfied with the testing, push the coreboot-sdk image to
 the hub.docker.com
 
-```sh
-make -C util/docker upload-coreboot-sdk
+```
+$ make -C util/docker upload-coreboot-sdk
 ```
 
-#### Building and pushing the coreboot-jenkins-node docker image
+#### Building and pushing the coreboot-jenkins-node docker image:
 
 This docker image is pretty simple, so there’s not really any testing
 that needs to be done.
 
-```sh
-make -C util/docker coreboot-jenkins-node
-make -C util/docker upload-coreboot-jenkins-node
+```
+$ make -C util/docker coreboot-jenkins-node
+$ make -C util/docker upload-coreboot-jenkins-node
 ```
 
 ### Coverity Setup
@@ -392,7 +391,7 @@ Rename the directory from its original name
 (cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a
 symlink:
 
-```sh
+```
 ln -s cov-analysis-linux64-7.7.0.4 coverity
 ```
 

Documentation/mainboard/acer/g43t-am3.md

@@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There
 seems to be a diode that prevents the external programmer from powering the
 whole board.
 
-The signal assignment on the header is identical to the pinout of the flash
+The signal assigment on the header is identical to the pinout of the flash
 chip. The pinout diagram below is valid when the PCI slots are on the left
 and the CPU is on the right. Note that HOLD# and WP# must be pulled high
 (to VCC) to be able to flash the chip.

Documentation/mainboard/index.md

@@ -30,7 +30,6 @@ This section contains documentation about coreboot on specific mainboards.
 - [P8H77-V](asus/p8h77-v.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
-- [wifigo_v1](asus/wifigo_v1.md)
 
 ## Cavium
 
@@ -181,12 +180,10 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
-- [LabTop Mk III](starlabs/labtop_kbl.md)
 - [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
-- [Flashing devices](starlabs/common/flashing.md)
 
 ## Supermicro
 

Documentation/mainboard/starlabs/common/flashing.md

@@ -16,7 +16,7 @@ fwupdmgr --version
 ```
 
 This will show the version number. **1.5.6** or greater will work.
-![fwupd version](../fwupdVersion.png)
+![fwupd version](fwupdVersion.png)
 On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
 
 ```
@@ -40,7 +40,7 @@ BIOS Lock must be disabled when switching from the standard AMI (American Megatr
 2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
 3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
 
-![Disable BIOS Lock](../BiosLock.jpg)
+![Disable BIOS Lock](BiosLock.jpg)
 
 4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
 
@@ -61,7 +61,7 @@ fwupdmgr switch-branch
 ```
 
 You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](../SwitchBranch.png)
+![Switch Branch](SwitchBranch.png)
 You will be prompted to confirm, press `y` to continue or `n` to cancel.
 
 Once the switch has been completed, you will be prompted to restart.

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -1,83 +0,0 @@
-# Star LabTop Mk III
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-8550u  (Kaby Lake Refresh)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 620
-    - GOP driver is recommended, VBT is provided
-    - eDP 13-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 8265 PCIe WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - USB 3.1 Gen 2 Type-C (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-
-The below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 8  MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/northbridge/intel/sandybridge/nri_registers.md

@@ -1899,7 +1899,7 @@ Please handle with care!
 +===========+==================================================================+
 |        0:7|  PDWN_idle_counter, This defines the rank indle period in DCLK   |
 |           |  cycles that causes power-down entrance. The minimum value       |
-|           |  should be greater than or equal to the worst roundtrip time     |
+|           |  should be greater then or equal to the worst roundtrip time     |
 |           |  plus burst length.                                              |
 +-----------+------------------------------------------------------------------+
 |       8:10|  PDWN_mode, selects the mode of power-down:                      |

Documentation/payloads.md

@@ -13,15 +13,7 @@ payload or can be made to work as one.
 the PCBIOS API that exists since the original IBM PC and was extended
 since. While originally written for emulators such as QEMU, it can be made
 to work as a coreboot payload and all the necessary code is in SeaBIOS'
-mainline code, or as a secondary payload load by another payload, e.g. it
-can be loaded from GRUB2 with the following menuentry in the run time
-config of GRUB2:
-
-    menuentry "SeaBIOS" --unrestricted {
-        root=(cbfsdisk)
-        multiboot /img/seabios
-        module /vgaroms/seavgabios.bin
-    }
+mainline code.
 
 ## Tianocore
 

Documentation/releases/boards_supported_on_branches.md

@@ -1,326 +0,0 @@
-# Platforms supported on branches
-
-For one reason or another, platforms have been deleted from the master
-branch at times in the past.  Early on, there was no real policy on
-removing boards.  Now the policy is that boards will only be removed if
-they're causing issues in the tree or if they're preventing progress.
-
-This does not mean that these boards are gone forever.  The release or
-commit prior to where they were removed can be checked out, and the
-boards can still be built there and updated in a release branch if
-desired.
-
-Currently, [jenkins](https://qa.coreboot.org), our continuous
-integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-and 4.16 branches.  Builders for other branches can be created on
-request.  Likewise, some releases are only marked with tags, and
-branches would need to be created to push new code to.  These branches
-can also be created on request.
-
-Patches can be backported from the master branch to any of these other
-branches as needed. The coreboot project will take care of backporting
-critical security fixes, but other patches will need to handled by
-anyone using that release.
-
-## [4.16 Release](coreboot-4.16-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.15 Release](coreboot-4.15-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.14 Release](coreboot-4.14-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.13 Release](coreboot-4.13-relnotes.md)
-Tag only
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-
-
-## [4.12 Release](coreboot-4.12-relnotes.md)
-
-Branch created, builder configured
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-| lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-| ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-
-
-## [4.11 Release](coreboot-4.11-relnotes.md)
-
-Branch created, builder configured
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-| advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-| amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-| amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-| amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-| amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-| amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-| amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-| amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-| amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-| amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-| amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-| asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-| asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-| asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-| asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-| asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-| asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-| asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-| avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-| esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-| facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-| gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-| gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-| gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-| google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-| hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-| iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-| intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-| intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-| intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-| intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-| intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-| jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-| msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-| ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-| ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-| opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-| siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-| supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-| supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-| supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-| tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-| via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-| via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-
-
-## [4.10 Release](coreboot-4.10-relnotes.md)
-Branch created
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-
-
-## [4.9 Release](coreboot-4.9-relnotes.md)
-Tag only
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-| pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-| pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-| pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-
-
-## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
-Branch created
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-| amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-| amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-| amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-| amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-| amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-| amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-| amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-| artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-| asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-| asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-| asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-| asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-| asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-| asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-| asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-| asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-| asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-| bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-| bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-| broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-| digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-| gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-| gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-| google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-| google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-| google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-| hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-| hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-| iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-| iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-| iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-| intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-| intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-| iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-| jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-| kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-| lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-| lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-| lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-| lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-| lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-| msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-| msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-| msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-| msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-| nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-| siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-| sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-| sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-| supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-| supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-| technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-| technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-| traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-| tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-| via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-| via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-| via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-| via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-| winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-| winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-| winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-
-
-## [4.7 Release](coreboot-4.7-relnotes.md)
-Tag only
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-| amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-| amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-| asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-| asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-| asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-| a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-| a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-| azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-| biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-| compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-| dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-| ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-| gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-| gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-| hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-| intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-| intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-| intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-| intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-| iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-| lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-| lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-| mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-| msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-| msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-| msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-| msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-| nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-| nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-| rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-| soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-| supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-| supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-| supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-| thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-| tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-| tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
-| wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-
-
-## [4.6](coreboot-4.6-relnotes.md)
-Tag only
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-| google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-| intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-
-
-## [4.5](coreboot-4.5-relnotes.md)
-Tag only
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-| google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-| google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-| google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-| google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-| google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-| google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-| google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-| google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-
-
-## [4.4](coreboot-4.4-relnotes.md)
-Branch created
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-| google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-| google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-| google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-| intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-
-
-## [4.3](coreboot-4.3-relnotes.md)
-Branch created
-
-* No platforms maintained on this release
-
-
-## [4.2](coreboot-4.2-relnotes.md)
-Branch created
-
-| Vendor/Board                | Processor              | Date added | Brd type |
-|-----------------------------|------------------------|------------|----------|
-| arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-| digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-| ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-| ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-| intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-| iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-| iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-| newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-| tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-| tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-| tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-| tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-| tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-| tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-| tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-| tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-| tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-| tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-| tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-| tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-
-
-## [4.1](coreboot-4.1-relnotes.md)
-Branch Created
-
-* No platforms maintained on this release

Documentation/releases/coreboot-4.16-relnotes.md

@@ -132,7 +132,7 @@ HECI based on Intel Core processors from Skylake to Alder Lake. State is
 set based on a CMOS value of `me_state`. A value of `0` will result in a
 (CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
 state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/soc/intel/common/block/cse/cse.c).
+[cse.c](../../src/soc/intel/common/block/cse/cse.c).
 
 
 ### Add [AMD] apcb_v3_edit tool

Documentation/releases/coreboot-4.17-relnotes.md

@@ -1,346 +1,19 @@
-coreboot 4.17
-========================================================================
+Upcoming release - coreboot 4.17
+================================
 
+The 4.17 release is planned for May, 2022.
 
-The coreboot 4.17 release is being done on June 1, 2022.
+We are continuing the quarterly release cadence in order to enable others to
+release quarterly on a fresher version of coreboot.
 
-Since the 4.16 release, we've had over 1260 new commits by around 150
-contributors.  Of those people, roughly 15 were first-time contributors.
+Update this document with changes that should be in the release notes.
 
-As always, we appreciate everyone who has contributed and done the hard
-work to make the coreboot project successful.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
+Significant changes
+-------------------
 
-Major Bugfixes in this release
-------------------------------
-* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264)
-
-
-New Mainboards
---------------
-
-* Clevo L140MU / L141MU / L142MU
-* Dell Precision T1650
-* Google Craask
-* Google Gelarshie
-* Google Kuldax
-* Google Mithrax
-* Google Osiris
-* HP Z220 CMT Workstation
-* Star Labs LabTop Mk III (i7-8550u)
-* Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-* Star Labs Lite Mk III (N5000)
-* Star Labs Lite Mk IV (N5030)
-
-
-Removed Mainboards
-------------------
-
-* Google Deltan
-* Google Deltaur
-
-Significant or interesting changes
-----------------------------------
-
-These changes are a few that were selected as a sampling of particularly
-interesting commits.
-
-
-### CBMEM init hooks changed
-
-Instead of having per stage x_CBMEM_INIT_HOOK, we now have only 2 hooks:
-* CBMEM_CREATION_HOOK: Used only in the first stage that creates cbmem,
-  typically romstage. For instance code that migrates data from cache
-  as ram to dram would use this hook.
-* CBMEM_READY_HOOK: Used in every stage that has cbmem. An example would
-  be initializing the cbmem console by appending to what previous stages
-  logged.
-The reason for this change is improved flexibility with regards to which
-stage initializes cbmem.
-
-
-### Payloads
-
-* SeaBIOS: Update stable release from 1.14.0 to 1.16.0
-* iPXE: Update stable release from 2019.3 to 2022.1
-* Add "GRUB2 atop SeaBIOS" aka "SeaGRUB" option, which builds GRUB2 as a
-  secondary payload for SeaBIOS with GRUB2 set as the default boot
-  entry.  This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as
-  a fallback method to access hardware that the native GRUB2 payload
-  cannot access.
-* Add option to build SeaBIOS and GRUB2 as secondary payloads
-* Add new coreDOOM payload.  See commit message below.
-
-
-### payloads/external: Add support for coreDOOM payload
-
-coreDOOM is a port of DOOM to libpayload, based on the doomgeneric
-source port. It renders the game to the coreboot linear framebuffer,
-and loads WAD files from CBFS.
-
-
-### cpu/x86/smm_module_load: Rewrite setup_stub
-
-This code was hard to read as it did too much and had a lot of state
-to keep track of.
-
-It also looks like the staggered entry points were first copied and
-only later the parameters of the first stub were filled in. This
-means that only the BSP stub is actually jumping to the permanent
-smihandler. On the APs the stub would jump to wherever c_handler
-happens to point to, which is likely 0. This effectively means that on
-APs it's likely easy to have arbitrary code execution in SMM which is a
-security problem.
-
-Note: This patch fixes CVE-2022-29264 for the 4.17 release.
-
-
-### cpu/x86/smm_module_loader.c: Rewrite setup
-
-This code is much easier to read if one does not have to keep track of
-mutable variables.
-
-This also fixes the alignment code on the TSEG smihandler setup code.
-It was aligning the code upwards instead of downwards which would cause
-it to encroach a part of the save state.
-
-
-### cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
-
-The sinkhole exploit exists in placing the lapic base such that it
-messes with GDT. This can be mitigated by checking the lapic MSR
-against the current program counter.
-
-
-### cpu/x86/64bit: Generate static page tables from an assembly file
-
-This removes the need for a tool to generate simple identity pages.
-Future patches will link this page table directly into the stages on
-some platforms so having an assembly file makes a lot of sense.
-
-This also optimizes the size of the page of each 4K page by placing
-the PDPE_table below the PDE.
-
-
-### cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
-
-This change will allow the SMI handler to write to the cbmem console
-buffer. Normally SMIs can only be debugged using some kind of serial
-port (UART). By storing the SMI logs into cbmem we can debug SMIs using
-'cbmem -1'. Now that these logs are available to the OS we could also
-verify there were no errors in the SMI handler.
-
-Since SMM can write to all of DRAM, we can't trust any pointers
-provided by cbmem after the OS has booted. For this reason we store the
-cbmem console pointer as part of the SMM runtime parameters. The cbmem
-console is implemented as a circular buffer so it will never write
-outside of this area.
-
-
-### security/tpm/crtm: Add a function to measure the bootblock on SoC level
-
-On platforms where the bootblock is not included in CBFS anymore
-because it is part of another firmware section (IFWI or a different
-CBFS), the CRTM measurement fails.
-
-This patch adds a new function to provide a way at SoC level to measure
-the bootblock. Following patches will add functionality to retrieve the
-bootblock from the SoC related location and measure it from there.
-In this way the really executed code will be measured.
-
-
-### soc/amd/common/block/psp: Add platform secure boot support
-
-Add Platform Secure Boot (PSB) enablement via the PSP if it is not
-already enabled. Upon receiving psb command, PSP will program PSB fuses
-as long as BIOS signing key token is valid.
-Refer to the AMD PSB user guide doc# 56654, Revision# 1.00.
-Unfortunately this document is only available with NDA customers.
-
-
-### drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
-
-This patch implements coreboot native debug handler to manage the FSP
-event messages.
-
-'FSP Event Handlers' feature introduced in FSP to generate event
-messages to aid in the debugging of firmware issues. This eliminates
-the need for FSP to directly write debug messages to the UART and FSP
-might not need to know the board related UART port configuration.
-Instead FSP signals the bootloader to inform it of a new debug message.
-This allows the coreboot to provide board specific methods of reporting
-debug messages, example: legacy UART or LPSS UART etc.
-
-This implementation has several advantages as:
-1. FSP relies on XIP 'DebugLib' driver even while printing FSP-S debug
-  messages, hence, without ROM being cached, post 'romstage' would
-  results into sluggish boot with FSP debug enabled.
-  This patch utilities coreboot native debug implementation which is
-  XIP during FSP-M and relocatable to DRAM based resource for FSP-S.
-
-2. This patch simplifies the FSP DebugLib implementation and remove the
-   need to have serial port library. Instead coreboot 'printk' can be
-   used for display FSP serial messages. Additionally, unifies the debug
-   library between coreboot and FSP.
-
-3. This patch is also useful to get debug prints even with FSP
-   non-serial image (refer to 'Note' below) as FSP PEIMs are now
-   leveraging coreboot debug library instead FSP 'NULL' DebugLib
-   reference for release build.
-
-4. Can optimize the FSP binary size by removing the DebugLib dependency
-   from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary
-   size is reduced by ~100KB+ and FSP-S debug library size is also
-   reduced by ~300KB+ (FSP-S debug and release binary size is exactly
-   same with this code changes). The total savings is ~400KB for each
-   FSP copy, and in case of Chrome AP firmware with 3 copies, the total
-   savings would be 400KB * 3 = ~1.2MB.
-
-Note: Need to modify FSP source code to remove 'MDEPKG_NDEBUG' as
-compilation flag for release build and generate FSP binary with non-NULL
-FSP debug wrapper module injected (to allow FSP event handler to execute
-even with FSP non-serial image) in the final FSP.fd.
-
-
-### security/tpm: Add vendor-specific tis functions to read/write TPM regs
-
-In order to abstract bus-specific logic from TPM logic, the prototype
-for two vendor-specific tis functions are added in this
-patch. tis_vendor_read() can be used to read directly from TPM
-registers, and tis_vendor_write() can be used to write directly to TPM
-registers.
-
-
-### arch/x86: Add support for catching null dereferences through debug regs
-
-This commit adds support for catching null dereferences and execution
-through x86's debug registers. This is particularly useful when running
-32-bit coreboot as paging is not enabled to catch these through page
-faults. This commit adds three new configs to support this feature:
-DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and
-DEBUG_NULL_DEREF_HALT.
-
-
-### drivers/i2c/generic: Add support for i2c device detection
-
-Add 'detect' flag which can be attached to devices which may or may not
-be present at runtime, and for which coreboot should probe the i2c bus
-to confirm device presence prior to adding an entry for it in the SSDT.
-
-This is useful for boards which may utilize touchpads/touchscreens from
-multiple vendors, so that only the device(s) present are added to the
-SSDT. This relieves the burden from the OS to detect/probe if a device
-is actually present and allows the OS to trust the ACPI _STA value.
-
-
-### util/cbmem: Add FlameGraph-compatible timestamps output
-
-Flame graphs are used to visualize hierarchical data, like call stacks.
-Timestamps collected by coreboot can be processed to resemble
-profiler-like output, and thus can be feed to flame graph generation
-tools.
-
-Generating flame graph using https://github.com/brendangregg/FlameGraph:
-```
-   cbmem -S > trace.txt
-   FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg
-```
-
-
-### src/console/Kconfig: Add option to disable loglevel prefix
-
-This patch adds an option to disable loglevel prefixes. This patch helps
-to achieve clear messages when low loglevel is used and very few
-messages are displayed on a terminal. This option also allows to
-maintain compatibility with log readers and continuous integration
-systems that depend on fixed log content.
-
-If the code contains:
-  printk(BIOS_DEBUG, "This is a debug message!\n")
-it will show as:
-  [DEBUG]  This is a debug message!
-but if the Kconfig contains:
-  CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
-the same message will show up as
-  This is a debug message!
-
-
-### util/cbmem: add an option to append timestamp
-
-Add an option to the cbmem utility that can be used to append an entry
-to the cbmem timestamp table from userspace. This is useful for
-bookkeeping of post-coreboot timing information while still being able
-to use cbmem-based tooling for processing the generated data.
-
-
-`-a | --add-timestamp ID:          append timestamp with ID\n`
-
-
-Additional changes
-------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* As always, general documentation, code cleanup, and refactoring
-* Remove doxygen config files and targets
-* Get clang compile working for all x86 platforms
-* Work on updating checkpatch to match the current Linux version
-* Timestamps: Rename timestamps to make names more consistent
-* Continue updating ACPI code to ASL 2.0
-* Remove redundant or unnecessary headers from C files
-* arch/x86/acpi_bert_storage.c: Use a common implementation
-* Postcar stage improvements
-* arch/x86/acpi: Consolidate POST code handling
-* intel/common: Enable ROM caching in ramstage
-* vendorcode/amd/agesa: Fix improper use of .data (const is important)
-* sandybridge & gm45: Support setting PCI bars above 4G
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever was
-the CRB board. From the looks of it the code never was ready for production as
-only engineering sample CPUIDs are supported.
-
-Thus, to reduce the maintanence overhead for the community, it is deprecated
-from this release on and support for the following components will be dropped
-with the release 4.19.
-
-  * Intel Icelake SoC
-  * Intel Icelake RVP mainboard
-
-
-### LEGACY_SMP_INIT
-
-As of release 4.18 (August 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
-
-
-Statistics
-----------
-
-- Total Commits: 1261
-- Average Commits per day: 13.26
-- Total lines added: 42535
-- Average lines added per commit: 33.73
-- Number of patches adding more than 100 lines: 51
-- Average lines added per small commit: 21.00
-- Total lines removed: 65961
-- Average lines removed per commit: 52.31
-- Total difference between added and removed: -23426
-- Total authors: 146
-- New authors: 17
+### Add significant changes here

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,56 +0,0 @@
-Upcoming release - coreboot 4.18
-================================
-
-The 4.18 release is planned for August 2022.
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-
-Significant changes
--------------------
-
-### Add significant changes here
-
-
-
-
-
-
-
-
-
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake
-
-Intel Icelake code will be removed following the 4.19 release, planned
-for November 2022. This consists of the Intel Icelake SOC and Intel
-Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the CRB board. From the looks of it the code never was ready for
-production as only engineering sample CPUIDs are supported. This reduces
-the maintanence overhead for the coreboot project.
-
-
-### LEGACY_SMP_INIT
-
-Legacy SMP init will be removed from the coreboot master branch
-immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch.
-
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.18 - Aug 2022](coreboot-4.18-relnotes.md)
+* [4.17 - May 2022](coreboot-4.17-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,7 +15,6 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
 * [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -73,6 +73,8 @@
 - Ultima (Lenovo Yoga 11e G3)
 - Wizpig
 - Daisy (Samsung Chromebook (2012))
+- Deltan
+- Deltaur
 - Drallion
 - Eve (Google Pixelbook)
 - Fizz

Documentation/util.md

@@ -25,7 +25,7 @@ status repository `Bash` `Go`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
-	* [_cbfstool_](util/cbfstool/index.md) - For manipulating CBFS file
+	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file
 `C`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
@@ -50,7 +50,7 @@ Controller (EC). `C`
 * __genbuild_h__ - Generate build system definitions `Shell`
 * __gitconfig__ - Initialize git repository submodules install git
 hooks `Bash`
-* [__ifdtool__](util/ifdtool/index.md) - Extract and dump Intel Firmware
+* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware
 Descriptor information `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
@@ -155,9 +155,7 @@ the documentation `Bash`
 
  ## In depth documentation
 
-* [cbfstool](util/cbfstool/index.md)
-* [ifdtool](util/ifdtool/index.md)
-* [intelp2m](util/intelp2m/index.md)
+* [ifdtool](ifdtool/index.md)
 
 ## Generated documentation
 

Documentation/util/intelp2m/index.md

@@ -1,210 +0,0 @@
-Intel Pad to Macro (intelp2m) converter
-=======================================
-
-This utility allows one to convert the configuration DW0/1 register
-values from an inteltool dump to coreboot macros.
-
-```bash
-cd util/intelp2m
-make
-./intelp2m -h
-./intelp2m -file /path/to/inteltool.log
-```
-
-### Platforms
-
-It is possible to use templates for parsing inteltool.log files.
-To specify such a pattern, use the option `-t <template number>`.
-
-```text
-    -t
-    template type number
-        0 - inteltool.log (default)
-        1 - gpio.h
-        2 - your template
-```
-
-For example, using template type 1, you can parse gpio.h from an
-existing board in the coreboot project.
-
-```bash
-./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h
-```
-
-You can also add a template to 'parser/template.go' for your file type
-with the configuration of the pads.
-
-platform type is set using the -p option (Sunrise by default):
-
-```text
--p string
-  set up a platform
-    snr - Sunrise PCH with Skylake/Kaby Lake CPU
-    lbg - Lewisburg PCH with Xeon SP CPU
-    apl - Apollo Lake SoC
-    cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
-    adl - AlderLake PCH
-  (default "snr")
-```
-
-```bash
-./intelp2m -p <platform> -file path/to/inteltool.log
-```
-
-### Packages
-
-![][pckgs]
-
-[pckgs]: gopackages.png
-
-### Bit fields in macros
-
-Use the `-fld=cb` option to only generate a sequence of bit fields in
-a new macro:
-
-```bash
-./intelp2m -fld cb -p apl -file ../apollo-inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \
-    PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */
-```
-
-### Raw DW0, DW1 register value
-
-To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register
-values you need to use the -fld=raw option:
-
-```bash
-./intelp2m -fld raw -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-```bash
-./intelp2m -iiii -fld raw -file /path/to/inteltool.log
-```
-
-```c
-/* GPP_A10 - CLKOUT_LPC1 */
-/* DW0: 0x44000500, DW1: 0x00000000 */
-/* DW0: 0x04000100 - IGNORED */
-/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-### Macro Check
-
-After generating the macro, the utility checks all used
-fields of the configuration registers. If some field has been
-ignored, the utility generates field macros. To not check
-macros, use the -n option:
-
-```bash
-./intelp2m -n -file /path/to/inteltool.log
-```
-
-In this case, some fields of the configuration registers
-DW0 will be ignored.
-
-```c
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
-```
-
-### Information level
-
-The utility can generate additional information about the bit
-fields of the DW0 and DW1 configuration registers. Using the
-options -i, -ii, -iii, -iiii you can set the info level from
-1 to 4:
-
-```bash
-./intelp2m -i -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),\
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),    /* LPSS_UART0_TXD */
-```
-
-```bash
-./intelp2m -ii -file /path/to/inteltool.log
-./intelp2m -iii -file /path/to/inteltool.log
-./intelp2m -iiii -file /path/to/inteltool.log
-```
-
-```c
-/* GPIO_39 - LPSS_UART0_TXD */
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
-   DISPUPD), */ --> (iiii)
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
-```
-
-If the -n switch was used and macros was generated without checking:
-```c
-/* GPIO_39 - LPSS_UART0_TXD */ --> (i)
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0: PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
-  PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii)
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \
-    DISPUPD),
-```
-
-### Ignoring Fields
-
-Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields
-from it that are not in the corresponding PAD_CFG_*() macro:
-
-```bash
-./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log
-```
-
-```c
-/* GPIO_39 - LPSS_UART0_TXD */
-/* DW0: 0x44000400, DW1: 0x00003100 */
-/* DW0: PAD_TRIG(OFF) - IGNORED */
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1,
-   TxLASTRxE, DISPUPD), */
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
-```
-
-### FSP-style macro
-
-The utility allows one to generate macros that include fsp/edk2-platform
-style bitfields:
-
-```bash
-./intelp2m -i -fld fsp -p lbg -file ../crb-inteltool.log
-```
-
-```c
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },    /* GPIO */
-```
-
-```bash
-./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log
-```
-
-```c
-/* GPP_A12 - GPIO */
-/* DW0: 0x80880102, DW1: 0x00000000 */
-/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },
-```
-
-### Supported Chipsets
-
-  Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs

Makefile

@@ -64,6 +64,9 @@ HOSTCXXFLAGS := -g
 
 PREPROCESS_ONLY := -E -P -x assembler-with-cpp -undef -I .
 
+DOXYGEN := doxygen
+DOXYGEN_OUTPUT_DIR := doxygen
+
 export $(COREBOOT_EXPORTS)
 
 all: real-all
@@ -74,6 +77,8 @@ help_coreboot help::
 	@echo  '  all                   - Build coreboot'
 	@echo  '  clean                 - Remove coreboot build artifacts'
 	@echo  '  distclean             - Remove build artifacts and config files'
+	@echo  '  doxygen               - Build doxygen documentation for coreboot'
+	@echo  '  doxyplatform          - Build doxygen documentation for the current platform'
 	@echo  '  sphinx                - Build sphinx documentation for coreboot'
 	@echo  '  sphinx-lint           - Build sphinx documenttion for coreboot with warnings as errors'
 	@echo  '  filelist              - Show files used in current build'
@@ -445,7 +450,27 @@ sphinx:
 sphinx-lint:
 	$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
 
-clean-for-update:
+doxy: doxygen
+doxygen:
+	$(DOXYGEN) Documentation/Doxyfile.coreboot
+
+doxygen_simple:
+	$(DOXYGEN) Documentation/Doxyfile.coreboot_simple
+
+doxyplatform doxygen_platform: $(obj)/project_filelist.txt
+	echo
+	echo "Building doxygen documentation for $(CONFIG_MAINBOARD_PART_NUMBER)"
+	export DOXYGEN_OUTPUT_DIR="$$( echo $(DOXYGEN_OUTPUT_DIR)/$(call strip_quotes, $(CONFIG_MAINBOARD_VENDOR))_$(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER)) | sed 's|[^A-Za-z0-9/]|_|g' )"; \
+	mkdir -p "$$DOXYGEN_OUTPUT_DIR"; \
+	export DOXYFILES="$$(cat $(obj)/project_filelist.txt | grep -v '\.ld$$' | sed 's/\.aml/\.dsl/' | tr '\n' ' ')"; \
+	export DOXYGEN_PLATFORM="$(call strip_quotes, $(CONFIG_MAINBOARD_DIR)) \($(call strip_quotes, $(CONFIG_MAINBOARD_PART_NUMBER))\) version $(KERNELVERSION)"; \
+	$(DOXYGEN) Documentation/doxygen/Doxyfile.coreboot_platform
+
+doxyclean: doxygen-clean
+doxygen-clean:
+	rm -rf $(DOXYGEN_OUTPUT_DIR)
+
+clean-for-update: doxygen-clean
 	rm -rf $(obj) .xcompile
 
 clean: clean-for-update clean-utils clean-payloads
@@ -471,5 +496,5 @@ distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
 	rm -rf coreboot-builds coreboot-builds-chromeos
 	rm -f abuild*.xml junit.xml* util/lint/junit.xml
 
-.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean sphinx sphinx-lint
+.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy doxygen_simple sphinx sphinx-lint
 .PHONY: ctags-project cscope-project clean-ctags

Makefile.inc

@@ -270,7 +270,7 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
 # For existing ASL code, ignore this warnings
 IASL_MISSING_DEPENDENCY = 3141
 
-IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING)
+IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)
 
 ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
 	IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
@@ -1100,19 +1100,38 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
 
-ifneq ($(CONFIG_ARCH_X86),y)
-add_bootblock = $(CBFSTOOL) $(1) write -u -r BOOTBLOCK -f $(2)
-endif
-
 # coreboot.pre doesn't follow the standard Make conventions. It gets modified
 # by multiple rules, and thus we can't compute the dependencies correctly.
 $(shell rm -f $(obj)/coreboot.pre)
 
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
-$(obj)/coreboot.pre: $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc $(objcbfs)/bootblock.bin
+$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
-	printf "    BOOTBLOCK\n"
-	$(call add_bootblock,$@.tmp,$(objcbfs)/bootblock.bin)
+ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp add \
+		-f $(objcbfs)/bootblock.bin \
+		-n bootblock \
+		-t bootblock \
+		$(TXTIBB) \
+		-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
+		$(TS_OPTIONS) \
+		$(CBFSTOOL_ADD_CMD_OPTIONS)
+else # ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp write -u \
+		-r BOOTBLOCK \
+		-f $(objcbfs)/bootblock.bin
+	# make space for the CBFS master header pointer. "ptr_" is just
+	# arbitrary 4 bytes that will be overwritten by add-master-header.
+	printf "ptr_" > $@.tmp.2
+	$(CBFSTOOL) $@.tmp add \
+		-f $@.tmp.2 \
+		-n "header pointer" \
+		-t "cbfs header" \
+		-b -4 \
+		$(CBFSTOOL_ADD_CMD_OPTIONS)
+	rm -f $@.tmp.2
+endif # ifeq ($(CONFIG_ARCH_X86),y)
+	$(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
 	$(prebuild-files) true
 	mv $@.tmp $@
 else # ifneq ($(CONFIG_UPDATE_IMAGE),y)

README.md

@@ -54,6 +54,7 @@ Build Requirements
 
 Optional:
 
+ * doxygen (for generating/viewing documentation)
  * gdb (for better debugging facilities on some targets)
  * ncurses (for `make menuconfig` and `make nconfig`)
  * flex and bison (for regenerating parsers)

configs/config.lenovo_t400_vboot_and_debug

@@ -12,4 +12,3 @@ CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
 CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
 CONFIG_VBOOT=y
-CONFIG_USE_EXP_X86_64_SUPPORT=y

payloads/Kconfig

@@ -121,15 +121,6 @@ config COREINFO_SECONDARY_PAYLOAD
 	  coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,
 	  or any other payload that can load additional payloads.
 
-config GRUB2_SECONDARY_PAYLOAD
-	bool "Load GRUB2 as a secondary payload"
-	default n
-	depends on !PAYLOAD_GRUB2
-	select PAYLOAD_BUILD_GRUB2
-	help
-	  GRUB2 can be loaded as a secondary payload under SeaBIOS or any
-	  other payload that can load additional payloads.
-
 config MEMTEST_SECONDARY_PAYLOAD
 	bool "Load Memtest86+ as a secondary payload"
 	default n
@@ -146,17 +137,6 @@ config NVRAMCUI_SECONDARY_PAYLOAD
 	  nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
 	  or any other payload that can load additional payloads.
 
-config SEABIOS_SECONDARY_PAYLOAD
-	bool "Load SeaBIOS as a secondary payload"
-	default n
-	depends on ARCH_X86
-	depends on !PAYLOAD_SEABIOS
-	depends on !PAYLOAD_SEAGRUB
-	select PAYLOAD_BUILD_SEABIOS
-	help
-	  SeaBIOS can be loaded as a secondary payload under GRUB or any
-	  other payload that can load additional payloads.
-
 config TINT_SECONDARY_PAYLOAD
 	bool "Load tint as a secondary payload"
 	default n
@@ -165,16 +145,6 @@ config TINT_SECONDARY_PAYLOAD
 	  tint can be loaded as a secondary payload under SeaBIOS, GRUB,
 	  or any other payload that can load additional payloads.
 
-config COREDOOM_SECONDARY_PAYLOAD
-	bool "Load coreDOOM as a secondary payload"
-	default n
-	depends on ARCH_X86
-	help
-	  coreDOOM can be loaded as a secondary payload under SeaBIOS, GRUB,
-	  or any other payload that can load additional payloads. Requires a
-	  linear framebuffer. If built as a secondary payload for SeaBIOS, the
-	  generated VGA BIOS option rom is also required.
-
 source "payloads/external/*/Kconfig.secondary"
 
 endmenu # "Secondary Payloads"

payloads/Makefile.inc

@@ -29,7 +29,6 @@ payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/Yabits \
 payloads/external/skiboot \
-payloads/external/coreDOOM \
 
 force-payload:
 

payloads/coreinfo/coreboot_module.c

@@ -186,6 +186,7 @@ static int parse_header(void *addr, int len)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			return parse_header((void *)(unsigned long)((struct cb_forward *)rec)->forward, 1);
+			break;
 		case CB_TAG_MEMORY:
 			parse_memory(ptr);
 			break;

payloads/external/GRUB2/Kconfig

@@ -1,15 +1,5 @@
-config PAYLOAD_BUILD_GRUB2
-	bool
-
 if PAYLOAD_GRUB2
 
-config PAYLOAD_FILE
-	default "payloads/external/GRUB2/grub2/build/default_payload.elf"
-
-endif
-
-if PAYLOAD_BUILD_GRUB2
-
 choice
 	prompt "GRUB2 version"
 	default GRUB2_STABLE
@@ -52,9 +42,12 @@ config GRUB2_EXTRA_MODULES
 	  * gfxmenu for graphical menus (you'll need a theme as well)
 	  * gfxterm_background for setting background
 
+config PAYLOAD_FILE
+	default "payloads/external/GRUB2/grub2/build/default_payload.elf"
+
 config GRUB2_INCLUDE_RUNTIME_CONFIG_FILE
 	bool "Include GRUB2 runtime config file into ROM image"
-	depends on PAYLOAD_BUILD_GRUB2
+	depends on PAYLOAD_GRUB2
 	default n
 	help
 	  The GRUB2 payload reads its runtime configuration file from etc/grub.cfg
@@ -79,20 +72,3 @@ config GRUB2_RUNTIME_CONFIG_FILE
 	  The path of the GRUB2 runtime configuration file to be added to CBFS.
 
 endif
-
-if PAYLOAD_SEAGRUB
-
-config PAYLOAD_FILE
-	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
-
-config SEABIOS_BOOTORDER_FILE
-	default "payloads/external/GRUB2/bootorder-seagrub"
-
-config SEAGRUB_ALLOW_SEABIOS_BOOTMENU
-	bool "Allow to access SeaBIOS boot menu before launching GRUB"
-	help
-	  Enable this to allow the access to the boot menu of SeaBIOS. It
-	  increases the flexibility but allows to bypass the secure mechanism
-	  implemented in the GRUB runtime config. Please use this with caution.
-
-endif

payloads/external/GRUB2/Kconfig.name

@@ -1,22 +1,9 @@
 config PAYLOAD_GRUB2
 	bool "GRUB2"
 	depends on ARCH_X86 || ARCH_ARM
-	select PAYLOAD_BUILD_GRUB2
 	help
 	  Select this option if you want to build a coreboot image
 	  with a GRUB2 payload. If you don't know what this is
 	  about, just leave it enabled.
 
 	  See https://coreboot.org/Payloads for more information.
-
-config PAYLOAD_SEAGRUB
-	bool "GRUB2 atop SeaBIOS"
-	depends on ARCH_X86
-	select PAYLOAD_BUILD_SEABIOS
-	select GRUB2_SECONDARY_PAYLOAD
-	help
-	  Select this option if you want to build a coreboot image
-	  with a GRUB2 payload running atop SeaBIOS to improve its
-	  hardware compatibility.
-
-	  See https://coreboot.org/Payloads for more information.

payloads/external/GRUB2/bootorder-seagrub

@@ -1 +0,0 @@
-/rom@img/grub2

payloads/external/Makefile.inc

@@ -1,7 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 # set up payload config and version files for later inclusion
-ifeq ($(CONFIG_PAYLOAD_BUILD_SEABIOS),y)
+ifeq ($(CONFIG_PAYLOAD_SEABIOS),y)
 PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config
 PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h
 endif
@@ -61,8 +61,7 @@ etc/grub.cfg-required := the GRUB runtime configuration file ($(CONFIG_GRUB2_RUN
 # SeaBIOS
 
 SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1)
-SEABIOS_TARGET_PATH=payloads/external/SeaBIOS/seabios/out/bios.bin.elf
-$(SEABIOS_TARGET_PATH): $(DOTCONFIG)
+payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG)
 	$(MAKE) -C payloads/external/SeaBIOS \
 			HOSTCC="$(HOSTCC)" \
 			CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) \
@@ -89,14 +88,9 @@ $(SEABIOS_TARGET_PATH): $(DOTCONFIG)
 			CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) \
 			CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ)
 
-payloads/external/SeaBIOS/seabios/out/vgabios.bin: $(SEABIOS_TARGET_PATH)
-payloads/external/SeaBIOS/seabios/.config: $(SEABIOS_TARGET_PATH)
-payloads/external/SeaBIOS/seabios/out/autoversion.h: $(SEABIOS_TARGET_PATH)
-
-cbfs-files-$(CONFIG_SEABIOS_SECONDARY_PAYLOAD) += img/seabios
-img/seabios-file := $(SEABIOS_TARGET_PATH)
-img/seabios-type := payload
-img/seabios-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
+payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
+payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
+payloads/external/SeaBIOS/seabios/out/autoversion.h: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
 
 # add a SeaBIOS bootorder file
 ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),)
@@ -128,18 +122,6 @@ $(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL))
 	$(CBFSTOOL) $< add-int -i 2 -n etc/threads
 endif
 
-ifeq ($(CONFIG_PAYLOAD_SEAGRUB),y)
-ifneq ($(CONFIG_SEAGRUB_ALLOW_SEABIOS_BOOTMENU),y)
-$(call add_intermediate, seabios_bootmenu, $(CBFSTOOL))
-	@printf "    SeaBIOS    Disable boot menu\n"
-	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/show-boot-menu 2>/dev/null)
-	$(CBFSTOOL) $< add-int -i 0 -n etc/show-boot-menu
-else
-$(call add_intermediate, seabios_bootmenu, $(CBFSTOOL))
-	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/show-boot-menu 2>/dev/null)
-endif
-endif
-
 # Depthcharge
 
 payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL)
@@ -207,13 +189,6 @@ payloads/external/FILO/filo/build/version.h: filo
 
 # Grub
 
-GRUB_TARGET_PATH=payloads/external/GRUB2/grub2/build/default_payload.elf
-
-cbfs-files-$(CONFIG_GRUB2_SECONDARY_PAYLOAD) += img/grub2
-img/grub2-file := $(GRUB_TARGET_PATH)
-img/grub2-type := payload
-img/grub2-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
-
 grub2: $(obj)/config.h
 	$(MAKE) -C payloads/external/GRUB2 \
 			HOSTCC="$(HOSTCC)" \
@@ -226,7 +201,7 @@ grub2: $(obj)/config.h
 			CONFIG_GRUB2_REVISION_ID=$(CONFIG_GRUB2_REVISION_ID) \
 			CONFIG_GRUB2_EXTRA_MODULES=$(CONFIG_GRUB2_EXTRA_MODULES)
 
-$(GRUB_TARGET_PATH): grub2
+payloads/external/GRUB2/grub2/build/default_payload.elf: grub2
 
 # U-Boot
 
@@ -372,19 +347,3 @@ payloads/external/skiboot/build/skiboot.elf:
 	$(MAKE) -C payloads/external/skiboot all \
 		CONFIG_SKIBOOT_GIT_REPO=$(CONFIG_SKIBOOT_GIT_REPO) \
 		CONFIG_SKIBOOT_REVISION=$(CONFIG_SKIBOOT_REVISION)
-# COREDOOM
-
-payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf coredoom:
-	$(MAKE) -C payloads/external/coreDOOM
-
-cbfs-files-$(CONFIG_COREDOOM_SECONDARY_PAYLOAD) += img/coreDOOM
-img/coreDOOM-file := payloads/external/coreDOOM/coredoom/doomgeneric/coredoom.elf
-img/coreDOOM-type := payload
-img/coreDOOM-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
-# WAD file
-ifneq ($(strip $(CONFIG_COREDOOM_WAD_FILE)),)
-cbfs-files-y += doom.wad
-doom.wad-file := $(strip $(CONFIG_COREDOOM_WAD_FILE))
-doom.wad-type := raw
-doom.wad-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
-endif

payloads/external/SeaBIOS/Kconfig

@@ -1,15 +1,5 @@
-config PAYLOAD_BUILD_SEABIOS
-	bool
-
 if PAYLOAD_SEABIOS
 
-config PAYLOAD_FILE
-	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
-
-endif
-
-if PAYLOAD_BUILD_SEABIOS
-
 choice
 	prompt "SeaBIOS version"
 	default SEABIOS_STABLE
@@ -74,7 +64,6 @@ config SEABIOS_HARDWARE_IRQ
 config SEABIOS_VGA_COREBOOT
 	prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
 	default y if !VENDOR_EMULATION
-	default y if COREDOOM_SECONDARY_PAYLOAD
 	depends on !VGA_ROM_RUN && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
 	bool
 	help
@@ -125,6 +114,9 @@ config SEABIOS_SERCON_PORT_ADDR
 
 	  By default primary console UART defined by TTYS0_BASE is used.
 
+config PAYLOAD_FILE
+	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+
 config PAYLOAD_VGABIOS_FILE
 	string
 	depends on SEABIOS_VGA_COREBOOT

payloads/external/SeaBIOS/Kconfig.name

@@ -1,7 +1,6 @@
 config PAYLOAD_SEABIOS
 	bool "SeaBIOS"
 	depends on ARCH_X86
-	select PAYLOAD_BUILD_SEABIOS
 	help
 	  Select this option if you want to build a coreboot image
 	  with a SeaBIOS payload. If you don't know what this is

payloads/external/coreDOOM/Kconfig.secondary

@@ -1,25 +0,0 @@
-if COREDOOM_SECONDARY_PAYLOAD
-
-config COREDOOM_WAD_FILE
-	string "DOOM WAD file"
-	depends on COREDOOM_SECONDARY_PAYLOAD
-	default "doom.wad"
-	help
-	  Add a WAD file to be loaded by coreDOOM.
-
-	  A WAD file contains all the game data for the Doom-engine, and
-	  is required to play the game.
-
-	  A list of the WAD files included in the official games can be
-	  found here: https://doomwiki.org/wiki/IWAD
-	  These WADs can be extracted from copies of the game that you
-	  own, and the shareware WADs may be freely downloaded from the
-	  internet.
-
-	  For a completely free (as in freedom) experience, the Freedoom
-	  project (https://freedoom.github.io) provides original game
-	  content under the BSD license. Other WADs not mentioned here are
-	  also available and may be found from various sources such as
-	  the internet and copies of other games using the Doom engine.
-
-endif

payloads/external/coreDOOM/Makefile

@@ -1,34 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-project_git_repo=https://github.com/nic3-14159/coreDOOM.git
-project_dir=coredoom
-
-unexport KCONFIG_AUTOHEADER
-unexport KCONFIG_AUTOCONFIG
-unexport KCONFIG_DEPENDENCIES
-unexport KCONFIG_SPLITCONFIG
-unexport KCONFIG_TRISTATE
-unexport KCONFIG_NEGATIVES
-
-all: coredoom
-
-checkout:
-	test -d coredoom || \
-	    git clone $(project_git_repo) $(project_dir)
-	cd $(project_dir) && \
-	    git checkout libpayload_port
-
-coredoom: libpayload
-	$(MAKE) -C $(project_dir)/doomgeneric
-
-libpayload: checkout
-	cp libpayload-config ../../libpayload/.config && \
-	    cd ../../libpayload && $(MAKE) olddefconfig && $(MAKE) && \
-	    $(MAKE) DESTDIR=../external/coreDOOM/coredoom/doomgeneric install
-
-clean:
-	test -d coredoom && $(MAKE) -C coredoom/doomgeneric clean || exit 0
-
-distclean:
-	rm -rf coredoom
-
-.PHONY: checkout coredoom clean distclean

payloads/external/coreDOOM/libpayload-config

@@ -1,13 +0,0 @@
-# CONFIG_LP_MULTIBOOT is not set
-CONFIG_LP_HEAP_SIZE=67108864
-CONFIG_LP_STACK_SIZE=16384
-CONFIG_LP_BASE_ADDRESS=0x00100000
-# CONFIG_LP_CURSES is not set
-CONFIG_LP_SERIAL_IOBASE=0x3f8
-CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y
-# CONFIG_LP_PCI is not set
-# CONFIG_LP_NVRAM is not set
-CONFIG_LP_TIMER_GENERIC_REG=0x0
-CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0
-# CONFIG_LP_STORAGE is not set
-# CONFIG_LP_USB_MSC is not set

payloads/external/tianocore/Makefile

@@ -100,7 +100,7 @@ update: $(project_dir)
 			echo "    $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \
 			exit 1; \
 		fi; \
-		if git status --ignore-submodules=dirty | grep -q clean; then \
+		if git status --ignore-submodules=dirty | grep -qv clean; then \
 			echo "    Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \
 			git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \
 		else \

payloads/libpayload/Kconfig

@@ -404,19 +404,8 @@ menu "Drivers"
 
 config PCI
 	bool "Support for PCI devices"
-	default y if ARCH_X86
-	default n
-
-config PCI_IO_OPS
-	bool "Support for PCI devices with port IO"
-	depends on PCI && IO_ADDRESS_SPACE
-	default y if ARCH_X86
-	default n
-
-config PCIE_MEDIATEK
-	bool "Support for PCIe devices on MediaTek platforms"
-	depends on PCI && !PCI_IO_OPS
-	default n
+	depends on ARCH_X86 # for now
+	default y
 
 config NVRAM
 	bool "Support for reading/writing NVRAM bytes"

payloads/libpayload/drivers/Makefile.inc

@@ -28,15 +28,7 @@
 ## SUCH DAMAGE.
 ##
 
-libc-$(CONFIG_LP_PCI) += pci_ops.c
-
-ifeq ($(CONFIG_LP_PCI_IO_OPS),y)
-libc-$(CONFIG_LP_PCI) += pci_io_ops.c
-else
-libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c
-endif
-
-libc-$(CONFIG_LP_PCIE_MEDIATEK) += pcie_mediatek.c
+libc-$(CONFIG_LP_PCI) += pci.c
 
 libc-$(CONFIG_LP_SPEAKER) += speaker.c
 

payloads/libpayload/drivers/pci.c

@@ -30,6 +30,42 @@
 #include <libpayload.h>
 #include <pci.h>
 
+u8 pci_read_config8(pcidev_t device, u16 reg)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	return inb(0xCFC + (reg & 3));
+}
+
+u16 pci_read_config16(pcidev_t device, u16 reg)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	return inw(0xCFC + (reg & 3));
+}
+
+u32 pci_read_config32(pcidev_t device, u16 reg)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	return inl(0xCFC + (reg & 3));
+}
+
+void pci_write_config8(pcidev_t device, u16 reg, u8 val)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	outb(val, 0xCFC + (reg & 3));
+}
+
+void pci_write_config16(pcidev_t device, u16 reg, u16 val)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	outw(val, 0xCFC + (reg & 3));
+}
+
+void pci_write_config32(pcidev_t device, u16 reg, u32 val)
+{
+	outl(device | (reg & ~3), 0xCF8);
+	outl(val, 0xCFC + (reg & 3));
+}
+
 static int find_on_bus(int bus, unsigned short vid, unsigned short did,
 		       pcidev_t * dev)
 {

payloads/libpayload/drivers/pci_io_ops.c

@@ -1,67 +0,0 @@
-/*
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2008 coresystems GmbH
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <libpayload.h>
-#include <pci.h>
-
-u8 pci_read_config8(pcidev_t dev, u16 reg)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	return inb(0xCFC + (reg & 3));
-}
-
-u16 pci_read_config16(pcidev_t dev, u16 reg)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	return inw(0xCFC + (reg & 3));
-}
-
-u32 pci_read_config32(pcidev_t dev, u16 reg)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	return inl(0xCFC + (reg & 3));
-}
-
-void pci_write_config8(pcidev_t dev, u16 reg, u8 val)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	outb(val, 0xCFC + (reg & 3));
-}
-
-void pci_write_config16(pcidev_t dev, u16 reg, u16 val)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	outw(val, 0xCFC + (reg & 3));
-}
-
-void pci_write_config32(pcidev_t dev, u16 reg, u32 val)
-{
-	outl(dev | (reg & ~3), 0xCF8);
-	outl(val, 0xCFC + (reg & 3));
-}

payloads/libpayload/drivers/pci_map_bus_ops.c

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <libpayload.h>
-#include <pci.h>
-
-u8 pci_read_config8(pcidev_t dev, u16 reg)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	return read8((void *)(cfg_base | reg));
-}
-
-u16 pci_read_config16(pcidev_t dev, u16 reg)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	return read16((void *)(cfg_base | (reg & ~1)));
-}
-
-u32 pci_read_config32(pcidev_t dev, u16 reg)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	return read32((void *)(cfg_base | (reg & ~3)));
-}
-
-void pci_write_config8(pcidev_t dev, u16 reg, u8 val)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	write8((void *)(cfg_base | reg), val);
-}
-
-void pci_write_config16(pcidev_t dev, u16 reg, u16 val)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	write16((void *)(cfg_base | (reg & ~1)), val);
-}
-
-void pci_write_config32(pcidev_t dev, u16 reg, u32 val)
-{
-	uintptr_t cfg_base = pci_map_bus(dev);
-
-	write32((void *)(cfg_base | (reg & ~3)), val);
-}

payloads/libpayload/drivers/pcie_mediatek.c

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <libpayload.h>
-#include <pci.h>
-
-#define PCIE_CFGNUM_REG			0x140
-#define PCIE_CFG_DEVFN(devfn)		((devfn) & GENMASK(7, 0))
-#define PCIE_CFG_BUS(bus)		(((bus) << 8) & GENMASK(15, 8))
-#define PCIE_CFG_OFFSET_ADDR		0x1000
-#define PCIE_CFG_HEADER(bus, devfn) \
-	(PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
-
-uintptr_t pci_map_bus(pcidev_t dev)
-{
-	u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
-	u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn);
-	write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val);
-
-	return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR;
-}

payloads/libpayload/drivers/storage/nvme.c

@@ -147,7 +147,7 @@ static void nvme_detach_device(struct storage_dev *dev)
 	if (delete_admin_queues(nvme))
 		printf("NVME ERROR: Failed to delete admin queues\n");
 
-	write32(nvme->config + 0x14, 0);
+	write32(nvme->config + 0x1c, 0);
 
 	int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
 	do {
@@ -321,7 +321,7 @@ static void nvme_init(pcidev_t dev)
 
 	void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff);
 
-	if (!(read64(pci_bar0) >> 37 & 0x01)) {
+	if (!(((read64(pci_bar0) >> 37) & 0xff) == 0x01)) {
 		printf("NVMe ERROR: PCIe device does not support the NVMe command set\n");
 		return;
 	}
@@ -341,39 +341,39 @@ static void nvme_init(pcidev_t dev)
 
 	if (!nvme->prp_list) {
 		printf("NVMe ERROR: Failed to allocate buffer for PRP list\n");
-		goto _free_abort;
+		goto abort;
 	}
 
 	const uint32_t cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS | NVME_CC_SHN
 			| NVME_CC_IOSQES | NVME_CC_IOCQES;
 
-	write32(nvme->config + 0x14, 0);
+	write32(nvme->config + 0x1c, 0);
 
 	int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
 	do {
 		status = read32(nvme->config + 0x1c) & 0x3;
 		if (status == 0x2) {
 			printf("NVMe ERROR: Failed to disable controller. FATAL ERROR\n");
-			goto _free_abort;
+			goto abort;
 		}
 		if (timeout < 0) {
 			printf("NVMe ERROR: Failed to disable controller. Timeout.\n");
-			goto _free_abort;
+			goto abort;
 		}
 		timeout -= 10;
 		mdelay(10);
 	} while (status != 0x0);
 	if (create_admin_queues(nvme))
-		goto _free_abort;
+		goto abort;
 	write32(nvme->config + 0x14, cc);
 
 	timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
 	do {
 		status = read32(nvme->config + 0x1c) & 0x3;
 		if (status == 0x2)
-			goto _delete_admin_abort;
+			goto abort;
 		if (timeout < 0)
-			goto _delete_admin_abort;
+			goto abort;
 		timeout -= 10;
 		mdelay(10);
 	} while (status != 0x1);
@@ -381,21 +381,20 @@ static void nvme_init(pcidev_t dev)
 	uint16_t command = pci_read_config16(dev, PCI_COMMAND);
 	pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
 	if (create_io_completion_queue(nvme))
-		goto _delete_admin_abort;
+		goto abort;
 	if (create_io_submission_queue(nvme))
-		goto _delete_completion_abort;
+		goto abort;
 	storage_attach_device((storage_dev_t *)nvme);
 	printf("NVMe init done.\n");
 	return;
 
-_delete_completion_abort:
+abort:
+	printf("NVMe init failed.\n");
+	delete_io_submission_queue(nvme);
 	delete_io_completion_queue(nvme);
-_delete_admin_abort:
 	delete_admin_queues(nvme);
-_free_abort:
 	free(nvme->prp_list);
 	free(nvme);
-	printf("NVMe init failed.\n");
 }
 
 void nvme_initialize(struct pci_dev *dev)

payloads/libpayload/include/arm/arch/barrier.h

@@ -33,7 +33,7 @@
  *
  */
 
-#ifndef __ARCH_BARRIER_H__
+#ifndef __ARCH_BARRIER_H_
 #define __ARCH_BARRIER_H__
 
 #include <arch/cache.h>

payloads/libpayload/include/arm64/arch/barrier.h

@@ -33,7 +33,7 @@
  *
  */
 
-#ifndef __ARCH_BARRIER_H__
+#ifndef __ARCH_BARRIER_H_
 #define __ARCH_BARRIER_H__
 
 #include <arch/cache.h>

payloads/libpayload/include/coreboot_tables.h

@@ -84,7 +84,6 @@ enum {
 	CB_TAG_ACPI_CNVS		= 0x0041,
 	CB_TAG_TYPE_C_INFO		= 0x0042,
 	CB_TAG_ACPI_RSDP                = 0x0043,
-	CB_TAG_PCIE			= 0x0044,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -266,12 +265,6 @@ struct cb_gpios {
 	struct cb_gpio gpios[0];
 };
 
-struct cb_pcie {
-	uint32_t tag;
-	uint32_t size;
-	cb_uint64_t ctrl_base;	/* Base address of PCIe controller */
-};
-
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;

payloads/libpayload/include/pci.h

@@ -31,8 +31,6 @@
 #define _PCI_H
 
 #include <arch/types.h>
-#include <stdint.h>
-
 typedef u32 pcidev_t;
 
 /* Device config space registers. */
@@ -102,15 +100,13 @@ typedef u32 pcidev_t;
 #define PCI_SLOT(_d) ((_d >> 11) & 0x1f)
 #define PCI_FUNC(_d) ((_d >> 8) & 0x7)
 
-uintptr_t pci_map_bus(pcidev_t dev);
+u8 pci_read_config8(u32 device, u16 reg);
+u16 pci_read_config16(u32 device, u16 reg);
+u32 pci_read_config32(u32 device, u16 reg);
 
-u8 pci_read_config8(pcidev_t dev, u16 reg);
-u16 pci_read_config16(pcidev_t dev, u16 reg);
-u32 pci_read_config32(pcidev_t dev, u16 reg);
-
-void pci_write_config8(pcidev_t dev, u16 reg, u8 val);
-void pci_write_config16(pcidev_t dev, u16 reg, u16 val);
-void pci_write_config32(pcidev_t dev, u16 reg, u32 val);
+void pci_write_config8(u32 device, u16 reg, u8 val);
+void pci_write_config16(u32 device, u16 reg, u16 val);
+void pci_write_config32(u32 device, u16 reg, u32 val);
 
 int pci_find_device(u16 vid, u16 did, pcidev_t *dev);
 u32 pci_read_resource(pcidev_t dev, int bar);

payloads/libpayload/include/sysinfo.h

@@ -84,7 +84,6 @@ struct sysinfo_t {
 	uintptr_t linker;
 	uintptr_t assembler;
 	uintptr_t mem_chip_base;
-	uintptr_t pcie_ctrl_base; /* Base address of PCIe controller */
 
 	uintptr_t cb_version;
 

payloads/libpayload/include/x86/arch/barrier.h

@@ -27,7 +27,7 @@
  *
  */
 
-#ifndef __ARCH_BARRIER_H__
+#ifndef __ARCH_BARRIER_H_
 #define __ARCH_BARRIER_H__
 
 #define mb()

payloads/libpayload/libc/coreboot.c

@@ -264,13 +264,6 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	}
 }
 
-static void cb_parse_pcie(void *ptr, struct sysinfo_t *info)
-{
-	const struct cb_pcie *pcie = ptr;
-
-	info->pcie_ctrl_base = pcie->ctrl_base;
-}
-
 static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
 {
 	const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr;
@@ -420,9 +413,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_ACPI_RSDP:
 			cb_parse_rsdp(ptr, info);
 			break;
-		case CB_TAG_PCIE:
-			cb_parse_pcie(ptr, info);
-			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;

payloads/nvramcui/nvramcui.c

@@ -49,19 +49,22 @@ static void render_form(FORM *form)
 	wclear(der);
 	wrefresh(der);
 	delwin(der);
-	copywin(inner_w, w, line, 0, 1, 1, min(numlines, getmaxy(inner_w) - line), 68, 0);
+	copywin(inner_w, w, line, 0, 1, 1,
+		min(numlines, getmaxy(inner_w) - line), 68, 0);
 	wmove(w, y + 1 - line, x + 1);
 	wrefresh(w);
 }
 
 /* determine number of options, and maximum option name length */
-static int count_cmos_options(struct cb_cmos_entries *option, int *numopts, int *maxlength)
+static int count_cmos_options(struct cb_cmos_entries *option, int *numopts,
+		int *maxlength)
 {
 	int n_opts = 0;
 	int max_l = 0;
 
 	while (option) {
-		if ((option->config != 'r') && (strcmp("check_sum", (char *)option->name) != 0)) {
+		if ((option->config != 'r') &&
+		    (strcmp("check_sum", (char *)option->name) != 0)) {
 			max_l = max(max_l, strlen((char *)option->name));
 			n_opts++;
 		}
@@ -78,11 +81,12 @@ static int count_cmos_options(struct cb_cmos_entries *option, int *numopts, int
 	*maxlength = max_l;
 
 	return 0;
+
 }
 
 /* walk over options, fetch details */
-static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **fields, int numopts,
-			      int maxlength)
+static void cmos_walk_options(struct cb_cmos_option_table *opttbl,
+		FIELD **fields, int numopts, int maxlength)
 {
 	struct cb_cmos_entries *option = first_cmos_entry(opttbl);
 	int i;
@@ -92,13 +96,16 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **field
 		       (strcmp("check_sum", (char *)option->name) == 0)) {
 			option = next_cmos_entry(option);
 		}
-		fields[2 * i] = new_field(1, strlen((char *)option->name), i * 2, 1, 0, 0);
+		fields[2 * i] =
+		    new_field(1, strlen((char *)option->name), i * 2, 1, 0, 0);
 		set_field_buffer(fields[2 * i], 0, (char *)option->name);
 		field_opts_off(fields[2 * i], O_ACTIVE);
 
-		fields[2 * i + 1] = new_field(1, 40, i * 2, maxlength + 2, 0, 0);
+		fields[2 * i + 1] =
+		    new_field(1, 40, i * 2, maxlength + 2, 0, 0);
 		char *buf = NULL;
-		int fail = get_option_as_string(use_nvram, opttbl, &buf, (char *)option->name);
+		int fail =
+		    get_option_as_string(use_nvram, opttbl, &buf, (char *)option->name);
 		switch (option->config) {
 		case 'h': {
 			set_field_type(fields[2 * i + 1], TYPE_INTEGER, 0, 0,
@@ -123,7 +130,8 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **field
 
 			while (cmos_enum) {
 				numvals++;
-				cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id);
+				cmos_enum = next_cmos_enum_of_id(
+				    cmos_enum, option->config_id);
 			}
 
 			char **values = malloc(sizeof(char *) * (numvals + 1));
@@ -134,11 +142,13 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **field
 			while (cmos_enum) {
 				values[cnt] = (char *)cmos_enum->text;
 				cnt++;
-				cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id);
+				cmos_enum = next_cmos_enum_of_id(
+				    cmos_enum, option->config_id);
 			}
 			values[cnt] = NULL;
 			field_opts_off(fields[2 * i + 1], O_EDIT);
-			set_field_type(fields[2 * i + 1], TYPE_ENUM, values, 1, 1);
+			set_field_type(fields[2 * i + 1], TYPE_ENUM, values, 1,
+				       1);
 			free(values); // copied by set_field_type
 			break;
 		}
@@ -151,7 +161,8 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **field
 		// underline is non-trivial on VGA text
 		set_field_back(fields[2 * i + 1], A_UNDERLINE);
 #endif
-		field_opts_off(fields[2 * i + 1], O_BLANK | O_AUTOSKIP | O_NULLOK);
+		field_opts_off(fields[2 * i + 1],
+			       O_BLANK | O_AUTOSKIP | O_NULLOK);
 
 		option = next_cmos_entry(option);
 	}

spd/lp5/memory_parts.json

@@ -59,26 +59,6 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 6400
             }
-        },
-        {
-            "name": "K3LKLKL0EM-MGCN",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 5500
-            }
-        },
-        {
-            "name": "H58G56AK6BX069",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 6400
-            }
         }
     ]
 }

spd/lp5/set-0/parts_spd_manifest.generated.txt

@@ -7,5 +7,3 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex
 K3LKBKB0BM-MGCP,spd-3.hex
 H9JCNNNBK3MLYR-N6E,spd-1.hex
 MT62F2G32D8DR-031 WT:B,spd-4.hex
-K3LKLKL0EM-MGCN,spd-5.hex
-H58G56AK6BX069,spd-3.hex

spd/lp5/set-1/parts_spd_manifest.generated.txt

@@ -7,5 +7,3 @@ H9JCNNNCP3MLYR-N6E,spd-2.hex
 K3LKBKB0BM-MGCP,spd-3.hex
 H9JCNNNBK3MLYR-N6E,spd-1.hex
 MT62F2G32D8DR-031 WT:B,spd-4.hex
-K3LKLKL0EM-MGCN,spd-5.hex
-H58G56AK6BX069,spd-3.hex

spd/lp5/set-1/spd-5.hex

@@ -1,32 +0,0 @@
-23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
-00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0
-03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/Kconfig

@@ -70,37 +70,25 @@ config COMPILER_GCC
 	  For details see http://gcc.gnu.org.
 
 config COMPILER_LLVM_CLANG
-	bool "LLVM/clang"
-	depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG
+	bool "LLVM/clang (TESTING ONLY - Not currently working)"
 	help
 	  Use LLVM/clang to build coreboot.  To use this, you must build the
 	  coreboot version of the clang compiler.  Run the command
 	    make clang
-	  Note that Clang is not currently working on all architectures.
+	  Note that this option is not currently working correctly and should
+	  really only be selected if you're trying to work on getting clang
+	  operational.
 
 	  For details see http://clang.llvm.org.
 
 endchoice
 
-config ARCH_SUPPORTS_CLANG
-	bool
-	help
-	  Opt-in flag for architectures that generally work well with CLANG.
-	  By default the option would be hidden.
-
-config ALLOW_EXPERIMENTAL_CLANG
-	bool "Allow experimental LLVM/Clang"
-	depends on !ARCH_SUPPORTS_CLANG
-	help
-	  On some architectures CLANG does not work that well.
-	  Use this only to try to get CLANG working.
-
 config ANY_TOOLCHAIN
 	bool "Allow building with any toolchain"
 	default n
 	help
 	  Many toolchains break when building coreboot since it uses quite
-	  unusual linker features. Unless developers explicitly request it,
+	  unusual linker features. Unless developers explicitely request it,
 	  we'll have to assume that they use their distro compiler by mistake.
 	  Make sure that using patched compilers is a conscious decision.
 
@@ -324,7 +312,6 @@ config ASAN
 	default n
 	select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
 	select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
-	depends on COMPILER_GCC
 	help
 	  Enable address sanitizer - runtime memory debugger,
 	  designed to find out-of-bounds accesses and use-after-scope bugs.
@@ -647,7 +634,7 @@ config HEAP_SIZE
 
 config STACK_SIZE
 	hex
-	default 0x2000 if ARCH_X86
+	default 0x1000 if ARCH_X86
 	default 0x0
 
 config MAX_CPUS
@@ -1340,12 +1327,6 @@ config BOOTBLOCK_CUSTOM
 	# src/lib/bootblock.c#main() C entry point.
 	bool
 
-config BOOTBLOCK_IN_CBFS
-	bool
-	default y if ARCH_X86
-	help
-	  Select this on platforms that have a top aligned bootblock inside cbfs.
-
 config MEMLAYOUT_LD_FILE
 	string
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"

src/acpi/acpigen_usb.c

@@ -106,7 +106,6 @@ static void add_device_references(struct acpi_dp *dsd,
 	add_device_ref(dsd, "orientation-switch", config->orientation_switch);
 	add_device_ref(dsd, "usb-role-switch", config->usb_role_switch);
 	add_device_ref(dsd, "mode-switch", config->mode_switch);
-	add_device_ref(dsd, "retimer-switch", config->retimer_switch);
 }
 
 void acpigen_write_typec_connector(const struct typec_connector_class_config *config,

src/arch/arm/boot.c

@@ -13,7 +13,7 @@ void arch_prog_run(struct prog *prog)
 	cache_sync_instructions();
 
 	switch (prog_cbfs_type(prog)) {
-	case CBFS_TYPE_FIT_PAYLOAD:
+	case CBFS_TYPE_FIT:
 		/*
 		 * We only load Linux payloads from the ramstage, so provide a hint to
 		 * the linker that the below functions do not need to be included in

src/arch/arm/include/arch/boot/boot.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ASM_ARM_BOOT_H
+#define ASM_ARM_BOOT_H
+
+#define ELF_CLASS	ELFCLASS32
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_ARM
+
+#endif /* ASM_ARM_BOOT_H */

src/arch/arm64/include/arch/boot/boot.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ASM_ARM64_BOOT_H
+#define ASM_ARM64_BOOT_H
+
+#define ELF_CLASS	ELFCLASS64
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_AARCH64
+
+#endif /* ASM_ARM64_BOOT_H */

src/arch/riscv/boot.c

@@ -27,7 +27,7 @@ static void do_arch_prog_run(struct arch_prog_run_args *args)
 	struct prog *prog = args->prog;
 	void *fdt = HLS()->fdt;
 
-	if (prog_cbfs_type(prog) == CBFS_TYPE_FIT_PAYLOAD)
+	if (prog_cbfs_type(prog) == CBFS_TYPE_FIT)
 		fdt = prog_entry_arg(prog);
 
 	if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {

src/arch/riscv/include/arch/barrier.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-#ifndef __ARCH_BARRIER_H__
+#ifndef __ARCH_BARRIER_H_
 #define __ARCH_BARRIER_H__
 
 static inline void mb(void)  { asm volatile("fence"); }

src/arch/x86/Kconfig

@@ -33,7 +33,6 @@ config ARCH_ALL_STAGES_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
-	select ARCH_SUPPORTS_CLANG
 
 # stage selectors for x64
 
@@ -321,38 +320,6 @@ config MEMLAYOUT_LD_FILE
 	string
 	default "src/arch/x86/memlayout.ld"
 
-config DEBUG_HW_BREAKPOINTS
-	bool
-	default y
-	help
-	  Enable support for hardware data and instruction breakpoints through
-	  the x86 debug registers
-
-config DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES
-	bool
-	default y
-	depends on DEBUG_HW_BREAKPOINTS && IDT_IN_EVERY_STAGE
-
-config DEBUG_NULL_DEREF_BREAKPOINTS
-	bool
-	default y
-	depends on DEBUG_HW_BREAKPOINTS
-	help
-	  Enable support for catching null dereferences and instruction execution
-
-config DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES
-	bool
-	default y
-	depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES
-
-config DEBUG_NULL_DEREF_HALT
-	bool
-	default n
-	depends on DEBUG_NULL_DEREF_BREAKPOINTS
-	help
-	  When enabled null dereferences and instruction fetches will halt execution.
-	  Otherwise an error will be printed.
-
 # Some EC need an "EC firmware pointer" (a data structure hinting the address
 # of its firmware blobs) being put at a fixed position. Its space
 # (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a

src/arch/x86/Makefile.inc

@@ -78,7 +78,6 @@ endef
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y)
 
 bootblock-y += boot.c
-bootblock-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 bootblock-y += post.c
 bootblock-y += cpu_common.c
 bootblock-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
@@ -88,7 +87,6 @@ bootblock-y += memset.c
 bootblock-y += memmove.c
 bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-bootblock-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
 bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
 bootblock-y += gdt_init.S
 bootblock-y += id.S
@@ -102,13 +100,6 @@ else
 $(eval $(call early_x86_stage,bootblock,elf64-x86-64))
 endif
 
-ifeq ($(CONFIG_BOOTBLOCK_IN_CBFS),y)
-add_bootblock = \
-	$(CBFSTOOL) $(1) add -f $(2) -n bootblock -t bootblock $(TXTIBB) \
-	-b -$(call file-size,$(2)) \
-	$(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
-endif
-
 $(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h
 bootblock-y += walkcbfs.S
 
@@ -122,7 +113,6 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += assembly_entry.S
 verstage-y += boot.c
-verstage-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 verstage-y += post.c
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += gdt_init.S
 verstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
@@ -134,7 +124,6 @@ verstage-y += memset.c
 verstage-y += memcpy.c
 verstage-y += memmove.c
 verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-verstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
 # If verstage is a separate stage it means there's no need
 # for a chipset-specific car_stage_entry() so use the generic one
 # which just calls verstage().
@@ -160,7 +149,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
 romstage-y += assembly_entry.S
 romstage-y += boot.c
-romstage-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 romstage-y += post.c
 romstage-y += gdt_init.S
 romstage-y += cpu_common.c
@@ -170,7 +158,6 @@ romstage-y += memcpy.c
 romstage-y += memmove.c
 romstage-y += memset.c
 romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-romstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
 romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -203,7 +190,6 @@ endif
 postcar-generic-ccopts += -D__POSTCAR__
 
 postcar-y += boot.c
-postcar-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 postcar-y += post.c
 postcar-y += gdt_init.S
 postcar-y += cpu_common.c
@@ -214,7 +200,6 @@ postcar-y += memcpy.c
 postcar-y += memmove.c
 postcar-y += memset.c
 postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-postcar-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
 postcar-y += postcar.c
 postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -249,7 +234,6 @@ ramstage-y += c_start.S
 ramstage-y += c_exit.S
 ramstage-y += cpu.c
 ramstage-y += cpu_common.c
-ramstage-$(CONFIG_DEBUG_HW_BREAKPOINTS) += breakpoint.c
 ramstage-y += ebda.c
 ramstage-y += exception.c
 ramstage-y += idt.S
@@ -259,7 +243,6 @@ ramstage-y += memmove.c
 ramstage-y += memset.c
 ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
-ramstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS) += null_breakpoint.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
 ramstage-y += rdrand.c
 ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
@@ -314,13 +297,11 @@ $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstag
 
 endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
 
-smm-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
 smm-y += memcpy.c
 smm-y += memmove.c
 smm-y += memset.c
 smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-smm-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c
 
 smm-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c)

src/arch/x86/acpi/debug.asl

@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
+* 0x80: POST_BASE
 * 0x3F8: DEBCOM_BASE
+* X80: POST_REGION
+* P80: PORT80
 *
 * CREG: DEBCOM_REGION
 * CUAR: DEBCOM_UART
@@ -14,6 +17,12 @@
 * DEBUG_INIT	DINI
 */
 
+OperationRegion(X80, SystemIO, 0x80, 1)
+	Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
 OperationRegion(CREG, SystemIO, 0x3F8, 8)
 	Field(CREG, ByteAcc, NoLock, Preserve)
 {

src/arch/x86/acpi/post.asl

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#if CONFIG(POST_IO)
-
-/* POST code support, typically on port 80 */
-OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-#else
-
-/* Dummy placeholder to avoid issues */
-Name (DBG0, 0)
-
-#endif

src/arch/x86/acpi_bert_storage.c

@@ -567,16 +567,15 @@ cper_ia32x64_context_t *cper_new_ia32x64_context_msr(
 	return ctx;
 }
 
-static void bert_reserved_region(void **start, size_t *size)
+/* The region must be in memory marked as reserved.  If not implemented,
+ * skip generating the information in the region.
+ */
+__weak void bert_reserved_region(void **start, size_t *size)
 {
-	if (!CONFIG(ACPI_BERT)) {
+	printk(BIOS_ERR, "%s not implemented.  BERT region generation disabled\n",
+			__func__);
 	*start = NULL;
 	*size = 0;
-	} else {
-		*start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE);
-		*size = CONFIG_ACPI_BERT_SIZE;
-	}
-	printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size);
 }
 
 static void bert_storage_setup(void *unused)

src/arch/x86/bootblock.ld

@@ -73,14 +73,9 @@ SECTIONS {
 	_X86_RESET_VECTOR = .;
 	.reset . : {
 		*(.reset);
-		. = _X86_RESET_VECTOR_FILLING;
-		BYTE(0);
+		. = 15;
+		BYTE(0x00);
 	}
-	. = 0xfffffffc;
-	.header_pointer . : {
-		KEEP(*(.header_pointer));
-	}
-	_X86_RESET_VECTOR_FILLING = 15 - SIZEOF(.header_pointer);
 	_ebootblock = .;
 }
 

src/arch/x86/breakpoint.c

@@ -1,300 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/registers.h>
-#include <arch/breakpoint.h>
-#include <console/console.h>
-#include <stdint.h>
-#include <types.h>
-
-#define DEBUG_REGISTER_COUNT 4
-
-/* Each enable field is 2 bits and starts at bit 0 */
-#define DEBUG_CTRL_ENABLE_SHIFT(index) (2 * (index))
-#define DEBUG_CTRL_ENABLE_MASK(index) (0x3 << DEBUG_CTRL_ENABLE_SHIFT(index))
-#define DEBUG_CTRL_ENABLE(index, enable) ((enable) << DEBUG_CTRL_ENABLE_SHIFT(index))
-
-/* Each breakpoint has a length and type, each is two bits and start at bit 16 */
-#define DEBUG_CTRL_LT_SHIFT(index) (4 * (index) + 16)
-#define DEBUG_CTRL_LT_MASK(index) (0xf << DEBUG_CTRL_LT_SHIFT(index))
-#define DEBUG_CTRL_LT(index, len, type) ((((len) << 2 | (type))) << DEBUG_CTRL_LT_SHIFT(index))
-
-/* Each field is one bit, starting at bit 0 */
-#define DEBUG_STATUS_BP_HIT_MASK(index) (1 << (index))
-#define DEBUG_STATUS_GET_BP_HIT(index, value) \
-	(((value) & DEBUG_STATUS_BP_HIT_MASK(index)) >> (index))
-
-/* Breakpoint lengths values */
-#define DEBUG_CTRL_LEN_1 0x0
-#define DEBUG_CTRL_LEN_2 0x1
-#define DEBUG_CTRL_LEN_8 0x2
-#define DEBUG_CTRL_LEN_4 0x3
-
-/* Breakpoint enable values */
-#define DEBUG_CTRL_ENABLE_LOCAL 0x1
-#define DEBUG_CTRL_ENABLE_GLOBAL 0x2
-
-/* eflags/rflags bit to continue execution after hitting an instruction breakpoint */
-#define FLAGS_RESUME (1 << 16)
-
-struct breakpoint {
-	bool allocated;
-	enum breakpoint_type type;
-	breakpoint_handler handler;
-};
-
-static struct breakpoint breakpoints[DEBUG_REGISTER_COUNT];
-
-static inline bool debug_write_addr_reg(int index, uintptr_t value)
-{
-	switch (index) {
-	case 0:
-		asm("mov %0, %%dr0" ::"r"(value));
-		break;
-
-	case 1:
-		asm("mov %0, %%dr1" ::"r"(value));
-		break;
-
-	case 2:
-		asm("mov %0, %%dr2" ::"r"(value));
-		break;
-
-	case 3:
-		asm("mov %0, %%dr3" ::"r"(value));
-		break;
-
-	default:
-		return false;
-	}
-
-	return true;
-}
-
-static inline uintptr_t debug_read_status(void)
-{
-	uintptr_t ret = 0;
-
-	asm("mov %%dr6, %0" : "=r"(ret));
-	return ret;
-}
-
-static inline void debug_write_status(uintptr_t value)
-{
-	asm("mov %0, %%dr6" ::"r"(value));
-}
-
-static inline uintptr_t debug_read_control(void)
-{
-	uintptr_t ret = 0;
-
-	asm("mov %%dr7, %0" : "=r"(ret));
-	return ret;
-}
-
-static inline void debug_write_control(uintptr_t value)
-{
-	asm("mov %0, %%dr7" ::"r"(value));
-}
-
-static enum breakpoint_result allocate_breakpoint(struct breakpoint_handle *out_handle,
-						  enum breakpoint_type type)
-{
-	for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) {
-		if (breakpoints[i].allocated)
-			continue;
-
-		breakpoints[i].allocated = true;
-		breakpoints[i].handler = NULL;
-		breakpoints[i].type = type;
-		out_handle->bp = i;
-		return BREAKPOINT_RES_OK;
-	}
-
-	return BREAKPOINT_RES_NONE_AVAILABLE;
-}
-
-static enum breakpoint_result validate_handle(struct breakpoint_handle handle)
-{
-	int bp = handle.bp;
-
-	if (bp < 0 || bp >= DEBUG_REGISTER_COUNT || !breakpoints[bp].allocated)
-		return BREAKPOINT_RES_INVALID_HANDLE;
-
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_create_instruction(struct breakpoint_handle *out_handle,
-						     void *virt_addr)
-{
-	enum breakpoint_result res =
-		allocate_breakpoint(out_handle, BREAKPOINT_TYPE_INSTRUCTION);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	int bp = out_handle->bp;
-	if (!debug_write_addr_reg(bp, (uintptr_t)virt_addr))
-		return BREAKPOINT_RES_INVALID_HANDLE;
-
-	uintptr_t control = debug_read_control();
-	control &= ~DEBUG_CTRL_LT_MASK(bp);
-	control |= DEBUG_CTRL_LT(bp, DEBUG_CTRL_LEN_1, BREAKPOINT_TYPE_INSTRUCTION);
-	debug_write_control(control);
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_create_data(struct breakpoint_handle *out_handle,
-					      void *virt_addr, size_t len, bool write_only)
-{
-	uintptr_t len_value = 0;
-
-	switch (len) {
-	case 1:
-		len_value = DEBUG_CTRL_LEN_1;
-		break;
-
-	case 2:
-		len_value = DEBUG_CTRL_LEN_2;
-		break;
-
-	case 4:
-		len_value = DEBUG_CTRL_LEN_4;
-		break;
-
-	case 8:
-		/* Only supported on 64-bit CPUs */
-		if (!ENV_X86_64)
-			return BREAKPOINT_RES_INVALID_LENGTH;
-		len_value = DEBUG_CTRL_LEN_8;
-		break;
-
-	default:
-		return BREAKPOINT_RES_INVALID_LENGTH;
-	}
-
-	enum breakpoint_type type =
-		write_only ? BREAKPOINT_TYPE_DATA_WRITE : BREAKPOINT_TYPE_DATA_RW;
-	enum breakpoint_result res = allocate_breakpoint(out_handle, type);
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	int bp = out_handle->bp;
-	if (!debug_write_addr_reg(bp, (uintptr_t)virt_addr))
-		return BREAKPOINT_RES_INVALID_HANDLE;
-
-	uintptr_t control = debug_read_control();
-	control &= ~DEBUG_CTRL_LT_MASK(bp);
-	control |= DEBUG_CTRL_LT(bp, len_value, type);
-	debug_write_control(control);
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_remove(struct breakpoint_handle handle)
-{
-	enum breakpoint_result res = validate_handle(handle);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-	breakpoint_enable(handle, false);
-
-	int bp = handle.bp;
-	breakpoints[bp].allocated = false;
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_enable(struct breakpoint_handle handle, bool enabled)
-{
-	enum breakpoint_result res = validate_handle(handle);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	uintptr_t control = debug_read_control();
-	int bp = handle.bp;
-	control &= ~DEBUG_CTRL_ENABLE_MASK(bp);
-	if (enabled)
-		control |= DEBUG_CTRL_ENABLE(bp, DEBUG_CTRL_ENABLE_GLOBAL);
-	debug_write_control(control);
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_get_type(struct breakpoint_handle handle,
-					   enum breakpoint_type *type)
-{
-	enum breakpoint_result res = validate_handle(handle);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	*type = breakpoints[handle.bp].type;
-	return BREAKPOINT_RES_OK;
-}
-
-enum breakpoint_result breakpoint_set_handler(struct breakpoint_handle handle,
-					      breakpoint_handler handler)
-{
-	enum breakpoint_result res = validate_handle(handle);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	breakpoints[handle.bp].handler = handler;
-	return BREAKPOINT_RES_OK;
-}
-
-static enum breakpoint_result is_breakpoint_hit(struct breakpoint_handle handle, bool *out_hit)
-{
-	enum breakpoint_result res = validate_handle(handle);
-
-	if (res != BREAKPOINT_RES_OK)
-		return res;
-
-	uintptr_t status = debug_read_status();
-	*out_hit = DEBUG_STATUS_GET_BP_HIT(handle.bp, status);
-
-	return BREAKPOINT_RES_OK;
-}
-
-int breakpoint_dispatch_handler(struct eregs *info)
-{
-	bool instr_bp_hit = 0;
-
-	for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) {
-		struct breakpoint_handle handle = { i };
-		bool hit = false;
-		enum breakpoint_type type;
-
-		if (is_breakpoint_hit(handle, &hit) != BREAKPOINT_RES_OK || !hit)
-			continue;
-
-		if (breakpoint_get_type(handle, &type) != BREAKPOINT_RES_OK)
-			continue;
-
-		instr_bp_hit |= type == BREAKPOINT_TYPE_INSTRUCTION;
-
-		/* Call the breakpoint handler. */
-		if (breakpoints[handle.bp].handler) {
-			int ret = breakpoints[handle.bp].handler(handle, info);
-			/* A non-zero return value indicates a fatal error. */
-			if (ret)
-				return ret;
-		}
-	}
-
-	/* Clear hit breakpoints. */
-	uintptr_t status = debug_read_status();
-	for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) {
-		status &= ~DEBUG_STATUS_BP_HIT_MASK(i);
-	}
-	debug_write_status(status);
-
-	if (instr_bp_hit) {
-		/* Set the resume flag so the same breakpoint won't be hit immediately. */
-#if ENV_X86_64
-		info->rflags |= FLAGS_RESUME;
-#else
-		info->eflags |= FLAGS_RESUME;
-#endif
-	}
-
-	return 0;
-}

src/arch/x86/car.ld

@@ -115,8 +115,8 @@ _rom_mtrr_base = _rom_mtrr_mask;
 
 . = 0xffffff00;
 .illegal_globals . : {
-	*(.data)
-	*(.data.*)
+	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
+	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");

src/arch/x86/ebda.c

@@ -1,19 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi.h>
-#include <bootstate.h>
-#include <commonlib/endian.h>
 #include <stdint.h>
-
-#define X86_BDA_SIZE		0x200
-#define X86_BDA_BASE		((void *)0x400)
-#define X86_EBDA_SEGMENT	((void *)0x40e)
-#define X86_EBDA_LOWMEM		((void *)0x413)
-
-#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
-#define DEFAULT_EBDA_SEGMENT	0xF600
-#define DEFAULT_EBDA_SIZE	0x400
-
+#include <acpi/acpi.h>
+#include <arch/ebda.h>
+#include <commonlib/endian.h>
 
 static void *get_ebda_start(void)
 {
@@ -50,7 +40,7 @@ static void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 	write_le16(ebda, ebda_kb);
 }
 
-static void setup_default_ebda(void *unused)
+void setup_default_ebda(void)
 {
 	if (acpi_is_wakeup_s3())
 		return;
@@ -59,6 +49,3 @@ static void setup_default_ebda(void *unused)
 		   DEFAULT_EBDA_SEGMENT,
 		   DEFAULT_EBDA_SIZE);
 }
-
-/* Ensure EBDA is prepared before Option ROMs. */
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, setup_default_ebda, NULL);

src/arch/x86/exception.c

@@ -1,9 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+
 #include <arch/cpu.h>
-#include <arch/breakpoint.h>
-#include <arch/null_breakpoint.h>
 #include <arch/exception.h>
-#include <arch/registers.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <console/streams.h>
@@ -373,7 +371,7 @@ static void put_packet(char *buffer)
 }
 #endif /* CONFIG_GDB_STUB */
 
-#define DEBUG_VECTOR 1
+#include <arch/registers.h>
 
 void x86_exception(struct eregs *info);
 
@@ -490,11 +488,6 @@ void x86_exception(struct eregs *info)
 	int logical_processor = 0;
 	u32 apic_id = CONFIG(SMP) ? lapicid() : 0;
 
-	if (info->vector == DEBUG_VECTOR) {
-		if (breakpoint_dispatch_handler(info) == 0)
-			return;
-	}
-
 #if ENV_RAMSTAGE
 	logical_processor = cpu_index();
 #endif
@@ -664,6 +657,4 @@ asmlinkage void exception_init(void)
 	}
 
 	load_idt(idt, sizeof(idt));
-
-	null_breakpoint_init();
 }

src/arch/x86/exit_car.S

@@ -4,6 +4,37 @@
 #include <cpu/x86/cr.h>
 #include <cpu/x86/cache.h>
 
+.section ".module_parameters", "aw", @progbits
+/* stack_top indicates the stack to pull MTRR information from. */
+.global post_car_stack_top
+post_car_stack_top:
+.long	0
+.long	0
+
+#if ENV_X86_64
+.code64
+.macro pop_eax_edx
+	pop	%rax
+	mov	%rax, %rdx
+	shr	$32, %rdx
+.endm
+.macro pop_ebx_esi
+	pop	%rbx
+	mov	%rbx, %rsi
+	shr	$32, %rsi
+.endm
+#else
+.code32
+.macro pop_eax_edx
+	pop	%eax
+	pop	%edx
+.endm
+.macro pop_ebx_esi
+	pop	%ebx
+	pop	%esi
+.endm
+#endif
+
 /* Place the stack in the bss section. It's not necessary to define it in the
  * the linker script. */
 	.section .bss, "aw", @nobits
@@ -58,22 +89,107 @@ skip_clflush:
 	mov	%cr0, %rax
 	and     $(~(CR0_CD | CR0_NW)), %eax
 	mov	%rax, %cr0
+
+	/* Ensure cache is clean. */
+	invd
+
+	/* Set up new stack. */
+	movabs	post_car_stack_top, %rax
+	mov	%rax, %rsp
 #else
 	mov	%cr0, %eax
 	and	$(~(CR0_CD | CR0_NW)), %eax
 	mov	%eax, %cr0
-#endif
+
 	/* Ensure cache is clean. */
 	invd
 
+	/* Set up new stack. */
+	mov	post_car_stack_top, %esp
+#endif
+	/*
+	 * Honor variable MTRR information pushed on the stack with the
+	 * following layout:
+	 *
+	 * Offset: Value
+	 *   ...
+	 *   0x14: MTRR mask 0 63:32
+	 *   0x10: MTRR mask 0 31:0
+	 *   0x0c: MTRR base 0 63:32
+	 *   0x08: MTRR base 0 31:0
+	 *   0x04: Number of variable MTRRs to set
+	 *   0x00: Number of variable MTRRs to clear
+	 */
+
+#if CONFIG(SOC_SETS_MSRS)
+
+	mov	%esp, %ebp
+	/* Need to align stack to 16 bytes at the call instruction. Therefore
+	   account for the 1 push. */
+	andl	$0xfffffff0, %esp
+#if ENV_X86_64
+	mov	%rbp, %rdi
+#else
+	sub	$12, %esp
+	push	%ebp
+#endif
+
+	call	soc_set_mtrrs
+	/* Ignore fixing up %esp since we're setting it a new value. */
+
+	/* eax: new top_of_stack with setup_stack_and_mtrrs data removed */
+	movl	%eax, %esp
+	/* Align stack to 16 bytes at call instruction. */
+	andl	$0xfffffff0, %esp
+	call	soc_enable_mtrrs
+#else /* CONFIG_SOC_SETS_MSRS */
+	/* Clear variable MTRRs. */
+	pop_ebx_esi	/* ebx: Number to clear, esi: Number to set */
+	test	%ebx, %ebx
+	jz	2f
+	xor	%eax, %eax
+	xor	%edx, %edx
+	mov	$(MTRR_PHYS_BASE(0)), %ecx
+1:
+	wrmsr
+	inc	%ecx
+	wrmsr
+	inc	%ecx
+	dec	%ebx
+	jnz	1b
+2:
+
+	/* Set Variable MTRRs based on stack contents. */
+	test	%esi, %esi
+	jz	2f
+	mov	$(MTRR_PHYS_BASE(0)), %ecx
+1:
+	/* Write MTRR base. */
+	pop_eax_edx
+	wrmsr
+	inc	%ecx
+	/* Write MTRR mask. */
+	pop_eax_edx
+	wrmsr
+	inc	%ecx
+
+	dec	%esi
+	jnz	1b
+2:
+
+	/* Enable MTRR. */
+	mov	$(MTRR_DEF_TYPE_MSR), %ecx
+	rdmsr
+	/* Make default type uncacheable. */
+	and	$(~(MTRR_DEF_TYPE_MASK)), %eax
+	or	$(MTRR_DEF_TYPE_EN), %eax
+	wrmsr
+#endif /* CONFIG_SOC_SETS_MSRS */
+
 	movl	$_estack, %esp
 	/* Align stack to 16 bytes at call instruction. */
 	andl	$0xfffffff0, %esp
 
-	/* Call this in assembly as some platforms like to mess with the bootflow and
-	   call into main directly from chipset_teardown_car. */
-	call	postcar_mtrr_setup
-
 	/* Call into main for postcar. */
 	call main
 	/* Should never return. */

src/arch/x86/include/arch/bert_storage.h

@@ -44,6 +44,9 @@
 #define CRASHLOG_RECORD_TYPE	0x2
 #define CRASHLOG_FW_ERR_REV	0x2
 
+/* Get implementation-specific reserved area for generating BERT info */
+void bert_reserved_region(void **start, size_t *size);
+
 /* Get the region where BERT error structures have been constructed for
  * generating the ACPI table
  */

src/arch/x86/include/arch/boot/boot.h

@@ -1,7 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef X86_BOOT_H
-#define X86_BOOT_H
+#ifndef ASM_I386_BOOT_H
+#define ASM_I386_BOOT_H
+
+#define ELF_CLASS	ELFCLASS32
+#define ELF_DATA	ELFDATA2LSB
+#define ELF_ARCH	EM_386
 
 #include <types.h>
 /*
@@ -11,6 +15,7 @@
  *
  * @noreturn
  */
-void protected_mode_jump(uint32_t func_ptr, uint32_t argument);
+void protected_mode_jump(uint32_t func_ptr,
+			 uint32_t argument);
 
-#endif /* X86_BOOT_H */
+#endif /* ASM_I386_BOOT_H */

src/arch/x86/include/arch/breakpoint.h

@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _BREAKPOINT_H_
-#define _BREAKPOINT_H_
-
-#include <arch/registers.h>
-#include <types.h>
-
-#if CONFIG(DEBUG_HW_BREAKPOINTS) && \
-	(CONFIG(DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) || ENV_RAMSTAGE)
-struct breakpoint_handle {
-	int bp;
-};
-
-typedef int (*breakpoint_handler)(struct breakpoint_handle, struct eregs *info);
-
-enum breakpoint_result {
-	BREAKPOINT_RES_OK = 0,
-	BREAKPOINT_RES_NONE_AVAILABLE = -1,
-	BREAKPOINT_RES_INVALID_HANDLE = -2,
-	BREAKPOINT_RES_INVALID_LENGTH = -3
-};
-
-enum breakpoint_type {
-	BREAKPOINT_TYPE_INSTRUCTION = 0x0,
-	BREAKPOINT_TYPE_DATA_WRITE = 0x1,
-	BREAKPOINT_TYPE_IO = 0x2,
-	BREAKPOINT_TYPE_DATA_RW = 0x3,
-};
-
-/* Creates an instruction breakpoint at the given address. */
-enum breakpoint_result breakpoint_create_instruction(struct breakpoint_handle *out_handle,
-						     void *virt_addr);
-/* Creates a data breakpoint at the given address for len bytes. */
-enum breakpoint_result breakpoint_create_data(struct breakpoint_handle *out_handle,
-					      void *virt_addr, size_t len, bool write_only);
-/* Removes a given breakpoint. */
-enum breakpoint_result breakpoint_remove(struct breakpoint_handle handle);
-/* Enables or disables a given breakpoint. */
-enum breakpoint_result breakpoint_enable(struct breakpoint_handle handle, bool enabled);
-/* Returns the type of a breakpoint. */
-enum breakpoint_result breakpoint_get_type(struct breakpoint_handle handle,
-					   enum breakpoint_type *type);
-/*
- * Sets a handler function to be called when the breakpoint is hit. The handler should return 0
- * to continue or any other value to halt execution as a fatal error.
- */
-enum breakpoint_result breakpoint_set_handler(struct breakpoint_handle handle,
-					      breakpoint_handler handler);
-/* Called by x86_exception to dispatch breakpoint exceptions to the correct handler. */
-int breakpoint_dispatch_handler(struct eregs *info);
-#else
-static inline int breakpoint_dispatch_handler(struct eregs *info)
-{
-	/* Not implemented */
-	return 0;
-}
-#endif
-#endif /* _BREAKPOINT_H_ */

src/arch/x86/include/arch/ebda.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ARCH_EBDA_H
+#define __ARCH_EBDA_H
+
+#include <stddef.h>
+
+#define X86_BDA_SIZE		0x200
+#define X86_BDA_BASE		((void *)0x400)
+#define X86_EBDA_SEGMENT	((void *)0x40e)
+#define X86_EBDA_LOWMEM		((void *)0x413)
+
+#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
+#define DEFAULT_EBDA_SEGMENT	0xF600
+#define DEFAULT_EBDA_SIZE	0x400
+
+void setup_default_ebda(void);
+
+#endif

src/arch/x86/include/arch/null_breakpoint.h

@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef _NULL_BREAKPOINT_H_
-#define _NULL_BREAKPOINT_H_
-
-#if CONFIG(DEBUG_NULL_DEREF_BREAKPOINTS) && \
-    (CONFIG(DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) || ENV_RAMSTAGE)
-
-/* Places data and instructions breakpoints at address zero. */
-void null_breakpoint_init(void);
-void null_breakpoint_disable(void);
-#else
-static inline void null_breakpoint_init(void)
-{
-	/* Not implemented */
-}
-static inline void null_breakpoint_disable(void)
-{
-	/* Not implemented */
-}
-#endif
-#endif /* _NULL_BREAKPOINT_H_ */

src/arch/x86/include/arch/romstage.h

@@ -16,10 +16,18 @@ void mainboard_romstage_entry(void);
  */
 
 struct postcar_frame {
+	uintptr_t stack;
 	int skip_common_mtrr;
-	struct var_mtrr_context *mtrr;
+	struct var_mtrr_context ctx;
 };
 
+/*
+ * Initialize postcar_frame object allocating stack from cbmem,
+ * with stack_size == 0, default 4 KiB is allocated.
+ * Returns 0 on success, < 0 on error.
+ */
+int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
+
 /*
  * Add variable MTRR covering the provided range with MTRR type.
  */
@@ -43,7 +51,18 @@ void fill_postcar_frame(struct postcar_frame *pcf);
  * prepare_and_run_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use.
  */
-void prepare_and_run_postcar(void);
+void prepare_and_run_postcar(struct postcar_frame *pcf);
+
+/*
+ * Load and run a program that takes control of execution that
+ * tears down CAR and loads ramstage. The postcar_frame object
+ * indicates how to set up the frame. If caching is enabled at
+ * the time of the call it is up to the platform code to handle
+ * coherency with dirty lines in the cache using some mechanism
+ * such as platform_prog_run() because run_postcar_phase()
+ * utilizes prog_run() internally.
+ */
+void run_postcar_phase(struct postcar_frame *pcf);
 
 /*
  * Systems without a native coreboot cache-as-ram teardown may implement

src/arch/x86/include/arch/smp/mpspec.h

@@ -3,7 +3,6 @@
 #ifndef __ASM_MPSPEC_H
 #define __ASM_MPSPEC_H
 
-#include <acpi/acpi.h>
 #include <device/device.h>
 #include <cpu/x86/lapic_def.h>
 
@@ -121,6 +120,15 @@ enum mp_irq_source_types {
 	mp_ExtINT = 3
 };
 
+#define MP_IRQ_POLARITY_DEFAULT	0x0
+#define MP_IRQ_POLARITY_HIGH	0x1
+#define MP_IRQ_POLARITY_LOW	0x3
+#define MP_IRQ_POLARITY_MASK    0x3
+#define MP_IRQ_TRIGGER_DEFAULT	0x0
+#define MP_IRQ_TRIGGER_EDGE	0x4
+#define MP_IRQ_TRIGGER_LEVEL	0xc
+#define MP_IRQ_TRIGGER_MASK     0xc
+
 struct mpc_config_lintsrc {
 	u8 mpc_type;
 	u8 mpc_irqtype;

src/arch/x86/null_breakpoint.c

@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/breakpoint.h>
-#include <arch/null_breakpoint.h>
-#include <bootstate.h>
-#include <console/console.h>
-#include <stdint.h>
-
-static struct breakpoint_handle null_deref_bp;
-static struct breakpoint_handle null_fetch_bp;
-
-static int handle_fetch_breakpoint(struct breakpoint_handle handle, struct eregs *regs)
-{
-	printk(BIOS_ERR, "Instruction fetch from address zero\n");
-	return CONFIG(DEBUG_NULL_DEREF_HALT);
-}
-
-static int handle_deref_breakpoint(struct breakpoint_handle handle, struct eregs *regs)
-{
-#if ENV_X86_64
-	printk(BIOS_ERR, "Null dereference at rip: 0x%llx\n", regs->rip);
-#else
-	printk(BIOS_ERR, "Null dereference at eip: 0x%x\n", regs->eip);
-#endif
-	return CONFIG(DEBUG_NULL_DEREF_HALT);
-}
-
-static void create_deref_breakpoint(void)
-{
-	enum breakpoint_result res =
-		breakpoint_create_data(&null_deref_bp, NULL, sizeof(uintptr_t), false);
-
-	if (res != BREAKPOINT_RES_OK) {
-		printk(BIOS_ERR, "Failed to create NULL dereference breakpoint\n");
-		return;
-	}
-
-	breakpoint_set_handler(null_deref_bp, &handle_deref_breakpoint);
-	breakpoint_enable(null_deref_bp, true);
-}
-
-static void create_instruction_breakpoint(void)
-{
-	enum breakpoint_result res = breakpoint_create_instruction(&null_fetch_bp, NULL);
-
-	if (res != BREAKPOINT_RES_OK) {
-		printk(BIOS_ERR, "Failed to create address zero instruction fetch breakpoint\n");
-		return;
-	}
-
-	breakpoint_set_handler(null_fetch_bp, &handle_fetch_breakpoint);
-	breakpoint_enable(null_fetch_bp, true);
-}
-
-void null_breakpoint_init(void)
-{
-	create_deref_breakpoint();
-	create_instruction_breakpoint();
-}
-
-void null_breakpoint_disable(void)
-{
-	breakpoint_remove(null_fetch_bp);
-	breakpoint_remove(null_deref_bp);
-}
-
-static void null_breakpoint_disable_hook(void *unused)
-{
-	null_breakpoint_disable();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL);
-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL);

src/arch/x86/postcar_loader.c

@@ -13,34 +13,65 @@
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
 
-static size_t var_mtrr_ctx_size(void)
+static inline void stack_push(struct postcar_frame *pcf, uint32_t val)
 {
-	int mtrr_count = get_var_mtrr_count();
-	return sizeof(struct var_mtrr_context) + mtrr_count * 2 * sizeof(msr_t);
+	uint32_t *ptr;
+
+	pcf->stack -= sizeof(val);
+	ptr = (void *)pcf->stack;
+	*ptr = val;
 }
 
-static int postcar_frame_init(struct postcar_frame *pcf)
+static void postcar_frame_prepare(struct postcar_frame *pcf)
 {
-	memset(pcf, 0, sizeof(*pcf));
+	var_mtrr_context_init(&pcf->ctx, pcf);
+}
 
-	struct var_mtrr_context *ctx;
+int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
+{
+	void *stack;
 
-	ctx = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, var_mtrr_ctx_size());
-	if (ctx == NULL) {
-		printk(BIOS_ERR, "Couldn't add var_mtrr_ctx setup in cbmem.\n");
+	/*
+	 * Use default postcar stack size of 4 KiB. This value should
+	 * not be decreased, because if mainboards use vboot, 1 KiB will
+	 * not be enough anymore.
+	 */
+
+	if (stack_size == 0)
+		stack_size = 4 * KiB;
+
+	stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size);
+	if (stack == NULL) {
+		printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n",
+			stack_size);
 		return -1;
 	}
 
-	pcf->mtrr = ctx;
-	var_mtrr_context_init(pcf->mtrr);
-
+	postcar_frame_prepare(pcf);
+	pcf->stack = (uintptr_t)stack;
+	pcf->stack += stack_size;
 	return 0;
 }
 
+static void postcar_var_mtrr_set(const struct var_mtrr_context *ctx,
+				uintptr_t addr, size_t size,
+				msr_t base, msr_t mask)
+{
+	struct postcar_frame *pcf = ctx->arg;
+
+	printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %zx)\n",
+			addr, addr + size - 1, size);
+
+	stack_push(pcf, mask.hi);
+	stack_push(pcf, mask.lo);
+	stack_push(pcf, base.hi);
+	stack_push(pcf, base.lo);
+}
+
 void postcar_frame_add_mtrr(struct postcar_frame *pcf,
 				uintptr_t addr, size_t size, int type)
 {
-	var_mtrr_set(pcf->mtrr, addr, size, type);
+	var_mtrr_set_with_cb(&pcf->ctx, addr, size, type, postcar_var_mtrr_set);
 }
 
 void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
@@ -59,34 +90,40 @@ static void postcar_frame_common_mtrrs(struct postcar_frame *pcf)
 	postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
 }
 
-static void run_postcar_phase(struct postcar_frame *pcf);
-
 /* prepare_and_run_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
-void prepare_and_run_postcar(void)
+void prepare_and_run_postcar(struct postcar_frame *pcf)
 {
-	struct postcar_frame pcf;
-
-	if (postcar_frame_init(&pcf))
+	if (postcar_frame_init(pcf, 0))
 		die("Unable to initialize postcar frame.\n");
 
-	fill_postcar_frame(&pcf);
+	fill_postcar_frame(pcf);
 
-	postcar_frame_common_mtrrs(&pcf);
+	postcar_frame_common_mtrrs(pcf);
 
-	run_postcar_phase(&pcf);
+	run_postcar_phase(pcf);
 	/* We do not return here. */
 }
 
-static void finalize_load(uintptr_t *reloc_params, uintptr_t mtrr_frame_ptr)
+static void postcar_commit_mtrrs(struct postcar_frame *pcf)
 {
-	*reloc_params = mtrr_frame_ptr;
+	/*
+	 * Place the number of used variable MTRRs on stack then max number
+	 * of variable MTRRs supported in the system.
+	 */
+	stack_push(pcf, pcf->ctx.used_var_mtrrs);
+	stack_push(pcf, pcf->ctx.max_var_mtrrs);
+}
+
+static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top)
+{
+	*stack_top_ptr = stack_top;
 	/*
 	 * Signal to rest of system that another update was made to the
 	 * postcar program prior to running it.
 	 */
-	prog_segment_loaded((uintptr_t)reloc_params, sizeof(uintptr_t), SEG_FINAL);
-	prog_segment_loaded((uintptr_t)mtrr_frame_ptr, var_mtrr_ctx_size(), SEG_FINAL);
+	prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t),
+		SEG_FINAL);
 }
 
 static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
@@ -107,7 +144,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
 		die_with_post_code(POST_INVALID_ROM,
 				   "No parameters found in after CAR program.\n");
 
-	finalize_load(rsl.params, (uintptr_t)pcf->mtrr);
+	finalize_load(rsl.params, pcf->stack);
 
 	stage_cache_add(STAGE_POSTCAR, prog);
 }
@@ -135,17 +172,19 @@ static void postcar_cache_invalid(void)
 	board_reset();
 }
 
-static void run_postcar_phase(struct postcar_frame *pcf)
+void run_postcar_phase(struct postcar_frame *pcf)
 {
 	struct prog prog =
 		PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar");
 
+	postcar_commit_mtrrs(pcf);
+
 	if (resume_from_stage_cache()) {
 		stage_cache_load_stage(STAGE_POSTCAR, &prog);
 		/* This is here to allow platforms to pass different stack
 		   parameters between S3 resume and normal boot. On the
 		   platforms where the values are the same it's a nop. */
-		finalize_load(prog.arg, (uintptr_t)pcf->mtrr);
+		finalize_load(prog.arg, pcf->stack);
 
 		if (prog_entry(&prog) == NULL)
 			postcar_cache_invalid();

src/arch/x86/smbios.c

@@ -516,8 +516,6 @@ static int smbios_write_type3(unsigned long *current, int handle)
 	return len;
 }
 
-#define MAX_CPUS_ENABLED (CONFIG_MAX_CPUS > 0xff ? 0xff : CONFIG_MAX_CPUS)
-
 static int smbios_write_type4(unsigned long *current, int handle)
 {
 	unsigned int cpu_voltage;
@@ -572,7 +570,7 @@ static int smbios_write_type4(unsigned long *current, int handle)
 		t->thread_count = t->thread_count2;
 	}
 	/* Assume we enable all the cores always, capped only by MAX_CPUS */
-	t->core_enabled = MIN(t->core_count, MAX_CPUS_ENABLED);
+	t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS);
 	t->core_enabled2 = MIN(t->core_count2, CONFIG_MAX_CPUS);
 	t->l1_cache_handle = 0xffff;
 	t->l2_cache_handle = 0xffff;

src/arch/x86/tables.c

@@ -142,7 +142,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 {
 	unsigned long high_table_pointer;
 
-#define MAX_SMBIOS_SIZE (32 * KiB)
+#define MAX_SMBIOS_SIZE (4 * KiB)
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS,
 		MAX_SMBIOS_SIZE);

src/commonlib/bsd/include/commonlib/bsd/cb_err.h

@@ -16,7 +16,6 @@ enum cb_err {
 	CB_SUCCESS = 0,		/**< Call completed successfully */
 	CB_ERR = -1,		/**< Generic error code */
 	CB_ERR_ARG = -2,	/**< Invalid argument */
-	CB_ERR_NOT_IMPLEMENTED = -3,	/**< Function not implemented */
 
 	/* NVRAM/CMOS errors */
 	CB_CMOS_OTABLE_DISABLED = -100,		/**< Option table disabled */

src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h

@@ -23,14 +23,13 @@ enum cbfs_type {
 	CBFS_TYPE_LEGACY_STAGE	= 0x10,
 	CBFS_TYPE_STAGE		= 0x11,
 	CBFS_TYPE_SELF		= 0x20,
-	CBFS_TYPE_FIT_PAYLOAD	= 0x21,
+	CBFS_TYPE_FIT		= 0x21,
 	CBFS_TYPE_OPTIONROM	= 0x30,
 	CBFS_TYPE_BOOTSPLASH	= 0x40,
 	CBFS_TYPE_RAW		= 0x50,
 	CBFS_TYPE_VSA		= 0x51,
 	CBFS_TYPE_MBI		= 0x52,
 	CBFS_TYPE_MICROCODE	= 0x53,
-	CBFS_TYPE_INTEL_FIT	= 0x54,
 	CBFS_TYPE_FSP		= 0x60,
 	CBFS_TYPE_MRC		= 0x61,
 	CBFS_TYPE_MMA		= 0x62,

src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h

@@ -18,12 +18,12 @@ struct mem_chip_info {
 	uint8_t num_channels;
 	uint8_t reserved[6];
 	struct mem_chip_channel {
-		uint64_t density;	/* number in _bytes_, not Megabytes! */
-		uint8_t io_width;	/* should be `8`, `16`, `32` or `64` */
-		uint8_t manufacturer_id; /* raw value from MR5 */
-		uint8_t revision_id[2];	/* raw values from MR6 and MR7 */
+		uint64_t density;
+		uint8_t io_width;
+		uint8_t manufacturer_id;
+		uint8_t revision_id[2];
 		uint8_t reserved[4];
-		uint8_t serial_id[8];	/* LPDDR5 only, MR47 - MR54 */
+		uint8_t serial_id[8]; /* LPDDR5 only */
 	} channel[0];
 };