mb/system76/mtl: Add Darter Pro 10

The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.

There are 2 variants in order to differentiate the 14" and 16" models,
as they have different keyboards and so have different EC firmware.

Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337
Signed-off-by: Tim Crawford <tcrawford@system76.com>

AUTHORS

@@ -39,7 +39,9 @@ Alexandru Gagniuc
 Alexey Buyanov
 Alexey Vazhnov
 Alice Sell
+Alicja Michalska
 Allen-KH Cheng
+Alper Nebi Yasak
 Amanda Hwang
 American Megatrends International, LLC
 Amersel
@@ -62,6 +64,7 @@ Anna Karaś
 Annie Chen
 Anton Kochkov
 Ao Zhong
+Appukuttan V K
 Arashk Mahshidfar
 Arec Kao
 Ariel Fang
@@ -93,6 +96,7 @@ Bora Guvendik
 Boris Barbulovski
 Boris Mittelberg
 Brandon Breitenstein
+Brandon Weeks
 Brian Norris
 Bryant Ou
 Carl-Daniel Hailfinger
@@ -101,6 +105,7 @@ Caveh Jalali
 Cavium Inc.
 Chao Gui
 Chen-Tsung Hsieh
+Chen. Gang C
 Chia-Ling Hou
 Chien-Chih Tseng
 Chris Wang
@@ -128,6 +133,7 @@ Da Lao
 Daisuke Nojiri
 Damien Zammit
 Dan Callaghan
+Dan Campbell
 Daniel Campello
 Daniel Gröber
 Daniel Kang
@@ -181,6 +187,7 @@ Eltan B.V
 Eltan B.V.
 Elyes Haouas
 Eran Mitrani
+Eren Peng
 Eric Biederman
 Eric Lai
 Eric Peers
@@ -194,13 +201,16 @@ Evan Green
 Evgeny Zinoviev
 Fabian Groffen
 Fabian Kunkel
+Fabian Meyer
 Fabio Aiuto
 Fabrice Bellard
 Facebook, Inc.
+Fei Yan
 Felix Friedlander
 Felix Held
 Felix Singer
 Fengquan Chen
+Filip Lewiński
 Flora Fu
 Florian Laufenböck
 Francois Toguo Fotso
@@ -214,7 +224,7 @@ Free Software Foundation, Inc.
 Freescale Semiconductor, Inc.
 Furquan Shaikh
 Gaggery Tsai
-Gang C Chen 
+Gang C Chen
 Garmin Chang
 Gary Jennejohn
 George Trudeau
@@ -234,6 +244,7 @@ HardenedLinux
 Harsha B R
 Harshit Sharma
 Henry C Chen
+Herbert Wu
 Hewlett Packard Enterprise Development LP
 Hewlett-Packard Development Company, L.P.
 Himanshu Sahdev
@@ -286,6 +297,7 @@ Jason Zhao
 jason-ch chen
 Jason-jh Lin
 Jay Patel
+Jean Lucas
 Jeff Chase
 Jeff Daly
 Jeff Li
@@ -307,6 +319,7 @@ Jitao Shi
 Joe Pillow
 Joe Tessler
 Joel Kitching
+Joel Linn
 Joey Peng
 Johanna Schander
 John Su
@@ -325,6 +338,7 @@ Jordan Crouse
 Jörg Mische
 Joseph Smith
 Josie Nordrum
+Juan José García-Castro Crespo
 Julia Tsai
 Julian Schroeder
 Julian Stecklina
@@ -337,6 +351,7 @@ Kangheui Won
 Kapil Porwal
 Karol Zmyslowski
 Karthik Ramasubramanian
+Kei Hiroyoshi
 Keith Hui
 Keith Packard
 Kenneth Chan
@@ -367,9 +382,11 @@ Lawrence Chang
 Leah Rowe
 Lean Sheng Tan
 Lei Wen
+Lennart Eichhorn
 Lenovo Group Ltd
 Leo Chou
 Li-Ta Lo
+Li1 Feng
 Liam Flaherty
 Libra Li
 Libretrend LDA
@@ -397,6 +414,7 @@ Marc Bertens
 Marc Jones
 Marco Chen
 Marek Kasiewicz
+Marek Maślanka
 Marek Vasut
 Mario Scheithauer
 Marius Gröger
@@ -465,10 +483,12 @@ Myles Watson
 Nancy.Lin
 Naresh Solanki
 Nathan Lu
+Naveen R. Iyer
 Neill Corlett
 Network Appliance Inc.
 Nicholas Chin
 Nicholas Sielicki
+Nicholas Sudsgaard
 Nick Barker
 Nick Chen
 Nick Vaccaro
@@ -502,6 +522,7 @@ Paul Fagerburg
 Paul Menzel
 Paul2 Huang
 Paulo Alcantara
+Pavan Holla
 Pavel Sayekat
 Paz Zcharya
 PC Engines GmbH
@@ -520,6 +541,7 @@ Philipp Deppenwiese
 Philipp Hug
 Piotr Kleinschmidt
 Po Xu
+Poornima Tom
 Prasad Malisetty
 Prashant Malani
 Pratik Vishwakarma
@@ -529,6 +551,7 @@ Protectli
 Purism SPC
 Purism, SPC
 Qii Wang
+Qinghong Zeng
 Qualcomm Technologies, Inc.
 Quanta Computer INC
 Raihow Shi
@@ -572,6 +595,7 @@ Robinson P. Tryon
 Rockchip, Inc.
 Rocky Phagura
 Roger Lu
+Roger Wang
 Roja Rani Yarubandi
 Romain Lievin
 Roman Zippel
@@ -745,12 +769,14 @@ Wojciech Macek
 Wolfgang Denk
 Won Chung
 Wonkyu Kim
-Wuxy 
+Wuxy
+Xiang W
 Xin Ji
 Xixi Chen
 Xuxin Xiong
 YADRO
 Yan Liu
+Yang Wu
 Yann Collet
 Yaroslav Kurlaev
 YH Lin
@@ -767,6 +793,7 @@ Yuanliding
 Yuchen He
 Yuchen Huang
 Yunlong Jia
+Yuval Peress
 Zachary Yedidia
 Zanxi Chen
 Zhanyong Wang
@@ -776,10 +803,11 @@ Zhi7 Li
 Zhiqiang Ma
 Zhixing Ma
 Zhiyong Tao
-zhongtian wu
+Zhongtian Wu
 Zhuohao Lee
 Ziang Wang
 Zoey Wu
 Zoltan Baldaszti
 小田喜陽彦
+忧郁沙茶
 陳建宏

Documentation/releases/coreboot-24.05-relnotes.md

@@ -149,6 +149,7 @@ Platform Updates
 ### Updated SoCs
 
 * Added src/soc/ibm/power9
+* Added src/soc/intel/xeon_sp/gnr
 * Added src/soc/sifive/fu740
 
 
@@ -156,15 +157,15 @@ Platform Updates
 Statistics from the 24.02 to the 24.05 release
 --------------------------------------------
 
-* Total Commits: 722
+* Total Commits: 739
-* Average Commits per day: 8.55
+* Average Commits per day: 8.64
-* Total lines added: 302523
+* Total lines added: 304721
-* Average lines added per commit: 419.01
+* Average lines added per commit: 412.34
-* Number of patches adding more than 100 lines: 57
+* Number of patches adding more than 100 lines: 60
-* Average lines added per small commit: 37.80
+* Average lines added per small commit: 37.74
-* Total lines removed: 16089
+* Total lines removed: 16195
-* Average lines removed per commit: 22.28
+* Average lines removed per commit: 21.91
-* Total difference between added and removed: 286434
+* Total difference between added and removed: 288526
 * Total authors: 131
 * New authors: 23
 

Documentation/releases/coreboot-24.08-relnotes.md

@@ -0,0 +1,100 @@
+Upcoming release - coreboot 24.08
+========================================================================
+
+The 24.08 release is scheduled for Mid Aug, 2024
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+
+
+Significant or interesting changes
+----------------------------------
+
+* Add changes that need a full description here
+
+* This section should have full descriptions and can or should have
+  a link to the referenced commits.
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+Changes to external resources
+-----------------------------
+
+### Toolchain updates
+
+* Upgrade ACPICA from 20230628 to 20240321
+* Upgrade CMake from 3.28.3 to 3.29.3
+* Upgrade nasm from 2.16.01 to 2.16.03
+* Upgrade LLVM from 17.0.6 to 18.1.6
+* Upgrade GCC from 13.2 to 14.1.0
+
+### Git submodule pointers
+
+
+### External payloads
+
+
+
+Platform Updates
+----------------
+
+### Added mainboards:
+* To be filled in immediately before the release by the release team
+
+
+### Removed Mainboards
+* To be filled in immediately before the release by the release team
+
+
+### Updated SoCs
+* To be filled in immediately before the release by the release team
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Statistics from the 24.05 to the 24.08 release
+--------------------------------------------
+* To be filled in immediately before the release by the release team
+
+
+
+Significant Known and Open Issues
+---------------------------------
+
+Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
+
+
+
+coreboot Links and Contact Information
+--------------------------------------
+
+* Main Web site: https://www.coreboot.org
+* Downloads: https://coreboot.org/downloads.html
+* Source control: https://review.coreboot.org
+* Documentation: https://doc.coreboot.org
+* Issue tracker: https://ticket.coreboot.org/projects/coreboot
+* Donations: https://coreboot.org/donate.html

Documentation/releases/index.md

@@ -6,7 +6,7 @@ Please add to the release notes as changes are added:
 ```{toctree}
 :maxdepth: 1
 
-24.05 - May 2024 <coreboot-24.05-relnotes.md>
+24.08 - August 2024 <coreboot-24.08-relnotes.md>
 ```
 
 The [checklist] contains instructions to ensure that a release covers all
@@ -22,6 +22,7 @@ important is taken care of.
 ```{toctree}
 :maxdepth: 1
 
+24.05  - May 2024 <coreboot-24.05-relnotes.md>
 24.02  - February 2024 <coreboot-24.02-relnotes.md>
 4.22   - November 2023 <coreboot-4.22-relnotes.md>
 4.21   - August 2023 <coreboot-4.21-relnotes.md>

configs/builder/config.intel.crb.avc

@@ -0,0 +1,50 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.avc
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_AVENUECITY_CRB=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/avenuecity/descriptor.bin"
+CONFIG_CPU_UCODE_BINARIES="site-local/avenuecity/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/avenuecity/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/avenuecity/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/avenuecity/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/"
+
+CONFIG_PAYLOAD_FILE="site-local/avenuecity/linuxboot_bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y

configs/builder/config.intel.crb.bnc

@@ -0,0 +1,50 @@
+# Type this in coreboot root directory to get a working .config:
+#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.bnc
+
+#
+# [RO] Board Configurations
+#
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB=y
+
+CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
+CONFIG_CONFIGURABLE_RAMSTAGE=y
+
+CONFIG_NO_GFX_INIT=y
+
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_PAYLOAD_LINUX=y
+
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_CONSOLE_SERIAL_115200=y
+
+#
+# [RW] IFWI Ingredients
+#
+CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin"
+CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb"
+CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
+CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
+CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
+CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
+
+CONFIG_PAYLOAD_FILE="site-local/beechnutcity/linuxboot_bzImage"
+CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
+
+#
+# [RW] Debug Settings
+#
+CONFIG_CONSOLE_POST=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+
+CONFIG_VERIFY_HOBS=y
+CONFIG_DISPLAY_MTRRS=y
+
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+
+CONFIG_HAVE_DEBUG_GPIO=y
+CONFIG_DEBUG_GPIO=y

payloads/external/Makefile.mk

@@ -381,6 +381,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT)
 	CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \
 	CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \
 	CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \
+	CONFIG_PXE_TRUST_CMD=$(CONFIG_PXE_TRUST_CMD) \
 	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot

payloads/external/edk2/Makefile

@@ -37,6 +37,8 @@ BUILD_STR += -s
 endif
 endif
 
+BUILD_STR += -D BUILD_ARCH=X64
+
 #
 # EDK II (edk2/master) has the following build options relevant to coreboot:
 #

payloads/external/iPXE/Kconfig

@@ -108,7 +108,16 @@ config IPXE_HAS_HTTPS
 	  Enable HTTPS protocol, which allows you to encrypt all communication
 	  with a web server and to verify the server's identity
 
+config PXE_TRUST_CMD
+	bool "Enable TRUST commands"
+	default y
+	help
+	  Enable imgverify and imgtrust commands, which allow you to verify
+	  digital signature of file prior loading it, and restrict to loading
+	  trusted files only.
+
 endif # BUILD_IPXE
+
 endmenu
 
 endif # PXE

payloads/external/iPXE/Makefile

@@ -52,6 +52,9 @@ endif
 ifeq ($(CONFIG_IPXE_HAS_HTTPS),y)
 	sed -i'' 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h"
 endif
+ifeq ($(CONFIG_PXE_TRUST_CMD),y)
+	sed -i'' 's|.*IMAGE_TRUST_CMD|#define IMAGE_TRUST_CMD|g' "$(project_dir)/src/config/general.h"
+endif
 
 build: config $(CONFIG_SCRIPT)
 ifeq ($(CONFIG_HAS_SCRIPT),y)

payloads/libpayload/Kconfig

@@ -106,17 +106,22 @@ menu "Architecture Options"
 
 choice
         prompt "Target Architecture"
-        default ARCH_X86
+        default ARCH_X86_32
 
 config ARCH_ARM
         bool "ARM"
         help
           Support the ARM architecture
 
-config ARCH_X86
+config ARCH_X86_32
-        bool "x86"
+        bool "x86_32"
         help
-          Support the x86 architecture
+          Support the x86_32 architecture
+
+config ARCH_X86_64
+        bool "x86_64"
+        help
+          Support the x86_64 architecture
 
 config ARCH_ARM64
         bool "ARM64"
@@ -133,6 +138,12 @@ config ARCH_MOCK
 
 endchoice
 
+config ARCH_X86
+	bool
+	default y if ARCH_X86_32 || ARCH_X86_64
+	help
+	  Support the x86 architecture
+
 config MULTIBOOT
 	bool "Multiboot header support"
 	depends on ARCH_X86

payloads/libpayload/Makefile

@@ -118,7 +118,8 @@ ARCH-y := $(ARCHDIR-y)
 # override here.
 ARCH-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCH-$(CONFIG_LP_ARCH_ARM64)   := arm64
-ARCH-$(CONFIG_LP_ARCH_X86)     := x86_32
+ARCH-$(CONFIG_LP_ARCH_X86_32)  := x86_32
+ARCH-$(CONFIG_LP_ARCH_X86_64)  := x86_64
 ARCH-$(CONFIG_LP_ARCH_MOCK)    := mock
 
 # Five cases where we don't need fully populated $(obj) lists:

payloads/libpayload/Makefile.mk

@@ -56,7 +56,6 @@ classes-$(CONFIG_LP_REMOTEGDB) += libgdb
 classes-$(CONFIG_LP_VBOOT_LIB) += vboot_fw
 classes-$(CONFIG_LP_VBOOT_LIB) += tlcl
 libraries := $(classes-y)
-classes-y += head.o
 
 subdirs-y := arch/$(ARCHDIR-y)
 subdirs-y += crypto libc drivers libpci gdb
@@ -97,7 +96,7 @@ $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) $(obj)/libpayload.config
 	cmp $@ $< 2>/dev/null || cp $< $@
 
 library-targets = $(addsuffix .a,$(addprefix $(obj)/,$(libraries))) $(obj)/libpayload.a
-lib: $$(library-targets) $(obj)/head.o
+lib: $$(library-targets) $(obj)/libpayload.ldscript
 
 extract_nth=$(word $(1), $(subst |, ,$(2)))
 
@@ -116,17 +115,16 @@ $(obj)/%.a: $$(%-objs)
 	printf "    AR         $(subst $(CURDIR)/,,$(@))\n"
 	printf "create $@\n$(foreach objc,$(filter-out %.a,$^),addmod $(objc)\n)$(foreach lib,$(filter %.a,$^),addlib $(lib)\n)save\nend\n" | $(AR) -M
 
-$(obj)/head.o: $(obj)/arch/$(ARCHDIR-y)/head.head.o.o
+$(obj)/libpayload.ldscript: arch/$(ARCHDIR-y)/libpayload.ldscript $(obj)/libpayload-config.h
-	printf "    CP         $(subst $(CURDIR)/,,$(@))\n"
+	@printf "  LDSCRIPT  $@\n"
-	cp $^ $@
+	$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -E -P -x assembler-with-cpp -undef -o $@ $<
 
 install: real-target
 	printf "    INSTALL    $(DESTDIR)/libpayload/lib\n"
 	install -m 755 -d $(DESTDIR)/libpayload/lib
 	install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/
-	install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
+	install -m 644 $(obj)/libpayload.ldscript $(DESTDIR)/libpayload/lib/
 	install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
-	install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y)
 	printf "    INSTALL    $(DESTDIR)/libpayload/include\n"
 	install -m 755 -d $(DESTDIR)/libpayload/include
 	find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \;

payloads/libpayload/arch/arm/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -mthumb -march=armv7-a
 arm_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
 
-head.o-y += head.S
+libc-y += head.S
 libc-y += eabi_compat.c
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
@@ -44,5 +44,4 @@ libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
-head.o-S-ccopts += $(arm_asm_flags)
 libc-S-ccopts += $(arm_asm_flags)

payloads/libpayload/arch/arm64/Makefile.mk

@@ -29,7 +29,7 @@
 CFLAGS += -march=armv8-a
 arm64_asm_flags =
 
-head.o-y += head.S
+libc-y += head.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
 libc-y += virtual.c
@@ -42,5 +42,4 @@ libc-y += mmu.c
 libgdb-y += gdb.c
 
 # Add other classes here when you put assembly files into them!
- head.o-S-ccopts += $(arm64_asm_flags)
+libc-S-ccopts += $(arm64_asm_flags)
- libc-S-ccopts += $(arm64_asm_flags)

payloads/libpayload/arch/mock/Makefile.mk

@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-head.o-y += head.c
-
 libc-y += virtual.c
 
 CFLAGS += -Wno-address-of-packed-member

payloads/libpayload/arch/mock/head.c

@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* This file is empty on purpose. It should not be used. */

payloads/libpayload/arch/x86/Makefile.mk

@@ -27,16 +27,26 @@
 ##
 
 ifneq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
+ifeq ($(CONFIG_LP_ARCH_X86_64),y)
+CFLAGS += -mpreferred-stack-boundary=4
+else
 CFLAGS += -mpreferred-stack-boundary=2
 endif
+endif
 
-head.o-y += head.S
+libc-$(CONFIG_LP_ARCH_X86_32)  += head.S
+libc-$(CONFIG_LP_ARCH_X86_64)  += head_64.S
+libc-$(CONFIG_LP_ARCH_X86_64) += pt.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
-libc-y += exec.S virtual.c
+libc-y += virtual.c
 libc-y += selfboot.c cache.c
-libc-y += exception_asm.S exception.c
+libc-y += exception.c
 libc-y += delay.c
+libc-$(CONFIG_LP_ARCH_X86_32) += exec.c
+libc-$(CONFIG_LP_ARCH_X86_32) += exec.S
+libc-$(CONFIG_LP_ARCH_X86_32) += exception_asm.S
+libc-$(CONFIG_LP_ARCH_X86_64) += exception_asm_64.S
 
 # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed.
 libc-$(CONFIG_LP_GPL) += string.c

payloads/libpayload/arch/x86/exception.c

@@ -34,7 +34,13 @@
 
 #define IF_FLAG				(1 << 9)
 
-u32 exception_stack[0x400] __attribute__((aligned(8)));
+#if CONFIG(LP_ARCH_X86_64)
+#define REGISTER_FMT "0x%016zx"
+#else
+#define REGISTER_FMT "0x%08zx"
+#endif
+
+u8 exception_stack[0x400] __aligned(16);
 
 static interrupt_handler handlers[256];
 
@@ -143,17 +149,27 @@ static void dump_exception_state(void)
 		break;
 	}
 	printf("\n");
-	printf("EIP:    0x%08x\n", exception_state->regs.eip);
+	printf("REG_IP:    " REGISTER_FMT "\n", exception_state->regs.reg_ip);
+	printf("REG_FLAGS: " REGISTER_FMT "\n", exception_state->regs.reg_flags);
+	printf("REG_AX:    " REGISTER_FMT "\n", exception_state->regs.reg_ax);
+	printf("REG_BX:    " REGISTER_FMT "\n", exception_state->regs.reg_bx);
+	printf("REG_CX:    " REGISTER_FMT "\n", exception_state->regs.reg_cx);
+	printf("REG_DX:    " REGISTER_FMT "\n", exception_state->regs.reg_dx);
+	printf("REG_SP:    " REGISTER_FMT "\n", exception_state->regs.reg_sp);
+	printf("REG_BP:    " REGISTER_FMT "\n", exception_state->regs.reg_bp);
+	printf("REG_SI:    " REGISTER_FMT "\n", exception_state->regs.reg_si);
+	printf("REG_DI:    " REGISTER_FMT "\n", exception_state->regs.reg_di);
+#if CONFIG(LP_ARCH_X86_64)
+	printf("REG_R8:    0x%016zx\n", exception_state->regs.reg_r8);
+	printf("REG_R9:    0x%016zx\n", exception_state->regs.reg_r9);
+	printf("REG_R10:    0x%016zx\n", exception_state->regs.reg_r10);
+	printf("REG_R11:    0x%016zx\n", exception_state->regs.reg_r11);
+	printf("REG_R12:    0x%016zx\n", exception_state->regs.reg_r12);
+	printf("REG_R13:    0x%016zx\n", exception_state->regs.reg_r13);
+	printf("REG_R14:    0x%016zx\n", exception_state->regs.reg_r14);
+	printf("REG_R15:    0x%016zx\n", exception_state->regs.reg_r15);
+#endif
 	printf("CS:     0x%04x\n", exception_state->regs.cs);
-	printf("EFLAGS: 0x%08x\n", exception_state->regs.eflags);
-	printf("EAX:    0x%08x\n", exception_state->regs.eax);
-	printf("ECX:    0x%08x\n", exception_state->regs.ecx);
-	printf("EDX:    0x%08x\n", exception_state->regs.edx);
-	printf("EBX:    0x%08x\n", exception_state->regs.ebx);
-	printf("ESP:    0x%08x\n", exception_state->regs.esp);
-	printf("EBP:    0x%08x\n", exception_state->regs.ebp);
-	printf("ESI:    0x%08x\n", exception_state->regs.esi);
-	printf("EDI:    0x%08x\n", exception_state->regs.edi);
 	printf("DS:     0x%04x\n", exception_state->regs.ds);
 	printf("ES:     0x%04x\n", exception_state->regs.es);
 	printf("SS:     0x%04x\n", exception_state->regs.ss);
@@ -164,7 +180,7 @@ static void dump_exception_state(void)
 void exception_dispatch(void)
 {
 	die_if(exception_state->vector >= ARRAY_SIZE(handlers),
-	       "Invalid vector %u\n", exception_state->vector);
+	       "Invalid vector %zu\n", exception_state->vector);
 
 	u8 vec = exception_state->vector;
 
@@ -184,7 +200,7 @@ void exception_dispatch(void)
 	       vec);
 
 	dump_exception_state();
-	dump_stack(exception_state->regs.esp, 512);
+	dump_stack(exception_state->regs.reg_sp, 512);
 	/* We don't call apic_eoi because we don't want to ack the interrupt and
 	   allow another interrupt to wake the processor. */
 	halt();
@@ -197,6 +213,10 @@ success:
 
 void exception_init(void)
 {
+	/* TODO: Add exception init code for x64, currently only supporting 32-bit code */
+	if (CONFIG(LP_ARCH_X86_64))
+		return;
+
 	exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
 	exception_init_asm();
 }
@@ -206,6 +226,17 @@ void set_interrupt_handler(u8 vector, interrupt_handler handler)
 	handlers[vector] = handler;
 }
 
+#if CONFIG(LP_ARCH_X86_64)
+static uint64_t eflags(void)
+{
+	uint64_t eflags;
+	asm volatile(
+		"pushfq\n\t"
+		"popq %0\n\t"
+	: "=rm" (eflags));
+	return eflags;
+}
+#else
 static uint32_t eflags(void)
 {
 	uint32_t eflags;
@@ -215,6 +246,7 @@ static uint32_t eflags(void)
 	: "=rm" (eflags));
 	return eflags;
 }
+#endif
 
 void enable_interrupts(void)
 {

payloads/libpayload/arch/x86/exception_asm_64.S

@@ -0,0 +1,221 @@
+/*
+ *
+ * Copyright 2024 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+	.align 16
+	.global exception_stack_end
+exception_stack_end:
+	.quad 0
+	.global exception_state
+exception_state:
+	.quad 0
+
+/* Some temporary variables which are used while saving exception state. */
+vector:
+	.quad 0
+error_code:
+	.quad 0
+old_rsp:
+	.quad 0
+old_rax:
+	.quad 0
+
+	.align 16
+
+/*
+ * Each exception vector has a small stub associated with it which sets aside
+ * the error code, if any, records which vector we entered from, and calls
+ * the common exception entry point. Some exceptions have error codes and some
+ * don't, so we have a macro for each type.
+ */
+
+	.macro stub num
+exception_stub_\num:
+	movq	$0, error_code
+	movq	$\num, vector
+	jmp	exception_common
+	.endm
+
+	.macro stub_err num
+exception_stub_\num:
+	pop	error_code
+	movq	$\num, vector
+	jmp	exception_common
+	.endm
+
+	.altmacro
+	.macro	user_defined_stubs from, to
+	stub	\from
+	.if	\to-\from
+	user_defined_stubs	%(from+1),\to
+	.endif
+	.endm
+
+	stub 0
+	stub 1
+	stub 2
+	stub 3
+	stub 4
+	stub 5
+	stub 6
+	stub 7
+	stub_err 8
+	stub 9
+	stub_err 10
+	stub_err 11
+	stub_err 12
+	stub_err 13
+	stub_err 14
+	stub 15
+	stub 16
+	stub_err 17
+	stub 18
+	stub 19
+	stub 20
+	stub 21
+	stub 22
+	stub 23
+	stub 24
+	stub 25
+	stub 26
+	stub 27
+	stub 28
+	stub 29
+	stub_err 30
+	stub 31
+	/* Split the macro so we avoid a stack overflow. */
+	user_defined_stubs 32, 63
+	user_defined_stubs 64, 127
+	user_defined_stubs 128, 191
+	user_defined_stubs 192, 255
+
+exception_common:
+
+	/* Return from the exception. */
+	iretl
+
+/*
+ * We need segment selectors for the IDT, so we need to know where things are
+ * in the GDT. We set one up here which is pretty standard and largely copied
+ * from coreboot.
+ */
+	.align 16
+gdt:
+	/* selgdt 0, unused */
+	.word 0x0000, 0x0000
+	.byte 0x00, 0x00, 0x00, 0x00
+
+	/* selgdt 8, unused */
+	.word 0x0000, 0x0000
+	.byte 0x00, 0x00, 0x00, 0x00
+
+	/* selgdt 0x10, flat 4GB code segment */
+	.word 0xffff, 0x0000
+	.byte 0x00, 0x9b, 0xcf, 0x00
+
+	/* selgdt 0x18, flat 4GB data segment */
+	.word 0xffff, 0x0000
+	.byte	0x00, 0x92, 0xcf, 0x00
+
+	/* selgdt 0x20, flat x64 code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xaf, 0x00
+gdt_end:
+
+/* GDT pointer for use with lgdt */
+.global gdt_ptr
+gdt_ptr:
+	.word	gdt_end - gdt - 1
+	.quad	gdt
+
+	/*
+	 * Record the target and construct the actual entry at init time. This
+	 * is necessary because the linker doesn't want to construct the entry
+	 * for us.
+	 */
+	.macro interrupt_gate target
+	.quad \target
+	.quad \target
+	.endm
+
+	.altmacro
+	.macro	user_defined_gates from, to
+	interrupt_gate	exception_stub_\from
+	.if	\to-\from
+	user_defined_gates	%(from+1),\to
+	.endif
+	.endm
+
+	.align 16
+	.global	idt
+idt:
+	interrupt_gate exception_stub_0
+	interrupt_gate exception_stub_1
+	interrupt_gate exception_stub_2
+	interrupt_gate exception_stub_3
+	interrupt_gate exception_stub_4
+	interrupt_gate exception_stub_5
+	interrupt_gate exception_stub_6
+	interrupt_gate exception_stub_7
+	interrupt_gate exception_stub_8
+	interrupt_gate exception_stub_9
+	interrupt_gate exception_stub_10
+	interrupt_gate exception_stub_11
+	interrupt_gate exception_stub_12
+	interrupt_gate exception_stub_13
+	interrupt_gate exception_stub_14
+	interrupt_gate exception_stub_15
+	interrupt_gate exception_stub_16
+	interrupt_gate exception_stub_17
+	interrupt_gate exception_stub_18
+	interrupt_gate exception_stub_19
+	interrupt_gate exception_stub_20
+	interrupt_gate exception_stub_21
+	interrupt_gate exception_stub_22
+	interrupt_gate exception_stub_23
+	interrupt_gate exception_stub_24
+	interrupt_gate exception_stub_25
+	interrupt_gate exception_stub_26
+	interrupt_gate exception_stub_27
+	interrupt_gate exception_stub_28
+	interrupt_gate exception_stub_29
+	interrupt_gate exception_stub_30
+	interrupt_gate exception_stub_31
+	user_defined_gates 32, 63
+	user_defined_gates 64, 127
+	user_defined_gates 128, 191
+	user_defined_gates 192, 255
+idt_end:
+
+/* IDT pointer for use with lidt */
+idt_ptr:
+	.word idt_end - idt - 1
+	.quad idt
+
+	.global exception_init_asm
+exception_init_asm:
+	ret

payloads/libpayload/arch/x86/exec.c

@@ -29,8 +29,10 @@
 #include <libpayload-config.h>
 #include <libpayload.h>
 
-#if CONFIG(LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86_32)
 extern void i386_do_exec(long addr, int argc, char **argv, int *ret);
+#else
+#error "exec does not currently support x86_64."
 #endif
 
 /**
@@ -45,7 +47,7 @@ int exec(long addr, int argc, char **argv)
 {
 	int val = -1;
 
-#if CONFIG(LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86_32)
 	i386_do_exec(addr, argc, argv, &val);
 #endif
 	return val;

payloads/libpayload/arch/x86/gdb.c

@@ -15,6 +15,7 @@
 #include <exception.h>
 #include <gdb.h>
 #include <libpayload.h>
+#include <stddef.h>
 
 static const u8 type_to_signal[] = {
 	[EXC_DE]  = GDB_SIGFPE,
@@ -53,12 +54,15 @@ void gdb_arch_init(void)
 
 void gdb_arch_enter(void)
 {
-	u32 *esp;
+	u8 *stack_pointer;
-
+#if CONFIG(LP_ARCH_X86_64)
-	asm volatile ("mov %%esp, %0" : "=r"(esp) );
+	asm volatile ("movq %%rsp, %0" : "=r"(stack_pointer));
+#else
+	asm volatile ("mov %%esp, %0" : "=r"(stack_pointer));
+#endif
 
 	/* Avoid reentrant exceptions, just call the hook if in one already. */
-	if (esp >= exception_stack && esp <= exception_stack_end)
+	if (stack_pointer >= exception_stack && stack_pointer <= exception_stack_end)
 		gdb_exception_hook(EXC_BP);
 	else
 		asm volatile ("int3");
@@ -66,12 +70,12 @@ void gdb_arch_enter(void)
 
 int gdb_arch_set_single_step(int on)
 {
-	const u32 tf_bit = 1 << 8;
+	const size_t tf_bit = 1 << 8;
 
 	if (on)
-		exception_state->regs.eflags |= tf_bit;
+		exception_state->regs.reg_flags |= tf_bit;
 	else
-		exception_state->regs.eflags &= ~tf_bit;
+		exception_state->regs.reg_flags &= ~tf_bit;
 
 	return 0;
 }

payloads/libpayload/arch/x86/head.S

@@ -29,7 +29,7 @@
 
 	.code32
 	.global _entry
-	.text
+	.section .text._entry
 	.align 4
 
 /*
@@ -38,37 +38,14 @@
  * change anything.
  */
 _entry:
-	jmp _init
 
-	.align 4
+	/* Add multiboot header and jump around it when building with multiboot support. */
-
+#if CONFIG(LP_MULTIBOOT)
-#define MB_MAGIC 0x1BADB002
+	#include "multiboot_header.inc"
-#define MB_FLAGS 0x00010003
+#endif
-
-mb_header:
-	.long MB_MAGIC
-	.long MB_FLAGS
-	.long -(MB_MAGIC + MB_FLAGS)
-	.long mb_header
-	.long _start
-	.long _edata
-	.long _end
-	.long _init
-
-/*
- * This function saves off the previous stack and switches us to our
- * own execution environment.
- */
-_init:
 	/* No interrupts, please. */
 	cli
 
-#if CONFIG(LP_MULTIBOOT)
-	/* Store EAX and EBX */
-	movl %eax, loader_eax
-	movl %ebx, loader_ebx
-#endif
-
 	/* save pointer to coreboot tables */
 	movl 4(%esp), %eax
 	movl %eax, cb_header_ptr

payloads/libpayload/arch/x86/head_64.S

@@ -0,0 +1,141 @@
+/*
+ *
+ * Copyright (C) 2024 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define IA32_EFER	0xC0000080
+#define  EFER_LME	(1 << 8)
+
+	.code32
+	.global _entry
+	.section .text._entry
+	.align 4
+
+/*
+ * WARNING: Critical Code Section - 32/64-bit Compatibility
+ * This code between `_entry` and `jnz _init64` is executed during system initialization.
+ * It MUST function correctly regardless of whether the system is booting in:
+ *   - 32-bit protected mode
+ *   - 64-bit long mode
+ * To achieve this, ONLY use instructions that produce identical binary output in both modes.
+ * Thoroughly test ALL modifications to this section in BOTH 32-bit and 64-bit boot
+ * environments.
+ */
+
+_entry:
+
+	/* Add multiboot header and jump around it when building with multiboot support. */
+#if CONFIG(LP_MULTIBOOT)
+	#include "multiboot_header.inc"
+#endif
+	/* No interrupts, please. */
+	cli
+
+	movl $IA32_EFER, %ecx
+	rdmsr
+	testl $EFER_LME, %eax
+	jnz _init64
+
+	lgdt %cs:gdt_ptr
+
+	/* save pointer to coreboot tables */
+	movl 4(%esp), %eax
+	/*
+	 * NOTE: coreboot tables has passed over the top of the stack
+	 * while calling in protected mode.
+	 */
+	movl %eax, cb_header_ptr
+
+	call init_page_table
+	movl $pm4le, %eax
+
+	/* load identity mapped page tables */
+	movl %eax, %cr3
+
+	/* enable PAE */
+	movl %cr4, %eax
+	btsl $5, %eax
+	movl %eax, %cr4
+
+	/* enable long mode */
+	movl $(IA32_EFER), %ecx
+	rdmsr
+	btsl $8, %eax
+	wrmsr
+
+	/* enable paging */
+	movl %cr0, %eax
+	btsl $31, %eax
+	movl %eax, %cr0
+
+	/* Jump to selgdt 0x20, flat x64 code segment */
+	ljmp $0x20, $_entry64
+
+.code64
+.align 16
+_init64:
+	movabs	$gdt_ptr, %rax
+	lgdt	(%rax)
+
+	/*
+	 * Note: The `cb_header_ptr` has passed as the first argument
+	 * to the x86-64 calling convention.
+	 */
+	movq %rdi, cb_header_ptr
+
+	call init_page_table
+	movq $pm4le, %rax
+
+	/* load identity mapped page tables */
+	movq %rax, %cr3
+
+_entry64:
+	/* Store current stack pointer and set up new stack. */
+	movq %rsp, %rax
+	movabs	$_estack, %rsp
+
+	push %rax
+
+	fninit
+	movq %cr0, %rax
+	andq $0xFFFFFFFFFFFFFFFB, %rax	/* clear EM */
+	orq $0x00000022, %rax	/* set MP, NE */
+	movq %rax, %cr0
+
+	movq %cr4, %rax
+	orq $0x00000600, %rax	/* set OSFXSR, OSXMMEXCPT */
+	movq %rax, %cr4
+
+	/* Let's rock. */
+	call start_main
+
+	/* %rax has the return value - pass it on unmolested */
+_leave:
+	/* Restore old stack. */
+	pop %rsp
+
+	/* Return to the original context. */
+	ret

payloads/libpayload/arch/x86/libpayload.ldscript

@@ -26,8 +26,13 @@
  * SUCH DAMAGE.
  */
 
+#if CONFIG(LP_ARCH_X86_64)
+OUTPUT_FORMAT(elf64-x86-64)
+OUTPUT_ARCH(x86_64)
+#else
 OUTPUT_FORMAT(elf32-i386)
 OUTPUT_ARCH(i386)
+#endif
 
 ENTRY(_entry)
 

payloads/libpayload/arch/x86/multiboot_header.inc

@@ -0,0 +1,54 @@
+/*
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
+ * Copyright (C) 2024 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define MB_MAGIC 0x1BADB002
+#define MB_FLAGS 0x00010003
+
+	jmp _init
+
+/*
+ * Note: The Multiboot standard requires Multiboot header to be placed
+ * below 0x2000 in the resulting image.  See:
+ * http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
+ */
+mb_header:
+	.long MB_MAGIC
+	.long MB_FLAGS
+	.long -(MB_MAGIC + MB_FLAGS)
+	.long mb_header
+	.long _start
+	.long _edata
+	.long _end
+	.long _init
+
+_init:
+	/* Store EAX and EBX */
+	movl %eax, loader_eax
+	movl %ebx, loader_ebx

payloads/libpayload/arch/x86/pt.S

@@ -0,0 +1,149 @@
+/*
+ *
+ * Copyright 2024 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * For reference see "AMD64 Architecture Programmer's Manual Volume 2",
+ * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4
+ *
+ * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty
+ */
+
+.section .bss
+#define _PRES (1ULL << 0)
+#define _RW   (1ULL << 1)
+#define _US   (1ULL << 2)
+#define _A    (1ULL << 5)
+#define _D    (1ULL << 6)
+#define _PS   (1ULL << 7)
+
+.section .bss.pm4le
+.global pm4le
+.align 4096
+pm4le:
+.skip 8
+
+.section .bss.main_page_table
+.global main_page_table
+.align 4096
+main_page_table:
+.skip 8192
+
+.section .bss.extra_page_table
+.global extra_page_table
+.align 4096
+extra_page_table:
+.skip 32
+
+/*
+ * WARNING: 32-bit/64-bit Mode Compatibility for Page Table Initialization
+ * This `init_page_table` function is designed to work in both 32-bit protected
+ * mode AND 64-bit long mode.
+ *
+ * Key Considerations:
+ * - Assembly Instructions:  Use ONLY instructions that have the SAME binary representation
+ *                           in both 32-bit and 64-bit modes.
+ * - `.code64` Directive:  We're compiling with `.code64` to ensure the assembler uses
+ *                         the correct 64-bit version of instructions (e.g., `inc`).
+ * - Register Notation:
+ *     - Use 64-bit register names (like `%rsi`) for register-indirect addressing to avoid
+ *       incorrect address size prefixes.
+ *     - It's safe to use `%esi` with `mov` instructions, as the high 32 bits are zeroed
+ *       in 64-bit mode.
+ *
+ * IMPORTANT:
+ * Thoroughly test ANY changes to this function in BOTH 32-bit and 64-bit boot environments.
+ */
+
+.code64
+.section .text.init_page_table
+.globl init_page_table
+.type init_page_table, @function
+
+init_page_table:
+	mov $0x80000001, %eax
+	cpuid
+	test $(1 << 26), %edx
+	jnz setup_1gb
+
+setup_2mb:
+	mov $2048, %edi
+	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
+	mov $0, %ecx
+	mov $main_page_table, %esi
+
+loop_2mb:
+	mov %eax, (%rsi, %rcx, 8)
+	mov $0, 4(%rsi, %rcx, 8)
+	add $0x200000, %eax
+	inc %ecx
+	cmp %edi, %ecx
+	jb loop_2mb
+
+	mov $4, %edi
+	mov $main_page_table, %eax
+	add $(_PRES + _RW + _US + _A), %eax
+	mov $0, %ecx
+	mov $extra_page_table, %esi
+
+fill_extra_page_table:
+	mov %eax, (%rsi, %rcx, 8)
+	mov $0, 4(%rsi, %rcx, 8)
+	add $4096, %eax
+	inc %ecx
+	cmp %edi, %ecx
+	jb fill_extra_page_table
+
+	mov $extra_page_table, %eax
+	jmp leave
+
+setup_1gb:
+	mov $512, %edi
+	mov $(_PRES + _RW + _US + _PS + _A + _D), %eax
+	mov $0, %ebx
+	mov $0, %ecx
+	mov $main_page_table, %esi
+
+loop_1gb:
+	mov %eax, (%rsi, %rcx, 8)
+	mov %ebx, 4(%rsi, %rcx, 8)
+	add $0x40000000, %eax
+	cmp $0x40000000, %eax
+	ja no_overflow_1gb
+	inc %ebx
+no_overflow_1gb:
+	inc %ecx
+	cmp %edi, %ecx
+	jb loop_1gb
+
+	mov $main_page_table, %eax
+
+leave:
+	or $(_PRES + _RW + _US + _A), %eax
+	mov %eax, pm4le
+
+	ret

payloads/libpayload/arch/x86/string.c

@@ -81,6 +81,16 @@ void *memcpy(void *dest, const void *src, size_t n)
 {
 	unsigned long d0, d1, d2;
 
+#if CONFIG(LP_ARCH_X86_64)
+	asm volatile(
+		"rep ; movsq\n\t"
+		"mov %4,%%rcx\n\t"
+		"rep ; movsb\n\t"
+		: "=&c" (d0), "=&D" (d1), "=&S" (d2)
+		: "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src)
+		: "memory"
+	);
+#else
 	asm volatile(
 		"rep ; movsl\n\t"
 		"movl %4,%%ecx\n\t"
@@ -89,6 +99,7 @@ void *memcpy(void *dest, const void *src, size_t n)
 		: "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src)
 		: "memory"
 	);
+#endif
 
 	return dest;
 }

payloads/libpayload/bin/lpgcc

@@ -74,34 +74,34 @@ else
 fi
 
 if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/arm
+  _ARCHDIR=arm
-  _ARCHLIBDIR=$_LIBDIR/arm
   _ARCHEXTRA=""
-  _ARCH=arm
+
 fi
 if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/arm64
+  _ARCHDIR=arm64
-  _ARCHLIBDIR=$_LIBDIR/arm64
   _ARCHEXTRA=""
-  _ARCH=arm64
 fi
 if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/x86
+  _ARCHDIR=x86
-  _ARCHLIBDIR=$_LIBDIR/x86
+  if [ "$CONFIG_LP_ARCH_X86_32" = "y" ]; then
-  _ARCHEXTRA="-m32 "
+    _ARCHEXTRA="-m32 "
-  _ARCH=x86
+  else
+    _ARCHEXTRA="-m64 "
+  fi
 fi
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/mock
+  _ARCHDIR=mock
-  _ARCHLIBDIR=$_LIBDIR/mock
   _ARCHEXTRA=""
-  _ARCH=mock
 fi
 
+_ARCHINCDIR=$_INCDIR/$_ARCHDIR
+_ARCHLIBDIR=$_LIBDIR/$_ARCHDIR
+
 if [ -f $_LIBDIR/libpayload.ldscript ]; then
 	_LDDIR=$_LIBDIR
-elif [ -f $BASE/../arch/$_ARCH/libpayload.ldscript ]; then
+elif [ -f $BASE/../arch/$_ARCHDIR/libpayload.ldscript ]; then
-	_LDDIR=$BASE/../arch/$_ARCH
+	_LDDIR=$BASE/../arch/$_ARCHDIR
 fi
 # Host arch should youse default linker script
 if [ "$CONFIG_LP_ARCH_MOCK" = "y" ]; then
@@ -126,13 +126,10 @@ CMDLINE=
 
 while [ $# -gt 0 ]; do
 	case $1 in
-	    -m32|-fno-stack-protector)
+	    -m32|-fno-stack-protector|-m64)
 		shift
 		continue
 		;;
-	    -m64)
-		error "Invalid option --64 - only 32 bit architectures are supported"
-		;;
 	    -c)
 		DOLINK=0
 		;;
@@ -205,14 +202,6 @@ if [ $DOLINK -eq 0 ]; then
     $DEFAULT_CC $CMDLINE $_CFLAGS
 else
     _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
-    if [ -f $_ARCHLIBDIR/head.o ]; then
-	    HEAD_O=$_ARCHLIBDIR/head.o
-    elif [ -f $_OBJ/head.o ]; then
-	    HEAD_O=$_OBJ/head.o
-    else
-	    echo "Could not find head.o"
-	    exit 1
-    fi
 
     if [ "$CONFIG_LP_ARM64_A53_ERRATUM_843419" = y ] &&
        grep -q fix-cortex-a53-843419 $_XCOMPILE; then
@@ -224,13 +213,8 @@ else
     _LDFLAGS="$_LDFLAGS -Wl,--defsym=CONFIG_LP_STACK_SIZE=$CONFIG_LP_STACK_SIZE"
 
     if [ $DEBUGME -eq 1 ]; then
-	echo "$DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
+	echo "$DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload $_LIBGCC"
     fi
 
-    # Note: $_ARCHLIBDIR/head.o must be the first object being linked, because it
+    $DEFAULT_CC $_LDFLAGS $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
-    # contains a Multiboot header.  The Multiboot standard requires this
-    # header to be placed below 0x2000 in the resulting image.  See:
-    # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
-
-    $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
 fi

payloads/libpayload/drivers/storage/ahci_common.c

@@ -66,7 +66,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 			    u8 *const user_buf, const size_t len,
 			    const int out)
 {
-	if ((u32)user_buf & 1) {
+	if ((uintptr_t)user_buf & 1) {
 		printf("ahci: Odd buffer pointer (%p).\n", user_buf);
 		if (dev->buf) /* orphaned buffer */
 			free(dev->buf - *(dev->buf - 1));
@@ -76,7 +76,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
 		dev->user_buf = user_buf;
 		dev->write_back = !out;
 		dev->buflen = len;
-		if ((u32)dev->buf & 1) {
+		if ((uintptr_t)dev->buf & 1) {
 			dev->buf[0] = 1;
 			dev->buf += 1;
 		} else {

payloads/libpayload/drivers/usb/uhci.c

@@ -274,7 +274,7 @@ uhci_stop(hci_t *controller)
 
 #define UHCI_SLEEP_TIME_US 30
 #define UHCI_TIMEOUT (USB_MAX_PROCESSING_TIME_US / UHCI_SLEEP_TIME_US)
-#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
+#define GET_TD(x) ((void *)(((unsigned long)(x))&~0xf))
 
 static td_t *
 wait_for_completed_qh(hci_t *controller, qh_t *qh)

payloads/libpayload/include/x86/arch/exception.h

@@ -29,6 +29,7 @@
 #ifndef _ARCH_EXCEPTION_H
 #define _ARCH_EXCEPTION_H
 
+#include <stddef.h>
 #include <stdint.h>
 
 void exception_init_asm(void);
@@ -38,20 +39,28 @@ void disable_interrupts(void);
 /** Returns 1 if interrupts are enabled. */
 int interrupts_enabled(void);
 
-struct exception_state
+#if CONFIG(LP_ARCH_X86_64)
-{
+struct exception_state {
 	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
 	struct {
-		u32 eax;
+		size_t reg_ax;
-		u32 ecx;
+		size_t reg_bx;
-		u32 edx;
+		size_t reg_cx;
-		u32 ebx;
+		size_t reg_dx;
-		u32 esp;
+		size_t reg_si;
-		u32 ebp;
+		size_t reg_di;
-		u32 esi;
+		size_t reg_bp;
-		u32 edi;
+		size_t reg_sp;
-		u32 eip;
+		size_t reg_r8;
-		u32 eflags;
+		size_t reg_r9;
+		size_t reg_r10;
+		size_t reg_r11;
+		size_t reg_r12;
+		size_t reg_r13;
+		size_t reg_r14;
+		size_t reg_r15;
+		size_t reg_ip;
+		size_t reg_flags;
 		u32 cs;
 		u32 ss;
 		u32 ds;
@@ -59,13 +68,39 @@ struct exception_state
 		u32 fs;
 		u32 gs;
 	} regs;
-	u32 error_code;
+	size_t error_code;
-	u32 vector;
+	size_t vector;
 } __packed;
+#else
+struct exception_state {
+	/* Careful: x86/gdb.c currently relies on the size and order of regs. */
+	struct {
+		size_t reg_ax;
+		size_t reg_cx;
+		size_t reg_dx;
+		size_t reg_bx;
+		size_t reg_sp;
+		size_t reg_bp;
+		size_t reg_si;
+		size_t reg_di;
+		size_t reg_ip;
+		size_t reg_flags;
+		u32 cs;
+		u32 ss;
+		u32 ds;
+		u32 es;
+		u32 fs;
+		u32 gs;
+	} regs;
+	size_t error_code;
+	size_t vector;
+} __packed;
+#endif
+
 extern struct exception_state *exception_state;
 
-extern u32 exception_stack[];
+extern u8 exception_stack[];
-extern u32 *exception_stack_end;
+extern u8 *exception_stack_end;
 
 enum {
 	EXC_DE = 0, /* Divide by zero */

payloads/libpayload/libc/Makefile.mk

@@ -29,7 +29,7 @@
 
 libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c
 libc-$(CONFIG_LP_LIBC) += memory.c ctype.c lib.c libgcc.c
-libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c
+libc-$(CONFIG_LP_LIBC) += rand.c time.c
 libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c
 libc-$(CONFIG_LP_LIBC) += args.c
 libc-$(CONFIG_LP_LIBC) += strlcpy.c

payloads/libpayload/vboot/Makefile.mk

@@ -15,7 +15,8 @@ vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \
 		       $(filter-out -I$(coreboottop)/%,$(1)))))
 
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM) := arm
-VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86) := x86
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_32) := x86
+VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_X86_64) := x86_64
 VBOOT_FIRMWARE_ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
 
 ifneq ($(CONFIG_LP_ARCH_MOCK),)

src/Kconfig

@@ -918,8 +918,9 @@ config GENERATE_PIRQ_TABLE
 	  If unsure, say Y.
 
 config GENERATE_SMBIOS_TABLES
-	depends on ARCH_X86
+	depends on ARCH_X86 || ARCH_ARM64
 	bool "Generate SMBIOS tables"
+	default n if ARCH_ARM64
 	default y
 	help
 	  Generate SMBIOS tables for this board.

src/acpi/acpi_apic.c

@@ -11,7 +11,7 @@ static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {
 	lapic->type = LOCAL_APIC; /* Local APIC structure */
 	lapic->length = sizeof(acpi_madt_lapic_t);
-	lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
+	lapic->flags = ACPI_MADT_LAPIC_ENABLED;
 	lapic->processor_id = cpu;
 	lapic->apic_id = apic;
 
@@ -23,7 +23,7 @@ static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 api
 	lapic->type = LOCAL_X2APIC; /* Local APIC structure */
 	lapic->reserved = 0;
 	lapic->length = sizeof(acpi_madt_lx2apic_t);
-	lapic->flags = (1 << 0); /* Processor/LAPIC enabled */
+	lapic->flags = ACPI_MADT_LAPIC_ENABLED;
 	lapic->processor_id = cpu;
 	lapic->x2apic_id = apic;
 
@@ -127,17 +127,12 @@ static int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride)
 
 	ioapic_get_sci_pin(&gsi, &irq, &flags);
 
+	/* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number
+	   instead of the 8259 IRQ number */
 	if (!CONFIG(ACPI_HAVE_PCAT_8259))
 		irq = gsi;
 
-	irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */
+	return acpi_create_madt_irqoverride(irqoverride, MP_BUS_ISA, irq, gsi, flags);
-	irqoverride->length = sizeof(acpi_madt_irqoverride_t);
-	irqoverride->bus = MP_BUS_ISA;
-	irqoverride->source = irq;
-	irqoverride->gsirq = gsi;
-	irqoverride->flags = flags;
-
-	return irqoverride->length;
 }
 
 static unsigned long acpi_create_madt_ioapic_gsi0_default(unsigned long current)
@@ -234,7 +229,7 @@ unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current)
 	madt->lapic_addr = cpu_get_lapic_addr();
 
 	if (CONFIG(ACPI_HAVE_PCAT_8259))
-		madt->flags |= 1;
+		madt->flags |= ACPI_MADT_PCAT_COMPAT;
 
 	if (CONFIG(ACPI_COMMON_MADT_LAPIC))
 		current = acpi_create_madt_lapics_with_nmis(current);

src/acpi/acpigen.c

@@ -14,6 +14,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/soundwire.h>
+#include <stdio.h>
 #include <types.h>
 
 static char *gencurrent;

src/acpi/acpigen_dptf.c

@@ -4,6 +4,7 @@
 #include <acpi/acpigen_dptf.h>
 #include <stdbool.h>
 #include <stdint.h>
+#include <stdio.h>
 
 /* Defaults */
 #define DEFAULT_RAW_UNIT		"ma"

src/acpi/acpigen_usb.c

@@ -5,6 +5,7 @@
 #include <acpi/acpigen.h>
 #include <acpi/acpigen_usb.h>
 #include <device/device.h>
+#include <stdio.h>
 
 static const char *power_role_to_str(enum usb_typec_power_role power_role)
 {

src/acpi/device.c

@@ -8,6 +8,7 @@
 #include <acpi/acpigen_pci.h>
 #include <device/device.h>
 #include <stdlib.h>
+#include <stdio.h>
 #include <types.h>
 #include <crc_byte.h>
 

src/arch/arm64/Makefile.mk

@@ -30,6 +30,9 @@ bootblock-y += eabi_compat.c
 decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 bootblock-y += transition.c transition_asm.S
+ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
+bootblock-y += smc.c smc_asm.S
+endif
 
 decompressor-y += memset.S
 bootblock-y += memset.S
@@ -69,6 +72,9 @@ verstage-y += memcpy.S
 verstage-y += memmove.S
 
 verstage-y += transition.c transition_asm.S
+ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
+verstage-y += smc.c smc_asm.S
+endif
 
 endif # CONFIG_ARCH_VERSTAGE_ARM64
 
@@ -88,6 +94,9 @@ romstage-y += memmove.S
 romstage-y += ramdetect.c
 romstage-y += romstage.c
 romstage-y += transition.c transition_asm.S
+ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
+romstage-y += smc.c smc_asm.S
+endif
 
 rmodules_arm64-y += memset.S
 rmodules_arm64-y += memcpy.S
@@ -109,6 +118,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM64),y)
 ramstage-y += div0.c
 ramstage-y += eabi_compat.c
 ramstage-y += boot.c
+ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
 ramstage-y += tables.c
 ramstage-y += ramdetect.c
 ramstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
@@ -117,6 +127,9 @@ ramstage-y += memcpy.S
 ramstage-y += memmove.S
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c
 ramstage-y += transition.c transition_asm.S
+ifneq ($(CONFIG_ARM64_CURRENT_EL),3)
+ramstage-y += smc.c smc_asm.S
+endif
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += dma.c

src/arch/arm64/include/armv8/arch/smc.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef ARM_ARM64_SMC_H
+#define ARM_ARM64_SMC_H
+
+#include <types.h>
+
+uint64_t smc(uint32_t function_id, uint64_t arg1, uint64_t arg2, uint64_t arg3,
+		uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7);
+
+#define smc_call0(function_id)			smc(function_id, 0, 0, 0, 0, 0, 0, 0)
+#define smc_call1(function_id, a1)		smc(function_id, a1, 0, 0, 0, 0, 0, 0)
+#define smc_call2(function_id, a1, a2)		smc(function_id, a1, a2, 0, 0, 0, 0, 0)
+#define smc_call3(function_id, a1, a2, a3)	smc(function_id, a1, a2, a3, 0, 0, 0, 0)
+
+/* Documented in https://developer.arm.com/documentation/den0022/ */
+enum psci_return_values {
+	PSCI_SUCCESS = 0,
+	PSCI_NOT_SUPPORTED = -1,
+	PSCI_INVALID_PARAMETERS = -2,
+	PSCI_DENIED = -3,
+	PSCI_ALREADY_ON = -4,
+	PSCI_ON_PENDING = -5,
+	PSCI_INTERNAL_FAILURE = -6,
+	PSCI_NOT_PRESENT = -7,
+	PSCI_DISABLED = -8,
+	PSCI_INVALID_ADDRESS = -9,
+};
+
+/* PSCI functions */
+#define PSCI_VERSION		0x84000000
+#define PSCI_FEATURES		0x8400000a
+
+/* Documented in https://developer.arm.com/documentation/den0028/ */
+enum smccc_return_values {
+	SMC_SUCCESS = 0,
+	SMC_NOT_SUPPORTED = -1,
+	SMC_NOT_REQUIRED = -2,
+	SMC_INVALID_PARAMETER = -3,
+};
+
+/* SMCCC functions */
+#define SMCCC_VERSION		0x80000000
+#define SMCCC_ARCH_FEATURES	0x80000001
+#define SMCCC_ARCH_SOC_ID	0x80000002
+#define  SMCCC_GET_SOC_VERSION	0
+#define  SMCCC_GET_SOC_REVISION	1
+
+uint8_t smccc_supports_arch_soc_id(void);
+enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision);
+
+#endif /* ARM_ARM64_SMC_H */

src/arch/arm64/smbios.c

@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cache.h>
+#include <arch/lib_helpers.h>
+#include <arch/smc.h>
+#include <console/console.h>
+#include <smbios.h>
+#include <stdio.h>
+
+static void smbios_processor_id(u32 *processor_id)
+{
+	uint32_t jep106code, soc_revision;
+	uint64_t midr_el1;
+
+	if (smccc_supports_arch_soc_id()) {
+		smccc_arch_soc_id(&jep106code, &soc_revision);
+		processor_id[0] = jep106code;
+		processor_id[1] = soc_revision;
+	} else {
+		midr_el1 = raw_read_midr_el1();
+		processor_id[0] = midr_el1;
+		processor_id[1] = 0;
+	}
+}
+
+static int smbios_processor_manufacturer(u8 *start)
+{
+	char midr_el1_implementer;
+	char buf[32];
+
+	// [31:24] - Implementer code
+	midr_el1_implementer = (raw_read_midr_el1() & 0xff000000) >> 24;
+
+	snprintf(buf, sizeof(buf), "CPU implementer %x", midr_el1_implementer);
+	return smbios_add_string(start, buf);
+}
+
+static int smbios_processor_name(u8 *start)
+{
+	uint16_t midr_el1_partnumber;
+	char buf[32];
+
+	// [15:4] - PartNum
+	midr_el1_partnumber = (raw_read_midr_el1() & 0xfff0) >> 4;
+
+	snprintf(buf, sizeof(buf), "ARMv8 Processor rev %d", midr_el1_partnumber);
+	return smbios_add_string(start, buf);
+}
+
+#define MAX_CPUS_ENABLED(cpus) (cpus > 0xff ? 0xff : cpus)
+
+/* NOTE: Not handling big.LITTLE clusters. Consider using MP services (not yet) or the DSU. */
+int smbios_write_type4(unsigned long *current, int handle)
+{
+	static unsigned int cnt = 0;
+	char buf[8];
+	uint16_t characteristics = 0;
+	unsigned int cpu_voltage;
+
+	struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION,
+						    sizeof(*t), handle);
+
+	snprintf(buf, sizeof(buf), "CPU%d", cnt++);
+	t->socket_designation = smbios_add_string(t->eos, buf);
+
+	smbios_processor_id(t->processor_id);
+	t->processor_manufacturer = smbios_processor_manufacturer(t->eos);
+	t->processor_version = smbios_processor_name(t->eos);
+	t->processor_family = SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2;
+	t->processor_family2 = SMBIOS_PROCESSOR_FAMILY2_ARMV8;
+	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
+
+	smbios_cpu_get_core_counts(&t->core_count2, &t->thread_count2);
+	t->core_count = MAX_CPUS_ENABLED(t->core_count2);
+	t->thread_count = MAX_CPUS_ENABLED(t->thread_count2);
+	/* Assume we always enable all cores */
+	t->core_enabled = t->core_count;
+	t->core_enabled2 = t->core_count2;
+	t->l1_cache_handle = 0xffff;
+	t->l2_cache_handle = 0xffff;
+	t->l3_cache_handle = 0xffff;
+	t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number());
+	t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED;
+	t->processor_upgrade = PROCESSOR_UPGRADE_UNKNOWN;
+
+	t->external_clock = smbios_processor_external_clock();
+	if (t->external_clock == 0)
+		t->external_clock = (raw_read_cntfrq_el0() / 1000 / 1000);
+
+	t->current_speed = smbios_cpu_get_current_speed_mhz();
+
+	/* This field identifies a capability for the system, not the processor itself. */
+	t->max_speed = smbios_cpu_get_max_speed_mhz();
+
+	/* TODO: Are "Enhanced Virtualization" (by EL2) and "Power/Performance Control" supported? */
+	characteristics |= PROCESSOR_64BIT_CAPABLE;
+	characteristics |= BIT(5); /* Execute Protection */
+
+	if (t->core_count > 1)
+		characteristics |= PROCESSOR_MULTI_CORE;
+	if (t->thread_count > 1)
+		characteristics |= BIT(4); /* BIT4: Hardware Thread */
+	if (smccc_supports_arch_soc_id())
+		characteristics |= BIT(9); /* Arm64 SoC ID */
+
+	t->processor_characteristics = characteristics | smbios_processor_characteristics();
+
+	cpu_voltage = smbios_cpu_get_voltage();
+	if (cpu_voltage > 0)
+		t->voltage = 0x80 | cpu_voltage;
+
+	const int len = smbios_full_table_len(&t->header, t->eos);
+	*current += len;
+	return len;
+}
+
+int smbios_write_type7_cache_parameters(unsigned long *current,
+					int *handle,
+					int *max_struct_size,
+					struct smbios_type4 *type4)
+{
+	enum cache_level level = CACHE_L1;
+	int h;
+	int len = 0;
+
+	while (1) {
+		enum smbios_cache_type type;
+		struct cache_info info;
+
+		const u8 cache_type = cpu_get_cache_type(level);
+		/* No more caches in the system */
+		if (!cache_type)
+			break;
+
+		switch (cache_type) {
+		case CACHE_INSTRUCTION:
+			type = SMBIOS_CACHE_TYPE_INSTRUCTION;
+			cpu_get_cache_info(level, cache_type, &info);
+			break;
+		case CACHE_DATA:
+			type = SMBIOS_CACHE_TYPE_DATA;
+			cpu_get_cache_info(level, cache_type, &info);
+			break;
+		case CACHE_SEPARATE:
+			type = SMBIOS_CACHE_TYPE_DATA;
+			cpu_get_cache_info(level, CACHE_DATA, &info);
+			h = (*handle)++;
+			update_max(len, *max_struct_size, smbios_write_type7(current, h,
+				   level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
+				   type, info.size, info.size));
+
+			type = SMBIOS_CACHE_TYPE_INSTRUCTION;
+			cpu_get_cache_info(level, CACHE_INSTRUCTION, &info);
+			break;
+		case CACHE_UNIFIED:
+			type = SMBIOS_CACHE_TYPE_UNIFIED;
+			cpu_get_cache_info(level, cache_type, &info);
+			break;
+		default:
+			type = SMBIOS_CACHE_TYPE_UNKNOWN;
+			info.size = info.associativity = 0;
+			break;
+		}
+
+		h = (*handle)++;
+		update_max(len, *max_struct_size, smbios_write_type7(current, h,
+			   level, smbios_cache_sram_type(), smbios_cache_associativity(info.associativity),
+			   type, info.size, info.size));
+
+		if (type4) {
+			switch (level) {
+			case 1:
+				type4->l1_cache_handle = h;
+				break;
+			case 2:
+				type4->l2_cache_handle = h;
+				break;
+			case 3:
+				type4->l3_cache_handle = h;
+				break;
+			default:
+				break;
+			}
+		}
+
+		level++;
+	}
+
+	return len;
+}

src/arch/arm64/smc.c

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/smc.h>
+#include <console/console.h>
+#include <types.h>
+
+/* Assumes at least a PSCI implementation is present */
+uint8_t smccc_supports_arch_soc_id(void)
+{
+	static uint8_t supported = 0xff;
+	uint64_t smc_ret;
+
+	if (supported != 0xff)
+		return supported;
+
+	// PSCI_FEATURES mandatory from PSCI 1.0
+	smc_ret = smc_call0(PSCI_VERSION);
+	if (smc_ret < 0x10000)
+		goto fail;
+
+	smc_ret = smc_call1(PSCI_FEATURES, SMCCC_VERSION);
+	if (smc_ret == PSCI_NOT_SUPPORTED)
+		goto fail;
+
+	// SMCCC_ARCH_FEATURES supported from SMCCC 1.1
+	smc_ret = smc_call0(SMCCC_VERSION);
+	if (smc_ret < 0x10001)
+		goto fail;
+
+	smc_ret = smc_call1(SMCCC_ARCH_FEATURES, SMCCC_ARCH_SOC_ID);
+	if (smc_ret != SMC_SUCCESS)
+		goto fail;
+
+	supported = 1;
+	return supported;
+
+fail:
+	supported = 0;
+	return supported;
+}
+
+enum cb_err smccc_arch_soc_id(uint32_t *jep106code, uint32_t *soc_revision)
+{
+	uint64_t smc_ret;
+
+	if (jep106code == NULL || soc_revision == NULL)
+		return CB_ERR_ARG;
+
+	smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_VERSION);
+	if (smc_ret != SMC_INVALID_PARAMETER)
+		*jep106code = smc_ret;
+	else
+		*jep106code = -1;
+
+	smc_ret = smc_call1(SMCCC_ARCH_SOC_ID, SMCCC_GET_SOC_REVISION);
+	if (smc_ret != SMC_INVALID_PARAMETER)
+		*soc_revision = smc_ret;
+	else
+		*soc_revision = -1;
+
+	if (*jep106code == -1 || *soc_revision == -1) {
+		printk(BIOS_ERR, "SMCCC_ARCH_SOC_ID failed!\n");
+		return CB_ERR;
+	} else
+		return CB_SUCCESS;
+}

src/arch/arm64/smc_asm.S

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/asm.h>
+
+ENTRY(smc)
+	/* W0, X1-X7 passed as arguments. Function ID is always W0. */
+	smc	#0
+	ret			/* X0 passed back as return value */
+ENDPROC(smc)

src/arch/arm64/tables.c

@@ -6,6 +6,9 @@
 #include <boot/tables.h>
 #include <bootmem.h>
 #include <cbmem.h>
+#include <console/console.h>
+#include <smbios.h>
+#include <string.h>
 #include <symbols.h>
 
 static void write_acpi_table(void)
@@ -18,10 +21,40 @@ static void write_acpi_table(void)
 	printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", acpi_end - acpi_start);
 }
 
+static void write_smbios_table(void)
+{
+	unsigned long smbios_begin, smbios_end;
+
+#define MAX_SMBIOS_SIZE (32 * KiB)
+
+	smbios_begin = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE);
+	if (!smbios_begin) {
+		printk(BIOS_ERR, "Out of memory for SMBIOS tables\n");
+		return;
+	}
+
+	/*
+	 * Clear the entire region to ensure the unused space doesn't
+	 * contain garbage from a previous boot, like stale table
+	 * signatures that could be found by the OS.
+	 */
+	memset((void *)smbios_begin, 0, MAX_SMBIOS_SIZE);
+
+	smbios_end = smbios_write_tables(smbios_begin);
+
+	if (smbios_end > (smbios_begin + MAX_SMBIOS_SIZE))
+		printk(BIOS_ERR, "Increase SMBIOS size\n");
+
+	printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", smbios_end - smbios_begin);
+}
+
 void arch_write_tables(uintptr_t coreboot_table)
 {
 	if (CONFIG(HAVE_ACPI_TABLES))
 		write_acpi_table();
+
+	if (CONFIG(GENERATE_SMBIOS_TABLES))
+		write_smbios_table();
 }
 
 void bootmem_arch_add_ranges(void)

src/arch/riscv/include/vm.h

@@ -3,7 +3,6 @@
 #ifndef _VM_H
 #define _VM_H
 
-#include <string.h>
 #include <stdint.h>
 #include <arch/encoding.h>
 

src/arch/x86/acpi.c

@@ -12,7 +12,8 @@ static u16 acpi_sci_int(void)
 
 	ioapic_get_sci_pin(&gsi, &irq, &flags);
 
-	/* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */
+	/* In systems without 8259, the SCI_INT field in the FADT contains the SCI GSI number
+	   instead of the 8259 IRQ number */
 	if (!CONFIG(ACPI_HAVE_PCAT_8259))
 		return gsi;
 

src/arch/x86/smbios.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <string.h>
 #include <smbios.h>
 #include <console/console.h>
 #include <arch/cpu.h>
 #include <cpu/x86/name.h>
+#include <stdio.h>
 
 static int smbios_cpu_vendor(u8 *start)
 {
@@ -68,7 +68,7 @@ static int get_socket_type(void)
 
 unsigned int __weak smbios_processor_family(struct cpuid_result res)
 {
-	return (res.eax > 0) ? 0x0c : 0x6;
+	return (res.eax > 0) ? SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO : SMBIOS_PROCESSOR_FAMILY_INTEL486;
 }
 
 static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
@@ -126,7 +126,7 @@ int smbios_write_type4(unsigned long *current, int handle)
 	t->processor_manufacturer = smbios_cpu_vendor(t->eos);
 	t->processor_version = smbios_processor_name(t->eos);
 	t->processor_family = smbios_processor_family(res);
-	t->processor_type = 3; /* System Processor */
+	t->processor_type = SMBIOS_PROCESSOR_TYPE_CENTRAL;
 	/*
 	 * If CPUID leaf 11 is available, calculate "core count" by dividing
 	 * SMT_ID (logical processors in a core) by Core_ID (number of cores).

src/console/vsprintf.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/vtxprintf.h>
-#include <string.h>
+#include <stdio.h>
 
 struct vsnprintf_context {
 	char *str_buf;

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -190,17 +190,26 @@ static void configure_c_states(struct device *dev)
 
 		/* C3 Interrupt Response Time Limit */
 		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
 		wrmsr(MSR_PKGC3_IRTL, msr);
 
 		/* C6 Interrupt Response Time Limit */
 		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
 		wrmsr(MSR_PKGC6_IRTL, msr);
 
 		/* C7 Interrupt Response Time Limit */
 		msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
 		wrmsr(MSR_PKGC7_IRTL, msr);
 
 		/* Primary Plane Current Limit (Icc) */

src/cpu/x86/pae/pgtbl.c

@@ -100,6 +100,97 @@ void paging_disable_pae(void)
 	write_cr4(cr4);
 }
 
+/*
+ * Prepare PAE pagetables that identity map the whole 32-bit address space using
+ * 2 MiB pages. The PAT are set to all cacheable, but MTRRs still apply. CR3 is
+ * loaded and PAE is enabled by this function.
+ *
+ * Requires a scratch memory for pagetables.
+ *
+ * @param pgtbl     Where pagetables reside, must be 4 KiB aligned and 20 KiB in
+ *                  size.
+ *                  Content at physical address isn't preserved.
+ * @return 0 on success, 1 on error
+ */
+int init_pae_pagetables(void *pgtbl)
+{
+	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
+	struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp;
+
+	printk(BIOS_DEBUG, "%s: Using address %p for page tables\n",
+	       __func__, pgtbl_buf);
+
+	/* Cover some basic error conditions */
+	if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB)) {
+		printk(BIOS_ERR, "%s: Invalid alignment\n", __func__);
+		return 1;
+	}
+
+	paging_disable_pae();
+
+	/* Point the page directory pointers at the page directories. */
+	memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp));
+
+	pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES;
+	pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES;
+	pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES;
+	pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES;
+
+	/* Identity map the whole 32-bit address space */
+	for (size_t i = 0; i < 2048; i++) {
+		pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW;
+		pd[i].addr_hi = 0;
+	}
+
+	paging_enable_pae_cr3((uintptr_t)pdp);
+
+	return 0;
+}
+
+/*
+ * Map single 2 MiB page in pagetables created by init_pae_pagetables().
+ *
+ * The function does not check if the page was already non identity mapped,
+ * this allows callers to reuse one page without having to explicitly unmap it
+ * between calls.
+ *
+ * @param pgtbl     Where pagetables created by init_pae_pagetables() reside.
+ *                  Content at physical address is preserved except for single
+ *                  entry corresponding to vmem_addr.
+ * @param paddr     Physical memory address to map. Function prints a warning if
+ *                  it isn't aligned to 2 MiB.
+ * @param vmem_addr Where the virtual non identity mapped page resides, must
+ *                  be at least 2 MiB in size. Function prints a warning if it
+ *                  isn't aligned to 2 MiB.
+ *                  Content at physical address is preserved.
+ * @return 0 on success, 1 on error
+ */
+void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr)
+{
+	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
+	struct pde *pd;
+
+	if (!IS_ALIGNED(paddr, s2MiB)) {
+		printk(BIOS_WARNING, "%s: Aligning physical address to 2MiB\n",
+		       __func__);
+		paddr = ALIGN_DOWN(paddr, s2MiB);
+	}
+
+	if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
+		printk(BIOS_WARNING, "%s: Aligning virtual address to 2MiB\n",
+		       __func__);
+		vmem_addr = (void *)ALIGN_DOWN((uintptr_t)vmem_addr, s2MiB);
+	}
+
+	/* Map a page using PAE at virtual address vmem_addr. */
+	pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT];
+	pd->addr_lo = paddr | PDE_PS | PDE_PRES | PDE_RW;
+	pd->addr_hi = paddr >> 32;
+
+	/* Update page tables */
+	asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory");
+}
+
 /*
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
@@ -130,22 +221,18 @@ void paging_disable_pae(void)
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 	       void *vmem_addr)
 {
-	struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl;
 	ssize_t offset;
+	const uintptr_t pgtbl_s = (uintptr_t)pgtbl;
+	const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table);
 
 	printk(BIOS_DEBUG, "%s: Using virtual address %p as scratchpad\n",
 	       __func__, vmem_addr);
-	printk(BIOS_DEBUG, "%s: Using address %p for page tables\n",
-	       __func__, pgtbl_buf);
 
 	/* Cover some basic error conditions */
-	if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB) ||
+	if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
-	    !IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) {
 		printk(BIOS_ERR, "%s: Invalid alignment\n", __func__);
 		return 1;
 	}
-	const uintptr_t pgtbl_s = (uintptr_t)pgtbl_buf;
-	const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table);
 
 	if (OVERLAP(dest, dest + length, pgtbl_s, pgtbl_e)) {
 		printk(BIOS_ERR, "%s: destination overlaps page tables\n",
@@ -160,31 +247,12 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 		return 1;
 	}
 
-	paging_disable_pae();
+	if (init_pae_pagetables(pgtbl))
-
+		return 1;
-	struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp;
-	/* Point the page directory pointers at the page directories. */
-	memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp));
-
-	pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES;
-	pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES;
-	pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES;
-	pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES;
 
 	offset = dest - ALIGN_DOWN(dest, s2MiB);
 	dest = ALIGN_DOWN(dest, s2MiB);
 
-	/* Identity map the whole 32-bit address space */
-	for (size_t i = 0; i < 2048; i++) {
-		pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW;
-		pd[i].addr_hi = 0;
-	}
-
-	/* Get pointer to PD that's not identity mapped */
-	pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT];
-
-	paging_enable_pae_cr3((uintptr_t)pdp);
-
 	do {
 		const size_t len = MIN(length, s2MiB - offset);
 
@@ -192,11 +260,7 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
 		 * Map a page using PAE at virtual address vmem_addr.
 		 * dest is already 2 MiB aligned.
 		 */
-		pd->addr_lo = dest | PDE_PS | PDE_PRES | PDE_RW;
+		pae_map_2M_page(pgtbl, dest, vmem_addr);
-		pd->addr_hi = dest >> 32;
-
-		/* Update page tables */
-		asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory");
 
 		printk(BIOS_SPEW, "%s: Clearing %llx[%lx] - %zx\n", __func__,
 		       dest + offset, (uintptr_t)vmem_addr + offset, len);
@@ -277,177 +341,3 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name)
 
 	return 0;
 }
-
-static void *get_pdpt_addr(void)
-{
-	if (preram_symbols_available())
-		return _pdpt;
-	return (void *)(uintptr_t)read_cr3();
-}
-
-static uint64_t pde_pat_flags(int pat)
-{
-	switch (pat) {
-	case PAT_UC:
-		return 0 | PDE_PCD | PDE_PWT;
-	case PAT_WC:
-		return 0 | 0 | PDE_PWT;
-	case PAT_WT:
-		return PDE_PAT | PDE_PCD | PDE_PWT;
-	case PAT_WP:
-		return PDE_PAT | 0 | PDE_PWT;
-	case PAT_WB:
-		return 0 | 0 | 0;
-	case PAT_UC_MINUS:
-		return 0 | PDE_PCD | 0;
-	default:
-		printk(BIOS_ERR, "PDE PAT defaulting to WB: %x\n", pat);
-		return pde_pat_flags(PAT_WB);
-	}
-}
-
-static uint64_t pde_page_flags(int pat)
-{
-	uint64_t flags = PDE_PS | PDE_PRES | PDE_RW | PDE_A | PDE_D;
-
-	return flags | pde_pat_flags(pat);
-}
-
-static uint64_t pte_pat_flags(int pat)
-{
-	switch (pat) {
-	case PAT_UC:
-		return 0 | PTE_PCD | PTE_PWT;
-	case PAT_WC:
-		return 0 | 0 | PTE_PWT;
-	case PAT_WT:
-		return PTE_PAT | PTE_PCD | PTE_PWT;
-	case PAT_WP:
-		return PTE_PAT | 0 | PTE_PWT;
-	case PAT_WB:
-		return 0 | 0 | 0;
-	case PAT_UC_MINUS:
-		return 0 | PTE_PCD | 0;
-	default:
-		printk(BIOS_ERR, "PTE PAT defaulting to WB: %x\n", pat);
-		return pte_pat_flags(PAT_WB);
-	}
-}
-
-static uint64_t pte_page_flags(int pat)
-{
-	uint64_t flags = PTE_PRES | PTE_RW | PTE_A | PTE_D;
-	return flags | pte_pat_flags(pat);
-}
-
-/* Identity map an address. This function does not handle splitting or adding
- * new pages to the page tables. It's assumed all the page tables are already
- * seeded with the correct amount and topology. */
-static int identity_map_one_page(uintptr_t base, size_t size, int pat,
-				int commit)
-{
-	uint64_t (*pdpt)[4];
-	uint64_t pdpte;
-	uint64_t (*pd)[512];
-	uint64_t pde;
-
-	pdpt = get_pdpt_addr();
-
-	pdpte = (*pdpt)[(base >> PDPTE_IDX_SHIFT) & PDPTE_IDX_MASK];
-
-	/* No page table page allocation. */
-	if (!(pdpte & PDPTE_PRES))
-		return -1;
-
-	pd = (void *)(uintptr_t)(pdpte & PDPTE_ADDR_MASK);
-
-	/* Map in a 2MiB page. */
-	if (size == s2MiB) {
-		if (!commit)
-			return 0;
-		pde = base;
-		pde |= pde_page_flags(pat);
-		(*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK] = pde;
-		return 0;
-	}
-
-	if (size == s4KiB) {
-		uint64_t (*pt)[512];
-		uint64_t pte;
-
-		pde = (*pd)[(base >> PDE_IDX_SHIFT) & PDE_IDX_MASK];
-
-		/* No page table page allocation. */
-		if (!(pde & PDE_PRES)) {
-			printk(BIOS_ERR, "Cannot allocate page table for pde %p\n",
-				(void *)base);
-			return -1;
-		}
-
-		/* No splitting pages */
-		if (pde & PDE_PS) {
-			printk(BIOS_ERR, "Cannot split pde %p\n", (void *)base);
-			return -1;
-		}
-
-		if (!commit)
-			return 0;
-
-		pt = (void *)(uintptr_t)(pde & PDE_ADDR_MASK);
-		pte = base;
-		pte |= pte_page_flags(pat);
-		(*pt)[(base >> PTE_IDX_SHIFT) & PTE_IDX_MASK] = pte;
-
-		return 0;
-	}
-
-	return -1;
-}
-
-static int _paging_identity_map_addr(uintptr_t base, size_t size, int pat,
-					int commit)
-{
-	while (size != 0) {
-		size_t map_size;
-
-		map_size = IS_ALIGNED(base, s2MiB) ? s2MiB : s4KiB;
-		map_size = MIN(size, map_size);
-
-		if (identity_map_one_page(base, map_size, pat, commit) < 0)
-			return -1;
-
-		base += map_size;
-		size -= map_size;
-	}
-
-	return 0;
-}
-
-static int paging_is_enabled(void)
-{
-	return !!(read_cr0() & CR0_PG);
-}
-
-int paging_identity_map_addr(uintptr_t base, size_t size, int pat)
-{
-	if (!paging_is_enabled()) {
-		printk(BIOS_ERR, "Paging is not enabled.\n");
-		return -1;
-	}
-
-	if (!IS_ALIGNED(base, s2MiB) && !IS_ALIGNED(base, s4KiB)) {
-		printk(BIOS_ERR, "base %p is not aligned.\n", (void *)base);
-		return -1;
-	}
-
-	if (!IS_ALIGNED(size, s2MiB) && !IS_ALIGNED(size, s4KiB)) {
-		printk(BIOS_ERR, "size %zx is not aligned.\n", size);
-		return -1;
-	}
-
-	/* First try without committing. If success commit. */
-	if (_paging_identity_map_addr(base, size, pat, 0))
-		return -1;
-
-	return _paging_identity_map_addr(base, size, pat, 1);
-}

src/cpu/x86/smm/smm_module_loader.c

@@ -11,6 +11,7 @@
 #include <device/mmio.h>
 #include <rmodule.h>
 #include <smmstore.h>
+#include <stdio.h>
 #include <string.h>
 #include <types.h>
 

src/device/Kconfig

@@ -846,18 +846,18 @@ config VGA_BIOS_ID
 	depends on VGA_BIOS
 	default "1106,3230"
 	help
-	  The comma-separated PCI vendor and device ID with optional revision if that
+	  The comma-separated PCI vendor and device ID that would associate
-	  feature is enabled that would associate your vBIOS to your video card.
+	  your vBIOS to your video card.
 
-	  Example: 1106,3230 or 1106,3230,a3
+	  Example: 1106,3230
 
 	  In the above example 1106 is the PCI vendor ID (in hex, but without
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
-	  video card (also in hex, without "0x" prefix). a3 specifies the revision.
+	  video card (also in hex, without "0x" prefix).
 
 	  This ID needs to match the PCI VID and DID in the VGA BIOS file's
 	  header and also needs to match the value returned by map_oprom_vendev
-	  or map_oprom_vendev_rev if the remapping feature is used.
+	  if the remapping feature is used.
 
 	  Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 
@@ -879,23 +879,17 @@ config VGA_BIOS_SECOND_ID
 	string "Graphics device PCI IDs"
 	depends on VGA_BIOS_SECOND
 	help
-	  The comma-separated PCI vendor and device ID with optional revision if that
+	  The comma-separated PCI vendor and device ID that would associate
-	  feature is enabled that would associate your vBIOS to your video card.
+	  your vBIOS to your video card.
 
-	  Example: 1106,3230 or 1106,3230,a3
+	  Example: 1106,3230
 
 	  In the above example 1106 is the PCI vendor ID (in hex, but without
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
-	  video card (also in hex, without "0x" prefix). a3 specifies the revision.
+	  video card (also in hex, without "0x" prefix).
 
 	  Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 
-config CHECK_REV_IN_OPROM_NAME
-	def_bool n
-	help
-	  Select this in the platform BIOS or chipset if the option rom has a revision
-	  that needs to be checked when searching CBFS.
-
 config VGA_BIOS_DGPU
 	bool "Add a discrete VGA BIOS image"
 	depends on VGA_BIOS

src/device/device_util.c

@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <types.h>
@@ -776,7 +777,7 @@ void show_all_devs_resources(int debug_level, const char *msg)
 	}
 }
 
-const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
+const struct resource *resource_range_idx(struct device *dev, unsigned long index,
 				uint64_t base, uint64_t size, unsigned long flags)
 {
 	struct resource *resource;
@@ -785,8 +786,13 @@ const struct resource *fixed_resource_range_idx(struct device *dev, unsigned lon
 
 	resource = new_resource(dev, index);
 	resource->base = base;
-	resource->size = size;
+
-	resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
+	if (flags & IORESOURCE_FIXED)
+		resource->size = size;
+	if (flags & IORESOURCE_BRIDGE)
+		resource->limit = base + size - 1;
+
+	resource->flags = IORESOURCE_ASSIGNED;
 	resource->flags |= flags;
 
 	printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n",

src/device/pci_rom.c

@@ -6,13 +6,13 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <stdio.h>
 #include <string.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <acpi/acpigen.h>
 
 /* Rmodules don't like weak symbols. */
-void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; }
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
 void vga_oprom_preload(void)
@@ -39,34 +39,26 @@ static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 	return cbfs_map(name, NULL);
 }
 
-static void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev)
-{
-	char name[20] = "pciXXXX,XXXX,XX.rom";
-
-	snprintf(name, sizeof(name), "pci%04hx,%04hx,%02hhx.rom", vendor, device, rev);
-
-	return cbfs_map(name, NULL);
-}
-
 struct rom_header *pci_rom_probe(const struct device *dev)
 {
 	struct rom_header *rom_header = NULL;
 	struct pci_data *rom_data;
-	u8 rev = pci_read_config8(dev, PCI_REVISION_ID);
-	u8 mapped_rev = rev;
 	u32 vendev = (dev->vendor << 16) | dev->device;
 	u32 mapped_vendev = vendev;
 
 	/* If the ROM is in flash, then don't check the PCI device for it. */
-	if (CONFIG(CHECK_REV_IN_OPROM_NAME)) {
+	mapped_vendev = map_oprom_vendev(vendev);
-		map_oprom_vendev_rev(&mapped_vendev, &mapped_rev);
+	rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16, mapped_vendev & 0xffff);
-		rom_header = cbfs_boot_map_optionrom_revision(mapped_vendev >> 16,
+
-							      mapped_vendev & 0xffff,
+	/* Handle the case of VGA_BIOS_ID not being set to the remapped PCI ID. This is a
-							      mapped_rev);
+	   workaround that should be removed once the underlying issue is fixed. */
-	} else {
+	if (!rom_header && vendev != mapped_vendev) {
-		mapped_vendev = map_oprom_vendev(vendev);
+		rom_header = cbfs_boot_map_optionrom(vendev >> 16, vendev & 0xffff);
-		rom_header = cbfs_boot_map_optionrom(mapped_vendev >> 16,
+		if (rom_header) {
-						     mapped_vendev & 0xffff);
+			printk(BIOS_NOTICE, "VGA_BIOS_ID should be the remapped PCI ID "
+					    "%04hx,%04hx in the VBIOS file\n",
+			       mapped_vendev >> 16, mapped_vendev & 0xffff);
+		}
 	}
 
 	if (rom_header) {

src/drivers/acpi/thermal_zone/thermal_zone.c

@@ -5,8 +5,8 @@
 #include <commonlib/bsd/helpers.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <stdio.h>
 #include <stdlib.h>
-#include <string.h>
 
 #include "chip.h"
 

src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c

@@ -3,7 +3,8 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 #include <console/console.h>
 

src/drivers/generic/gpio_keys/gpio_keys.c

@@ -3,7 +3,7 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/cs35l53/cs35l53.c

@@ -6,6 +6,7 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/generic/generic.c

@@ -7,7 +7,8 @@
 #include <device/i2c_simple.h>
 #include <device/device.h>
 #include <gpio.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #if CONFIG(HAVE_ACPI_TABLES)

src/drivers/i2c/gpiomux/bus/bus.c

@@ -4,7 +4,7 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/gpiomux/mux/mux.c

@@ -4,7 +4,7 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/hid/hid.c

@@ -4,7 +4,8 @@
 #include <acpi/acpi_device.h>
 #include <assert.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 #include <gpio.h>
 #include <console/console.h>

src/drivers/i2c/max98390/max98390.c

@@ -7,6 +7,7 @@
 #include <device/device.h>
 #include <identity.h>
 #include <stdint.h>
+#include <stdio.h>
 #include <vendorcode/google/dsm_calib.h>
 #include "chip.h"
 

src/drivers/i2c/max98396/max98396.c

@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/i2c/rt1011/rt1011.c

@@ -6,6 +6,7 @@
 #include <device/i2c.h>
 #include <device/device.h>
 #include <stdint.h>
+#include <stdio.h>
 #include <vendorcode/google/dsm_calib.h>
 #include "chip.h"
 

src/drivers/i2c/rt5645/rt5645.c

@@ -4,6 +4,8 @@
 #include <acpi/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #define RT5645_ACPI_NAME	"RT58"

src/drivers/i2c/sx9310/sx9310.c

@@ -5,7 +5,8 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #define I2C_SX9310_ACPI_ID	"STH9310"

src/drivers/i2c/sx9324/sx9324.c

@@ -5,7 +5,8 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #define I2C_SX9324_ACPI_ID	"STH9324"

src/drivers/i2c/sx9360/sx9360.c

@@ -5,7 +5,8 @@
 #include <console/console.h>
 #include <device/i2c_simple.h>
 #include <device/device.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #define I2C_SX9360_ACPI_ID	"STH9360"

src/drivers/i2c/tpm/cr50.c

@@ -498,7 +498,7 @@ tpm_result_t tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t d
 	if (rc)
 		return rc;
 
-	printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id %#x)\n",
+	printk(BIOS_DEBUG, "GSC TPM 2.0 (i2c %u:0x%02x id %#x)\n",
 	       bus, dev_addr, did_vid >> 16);
 
 	if (tpm_first_access_this_boot()) {

src/drivers/intel/dptf/dptf.c

@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <intelblocks/pmc_ipc.h>
+#include <stdio.h>
 #include <soc/dptf.h>
 #include <soc/pci_devs.h>
 #include "chip.h"

src/drivers/intel/fsp2_0/silicon_init.c

@@ -77,7 +77,7 @@ bool fsp_is_multi_phase_init_enabled(void)
 
 static void fsp_fill_common_arch_params(FSPS_UPD *supd)
 {
-#if CONFIG(FSPS_HAS_ARCH_UPD)
+#if (CONFIG(FSPS_HAS_ARCH_UPD) && !CONFIG(PLATFORM_USES_FSP2_4))
 	FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd;
 	s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
 #endif

src/drivers/intel/fsp2_0/util.c

@@ -8,6 +8,7 @@
 #include <commonlib/fsp.h>
 #include <console/console.h>
 #include <fsp/util.h>
+#include <stdio.h>
 #include <string.h>
 #include <types.h>
 #include <assert.h>

src/drivers/intel/gma/acpi.c

@@ -1,7 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <acpi/acpigen.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "i915.h"
 
 void

src/drivers/intel/mipi_camera/camera.c

@@ -9,6 +9,8 @@
 #include <device/i2c_simple.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 #define CSI2_DATA_STREAM_INTERFACE_GUID \

src/drivers/intel/pmc_mux/conn/conn.c

@@ -7,6 +7,7 @@
 #include <console/console.h>
 #include <drivers/usb/acpi/chip.h>
 #include <intelblocks/acpi.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/intel/usb4/retimer/retimer.c

@@ -7,7 +7,8 @@
 #include <device/device.h>
 #include <drivers/usb/acpi/chip.h>
 #include <gpio.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 #include "retimer.h"
 

src/drivers/nxp/uwb/uwb.c

@@ -6,7 +6,8 @@
 #include <device/device.h>
 #include <device/spi.h>
 #include <spi-generic.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 static int spi_acpi_get_bus(const struct device *dev)

src/drivers/ocp/dmi/smbios.c

@@ -6,6 +6,7 @@
 #include <delay.h>
 #include <cpu/x86/mp.h>
 #include <timer.h>
+#include <stdio.h>
 #include <string.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>

src/drivers/spi/acpi/acpi.c

@@ -6,7 +6,8 @@
 #include <device/device.h>
 #include <device/spi.h>
 #include <spi-generic.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 static int spi_acpi_get_bus(const struct device *dev)

src/drivers/uart/acpi/acpi.c

@@ -3,7 +3,8 @@
 #include <acpi/acpi_device.h>
 #include <acpi/acpigen.h>
 #include <console/console.h>
-#include <string.h>
+#include <stdio.h>
+
 #include "chip.h"
 
 static bool uart_acpi_add_gpios_to_crs(struct drivers_uart_acpi_config *config)

src/drivers/uart/oxpcie_early.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
-#include <stddef.h>
 #include <device/pci_ops.h>
 #include <console/uart.h>
 #include <device/pci.h>

src/drivers/usb/hub/acpi.c

@@ -2,6 +2,7 @@
 
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
+#include <stdio.h>
 
 #include "chip.h"
 

src/drivers/usb/pci_xhci/pci_xhci.c

@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/xhci.h>
+#include <stdio.h>
 #include <stdlib.h>
 
 #define PCI_XHCI_CLASSCODE	0x0c0330 /* USB3.0 xHCI controller */

src/drivers/wifi/generic/acpi.c

@@ -7,6 +7,7 @@
 #include <device/pci_ids.h>
 #include <mtcl.h>
 #include <sar.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <wrdd.h>
 

src/ec/clevo/it5570e/ssdt.c

@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/mmio.h>
+#include <stdio.h>
 
 #include "chip.h"
 #include "ec.h"

src/ec/dasharo/ec/Kconfig

@@ -0,0 +1,21 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config EC_DASHARO_EC
+	bool
+	help
+	  Dasharo EC
+
+config EC_DASHARO_EC_BAT_THRESHOLDS
+	depends on EC_DASHARO_EC
+	bool
+	default y
+
+config EC_DASHARO_EC_DGPU
+	depends on EC_DASHARO_EC
+	bool
+	default n
+
+config EC_DASHARO_EC_OLED
+	depends on EC_DASHARO_EC
+	bool
+	default n

src/ec/dasharo/ec/Makefile.mk

@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_EC_DASHARO_EC),y)
+
+all-y += dasharo_ec.c
+
+ramstage-y += smbios.c
+
+smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c
+
+endif

src/ec/dasharo/ec/acpi/ac.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003" /* Power Source Device */)
+	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
+	{
+		_SB
+	})
+
+	Name (ACFG, 1)
+
+	Method (_PSR, 0, NotSerialized)  // _PSR: Power Source
+	{
+		Return (ACFG)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}

src/ec/dasharo/ec/acpi/battery.asl

@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (BAT0)
+{
+	Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */)
+	Name (_UID, 0)
+	Name (_PCL, Package (0x01)  // _PCL: Power Consumer List
+	{
+		_SB
+	})
+	Name (BFCC, 0)
+	Method (_STA, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			If (^^PCI0.LPCB.EC0.BAT0)
+			{
+				Return (0x1F)
+			}
+			Else
+			{
+				Return (0x0F)
+			}
+		}
+		Else
+		{
+			Return (0x0F)
+		}
+	}
+
+	Name (PBIF, Package (0x0D)
+	{
+		1, // 0 - Power Unit
+		0xFFFFFFFF, // 1 - Design Capacity
+		0xFFFFFFFF, // 2 - Last Full Charge Capacity
+		1, // 3 - Battery Technology
+		0xFFFFFFFF, // 4 - Design Voltage
+		0, // 5 - Design Capacity of Warning
+		0, // 6 - Design Capacity of Low
+		0x40, // 7 - Battery Capacity Granularity 1
+		0x40, // 8 - Battery Capacity Granularity 2
+		" ", // 9 - Model Number
+		" ", // 10 - Serial Number
+		" ", // 11 - Battery Type
+		" " // 12 - OEM Information
+	})
+	Method (IVBI, 0, NotSerialized)
+	{
+		PBIF [1] = 0xFFFFFFFF
+		PBIF [2] = 0xFFFFFFFF
+		PBIF [4] = 0xFFFFFFFF
+		PBIF [9] = " "
+		PBIF [10] = " "
+		PBIF [11] = " "
+		PBIF [12] = " "
+		BFCC = 0
+	}
+
+	Method (UPBI, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+			PBIF [1] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+			PBIF [2] = Local0
+			BFCC = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+			PBIF [4] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+			PBIF [5] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+			PBIF [6] = Local0
+			PBIF [9] = "BAT"
+			PBIF [10] = "0001"
+			PBIF [11] = "LION"
+			PBIF [12] = "Notebook"
+		}
+		Else
+		{
+			IVBI ()
+		}
+	}
+
+	Method (_BIF, 0, NotSerialized)  // _BIF: Battery Information
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBI ()
+		}
+		Else
+		{
+			IVBI ()
+		}
+
+		Return (PBIF) /* \_SB_.BAT0.PBIF */
+	}
+
+	Name (PBIX, Package ()
+	{
+		0, // 0 - Revision
+		1, // 1 - Power Unit: mAh
+		0xFFFFFFFF, // 2 - Design Capacity
+		0xFFFFFFFF, // 3 - Last Full Charge Capacity
+		1, // 4 - Battery Technology: Rechargeable
+		0xFFFFFFFF, // 5 - Design Voltage
+		0, // 6 - Design Capacity of Warning
+		0, // 7 - Design Capacity of Low
+		0, // 8 - Cycle Count
+		98000, // 9 - Measurement Accuracy
+		0xFFFFFFFF, // 10 - Max Sampling Time
+		0xFFFFFFFF, // 11 - Min Sampling Time
+		0xFFFFFFFF, // 12 - Max Averaging Interval
+		0xFFFFFFFF, // 13 - Min Averaging Interval
+		0x40, // 14 - Battery Capacity Granularity 1
+		0x40, // 15 - Battery Capacity Granularity 2
+		" ", // 16 - Model Number
+		" ", // 17 - Serial Number
+		" ", // 18 - Battery Type
+		" " // 19 - OEM Information
+	})
+
+	Method (IVBX, 0, NotSerialized)
+	{
+		PBIX [2] = 0xFFFFFFFF
+		PBIX [3] = 0xFFFFFFFF
+		PBIX [5] = 0xFFFFFFFF
+		PBIX [16] = " "
+		PBIX [17] = " "
+		PBIX [18] = " "
+		PBIX [19] = " "
+		BFCC = 0
+	}
+
+	Method (UPBX, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
+			PBIX [2] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
+			PBIX [3] = Local0
+			BFCC = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
+			PBIX [5] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
+			PBIX [6] = Local0
+			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
+			PBIX [7] = Local0
+			LOCAL0 = ^^PCI0.LPCB.EC0.CYC0
+			PBIX [8] = LOCAL0
+			PBIX [16] = "BAT"
+			PBIX [17] = "0001"
+			PBIX [18] = "LION"
+			PBIX [19] = "Notebook"
+		}
+		Else
+		{
+			IVBX ()
+		}
+	}
+
+	// _BIX: Battery Information Extended
+	Method (_BIX, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBX ()
+		}
+		Else
+		{
+			IVBX ()
+		}
+		Return (PBIX) /* \_SB_.BAT0.PBIX */
+	}
+
+	Name (PBST, Package (0x04)
+	{
+		0, // 0 - Battery state
+		0xFFFFFFFF, // 1 - Battery present rate
+		0xFFFFFFFF, // 2 - Battery remaining capacity
+		0xFFFFFFFF // 3 - Battery present voltage
+	})
+	Method (IVBS, 0, NotSerialized)
+	{
+		PBST [0] = 0
+		PBST [1] = 0xFFFFFFFF
+		PBST [2] = 0xFFFFFFFF
+		PBST [3] = 0xFFFFFFFF
+	}
+
+	Method (UPBS, 0, NotSerialized)
+	{
+		If (^^PCI0.LPCB.EC0.BAT0)
+		{
+			Local0 = 0
+			Local1 = 0
+			If (^^AC.ACFG)
+			{
+				If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02))
+				{
+					Local0 |= 0x02
+					Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+				}
+			}
+			Else
+			{
+				Local0 |= 1
+				Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF)
+			}
+
+			Local7 = (Local1 & 0x8000)
+			If ((Local7 == 0x8000))
+			{
+				Local1 ^= 0xFFFF
+			}
+
+			Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
+			Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
+			PBST [0] = Local0
+			PBST [1] = Local1
+			PBST [2] = Local2
+			PBST [3] = Local3
+			If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
+			{
+				Notify (BAT0, 0x81) // Information Change
+			}
+		}
+		Else
+		{
+			IVBS ()
+		}
+	}
+
+	Method (_BST, 0, NotSerialized)  // _BST: Battery Status
+	{
+		If (^^PCI0.LPCB.EC0.ECOK)
+		{
+			UPBS ()
+		}
+		Else
+		{
+			IVBS ()
+		}
+
+		Return (PBST) /* \_SB_.BAT0.PBST */
+	}
+}

src/ec/dasharo/ec/acpi/battery_thresholds.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Field (ERAM, ByteAcc, Lock, Preserve)
+{
+	Offset (0xBC),
+	BTL0,   8,      /* BAT0 charging start threshold */
+	BTH0,   8,      /* BAT0 charging end threshold */
+}
+
+/*
+ * Get battery charging threshold
+ *
+ * Arg0: 0: Start threshold
+ *       1: Stop threshold
+ */
+Method (GBCT, 1, NotSerialized)
+{
+	If (Arg0 == 0) {
+		Return (BTL0)
+	}
+
+	If (Arg0 == 1) {
+		Return (BTH0)
+	}
+
+	Return (0xFF)
+}
+
+/*
+ * Set battery charging threshold
+ *
+ * Arg0: 0: Start threshold
+ *       1: Stop threshold
+ * Arg1: Percentage
+ */
+Method (SBCT, 2, NotSerialized)
+{
+	If (Arg1 <= 100) {
+		If (Arg0 == 0) {
+			BTL0 = Arg1
+		}
+		If (Arg0 == 1) {
+			BTH0 = Arg1
+		}
+	}
+}

src/ec/dasharo/ec/acpi/buttons.asl

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (PWRB)
+{
+	Name (_HID, EisaId ("PNP0C0C"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+}
+
+Device (SLPB)
+{
+	Name (_HID, EisaId ("PNP0C0E"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+}

src/ec/dasharo/ec/acpi/ec.asl

@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "ac.asl"
+	#include "battery.asl"
+	#include "buttons.asl"
+	#include "hid.asl"
+	#include "lid.asl"
+	#include "s76.asl"
+}
+
+Device (\_SB.PCI0.LPCB.EC0)
+{
+	Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */)
+	Name (_GPE, EC_GPE_SCI)  // _GPE: General Purpose Events
+	Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+	{
+		IO (Decode16,
+			0x0062,             // Range Minimum
+			0x0062,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+		IO (Decode16,
+			0x0066,             // Range Minimum
+			0x0066,             // Range Maximum
+			0x00,               // Alignment
+			0x01,               // Length
+			)
+	})
+
+	#include "ec_ram.asl"
+
+	Name (ECOK, 0)
+	Method (_REG, 2, Serialized)  // _REG: Region Availability
+	{
+		Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1))
+		If ((Arg0 == 0x03) && (Arg1 == 1)) {
+			// Enable hardware touchpad lock, airplane mode, and keyboard backlight keys
+			ECOS = 1
+
+			// Enable software display brightness keys
+			WINF = 1
+
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, 0)
+			Notify(^^^^BAT0, 0)
+
+			PNOT ()
+
+			// EC is now available
+			ECOK = Arg1
+
+			// Reset Dasharo Device
+			^^^^S76D.RSET()
+		}
+	}
+
+	Name (S3OS, 0)
+	Method (PTS, 1, Serialized) {
+		Printf ("EC: PTS: %o", ToHexString(Arg0))
+		If (ECOK) {
+			// Save ECOS during sleep
+			S3OS = ECOS
+
+			// Clear wake cause
+			WFNO = 0
+		}
+	}
+
+	Method (WAK, 1, Serialized) {
+		Printf ("EC: WAK: %o", ToHexString(Arg0))
+		If (ECOK) {
+			// Restore ECOS after sleep
+			ECOS = S3OS
+
+			// Set current AC state
+			^^^^AC.ACFG = ADP
+
+			// Update battery information and status
+			^^^^BAT0.UPBI()
+			^^^^BAT0.UPBS()
+
+			// Notify of changes
+			Notify(^^^^AC, 0)
+			Notify(^^^^BAT0, 0)
+		}
+	}
+
+	Method (_Q0A, 0, NotSerialized) // Touchpad Toggle
+	{
+		Printf ("EC: Touchpad Toggle")
+	}
+
+	Method (_Q0B, 0, NotSerialized) // Screen Toggle
+	{
+		Printf ("EC: Screen Toggle")
+#if CONFIG(EC_DASHARO_EC_OLED)
+		Notify (^^^^S76D, 0x85)
+#endif // CONFIG(EC_DASHARO_EC_OLED)
+	}
+
+	Method (_Q0C, 0, NotSerialized)  // Mute
+	{
+		Printf ("EC: Mute")
+	}
+
+	Method (_Q0D, 0, NotSerialized) // Keyboard Backlight
+	{
+		Printf ("EC: Keyboard Backlight")
+	}
+
+	Method (_Q0E, 0, NotSerialized) // Volume Down
+	{
+		Printf ("EC: Volume Down")
+	}
+
+	Method (_Q0F, 0, NotSerialized) // Volume Up
+	{
+		Printf ("EC: Volume Up")
+	}
+
+	Method (_Q10, 0, NotSerialized) // Switch Video Mode
+	{
+		Printf ("EC: Switch Video Mode")
+	}
+
+	Method (_Q11, 0, NotSerialized) // Brightness Down
+	{
+		Printf ("EC: Brightness Down")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (20)
+		}
+	}
+
+	Method (_Q12, 0, NotSerialized) // Brightness Up
+	{
+		Printf ("EC: Brightness Up")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (19)
+		}
+	}
+
+	Method (_Q13, 0, NotSerialized) // Camera Toggle
+	{
+		Printf ("EC: Camera Toggle")
+	}
+
+	Method (_Q14, 0, NotSerialized) // Airplane Mode
+	{
+		Printf ("EC: Airplane Mode")
+		if (^^^^HIDD.HRDY) {
+			^^^^HIDD.HPEM (8)
+		}
+		// TODO: hardware airplane mode
+	}
+
+	Method (_Q15, 0, NotSerialized) // Suspend Button
+	{
+		Printf ("EC: Suspend Button")
+		Notify (SLPB, 0x80)
+	}
+
+	Method (_Q16, 0, NotSerialized) // AC Detect
+	{
+		Printf ("EC: AC Detect")
+		^^^^AC.ACFG = ADP
+		Notify (AC, 0x80) // Status Change
+		If (BAT0)
+		{
+			Notify (^^^^BAT0, 0x81) // Information Change
+			Notify (^^^^BAT0, 0x80) // Status Change
+		}
+	}
+
+	Method (_Q17, 0, NotSerialized)  // BAT0 Update
+	{
+		Printf ("EC: BAT0 Update (17)")
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q19, 0, NotSerialized)  // BAT0 Update
+	{
+		Printf ("EC: BAT0 Update (19)")
+		Notify (^^^^BAT0, 0x81) // Information Change
+	}
+
+	Method (_Q1B, 0, NotSerialized) // Lid Close
+	{
+		Printf ("EC: Lid Close")
+		Notify (LID0, 0x80)
+	}
+
+	Method (_Q1C, 0, NotSerialized) // Thermal Trip
+	{
+		Printf ("EC: Thermal Trip")
+		/* TODO
+		Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change
+		Notify (\_TZ.TZ0, 0x80) // Thermal Status Change
+		*/
+	}
+
+	Method (_Q1D, 0, NotSerialized) // Power Button
+	{
+		Printf ("EC: Power Button")
+		Notify (PWRB, 0x80)
+	}
+
+	Method (_Q50, 0, NotSerialized) // Other Events
+	{
+		Local0 = OEM4
+		If (Local0 == 0x8A) {
+			Printf ("EC: White Keyboard Backlight")
+			Notify (^^^^S76D, 0x80)
+		} ElseIf (Local0 == 0x9F) {
+			Printf ("EC: Color Keyboard Toggle")
+			Notify (^^^^S76D, 0x81)
+		} ElseIf (Local0 == 0x81) {
+			Printf ("EC: Color Keyboard Down")
+			Notify (^^^^S76D, 0x82)
+		} ElseIf (Local0 == 0x82) {
+			Printf ("EC: Color Keyboard Up")
+			Notify (^^^^S76D, 0x83)
+		} ElseIf (Local0 == 0x80) {
+			Printf ("EC: Color Keyboard Color Change")
+			Notify (^^^^S76D, 0x84)
+		} Else {
+			Printf ("EC: Other: %o", ToHexString(Local0))
+		}
+	}
+
+	#if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS)
+	#include "battery_thresholds.asl"
+	#endif
+}

src/ec/dasharo/ec/acpi/ec_ram.asl

@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+OperationRegion (ERAM, EmbeddedControl, 0, 0xFF)
+Field (ERAM, ByteAcc, Lock, Preserve)
+{
+	Offset (0x03),
+	LSTE, 1,	// Lid is open
+	, 1,
+	LWKE, 1,	// Lid wake
+	, 5,
+	Offset (0x07),
+	TMP1, 8,	// CPU temperature
+	Offset (0x10),
+	ADP, 1,		// AC adapter connected
+	, 1,
+	BAT0, 1,	// Battery connected
+	, 5,
+	WFNO, 8,	// Wake cause (not implemented)
+	Offset (0x16),
+	BDC0, 32,	// Battery design capacity
+	BFC0, 32,	// Battery full capacity
+	Offset (0x22),
+	BDV0, 32,	// Battery design voltage
+	BST0, 32,	// Battery status
+	BPR0, 32,	// Battery current
+	BRC0, 32,	// Battery remaining capacity
+	BPV0, 32,	// Battery voltage
+	Offset (0x3A),
+	BCW0, 32,
+	BCL0, 32,
+	CYC0, 16,	// Battery cycle count
+	Offset (0x68),
+	ECOS, 8,	// Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
+	Offset (0xC8),
+	OEM1, 8,
+	OEM2, 8,
+	OEM3, 16,
+	OEM4, 8,	// Extra SCI data
+	Offset (0xCD),
+	TMP2, 8,	// GPU temperature
+	DUT1, 8,	// Fan 1 duty
+	DUT2, 8,	// Fan 2 duty
+	RPM1, 16,	// Fan 1 RPM
+	RPM2, 16,	// Fan 2 RPM
+	Offset (0xD9),
+	AIRP, 8,	// Airplane mode LED
+	WINF, 8,	// Enable ACPI brightness controls
+	Offset (0xF8),
+	FCMD, 8,
+	FDAT, 8,
+	FBUF, 8,
+	FBF1, 8,
+	FBF2, 8,
+	FBF3, 8,
+}

src/ec/dasharo/ec/acpi/hid.asl

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (HIDD)
+{
+	Name (_HID, "INT33D5")
+	Name (HBSY, 0)
+	Name (HIDX, 0)
+	Name (HRDY, 0)
+
+	Method (HDEM, 0, Serialized)
+	{
+		HBSY = 0
+		Return (HIDX)
+	}
+
+	Method (HDMM, 0, Serialized)
+	{
+		Return (0)
+	}
+
+	Method (HDSM, 1, Serialized)
+	{
+		HRDY = Arg0
+	}
+
+	Method (HPEM, 1, Serialized)
+	{
+		HBSY = 1
+		HIDX = Arg0
+
+		Notify (HIDD, 0xC0)
+		Local0 = 0
+		While ((Local0 < 0xFA) && HBSY)
+		{
+			Sleep (0x04)
+			Local0++
+		}
+
+		If (HBSY == 1)
+		{
+			HBSY = 0
+			HIDX = 0
+			Return (1)
+		}
+		Else
+		{
+			Return (0)
+		}
+	}
+}

src/ec/dasharo/ec/acpi/lid.asl

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (LID0)
+{
+	Name (_HID, EisaId ("PNP0C0D"))
+	Name (_PRW, Package () { EC_GPE_SWI, 3 })
+
+	Method (_LID, 0, NotSerialized) {
+		Printf ("LID: _LID")
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			Return (^^PCI0.LPCB.EC0.LSTE)
+		} Else {
+			Return (1)
+		}
+	}
+
+	Method (_PSW, 1, NotSerialized) {
+		Printf ("LID: _PSW: %o", ToHexString(Arg0))
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.LWKE = Arg0
+		}
+	}
+}

src/ec/dasharo/ec/acpi/s76.asl

@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Notifications:
+//   0x80 - hardware backlight toggle
+//   0x81 - backlight toggle
+//   0x82 - backlight down
+//   0x83 - backlight up
+//   0x84 - backlight color change
+//   0x85 - OLED screen toggle
+Device (S76D) {
+	Name (_HID, "17761776")
+	Name (_UID, 0)
+	// Hide the device so that Windows does not warn about a missing driver.
+	Name (_STA, 0xB)
+
+	Method (RSET, 0, Serialized) {
+		Printf ("S76D: RSET")
+		SAPL(0)
+		SKBB(0)
+		SKBC(0xFFFFFF)
+	}
+
+	Method (INIT, 0, Serialized) {
+		Printf ("S76D: INIT")
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use software control
+			^^PCI0.LPCB.EC0.ECOS = 2
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	Method (FINI, 0, Serialized) {
+		Printf ("S76D: FINI")
+		RSET()
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			// Set flags to use hardware control
+			^^PCI0.LPCB.EC0.ECOS = 1
+			Return (0)
+		} Else {
+			Return (1)
+		}
+	}
+
+	// Get Airplane LED
+	Method (GAPL, 0, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (^^PCI0.LPCB.EC0.AIRP & 0x40) {
+				Return (1)
+			}
+		}
+		Return (0)
+	}
+
+	// Set Airplane LED
+	Method (SAPL, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0) {
+				^^PCI0.LPCB.EC0.AIRP |= 0x40
+			} Else {
+				^^PCI0.LPCB.EC0.AIRP &= 0xBF
+			}
+		}
+	}
+
+	// Get Keyboard Backlight Kind
+	// 0 - No backlight
+	// 1 - White backlight
+	// 2 - RGB backlight
+	Method (GKBK, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 2
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+		}
+		Return (Local0)
+	}
+
+	// Get Keyboard Brightness
+	Method (GKBB, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 1
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Brightness
+	Method (SKBB, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 0
+			^^PCI0.LPCB.EC0.FBUF = Arg0
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+
+	// Get Keyboard Color
+	Method (GKBC, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 4
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+			Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
+			Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Color
+	Method (SKBC, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 3
+			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
+			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
+			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
+
+	// Fan names
+	Method (NFAN, 0, Serialized) {
+		Return (Package() {
+			"CPU fan",
+#if CONFIG(EC_DASHARO_EC_DGPU)
+			"GPU fan",
+#endif
+		})
+	}
+
+	// Get fan duty cycle and RPM as a single value
+	Method (GFAN, 1, Serialized) {
+		Local0 = 0
+		Local1 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT1
+				Local1 = ^^PCI0.LPCB.EC0.RPM1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT2
+				Local1 = ^^PCI0.LPCB.EC0.RPM2
+			}
+		}
+		If (Local1 != 0) {
+			// 60 * (EC frequency / 120) / 2
+			Local1 = 2156250 / Local1
+		}
+		Return ((Local1 << 8) | Local0)
+	}
+
+	// Temperature names
+	Method (NTMP, 0, Serialized) {
+		Return (Package() {
+			"CPU temp",
+#if CONFIG(EC_DASHARO_EC_DGPU)
+			"GPU temp",
+#endif
+		})
+	}
+
+	// Get temperature
+	Method (GTMP, 1, Serialized) {
+		Local0 = 0;
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP2
+			}
+		}
+		Return (Local0)
+	}
+}