mb/system76/gaze17: 3060: Fix RTD3 configs

The gaze17, like the oryp9, ties all resets for RTD3 to BUF_PLT_RST#
instead of using dedicated lines and ties the enable GPIO to 3.3VS.

Disable RTD3 config for the CPU PCIe RP and disable L23 for the PCH SSD
slot to fix suspend with Western Digital drives.

Change-Id: Iab3796d98ce74e09e74abb48b437e74a60c7b6b1
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS

.gitignore

@@ -31,9 +31,6 @@ site-local
 # Development friendly files
 tags
 .clang_complete
-.cache
-compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/
@@ -43,3 +40,5 @@ tarballs/
 *~
 *.kate-swp
 *.kdev4
+
+doxygen/*

.gitmodules

@@ -1,67 +1,63 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/.mdl_style.rb

@@ -1,9 +0,0 @@
-# See one of the following URLs for explanations of all the rules
-# https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-# https://web.archive.org/web/20220424164542/https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-
-all
-exclude_rule 'no-multiple-blanks'
-exclude_rule 'blanks-around-headers'
-exclude_rule 'blanks-around-lists'
-rule 'line-length', :line_length => 72

Documentation/acpi/devicetree.md

@@ -1,4 +1,82 @@
-# Driver Devicetree Entries
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+### Naming and referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+	device domain 0 on
+		...
+		device pci 00.2 alias iommu off end
+		...
+	end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+	device domain 0
+		...
+		device ref iommu on end
+		...
+	end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+	# NOTE: not inside domain 0!
+	device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
+## Device drivers
 
 Let's take a look at an example entry from
 ``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
@@ -9,7 +87,6 @@ device pci 15.0 on
 		register "hid" = ""ELAN0000""
 		register "desc" = ""ELAN Touchpad""
 		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
 		register "wake" = "GPE0_DW0_21"
 		device i2c 15 on end
 	end
@@ -141,31 +218,6 @@ find the names in your SoC's header file.  The ACPI_* macros are defined in
 Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
 This is often done in a mainboard-specific file named ``gpio.c``.
 
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. While no
-boards in the tree currently implement this, it has been used in downstream
-forks without issue for some time now.
-
 ### wake
 
 The last register is:
@@ -232,7 +284,7 @@ Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 
 ## Notes
 
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/index.md

@@ -10,3 +10,7 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
+
+## devicetree
+
+- [Adding devices to a device tree](devicetree.md)

Documentation/community/forums.md

@@ -31,7 +31,7 @@ topics, including community and technical matters that benefit from
 an official decision.
 
 We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
+best with [Google Meet](https://meet.google.com/syn-toap-agu),
 using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
 for the agenda and meeting minutes. Neither the video conference nor
 the document require a Google account to participate, although editing

Documentation/contributing/coding_style.md

@@ -3,7 +3,7 @@
 This document describes the preferred C coding style for the
 coreboot project. It is in many ways exactly the same as the Linux
 kernel coding style. In fact, most of this document has been copied from
-the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/plain/Documentation/process/4.Coding.rst)
+the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
 
 The guidelines in this file should be seen as a strong suggestion, and
 should overrule personal preference. But they may be ignored in
@@ -1002,7 +1002,7 @@ The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
 <https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8>
+<https://www.google.com/search?q=isbn+0-13-110362-8.
 
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.

Documentation/contributing/gerrit_guidelines.md

@@ -53,10 +53,7 @@ it's implemented, should restart the wait period.
 a recently-introduced issue (build, boot or OS-level compatibility, not
 necessarily identified by coreboot.org facilities). Its commit message
 has to explain what change introduced the problem and the nature of
-the problem so that the emergency need becomes apparent. Avoid stating
-something like "fix build error" in the commit summary, describe what
-the commit does instead, just like any other commit. In addition, it is
-recommended to reference the commit that introduced the issue. The change
+the problem so that the emergency need becomes apparent. The change
 itself should be as limited in scope and impact as possible to make it
 simple to assess the impact. Such a change can be merged early with 3
 Code-Review+2. For emergency fixes that affect a single project (SoC,

Documentation/contributing/project_ideas.md

@@ -87,7 +87,7 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
 yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a

Documentation/coreboot_logo.svg

@@ -1,40 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<svg
-   width="250"
-   height="200"
-   viewBox="0 0 250.00001 200"
-   version="1.1"
-   id="svg4"
-   sodipodi:docname="coreboot_logo.svg"
-   inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)"
-   xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
-   xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
-   xmlns="http://www.w3.org/2000/svg"
-   xmlns:svg="http://www.w3.org/2000/svg">
-  <defs
-     id="defs8" />
-  <sodipodi:namedview
-     id="namedview6"
-     pagecolor="#ffffff"
-     bordercolor="#666666"
-     borderopacity="1.0"
-     inkscape:pageshadow="2"
-     inkscape:pageopacity="0.0"
-     inkscape:pagecheckerboard="true"
-     showgrid="false"
-     width="250px"
-     height="200px"
-     inkscape:zoom="1.464382"
-     inkscape:cx="-62.825135"
-     inkscape:cy="121.21154"
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Documentation/distributions.md

@@ -8,15 +8,6 @@ and those providing after-market firmware to extend the usefulness of devices.
 
 ## Hardware shipping with coreboot
 
-### NovaCustom laptops
-
-[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
-[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
-[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
-Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
-and the firmware is equipped with important security features such as measured
-boot, verified boot, TPM integration and UEFI Secure Boot.
-
 ### ChromeOS Devices
 
 All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
@@ -37,15 +28,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
+use Tianocore as the payload and include an NVRAM option to disable the
+Intel Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
+distribution of coreboot, EDK2, and System76 firmware applications.
 
 ### Purism
 
@@ -63,20 +54,11 @@ provides ready-made firmware images for supported devices: those which can be
 built entirely from source code. Their copy of the coreboot repository is
 therefore stripped of all devices that require binary components to boot.
 
-
-### Dasharo
-
-[Dasharo](https://dasharo.com/) is an open-source based firmware distribution
-focusing on clean and simple code, long-term maintenance, transparent
-validation, privacy-respecting implementation, liberty for the owners, and
-trustworthiness for all.
-
-
 ### MrChromebox
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/doxygen/Doxyfile.coreboot_platform

@@ -0,0 +1,319 @@
+# Doxyfile 1.8.11
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING      = UTF-8
+PROJECT_NAME           = "coreboot for $(DOXYGEN_PLATFORM)"
+PROJECT_NUMBER         =
+PROJECT_BRIEF          = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO           = Documentation/coreboot_logo.png
+OUTPUT_DIRECTORY       = $(DOXYGEN_OUTPUT_DIR)
+CREATE_SUBDIRS         = YES
+ALLOW_UNICODE_NAMES    = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       =
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+TCL_SUBST              =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
+AUTOLINK_SUPPORT       = YES
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+GROUP_NESTED_COMPOUNDS = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
+EXTRACT_PACKAGE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+HIDE_COMPOUND_REFERENCE= NO
+SHOW_INCLUDE_FILES     = YES
+SHOW_GROUPED_MEMB_INC  = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = YES
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            =
+CITE_BIB_FILES         =
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_AS_ERROR          = NO
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = $(DOXYFILES)
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          =
+RECURSIVE              = NO
+EXCLUDE                =
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       =
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+USE_MDFILE_AS_MAINPAGE =
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+SOURCE_TOOLTIPS        = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+CLANG_ASSISTED_PARSING = NO
+CLANG_OPTIONS          =
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_STYLESHEET  =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
+HTML_COLORSTYLE_GAMMA  = 80
+HTML_TIMESTAMP         = NO
+HTML_DYNAMIC_SECTIONS  = NO
+HTML_INDEX_NUM_ENTRIES = 100
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen documentation"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = NO
+CHM_FILE               =
+HHC_LOCATION           =
+GENERATE_CHI           = NO
+CHM_INDEX_ENCODING     =
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+GENERATE_QHP           = NO
+QCH_FILE               =
+QHP_NAMESPACE          = org.doxygen.Project
+QHP_VIRTUAL_FOLDER     = doc
+QHP_CUST_FILTER_NAME   =
+QHP_CUST_FILTER_ATTRS  =
+QHP_SECT_FILTER_ATTRS  =
+QHG_LOCATION           =
+GENERATE_ECLIPSEHELP   = NO
+ECLIPSE_DOC_ID         = org.doxygen.Project
+DISABLE_INDEX          = NO
+GENERATE_TREEVIEW      = YES
+ENUM_VALUES_PER_LINE   = 4
+TREEVIEW_WIDTH         = 250
+EXT_LINKS_IN_WINDOW    = NO
+FORMULA_FONTSIZE       = 10
+FORMULA_TRANSPARENT    = YES
+USE_MATHJAX            = NO
+MATHJAX_FORMAT         = HTML-CSS
+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_EXTENSIONS     =
+MATHJAX_CODEFILE       =
+SEARCHENGINE           = YES
+SERVER_BASED_SEARCH    = NO
+EXTERNAL_SEARCH        = NO
+SEARCHENGINE_URL       =
+SEARCHDATA_FILE        = searchdata.xml
+EXTERNAL_SEARCH_ID     =
+EXTRA_SEARCH_MAPPINGS  =
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+LATEX_FOOTER           =
+LATEX_EXTRA_STYLESHEET =
+LATEX_EXTRA_FILES      =
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+LATEX_SOURCE_CODE      = NO
+LATEX_BIB_STYLE        = plain
+LATEX_TIMESTAMP        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+RTF_SOURCE_CODE        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_SUBDIR             =
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+GENERATE_DOCBOOK       = NO
+DOCBOOK_OUTPUT         = docbook
+DOCBOOK_PROGRAMLISTING = NO
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = YES
+EXPAND_ONLY_PREDEF     = YES
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             = __attribute__(x)=
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+EXTERNAL_PAGES         = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+DIA_PATH               =
+HIDE_UNDOC_RELATIONS   = NO
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = YES
+UML_LIMIT_NUM_FIELDS   = 10
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+PLANTUML_INCLUDE_PATH  =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES

Documentation/drivers/cbfs_smbios.md

@@ -1,65 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,21 +298,21 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
 
-### OEM Variables
+## OEM Variables
 Platform vendors can define an array of OEM-specific values as OEM variables
 to be used under DPTF policy. There are total six OEM variables available.
 These can be used in AP policy for more specific actions. These OEM variables

Documentation/drivers/index.md

@@ -4,14 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code across platforms.
 
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/getting_started/architecture.md

@@ -3,7 +3,7 @@
 ## Overview
 ![][architecture]
 
-[architecture]: comparison_coreboot_uefi.svg
+[architecture]: comparision_coreboot_uefi.svg
 
 ## Stages
 coreboot consists of multiple stages that are compiled as separate binaries and

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/index.md

@@ -6,4 +6,3 @@
 * [Kconfig](kconfig.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/ifdtool/layout.md

@@ -2,7 +2,7 @@
 
 A coreboot image for an Intel SoC contains two separate definitions of the
 layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and
-sizes of various regions of flash and the [coreboot FMAP](../../lib/flashmap.md).
+sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md).
 
 The FMAP should define all of the of the regions defined by the IFD to ensure
 that those regions are accounted for by coreboot and will not be accidentally
@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this     |
+| 8          | EC Firmware      | SI_EC     | Most Chrome OS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+

Documentation/index.md

@@ -5,11 +5,6 @@ It is built from Markdown files in the
 [Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
 directory in the source code.
 
-## Spelling of coreboot
-
-The correct spelling of coreboot is completely in lower case characters and in
-one word without a space between the two parts.
-
 ## Purpose of coreboot
 
 coreboot is a project to develop open source boot firmware for various
@@ -26,7 +21,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 
@@ -194,7 +189,5 @@ Contents:
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
 * [Project infrastructure & services](infrastructure/index.md)
-* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
-* [Acronyms & Definitions](acronyms.md)
 * [Documentation License](documentation_license.md)

Documentation/infrastructure/builders.md

@@ -41,33 +41,25 @@ can run into "out of storage space" errors.
 #### Current Build Machines
 
 To give an idea of what a suitable build machine might be, currently the
-coreboot project has 6 active jenkins build machines.
+coreboot project has 4 active jenkins build machines.
 
 These times are taken from the week of Feb 21 - Feb 28, 2022
 
 * Congenialbuilder - 128 threads, 256GiB RAM
-  * Coverity Builds, Toolchain builds, Scanbuild-builds
-  * Fastest Passing coreboot gerrit build: 6 min, 47 sec
-  * Slowest Passing coreboot gerrit build: 14 min
+  *  Fastest Passing coreboot gerrit build: 6 min, 47 sec
+  *  Slowest Passing coreboot gerrit build: 14 min
 
-* Gleefulbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 10 min
-  * Slowest Passing coreboot gerrit build: 46 min
+* Gleefulbuilder - 64 thread, 64GiB RAM
+  *  Fastest Passing coreboot gerrit build: 10 min
+  *  Slowest Passing coreboot gerrit build: 46 min
 
 * Fabulousbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min, 56 sec
-  * Slowest Passing coreboot gerrit build: 56 min (No ccache)
+  *  Fastest Passing coreboot gerrit build: 7 min, 56 sec
+  *  Slowest Passing coreboot gerrit build: 56 min (No ccache)
 
 * Ultron (9elements) - 48 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 12 min
-  * Slowest Passing coreboot gerrit build: 58 min
-
-* Bob - 64 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min
-  * Slowest Passing coreboot gerrit build: 34 min
-
-* Pokeybuilder - 32 Threads, 96GiB RAM
-  * Runs coreboot-checkpatch and other lighter builds
+  *  Fastest Passing coreboot gerrit build: 12
+  *  Slowest Passing coreboot gerrit build: 58 min
 
 
 ### Jenkins Builds
@@ -77,18 +69,7 @@ for a number of different projects - coreboot, flashrom, memtest86+,
 em100, etc.  Many of these have builders for their current master branch
 as well as Gerrit and [Coverity](coverity.md) builds.
 
-
-#### Long builds - over 90 minutes on congenialbuilder
-There are a few builds that take a long time even on the fastest
-machines.  These tasks run overnight in the US timezones.
-* coreboot_coverity - 9 to 12 hours
-* coreboot_scanbuild - ~3 hours
-* coreboot_toolchain - ~1 hour 45 minutes
-
-
-#### All builds
-
-You can see all the builds in the main jenkins interface:
+You can see all the builds here:
 [https://qa.coreboot.org/](https://qa.coreboot.org/)
 
 Most of the time on the builders is taken up by the coreboot master and
@@ -110,8 +91,8 @@ hour.
 
 On a system with 32 cores, it was tested with this command:
 
-```sh
-stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
+```
+$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
 ```
 
 You can watch the temperature with the sensors package or with ‘acpi -t’
@@ -121,8 +102,8 @@ You can check for thermal throttling by running this command and seeing
 if the values go down on any of the cores after it's been running for a
 while.
 
-```sh
-while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
+```
+$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
 ```
 
 If the machine throttles or resets, you probably need to upgrade the
@@ -161,7 +142,7 @@ These instructions keep changing, so just check the latest information.
 
 As a regular user - *Not root*, run:
 
-```sh
+```
 sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
 sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
 sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
@@ -177,7 +158,7 @@ To make configuration and the later commands easier, these should go in
 your shell's .rc file.  Note that you only need to set them if you're
 using something other than the default.
 
-```sh
+```
 # Set the port used on your machine to connect to jenkins.
 export COREBOOT_JENKINS_PORT=49151
 
@@ -199,13 +180,13 @@ continuing to the next step.
 
 From the coreboot directory, run
 
-```sh
+```
 make -C util/docker help
 ```
 
 This will show you the available targets and variables needed:
 
-```text
+```
 Commands for working with docker images:
   coreboot-sdk                 - Build coreboot-sdk container
   upload-coreboot-sdk          - Upload coreboot-sdk to hub.docker.com
@@ -240,7 +221,7 @@ Variables:
 
 ### Install the coreboot jenkins builder
 
-```sh
+```
 make -C util/docker docker-jenkins-server
 ```
 
@@ -271,12 +252,11 @@ the ccache gets populated, the build time will drop.
 
 
 ### How to log in to the docker instance for debugging
-
-```sh
-make -C util/docker docker-jenkins-attach
-su coreboot
-cd ~/slave-root/workspace
-bash
+```
+    $ make -C util/docker docker-jenkins-attach
+    $ su coreboot
+    $ cd ~/slave-root/workspace
+    $ bash
 ```
 
 
@@ -293,18 +273,18 @@ then update to get a fresh installation.
 
 To delete the old containers & images:
 
-```sh
-docker stop $COREBOOT_JENKINS_CONTAINER
-docker rm $COREBOOT_JENKINS_CONTAINER
-docker images # lists all existing images
-docker rmi XXXX # Use the image ID found in the above command.
+```
+$ docker stop $COREBOOT_JENKINS_CONTAINER
+$ docker rm $COREBOOT_JENKINS_CONTAINER
+$ docker images # lists all existing images
+$ docker rmi XXXX # Use the image ID found in the above command.
 ```
 
 To get and run the new coreboot-jenkins image, change the value in the
 `DOCKER_COMMIT` variable to the new image value.
 
-```sh
-make -C util/docker docker-jenkins-server
+```
+$ make -C util/docker docker-jenkins-server
 ```
 
 #### Getting ready to push the docker images
@@ -318,15 +298,15 @@ Get an admin to add the account to the coreboot team on hub.docker.com
 Make sure your credentials are configured on your host machine by
 running
 
-```sh
-docker login
+```
+$ docker login
 ```
 
 This will prompt you for your docker username, password, and your email
 address, and write out to ~/.docker/config.json.  Without this file, you
 won’t be able to push the images.
 
-#### Updating the Dockerfiles
+#### Updating the Dockerfiles:
 
 The coreboot-sdk Dockerfile will need to be updated when any additional
 dependencies are added.  Both the coreboot-sdk and the
@@ -337,15 +317,15 @@ files are stored in the coreboot repo under coreboot/util/docker.
 Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/)
 page before updating the files.
 
-#### Rebuilding the coreboot-sdk docker image to update the toolchain
+#### Rebuilding the coreboot-sdk docker image to update the toolchain:
 
-```sh
-make -C util/docker coreboot-sdk
+```
+$ make -C util/docker coreboot-sdk
 ```
 
 This takes a relatively long time.
 
-#### Test the coreboot-sdk docker image
+#### Test the coreboot-sdk docker image:
 
 There are two methods of running the docker image - interactively as a
 shell, or doing the build directly.  Running interactively as a shell is
@@ -353,44 +333,44 @@ useful for early testing, because it allows you to update the image
 (without any changes getting saved) and re-test builds.  This saves the
 time of having to rebuild the image for every issue you find.
 
-#### Running the docker image interactively
+#### Running the docker image interactively:
 
 Run:
 
-```sh
-make -C util/docker docker-jenkins-server
-make -C util/docker docker-jenkins-attach
+```
+$ make -C util/docker docker-jenkins-server
+$ make -C util/docker docker-jenkins-attach
 ```
 
-#### Running the build directly
+#### Running the build directly:
 
 From the coreboot directory:
 
-```sh
-make -C util/docker docker-build-coreboot
+```
+$ make -C util/docker docker-build-coreboot
 ```
 
 You’ll also want to test building the other projects and payloads:
 ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo,
 nvramcui, tint...
 
-#### Pushing the coreboot-sdk image to hub.docker.com for use
+#### Pushing the coreboot-sdk image to hub.docker.com for use:
 
 When you’re satisfied with the testing, push the coreboot-sdk image to
 the hub.docker.com
 
-```sh
-make -C util/docker upload-coreboot-sdk
+```
+$ make -C util/docker upload-coreboot-sdk
 ```
 
-#### Building and pushing the coreboot-jenkins-node docker image
+#### Building and pushing the coreboot-jenkins-node docker image:
 
 This docker image is pretty simple, so there’s not really any testing
 that needs to be done.
 
-```sh
-make -C util/docker coreboot-jenkins-node
-make -C util/docker upload-coreboot-jenkins-node
+```
+$ make -C util/docker coreboot-jenkins-node
+$ make -C util/docker upload-coreboot-jenkins-node
 ```
 
 ### Coverity Setup
@@ -411,7 +391,7 @@ Rename the directory from its original name
 (cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a
 symlink:
 
-```sh
+```
 ln -s cov-analysis-linux64-7.7.0.4 coverity
 ```
 

Documentation/infrastructure/services.md

@@ -16,21 +16,6 @@ all your email addresses you intend to use in the context of coreboot
 development so that commits with your email address in them are associated with
 you properly.
 
-Below is a list of its SSH host keys and fingerprints.
-```Bash
-[review.coreboot.org]:29418 ssh-rsa AAAAB3NzaC1yc2EAAAABIwAAAQEAvNDn8qGHlWM/5ndFltStlg3QTc8xvGOgyjxxZByhMZx8LVE4cfgF38WP3euq0avyFy7gAJNghHorXpYKoOzuQPn2WNi5QhyGsUhg7ZJz9hC7Z2gqxxsZF3E7rku4Uj9sN7hWx9fBngxD4z2tP4y/18FTT5XTMcC3Q2sBCOLM0XVAO5R/nb2GO3d27avy+sanKAFEwJHnZ996IoTlU8JJFyi1Y6g30dC2K75oFgCtzntxf++wvrkkKPa+CFQub8fp20shat9WwX9kXjpRjt/Yv9LgqFCaI5ztJvWXicAmbgghGVzbzz4GoSjjF9cxxJF//KTmNb4iGQqmP3Olm27xuw==
-
-[review.coreboot.org]:29418 ecdsa-sha2-nistp256 AAAAE2VjZHNhLXNoYTItbmlzdHAyNTYAAAAIbmlzdHAyNTYAAABBBBzlwf/bFejt4EEz1QmbNOfK/HN1NtdcefrRs5Gs42uGnIvjxsff+vEF3//jCTvFPadoy3DrPsbQB3ioQAcYppk=
-
-[review.coreboot.org]:29418 ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAIOC3Z32gc+1rJXhKX+SW0vESlXR/h/mhcxd+62B1PWC2
-```
-
-```Bash
-2048 SHA256:WW5prF7YE3MTnkRIxLklr9Gxddj9s5BZKUqWJF5dnTg review.coreboot.org:29418 (RSA)
-256 SHA256:IuLv/DgrBtVn36eMP1zFD0ISAl3IxIoCeiRms6UDhZc review.coreboot.org:29418 (ECDSA)
-256 SHA256:QFZieVHy8dCRl9tDib6qiwELnfa7SVU4ZWJ5VrXoC8k review.coreboot.org:29418 (ED25519)
-```
-
 ### https push access
 When using the https URLs to git repositories, you can push with the "HTTP
 Credentials" you can have Gerrit generate for you on that page. By default,

Documentation/lib/flashmap.md

@@ -4,7 +4,7 @@
 
 [Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
 describe partitions in a flash chip. It was added to coreboot to support the
-requirements of ChromiumOS firmware but then was also used in other scenarios
+requirements of Chromium OS firmware but then was also used in other scenarios
 where precise placement of data in flash was necessary, or for data that is
 written to at runtime, as CBFS is considered too fragile for such situations.
 The Flashmap implementation inside coreboot is the de facto standard today.

Documentation/lib/fw_config.md

@@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
 otherwise similar enough to use the same coreboot build target.
 
 The initial implementation is designed to take advantage of a bitmask returned by the Embedded
-Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
-image across multiple devices by selecting various options at runtime.  See the ChromiumOS
+Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware
+image across multiple devices by selecting various options at runtime.  See the Chromium OS
 [Firmware Config][1] documentation for more information.
 
 This firmware configuration interface differs from the CMOS option interface in that this
@@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
 
 ### Embedded Controller
 
-Google ChromeOS devices support an Embedded Controller interface for reading and writing the
+Google Chrome OS devices support an Embedded Controller interface for reading and writing the
 firmware configuration value, along with other board-specific information.  It is possible for
 coreboot to read this value at boot on systems that support this feature.
 
@@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
 before asking the embedded controller.
 
 It is also possible to adjust the value in the embedded controller *(after disabling write
-protection)* with the `ectool` command in a ChromeOS environment.
+protection)* with the `ectool` command in a Chrome OS environment.
 
-For more information on the firmware configuration field on ChromeOS devices see the Chromium
+For more information on the firmware configuration field on Chrome OS devices see the Chromium
 documentation for [Firmware Config][1] and [Board Info][2].
 
 [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md

Documentation/mainboard/acer/g43t-am3.md

@@ -134,7 +134,7 @@ SPI_ROM1 header while the board is off and disconnected from power. There
 seems to be a diode that prevents the external programmer from powering the
 whole board.
 
-The signal assignment on the header is identical to the pinout of the flash
+The signal assigment on the header is identical to the pinout of the flash
 chip. The pinout diagram below is valid when the PCI slots are on the left
 and the CPU is on the right. Note that HOLD# and WP# must be pulled high
 (to VCC) to be able to flash the chip.

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -1,4 +1,4 @@
-# Pademelon board
+# Padmelon board
 
 ## Specs (with Merlin Falcon SOC)
 
@@ -18,7 +18,7 @@
 
 ## Mainboard
 
-![mainboard][pademelon]
+![mainboard][padmelon]
 
 Three items are marked in this picture
 1. dediprog header
@@ -27,7 +27,7 @@ Three items are marked in this picture
 
 ## Back panel
 
-![back panel][pademelon_io]
+![back panel][padmelon_io]
 
 * The lower serial port is UART A (debug serial)
 
@@ -65,9 +65,9 @@ Three items are marked in this picture
 
 ```eval_rst
 +----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
+|padmelon.jpg                | Motherboard with components identified |
 +----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
+|padmelon_io.jpg             | Back panel picture                     |
 +----------------------------+----------------------------------------+
 ```
 
@@ -76,5 +76,5 @@ Three items are marked in this picture
 [Merlin Falcon BKDG][merlinfalcon]
 
 [merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using edk2 + a PCIe GPU under Windows crashes with an
+- Using TianoCore + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
-- PS/2 mouse using edk2
-- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

Documentation/mainboard/facebook/monolith.md

@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
+All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

Documentation/mainboard/hp/folio_9480m.md

@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, edk2
+- Payload: SeaBIOS, Tianocore
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

Documentation/mainboard/hp/z220_sff.md

@@ -44,17 +44,8 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
-otherwise there's not enough space near the flash.
-
-In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
-be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
-interfere.
-
-## Side note
-The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
-that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
-even interchangeable, so should do coreboot images built for them.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
 
 ## Technology
 
@@ -75,6 +66,5 @@ even interchangeable, so should do coreboot images built for them.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
-[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -11,7 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [G43T-AM3](acer/g43t-am3.md)
 
 ## AMD
-- [pademelon](amd/pademelon/pademelon.md)
+- [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
@@ -30,7 +30,6 @@ This section contains documentation about coreboot on specific mainboards.
 - [P8H77-V](asus/p8h77-v.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
-- [wifigo_v1](asus/wifigo_v1.md)
 
 ## Cavium
 
@@ -146,6 +145,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 
@@ -180,12 +180,10 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Star Labs Systems
 
-- [LabTop Mk III](starlabs/labtop_kbl.md)
 - [LabTop Mk IV](starlabs/labtop_cml.md)
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
-- [Flashing devices](starlabs/common/flashing.md)
 
 ## Supermicro
 

Documentation/mainboard/kontron/mal10.md

@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- edk2
+- Tianocore
 - Linux as payload
 
 ## Flashing coreboot

Documentation/mainboard/opencellular/rotundu.md

@@ -0,0 +1,76 @@
+# Rutundu
+
+This page describes how to run coreboot on the [Rotundu] compute board
+from [OpenCellular].
+
+## TODO
+
+* Configure UART
+* EC interface
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q128    |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit.
+Directly connecting a Pomona test-clip on the flash is also possible.
+
+**Closeup view of SOIC-8 flash IC**
+
+![][rotundu_flash]
+
+[rotundu_flash]: rotundu_flash.jpg
+
+**SPI header**
+
+![][rotundu_header2]
+
+[rotundu_header2]: rotundu_header2.jpg
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][rotundu_j16]
+
+[rotundu_j16]: rotundu_j16.png
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Baytrail                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Rotundu]: https://github.com/Telecominfraproject/OpenCellular
+[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/purism/librem_14.md

@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

Documentation/mainboard/purism/librem_mini.md

@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

Documentation/mainboard/starlabs/common/flashing.md

@@ -16,7 +16,7 @@ fwupdmgr --version
 ```
 
 This will show the version number. **1.5.6** or greater will work.
-![fwupd version](../fwupdVersion.png)
+![fwupd version](fwupdVersion.png)
 On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands:
 
 ```
@@ -40,7 +40,7 @@ BIOS Lock must be disabled when switching from the standard AMI (American Megatr
 2\. When the BIOS settings load, use the arrow keys to navigate to the **Advanced** tab\. Here you will see **BIOS Lock**\.
 3\. Press `Enter` to change this setting from **Enabled** to **Disabled**
 
-![Disable BIOS Lock](../BiosLock.jpg)
+![Disable BIOS Lock](BiosLock.jpg)
 
 4\. Next, press the `F10` key to **Save & Exit** and then `Enter` to confirm.
 
@@ -61,7 +61,7 @@ fwupdmgr switch-branch
 ```
 
 You can then select which branch you would like to use, by typing in the corresponding number:
-![Switch Branch](../SwitchBranch.png)
+![Switch Branch](SwitchBranch.png)
 You will be prompted to confirm, press `y` to continue or `n` to cancel.
 
 Once the switch has been completed, you will be prompted to restart.

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -1,83 +0,0 @@
-# Star LabTop Mk III
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-8550u  (Kaby Lake Refresh)
-- EC
-    - ITE IT8987E
-    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel UHD Graphics 620
-    - GOP driver is recommended, VBT is provided
-    - eDP 13-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 8GB on-board
-- Networking
-    - 8265 PCIe WiFi / Bluetooth soldered to PCBA
-- Sound
-    - Realtek ALC256
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1280x720 CCD camera
-    - USB 3.1 Gen 2 Type-C (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-
-The below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Gigadevice |
-+---------------------+------------+
-| Model               | 25Q128JVSQ |
-+---------------------+------------+
-| Size                | 8  MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/northbridge/intel/haswell/mrc.bin.md

@@ -3,7 +3,7 @@
 All Haswell boards supported by coreboot currently require a proprietary
 blob in order to initialise the DRAM and a few other components. The
 blob, named `mrc.bin`, largely consists of Intel's memory reference code
-(MRC), but it has been tailored specifically for ChromeOS. It is just
+(MRC), but it has been tailored specifically for Chrome OS. It is just
 under 200 KiB in size. Another name for `mrc.bin` is the system agent
 binary.
 

Documentation/northbridge/intel/sandybridge/nri_registers.md

@@ -1899,7 +1899,7 @@ Please handle with care!
 +===========+==================================================================+
 |        0:7|  PDWN_idle_counter, This defines the rank indle period in DCLK   |
 |           |  cycles that causes power-down entrance. The minimum value       |
-|           |  should be greater than or equal to the worst roundtrip time     |
+|           |  should be greater then or equal to the worst roundtrip time     |
 |           |  plus burst length.                                              |
 +-----------+------------------------------------------------------------------+
 |       8:10|  PDWN_mode, selects the mode of power-down:                      |

Documentation/payloads.md

@@ -11,23 +11,17 @@ payload or can be made to work as one.
 
 [SeaBIOS](https://www.seabios.org) is an open source implementation of
 the PCBIOS API that exists since the original IBM PC and was extended
-since. While originally written for emulators such as QEMU, it can be built
-as a coreboot payload. It supports executing Option ROMs in a more complete
-fashion than coreboot. It also supports Multiboot.
+since. While originally written for emulators such as QEMU, it can be made
+to work as a coreboot payload and all the necessary code is in SeaBIOS'
+mainline code.
 
-When chainloaded from GRUB2, the following menuentry could be used:
+## Tianocore
 
-    menuentry "SeaBIOS" --unrestricted {
-        root=(cbfsdisk)
-        multiboot /img/seabios
-        module /vgaroms/seavgabios.bin
-    }
-
-## edk2
-
-[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
-cross-platform firmware development environment for the UEFI and UEFI
-Platform Initialization (PI) specifications.
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 

Documentation/releases/boards_supported_on_branches.md

@@ -1,549 +0,0 @@
-# Platforms supported on branches
-
-For one reason or another, platforms have been deleted from the master
-branch at times in the past.  Early on, there was no real policy on
-removing boards.  Now the policy is that boards will only be removed if
-they're causing issues in the tree or if they're preventing progress.
-
-This does not mean that these boards are gone forever.  The release or
-commit prior to where they were removed can be checked out, and the
-boards can still be built there and updated in a release branch if
-desired.
-
-Currently, [jenkins](https://qa.coreboot.org), our continuous
-integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-and 4.16 branches.  Builders for other branches can be created on
-request.  Likewise, some releases are only marked with tags, and
-branches would need to be created to push new code to.  These branches
-can also be created on request.
-
-Patches can be backported from the master branch to any of these other
-branches as needed. The coreboot project will take care of backporting
-critical security fixes, but other patches will need to handled by
-anyone using that release.
-
-## [4.16 Release](coreboot-4.16-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.15 Release](coreboot-4.15-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.14 Release](coreboot-4.14-relnotes.md)
-Branch created, builder configured
-
-* No platforms maintained on this release
-
-
-## [4.13 Release](coreboot-4.13-relnotes.md)
-Tag only
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-## [4.12 Release](coreboot-4.12-relnotes.md)
-
-Branch created, builder configured
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-+-----------------------------+------------------------+------------+----------+
-| ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-## [4.11 Release](coreboot-4.11-relnotes.md)
-
-Branch created, builder configured
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-+-----------------------------+------------------------+------------+----------+
-| intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
-| opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.10 Release](coreboot-4.10-relnotes.md)
-Branch created
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.9 Release](coreboot-4.9-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-| pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-+-----------------------------+------------------------+------------+----------+
-| amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-+-----------------------------+------------------------+------------+----------+
-| artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-+-----------------------------+------------------------+------------+----------+
-| hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-+-----------------------------+------------------------+------------+----------+
-| iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-+-----------------------------+------------------------+------------+----------+
-| intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-+-----------------------------+------------------------+------------+----------+
-| sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-+-----------------------------+------------------------+------------+----------+
-| technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
-| via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-+-----------------------------+------------------------+------------+----------+
-| winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.7 Release](coreboot-4.7-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-+-----------------------------+------------------------+------------+----------+
-| asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-+-----------------------------+------------------------+------------+----------+
-| asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-| ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-+-----------------------------+------------------------+------------+----------+
-| lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
-| mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-+-----------------------------+------------------------+------------+----------+
-| rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-+-----------------------------+------------------------+------------+----------+
-| supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-+-----------------------------+------------------------+------------+----------+
-| thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
-| wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.6](coreboot-4.6-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.5](coreboot-4.5-relnotes.md)
-Tag only
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-+-----------------------------+------------------------+------------+----------+
-| google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-+-----------------------------+------------------------+------------+----------+
-| google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.4](coreboot-4.4-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.3](coreboot-4.3-relnotes.md)
-Branch created
-
-* No platforms maintained on this release
-
-
-## [4.2](coreboot-4.2-relnotes.md)
-Branch created
-
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
-| Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
-| arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
-| ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
-| newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-| tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
-
-
-## [4.1](coreboot-4.1-relnotes.md)
-Branch Created
-
-* No platforms maintained on this release

Documentation/releases/coreboot-4.15-relnotes.md

@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single edk2 package/target.
+that we're only building from a single Tianocore package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

Documentation/releases/coreboot-4.16-relnotes.md

@@ -132,7 +132,7 @@ HECI based on Intel Core processors from Skylake to Alder Lake. State is
 set based on a CMOS value of `me_state`. A value of `0` will result in a
 (CS)ME state of `0` (working) and value of `1` will result in a (CS)ME
 state of `3` (disabled). For an example CMOS layout and more info, see
-[cse.c](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/soc/intel/common/block/cse/cse.c).
+[cse.c](../../src/soc/intel/common/block/cse/cse.c).
 
 
 ### Add [AMD] apcb_v3_edit tool

Documentation/releases/coreboot-4.17-relnotes.md

@@ -1,345 +1,19 @@
-coreboot 4.17
-========================================================================
+Upcoming release - coreboot 4.17
+================================
 
-The coreboot 4.17 release was done on June 3, 2022.
+The 4.17 release is planned for May, 2022.
 
-Since the 4.16 release, we've had over 1300 new commits by around 150
-contributors.  Of those people, roughly 15 were first-time contributors.
+We are continuing the quarterly release cadence in order to enable others to
+release quarterly on a fresher version of coreboot.
 
-As always, we appreciate everyone who has contributed and done the hard
-work to make the coreboot project successful.
+Update this document with changes that should be in the release notes.
 
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
-Major Bugfixes in this release
-------------------------------
-* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-29264)
+Significant changes
+-------------------
 
-
-New Mainboards
---------------
-
-* Clevo L140MU / L141MU / L142MU
-* Dell Precision T1650
-* Google Craask
-* Google Gelarshie
-* Google Kuldax
-* Google Mithrax
-* Google Osiris
-* HP Z220 CMT Workstation
-* Star Labs LabTop Mk III (i7-8550u)
-* Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-* Star Labs Lite Mk III (N5000)
-* Star Labs Lite Mk IV (N5030)
-
-
-Removed Mainboards
-------------------
-
-* Google Deltan
-* Google Deltaur
-
-Significant or interesting changes
-----------------------------------
-
-These changes are a few that were selected as a sampling of particularly
-interesting commits.
-
-
-### CBMEM init hooks changed
-
-Instead of having per stage x_CBMEM_INIT_HOOK, we now have only 2 hooks:
-* CBMEM_CREATION_HOOK: Used only in the first stage that creates cbmem,
-  typically romstage. For instance code that migrates data from cache
-  as ram to dram would use this hook.
-* CBMEM_READY_HOOK: Used in every stage that has cbmem. An example would
-  be initializing the cbmem console by appending to what previous stages
-  logged.
-The reason for this change is improved flexibility with regards to which
-stage initializes cbmem.
-
-
-### Payloads
-
-* SeaBIOS: Update stable release from 1.14.0 to 1.16.0
-* iPXE: Update stable release from 2019.3 to 2022.1
-* Add "GRUB2 atop SeaBIOS" aka "SeaGRUB" option, which builds GRUB2 as a
-  secondary payload for SeaBIOS with GRUB2 set as the default boot
-  entry.  This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as
-  a fallback method to access hardware that the native GRUB2 payload
-  cannot access.
-* Add option to build SeaBIOS and GRUB2 as secondary payloads
-* Add new coreDOOM payload.  See commit message below.
-
-
-### payloads/external: Add support for coreDOOM payload
-
-coreDOOM is a port of DOOM to libpayload, based on the doomgeneric
-source port. It renders the game to the coreboot linear framebuffer,
-and loads WAD files from CBFS.
-
-
-### cpu/x86/smm_module_load: Rewrite setup_stub
-
-This code was hard to read as it did too much and had a lot of state
-to keep track of.
-
-It also looks like the staggered entry points were first copied and
-only later the parameters of the first stub were filled in. This
-means that only the BSP stub is actually jumping to the permanent
-smihandler. On the APs the stub would jump to wherever c_handler
-happens to point to, which is likely 0. This effectively means that on
-APs it's likely easy to have arbitrary code execution in SMM which is a
-security problem.
-
-Note: This patch fixes CVE-2022-29264 for the 4.17 release.
-
-
-### cpu/x86/smm_module_loader.c: Rewrite setup
-
-This code is much easier to read if one does not have to keep track of
-mutable variables.
-
-This also fixes the alignment code on the TSEG smihandler setup code.
-It was aligning the code upwards instead of downwards which would cause
-it to encroach a part of the save state.
-
-
-### cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub
-
-The sinkhole exploit exists in placing the lapic base such that it
-messes with GDT. This can be mitigated by checking the lapic MSR
-against the current program counter.
-
-
-### cpu/x86/64bit: Generate static page tables from an assembly file
-
-This removes the need for a tool to generate simple identity pages.
-Future patches will link this page table directly into the stages on
-some platforms so having an assembly file makes a lot of sense.
-
-This also optimizes the size of the page of each 4K page by placing
-the PDPE_table below the PDE.
-
-
-### cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
-
-This change will allow the SMI handler to write to the cbmem console
-buffer. Normally SMIs can only be debugged using some kind of serial
-port (UART). By storing the SMI logs into cbmem we can debug SMIs using
-'cbmem -1'. Now that these logs are available to the OS we could also
-verify there were no errors in the SMI handler.
-
-Since SMM can write to all of DRAM, we can't trust any pointers
-provided by cbmem after the OS has booted. For this reason we store the
-cbmem console pointer as part of the SMM runtime parameters. The cbmem
-console is implemented as a circular buffer so it will never write
-outside of this area.
-
-
-### security/tpm/crtm: Add a function to measure the bootblock on SoC level
-
-On platforms where the bootblock is not included in CBFS anymore
-because it is part of another firmware section (IFWI or a different
-CBFS), the CRTM measurement fails.
-
-This patch adds a new function to provide a way at SoC level to measure
-the bootblock. Following patches will add functionality to retrieve the
-bootblock from the SoC related location and measure it from there.
-In this way the really executed code will be measured.
-
-
-### soc/amd/common/block/psp: Add platform secure boot support
-
-Add Platform Secure Boot (PSB) enablement via the PSP if it is not
-already enabled. Upon receiving psb command, PSP will program PSB fuses
-as long as BIOS signing key token is valid.
-Refer to the AMD PSB user guide doc# 56654, Revision# 1.00.
-Unfortunately this document is only available with NDA customers.
-
-
-### drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
-
-This patch implements coreboot native debug handler to manage the FSP
-event messages.
-
-'FSP Event Handlers' feature introduced in FSP to generate event
-messages to aid in the debugging of firmware issues. This eliminates
-the need for FSP to directly write debug messages to the UART and FSP
-might not need to know the board related UART port configuration.
-Instead FSP signals the bootloader to inform it of a new debug message.
-This allows the coreboot to provide board specific methods of reporting
-debug messages, example: legacy UART or LPSS UART etc.
-
-This implementation has several advantages as:
-1. FSP relies on XIP 'DebugLib' driver even while printing FSP-S debug
-  messages, hence, without ROM being cached, post 'romstage' would
-  results into sluggish boot with FSP debug enabled.
-  This patch utilities coreboot native debug implementation which is
-  XIP during FSP-M and relocatable to DRAM based resource for FSP-S.
-
-2. This patch simplifies the FSP DebugLib implementation and remove the
-   need to have serial port library. Instead coreboot 'printk' can be
-   used for display FSP serial messages. Additionally, unifies the debug
-   library between coreboot and FSP.
-
-3. This patch is also useful to get debug prints even with FSP
-   non-serial image (refer to 'Note' below) as FSP PEIMs are now
-   leveraging coreboot debug library instead FSP 'NULL' DebugLib
-   reference for release build.
-
-4. Can optimize the FSP binary size by removing the DebugLib dependency
-   from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary
-   size is reduced by ~100KB+ and FSP-S debug library size is also
-   reduced by ~300KB+ (FSP-S debug and release binary size is exactly
-   same with this code changes). The total savings is ~400KB for each
-   FSP copy, and in case of Chrome AP firmware with 3 copies, the total
-   savings would be 400KB * 3 = ~1.2MB.
-
-Note: Need to modify FSP source code to remove 'MDEPKG_NDEBUG' as
-compilation flag for release build and generate FSP binary with non-NULL
-FSP debug wrapper module injected (to allow FSP event handler to execute
-even with FSP non-serial image) in the final FSP.fd.
-
-
-### security/tpm: Add vendor-specific tis functions to read/write TPM regs
-
-In order to abstract bus-specific logic from TPM logic, the prototype
-for two vendor-specific tis functions are added in this
-patch. tis_vendor_read() can be used to read directly from TPM
-registers, and tis_vendor_write() can be used to write directly to TPM
-registers.
-
-
-### arch/x86: Add support for catching null dereferences through debug regs
-
-This commit adds support for catching null dereferences and execution
-through x86's debug registers. This is particularly useful when running
-32-bit coreboot as paging is not enabled to catch these through page
-faults. This commit adds three new configs to support this feature:
-DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and
-DEBUG_NULL_DEREF_HALT.
-
-
-### drivers/i2c/generic: Add support for i2c device detection
-
-Add 'detect' flag which can be attached to devices which may or may not
-be present at runtime, and for which coreboot should probe the i2c bus
-to confirm device presence prior to adding an entry for it in the SSDT.
-
-This is useful for boards which may utilize touchpads/touchscreens from
-multiple vendors, so that only the device(s) present are added to the
-SSDT. This relieves the burden from the OS to detect/probe if a device
-is actually present and allows the OS to trust the ACPI _STA value.
-
-
-### util/cbmem: Add FlameGraph-compatible timestamps output
-
-Flame graphs are used to visualize hierarchical data, like call stacks.
-Timestamps collected by coreboot can be processed to resemble
-profiler-like output, and thus can be feed to flame graph generation
-tools.
-
-Generating flame graph using https://github.com/brendangregg/FlameGraph:
-```
-   cbmem -S > trace.txt
-   FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg
-```
-
-
-### src/console/Kconfig: Add option to disable loglevel prefix
-
-This patch adds an option to disable loglevel prefixes. This patch helps
-to achieve clear messages when low loglevel is used and very few
-messages are displayed on a terminal. This option also allows to
-maintain compatibility with log readers and continuous integration
-systems that depend on fixed log content.
-
-If the code contains:
-  printk(BIOS_DEBUG, "This is a debug message!\n")
-it will show as:
-  [DEBUG]  This is a debug message!
-but if the Kconfig contains:
-  CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
-the same message will show up as
-  This is a debug message!
-
-
-### util/cbmem: add an option to append timestamp
-
-Add an option to the cbmem utility that can be used to append an entry
-to the cbmem timestamp table from userspace. This is useful for
-bookkeeping of post-coreboot timing information while still being able
-to use cbmem-based tooling for processing the generated data.
-
-
-`-a | --add-timestamp ID:          append timestamp with ID\n`
-
-
-Additional changes
-------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* As always, general documentation, code cleanup, and refactoring
-* Remove doxygen config files and targets
-* Get clang compile working for all x86 platforms
-* Work on updating checkpatch to match the current Linux version
-* Timestamps: Rename timestamps to make names more consistent
-* Continue updating ACPI code to ASL 2.0
-* Remove redundant or unnecessary headers from C files
-* arch/x86/acpi_bert_storage.c: Use a common implementation
-* Postcar stage improvements
-* arch/x86/acpi: Consolidate POST code handling
-* intel/common: Enable ROM caching in ramstage
-* vendorcode/amd/agesa: Fix improper use of .data (const is important)
-* sandybridge & gm45: Support setting PCI bars above 4G
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever was
-the CRB board. From the looks of it the code never was ready for production as
-only engineering sample CPUIDs are supported.
-
-Thus, to reduce the maintanence overhead for the community, it is deprecated
-from this release on and support for the following components will be dropped
-with the release 4.19.
-
-  * Intel Icelake SoC
-  * Intel Icelake RVP mainboard
-
-
-### LEGACY_SMP_INIT
-
-As of release 4.18 (August 2022) we plan to deprecate LEGACY_SMP_INIT.
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-No platforms in the tree have any hardware limitations that would block
-migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase.
-
-
-Statistics
-----------
-
-- Total Commits: 1305
-- Average Commits per day: 13.42
-- Total lines added: 51422
-- Average lines added per commit: 39.40
-- Number of patches adding more than 100 lines: 59
-- Average lines added per small commit: 24.73
-- Total lines removed: 66206
-- Average lines removed per commit: 50.73
-- Total difference between added and removed: -14784
-- Total authors: 146
-- New authors: 17
+### Add significant changes here

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,236 +0,0 @@
-Upcoming release - coreboot 4.18 release
-========================================================================
-
-The 4.18 release is quite late, but is now planned for October 16, 2022.
-
-In the past 4 months since the 4.17 release, the coreboot project has
-merged more than 1800 commits from over 200 different authors. Over 50
-of those authors submitted their first patches.
-
-Welcome and thank you to all of our new contributors, and of course the
-work of all of the seasoned contributors is greatly appreciated.
-
-
-Significant or interesting changes
-----------------------------------
-
-### sconfig: Allow to specify device operations
-
-Currently we only have runtime mechanisms to assign device operations to
-a node in our devicetree (with one exception: the root device). The most
-common method is to map PCI IDs to the device operations with a `struct
-pci_driver`. Another accustomed way is to let a chip driver assign them.
-
-For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
-ID lists grew very large and are incredibly error-prone. Often, IDs are
-missing and sometimes IDs are added almost mechanically without checking
-the code for compatibility. Maintaining these lists in a central place
-also reduces flexibility.
-
-Now, for onboard devices it is actually unnecessary to assign the device
-operations at runtime. We already know exactly what operations should be
-assigned. And since we are using chipset devicetrees, we have a perfect
-place to put that information.
-
-This patch adds a simple mechanism to `sconfig`. It allows us to speci-
-fy operations per device, e.g.
-
-device pci 00.0 alias system_agent on
-	ops system_agent_ops
-end
-
-The operations are given as a C identifier. In this example, we simply
-assume that a global `struct device_operations system_agent_ops` exists.
-
-
-### Set touchpads to use detect (vs probed) flag
-
-Historically, ChromeOS devices have worked around the problem of OEMs
-using several different parts for touchpads/touchscreens by using a
-ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
-to indicate that the device may or may not be present, and that the
-driver should probe to confirm device presence.
-
-Since release 4.18, coreboot  supports detection for i2c devices at
-runtime when creating the device entries for the ACPI/SSDT tables,
-rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
-in the tree from using the 'probed' flag to the 'detect' flag.
-
-Touchscreens require more involved power sequencing, which will be done
-at some future time, after which they will switch over as well.
-
-
-### Add SBOM (Software Bill of Materials) Generation
-
-Firmware is typically delivered as one large binary image that gets
-flashed. Since this final image consists of binaries and data from a
-vast number of different people and companies, it's hard to determine
-what all the small parts included in it are. The goal of the software
-bill of materials (SBOM) is to take a firmware image and make it easy to
-find out what it consists of and where those pieces came from.
-
-Basically, this answers the question, who supplied the code that's
-running on my system right now? For example, buyers of a system can use
-an SBOM to perform an automated vulnerability check or license analysis,
-both of which can be used to evaluate risk in a product. Furthermore,
-one can quickly check to see if the firmware is subject to a new
-vulnerability included in one of the software parts (with the specified
-version) of the firmware.
-
-Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
-
-- Add Makefile.inc to generate and build coswid tags
-- Add templates for most payloads, coreboot, intel-microcode,
-  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
-  intel ME and compiler (gcc,clang,other)
-- Add Kconfig entries to optionally supply a path to CoSWID tags
-  instead of using the default CoSWID tags
-- Add CBFS entry called SBOM to each build via Makefile.inc
-- Add goswid utility tool to generate SBOM data
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Allocator v4 is not yet ready, but received significant work.
-* Console: create an [smbus console driver](https://doc.coreboot.org/technotes/console.html)
-* pciexp_device: Numerous updates and fixes
-* Update checkpatch to match Linux v5.19
-* Continue updating ACPI to ASL 2.0 syntax
-* arch/x86: Add a common romstage entry point
-* Documentation: Add a list of [acronyms](https://doc.coreboot.org/acronyms.html)
-* Start hooking up ops in devicetree
-* Large amounts of general code cleanup and improvement, as always
-* Work to make sure all files have licenses
-
-
-Payloads
---------
-
-### EDK II (TianoCore)
-
-coreboot uses TianoCore interchangeably with EDK II, and whilst the
-meaning is generally clear, it's not the payload it uses.
-Consequentially, TianoCore has been renamed to EDK II (2).
-
-The option to use the already deprecated CorebootPayloadPkg has been
-removed.
-
-Recent changes to both coreboot and EDK means that UefiPayloadPkg seems
-to work on all hardware. It has been tested on:
-
-* Intel Core 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 8th, 9th, 10th,
-  11th and 12th generation processors
-* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
-* AMD Stoney Ridge and Picasso
-
-CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
-
-The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
-`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
-
-
-New Mainboards
---------------
-
-* AMD Birman
-* AMD Pademelon renamed from Padmelon
-* Google Evoker
-* Google Frostflow
-* Google Gaelin4ADL
-* Google Geralt
-* Google Joxer
-* Google Lisbon
-* Google Magikarp
-* Google Morthal
-* Google Pujjo
-* Google Rex 0
-* Google Shotzo
-* Google Skolas
-* Google Tentacruel
-* Google Winterhold
-* Google Xivu
-* Google Yaviks
-* Google Zoglin
-* Google Zombie
-* Google Zydron
-* MSI PRO Z690-A WIFI DDR4
-* Siemens MC APL7
-
-
-Removed Mainboards
-------------------
-
-* Google Brya4ES
-
-
-Updated SoCs
-------------
-
-* Added Intel Meteor Lake
-* Added Mediatek Mt8188
-* Renamed AMD Sabrina to Mendocino
-* Added AMD Morgana
-
-
-Plans for Code Deprecation
---------------------------
-
-### LEGACY_SMP_INIT
-
-Legacy SMP init will be removed from the coreboot master branch
-immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch or tag.
-
-This also includes the codepath for SMM_ASEG. This code is used to start
-APs and do some feature programming on each AP, but also set up SMM.
-This has largely been superseded by PARALLEL_MP, which should be able to
-cover all use cases of LEGACY_SMP_INIT, with little code changes. The
-reason for deprecation is that having 2 codepaths to do the virtually
-the same increases maintenance burden on the community a lot, while also
-being rather confusing.
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics
-----------
-
-- Total Commits: 1819
-- Average Commits per day: 13.44
-- Total lines added: 150195
-- Average lines added per commit: 82.57
-- Number of patches adding more than 100 lines: 127
-- Average lines added per small commit: 38.38
-- Total lines removed: 33788
-- Average lines removed per commit: 18.58
-- Total difference between added and removed: 116407

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,64 +0,0 @@
-Upcoming release - coreboot 4.19
-========================================================================
-
-The 4.19 release is planned for January 2023.
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-Significant changes
--------------------
-
-### Add significant changes here
-
-
-
-Additional coreboot changes
----------------------------
-
-* One or two line change comments go here
-
-
-
-Payloads
---------
-
-### Payload changes go here
-
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard

Documentation/releases/coreboot-4.6-relnotes.md

@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the edk2 UEFI implementation which
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the edk2 which has not been updated.
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the edk2
+the hope is that by the end of the summer, we finally support the EDK2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/
 

Documentation/releases/coreboot-4.7-relnotes.md

@@ -84,7 +84,7 @@ General changes
 
 * Integrate me_cleaner
 * Add flashconsole implementation
-* Build edk2 UEFI payload from upstream source
+* Build Tianocore UEFI payload from upstream source
 * Remove CMOS NVRAM configurable baud rates
 * A common mrc_cache driver to store romstage settings in SPI flash
 

Documentation/releases/coreboot-4.8.1-relnotes.md

@@ -71,7 +71,7 @@ detection
 Payloads
 --------
 * Bumped SeaBIOS to 1.11.1
-* Improved edk2 integration
+* Improved TianoCore integration
 
 Security
 --------

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.19 - Jan 2023](coreboot-4.19-relnotes.md)
+* [4.17 - May 2022](coreboot-4.17-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,8 +15,6 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.18 - Oct 2022](coreboot-4.18-relnotes.md)
-* [4.17 - May 2022](coreboot-4.17-relnotes.md)
 * [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)

Documentation/security/vboot/index.md

@@ -176,6 +176,7 @@ CMOS, the EC, or in a read/write area of the SPI flash device.
 Select one of the following:
 
 * `VBOOT_VBNV_CMOS`
+* `VBOOT_VBNV_EC`
 * `VBOOT_VBNV_FLASH`
 
 More non-volatile storage features may be found in `security/vboot/Kconfig`.
@@ -328,7 +329,7 @@ Google's Chromebooks have some special features:
 ### Developer Mode
 
 Developer mode allows the user to use coreboot to boot another operating system.
-This may be a another (beta) version of ChromeOS, or another flavor of
+This may be a another (beta) version of Chrome OS, or another flavor of
 GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
 into developer mode, all locally saved data on the system is lost.
 This prevents someone from entering developer mode to subvert the system

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman
 - Chausie
 - Majolica
 
@@ -36,6 +35,7 @@
 - Anahera4ES
 - Brask
 - Brya 0
+- Brya4ES
 - Felwinter
 - Gimble
 - Gimble4ES
@@ -46,8 +46,6 @@
 - Primus4ES
 - Redrix
 - Redrix4ES
-- Skolas
-- Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
@@ -57,26 +55,12 @@
 - Crota
 - Moli
 - Kinox
-- Craask
-- Osiris
-- Mithrax
-- Kuldax
-- Joxer
-- Pujjo
-- Xivu
-- Gaelin4ADL
-- Yaviks
-- Lisbon
-- Zydron
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
-- Steelix
 - Krabby
-- Tentacruel
-- Magikarp
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -88,6 +72,9 @@
 - Terra (ASUS Chromebook C202SA/C300SA/C301SA)
 - Ultima (Lenovo Yoga 11e G3)
 - Wizpig
+- Daisy (Samsung Chromebook (2012))
+- Deltan
+- Deltaur
 - Drallion
 - Eve (Google Pixelbook)
 - Fizz
@@ -95,7 +82,6 @@
 - Endeavour
 - Foster
 - Gale (Google WiFi)
-- Geralt
 - Asuka (Dell Chromebook 13 3380)
 - Caroline (Samsung Chromebook Pro)
 - Cave (Asus Chromebook Flip C302SA)
@@ -113,25 +99,34 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
+- Ambassador
+- Dooly
 - Dratini (HP Pro c640 Chromebook)
+- Duffy Legacy (32MB)
+- Duffy (ASUS Chromebox 4)
+- Faffy (ASUS Fanless Chromebox)
+- Genesis
 - Hatch
 - Helios (ASUS Chromebook Flip C436FA)
 - Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
+- Kaisa Legacy (32MB)
+- Kaisa (Acer Chromebox CXI4)
 - Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
+- Moonbuggy
 - Mushu
 - Nightfury (Samsung Galaxy Chromebook 2)
+- Noibat (HP Chromebox G3)
 - Palkia
+- Puff
+- Scout
+- Wyvern (CTL Chromebox CBx2)
 - Herobrine
 - Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
-- Villager
-- Evoker
-- Zoglin
-- Zombie
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
@@ -171,26 +166,14 @@
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
 - Parrot (Acer C7/C710 Chromebook)
+- Peach Pit (Samsung Chromebook 2 11\")
 - Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
 - Nautilus (Samsung Chromebook Plus V2, V2 LTE)
 - Nocturne (Google Pixel Slate)
-- Rammus
+- Rammus (Asus Chromebook C425, Flip C433, Flip C434)
 - Soraka (HP Chromebook x2)
-- Ambassador
-- Dooly
-- Duffy Legacy (32MB)
-- Duffy (ASUS Chromebox 4)
-- Faffy (ASUS Fanless Chromebox)
-- Genesis
-- Kaisa Legacy (32MB)
-- Kaisa (Acer Chromebox CXI4)
-- Moonbuggy
-- Noibat (HP Chromebox G3)
-- Puff
-- Scout
-- Wyvern (CTL Chromebox CBx2)
 - Banjo (Acer Chromebook 15 (CB3-531))
 - Candy (Dell Chromebook 11 3120)
 - Clapper (Lenovo N20 Chromebook)
@@ -212,13 +195,8 @@
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
-- Rex 0
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
-- Skyrim
-- Winterhold
-- Morthal
-- Frostflow
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -246,25 +224,6 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Delbin (ASUS Chromebook Flip CX5)
-- Eldrid
-- Halvor
-- Lindar
-- Malefor
-- Terrador
-- Todor
-- Trondo
-- Volteer
-- Volteer2
-- Volteer2_Ti50
-- Voxel (Acer Chromebook Spin 713 (CP713-3W))
-- Elemi (HP Pro c640 G2 Chromebook)
-- Voema
-- Drobit (ASUS Chromebook CX9400)
-- Copano (ASUS Chromebook Flip CX5400)
-- Collis
-- Volet
-- Chronicler
 - Dalboz
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
 - Ezkinil (Acer Chromebook Spin 514)
@@ -277,7 +236,6 @@
 - Gumboz (HP Chromebook x360 14a)
 
 ## HP
-- Z220 CMT Workstation
 - Z220 SFF Workstation
 
 ## Intel
@@ -288,7 +246,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11
@@ -315,8 +272,6 @@
 - Whitetip Mountain 2 CRB
 
 ## Lenovo
-- ThinkPad T440p
-- ThinkPad W541
 - ThinkPad T400
 - ThinkPad T500
 - ThinkPad R400
@@ -328,6 +283,7 @@
 - ThinkPad T430
 - ThinkPad T430s
 - ThinkPad T431s
+- ThinkPad T440p
 - ThinkPad T520
 - ThinkPad W520
 - ThinkPad T530
@@ -345,9 +301,6 @@
 - ThinkPad X230s
 - ThinkPad X60 / X60s / X60t
 
-## MSI
-- PRO Z690-A WIFI DDR4
-
 ## OpenCellular
 - Elgon (GBCv2)
 
@@ -362,11 +315,6 @@
 - MC APL4
 - MC APL5
 - MC APL6
-- MC APL7
-
-## Star Labs
-- Star Labs Lite Mk III (N5000)
-- Star Labs Lite Mk IV (N5030)
 
 ## Supermicro
 - X11SSH-TF

Documentation/soc/amd/psp_integration.md

@@ -117,23 +117,14 @@ implementations currently use combo tables.
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Size of PSP entry in bytes |
 +--------------+---------------+------------------+----------------------------+
-| Location /   | 0x08          | 62               | Location: Physical Address |
+| Location /   | 0x08          | 64               | Location: Physical Address |
 | Value        |               |                  | of SPIROM location where   |
 |              |               |                  | corresponding PSP entry    |
 |              |               |                  | located.                   |
 |              |               |                  |                            |
-|              |               |                  | Value: 62-bit value for the|
+|              |               |                  | Value: 64-bit value for the|
 |              |               |                  | PSP Entry                  |
 +--------------+---------------+------------------+----------------------------+
-| Address Mode | 0x0F[7:6]     | 2                | 00: x86 Physical address   |
-|              |               |                  | 01: offset from start of   |
-|              |               |                  |     BIOS (flash offset)    |
-|              |               |                  | 02: offset from start of   |
-|              |               |                  |     directory header       |
-|              |               |                  | 03: offset from start of   |
-|              |               |                  |     partition              |
-+--------------+---------------+------------------+----------------------------+
-
 ```
 ### PSP Directory Table Types
 
@@ -181,10 +172,6 @@ implementations currently use combo tables.
 *   Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
     This is mandatory in order to support encrypted firmware.
 
-**0x22**: PSP Token Unlock data
-*   Used to support time-bound Secure Debug unlock during boot.  This entry may
-    be omitted if the Token Unlock debug feature is not required.
-
 **0x24**: Security policy binary
 *   A security policy is applied to restrict the untrusted access to security
     sensitive regions.
@@ -213,6 +200,10 @@ implementations currently use combo tables.
 **0x52**: PSP boot loader usermode OEM application
 *   Supported only in certain SKUs.
 
+**0x22**: PSP Token Unlock data
+*   Used to support time-bound Secure Debug unlock during boot.  This entry may
+    be omitted if the Token Unlock debug feature is not required.
+
 ### Firmware Version of Binaries
 
 Every firmware binary contains 256 bytes of a PSP Header, which includes
@@ -311,25 +302,15 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
 +--------------+---------------+------------------+----------------------------+
 | SubProgram   | 0x03[2:0]     | 3                | Specify the SubProgram     |
 +--------------+---------------+------------------+----------------------------+
-| RomId        | 0x03[4:3]     | 2                | Which SPI device the       |
-|              |               |                  | content is placed in       |
-+--------------+---------------+------------------+----------------------------+
-| Writeable    | 0x03[5]       | 1                | Region is writable or read |
-|              |               |                  | only                       |
-+--------------+---------------+------------------+----------------------------+
-| Reserved     | 0x03[7:6]     | 2                | Reserved - Set to zero     |
+| Reserved     | 0x03[7:3]     | 5                | Reserved - Set to zero     |
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Memory Region Size         |
 +--------------+---------------+------------------+----------------------------+
-| Source       | 0x08          | 62               | Physical Address of SPIROM |
+| Source       | 0x08          | 64               | Physical Address of SPIROM |
 | Address      |               |                  | location where the data for|
 |              |               |                  | the corresponding entry is |
 |              |               |                  | located                    |
 +--------------+---------------+------------------+----------------------------+
-| Entry Address| 0x0F[7:6]     | 2                | Same as Entry Address Mode |
-| Mode         |               |                  | in PSP directory table     |
-|              |               |                  | entry fields               |
-+--------------+---------------+------------------+----------------------------+
 | Destination  | 0x10          | 64               | Destination Address of     |
 | Address      |               |                  | memory location where the  |
 |              |               |                  | data for the corresponding |

Documentation/soc/intel/cse_fw_update/cse_fw_update.md

@@ -8,7 +8,7 @@ power transition flows.
 
 ## Problem Statement
 
-Currently, on ChromiumOS Systems, CSE region is not updatable. So, new CSE FW
+Currently, on Chromium OS Systems, CSE region is not updatable. So, new CSE FW
 versions that are released by Intel to address important functional and security
 bugs post-product launch will not be available to the end-user. Hence, the proposed
 solution allows in-field CSE FW update to propagate those bug fixes

Documentation/soc/intel/mp_init/mp_init.md

@@ -51,6 +51,6 @@ option in order to perform SGX and C6DRAM enabling.
 Typically all platforms supported by FSP 2.1 specification will have
 external PPI service feature implemented.
 
-## References
+[References]
 - [PPI](../fsp/ppi/ppi.md)
 - [MP Service PPI](../fsp/ppi/mp_service_ppi.md)

Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md

@@ -3,7 +3,7 @@ Rebuilding coreboot image generation
 
 Current situation
 -----------------
-ChromeOS (CrOS) probably has the most complex image bundling process in the
+Chrome OS (CrOS) probably has the most complex image bundling process in the
 coreboot ecosystem. To make CrOS features more accessible to the wider
 coreboot community, we want to move these capabilities into upstream
 coreboot’s build system.
@@ -21,7 +21,7 @@ putting more data (eg. the bitmap data, keys) as raw data into other fmap
 regions.
 
 With the recent addition of more files to CBFS, both on the coreboot side
-(dsdt, FSP, and so on) and with ChromeOS specifics (eg. more files describing
+(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing
 boot screens) we either need to expand the scope of bundle\_firmware or move
 the capability to build complex images to upstream coreboot’s build system.
 This document proposes to do the latter and outlines how this could be
@@ -41,14 +41,14 @@ images:
   variable to guarantee success if there’s enough room for the files. While that
   could be added, that becomes more make macro work indistinguishable from magic
   that people fail to understand, break and with good reason complain about
-  to work around such issues, ChromeOS firmware uses a custom tool with even
+  to work around such issues, Chrome OS firmware uses a custom tool with even
   more special cases to finally build the image it needs. If coreboot upstream
   is to support vboot, it should also be powerful enough not to need magic tools
   that only live within downstream projects.
 
 Requirements
 ------------
-A complete ChromeOS coreboot image consists of (depending on the device)
+A complete Chrome OS coreboot image consists of (depending on the device)
 * platform specific data in raw fmap regions (eg IFD, ME firmware),
 * the bootblock (coming from the bootblock),
 * three copies of coreboot, consisting of the stages (verstage, romstage,
@@ -68,7 +68,7 @@ using a yet to be implemented switching scheme based on fmaps) consists of
 * payload plus data (with each of the coreboot copies),
 
 Since a single platform is potentially built with different payload
-configurations (eg. modding a Chromebook to not use the verified ChromeOS
+configurations (eg. modding a Chromebook to not use the verified Chrome OS
 boot scheme), some concerns need to be kept separate:
 * Platform requirements that have nothing to do with the payload or boot schemes
  * IFD, ME, … need to copied to the right place
@@ -111,11 +111,11 @@ Boot method manifest
 --------------------
 The boot method manifest can subdivide the BIOS region, eg. using it directly
 (for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s
-fallback/normal) or in many parts (for ChromeOS, which requires two CBFS
+fallback/normal) or in many parts (for Chrome OS, which requires two CBFS
 regions, one for GBB, several for VPD, …).
 It also specifies which of the file lists specified earlier belong in which
 region (eg. with verstage verifying romstage, verstage needs to be only in
-ChromeOS’ RO region, while romstage belongs in RO and both RW regions).
+Chrome OS’ RO region, while romstage belongs in RO and both RW regions).
 It can also specify a post processing step that is executed before the
 chipset’s.
 
@@ -148,7 +148,7 @@ It specifies an IFD region, an ME, and the BIOS region. After the image is
 built, the entire image needs to be processed (although the tool likely works
 only on a small part of it)
 
-It’s built in a ChromeOS-like configuration (simplified at places to avoid
+It’s built in a Chrome OS-like configuration (simplified at places to avoid
 distracting from the important parts), so it has three CBFS regions, and
 several data regions for its own purpose (similar to GBB, FWID, VPD, …). After
 the regions are filled, one data region must be post-processed to contain

Documentation/technotes/console.md

@@ -1,66 +0,0 @@
-# coreboot Console
-
-coreboot supports multiple ways to access its console.
-https://www.coreboot.org/Console_and_outputs
-
-
-## SMBus Console
-
-SMBus is a two-wire interface which is based on the principles of
-operation of I2C. SMBus, was first was designed to allow a battery to
-communicate with the charger, the system host, and/or other
-power-related components in the system.
-
-Enable the SMBus console with `CONSOLE_I2C_SMBUS` Kconfig. Set
-`CONSOLE_I2C_SMBUS_SLAVE_ADDRESS` and
-`CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER` configuration values of the
-slave I2C device which you will use to capture I2C packets.
-
-Modern computer Random Access Memory (RAM) slot has SMBus in it
-according to the JEDEC standards. We can use a breakout-board to expose
-those SMBus pins. Some mainboard have SMBus pins in the PCIe slot as
-well.
-
-This feature has been tested on the following platforms:
-```eval_rst
-+------------------------------------+
-| Tested platforms                   |
-+====================================+
-| GA-H61M-S2PV + Intel Ivy Bridge    |
-+---------------------+---------------
-```
-
-A minimal DDR3 DIMM breakout board PCB design with only the
-SDA(Data line) and SCL(Clock line) pins of I2C/SMBus can be found
-[here](https://github.com/drac98/ram-breakout-board).
-See the PCB layout [here](https://archive.org/details/ddr3-dimm-F_Cu)
-
-NOTE:
-To capture the I2C packets, an I2C slave device is required. The easiest
-way to capture the log message is to use a I2C to UART converter chip
-with a UART to USB converter chip. The setup would be as follows.
-```text
-+---------+    +-------------+    +-------------+
-+   PC    +----+ UART to USB +----+ I2C to UART |
-+---------+    +-------------+    +-------------+
-                                              | |
-------------------------------------------------+--  System Management
-----------------------------------------------+----  Bus
-```
-
-Watch this [video](https://youtu.be/Q0dK41n9db8) to see how it is set
-up. A backup of the video is available
-[here](https://web.archive.org/web/20220916172605/https://www.youtube.com/watch?v=Q0dK41n9db8)
-
-If you are using any of the `SC16IS740/750/760` I2C to UART converter
-chip, you can enable the `SC16IS7XX_INIT` option to initialize the chip.
-
-If not we can use other I2C slave devices like an Arduino or a
-Beagleboard.
-* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/latest/i2c/slave-interface.html)
-* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/beaglebone-black-and-arduino-uno-i2c-communication-using-c/29990/8)
-
-This feature was added as part of a GSoC 2022 project. Checkout the
-following blog posts for more details.
-* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273691a8ac)
-* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f24)

Documentation/technotes/index.md

@@ -5,4 +5,3 @@
 * [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
 * [Unit Test Code Coverage](2021-05-code-coverage.md)
 * [Address Sanitizer](asan.md)
-* [coreboot Consoles](console.md)

Documentation/tutorial/flashing_firmware/ext_standalone.md

@@ -19,45 +19,5 @@ It is possible to set the onboard flash on hold and use another flash chip.
 Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
 low, and /HOLD of your replacement flash IC high.
 
-### SPI header
-Some boards feature a pin header which is connected to the SPI bus. This can
-also be used to connect a secondary flash chip.
-
-#### HP boards
-Many HP desktop mainboards have a 2x8 or 2x10 block of header pins which
-can be used to connect a second flash chip. One pin is connected to the
-onboard flash's /CS pin, and another is connected to the chipset's /CS
-pin. Normally a jumper cap is placed between these pins, allowing the
-chipset to access the onboard flash. To use this header, remove this
-jumper and connect all lines except /CS one-to-one with the
-corresponding pin on the header. The secondary flash chip's /CS line
-should be connected to the chipset /CS pin on the header. By doing this
-the secondary SPI flash, rather than the onboard flash, will respond to
-accesses from the chipset.
-
-![][hp_spi_header_pinout]
-
-![][hp_spi_header_mainboard]
-
-Note that on boards where this header is unpopulated, a jumper resistor
-will be populated nearby which serves the purpose of the jumper cap. One
-end should have continuity with the /CS pin on the flash, and the other
-end should have continuity with the chipset /CS pin on the unpopulated
-header. It may also be possible to find this resistor through visual
-inspection of the traces on the /CS pins. This resistor should be
-desoldered if you wish to solder a pin header to the board and connect a
-secondary flash, otherwise the onboard flash will always respond to
-accesses.
-
-#### Other boards
-Other boards may have similar headers, but will likely use a different
-pinout than the ones explicitly mentioned here. Usually such a header
-will be located near the onboard SPI flash. If schematics are available,
-the pinout for the header will likely be found in it, but it could also
-be determined using a multimeter in continuity mode to map out the
-connections between the SPI flash and the header.
-
 
 [EM100Pro]: https://www.dediprog.com/product/EM100Pro
-[hp_spi_header_pinout]: hp_spi_header.svg
-[hp_spi_header_mainboard]: hp_spi_header_mb.jpg

Documentation/tutorial/flashing_firmware/hp_spi_header.svg

@@ -1,109 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-
-<svg
-   width="40.266247mm"
-   height="20.267391mm"
-   viewBox="0 0 40.266247 20.267391"
-   version="1.1"
-   id="svg5"
-   xmlns="http://www.w3.org/2000/svg"
-   xmlns:svg="http://www.w3.org/2000/svg">
-  <defs
-     id="defs2" />
-  <g
-     id="layer1"
-     transform="translate(0.1322915,0.1322915)">
-    <path
-       style="fill:none;stroke:#000000;stroke-width:0.264583"
-       d="M 0,0 C 0,6.6676027 0,13.335205 0,20.002808"
-       id="path500" />
-    <path
-       style="fill:none;stroke:#000000;stroke-width:0.264583"
-       d="m 0,20.002808 c 13.333889,0 26.667777,0 40.001666,0 0,-6.667603 0,-13.3352053 0,-20.002808 -6.665673,0 -13.331347,0 -19.99702,0 0,6.6676027 0,13.335205 0,20.002808"
-       id="path506" />
-    <path
-       style="fill:none;stroke:#000000;stroke-width:0.264583"
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-    <path
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-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="22.156124"
-       y="6.3107877"
-       id="text676"><tspan
-         x="22.156124"
-         y="6.3107877">VCC</tspan></text>
-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       id="text730"><tspan
-         id="tspan728"
-         x="31.972855"
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-    <text
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-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       id="text734"><tspan
-         id="tspan732"
-         x="32.398666"
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-    <text
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-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       y="16.285427"
-       id="text738"><tspan
-         id="tspan736"
-         x="22.770041"
-         y="16.285427">DO</tspan></text>
-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="13.605446"
-       y="16.286804"
-       id="text742"><tspan
-         id="tspan740"
-         x="13.605446"
-         y="16.286804">DI</tspan></text>
-    <text
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-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       y="6.1998558"
-       id="text746"><tspan
-         id="tspan744"
-         x="2.5204566"
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-    <text
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-       font-size="2.5px"
-       style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal"
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-         x="5.0321894"
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-         x="5.0321894"
-         y="17.146358"
-         id="tspan752">chipset</tspan></text>
-  </g>
-</svg>

Documentation/tutorial/part1.md

@@ -2,179 +2,118 @@ Tutorial, part 1: Starting from scratch
 ===========================================
 
 This tutorial will guide you through the process of setting up a working
-coreboot toolchain. In same cases you will find specific instructions
-for Debian (apt-get), Fedora (dnf) and Arch Linux (pacman) based package
-management systems. Use the instructions according to your system.
-
-**Note: Summaries of each of the steps are at the end of the document.**
-
+coreboot toolchain. In same cases you will find specific instructions for Debian (apt-get),
+Fedora (dnf) and Arch Linux (pacman) based package management systems. Use the
+instructions according to your system.
 
 Download, configure, and build coreboot
 ---------------------------------------
 
-
 ### Step 1 - Install tools and libraries needed for coreboot
-
-Debian based distros:
-`sudo apt-get install -y bison build-essential curl flex git gnat`
-`libncurses5-dev m4 zlib1g-dev`
-
-Arch based distros:
-`sudo pacman -S base-devel curl git gcc-ada ncurses zlib`
-
-Redhat based distros:
-`sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++`
-`ncurses-devel wget zlib-devel patch`
-
+    $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
+    $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
+    $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel patch
 
 ### Step 2 - Download coreboot source tree
-
-```Bash
-git clone https://review.coreboot.org/coreboot
-cd coreboot
-```
-
-
+    $ git clone https://review.coreboot.org/coreboot
+    $ cd coreboot
 
 ### Step 3 - Build the coreboot toolchain
-
-Please note that this can take a significant amount of time. Use `CPUS=`
-to specify number of `make` jobs to run in parallel.
+Please note that this can take a significant amount of time. Use `CPUS=` to
+specify number of `make` jobs to run in parallel.
 
 This will list toolchain options and supported architectures:
 
-```Bash
-make help_toolchain
-```
+    $ make help_toolchain
 
 Here are some examples:
 
-```Bash
-make crossgcc-i386 CPUS=$(nproc)       # build i386 toolchain
-make crossgcc-aarch64 CPUS=$(nproc)    # build Aarch64 toolchain
-make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
-```
+    $ make crossgcc-i386 CPUS=$(nproc)       # build i386 toolchain
+    $ make crossgcc-aarch64 CPUS=$(nproc)    # build Aarch64 toolchain
+    $ make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
 
-Note that the i386 toolchain is currently used for all x86 platforms,
-including x86_64.
-
-Also note that you can possibly use your system toolchain, but the
-results are not reproducible, and may have issues, so this is not
-recommended.  See step 5 to use your system toolchain.
+Note that the i386 toolchain is currently used for all x86 platforms, including
+x86_64.
 
+Also note that you can possibly use your system toolchain, but the results are
+not reproducible, and may have issues, so this is not recommended.  See step 5
+to use your system toolchain.
 
 ### Step 4 - Build the payload - coreinfo
-
-```Bash
-make -C payloads/coreinfo olddefconfig
-make -C payloads/coreinfo
-```
-
+    $ make -C payloads/coreinfo olddefconfig
+    $ make -C payloads/coreinfo
 
 ### Step 5 - Configure the build
 
 ##### Configure your mainboard
-
-```Bash
-make menuconfig
-```
-
-Do the next steps in the menu:
-
-```Text
-select 'Mainboard' menu
-Beside 'Mainboard vendor' should be '(Emulation)'
-Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
-select < Exit >
-```
-
+    $ make menuconfig
+       select 'Mainboard' menu
+       Beside 'Mainboard vendor' should be '(Emulation)'
+       Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
+       select < Exit >
 These should be the default selections, so if anything else was set, run
 `make distclean` to remove your old config file and start over.
 
 ##### Optionally use your system toolchain (Again, not recommended)
-
-```Text
-select 'General Setup' menu
-select 'Allow building with any toolchain'
-select < Exit >
-```
+       select 'General Setup' menu
+       select 'Allow building with any toolchain'
+       select < Exit >
 
 ##### Select the payload
-
-```Text
-select 'Payload' menu
-select 'Add a Payload'
-choose 'An Elf executable payload'
-select 'Payload path and filename'
-enter 'payloads/coreinfo/build/coreinfo.elf'
-select < Exit >
-select < Exit >
-select < Yes >
-```
+       select 'Payload' menu
+       select 'Add a Payload'
+       choose 'An Elf executable payload'
+       select 'Payload path and filename'
+       enter 'payloads/coreinfo/build/coreinfo.elf'
+       select < Exit >
+       select < Exit >
+       select < Yes >
 
 ##### Check your configuration (optional step):
 
-```Bash
-make savedefconfig
-cat defconfig
-```
+    $ make savedefconfig
+    $ cat defconfig
 
-There should only be two lines (or 3 if you're using the system
-toolchain):
+There should only be two lines (or 3 if you're using the system toolchain):
 
-```Text
-CONFIG_PAYLOAD_ELF=y
-CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
-```
+    CONFIG_PAYLOAD_ELF=y
+    CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
 
 ### Step 6 - build coreboot
-
-```Bash
-make
-```
+    $ make
 
 At the end of the build, you should see:
 
-`Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)``
-
-This means your build was successful. The output from the build is in
-the build directory. build/coreboot.rom is the full rom file.
+    Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)
 
+This means your build was successful. The output from the build is in the build
+directory. build/coreboot.rom is the full rom file.
 
 Test the image using QEMU
 -------------------------
 
-
 ### Step 7 - Install QEMU
-
-* Debian: `sudo apt-get install -y qemu`
-* Arch: `sudo pacman -S qemu`
-* Redhat: `sudo dnf install qemu`
-
+    $ sudo apt-get install -y qemu
+    $ sudo pacman -S qemu
+    $ sudo dnf install qemu
 
 ### Step 8 - Run QEMU
-
 Start QEMU, and point it to the ROM you just built:
 
-```Bash
-qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
-```
-
-You should see the serial output of coreboot in the original console
-window, and a new window will appear running the coreinfo payload.
+    $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
 
+You should see the serial output of coreboot in the original console window, and
+a new window will appear running the coreinfo payload.
 
 Summary
 -------
 
-
 ### Step 1 summary - Install tools and libraries needed for coreboot
-
 Depending on your distribution you have installed the minimum additional
-software requirements to continue with downloading and building
-coreboot.  Not every distribution has the tools, that would be required,
-installed by default. In the following we shortly introduce the purpose
-of the installed packages:
+software requirements to continue with downloading and building coreboot.
+Not every distribution has the tools, that would be required,
+installed by default. In the following we shortly introduce the purpose of the
+installed packages:
 
 * `build-essential` or `base-devel` are the basic tools for building software.
 * `git` is needed to download coreboot from the coreboot git repository.
@@ -183,89 +122,71 @@ of the installed packages:
 are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
 of the same version.
 
-If you started with a different distribution or package management
-system you might need to install other packages. Most likely they are
-named slightly different. If that is the case for you, we'd like to
-encourage you to contribute to the project and submit a pull request
-with an update for this documentation for your system.
-
+If you started with a different distribution or package management system you
+might need to install other packages. Most likely they are named slightly
+different. If that is the case for you, we'd like to encourage you to contribute
+to the project and submit a pull request with an update for this documentation
+for your system.
 
 ### Step 2 summary - Download coreboot source tree
-
-This will download a 'read-only' copy of the coreboot tree. This just
-means that if you made changes to the coreboot tree, you couldn't
-immediately contribute them back to the community. To pull a copy of
-coreboot that would allow you to contribute back, you would first need
-to sign up for an account on gerrit.
-
+This will download a 'read-only' copy of the coreboot tree. This just means
+that if you made changes to the coreboot tree, you couldn't immediately
+contribute them back to the community. To pull a copy of coreboot that would
+allow you to contribute back, you would first need to sign up for an account on
+gerrit.
 
 ### Step 3 summary - Build the coreboot toolchain.
-
-This builds one of the coreboot cross-compiler toolchains for X86
-platforms.  Because of the variability of compilers and the other
-required tools between the various operating systems that coreboot can
-be built on, coreboot supplies and uses its own cross-compiler toolchain
-to build the binaries that end up as part of the coreboot ROM. The
-toolchain provided by the operating system (the 'host toolchain') is
-used to build various tools that will run on the local system during the
-build process.
-
+This builds one of the coreboot cross-compiler toolchains for X86 platforms.
+Because of the variability of compilers and the other required tools between
+the various operating systems that coreboot can be built on, coreboot supplies
+and uses its own cross-compiler toolchain to build the binaries that end up as
+part of the coreboot ROM. The toolchain provided by the operating system (the
+'host toolchain') is used to build various tools that will run on the local
+system during the build process.
 
 ### Step 4 summary - Build the payload
-
-To actually do anything useful with coreboot, you need to build a
-payload to include into the rom. The idea behind coreboot is that it
-does the minimum amount possible before passing control of the machine
-to a payload. There are various payloads such as grub or SeaBIOS that
-are typically used to boot the operating system. Instead, we used
-coreinfo, a small demonstration payload that allows the user to look at
-various things such as memory and the contents of the coreboot file
-system (CBFS) - the pieces that make up the coreboot rom.
-
+To actually do anything useful with coreboot, you need to build a payload to
+include into the rom. The idea behind coreboot is that it does the minimum amount
+possible before passing control of the machine to a payload. There are various
+payloads such as grub or SeaBIOS that are typically used to boot the operating
+system. Instead, we used coreinfo, a small demonstration payload that allows the
+user to look at various things such as memory and the contents of the coreboot
+file system (CBFS) - the pieces that make up the coreboot rom.
 
 ### Step 5 summary - Configure the build
-
-This step configures coreboot's build options using the menuconfig
-interface to Kconfig. Kconfig is the same configuration program used by
-the linux kernel. It allows you to enable, disable, and change various
-values to control the coreboot build process, including which
-mainboard(motherboard) to use, which toolchain to use, and how the
-runtime debug console should be presented and saved.  Anytime you change
-mainboards in Kconfig, you should always run `make distclean` before
-running `make menuconfig`. Due to the way that Kconfig works, values
-will be kept from the previous mainboard if you skip the clean step.
-This leads to a hybrid configuration which may or may not work as
-expected.
-
+This step configures coreboot's build options using the menuconfig interface to
+Kconfig. Kconfig is the same configuration program used by the linux kernel. It
+allows you to enable, disable, and change various values to control the coreboot
+build process, including which mainboard(motherboard) to use, which toolchain to
+use, and how the runtime debug console should be presented and saved.
+Anytime you change mainboards in Kconfig, you should always run `make distclean`
+before running `make menuconfig`. Due to the way that Kconfig works, values will
+be kept from the previous mainboard if you skip the clean step. This leads to a
+hybrid configuration which may or may not work as expected.
 
 ### Step 6 summary - Build coreboot
-
-You may notice that a number of other pieces are downloaded at the
-beginning of the build process. These are the git submodules used in
-various coreboot builds.  By default, the _blobs_ submodule is not
-downloaded. This git submodule may be required for other builds for
-microcode or other binaries. To enable downloading this submodule,
-select the option "Allow use of binary-only repository" in the "General
-Setup" menu of Kconfig This attempts to build the coreboot rom. The rom
-file itself ends up in the build directory as 'coreboot.rom'. At the end
-of the build process, the build displayed the contents of the rom file.
-
+You may notice that a number of other pieces are downloaded at the beginning of
+the build process. These are the git submodules used in various coreboot builds.
+By default, the _blobs_ submodule is not downloaded. This git submodule may be
+required for other builds for microcode or other binaries. To enable downloading
+this submodule, select the option "Allow use of binary-only repository" in the
+"General Setup" menu of Kconfig
+This attempts to build the coreboot rom. The rom file itself ends up in the
+build directory as 'coreboot.rom'. At the end of the build process, the build
+displayed the contents of the rom file.
 
 ### Step 7 summary - Install QEMU
-
 QEMU is a processor emulator which we can use to show the coreboot boot
 process in a virtualised environment.
 
-
 ### Step 8 summary - Run QEMU
-
 Here's the command line instruction broken down:
 * `qemu-system-x86_64`
-This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3
-PCI to ISA bridge.
+This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
+ISA bridge.
 * `-bios build/coreboot.rom`
-Use the coreboot rom image that we just built. If this flag is left out,
-the standard SeaBIOS image that comes with QEMU is used.
+Use the coreboot rom image that we just built. If this flag is left out, the
+standard SeaBIOS image that comes with QEMU is used.
 * `-serial stdio`
-Send the serial output to the console. This allows you to view the
-coreboot boot log.
+Send the serial output to the console. This allows you to view the coreboot
+boot log.

Documentation/tutorial/part2.md

@@ -4,29 +4,28 @@
 
 If you already have an account, skip to Step 2.
 
-Otherwise, go to <https://review.coreboot.org> in your preferred web
-browser.  Select **Sign in** in the upper right corner.
+Otherwise, go to <https://review.coreboot.org> in your preferred web browser.
+Select **Sign in** in the upper right corner.
 
-Select the appropriate sign-in. For example, if you have a Google
-account, select **Google OAuth2** (gerrit-oauth-provider plugin).
-**Note:** Your username for the account will be the username of the
-account you used to sign-in with. (ex. your Google username).
+Select the appropriate sign-in. For example, if you have a Google account,
+select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your
+username for the account will be the username of the account you used to
+sign-in with. (ex. your Google username).
 
 ## Step 2a: Set up SSH keys
 
 If you prefer to use an HTTP password instead, skip to Step 2b.
 
-If you do not have an SSH key set up on your account already (as is the
-case with a newly created account), follow the instructions below;
-otherwise, doing so could overwrite an existing key.
+If you do not have an SSH key set up on your account already (as is the case
+with a newly created account), follow the instructions below; otherwise,
+doing so could overwrite an existing key.
 
 In a terminal, run `ssh-keygen -t ed25519` and confirm the default path
 `.ssh/id_ed25519`.
 
-Make a passphrase -- remember this phrase. It will be needed whenever
-you use this public key. **Note:** You might want to use a short
-password, or forego the password altogether as you will be using it very
-often.
+Make a passphrase -- remember this phrase. It will be needed whenever you use
+this public key. **Note:** You might want to use a short password, or
+forego the password altogether as you will be using it very often.
 
 Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix
 as you need to send the public key) into the textbox "New SSH Key" at
@@ -34,19 +33,17 @@ https://review.coreboot.org/settings/#SSHKeys and save it.
 
 ## Step 2b: Set up an HTTP Password
 
-Alternatively, instead of using SSH keys, you can use an HTTP password.
-To do so, after you select your name and click on **Settings** on the
-left-hand side, rather than selecting **SSH Public Keys**, select **HTTP
-Password**.
+Alternatively, instead of using SSH keys, you can use an HTTP password. To do so,
+after you select your name and click on **Settings** on the left-hand side, rather
+than selecting **SSH Public Keys**, select **HTTP Password**.
 
-Click **Generate Password**. This should fill the "Password" box with a
-password. Copy the password, and add the following to your
-`$HOME/.netrc` file:
+Click **Generate Password**. This should fill the "Password" box with a password. Copy
+the password, and add the following to your `$HOME/.netrc` file:
 
 	machine review.coreboot.org login YourUserNameHere password YourPasswordHere
 
-where YourUserNameHere is your username, and YourPasswordHere is the
-password you just generated.
+where YourUserNameHere is your username, and YourPasswordHere is the password you
+just generated.
 
 If your system is behind a snooping HTTPS proxy, you might also have to
 make its SSL certificate known to curl, a system specific operation.
@@ -58,28 +55,26 @@ certificate verification in git:
 The `--global` argument sets it for all git transfers of your local
 user, `false` means not to validate the certificate.
 
-If that still doesn't allow you to pull or push changes to the server,
-the proxy is likely tampering with the data stream, in which case
-there's nothing we can do.
+If that still doesn't allow you to pull or push changes to the server, the
+proxy is likely tampering with the data stream, in which case there's nothing
+we can do.
 
 ## Step 3: Clone coreboot and configure it for submitting patches
 
-On Gerrit, click on the **Browse** tab in the upper left corner and
-select **Repositories**. From the listing, select the "coreboot" repo.
-You may have to click the next page arrow at the bottom a few times to
-find it.
+On Gerrit, click on the **Browse** tab in the upper left corner and select
+**Repositories**. From the listing, select the "coreboot" repo. You may have
+to click the next page arrow at the bottom a few times to find it.
 
 If you are using SSH keys, select **ssh** from the tabs under "Project
-coreboot" and run the "clone with commit-msg hook" command that's
-provided.  This should prompt you for your id_rsa passphrase, if you
-previously set one.
+coreboot" and run the "clone with commit-msg hook" command that's provided.
+This should prompt you for your id_rsa passphrase, if you previously set one.
 
-**Note:** if the **ssh** option is not showing, check that you have a
-username set. Click the profile picture at the top right and select
-**User Settings**, then set your username in the **Profile** section.
+**Note:** if the **ssh** option is not showing, check that you have a username
+set. Click the profile picture at the top right and select **User Settings**,
+then set your username in the **Profile** section.
 
-If you are using HTTP, instead, select **http** from the tabs under
-"Project coreboot" and run the command that appears.
+If you are using HTTP, instead, select **http** from the tabs under "Project coreboot"
+and run the command that appears.
 
 Now is a good time to configure your global git identity, if you haven't
 already.
@@ -87,32 +82,30 @@ already.
 	git config --global user.name "Your Name"
 	git config --global user.email "Your Email"
 
-Finally, enter the local git repository and set up repository specific
-hooks and other configurations.
+Finally, enter the local git repository and set up repository specific hooks
+and other configurations.
 
 	cd coreboot
 	make gitconfig
 
 ## Step 4: Submit a commit
 
-An easy first commit to make is fixing existing checkpatch errors and
-warnings in the source files. To see errors that are already present,
-build the files in the repository by running `make lint` in the coreboot
-directory. Alternatively, if you want to run `make lint` on a specific
-directory, run:
+An easy first commit to make is fixing existing checkpatch errors and warnings
+in the source files. To see errors that are already present, build the files in
+the repository by running `make lint` in the coreboot directory. Alternatively,
+if you want to run `make lint` on a specific directory, run:
 
 	util/lint/lint-007-checkpatch <filepath>
 
-where `filepath` is the filepath of the directory (ex.
-`src/cpu/amd/car`).
+where `filepath` is the filepath of the directory (ex. `src/cpu/amd/car`).
 
 Any changes made to files under the src directory are made locally,
 and can be submitted for review.
 
-Once you finish making your desired changes, use the command line to
-stage and submit your changes. An alternative and potentially easier way
-to stage and submit commits is to use git cola, a graphical user
-interface for git. For instructions on how to do so, skip to Step 4b.
+Once you finish making your desired changes, use the command line to stage
+and submit your changes. An alternative and potentially easier way to stage
+and submit commits is to use git cola, a graphical user interface for git. For
+instructions on how to do so, skip to Step 4b.
 
 ## Step 4a: Use the command line to stage and submit a commit
 
@@ -126,21 +119,20 @@ To commit the change, run
 
 	git commit -s
 
-**Note:** The -s adds a signed-off-by line by the committer. Your commit
-should be signed off with your name and email (i.e. **Your Name**
-**\<Your Email\>**, based on what you set with git config earlier).
+**Note:** The -s adds a signed-off-by line by the committer. Your commit should be
+signed off with your name and email (i.e. **Your Name** **\<Your Email\>**, based on
+what you set with git config earlier).
 
-Running git commit first checks for any errors and warnings using lint.
-If there are any, you must go back and fix them before submitting your
-commit.  You can do so by making the necessary changes, and then staging
-your commit again.
+Running git commit first checks for any errors and warnings using lint. If
+there are any, you must go back and fix them before submitting your commit.
+You can do so by making the necessary changes, and then staging your commit again.
 
-When there are no errors or warnings, your default text editor will
-open.  This is where you will write your commit message.
+When there are no errors or warnings, your default text editor will open.
+This is where you will write your commit message.
 
-The first line of your commit message is your commit summary. This is a
-brief one-line description of what you changed in the files using the
-template below:
+The first line of your commit message is your commit summary. This is a brief
+one-line description of what you changed in the files using the template
+below:
 
     <filepath>: Short description
 
@@ -151,30 +143,29 @@ For example,
 **Note:** It is good practice to use present tense in your descriptions
 and do not punctuate your summary.
 
-Then hit Enter. The next paragraph should be a more in-depth explanation
-of the changes you've made to the files. Again, it is good practice to
-use present tense. Ex.
+Then hit Enter. The next paragraph should be a more in-depth explanation of the
+changes you've made to the files. Again, it is good practice to use present
+tense. Ex.
 
     Fix space prohibited between function name and open parenthesis,
-    line over 80 characters, unnecessary braces for single statement
-    blocks, space required before open brace errors and warnings.
+    line over 80 characters, unnecessary braces for single statement blocks,
+    space required before open brace errors and warnings.
 
-When you have finished writing your commit message, save and exit the
-text editor. You have finished committing your change. If, after
-submitting your commit, you wish to make changes to it, running `git
-commit --amend` allows you to take back your commit and amend it.
+When you have finished writing your commit message, save and exit the text
+editor. You have finished committing your change. If, after submitting your
+commit, you wish to make changes to it, running `git commit --amend` allows
+you to take back your commit and amend it.
 
-When you are done with your commit, run `git push` to push your commit
-to coreboot.org. **Note:** To submit as a private patch, use `git push
-origin HEAD:refs/for/master%private`. Submitting as a private patch
-means that your commit will be on review.coreboot.org, but is only
-visible to yourself and those you add as reviewers. This mode isn't
-perfect: Somebody who knows the commit ID can still fetch the change and
-everything it refers (e.g.  parent commits).
+When you are done with your commit, run `git push` to push your commit to
+coreboot.org. **Note:** To submit as a private patch, use
+`git push origin HEAD:refs/for/master%private`. Submitting as a private patch
+means that your commit will be on review.coreboot.org, but is only visible to
+yourself and those you add as reviewers. This mode isn't perfect: Somebody who
+knows the commit ID can still fetch the change and everything it refers (e.g.
+parent commits).
 
-This has been a quick primer on how to submit a change to Gerrit for
-review using git. You may wish to review the [Gerrit code review
-workflow
+This has been a quick primer on how to submit a change to Gerrit for review
+using git. You may wish to review the [Gerrit code review workflow
 documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review),
 especially if you plan to work on multiple changes at the same time.
 
@@ -205,14 +196,14 @@ in-depth explanation of the changes you've made to the files. Again, it
 is good practice to use present tense. Ex.
 
     Fix space prohibited between function name and open parenthesis,
-    line over 80 characters, unnecessary braces for single statement
-    blocks, space required before open brace errors and warnings.
+    line over 80 characters, unnecessary braces for single statement blocks,
+    space required before open brace errors and warnings.
 
 Then press Enter two times to move the cursor to below your description.
 To the left of the text boxes, there is an icon with an downward arrow.
-Press the arrow and select "Sign Off." Make sure that you are signing
-off with your name and email (i.e. **Your Name** **\<Your Email\>**,
-based on what you set with git config earlier).
+Press the arrow and select "Sign Off." Make sure that you are signing off
+with your name and email (i.e. **Your Name** **\<Your Email\>**, based on what
+you set with git config earlier).
 
 Now, review each of your changes and mark either individual changes or
 an entire file as Ready to Commit by marking it as 'Staged'. To do
@@ -243,11 +234,11 @@ and the commit succeeds, move to the command line and run `git push`.
 
 Your commits can now be seen on review.coreboot.org if you select "Your"
 and click on "Changes" and can be reviewed by others. Your code will
-first be reviewed by build bot (Jenkins), which will either give you a
-warning or verify a successful build; if so, your commit will receive a
-+1. Other users may also give your commit +1. For a commit to be merged,
-it needs to receive a +2. **Note:** A +1 and a +1 does not make a +2.
-Only certain users can give a +2.
+first be reviewed by build bot (Jenkins), which will either give you a warning
+or verify a successful build; if so, your commit will receive a +1. Other
+users may also give your commit +1. For a commit to be merged, it needs
+to receive a +2. **Note:** A +1 and a +1 does not make a +2. Only certain users
+can give a +2.
 
 ## Step 6 (optional): bash-git-prompt
 
@@ -264,11 +255,9 @@ as this one is specific to bash.
 Alternatively, follow the instructions below:
 Run the following two commands in the command line:
 
-```Bash
-cd
-git clone https://github.com/magicmonty/bash-git-prompt.git \
-    .bash-git-prompt --depth=1
-```
+    cd
+    git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1
+
 **Note:** cd will change your directory to your home directory, so the
 git clone command will be run there.
 
@@ -280,38 +269,36 @@ Finally, open the `~/.bashrc` file and append the following two lines:
 Now, whenever you are in a git repository, it will continuously display
 its state.
 
-There also are additional configurations that you can change depending
-on your preferences. If you wish to do so, look at the "All configs for
-.bashrc" section on <https://github.com/magicmonty/bash-git-prompt>.
-Listed in that section are various lines that you can copy, uncomment
-and add to your .bashrc file to change the configurations. Example
-configurations include avoid fetching remote status, and supporting
-versions of Git older than 1.7.10.
+There also are additional configurations that you can change depending on your
+preferences. If you wish to do so, look at the "All configs for .bashrc" section
+on <https://github.com/magicmonty/bash-git-prompt>. Listed in that section are
+various lines that you can copy, uncomment and add to your .bashrc file to
+change the configurations. Example configurations include avoid fetching remote
+status, and supporting versions of Git older than 1.7.10.
 
 ## Appendix: Miscellaneous Advice
 
 ### Updating a commit after running git push:
 
-Suppose you would like to update a commit that has already been pushed
-to the remote repository. If the commit you wish to update is the most
-recent commit you have made, after making your desired changes, stage
-the files (either using git add or in git cola), and amend the commit.
-To do so, if you are using the command line, run `git commit --amend`.
-If you are using git cola, click on the gear icon located on the upper
-left side under **Commit** and select **Amend Last Commit** in the drop
-down menu. Then, stage the files you have changed, commit the changes,
-and run git push to push the changes to the remote repository. Your
-change should be reflected in Gerrit as a new patch set.
+Suppose you would like to update a commit that has already been pushed to the
+remote repository. If the commit you wish to update is the most recent
+commit you have made, after making your desired changes, stage the files
+(either using git add or in git cola), and amend the commit. To do so,
+if you are using the command line, run `git commit --amend`. If you are
+using git cola, click on the gear icon located on the upper left side under
+**Commit** and select **Amend Last Commit** in the drop down menu. Then, stage
+the files you have changed, commit the changes, and run git push to push the
+changes to the remote repository. Your change should be reflected in Gerrit as
+a new patch set.
 
-If, however, the commit you wish to update is not the most recent commit
-you have made, you will first need to checkout that commit. To do so,
-find the URL of the commit on <https://review.coreboot.org> and go to
-that page; if the commit is one that you previously pushed, it can be
-found by selecting **My** and then **Changes** in the upper left corner.
-To checkout this commit, in the upper right corner, click on
-**Download**, and copy the command listed next to checkout by clicking
-**Copy to clipboard**. Then, run the copied command in your coreboot
-repository. Now, the last commit should be the most recent commit to
-that patch; to update it, make your desired changes, stage the files,
-then amend and push the commit using the instructions in the above
+If, however, the commit you wish to update is not the most recent commit you
+have made, you will first need to checkout that commit. To do so, find the
+URL of the commit on <https://review.coreboot.org> and go to that page; if
+the commit is one that you previously pushed, it can be found by selecting
+**My** and then **Changes** in the upper left corner. To checkout this commit,
+in the upper right corner, click on **Download**, and copy the command listed
+next to checkout by clicking **Copy to clipboard**. Then, run the copied
+command in your coreboot repository. Now, the last commit should be the most
+recent commit to that patch; to update it, make your desired changes, stage
+the files, then amend and push the commit using the instructions in the above
 paragraph.

Documentation/tutorial/part3.md

@@ -1,32 +1,31 @@
 # Writing unit tests for coreboot
 
 ## Introduction
-General thoughts about unit testing coreboot can be found in [Unit
-testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
-Additionally, [code coverage](../technotes/2021-05-code-coverage.md)
-support is available for unit tests.
+General thoughts about unit testing coreboot can be found in
+[Unit testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
+Additionally, [code coverage](../technotes/2021-05-code-coverage.md) support
+is available for unit tests.
 
-This document aims to guide developers through the process of adding and
-writing unit tests for coreboot modules.
+This document aims to guide developers through the process of adding and writing
+unit tests for coreboot modules.
 
-As an example of unit under test, `src/device/i2c.c` (referred hereafter
-as UUT "Unit Under Test") will be used. This is simple module, thus it
-should be easy for the reader to focus solely on the testing logic,
-without the need to spend too much time on digging deeply into the
-source code details and flow of operations. That being said, a good
-understanding of what the unit under test is doing is crucial for
-writing unit tests.
+As an example of unit under test, `src/device/i2c.c` (referred hereafter as UUT
+"Unit Under Test") will be used. This is simple module, thus it should be easy
+for the reader to focus solely on the testing logic, without the need to spend
+too much time on digging deeply into the source code details and flow of
+operations. That being said, a good understanding of what the unit under test is
+doing is crucial for writing unit tests.
 
 This tutorial should also be helpful for developers who want to follow
-[TDD](https://en.wikipedia.org/wiki/Test-driven_development). Even
-though TDD has a different work flow of building tests first, followed
-by the code that satisfies them, the process of writing tests and adding
-them to the tree is the same.
+[TDD](https://en.wikipedia.org/wiki/Test-driven_development). Even though TDD
+has a different work flow of building tests first, followed by the code that
+satisfies them, the process of writing tests and adding them to the tree is the
+same.
 
 ## Analysis of unit under test
-First of all, it is necessary to precisely establish what we want to
-test in a particular module. Usually this will be an externally exposed
-API, which can be used by other modules.
+First of all, it is necessary to precisely establish what we want to test in a
+particular module. Usually this will be an externally exposed API, which can be
+used by other modules.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -35,70 +34,66 @@ API, which can be used by other modules.
 
    .. code-block:: c
 
-     int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg,
-                 uint8_t *data, uint8_t mask, uint8_t shift)
-     int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg,
-                 uint8_t data, uint8_t mask, uint8_t shift)
+     int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data,
+                 uint8_t mask, uint8_t shift)
+     int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data,
+                 uint8_t mask, uint8_t shift)
 
-   For sake of simplicity, let's focus on `i2c_read_field` in this
-   document.
+   For sake of simplicity, let's focus on `i2c_read_field` in this document.
 ```
 
-Once the API is defined, the next question is __what__ this API is doing
-(or what it will be doing in case of TDD). In other words, what outputs
-we are expecting from particular functions, when providing particular
-input parameters.
+Once the API is defined, the next question is __what__ this API is doing (or
+what it will be doing in case of TDD). In other words, what outputs we are
+expecting from particular functions, when providing particular input parameters.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
    .. code-block:: c
 
-     int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg,
-                 uint8_t *data, uint8_t mask, uint8_t shift)
+     int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data,
+                 uint8_t mask, uint8_t shift)
 
-   This is a method which means to read content of register `reg` from
-   i2c device on i2c `bus` and slave address `chip`, applying bit `mask`
-   and offset `shift` to it. Returned data should be placed in `data`.
+   This is a method which means to read content of register `reg` from i2c device
+   on i2c `bus` and slave address `chip`, applying bit `mask` and offset `shift`
+   to it. Returned data should be placed in `data`.
 ```
 
-The next step is to determine all external dependencies of UUT in order
-to mock them out. Usually we want to isolate the UUT as much as
-possible, so that the test result depends __only__ on the behavior of
-UUT and not on the other modules. While some software dependencies may
-be hard to be mock (for example due to complicated dependencies) and
-thus should be simply linked into the test binaries, all hardware
-dependencies need to be mocked out, since in the user-space host
-environment, targets hardware is not available.
+The next step is to determine all external dependencies of UUT in order to mock
+them out. Usually we want to isolate the UUT as much as possible, so that the
+test result depends __only__ on the behavior of UUT and not on the other
+modules. While some software dependencies may be hard to be mock (for example
+due to complicated dependencies) and thus should be simply linked into the test
+binaries, all hardware dependencies need to be mocked out, since in the
+user-space host environment, targets hardware is not available.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
    `i2c_read_field` is calling `i2c_readb`, which eventually invokes
-   `i2c_transfer`. This method simply calls `platform_i2c_transfer`. The
-   last function in the chain is a hardware-touching one, and defined
-   separately for different SOCs. It is responsible for issuing
-   transactions on the i2c bus.  For the purpose of writing unit test,
-   we should mock this function.
+   `i2c_transfer`. This method simply calls `platform_i2c_transfer`. The last
+   function in the chain is a hardware-touching one, and defined separately for
+   different SOCs. It is responsible for issuing transactions on the i2c bus.
+   For the purpose of writing unit test, we should mock this function.
 ```
 
 ## Adding new tests
-In order to keep the tree clean, the `tests/` directory should mimic the
-`src/` directory, so that test harness code is placed in a location
-corresponding to UUT. Furthermore, the naming convention is to add the
-suffix `-test` to the UUT name when creating a new test harness file.
+In order to keep the tree clean, the `tests/` directory should mimic the `src/`
+directory, so that test harness code is placed in a location corresponding to
+UUT. Furthermore, the naming convention is to add the suffix `-test` to the UUT
+name when creating a new test harness file.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
    Considering that UUT is `src/device/i2c.c`, test file should be named
-   `tests/device/i2c-test.c`. When adding a new test file, it needs to
-   be registered with the coreboot unit testing infrastructure.
+   `tests/device/i2c-test.c`. When adding a new test file, it needs to be
+   registered with the coreboot unit testing infrastructure.
 ```
 
-Every directory under `tests/` should contain a Makefile.inc, similar to
-what can be seen under the `src/`. Register a new test in Makefile.inc,
-by __appending__ test name to the `tests-y` variable.
+Every directory under `tests/` should contain a Makefile.inc, similar to what
+can be seen under the `src/`. Register a new test in Makefile.inc, by
+__appending__ test name to the `tests-y` variable.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -108,11 +103,10 @@ by __appending__ test name to the `tests-y` variable.
      tests-y += i2c-test
 ```
 
-Next step is to list all source files, which should be linked together
-in order to create test binary. Usually a tests requires only two files
-- UUT and test harness code, but sometimes more is needed to provide the
-test environment.  Source files are registered in `<test_name>-srcs`
-variable.
+Next step is to list all source files, which should be linked together in order
+to create test binary. Usually a tests requires only two files - UUT and test
+harness code, but sometimes more is needed to provide the test environment.
+Source files are registered in `<test_name>-srcs` variable.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -123,10 +117,9 @@ variable.
      i2c-test-srcs += src/device/i2c.c
 ```
 
-Above minimal configuration is a basis for further work. One can try to
-build and run test binary either by invoking `make
-tests/<test_dir>/<test_name>` or by running all unit tests (whole suite)
-for coreboot `make unit-tests`.
+Above minimal configuration is a basis for further work. One can try to build
+and run test binary either by invoking `make tests/<test_dir>/<test_name>` or by
+running all unit tests (whole suite) for coreboot `make unit-tests`.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -142,34 +135,31 @@ for coreboot `make unit-tests`.
      make unit-tests
 ```
 
-When trying to build test binary, one can often see linker complains
-about `undefined reference` to couple of symbols. This is one of
-solutions to determine all external dependencies of UUT - iteratively
-build test and resolve errors one by one. At this step, developer should
-decide either it's better to add an extra module to provide necessary
-definitions or rather mock such dependency. Quick guide through adding
-mocks is provided later in this doc.
+When trying to build test binary, one can often see linker complains about
+`undefined reference` to couple of symbols. This is one of solutions to
+determine all external dependencies of UUT - iteratively build test and resolve
+errors one by one. At this step, developer should decide either it's better to
+add an extra module to provide necessary definitions or rather mock such
+dependency. Quick guide through adding mocks is provided later in this doc.
 
 ## Writing new tests
-In coreboot, [Cmocka](https://cmocka.org/) is used as unit test
-framework. The project has exhaustive [API
-documentation](https://api.cmocka.org/). Let's see how we may
-incorporate it when writing tests.
+In coreboot, [Cmocka](https://cmocka.org/) is used as unit test framework. The
+project has exhaustive [API documentation](https://api.cmocka.org/). Let's see
+how we may incorporate it when writing tests.
 
 ### Assertions
-Testing the UUT consists of calling the functions in the UUT and
-comparing the returned values to the expected values. Cmocka implements
-[a set of assert
-macros](https://api.cmocka.org/group__cmocka__asserts.html) to compare a
-value with an expected value. If the two values do not match, the test
+Testing the UUT consists of calling the functions in the UUT and comparing the
+returned values to the expected values. Cmocka implements
+[a set of assert macros](https://api.cmocka.org/group__cmocka__asserts.html) to
+compare a value with an expected value. If the two values do not match, the test
 fails with an error message.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
-   In our example, the simplest test is to call UUT for reading our fake
-   devices registers and do all calculation in the test harness itself.
-   At the end, let's compare integers with `assert_int_equal`.
+   In our example, the simplest test is to call UUT for reading our fake devices
+   registers and do all calculation in the test harness itself. At the end, let's
+   compare integers with `assert_int_equal`.
 
    .. code-block:: c
 
@@ -201,25 +191,24 @@ fails with an error message.
 ### Mocks
 
 #### Overview
-Many coreboot modules are low level software that touch hardware
-directly.  Because of this, one of the most important and challenging
-part of writing tests is to design and implement mocks. A mock is a
-software component which implements the API of another component so that
-the test can verify that certain functions are called (or not called),
-verify the parameters passed to those functions, and specify the return
-values from those functions. Mocks are especially useful when the API to
-be implemented is one that accesses hardware components.
+Many coreboot modules are low level software that touch hardware directly.
+Because of this, one of the most important and challenging part of
+writing tests is to design and implement mocks. A mock is a software component
+which implements the API of another component so that the test can verify that
+certain functions are called (or not called), verify the parameters passed to
+those functions, and specify the return values from those functions. Mocks are
+especially useful when the API to be implemented is one that accesses hardware
+components.
 
-When writing a mock, the developer implements the same API as the module
-being mocked. Such a mock may, for example, register a set of driver
-methods. Behind this API, there is usually a simulation of real
-hardware.
+When writing a mock, the developer implements the same API as the module being
+mocked. Such a mock may, for example, register a set of driver methods. Behind
+this API, there is usually a simulation of real hardware.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
-   For purpose of our i2c test, we may introduce two i2c devices with
-   set of registers, which simply are structs in memory.
+   For purpose of our i2c test, we may introduce two i2c devices with set of
+   registers, which simply are structs in memory.
 
    .. code-block:: c
 
@@ -277,17 +266,16 @@ hardware.
                      };
 ```
 
-Cmocka uses a feature that gcc provides for breaking dependencies at the
-link time. It is possible to override implementation of some function,
-with the method from test harness. This allows test harness to take
-control of execution from binary (during the execution of test), and
-stimulate UUT as required without changing the source code.
+Cmocka uses a feature that gcc provides for breaking dependencies at the link
+time. It is possible to override implementation of some function, with the
+method from test harness. This allows test harness to take control of execution
+from binary (during the execution of test), and stimulate UUT as required
+without changing the source code.
 
-coreboot unit test infrastructure supports overriding of functions at
-link time.  This is as simple as adding a `name_of_function` to be
-mocked into <test_name>-mocks variable in Makefile.inc. The result is
-that the test's implementation of that function is called instead of
-coreboot's.
+coreboot unit test infrastructure supports overriding of functions at link time.
+This is as simple as adding a `name_of_function` to be mocked into
+<test_name>-mocks variable in Makefile.inc. The result is that the test's
+implementation of that function is called instead of coreboot's.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -296,45 +284,44 @@ coreboot's.
 
      i2c-test-mocks += platform_i2c_transfer
 
-   Now, dev can write own implementation of `platform_i2c_transfer`.
-   This implementation instead of accessing real i2c bus, will
-   write/read from fake structs.
+   Now, dev can write own implementation of `platform_i2c_transfer`. This
+   implementation instead of accessing real i2c bus, will write/read from
+   fake structs.
 
    .. code-block:: c
 
-     int platform_i2c_transfer(unsigned int bus, struct i2c_msg
-                 *segments, int count)
+     int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
+             int count)
      {
      }
 ```
 
 #### Checking mock's arguments
-A test can verify the parameters provided by the UUT to the mock
-function. The developer may also verify that number of calls to mock is
-correct and the order of calls to particular mocks is as expected (See
-[this](https://api.cmocka.org/group__cmocka__call__order.html)). The
-Cmocka macros for checking parameters are described
-[here](https://api.cmocka.org/group__cmocka__param.html). In general, in
-mock function, one makes a call to `check_expected(<param_name>)` and in
-the corresponding test function, `expect*()` macro, with description
-which parameter in which mock should have particular value, or be inside
-a described range.
+A test can verify the parameters provided by the UUT to the mock function. The
+developer may also verify that number of calls to mock is correct and the order
+of calls to particular mocks is as expected (See
+[this](https://api.cmocka.org/group__cmocka__call__order.html)). The Cmocka
+macros for checking parameters are described
+[here](https://api.cmocka.org/group__cmocka__param.html). In general, in mock
+function, one makes a call to `check_expected(<param_name>)` and in the
+corresponding test function, `expect*()` macro, with description which parameter
+in which mock should have particular value, or be inside a described range.
 
 ```eval_rst
 .. admonition:: i2c-test example
 
-   In our example, we may want to check that `platform_i2c_transfer` is
-   fed with number of segments bigger than 0, each segment has flags
-   which are in supported range and each segment has buf which is
-   non-NULL. We are expecting such values for _every_ call, thus the
-   last parameter in `expect*` macros is -1.
+   In our example, we may want to check that `platform_i2c_transfer` is fed with
+   number of segments bigger than 0, each segment has flags which are in
+   supported range and each segment has buf which is non-NULL. We are expecting
+   such values for _every_ call, thus the last parameter in `expect*` macros is
+   -1.
 
    .. code-block:: c
 
      static void mock_expect_params_platform_i2c_transfer(void)
      {
-             unsigned long int expected_flags[] = {0, I2C_M_RD,
-                     I2C_M_TEN, I2C_M_RECV_LEN, I2C_M_NOSTART};
+             unsigned long int expected_flags[] = {0, I2C_M_RD, I2C_M_TEN,
+                     I2C_M_RECV_LEN, I2C_M_NOSTART};
 
              /* Flags should always be only within supported range */
              expect_in_set_count(platform_i2c_transfer, segments->flags,
@@ -343,8 +330,8 @@ a described range.
              expect_not_value_count(platform_i2c_transfer, segments->buf,
                      NULL, -1);
 
-             expect_in_range_count(platform_i2c_transfer, count, 1,
-                     INT_MAX, -1);
+             expect_in_range_count(platform_i2c_transfer, count, 1, INT_MAX,
+                     -1);
      }
 
    And the checks below should be added to our mock
@@ -360,11 +347,11 @@ a described range.
 ```
 
 #### Instrument mocks
-It is possible for the test function to instrument what the mock will
-return to the UUT. This can be done by using the `will_return*()` and
-`mock()` macros.  These are described in [the Mock Object
-section](https://api.cmocka.org/group__cmocka__mock.html) of the Cmocka
-API documentation.
+It is possible for the test function to instrument what the mock will return to
+the UUT. This can be done by using the `will_return*()` and `mock()` macros.
+These are described in
+[the Mock Object section](https://api.cmocka.org/group__cmocka__mock.html) of
+the Cmocka API documentation.
 
 ```eval_rst
 .. admonition:: Example
@@ -374,18 +361,17 @@ API documentation.
 ```
 
 ### Test runner
-Finally, the developer needs to implement the test `main()` function.
-All tests should be registered there and cmocka test runner invoked. All
-methods for invoking Cmocka test are described
+Finally, the developer needs to implement the test `main()` function. All tests
+should be registered there and cmocka test runner invoked. All methods for
+invoking Cmocka test are described
 [here](https://api.cmocka.org/group__cmocka__exec.html).
 
 ```eval_rst
 .. admonition:: i2c-test example
 
-   We don't need any extra setup and teardown functions for i2c-test, so
-   let's simply register test for `i2c_read_field` and return from main
-   value which is output of Cmocka's runner (it returns number of tests
-   that failed).
+   We don't need any extra setup and teardown functions for i2c-test, so let's
+   simply register test for `i2c_read_field` and return from main value which is
+   output of Cmocka's runner (it returns number of tests that failed).
 
    .. code-block:: c
 

Documentation/util.md

@@ -1,36 +1,19 @@
-
-[//]: # ( DO NOT EDIT - AUTOGENERATED FILE )
-
-[//]: # ( RUN 'util/util_readme/util_readme.sh' to regenerate )
-
 # Utilities
 
 ## List of utils
 
 _Scripts and programs found in the coreboot `./util` directory_
-
 * __abuild__ - coreboot autobuild script builds coreboot images for all
 available targets. `bash`
 * __acpi__ - Walk through all ACPI tables with their addresses. `bash`
 * __amdfwtool__ - Create AMD Firmware combination `C`
-* __amdtools__ Various tools for AMD processors
-	* _update_efs_spi_speed_ - Change SPI speed in binary. `Bash`
-	* Tools to compare extended K8 memory settings.
-	* _k8-compare-pci-space.pl_ - Shows differences between values
-in PCI space and the default value. `Perl`
-	* _k8-interpret-extended-memory-settings.pl_ - Shows
-differences between memory controller values and the default value.
-`Perl`
-	* _k8-read-mem-settings.sh_ - Makes data files understood by
-the k8-interpret-extended-memory-settings script. `Bash`
-	* _parse-bkdg.pl_ - Make bkdg.data file used by above scripts.
-`Perl`
-	* _example_input_ - Sample input for the above scripts. `Text`
+* __amdtools__ - A set of tools to compare extended) K8 memory
+settings. `Perl`
 * __apcb__ - AMD PSP Control Block tools
 	* _apcb_edit.py_ - This tool allows patching an existing APCB
 binary with specific SPDs and GPIO selection pins. `Python3`
-	* _apcb_v3_edit.py_ - This tool allows patching an existing
-APCB v3 binary with up to 16 specific SPDs. `Python3`
+	* _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3
+binary with specific SPDs. `Python3`
 * __archive__ - Concatenate files and create an archive `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`
@@ -42,42 +25,42 @@ status repository `Bash` `Go`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
-	* _cbfstool_ - For manipulating CBFS file `C`
+	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file
+`C`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`
 * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
-* __chromeos__ - These scripts can be used to access ChromeOS
+* __chromeos__ - These scripts can be used to access Chrome OS
 resources, for example to extract System Agent reference code and other
-blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
+blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS
 recovery image. `C`
 * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
-libc support) `Bash`
+libc support)
 * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
-_coreboot.org-status_ and _docs.coreboot.org_ `Make`
+_coreboot.org-status_ and _docs.coreboot.org_
 * __dtd_parser__ - DTD structure parser `Python2`
 * __ectool__ - Dumps the RAM of a laptop's Embedded/Environmental
 Controller (EC). `C`
 * __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2).
 `Python3`
-* __find_usbdebug__ - Help find USB debug ports `Bash`
+* __find_usbdebug__ - Help find USB debug ports
 * __futility__ - Firmware utility for signing ChromeOS images `Make`
 * __fuzz-tests__ - Create test cases that crash the jpeg code. `C`
 * __genbuild_h__ - Generate build system definitions `Shell`
 * __gitconfig__ - Initialize git repository submodules install git
 hooks `Bash`
-* __ifdtool__ - Extract and dump Intel Firmware Descriptor information
-`C`
+* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware
+Descriptor information `C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - convert the configuration DW0/1 registers value from
-an inteltool dump to coreboot macros. `go`
+* __intelp2m__ - Intel Pad to Macro (intelp2m) converter 'Go'
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`
 * __ipqheader__
-	* _createxbl.py_ - Concatenates XBL segments into one ELF image
-`Python`
+	* _createxbl.py_ - Concatenates XBL segments into one ELF
+image `Python`
 	* _ipqheader.py_ - Returns a packed MBN header image with the
 specified base and size `Python`
 	* _mbncat.py_ - Generate ipq8064 uber SBL `Python`
@@ -88,8 +71,6 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
 embedded controller and insert them to the firmware image. `C`
 * __kconfig__ - Build system `Make`
 * __lint__ - Source linter and linting rules `Shell`
-* __liveiso__ - A script and NixOS configuration files to create an ISO
-image for testing purposes and for working on firmware. `Bash`
 * __mainboard__ - mainboard specific scripts
 	* _google_ - Directory for google mainboard specific scripts
 * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
@@ -101,12 +82,14 @@ partial deblobbing of Intel ME/TXE firmware images `Python`
 * __nvidia__ - nvidia blob parsers
 * __nvramtool__ - Reads and writes coreboot parameters and displaying
 information from the coreboot table in CMOS/NVRAM. `C`
+* __pgtblgen__ - Generates page tables based on fixed physical address.
+`C`
 * __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo
 ThinkPads. PMH7 is used for switching on and off the power of some
 devices on the board such as dGPU. `C`
 * __post__ - Userspace utility that can be used to test POST cards. `C`
 * __qemu__ - Makefile & comprehensive default config for QEMU Q35
-emulation `Make`
+emulation
 * __qualcomm__ - CMM script to debug Qualcomm coreboot environments.
 `CMM`
 * __release__ - Generate coreboot release `Bash`
@@ -123,7 +106,7 @@ command line `Bash`
 	* _cross-repo-cherrypick_ - Pull in patches from another tree
 from a gerrit repository. `Shell`
 	* _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files
-into various human readable formats. `Bash`
+into various human readable formats.
 	* _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an
 fmaptool compatible .fmd format `Bash`
 	* _find-unused-kconfig-symbols.sh_ - Points out Kconfig
@@ -144,6 +127,12 @@ file `Perl`
 * __spdtool__ - Dumps SPD ROMs from a given blob to separate files
 using known patterns and reserved bits. Useful for analysing firmware
 that holds SPDs on boards that have soldered down DRAM. `python`
+* __spd_tools__ - Tools for generating SPD files for DDR4 memory used
+in platforms with memory down configuration.
+	* _gen_spd.go_ - Generates de-duplicated SPD files using a
+global memory part list provided by the mainboard in JSON format. `Go`
+	* _gen_part_id.go_ - Allocates DRAM strap IDs for different
+DDR4 memory parts used by the board. `Go`
 * __spkmodem_recv__ - Decode spkmodem signals `C`
 * __superiotool__ - A user-space utility to detect Super I/O of a
 mainboard and provide detailed information about the register contents
@@ -163,11 +152,10 @@ the documentation `Bash`
 `Go`
 * __xcompile__ - Cross compile setup `Bash`
 
-## In depth documentation
 
-* [cbfstool](util/cbfstool/index.md)
-* [ifdtool](util/ifdtool/index.md)
-* [intelp2m](util/intelp2m/index.md)
+ ## In depth documentation
+
+* [ifdtool](ifdtool/index.md)
 
 ## Generated documentation
 

Documentation/util/intelp2m/index.md

@@ -1,210 +0,0 @@
-Intel Pad to Macro (intelp2m) converter
-=======================================
-
-This utility allows one to convert the configuration DW0/1 register
-values from an inteltool dump to coreboot macros.
-
-```bash
-cd util/intelp2m
-make
-./intelp2m -h
-./intelp2m -file /path/to/inteltool.log
-```
-
-### Platforms
-
-It is possible to use templates for parsing inteltool.log files.
-To specify such a pattern, use the option `-t <template number>`.
-
-```text
-    -t
-    template type number
-        0 - inteltool.log (default)
-        1 - gpio.h
-        2 - your template
-```
-
-For example, using template type 1, you can parse gpio.h from an
-existing board in the coreboot project.
-
-```bash
-./intelp2m -t 1 -file coreboot/src/mainboard/yourboard/gpio.h
-```
-
-You can also add a template to 'parser/template.go' for your file type
-with the configuration of the pads.
-
-platform type is set using the -p option (Sunrise by default):
-
-```text
--p string
-  set up a platform
-    snr - Sunrise PCH with Skylake/Kaby Lake CPU
-    lbg - Lewisburg PCH with Xeon SP CPU
-    apl - Apollo Lake SoC
-    cnl - CannonLake-LP or Whiskeylake/Coffeelake/Cometlake-U SoC
-    adl - AlderLake PCH
-  (default "snr")
-```
-
-```bash
-./intelp2m -p <platform> -file path/to/inteltool.log
-```
-
-### Packages
-
-![][pckgs]
-
-[pckgs]: gopackages.png
-
-### Bit fields in macros
-
-Use the `-fld=cb` option to only generate a sequence of bit fields in
-a new macro:
-
-```bash
-./intelp2m -fld cb -p apl -file ../apollo-inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPIO_37, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_TRIG(OFF), \
-    PAD_PULL(DN_20K)), /* LPSS_UART0_TXD */
-```
-
-### Raw DW0, DW1 register value
-
-To generate the gpio.c with raw PAD_CFG_DW0 and PAD_CFG_DW1 register
-values you need to use the -fld=raw option:
-
-```bash
-./intelp2m -fld raw -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-```bash
-./intelp2m -iiii -fld raw -file /path/to/inteltool.log
-```
-
-```c
-/* GPP_A10 - CLKOUT_LPC1 */
-/* DW0: 0x44000500, DW1: 0x00000000 */
-/* DW0: 0x04000100 - IGNORED */
-/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
-_PAD_CFG_STRUCT(GPP_A10, 0x44000500, 0x00000000),
-```
-
-### Macro Check
-
-After generating the macro, the utility checks all used
-fields of the configuration registers. If some field has been
-ignored, the utility generates field macros. To not check
-macros, use the -n option:
-
-```bash
-./intelp2m -n -file /path/to/inteltool.log
-```
-
-In this case, some fields of the configuration registers
-DW0 will be ignored.
-
-```c
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),
-```
-
-### Information level
-
-The utility can generate additional information about the bit
-fields of the DW0 and DW1 configuration registers. Using the
-options -i, -ii, -iii, -iiii you can set the info level from
-1 to 4:
-
-```bash
-./intelp2m -i -file /path/to/inteltool.log
-```
-
-```c
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),\
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),    /* LPSS_UART0_TXD */
-```
-
-```bash
-./intelp2m -ii -file /path/to/inteltool.log
-./intelp2m -iii -file /path/to/inteltool.log
-./intelp2m -iiii -file /path/to/inteltool.log
-```
-
-```c
-/* GPIO_39 - LPSS_UART0_TXD */
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE,
-   DISPUPD), */ --> (iiii)
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
-```
-
-If the -n switch was used and macros was generated without checking:
-```c
-/* GPIO_39 - LPSS_UART0_TXD */ --> (i)
-/* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii)
-/* DW0: PAD_TRIG(OFF) - IGNORED */ --> (iii)
-/* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) |
-  PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii)
-PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, \
-    DISPUPD),
-```
-
-### Ignoring Fields
-
-Utilities can generate the _PAD_CFG_STRUCT macro and exclude fields
-from it that are not in the corresponding PAD_CFG_*() macro:
-
-```bash
-./intelp2m -iiii -fld cb -ign -file /path/to/inteltool.log
-```
-
-```c
-/* GPIO_39 - LPSS_UART0_TXD */
-/* DW0: 0x44000400, DW1: 0x00003100 */
-/* DW0: PAD_TRIG(OFF) - IGNORED */
-/* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1,
-   TxLASTRxE, DISPUPD), */
-_PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP), \
-    PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)),
-```
-
-### FSP-style macro
-
-The utility allows one to generate macros that include fsp/edk2-platform
-style bitfields:
-
-```bash
-./intelp2m -i -fld fsp -p lbg -file ../crb-inteltool.log
-```
-
-```c
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },    /* GPIO */
-```
-
-```bash
-./intelp2m -iiii -fld fsp -p lbg -file ../crb-inteltool.log
-```
-
-```c
-/* GPP_A12 - GPIO */
-/* DW0: 0x80880102, DW1: 0x00000000 */
-/* PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT), */
-{ GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInvOut,
-  GpioOutLow, GpioIntSci | GpioIntLvlEdgDis, GpioResetNormal, GpioTermNone,
-  GpioPadConfigLock },
-```
-
-### Supported Chipsets
-
-  Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonLake-LP SoCs

LICENSES/BSD-2-Clause-Patent.txt

@@ -1,49 +0,0 @@
-Redistribution and use in source and binary forms, with or without
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LICENSES/BSD-2-Clause.txt

@@ -1,23 +0,0 @@
-Copyright (c) <year> <owner>.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
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-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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LICENSES/BSD-4-Clause-UC.txt

@@ -1,31 +0,0 @@
-Copyright [various years] The Regents of the University of California.
-All rights reserved.
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-modification, are permitted provided that the following conditions are
-met:
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-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. All advertising materials mentioning features or use of this software
-   must display the following acknowledgement: This product includes
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