mb/system76/adl: galp6: Fix GLAN RTD3

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I9d5cf318dcbbe4bda916b1a17469e1ad6b6b58e4

.gitmodules

@@ -1,67 +1,67 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk

Documentation/Makefile

@@ -10,9 +10,9 @@ FIGS=codeflow.pdf hypertransport.pdf
 
 all: corebootPortingGuide.pdf
 
-SVG2PDF=$(shell command -v svg2pdf)
-INKSCAPE=$(shell command -v inkscape)
-CONVERT=$(shell command -v convert)
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
 
 codeflow.pdf: codeflow.svg
 ifneq ($(strip $(SVG2PDF)),)

Documentation/acpi/index.md

@@ -10,10 +10,3 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
-
-
-##  ACPI specification - Useful links
-
-- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)

Documentation/acronyms.md

@@ -90,7 +90,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ASPM - PCI: [**Active State Power
   Management**](https://en.wikipedia.org/wiki/Active_State_Power_Management)
 * ATA - [**Advanced Technology Attachment**](https://en.wikipedia.org/wiki/Parallel_ATA)
-* ATS - PCIe: Address Translation Services
 * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI)
 * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX)
 * AVX -  [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions)
@@ -235,7 +234,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DDI -  Intel: Digital Display Interface
 * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
 * DEVAPC - Mediatek: Device Access Permission Control
-* DF - Data Fabric
 * DFP - USB: Downstream Facing port
 * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
 * DID - Device Identifier
@@ -284,7 +282,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
   vs Integrated TPMs or fTPMs (Firmware TPMs).
 * DTS - U-Boot: Device Tree Source
-* DUT - Device Under Test
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
@@ -298,7 +295,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 ## E
 
 * EBDA - Extended BIOS Data Area
-* EBG - Intel: Emmitsburg PCH
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
@@ -312,7 +308,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
   electrical erasable programmable ROM).
 * EFI - [**Extensible Firmware Interface**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface)
-* EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process.
 * EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29#EHCI) - USB 2.0
 * EHL - Intel: [**Elkhart Lake**](https://en.wikichip.org/wiki/intel/cores/elkhart_lake)
 * EIDE - Enhanced Integrated Drive Electronics
@@ -364,7 +359,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
 * FSP - Intel: Firmware Support Package
-* FSR - Intel: Firmware Status Register
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
 * fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
   based in firmware instead of actual hardware.  It typically runs in
@@ -391,7 +385,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GNB - Graphics NorthBridge
 * GNVS - Global Non-Volatile Storage
 * GPD - PCH GPIO in Deep Sleep well (D5 power)
-* GPE - ACPI: General Purpose Event
 * GPI - GPIOs: GPIO Input
 * GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_Input/Output) (Pin)
 * GPMR - Intel: General Purpose Memory Range
@@ -403,8 +396,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GPU - [**Graphics Processing Unit**](https://en.wikipedia.org/wiki/Graphics_processing_unit)
 * GSoC - [**Google Summer of Code**](https://en.wikipedia.org/wiki/Google_Summer_of_Code)
 * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
-* GSPI - Generic SPI - These are SPI controllers available for general
-  use, not dedicated to flash, for example.
 * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
 
 
@@ -419,9 +410,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * HID - [**Human Interface
   Device**](https://en.wikipedia.org/wiki/Human_interface_device)
 * HOB - UEFI: Hand-Off Block
-* HPD - Hot-Plug Detect
 * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
-* HSP - AMD: Hardware Security Processor
 * HSTI - Hardware Security Test Interface
 * HSW - Intel: Haswell
 * Hybrid S3 - System Power State:  This is where the operating system
@@ -467,7 +456,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IF - AMD: [**Infinity
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
-* IFD - Intel: Intel Flash Descriptor
 * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
   into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
   This never worked well for anything beyond fan control and caused
@@ -501,7 +489,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IVHD - ACPI: I/O Virtualization Hardware Definition
 * IVMD - ACPI: I/O Virtualization Memory Definition
 * IVRS - I/O Virtualization Reporting Structure
-* IWYU - Include What you Use - A tool to help with include file use
 
 
 ## J
@@ -542,7 +529,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * LAPIC - Local APIC
 * LBA - Logical Block Address
 * LCD - Liquid Crystal Display
-* LCAP - PCIe: Link Capabilities
+* LCAP - PCIe:Link Capabilities
 * LED - Light Emitting Diode
 * LF - Line Feed - The standard Unix EOL (End-of-Line) marker.
 * LGTM - Looks Good To Me
@@ -555,7 +542,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   count**](http://www.intel.com/design/chipsets/industry/lpc.htm) bus
   was a replacement for the ISA bus, created by serializing a number of
   parallel signals to get rid of those connections.
-* LPM - USB: Link Power Management
 * LPT - Line Print Terminal, Local Print Terminal, or Line Printer. -
   The Parallel Port
 * LRU - Least Recently Used - a rule used in operating systems that
@@ -572,10 +558,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * M.2 - An interface specification for small peripheral cards.
 * MAC Address - Media Access Control Address
-* MAFS - (eSPI) Master Attached Flash Sharing: Flash components are
-  attached to the controller device and may be accessed by by the
-  peripheral devices through the eSPI flash access channel.
-* MBP - Intel UEFI: ME-to-BIOS Payload
 * MBR - Master Boot Record
 * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
 * MCR - Machine Check Registers
@@ -643,7 +625,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 ## N
 
 * Nack - Negative Acknowledgement
-* NB - North Bridge
 * NBCI - Nvidia: NoteBook Common Interface
 * NC - GPIOs: No Connect
 * NDA - Non-Disclosure Agreement.
@@ -722,9 +703,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PCMCIA: Personal Computer Memory Card International Association
 * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
 * PCR: TPM: Platform Configuration Register
-* PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor.
-  The resistor allows the pin to be set to the reference voltage as
-  needed.
+* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage.  Setting it low drives it to ground through a resistor.
 * PD - Power Delivery - This is a specification for communicating power
   needs and availability between two devices, typically over USB type C.
 * PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU
@@ -732,7 +711,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PEI - UEFI: Pre-EFI Initialization
 * PEIM - UEFI: PEI Module
 * PEP - Intel: Power Engine Plug-in
-* PHX - AMD: Phoenix SoC
 * PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
   hardware that implements the send/receive functionality of a
   communication protocol.
@@ -774,19 +752,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * POTS - [**Plain Old Telephone
   Service**](https://en.wikipedia.org/wiki/Plain_old_telephone_service)
 * PPI - UEFI: PEIM-to-PEIM Interface
-* PPR - Processor Programming Reference
+* PPR: Processor Programming Reference
 * PPT - AMD: Package Power Tracking
-* PROM - Programmable Read Only Memory
+* PROM: Programmable Read Only Memory
 * Proto - Production Timeline: The first initial production to test key
   concepts.
 * PSE - Page Size Extention
-* PSF - Intel: Primary Sideband Fabric
 * PSP - AMD: Platform Security Processor
 * PSPP - AMD: PCIE Speed Power Policy
-* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
-* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
-  resistor. The resistor allows the signal to still be set to ground
-  when needed.
+* PU - GPIOs: Pull-Up - Setting the pin low drives it to ground.  Setting it high drives it to the reference voltage through a resistor.
 * PVT - Production Timeline: (Production Validation Test
 * PWM - Pulse Width Modulation
 * PXE - Pre-boot Execution Environment
@@ -832,7 +806,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * RRG - AMD (ATI): Register Reference Guide
 * RSDP - Root System Description Pointer
 * RTC - Real Time Clock
-* RTD3 - Power State: Runtime D3
 * RTFM - Read the Fucking Manual
 * RTOS - Real-Time Operating System
 * RVP - Intel: Reference Validation Platform
@@ -868,11 +841,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   contents of memory.  Any critical processor state is restored.
 * S5 - ACPI System Power State: System is “completely powered off”, but
   still has power going to the board.
-* SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the
-  peripheral device.  Only valid for server platforms.
-* SAGV - Intel: System Agent Geyserville. The original internal name
-  for the feature eventually released as Speedstep which controls the
-  processor voltage and frequencies.
 * SAR - The [**Specific Absorption
   Rate**](https://en.wikipedia.org/wiki/Specific_absorption_rate) is the
   measurement for the amount of Radio Frequency (RF) energy absorbed by
@@ -896,7 +864,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   SAS (Serial Attached SCSI).  The initial version is now often referred
   to as Parallel SCSI.
 * SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card
-* SDHCI - SD Host Controller Interface
 * SDRAM - Synchronous DRAM
 * SDLE: AMD: Stardust Dynamic Load Emulator
 * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
@@ -941,7 +908,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SPL - AMD: Security Patch Level
 * SPM - Mediatek: System Power Manager
 * SPMI - MIPI: System Power Management Interface
-* SPR - Sapphire Rapids
 * SRAM - Static Random Access Memory
 * SSD - Solid State Drive
 * SSDT - Secondary System Descriptor Table - ACPI table
@@ -995,8 +961,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TOLUM - Top of Low Usable Memory
 * ToM - Top of Memory
 * TPM - Trusted Platform Module
-* TS - TimeStamp
-* TSN - Time-Sensitive Networking
+* TS - TimeStamp -
 * TSC - [**Time Stamp
   Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
 * TSEG - TOM (Top of Memory) Segment
@@ -1014,7 +979,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
 * UEFI - Unified Extensible Firmware Interface
-* UFC - User Facing Camera
 * UFP - USB: Upstream Facing Port
 * UFS - Universal Flash storage
 * UHCI - USB: [**Universal Host Controller
@@ -1037,7 +1001,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VBIOS - Video BIOS
 * VBNV - Vboot Non-Volatile storage
 * VBT - [**Video BIOS
-  Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
+  Table**](https://01.org/linuxgraphics/gfx-docs/drm/ch04s02.html#id-1.4.3.4.16)
 * VESA - Video Electronics Standards Association
 * VGA: Video Graphics Array
 * VID: Vendor Identifier
@@ -1064,7 +1028,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   devices that open 360 degrees, or on the outside of the cover.  For
   tablets, it's on the the side away from the screen.
 * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
-* WFC - World Facing Camera
 * WLAN - Wireless LAN (Local Area Network)
 * WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)

Documentation/contributing/gerrit_guidelines.md

@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * In general, patches should remain open for review for at least 24 hours
 since the last significant modification to the change. The purpose is to
@@ -127,54 +127,6 @@ those platforms. While it would be nice to update any other platforms, you
 must at least provide a path that will allow other platforms to continue
 working.
 
-Sign-off Procedure
-------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
 
 Recommendations for gerrit activity
 -----------------------------------
@@ -221,10 +173,7 @@ This helps verify that the patch train won’t tie up the jenkins builders
 for no reason if there are failing patches in the train. For running
 parallel builds, you can specify the number of cores to use by setting the
 the CPUS environment variable. Example:
-
-```Bash
-make what-jenkins-does CPUS=8
-```
+        make what-jenkins-does CPUS=8
 
 * Use a topic when pushing a train of patches. This groups the commits
 together so people can easily see the connection at the top level of
@@ -232,10 +181,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
 commits with the i915-kernel-x60 set, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -245,10 +191,7 @@ Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
 isn't as obvious as the commit message. These patches can also be pushed with
 the wip flag:
-
-```Bash
-git push origin HEAD:refs/for/master%wip
-```
+	git push origin HEAD:refs/for/master%wip
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
@@ -257,16 +200,10 @@ sorts of patches are frequently posted as ideas or RFCs for the community to
 look at. Note that private changes can still be fetched from Gerrit by anybody
 who knows their commit ID, so don't use this for sensitive changes. To push
 a private change, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%private
-```
+        git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:
-
-```Bash
-git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -340,15 +277,13 @@ git/gerrit tags by prepending the lines with 'Original-'.  Marking
 the original text this way makes it much easier to tell what changes
 happened in which repository. This applies to these lines, not the actual
 commit message itself:
-
-	* Commit-Id:
-	* Change-Id:
-	* Signed-off-by:
-	* Reviewed-on:
-	* Tested-by:
-	* Reviewed-by:
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
+        Commit-Id:
+        Change-Id:
+        Signed-off-by:
+        Reviewed-on:
+        Tested-by:
+        Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
@@ -434,7 +369,3 @@ Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
 
 [ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes

Documentation/contributing/gsoc.md

@@ -1,16 +1,5 @@
 # Google Summer of Code
 
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
 
 ## Contacts
 
@@ -19,6 +8,9 @@ please have a look at our [community forums] and reach out to us. Working closel
 with the community is highly encouraged, as we've seen that our most successful
 contributors are generally very involved.
 
+Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
+2022. Please feel free to reach out to them directly if you have any questions.
+
 
 ## Why work on coreboot for GSoC?
 
@@ -59,8 +51,6 @@ contributors are generally very involved.
 
   * [Glossary][GSoC Glossary]
 
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
 
 ## Contributor requirements & commitments
 
@@ -101,7 +91,7 @@ amount of spare time. If this is not the case, then you should not apply.
       process and common issues.
 
     * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
+      Check the [easy project list][Project ideas] or ask for simple tasks on
       the [mailing list] or on our other [community forums] if you need ideas.
 
 
@@ -283,4 +273,3 @@ questions.
 [GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
 [GSoC Rules]: https://summerofcode.withgoogle.com/rules
 [GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips

Documentation/contributing/project_ideas.md

@@ -20,12 +20,12 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Small projects
+## Easy projects
 
 This is a collection of tasks which don't require deep knowledge on
 coreboot itself. If you are a beginner and want to get familiar with the
 the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
+dirty with some easy tasks, then these are for you.
 
   * Resolve static analysis issues reported by [scan-build] and
     [Coverity scan]. More details on the page for
@@ -36,7 +36,7 @@ dirty with some small tasks, then these are for you.
 [scan-build]: https://coreboot.org/scan-build/
 [Coverity scan]: https://scan.coverity.com/projects/coreboot
 [Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
+[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
 
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
@@ -63,6 +63,7 @@ non-Linux builds or Docker for different Linux distributions.
 * hardware requirements: Nothing special
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Support Power9/Power8 in coreboot
 There are some basic PPC64 stubs in coreboot, and there's open hardware
@@ -87,7 +88,7 @@ across architectures.
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
 to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
+yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a
 combination of payload and architecture to support.
@@ -129,6 +130,7 @@ their bug reports.
   going on from the resulting logs.
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Extend Ghidra to support analysis of firmware images
 [Ghidra](https://ghidra-sre.org) is a recently released cross-platform

Documentation/distributions.md

@@ -71,8 +71,6 @@ focusing on clean and simple code, long-term maintenance, transparent
 validation, privacy-respecting implementation, liberty for the owners, and
 trustworthiness for all.
 
-Contributions are welcome,
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
 
 ### MrChromebox
 

Documentation/external_docs.md

@@ -24,33 +24,11 @@ Please add any helpful or informational links and sections as you see fit.
 
 * [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
 * [Interface BUS](http://www.interfacebus.com/)
+* Open course material for a variety of topics such as assembly, firmware,
+  security, debugging, and more.
+  * [Open Security Training](https://opensecuritytraining.info/Training.html),
+  * [Open Security Training 2](https://p.ost2.fyi/)
 
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
 
 ## Firmware Specifications & Information
 

Documentation/index.md

@@ -1,8 +1,9 @@
 # Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
-It is built from Markdown files in the [Documentation] directory in the
-source code.
+It is built from Markdown files in the
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
 
 ## Spelling of coreboot
 
@@ -142,7 +143,7 @@ say hello!
 ## Getting the source code
 
 coreboot is primarily developed in the
-[git](https://review.coreboot.org/plugins/gitiles/coreboot) version control
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
 system, using [Gerrit](https://review.coreboot.org) to manage
 contributions and code review.
 
@@ -192,12 +193,9 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Software Bill of Materials](sbom/sbom.md)
 * [Project infrastructure & services](infrastructure/index.md)
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Acronyms & Definitions](acronyms.md)
 * [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)
-
-[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/

Documentation/mainboard/asrock/h77pro4-m.md

@@ -45,9 +45,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
 - Rear eSATA connector (multiplexed with one ASM1061 port)
 - Gigabit Ethernet
 - Console output on the serial port
-- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
-Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
-- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
+- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
 extlinux
 - Internal flashing with flashrom-1.2, see
 [Internal Programming](#internal-programming)

Documentation/mainboard/asus/p2b-ls.md

@@ -1,108 +0,0 @@
-# ASUS P2B-LS
-
-This page describes how to run coreboot on the ASUS P2B-LS mainboard.
-
-## Variants
-
-- P2B-LS
-- P2B-L (Same circuit board with SCSI components omitted)
-- P2B-S (Same circuit board with ethernet components omitted)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | no                        |
-+---------------------+---------------------------+
-| Dual BIOS feature   | no                        |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-[flashrom] works out of the box since 0.9.2.
-Because of deficiency in vendor firmware, user needs to override the laptop
-warning as prompted. Once coreboot is in place there will be no further issue.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- Ethernet (-LS, -L; Intel 82558)
-- SCSI (-LS, -S; Adaptec AIC7890)
-- USB
-- ISA add-on cards
-- PCI add-on cards
-- AGP graphics card
-- Floppy
-- Serial ports 1 and 2
-- Reboot
-- Soft off
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted.
-  With SeaBIOS as payload, setting keyboard initialization timeout to
-  500ms may fix the issue.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-- Termination is enabled for all SCSI ports (if equipped). Support to
-  disable termination is pending. Note that the SCSI-68 port is
-  always terminated, even with vendor firmware.
-
-## Untested
-
-- Parallel port
-- EDO memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- S3 suspend to RAM
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p3b-f.md

@@ -1,106 +0,0 @@
-# ASUS P3B-F
-
-This page describes how to run coreboot on the ASUS P3B-F mainboard.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | See below                 |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6.
-If you are using older versions of flashrom, below has to be done (with ACPI disabled!)
-before flashrom can detect the flash chip:
-
-```bash
-  #  rmmod w83781d
-  #  modprobe i2c-dev
-  #  i2cset 0 0x48 0x80 0x80
-```
-
-Upon power up, flash chip is inaccessible until flashrom has been run once.
-Since flashrom does not support reversing board enabling steps,
-once it detects the flash chip, there will be no write protection until
-the next power cycle.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- USB
-- PCI add-on cards
-- AGP graphics cards
-- Serial ports 1 and 2
-- Reboot
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS
-  as payload, setting keyboard initialization timeout to 2500ms may help.
-
-- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not
-  yet ready by the time SeaBIOS attempts to boot from them.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-## Untested
-
-- Floppy
-- Parallel port
-- EDO memory
-- ECC memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098))
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/i440bx/index`      |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p8z77-m.md

@@ -1,137 +0,0 @@
-# ASUS P8Z77-M
-
-This page describes how to run coreboot on the [ASUS P8Z77-M].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+----------------+
-| Type                | Value          |
-+=====================+================+
-| Model               | W25Q64FVA1Q    |
-+---------------------+----------------+
-| Size                | 8 MiB          |
-+---------------------+----------------+
-| Package             | DIP-8          |
-+---------------------+----------------+
-| Socketed            | yes            |
-+---------------------+----------------+
-| Write protection    | yes            |
-+---------------------+----------------+
-| Dual BIOS feature   | no             |
-+---------------------+----------------+
-| Internal flashing   | yes            |
-+---------------------+----------------+
-```
-
-The flash chip is located between the blue SATA ports.
-
-The main SPI flash cannot be written internally because Asus disables BIOSWE and
-enables ``BLE/SMM_BWP`` flags in ``BIOS_CNTL`` for their latest bioses.
-To install coreboot for the first time, the flash chip must be removed and
-flashed with an external programmer; flashing in-circuit doesn't work.
-The flash chip is socketed, so it's easy to remove and reflash.
-
-## Working
-
-- All USB2 ports (mouse, keyboard and thumb drive)
-- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
-- Gigabit Ethernet (RTL8111F)
-- SATA3, SATA2 (all ports, hot-swap not tested)
-       (Blue SATA2)  (Blue SATA2)  (White SATA3)
-        port 5        port 3        port 1
-        port 6        port 4        port 2
-
-- CPU Temp sensors and hardware monitor (some values don't make sense)
-- Native and MRC memory initialization
-  (please see [Native raminit compatibility] and [MRC memory compatibility])
-
-- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
-  (VGA/DVI-D/HDMI tested and working)
-- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3
-  (Arch based))
-- Serial port
-- PCI slot
-  Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested)
-  Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from
-  SeaBIOS)
-- S3 suspend from Linux
-- 2-channel analog audio (WAV playback by mplayer via back panel line out port)
-- Windows 10 with libgfxinit high resolution framebuffer and VBT
-
-## Known issues
-
-- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could
-  be reconfigured by the blob.
-
-- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config.
-  Otherwise integrated graphics would fail with a black screen.
-
-- PCI POST card is not functional because the PCI bridge early init is not yet done.
-
-- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for
-  an x8, and is electrically an x4 only.
-
-## Untested
-
-- Wake-on-LAN
-- USB3 on header
-- TPM header
-- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
-- HDMI and S/PDIF audio out
-
-## Not working
-
-- PS/2 keyboard or mouse
-- 4 and 6 channel analog audio out: Rear left and right audio is a muted
-  copy of front left and right audio, and the other two channels are silent.
-
-## Native (and MRC) raminit compatibility
-
-- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
-
-- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable
-  with obvious pattern of bit errors during memtest86+ runs.
-
-- Samsung PC3-10600U 2x2GB kit works at full rated speed.
-
-- Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
-
-## Extra onboard buttons
-
-The board has two onboard buttons, and each has a related LED nearby.
-What controls the LEDs and what the buttons control are unknown,
-therefore they currently do nothing under coreboot.
-
-- BIOS_FLBK
-  OEM firmware uses this button to facilitate a simple update mechanism
-  via a USB drive plugged into the bottom USB port of the USB/LAN stack.
-
-- MemOK!
-  OEM firmware uses this button for memory tuning related to overclocking.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6779D                                 |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-- [Flash chip datasheet][W25Q64FVA1Q]
-
-[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/
-[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/2170p.md

@@ -1,91 +0,0 @@
-# HP EliteBook 2170p
-
-This page is about the notebook [HP EliteBook 2170p].
-
-## Release status
-
-HP EliteBook 2170p was released in 2012 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-1. EC firmware
-2. Intel ME firmware
-
-EC firmware can be retrieved from the HP firmware update image, or the firmware
-backup of the laptop. EC Firmware is part of the coreboot build process.
-The guide on extracting EC firmware and using it to build coreboot is in
-document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops).
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-## Programming
-
-The flash chip is located between the memory slots, WWAN card and CPU,
-covered by the base enclosure, which needs to be removed according to
-the [Maintenance and Service Guide] to access the flash chip. Unlike
-other variants, the flash chip on 2170p is socketed, so it can be taken
-off and operated with an external programmer.
-
-Pin 1 of the flash chip is at the side near the CPU.
-
-![Flash Chip in 2170p](2170p_flash.jpg)
-
-For more details have a look at the general [flashing tutorial].
-
-## Debugging
-
-The board can be debugged with serial port on the dock or EHCI debug.
-The EHCI debug port is the left USB3 port.
-
-## Test status
-
-### Known issues
-
-- GRUB payload freezes if at_keyboard module is in the GRUB image
-  ([bug #141])
-
-### Untested
-
-- Fingerprint Reader
-- Dock: Parallel port, PS/2 mouse, S-Video port
-
-### Working
-
-- Integrated graphics init with libgfxinit
-- SATA
-- Audio: speaker and microphone
-- Ethernet
-- WLAN
-- WWAN
-- Bluetooth
-- SD Card Reader
-- SmartCard Reader
-- USB
-- DisplayPort
-- Keyboard, touchpad and trackpoint
-- EC ACPI support and thermal control
-- Dock: all USB ports, DVI-D, Serial debug, PS/2 keyboard
-- TPM
-- Internal flashing when IFD is unlocked
-- Using `me_cleaner`
-
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Panther Point QM77                         |
-+------------------+--------------------------------------------------+
-| EC               | SMSC KBC1126                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[HP EliteBook 2170p]: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03387961.pdf
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -14,99 +14,30 @@ The following things are still missing from this coreboot port:
 ## Flashing coreboot
 
 ```eval_rst
-+---------------------+-------------------------+
-| Type                | Value                   |
-+=====================+=========================+
-| Socketed flash      | no                      |
-+---------------------+-------------------------+
-| Model               | MX25L6406E/MX25L6408E   |
-+---------------------+-------------------------+
-| Size                | 8 MiB                   |
-+---------------------+-------------------------+
-| In circuit flashing | yes                     |
-+---------------------+-------------------------+
-| Package             | SOIC-8                  |
-+---------------------+-------------------------+
-| Write protection    | bios region             |
-+---------------------+-------------------------+
-| Dual BIOS feature   | No                      |
-+---------------------+-------------------------+
-| Internal flashing   | yes                     |
-+---------------------+-------------------------+
-```
-
-### Flash layout
-The original layout of the flash should look like this:
-```
-00000000:00000fff fd
-00510000:007fffff bios
-00003000:0050ffff me
-00001000:00002fff gbe
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L6406E |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
 ```
 
 ### Internal programming
 
 The SPI flash can be accessed using [flashrom].
-```console
-$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
-```
-
-After shorting the FDO jumper you gain access to the full flash, but you
-still cannot write in the bios region due to SPI protected ranges.
-
-**Position of FDO jumper close to the IO and second fan connector**
-![][compaq_8200_jumper]
-
-[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg
-
-To write to the bios region you can use an [IFD Hack] originally developed
-for MacBooks, but with modified values described in this guide.
-You should read both guides before attempting the procedure.
-
-Since you can still write in the flash descriptor, you can shrink
-the ME and then move the bios region into where the ME originally was.
-coreboot does not by default restrict writing to any part of the flash, so
-you will first flash a small coreboot build and after it boots, flash
-the full one.
-
-The temporary flash layout with the neutered ME firmware should look like this:
-```
-00000000:00000fff fd
-00023000:001fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-00200000:007fffff pd
-```
-
-It is very important to use these exact numbers or you will need to fix it
-using external flashing, but you should already be familiar with the risks
-if you got this far.
-
-The temporary ROM chip size to set in menuconfig is 2 MB but the default
-CBFS size is too large for that, you can use up to about 0x1D0000.
-
-When building both the temporary and the permanent installation, don't forget
-to also add the gigabit ethernet configuration when adding the flash descriptor
-and ME firmware.
-
-You can pad the ROM to the required 8MB with zeros using:
-```console
-$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
-$ cat coreboot.rom 6M.bin > coreboot8.rom
-```
-
-If you want to continue using the neutered ME firmware use this flash layout
-for stage 2:
-```
-00000000:00000fff fd
-00023000:007fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-```
-
-If you want to use the original ME firmware use the original flash layout.
-
-More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md).
 
 ### External programming
 
@@ -143,7 +74,7 @@ as otherwise there's not enough space near the flash.
 | Coprocessor      | Intel ME                                         |
 +------------------+--------------------------------------------------+
 ```
-[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
+
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -23,14 +23,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
-- [P2B-LS](asus/p2b-ls.md)
-- [P3B-F](asus/p3b-f.md)
 - [P5Q](asus/p5q.md)
 - [P8C WS](asus/p8c_ws.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8H77-V](asus/p8h77-v.md)
-- [P8Z77-M](asus/p8z77-m.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
 - [wifigo_v1](asus/wifigo_v1.md)
@@ -81,7 +78,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [HP Sure Start](hp/hp_sure_start.md)
-- [EliteBook 2170p](hp/2170p.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)
@@ -89,7 +85,6 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
-- [DQ67SW](intel/dq67sw.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -173,8 +168,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [FW2B / FW4B](protectli/fw2b_fw4b.md)
 - [FW6A / FW6B / FW6C](protectli/fw6.md)
-- [VP2420](protectli/vp2420.md)
-- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
 
 ## Roda
 
@@ -214,6 +207,7 @@ The boards in this section are not real mainboards, but emulators.
 - [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Lemur Pro 11](system76/lemp11.md)

Documentation/mainboard/intel/dq67sw.md

@@ -1,170 +0,0 @@
-# Intel DQ67SW
-
-The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel Q67 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1333                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton/Winbond W83677HG-i                       |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82579LM Gigabit Ethernet                   |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header                                  |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- Integrated GPU with libgfxinit
-- PCIe graphics in the PEG slot
-- Additional PCIe slots
-- PCI slot
-- All rear (4x) and internal (8x) USB2 ports
-- Rear USB3 ports (2x)
-- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
-- Two rear eSATA connectors (3 Gb/s)
-- SATA at 6 Gb/s
-- Gigabit Ethernet
-- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
-- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
-- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
-    - slackware64 (Linux 5.15)
-    - Windows 10 (22H2)
-- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
-- Poweroff
-- Resume from S3
-- Console output on the serial port
-
-### Not working
-
-- Automatic fan control. One can still use OS-based fan control programs,
-  such as fancontrol on Linux or SpeedFan on Windows.
-- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
-  works, but once Windows Update installs drivers, it crashes and enters a
-  bootloop.
-
-### Untested
-
-- Firewire (LSI L-FW3227-100)
-- EHCI debug
-- S/PDIF audio
-- Audio jacks other than the green one
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | yes        |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | see below  |
-+---------------------+------------+
-| In circuit flashing | see below  |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-
-    00000000:00000fff fd
-    00580000:007fffff bios
-    00003000:0057ffff me
-    00001000:00002fff gbe
-
-Unfortunately the SPI interface to the chip is locked down by the vendor
-firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
-the PCI configuration space of the LPC Interface Bridge, is set.
-
-It is possible to program the chip is to attach an external programmer
-with an SOIC-8 clip.
-
-```eval_rst
-Another way is to boot the vendor firmware in UEFI mode and exploit the
-unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
-
-On this specific board it is possible to prevent the BLE bit from being set
-when it resumes from S3. One entry in the S3 Boot Script must be modified,
-e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
-that supports this specific type of S3 Boot Script, for example from strobo5:
-
-    $ git clone -b headerless https://github.com/strobo5/chipsec.git
-    $ cd chipsec
-    $ python setup.py build_ext -i
-    $ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
-
-The boot script contains an entry that writes 0x02 to memory at address
-0xe00f80dc. This address points at the PCIe configuration register at offset
-0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
-Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
-prevents this by making it write a 0 instead.
-
-```eval_rst
-After suspending and resuming the board, the BIOS region can be flashed with
-a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
-so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-## Hardware monitoring and fan control
-
-Currently there is no automatic, OS-independent fan control.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## References
-
-[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
-May 2011,
-Document number 324645-006
-
-[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
-December 2008,
-Document number 321090
-

Documentation/mainboard/protectli/vp2420.md

@@ -1,87 +0,0 @@
-# Protectli Vault VP2420
-
-This page describes how to run coreboot on the [Protectli VP2420].
-
-![](VP2420_back.jpg)
-![](VP2420_front.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. Firmware can be easily
-flashed with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is soldered in
-under RAM, easily accessed after taking out the memory. Specifically, it's a
-KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](VP2420_internal.jpg)
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 4 Ethernet ports
-- HDMI, DisplayPort
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector
-- SMBus (reading SPD from DIMMs)
-- Initialization with Elkhart Lake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Celeron J6412                              |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Elkhart Lake                               |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8613E                                      |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
-- [VP2420 Product Page](https://protectli.com/product/vp2420/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-- [flashrom](https://flashrom.org/Flashrom)

Documentation/mainboard/protectli/vp46xx.md

@@ -1,135 +0,0 @@
-# Protectli Vault VP46xx series
-
-This page describes how to run coreboot on the [Protectli VP46xx].
-
-![](vp46xx_front.jpg)
-![](vp46xx_back.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule. VP4630 and VP4650 use CometLake2 FSP and VP4670
-use CometLake1 FSP (see [variants](#variants) section), so be sure to select
-the correct board in the coreboot's menuconfig, otherwise the platform will not
-succeed on memory initialization.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. The first version
-supporting the chipset is flashrom v1.2. Firmware an be easily flashed
-with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB socketed SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is near the M.2
-WiFi slot connector. Remove the chip from socket and use a clip to program the
-chip. Specifically, it's a KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](vp46xx_flash.jpg)
-
-## Known issues
-
-- After flashing with external programmer it is always required to reset RTC
-  with a jumper or disconnect the coin cell temporarily. Only then the platform
-  will boot after flashing.
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 6 Ethernet ports
-- HDMI, DisplayPort and USB-C Display Port with libgfxinit and FSP GOP
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector (Fintek F81232 USB to
-  UART adapter present on board)
-- SMBus (reading SPD from DIMMs)
-- Initialization with CometLake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- LPC TPM module (using Protectli custom-designed module with Infineon SLB9660)
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Variants
-
-There are 3 variants of VP46xx boards: VP4630, VP4650 and VP4670. They differ
-only in used SoC and some units may come with different Super I/O chips, either
-ITE IT8786E or IT8784E, but the configuration is the same on this platform.
-
-- VP4630:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i3-10110U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4650:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i5-10210U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4670:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-10810U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
-- [VP4630 Product Page](https://protectli.com/product/vp4630/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-
-[Protectli VP46xx]: https://protectli.com/vault-6-port/
-[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/system76/gaze17.md

@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B256E           |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/releases/boards_supported_on_branches.md

@@ -12,9 +12,9 @@ desired.
 
 Currently, [jenkins](https://qa.coreboot.org), our continuous
 integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, 4.18, and 4.19 branches.  Builders for other branches can be
-added upon request.  Likewise, some releases are only marked with tags,
-and branches would need to be created to push new code.  These branches
+4.16, and 4.18 branches.  Builders for other branches can be created on
+request.  Likewise, some releases are only marked with tags, and
+branches would need to be created to push new code to.  These branches
 can also be created on request.
 
 Patches can be backported from the master branch to any of these other
@@ -23,17 +23,6 @@ critical security fixes, but other patches will need to handled by
 anyone using that release.
 
 
-## [4.19 Release](coreboot-4.19-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| intel/icelake_rvp             | INTEL_ICELAKE          | 2018-10-26 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
 ## [4.18 Release](coreboot-4.18-relnotes.md)
 Branch created, builder configured
 
@@ -42,53 +31,29 @@ Branch created, builder configured
 | Vendor/Board                  | Processor              | Date added | Brd type  |
 +===============================+========================+============+===========+
 | amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
 +-------------------------------+------------------------+------------+-----------+
 ```

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,7 +1,7 @@
-coreboot 4.19 release
+Upcoming release - coreboot 4.19
 ========================================================================
 
-The 4.19 release was completed on the 16th of January 2023.
+The 4.19 release is planned for the 16th of January 2023.
 
 Since the last release, the coreboot project has merged over 1600
 commits from over 150 authors. Of those authors, around 25 were
@@ -217,30 +217,17 @@ Significant Known and Open Issues
 ---------------------------------
 
 Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
+
 | #   | Subject                                                         |
-+=====+=================================================================+
+|-----|-----------------------------------------------------------------|
 | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
 | 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
 | 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
 | 445 | Thinkpad X200 wifi issue                                        |
-+-----+-----------------------------------------------------------------+
 | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
 | 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
 | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
 | 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
 | 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
 | 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```

Documentation/releases/coreboot-4.20-relnotes.md

@@ -1,176 +1,41 @@
 Upcoming release - coreboot 4.20
 ========================================================================
 
-The 4.20 release is being done on May 15, 2023.
+The 4.20 release is planned for the 20th of April 2023.
 
-The coreboot community has done a tremendous amount of work on the
-codebase over the last three and a half month. We've had over 1600
-commits in that time period, doing ongoing cleanup and improvement.
 
-It can be hard to remember at times how much the codebase really has
-improved, but looking back at coreboot code from previous years, it's
-really impressive the changes that have happened. We'd like to thank
-everyone who has been involved in these changes. It's great to work
-with everyone involved, from the people who make the small cleanup
-patches and review all of the incoming changes to the people working
-on new chipsets and SoCs. We'd additionally like to thank all of those
-individuals who make the effort to become involved and report issues
-or push even a single patch to fix a bug that they've noticed.
+The 4.21 release is planned for around the 17th of July, 2023
 
-Many thanks to everyone involved!
 
-We plan to get the 4.21 release done in mid August, 2023,
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+* This document may also be edited at the google doc copy:
+  https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
 
 Significant or interesting changes
 ----------------------------------
 
-### cpu/mp_init.c: Only enable CPUs once they execute code
-
-On some systems the BSP cannot know how many CPUs are present in the
-system. A typical use case is a multi socket system. Setting the enable
-flag only on CPUs that actually exist makes it more flexible.
-
-### cpu/x86/smm: Add PCI resource store functionality
-
-In certain cases data within protected memmory areas like SMRAM could
-be leaked or modified if an attacker remaps PCI BARs to point within
-that area. Add support to the existing SMM runtime to allow storing
-PCI resources in SMRAM and then later retrieving them.
-
-This helps prevent moving BARs around to get SMM to access memory in
-areas that shouldn't be accessed.
-
-### acpi: Add SRAT x2APIC table support
-
-For platforms using X2APIC mode add SRAT x2APIC table
-generation. This allows to setup proper SRAT tables.
-
-### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
-
-This patch supports projects to use _DSM to control USB3 U1/U2
-transition per port.
-
-More details can be found in
-https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
-
-The ACPI and USB driver of linux kernel need corresponding functions
-to support this feature. Please see
-https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
-
-### drivers/efi: Add EFI variable store option support
-
-Add a driver to read and write EFI variables stored in a region device.
-This is particularly useful for EDK2 as payload and allows to reuse
-existing EFI tools to set/get options used by the firmware.
-
-The write implementation is fault tolerant and doesn't corrupt the
-variable store. A faulting write might result in using the old value
-even though a 'newer' had been completely written.
-
-Implemented basic unit tests for header corruption, writing existing
-data and append new data into the store.
-
-Initial firmware region state:
-Initially the variable store region isn't formatted. Usually this is
-done in the EDK2 payload when no valid firmware volume could be found.
-It might be useful to do this offline or in coreboot to have a working
-option store on the first boot or when it was corrupted.
-
-Performance improvements:
-Right now the code always checks if the firmware volume header is valid.
-This could be optimised by caching the test result in heap. For write
-operations it would be good to cache the end of the variable store in
-the heap as well, instead of walking the whole store. For read
-operations caching the entire store could be considered.
-
-Reclaiming memory:
-The EFI variable store is append write only. To update an existing
-variable, first a new is written to the end of the store and then the
-previous is marked invalid. This only works on PNOR flash that allow to
-clear set bits, but keep cleared bits state.
-This mechanisms allows a fault tolerant write, but it also requires to
-"clean" the variable store for time to time. This cleaning would remove
-variables that have been marked "deleted".
-Such cleaning mechanism in turn must be fault tolerant and thus must use
-a second partition in the SPI flash as backup/working region.
-For now to cleaning is done in coreboot.
-
-Fault checking:
-The driver should check if a previous write was successful and if not
-mark variables as deleted on the next operation.
+### Add changes that need a full description here
 
 
-### drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
-
-Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
-and prints EWL type 3 primarily associated with MRC training failures.
-
-### Toolchain updates
-
-* Upgrade MPC from version 1.2.1 to 1.3.1
-* Upgrade MPFR from version 4.1.1 to 4.2.0
-* Upgrade CMake from version 3.25.0 to 3.26.3
-* Upgrade LLVM from version 15.0.6 to 15.0.7
-* Upgrade GCC from version 11.2.0 to 11.3.0
-* Upgrade binutils from version 2.37 to 2.40
 
 Additional coreboot changes
 ---------------------------
 
-* Remove Yabits payload. Yabits is deprecated and archived.
-* Add DDR2 support to Intel GM45 code.
-* Fix superiotool compilation issues when using musl-libc.
-* Drop the Python 2 package from the coreboot-sdk.
-* Drop the Zephyr SDK from coreboot-sdk since the packaged version
-  was quite old and wasn’t really used.
-* Add inteltool support for the Intel "Emmitsburg" PCH.
-* Work to improve cache hit percentage when rebuilding using ccache.
-* Adding Sound-Open-Firmware drivers to chromebooks to enable audio on
-  non-chrome operating systems.
-* Improve and expand ACPI generation code.
-* Fix some issues for the RISC-V code.
-* Continue upstreaming the POWER9 architecture.
-* Add documentation for SBOM (Software Bill of Materials).
-* Add SimNow console logging support for AMD.
-* Do initial work on Xeon SPR
-* CMOS defaults greater than 128 bytes long now extend to bank 1.
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
 
-New Mainboards
---------------
-* Asrock: B75M-ITX
-* Dell: Latitude E6400
-* Google: Aurash
-* Google: Boxy
-* Google: Constitution
-* Google: Gothrax
-* Google: Hades
-* Google: Myst
-* Google: Screebo
-* Google: Starmie
-* Google: Taranza
-* Google: Uldren
-* Google: Yavilla
-* HP: EliteBook 2170p
-* Intel: Archer City CRB
-* Intel: DQ67SW
-* Protectli: VP2420
-* Protectli: VP4630/VP4650
-* Protectli: VP4670
-* Siemens: MC EHL4
-* Siemens: MC EHL5
-* System76: lemp11
-* System76: oryp10
-* System76: oryp9
 
-Removed Mainboards
-------------------
-* Intel Icelake U DDR4/LPDDR4 RVP
-* Intel Icelake Y LPDDR4 RVP
-* Scaleway TAGADA
 
-Updated SoCs
-------------
-* Removed soc/intel/icelake
 
 Plans to move platform support to a branch
 ------------------------------------------
@@ -181,46 +46,22 @@ The SoC Intel Quark is unmaintained and different efforts to revive it
 have so far failed.  The only user of this SoC ever was the Galileo
 board.
 
-Thus, to reduce the maintenance overhead for the community, support for
+Thus, to reduce the maintanence overhead for the community, support for
 the following components will be removed from the master branch and will
 be maintained on the release 4.20 branch.
 
   * Intel Quark SoC
   * Intel Galileo mainboard
 
+
 Statistics from the 4.19 to the 4.20 release
 --------------------------------------------
 
-Total Commits: ~1625
-Average Commits per day: ~13.71
-Total lines added: ~101911
-Average lines added per commit: ~62.71
-Number of patches adding more than 100 lines: ~126
-Average lines added per small commit: ~37.98
-Total lines removed: ~34756
-Average lines removed per commit: ~21.39
-Total difference between added and removed: ~67155
-Total authors: ~170
-New authors: ~35
+* To be filled in immediately before the release by the release team
+
 
 Significant Known and Open Issues
 ---------------------------------
 
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
+* To be filled in immediately before the release by the release team
 
-| #   | Subject                                                         |
-|-----|-----------------------------------------------------------------|
-| 478 | X200 booting Linux takes a long time with TSC                   |
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-| 446 | Optiplex 9010 No Post                                           |
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-| 427 | x200: Two battery charging issues                               |
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-| 412 | x230 reboots on suspend                                         |
-| 393 | T500 restarts rather than waking up from suspend                |
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |

Documentation/releases/coreboot-4.21-relnotes.md

@@ -1,51 +0,0 @@
-Upcoming release - coreboot 4.21
-========================================================================
-
-The 4.21 release is planned for mid-August, 2023
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-Significant or interesting changes
-----------------------------------
-
-### Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-Platform Updates
-----------------
-
-* To be filled in immediately before the release by the release team
-
-Plans to move platform support to a branch
-------------------------------------------
-
-* Seciton to be filled in or removed after discussion
-
-Statistics from the 4.20 to the 4.21 release
---------------------------------------------
-
-* To be filled in immediately before the release by the release team
-
-
-Significant Known and Open Issues
----------------------------------
-
-* To be filled in immediately before the release by the release team
-

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.21 - August 2023](coreboot-4.21-relnotes.md)
+* [4.20 - April 2023](coreboot-4.20-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,7 +15,6 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.20 - May 2023](coreboot-4.20-relnotes.md)
 * [4.19 - January 2023](coreboot-4.19-relnotes.md)
 * [4.18 - October 2022](coreboot-4.18-relnotes.md)
 * [4.17 - May 2022](coreboot-4.17-relnotes.md)

Documentation/sbom/sbom.md

@@ -1,156 +0,0 @@
-# Software Bill of Materials (SBOM)
-
-SBOM is a collection of information of each software component
-you are supplying/building. Similar to a package manager on Linux
-based systems, it holds information of as many software parts as
-possible. This information can be a version, name of the software, URL,
-license information and more. A SBOM can be saved in various formats.
-In coreboot it's saved as "uSWID" file. uSWID is not a standard or
-specification but it doesn't need to be, since it's basically just an
-array/list of CoSWID (Concise Software Identification) files which in
-turn are specified by a RFC specification. CoSWID files are saved in a
-CBOR format. CBOR is like JSON if JSON were a binary format. Similar
-to a package manager the CoSWID format can link multiple softwares
-together. For example on most modern Intel systems FSP is included as
-a dependency of coreboot. That kind of relationship between software
-components (among others) can be expressed in an uSWID file. That makes
-firmware/software much more transparent. One could for example create a
-software that takes a coreboot firmware image as input and
-automatically creates a graph with all software components the coreboot
-image contains and their relationship to each other.
-
-
-## SWID/CoSWID
-
-SWID is a standard hidden behind an ISO paywall.
-It generally identifies/describes Software components. Since SWID files
-are written in XML, they can get too large for devices with network and
-storage constraints. CoSWID is basically SWID but in CBOR binary
-format, which makes it far smaller compared to its big brother. Also,
-CoSWID is a RFC specification (so publicly accessible). Therefore
-CoSWID is the standard used in coreboot SBOM. But one CoSWID file/tag
-can only describe one single software, but since software is usually
-composed of multiple parts (especially in firmware with many binary
-blobs) uSWID was born as a container format to hold multiple CoSWID
-files. It also has a magic value, that makes software capable of
-extracting uSWID/CoSWID data without the need to understand the
-underlying format of the binary (in coreboot it's the CBFS and in EDK2
-it's the COFF). To get a simple overview of how a SWID/CoSWID file
-looks like, just take a look at the various "templates" in src/sbom/.
-There are of course other SBOM specifications out there, but most of
-them are rather blown up and don't support a binary format at all.
-
-
-## coreboot implementation
-
-Quick overview of how things are generated:
-
-![Generation of an SBOM File in coreboot][sbom_generation]
-
-[sbom_generation]: sbom_generation.svg
-
-After all SBOM data has been fetched from all the software components,
-the 'goswid' tool links them all together into one sbom.uswid file.
-Therefore the goswid tool is basically a linker that takes multiple
-CoSWID/SWID files and converts them into one uSWID file. Although the
-image shows only Files in JSON format it is also possible to supply
-them in XML or CBOR format.
-
-The final SBOM file is located inside the CBFS.
-For each software component in coreboot SBOM, there is an option in
-Kconfig (usually called `CONFIG_INCLUDE_[software-name]_SBOM`) to either
-include or not include SBOM metadata for the specified software.
-Furthermore there is a `CONFIG_SBOM_[software-name]_PATH` option which
-contains a path to a SWID/CoSWID file in a format of choice
-(being either JSON, XML or CBOR). `CONFIG_SBOM_[software-name]_PATH`
-option usually defaults to a very generic CoSWID file in JSON format
-(which are stored in src/sbom/). That at least gives minimal
-information like the name of the software and maybe a version.
-But it is always preferred, that the `CONFIG_SBOM_[software-name]_PATH`
-is set to a custom CoSWID/SWID file that contains much more information
-(like version/commit-hash, license, URL, dependencies, ...).
-Therefore using the defaults is by any means to be avoided, since they
-hold very little information or even worse wrong information.
-Furthermore some of these Kconfig options have a suboption
-(usually called `CONFIG_SBOM_[software-name]_GENERATE`) to generate
-some basic SBOM data for the specified software component, in order to
-get at least some bit of information about it by analyzing the binary
-(for binary blobs) or querying information via git (for open source
-projects). This is for example currently done for all payloads. For
-each payload the commit hash used in the build is taken and put into
-the SBOM file. For open-source projects (like all payloads) crucial
-information like the current commit-hash of the payload can easily be
-put into the SBOM file. Extracting information out of binary blobs is a
-bit trickier for obvious reasons. For closed source binary blobs it is
-therefore recommended that vendors and software-engineers create a SBOM
-file as part of their build process and add a path to that SBOM file
-via Kconfig options in coreboot (`CONFIG_SBOM_[software-name]_PATH`).
-That way the final SBOM has much more useful and correct data.
-
-
-## Build coreboot with SBOM
-
-Directly under the 'General setup' Kconfig menu is a
-'Software Bill of Materials (SBOM)' submenu where all options are to
-enable/disable SBOM integration in to the corebeoot build.
-Therefore one can just enable/disable them via `make menuconfig`.
-
-
-## What to do as Developer of a binary blob (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format
-as part of your software build process
-
-2. Supply that generated File along with your binary blob (preferably
-not inside the blob)
-
-3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your
-defconfig pointing to your [software-name] generated File.
-
-
-## What to do as Developer of an open source project (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID file in either JSON, XML or CBOR format
-as part of your software's build process. For example in form of a
-Makefile target.
-
-2. Change src/sbom/Makefile.inc (in order to know where to find the
-CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
-builds said software. For example for GRUB2 that could mean to add a
-Makefile target in payloads/external/GRUB2/Makefile.
-
-
-## Problems
-
-What to do if the binary blob that is included in coreboot's build
-already has a SBOM file embedded in the binary? One could supply the
-path of the software binary itself (e.g. me.bin) as SBOM file path for
-the software in question. Which would basically mean to set
-`CONFIG_SBOM_[software-name]_PATH=/path/to/me.bin`. This is possible
-since the 'goswid' tooling is able to extract uSWID information out of
-an unknown binary format because of uSWIDs magic value. But even if
-coreboot can extract the uSWID data there is still the question of what
-to do next. One can do one of the following:
-
-  - Do not include the Software's SBOM data in the final SBOM of
-    coreboot. Data would not be duplicated, but therefore not included
-    in coreboot SBOM file.
-
-  - Extract the uSWID/CoSWID information from the binary and also
-    include it in the coreboot SBOM. That would mean, that SBOM data
-    is duplicated.
-
-The first solution should in general be preferred, since its no
-problem if SBOM data is located at multiple locations/binaries if they
-don't have a direct dependency on each other. It would be good if
-software that cannot run on its own only supplies the SBOM data along
-with it as kind of extra file instead of embedded in an unknown binary
-blob. coreboot can then just take it and include it in its own SBOM
-file. If on the other hand the binary can function on its own (e.g. EC
-or BMC binary), it is generally preferred that the software supplies
-its own SBOM data and coreboot just simply doesn't include it in its
-own SBOM file. That would make a more or less clear distinction and
-avoids duplication in case the BMC or EC is updated (without updating
-coreboot). The distinction is not always easy and this problem is
-currently not considered in the implementation, since none of the
-software components currently create a SBOM file on their own.

Documentation/sbom/sbom_generation.plantuml

@@ -1,61 +0,0 @@
-@startuml
-
-map "src/sbom/compiler-gcc.json" as gcc {
-    software-name => GCC
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/intel-me.json" as me {
-    software-name => Intel Mangement Engine
-    ... => ...
-}
-map "src/sbom/intel-microcode.json" as ucode {
-    software-name => Intel Microcode
-    ... => ...
-}
-map "src/sbom/generic-ec.json" as ec {
-    software-name => ecxyz
-    ... => ...
-}
-map "src/sbom/generic-fsp.json" as fsp {
-    software-name => Firmware Support Package
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/payload-[...].json" as payload {
-    software-name => ...
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/coreboot.json" as coreboot {
-    software-name => coreboot
-    version => x.y.z
-    url => coreboot.rocks
-    ... => ...
-}
-object "sbom.uswid" as uswid {
-    merged SBOM data in binary format
-}
-object goswid {
-    # ./goswid
-        --compiler gcc.json
-        --parent coreboot.json
-        --requires fsp.json,payload.json
-        intel-me.json
-        intel-ec.json
-        intel-ucode.json
-        --output sbom.uswid
-}
-
-left to right direction
-gcc --> goswid
-me --> goswid
-ucode --> goswid
-goswid <-- ec
-goswid <-- fsp
-goswid <-- payload
-
-coreboot -up> goswid
-goswid -up> uswid
-
-@enduml

Documentation/security/vboot/list_vboot.md

@@ -73,11 +73,6 @@
 - Gladios
 - Marasov
 - Omnigul
-- Constitution
-- Aurash
-- Hades
-- Uldren
-- Yavilla
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -88,7 +83,6 @@
 - Krabby
 - Tentacruel
 - Magikarp
-- Starmie
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -176,7 +170,6 @@
 - Pico
 - Link (Google Chromebook Pixel (2013))
 - Mistral
-- Myst
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
 - Nyan Blaze (HP Chromebook 14 G3)
@@ -210,7 +203,6 @@
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
 - Rex 0
-- Screebo
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Skyrim
@@ -245,25 +237,25 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Chronicler
-- Collis
-- Copano (ASUS Chromebook Flip CX5400)
 - Delbin (ASUS Chromebook Flip CX5)
-- Drobit (ASUS Chromebook CX9400)
 - Eldrid
-- Elemi (HP Pro c640 G2 Chromebook)
 - Halvor
 - Lindar
 - Malefor
 - Terrador
 - Todor
 - Trondo
-- Voema
-- Volet
 - Volteer
 - Volteer2
 - Volteer2_Ti50
 - Voxel (Acer Chromebook Spin 713 (CP713-3W))
+- Elemi (HP Pro c640 G2 Chromebook)
+- Voema
+- Drobit (ASUS Chromebook CX9400)
+- Copano (ASUS Chromebook Flip CX5400)
+- Collis
+- Volet
+- Chronicler
 - Dalboz
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
 - Ezkinil (Acer Chromebook Spin 514)
@@ -295,6 +287,7 @@
 - Coffeelake S U-DIMM DDR4 RVP8
 - Cometlake U DDR4 RVP
 - Elkhartlake LPDDR4x CRB
+- Emerald Lake 2 CRB
 - Galileo
 - Glkrvp
 - Jasperlake DDR4/LPDDR4 RVP
@@ -306,7 +299,6 @@
 - Kunimitsu
 - Meteorlake-P RVP
 - Meteorlake-P RVP with Chrome EC
-- Meteorlake-P RVP with Microchip EC
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -351,11 +343,6 @@
 ## OpenCellular
 - Elgon (GBCv2)
 
-## Protectli
-- VP4630/VP4650
-- VP4670
-- VP2420
-
 ## SAMSUNG
 - Lumpy
 - Stumpy

Documentation/security/vboot/measured_boot.md

@@ -1,52 +1,16 @@
 # Measured Boot
-Measured boot feature was initially implemented as an extension of Google
-Verified Boot. However, the two features were decoupled since then and use of
-measured boot no longer requires enabling vboot.
-
-In most cases TPM eventlog is initialized during bootblock before TPM gets set
-up, hence digests are not measured into TPM immediately, but are only cached in
-the event log. Later, as part of TPM setup, the cached events are applied onto
-TPM device. The behaviour is different if TPM_MEASURED_BOOT_INIT_BOOTBLOCK
-kconfig is set, which moves TPM initialization into bootblock.
-
-## SRTM
-A measured-based trust chain is one that begins with an initial entity that
-takes the first measurement, referred to as the "Core Root of Trust for
-Measurement" (CRTM), before control is granted to the measured entity. This
-process of measurement and then passing control is referred to as a transitive
-trust. When the CRTM can only ever be executed once during the power life-cycle
-of the system, it is referred to as a "Static CRTM" (S-CRTM). Thus the trust
-chain constructed from the S-CRTM is referred to as the Static Root of Trust for
-Measurement (SRTM) trust chain. The theory is that as long as a proper
-transitive trust is conducted as more code is allowed to execute, a trustworthy
-record showing the provenance of the executing system may be provided to
-establish the trustworthiness of the system.
+coreboot measured boot is implemented as Google Verified Boot extension. This
+means in order to use it, vboot needs to be available for your platform. The
+goal of this implementation is to implement an easy to understand and
+transparent measured boot mechanism.
 
 ## IBB/CRTM
-The "Initial Boot Block" (IBB) is a one-time executed code block loaded at the
-reset vector. Under measured boot mode, the IBB measures itself before measuring
-the next code block making it an S-CRTM for the measured boot trust chain, an
-SRTM trust chain. Since the IBB measures itself and executes out of DRAM, it is
-said to have a "Root of Trust" (RoT) that is rooted in software.
-
-## S-CRTM Hardening
-To address attacks that took advantage of the IBB being self-referential with
-both the "Root of Trust for Verification" (RTV) and "Root of Trust for
-Measurement" (RTM) being rooted in software, hardening was implemented by CPU
-manufactures. This was accomplished by introducing RoT, typically an RTV, to an
-external entity provided by the manufacture that could be validated by the CPU
-at boot. Examples of this are Intel's BootGuard and AMD's Hardware Validated
-Boot (also known as Platform Secure Boot). These solutions work by having the
-IBB invoke the manufacture provided RoT as early as possible, for which the CPU
-has already validated or validates when invoked. The RoT will then validate the
-IBB, thus moving the root for the respective trust chain, typically the
-verification trust chain, into hardware.
-
-It should be noted that when Intel BootGuard was originally designed, it
-provided a measurement mode that resulted in the ACM (Authenticated Code
-Module) becoming the S-CRTM for the SRTM trust chain. Unfortunately, this was
-never deployed and thus relying on "Root of Trust for Verification" (RTV)
-signature check as the only assertion rooted in hardware.
+The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first
+code block loaded at reset vector and measured by a DRTM solution.
+In case SRTM mode is active, the IBB measures itself before measuring the next
+code block. In coreboot, cbfs files which are part of the IBB are identified
+by a metadata tag. This makes it possible to have platform specific IBB
+measurements without hardcoding them.
 
 ## Known Limitations
 At the moment measuring IBB dynamically and FMAP partitions are not possible but
@@ -55,59 +19,43 @@ will be added later to the implementation.
 Also SoCs making use of VBOOT_RETURN_FROM_VERSTAGE are not able to use the
 measured boot extension because of platform constraints.
 
+## SRTM Mode
+The "Static Root of Trust for Measurement" is the easiest way doing measurements
+by measuring code before it is loaded.
+
 ### Measurements
-To construct the coreboot SRTM trust chain, the CBFS files which are part of the
-IBB, are identified by a metadata tag. This makes it possible to have platform
-specific IBB measurements without hard-coding them.
+SRTM mode measurements are done starting with the IBB as root of trust.
+Only CBFS contents are measured at the moment.
 
 #### CBFS files (stages, blobs)
 * CBFS data is measured as raw data before decompression happens.
 * CBFS header is excluded from measurements.
-* Measurements are stored in PCR 2 (by default, use PCR_SRTM kconfig option to
-  change).
+* Measurements are stored in PCR 2.
 
 #### Runtime Data
 * CBFS data which changes by external input dynamically. Never stays the same.
 * It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
-  measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
-  in order to avoid PCR pre-calculation issues.
+  measured into a different PCR 3 in order to avoid PCR pre-calculation issues.
 
 ![][srtm]
 
 [srtm]: srtm.png
 
-### TPM eventlog
-There are three supported formats of event logs:
-* coreboot-specific format.
-* [TPM1.2 Specification][TPM12] (chapter 11).
-* [TPM2.0 Specification][TPM20] (chapter 10).
+### TCPA eventlog
+coreboot makes use of its own TCPA log implementation. Normally the eventlog
+specification can be found via the TCG homepage:
 
-#### coreboot-specific format
-```c
-struct tcpa_entry {
-	uint32_t pcr;           /* PCR number. */
-	char digest_type[10];   /* Hash algorithm name. */
-	uint8_t digest[64];     /* Digest (tail can be unused). */
-	uint32_t digest_length; /* Number of digest bytes used. */
-	char name[50];          /* Description of what was hashed. */
-} __packed;
+[UEFI Specification](https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/)
 
-struct tcpa_table {
-	uint16_t max_entries;
-	uint16_t num_entries;
-	struct tcpa_entry entries[0];
-} __packed;
-```
+[BIOS Specification](https://www.trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf)
 
-Single hash per PCR. No magic number or any other way of recognizing it.
-Endianness isn't specified.
+Both of them are not representing firmware measurements in a generalized way.
+Therefore we have to implement our own solution.
 
-In principle can hold any hash with 512 bits or less. In practice,
-SHA-1 (for TPM1) and SHA-256 (TPM2) are used.
+We decided to provide an easy to understand TCPA log which can be read out
+from the operating system and firmware itself.
 
-Can be parsed by `cbmem`.
-
-##### Console dump format
+#### Table Format
 The first column describes the PCR index used for measurement.
 The second column is the hash of the raw data. The third column contains
 the hash algorithm used in the operation. The last column provides
@@ -115,53 +63,6 @@ information about what is measured. First the namespace from where the data
 came from, CBFS or FMAP, then the name used to look up the data
 (region or file name).
 
-#### TPM 1.2 format
-Single hash per PCR (always SHA-1). First entry serves as a header, provides
-ID and version. Always little endian. Event data describes what is being hashed
-as a NUL-terminated string instead of providing the actual raw data.
-
-Can be parsed by at least `cbmem` and Linux (exports in both text and binary
-forms).
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x31544243 ("CBT1" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
-#### TPM 2.0 format
-One or more hashes per PCR, but implementation is limited to single hash (SHA-1,
-SHA-256, SHA-384 or SHA-512). First entry is overall compatible with TPM 1.2 and
-serves as a header with ID, version and number of hashing algorithms used.
-Always little endian. Event data describes what is being hashed as a
-NUL-terminated string instead of providing the actual raw data.
-
-By default SHA-1 is used for TPM1 and SHA-256 for TPM2. Other options are
-selectable via kconfig menu.
-
-Can be parsed by at least `cbmem`, Linux (exports only binary form) and
-[Skiboot][skiboot].
-
-[skiboot]: https://github.com/open-power/skiboot/
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x32544243 ("CBT2" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
 #### Example:
 ```bash
 PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock]
@@ -186,7 +87,7 @@ PCR-2 178561f046e2adbc621b12b47d65be82756128e2a1fe5116b53ef3637da700e8 SHA256 [F
 PCR-2 091706f5fce3eb123dd9b96c15a9dcc459a694f5e5a86e7bf6064b819a8575c7 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/payload]
 ```
 
-#### Dump TPM eventlog in the OS:
+#### Dump TCPA eventlog in the OS:
 ```bash
 cbmem -L
 ```
@@ -201,64 +102,38 @@ cbfstool coreboot.rom extract -r COREBOOT -n fallback/romstage -U -f /dev/stdout
 cbfstool coreboot.rom read -n SI_ME -f /dev/stdout | sha256sum
 ```
 
-## DRTM
-Certain hardware platforms, for example those with Intel TXT or AMD-V, provide
-a mechanism to dynamically execute a CRTM, referred to as the "Dynamic
-CRTM" (D-CRTM), at any point and repeatedly during a single power life-cycle of
-a system. The trust chain constructed by this D-CRTM is referred to as the
-"Dynamic Root of Trust for Measurement" (DRTM) trust chain. On platforms with
-Intel TXT and AMD-V, the D-CRTM is the CPU itself, which is the reason for these
-capabilities being referred to as having a "Root of Trust" (RoT) rooted in
-hardware.
+## DRTM Mode
+The "Dynamic Root of Trust for Measurement" is realised by platform features
+like Intel TXT or Boot Guard. The features provide a way of loading a signed
+"Authenticated Code Module" aka signed blob. Most of these features are also
+a "Trusted Execution Environment", e.g. Intel TXT.
 
-To provide as an authority assertion and for the DRTM trust chain attestations
-to co-exist with the SRTM trust chain, the TPM provides localities, localities
-1 - 4, which restrict access to a subset of the Platform Configuration
-Registers (PCR), specifically the DRTM PCRs 17 - 22. The mechanism to assert
-authority for access to these localities is platform specific, though the
-intention was for it to be a hardware mechanism. On Intel x86 platforms this is
-controlled through communication between the CPU and the PCH to determine if
-the "Dynamic Launch" instruction, `GETSEC[SENTER]`, was executed and that the
-CPU is in SMX mode. For AMD x86 platforms, this controlled with the APU with a
-similar enforcement that the "Dynamic Launch" instruction, `SKINIT`, was
-executed.
+DRTM gives you the ability of measuring the IBB from a higher Root of Trust
+instead of doing it yourself without any hardware support.
 
-## Platform Configuration Registers
-PCRs are allocated as follows:
-* PCRs 0-15 are SRTM PCRs.
-  - PCRs 0-7 are reserved for firmware usage.
-* PCR 16 is the debug PCR.
-* PCRs 17-22 are DRTM PCRs (PCR 22 is resettable from locality 1).
-* PCR 23 is the application/user PCR and is resettable from locality 0.
+## Platform Configuration Register
+Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 4 PCR
+banks in order to store the measurements. coreboot uses the SHA-1 or SHA-256
+hash algorithm depending on the TPM specification for measurements. PCR-4 to
+PCR-7 are left empty.
 
-coreboot uses 3 or 4 PCRs in order to store the measurements. PCRs 4-7 are left
-empty.
+### PCR-0
+_Hash:_ SHA1
 
-The firmware computes the hash and passes it to TPM.
+_Description:_ Google vboot GBB flags.
 
-The bank used by the TPM depends on the selected eventlog format. CBFS hashes
-use the same algorithm as the bank. However, GBB flags are always hashed by
-SHA-1 and GBB HWID by SHA-256. This results in these hashes being truncated or
-extended with zeroes in eventlog and on passing them to TPM.
+### PCR-1
+_Hash:_ SHA1/SHA256
 
-### If CHROMEOS kconfig option is set
-vboot-specific (non-standard) PCR usage.
+_Description:_ Google vboot GBB HWID.
 
-* PCR-0 - SHA1 of Google vboot GBB flags.
-* PCR-1 - SHA256 of Google vboot GBB HWID.
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
+### PCR-2
+_Hash:_ SHA1/SHA256
 
-### If CHROMEOS kconfig option is NOT set
-See [TPM1.2 Specification][TPM12] (section 3.3.3) and
-[TPM2.0 Specification][TPM20] (section 3.3.4) for PCR assignment information.
+_Description:_ Core Root of Trust for Measurement which includes all stages,
+data and blobs.
 
-* PCR-0 - Unused.
-* PCR-1 - SHA1 of Google vboot GBB flags, SHA256 of Google vboot GBB HWID.
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
+### PCR-3
+_Hash:_ SHA1/SHA256
 
-[TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf
-[TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_v23_pub.pdf
+_Description:_ Runtime data like hwinfo.hex or MRC cache.

Documentation/technotes/console.md

@@ -27,7 +27,7 @@ This feature has been tested on the following platforms:
 | Tested platforms                   |
 +====================================+
 | GA-H61M-S2PV + Intel Ivy Bridge    |
-+------------------------------------+
++---------------------+---------------
 ```
 
 A minimal DDR3 DIMM breakout board PCB design with only the

Documentation/tutorial/part1.md

@@ -6,19 +6,6 @@ coreboot toolchain. In same cases you will find specific instructions
 for Debian (apt-get), Fedora (dnf) and Arch Linux (pacman) based package
 management systems. Use the instructions according to your system.
 
-To test the toolchain and make sure it works, we will build coreboot for
-an emulated system provided by QEMU. This allows you to get familiar
-with the general process of configuring and building coreboot without
-needing to flash any hardware.
-
-**IMPORTANT:**
-**Do not attempt to flash the coreboot ROM built here to a real board**
-
-coreboot is board specific, so a ROM built for one board model (such as
-the QEMU emulation boards) cannot be expected to work on a different
-board. You must reconfigure coreboot for your board and rebuild the ROM
-before flashing it to a physical system.
-
 **Note: Summaries of each of the steps are at the end of the document.**
 
 
@@ -69,7 +56,7 @@ make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
 ```
 
 Note that the i386 toolchain is currently used for all x86 platforms,
-including x86_64. For this tutorial we only need the i386 toolchain.
+including x86_64.
 
 Also note that you can possibly use your system toolchain, but the
 results are not reproducible, and may have issues, so this is not
@@ -116,8 +103,8 @@ select < Exit >
 
 ```Text
 select 'Payload' menu
-select 'Payload to add (SeaBIOS) --->'
-choose 'An ELF executable payload'
+select 'Add a Payload'
+choose 'An Elf executable payload'
 select 'Payload path and filename'
 enter 'payloads/coreinfo/build/coreinfo.elf'
 select < Exit >
@@ -132,26 +119,15 @@ make savedefconfig
 cat defconfig
 ```
 
-There should only be 9 lines (or 10 if you're using the system
+There should only be two lines (or 3 if you're using the system
 toolchain):
 
 ```Text
-CONFIG_CBFS_SIZE=0x00400000
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402
-CONFIG_POST_IO_PORT=0x80
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
 ```
 
-Note that this may differ depending on the revision of the coreboot
-source you are building from and should not be taken as the required
-contents of defconfig. 
-
-### Step 6 - Build coreboot
+### Step 6 - build coreboot
 
 ```Bash
 make
@@ -159,10 +135,10 @@ make
 
 At the end of the build, you should see:
 
-`Built emulation/qemu-i440fx (QEMU x86 i440fx/piix4)`
+`Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)``
 
 This means your build was successful. The output from the build is in
-the `build` directory. `build/coreboot.rom` is the full rom file.
+the build directory. build/coreboot.rom is the full rom file.
 
 
 Test the image using QEMU
@@ -171,7 +147,7 @@ Test the image using QEMU
 
 ### Step 7 - Install QEMU
 
-* Debian: `sudo apt-get install -y qemu-system`
+* Debian: `sudo apt-get install -y qemu`
 * Arch: `sudo pacman -S qemu`
 * Redhat: `sudo dnf install qemu`
 
@@ -246,19 +222,6 @@ coreinfo, a small demonstration payload that allows the user to look at
 various things such as memory and the contents of the coreboot file
 system (CBFS) - the pieces that make up the coreboot rom.
 
-Usually, the coreboot build system automatically builds the payload
-selected in the "Payload to add" menu and sets it as the default payload
-(also known as the "primary payload"). Such payloads are able to boot an
-operating system and may be able to load another payload. Although
-coreinfo can be found in the "Secondary Payloads" menu, in which case it
-would be handled automatically, it is not available as a primary payload
-since it cannot load an OS or another payload. Secondary payloads must
-be loaded from other primary or secondary payloads and will not be run
-when coreboot hands off execution after initializing hardware. Thus, to
-get coreinfo to run as if it were a primary payload, it must be manually
-built and explicitly set as the primary payload using the "ELF
-executable payload" option.
-
 
 ### Step 5 summary - Configure the build
 

MAINTAINERS

@@ -177,11 +177,6 @@ F:	src/mainboard/apple/
 
 
 
-ASROCK B75M-ITX MAINBOARD
-M:	Kevin Keijzer <kevin@quietlife.nl>
-S:	Maintained
-F:	src/mainboard/asrock/b75m-itx/
-
 ASROCK B85M PRO4 MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
@@ -270,10 +265,6 @@ DELL MAINBOARDS
 S:	Orphan
 F:	src/mainboard/dell/
 
-DELL E6400 MAINBOARD
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-S:	Maintained
-F:	src/mainboard/dell/e6400/
 
 
 ELMEX MAINBOARDS
@@ -384,18 +375,6 @@ F:	src/mainboard/google/zork/
 F:	src/mainboard/google/guybrush/
 F:	src/mainboard/google/skyrim/
 
-GOOGLE MEDIATEK-BASED MAINBOARDS
-M:	Hung-Te Lin <hungte@chromium.org>
-M:	Yu-Ping Wu <yupingso@google.com>
-M:	Yidi Lin <yidilin@google.com>
-S:	Supported
-F:	src/mainboard/google/asurada/
-F:	src/mainboard/google/cherry/
-F:	src/mainboard/google/corsola/
-F:	src/mainboard/google/geralt/
-F:	src/mainboard/google/kukui/
-F:	src/mainboard/google/oak/
-
 
 
 HP 280 G2 MAINBOARD
@@ -704,12 +683,6 @@ M:	Caveh Jalali <caveh@chromium.org>
 S:	Maintained
 F:	src/ec/google/
 
-DELL SMSC MEC5035 EC
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-W:	https://github.com/nic3-14159/E6400-EC-research
-S:	Maintained
-F:	src/ec/dell/mec5035/
-
 LENOVO EC
 M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
@@ -916,8 +889,6 @@ F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
 
 MEDIATEK SOCS
 M:	Hung-Te Lin <hungte@chromium.org>
-M:	Yu-Ping Wu <yupingso@google.com>
-M:	Yidi Lin <yidilin@google.com>
 S:	Supported
 F:	src/soc/mediatek/
 
@@ -961,14 +932,6 @@ M:	Marcello Sylvester Bauer <info@marcellobauer.com>
 S:	Supported
 F:	payloads/external/LinuxBoot/
 
-EDK2 PAYLOAD INTEGRATION
-M:	Benjamin Doron <benjamin.doron00@gmail.com>
-M:	Matt DeVillier <matt.devillier@gmail.com>
-M:	Sean Rhodes <sean@starlabs.systems>
-M:	Lean Sheng Tan <sheng.tan@9elements.com>
-S:	Supported
-F:	payloads/external/edk2/
-
 ################################################################################
 # Utilities
 ################################################################################
@@ -1001,7 +964,6 @@ F:	util/crossgcc/
 
 DOCKER
 M:	Martin Roth <gaumless@gmail.com>
-M:	Felix Singer <felixsinger@posteo.net>
 S:	Supported
 F:	util/docker/
 

Makefile

@@ -442,7 +442,7 @@ $(obj)/project_filelist.txt:
 		echo "*** Error: Project must be built before generating file list ***"; \
 		exit 1; \
 	fi
-	find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -name "*.d" -exec cat {} \; | \
+	find $(obj) -path "$(obj)/util" -prune -o -name "*.d" -exec cat {} \; | \
 	  sed "s|$(top)/||" | sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \
 	  grep -v '\.o$$' > $(obj)/project_filelist.txt
 

Makefile.inc

@@ -107,9 +107,6 @@ classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_mi
 $(call add-special-class,all)
 all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
 
-$(call add-special-class,all_x86)
-all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
-
 $(call add-special-class,verstage_x86)
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 verstage_x86-handler = $(eval verstage-y += $(2))
@@ -144,7 +141,6 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
 # toupper:        returns the value in all uppercase
 # ws_to_under:    returns the value with any whitespace changed to underscores
 _toint=$(shell printf "%d" $1)
-_tohex=$(shell printf 0x"%x" $1)
 _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2))
 int-add=$(if $(filter 1,$(words $1)),$(strip $1),$(call int-add,$(call _int-add2,$(word 1,$1),$(word 2,$1)) $(wordlist 3,$(words $1),$1)))
 int-subtract=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) - $(call _toint,$(word 2,$1))))
@@ -314,7 +310,7 @@ cbfs-files-processor-nvramtool= \
 # arg1: input
 # arg2: output
 define cbfs-files-processor-config
-	$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
+	$(eval $(2): $(1) $(obj)/build.h; \
 		+printf "    CREATE     $(2) (from $(1))\n"; \
 		printf "# This image was built using coreboot " > $(2).tmp && \
 		grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
@@ -427,7 +423,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
-CFLAGS_common += -Wdangling-else -Wmissing-include-dirs
+CFLAGS_common += -Wdangling-else
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
@@ -437,6 +433,8 @@ CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference -Wreturn-type
 CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
+# cf. commit f69a99db (coreboot: x86: enable gc-sections)
+CFLAGS_common += -Wno-unused-but-set-variable
 endif
 endif
 
@@ -654,14 +652,6 @@ bootblock-c-deps+=$(DEVICETREE_STATIC_C)
 postcar-c-deps+=$(DEVICETREE_STATIC_C)
 smm-c-deps+=$(DEVICETREE_STATIC_C)
 
-# Ensure fmap_config.h are created before any objects are compiled
-ramstage-c-deps+=$(obj)/fmap_config.h
-romstage-c-deps+=$(obj)/fmap_config.h
-verstage-c-deps+=$(obj)/fmap_config.h
-bootblock-c-deps+=$(obj)/fmap_config.h
-postcar-c-deps+=$(obj)/fmap_config.h
-smm-c-deps+=$(obj)/fmap_config.h
-
 .PHONY: devicetree
 devicetree: $(DEVICETREE_STATIC_C)
 
@@ -832,7 +822,7 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-)
 #
 # This is the default implementation. When using a boot strategy employing
 # multiple CBFSes in fmap regions, override it.
-regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT)
+regions-for-file ?= COREBOOT
 
 ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y)
 	cbfs-autogen-attributes=-g
@@ -935,22 +925,11 @@ prebuild-files = $(foreach region,$(all-regions), \
 		$(call sort-files,$(call placed-files-in-region,$(region))), \
 		$(call cbfs-add-cmd,$(file),$(region),$(CONFIG_UPDATE_IMAGE))))
 
-# If no FMD file (Flashmap) is supplied by mainboard, fall back to a default
 ifeq ($(CONFIG_FMDFILE),)
-
+# For a description of the flash layout described by these variables, check
+# the $(DEFAULT_FLASHMAP) .fmd files.
 ifeq ($(CONFIG_ARCH_X86),y)
-
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
-# check if IFD_CHIPSET is set and if yes generate a FMAP template from IFD descriptor
-ifneq ($(CONFIG_IFD_CHIPSET),)
-ifeq ($(CONFIG_HAVE_IFD_BIN),y)
-DEFAULT_FLASHMAP:=$(obj)/fmap-template.fmd
-$(DEFAULT_FLASHMAP): $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) $(IFDTOOL)
-	echo "    IFDTOOL    -p $(CONFIG_IFD_CHIPSET) -F $@ $<"
-	$(IFDTOOL) -p $(CONFIG_IFD_CHIPSET) -F $@ $<
-endif # ifeq($(CONFIG_HAVE_IFD_BIN),y)
-endif # ifneq($(CONFIG_IFD_CHIPSET),)
-
 # entire flash
 FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)

configs/builder/config.intel.crb.ac

@@ -1,23 +0,0 @@
-# Intel ArcherCity CRB is a dual socket CRB based on Intel
-# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
-#
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
-
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_ARCHERCITY_CRB=y
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-CONFIG_PAYLOAD_LINUX=y
-CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage"
-CONFIG_HAVE_ME_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd"
-CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin"
-CONFIG_ME_BIN_PATH="site-local/archercity/me.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb"
-CONFIG_VALIDATE_INTEL_DESCRIPTOR=y

configs/builder/config.ocp.tiogapass

@@ -2,7 +2,6 @@
 #   make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass
 
 CONFIG_VENDOR_OCP=y
-CONFIG_BOARD_OCP_TIOGAPASS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y

configs/config.facebook_fbg1701.sbom

@@ -1,6 +1,6 @@
-CONFIG_SBOM=y
-CONFIG_SBOM_PAYLOAD=y
-CONFIG_SBOM_ME=y
-CONFIG_SBOM_MICROCODE=y
+CONFIG_INCLUDE_COREBOOT_SBOM=y
+CONFIG_INCLUDE_PAYLOAD_SBOM=y
+CONFIG_INCLUDE_ME_SBOM=y
+CONFIG_INCLUDE_MICROCODE_SBOM=y
 CONFIG_VENDOR_FACEBOOK=y
 CONFIG_BOARD_FACEBOOK_FBG1701=y

configs/config.lenovo_t400_vboot_and_debug

@@ -13,4 +13,3 @@ CONFIG_DEBUG_ADA_CODE=y
 CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
 CONFIG_VBOOT=y
 CONFIG_USE_EXP_X86_64_SUPPORT=y
-CONFIG_ARCH_X86_64_PGTBL_LOC=0xfffe8000

configs/config.protectli_vp2420

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_CBFS_SIZE=0x900000
-CONFIG_ONBOARD_VGA_IS_PRIMARY=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_BOARD_PROTECTLI_VP2420=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4630_vp4650

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_TPM2=y
-CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4670

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4670=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_TPM2=y
-CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

payloads/Makefile.inc

@@ -27,6 +27,7 @@ payloads/external/tint \
 payloads/external/edk2 \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
+payloads/external/Yabits \
 payloads/external/skiboot \
 payloads/external/coreDOOM \
 

payloads/external/LinuxBoot/Kconfig

@@ -189,18 +189,6 @@ config LINUXBOOT_UROOT_MAIN
 	help
 	  Latest u-root version
 
-config LINUXBOOT_UROOT_V7_0_0
-	bool "v7.0.0"
-
-config LINUXBOOT_UROOT_V6_0_0
-	bool "v6.0.0"
-
-config LINUXBOOT_UROOT_V5_0_0
-	bool "v5.0.0"
-
-config LINUXBOOT_UROOT_V4_0_0
-	bool "v4.0.0"
-
 config LINUXBOOT_UROOT_V3_0_0
 	bool "v3.0.0"
 
@@ -220,10 +208,6 @@ config LINUXBOOT_UROOT_VERSION
 	string
 	default LINUXBOOT_UROOT_CHECKOUT if LINUXBOOT_UROOT_CUSTOM
 	default "main" if LINUXBOOT_UROOT_MAIN
-	default "v7.0.0" if LINUXBOOT_UROOT_V7_0_0
-	default "v6.0.0" if LINUXBOOT_UROOT_V6_0_0
-	default "v5.0.0" if LINUXBOOT_UROOT_V5_0_0
-	default "v4.0.0" if LINUXBOOT_UROOT_V4_0_0
 	default "v3.0.0" if LINUXBOOT_UROOT_V3_0_0
 	default "v2.0.0" if LINUXBOOT_UROOT_V2_0_0
 	default "v1.0.0" if LINUXBOOT_UROOT_V1_0_0

payloads/external/Makefile.inc

@@ -166,11 +166,10 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
 		CONFIG_EDK2_CPU_TIMER_LIB=$(CONFIG_EDK2_CPU_TIMER_LIB) \
 		CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
-		CONFIG_EDK2_USE_EDK2_PLATFORMS=$(CONFIG_EDK2_USE_EDK2_PLATFORMS) \
-		CONFIG_EDK2_PLATFORMS_REPOSITORY=$(CONFIG_EDK2_PLATFORMS_REPOSITORY) \
-		CONFIG_EDK2_PLATFORMS_TAG_OR_REV=$(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) \
 		CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
 		CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
+		CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \
+		CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
 		CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
 		CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
 		CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
@@ -186,7 +185,6 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
 		CONFIG_CPU_XTAL_HZ=$(CONFIG_CPU_XTAL_HZ) \
 		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
-		CONFIG_EDK2_SECURE_BOOT_SUPPORT=$(CONFIG_EDK2_SECURE_BOOT_SUPPORT) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -211,6 +209,7 @@ $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG)
 		CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
 		CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
 		CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
+		CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
 		CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
 		CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
 		CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
@@ -364,7 +363,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT)
 	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot
-.PHONY: linuxboot
+
 linuxboot:
 	$(MAKE) -C payloads/external/LinuxBoot \
 		CPUS=$(CPUS) \
@@ -400,6 +399,17 @@ payloads/external/LinuxBoot/linuxboot/bzImage: linuxboot
 payloads/external/LinuxBoot/linuxboot/uImage: linuxboot
 payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio: linuxboot
 
+# Yabits
+
+payloads/external/Yabits/uefi/build/uefi.elf yabits:
+	$(MAKE) -C payloads/external/Yabits all \
+		XGCCPATH="$(XGCCPATH)" \
+		CONFIG_YABITS_REVISION=$(CONFIG_YABITS_REVISION) \
+		CONFIG_YABITS_REVISION_ID=$(CONFIG_YABITS_REVISION_ID) \
+		CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \
+		CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \
+		MFLAGS= MAKEFLAGS=
+
 # BOOTBOOT
 
 payloads/external/BOOTBOOT/bootboot/dist/bootbootcb.elf:

payloads/external/U-Boot/Makefile

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-TAG-$(CONFIG_UBOOT_MASTER)=master
+TAG-$(CONFIG_UBOOT_MASTER)=origin/master
 TAG-$(CONFIG_UBOOT_STABLE)=$(STABLE_COMMIT_ID)
 
 project_name=U-Boot

payloads/external/Yabits/Kconfig

@@ -0,0 +1,47 @@
+if PAYLOAD_YABITS
+
+choice
+	prompt "Yabits version"
+	default YABITS_STABLE
+
+config YABITS_STABLE
+	bool "Stable"
+	help
+	  Stable Yabits version.
+
+	  For reproducible builds, this option must be selected.
+
+config YABITS_MASTER
+	bool "Master"
+	help
+	  Newest version.
+
+	  This option will fetch the newest version of the Yabits code,
+	  updating as new changes are committed.  This makes the build
+	  non-reproducible, as it can fetch different code each time.
+
+config YABITS_REVISION
+	bool "git revision"
+	help
+	  Select this option if you have a specific commit or branch
+	  that you want to use as the revision from which to
+	  build Yabits.  Using a branch name makes the build
+	  non-reproducible, as it can fetch different code as the
+	  branch changes.
+
+	  You will be able to specify the name of a branch or a commit id
+	  later.
+
+endchoice
+
+config YABITS_REVISION_ID
+	string "Insert a commit's SHA-1 or a branch name"
+	depends on YABITS_REVISION
+	default "origin/master"
+	help
+	   The commit's SHA-1 or branch name of the revision to use.
+
+config PAYLOAD_FILE
+	default "payloads/external/Yabits/uefi/build/uefi.elf"
+
+endif

payloads/external/Yabits/Kconfig.name

@@ -0,0 +1,11 @@
+config PAYLOAD_YABITS
+	bool "Yabits - Yet another UEFI Bootloader (Under Development)"
+	depends on ARCH_X86
+	help
+	  Yabits - yabits.github.io
+	  yabits is a pure UEFI coreboot payload. Compared with
+	  TianoCore, it is fast and lightweight. yabits is based on the
+	  part of Minoca OS. It can run GRUB2, Linux, OpenBSD, and other
+	  UEFI applications.
+
+	  It is still under the development and not ready for production.

payloads/external/Yabits/Makefile

@@ -0,0 +1,56 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+TAG-$(CONFIG_YABITS_MASTER)=origin/master
+NAME-$(CONFIG_YABITS_MASTER)=Master
+TAG-$(CONFIG_YABITS_STABLE)=d25abb067431dee9af9f8a874a209730ab7f0e91
+NAME-$(CONFIG_YABITS_STABLE)=Stable
+TAG-$(CONFIG_YABITS_REVISION)=$(CONFIG_YABITS_REVISION_ID)
+
+project_name=Yabits
+project_dir=$(CURDIR)/uefi
+project_git_repo=https://github.com/yabits/uefi.git
+LIBCONFIG_PATH="../../../libpayload"
+
+all: build
+
+$(project_dir):
+	echo "    Cloning $(project_name) from Git"
+	git clone $(project_git_repo) $(project_dir)
+
+fetch: $(project_dir)
+ifeq ($(TAG-y),)
+	echo "Error: The specified tag is invalid"
+ifeq ($(CONFIG_YABITS_REVISION),y)
+	echo "Error: There is no revision specified for $(project_name)"
+	false
+endif
+	false
+endif
+	-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
+		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
+		echo "    Fetching new commits from the $(project_name) git repo"; \
+		git fetch; fi
+
+checkout: fetch
+	echo "    Checking out $(project_name) revision $(NAME-y) ($(TAG-y))"
+	cd $(project_dir); \
+		git checkout master; \
+		git branch -D coreboot 2>/dev/null; \
+		git checkout -b coreboot $(TAG-y)
+
+build: checkout
+	echo "    MAKE       $(project_name) $(NAME-y)"
+	$(if $(wildcard uefi/.xcompile),,$(shell bash ../../../util/xcompile/xcompile > uefi/.xcompile))
+	$(MAKE) -C $(project_dir) defconfig LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH)
+	$(MAKE) -C $(project_dir) all LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH)
+
+clean:
+	test -d $(project_dir) && $(MAKE) -C $(project_dir) clean LIBCONFIG_PATH=$(LIBCONFIG_PATH) XGCC=$(XGCCPATH) || exit 0
+
+distclean:
+	rm -rf $(project_dir)
+
+print-repo-info:
+	echo "$(project_git_repo) $(project_dir)"
+
+.PHONY: all build checkout clean distclean fetch print-repo-info

payloads/external/edk2/Kconfig

@@ -53,7 +53,7 @@ config EDK2_REPOSITORY
 
 config EDK2_TAG_OR_REV
 	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202304" if EDK2_REPO_MRCHROMEBOX
+	default "origin/uefipayload_202207" if EDK2_REPO_MRCHROMEBOX
 	default "origin/master" if EDK2_REPO_OFFICIAL
 	default "" if EDK2_REPO_CUSTOM
 	help
@@ -61,30 +61,6 @@ config EDK2_TAG_OR_REV
 	  EDK2_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
 	  "origin/uefipayload_202202"
 
-config EDK2_USE_EDK2_PLATFORMS
-	bool "Use edk2-platforms repository"
-	default n
-	help
-	  Clone edk2-platforms repository to the edk2 workspace for additional modules.
-
-if EDK2_USE_EDK2_PLATFORMS
-
-config EDK2_PLATFORMS_REPOSITORY
-	string "URL to git repository for edk2-platforms"
-	default "https://github.com/tianocore/edk2-platforms"
-	help
-	  URL to the edk2-platfors repository to clone.
-
-config EDK2_PLATFORMS_TAG_OR_REV
-	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/master"
-	help
-	  The commit's SHA-1 or branch name of the revision to use. This must exist in
-	  EDK2_PLATFORMS_REPOSITORY, and in the case of a branch name, prefixed with
-	  origin i.e. "origin/master"
-
-endif
-
 choice
 	prompt "edk2 build"
 	default EDK2_RELEASE
@@ -104,6 +80,23 @@ config EDK2_RELEASE
 
 endchoice
 
+config EDK2_VERBOSE_BUILD
+	bool "Output verbose build log for troubleshooting build failures"
+	help
+	  Switch off the `-q` (quiet) and `-s` (silent) build arguments which makes the
+	  build log extremely verbose. This can be used to troubleshoot failed builds
+	  which are usually down to missing tools or toolchain.
+
+config EDK2_ABOVE_4G_MEMORY
+	bool "Enable above 4G memory"
+	default n
+	help
+	  Select this option to enable Above 4G Decode. This will allow the
+	  payload to use all of the memory, rather than an maximum of 4G.
+
+	  Disabling memory above 4G is useful for bootloaders that are not
+	  fully 64-bit aware such as Qubes R4.0.4 bootloader.
+
 config EDK2_BOOTSPLASH_FILE
 	string "edk2 Bootsplash path and filename"
 	default "Documentation/coreboot_logo.bmp"
@@ -225,14 +218,6 @@ config EDK2_SERIAL_SUPPORT
 	  Enable serial port output in edk2. Serial output limits the performance of edk2's
 	  FrontPage.
 
-config EDK2_SECURE_BOOT_SUPPORT
-	bool "Enable UEFI Secure Boot support"
-	depends on EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
-	default y if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
-	help
-	  Select this option to enable UEFI SecureBoot support in edk2.
-	  UEFI SecureBoot will be disabled by default and can be enabled from the menu option.
-
 config EDK2_CUSTOM_BUILD_PARAMS
 	string "edk2 additional custom build parameters"
 	default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2

payloads/external/edk2/Makefile

@@ -6,22 +6,7 @@ export SHELL := env bash
 project_name = edk2
 export WORKSPACE := $(CURDIR)/workspace
 export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
-
-ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y)
-export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms
-export PACKAGES_PATH := $(EDK2_PATH):\
-			$(EDK2_PLATFORMS_PATH)/Platform/Intel:\
-			$(EDK2_PLATFORMS_PATH)/Silicon/Intel:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/Debugging:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/Network:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/OutOfBandManagement:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/PowerManagement:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/SystemInformation:\
-			$(EDK2_PLATFORMS_PATH)/Features/Intel/UserInterface
-else
 export PACKAGES_PATH := $(EDK2_PATH)
-endif
 
 OBJCOPY = $(GCC_PREFIX)objcopy
 
@@ -30,7 +15,7 @@ BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc
 endif
 BUILD_STR += -t COREBOOT
 BUILD_STR += -D BOOTLOADER=COREBOOT
-ifneq ($(V),1)
+ifneq ($(CONFIG_EDK2_VERBOSE_BUILD),y)
 BUILD_STR += -q
 ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
 BUILD_STR += -s
@@ -43,6 +28,10 @@ endif
 #
 # OPTION			= DEFAULT_VALUE
 #
+# ABOVE_4G_MEMORY		= TRUE
+ifneq ($(CONFIG_EDK2_ABOVE_4G_MEMORY),y)
+BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
+endif
 # BOOTSPLASH_IMAGE		= FALSE
 ifneq ($(CONFIG_EDK2_BOOTSPLASH_FILE),)
 BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
@@ -107,10 +96,6 @@ endif
 ifneq ($(CONFIG_EDK2_SD_MMC_TIMEOUT),)
 BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_EDK2_SD_MMC_TIMEOUT) * 1000)) )
 endif
-# EDK2_SECURE_BOOT_SUPPORT      = FALSE
-ifeq ($(CONFIG_EDK2_SECURE_BOOT_SUPPORT), y)
-BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE
-endif
 
 #
 # EDKII has the below PCDs that are relevant to coreboot:
@@ -134,23 +119,6 @@ all: UefiPayloadPkg
 $(WORKSPACE):
 	mkdir $(WORKSPACE)
 
-$(EDK2_PLATFORMS_PATH): $(WORKSPACE)
-	if [ ! -d "$(EDK2_PLATFORMS_PATH)" ]; then \
-		git clone --recurse-submodules $(CONFIG_EDK2_PLATFORMS_REPOSITORY) $(EDK2_PLATFORMS_PATH) -j5; \
-	fi
-	cd $(EDK2_PLATFORMS_PATH); \
-		if ! git rev-parse --verify -q $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) >/dev/null; then \
-			echo "    $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) is not a valid git reference"; \
-			exit 1; \
-		fi; \
-		if git status --ignore-submodules=dirty | grep -q "nothing to commit, working tree clean"; then \
-			echo "    Checking out edk2-platforms revision $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV)"; \
-			git checkout --detach $(CONFIG_EDK2_PLATFORMS_TAG_OR_REV) -f; \
-		else \
-			echo "    Working directory not clean; will not overwrite"; \
-		fi; \
-		git submodule update --init --checkout
-
 $(EDK2_PATH): $(WORKSPACE)
 	if [ ! -d "$(EDK2_PATH)" ]; then \
 		git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \
@@ -208,7 +176,6 @@ print:
 	echo "   ##### $(project_name) Build Summary #####"
 	echo "   Repository:     $(CONFIG_EDK2_REPOSITORY)"
 	echo "   Branch:         $(CONFIG_EDK2_TAG_OR_REV)"
-	echo "   Packages path:  $(PACKAGES_PATH)"
 	echo " $(BUILD_STR)" | \
 		sed -e 's/--/-/g' -e 's/-/\n   /g' | sort | sed \
 		-e 's/a /Architecture:   /g' \
@@ -220,7 +187,7 @@ print:
 		-e 's/s /Build:          Silent/' \
 		-e 's/t /Toolchain:      /'
 
-prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo
+prep: $(EDK2_PATH) clean checktools logo
 	cd $(WORKSPACE); \
 		source $(EDK2_PATH)/edksetup.sh; \
 		unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \

payloads/libpayload/arch/x86/boot_media.c

@@ -1,7 +1,11 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
 
-#include <libpayload.h>
+#include <arch/virtual.h>
 #include <boot_device.h>
+#include <commonlib/bsd/cb_err.h>
+#include <stddef.h>
+#include <string.h>
+#include <sysinfo.h>
 
 __attribute__((weak)) ssize_t boot_device_read(void *buf, size_t offset, size_t size)
 {

payloads/libpayload/bin/lpgcc

@@ -229,5 +229,5 @@ else
     # header to be placed below 0x2000 in the resulting image.  See:
     # http://www.gnu.org/software/grub/manual/multiboot/html_node/OS-image-format.html
 
-    $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload -xnone $_LIBGCC
+    $DEFAULT_CC $_LDFLAGS $HEAD_O $CMDLINE $_CFLAGS -lpayload $_LIBGCC
 fi

payloads/libpayload/curses/PDCurses/aclocal.m4

@@ -463,7 +463,7 @@ EOF
 			DYN_COMP=""
 		else
 			slash="\\"
-			mh_dyncomp="`grep -E -c $slash$a conftest.tmp`"
+			mh_dyncomp="`egrep -c $slash$a conftest.tmp`"
 			if test "$mh_dyncomp" = "0"; then
 				DYN_COMP="$a -DDYNAMIC"
 				AC_MSG_RESULT($a)

payloads/libpayload/include/assert.h

@@ -50,7 +50,7 @@ void mock_assert(const int result, const char *const expression, const char *con
 	if ((statement) == 0) {					\
 		fprintf(stderr, "assertion failed in file %s, "	\
 			"function %s(), line %d\n",		\
-			 __FILE__, __func__, __LINE__);	\
+			 __FILE__, __FUNCTION__, __LINE__);	\
 		abort();					\
 	}
 #endif

payloads/libpayload/include/die.h

@@ -35,7 +35,7 @@ void die_work(const char *file, const char *func, const int line,
 	__attribute__((noreturn));
 
 #define die(fmt, args...) \
-	do { die_work(__FILE__, __func__, __LINE__, fmt, ##args); } \
+	do { die_work(__FILE__, __FUNCTION__, __LINE__, fmt, ##args); } \
 	while (0)
 
 #define die_if(condition, fmt, args...) \

payloads/libpayload/include/stddef.h

@@ -2,10 +2,7 @@
 #define _STDDEF_H
 
 #include <arch/types.h>
-
-#if !defined(offsetof)
-#define offsetof(type, member) __builtin_offsetof(type, member)
-#endif
+#include <commonlib/bsd/helpers.h>
 
 #ifndef __WCHAR_TYPE__
 #define __WCHAR_TYPE__ int

payloads/libpayload/include/stdlib.h

@@ -148,7 +148,7 @@ static inline void *xmalloc_work(size_t size, const char *file,
 	}
 	return ret;
 }
-#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__)
+#define xmalloc(size) xmalloc_work((size), __FILE__, __FUNCTION__, __LINE__)
 
 static inline void *xzalloc_work(size_t size, const char *file,
 				 const char *func, int line)
@@ -157,7 +157,7 @@ static inline void *xzalloc_work(size_t size, const char *file,
 	memset(ret, 0, size);
 	return ret;
 }
-#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__)
+#define xzalloc(size) xzalloc_work((size), __FILE__, __FUNCTION__, __LINE__)
 
 static inline void *xmemalign_work(size_t align, size_t size, const char *file,
 				  const char *func, int line)

payloads/libpayload/include/string.h

@@ -59,7 +59,6 @@ char *strcat(char *d, const char *s);
 char *strchr(const char *s, int c);
 char *strrchr(const char *s, int c);
 char *strdup(const char *s);
-char *strndup(const char *s, size_t size);
 char *strstr(const char *h, const char *n);
 char *strsep(char **stringp, const char *delim);
 size_t strspn(const char *s, const char *a);

payloads/libpayload/include/strings.h

@@ -29,6 +29,8 @@
 #ifndef _STRINGS_H
 #define _STRINGS_H
 
-#define ffs(x) __builtin_ffs(x)
+#include <libpayload.h>
+
+static inline int ffs(int i) { return __ffs(i) + 1; }
 
 #endif

payloads/libpayload/libc/string.c

@@ -321,25 +321,6 @@ char *strdup(const char *s)
 	return p;
 }
 
-/**
- * Duplicate a string with a max length of size
- *
- * @param s The string to duplicate.
- * @param size The max length of the string
- * @return A pointer to the copy of the original string.
- */
-char *strndup(const char *s, size_t size)
-{
-	size_t n = strnlen(s, size);
-	char *p = malloc(n + 1);
-
-	if (p != NULL) {
-		strncpy(p, s, n);
-		p[n] = 0;
-	}
-	return p;
-}
-
 /**
  * Find a substring within a string.
  *

payloads/libpayload/vboot/Kconfig

@@ -24,12 +24,4 @@ config VBOOT_X86_SHA_EXT
 	  This option enables SHA256 implementation using x86 SHA processor extension
 	  instructions: sha256msg1, sha256msg2, sha256rnds2.
 
-config VBOOT_SHA_ARMV8_CE
-	bool "SHA256 implementation using ARMv8 Crypto Extension"
-	default y if CHROMEOS
-	default n
-	depends on ARCH_ARM64
-	help
-	  This option enables SHA256 implementation using ARMv8 Crypto Extension.
-
 endif

payloads/libpayload/vboot/Makefile.inc

@@ -37,7 +37,6 @@ $(VBOOT_FW_LIB): $(obj)/libpayload-config.h
 		$(MAKE) -C "$(VBOOT_SOURCE)" \
 		TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \
 		X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \
-		ARMV8_CRYPTO_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_SHA_ARMV8_CE)) \
 		UNROLL_LOOPS=1 \
 		BUILD="$(VBOOT_BUILD_DIR)" \
 		V=$(V) \

spd/lp5/memory_parts.json

@@ -50,7 +50,7 @@
                 "speedMbps": 6400
             }
         },
-        {
+	{
             "name": "MT62F2G32D8DR-031 WT:B",
             "attribs": {
                 "densityPerDieGb": 8,
@@ -132,17 +132,6 @@
                 "lp5x": true
             }
         },
-        {
-            "name":  "K3KL6L60GM-MGCT",
-            "attribs": {
-                "densityPerDieGb": 8,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 7500,
-                "lp5x": true
-            }
-        },
         {
             "name":  "K3KL8L80CM-MGCT",
             "attribs": {
@@ -187,7 +176,7 @@
                 "lp5x": true
             }
         },
-        {
+	{
             "name": "H9JCNNNFA5MLYR-N6E",
             "attribs": {
                 "densityPerDieGb": 8,
@@ -196,50 +185,6 @@
                 "ranksPerChannel": 2,
                 "speedMbps": 6400
             }
-        },
-        {
-            "name": "H58G66BK8BX067",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 4,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
-        },
-        {
-            "name": "H58G56BK8BX068",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
-        },
-        {
-            "name": "MT62F1G32D2DS-023 WT:B",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 2,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 1,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
-        },
-        {
-            "name": "MT62F2G32D4DS-023 WT:B",
-            "attribs": {
-                "densityPerDieGb": 16,
-                "diesPerPackage": 4,
-                "bitWidthPerChannel": 16,
-                "ranksPerChannel": 2,
-                "speedMbps": 8533,
-                "lp5x": true
-            }
         }
     ]
 }

spd/lp5/platforms_manifest.generated.txt

@@ -3,5 +3,4 @@
 
 MTL,set-0
 ADL,set-0
-PHX,set-1
 MDN,set-1

spd/lp5/set-0/parts_spd_manifest.generated.txt

@@ -14,13 +14,8 @@ MT62F1G32D4DS-031 WT:B,spd-2.hex
 K3LKCKC0BM-MGCP,spd-6.hex
 MT62F1G32D2DS-026 WT:B,spd-7.hex
 MT62F2G32D4DS-026 WT:B,spd-8.hex
-K3KL6L60GM-MGCT,spd-9.hex
 K3KL8L80CM-MGCT,spd-7.hex
 K3KL9L90CM-MGCT,spd-8.hex
 H58G66BK7BX067,spd-8.hex
 H58G56BK7BX068,spd-7.hex
 H9JCNNNFA5MLYR-N6E,spd-4.hex
-H58G66BK8BX067,spd-10.hex
-H58G56BK8BX068,spd-11.hex
-MT62F1G32D2DS-023 WT:B,spd-11.hex
-MT62F2G32D4DS-023 WT:B,spd-10.hex

spd/lp5/set-0/spd-11.hex

@@ -1,32 +0,0 @@
-23 10 15 0E 16 22 95 08 00 00 00 00 02 01 00 00
-00 00 08 00 00 00 00 00 AD 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 B6 00 C1 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-0/spd-9.hex

@@ -1,11 +1,11 @@
-23 10 15 0E 15 1A 95 08 00 00 00 00 02 01 00 00
-00 00 09 00 00 00 00 00 AB 00 90 A8 90 90 06 C0
+23 10 13 0E 15 1A F9 08 00 00 00 00 0A 01 00 00
+00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 C9 00 C5 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-1/parts_spd_manifest.generated.txt

@@ -14,13 +14,8 @@ MT62F1G32D4DS-031 WT:B,spd-2.hex
 K3LKCKC0BM-MGCP,spd-6.hex
 MT62F1G32D2DS-026 WT:B,spd-7.hex
 MT62F2G32D4DS-026 WT:B,spd-8.hex
-K3KL6L60GM-MGCT,spd-9.hex
 K3KL8L80CM-MGCT,spd-7.hex
 K3KL9L90CM-MGCT,spd-8.hex
 H58G66BK7BX067,spd-8.hex
 H58G56BK7BX068,spd-7.hex
 H9JCNNNFA5MLYR-N6E,spd-4.hex
-H58G66BK8BX067,spd-10.hex
-H58G56BK8BX068,spd-11.hex
-MT62F1G32D2DS-023 WT:B,spd-11.hex
-MT62F2G32D4DS-023 WT:B,spd-10.hex

spd/lp5/set-1/spd-10.hex

@@ -1,32 +0,0 @@
-23 11 13 0E 86 21 B5 18 00 40 00 00 0A 02 00 00
-00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-1/spd-11.hex

@@ -1,32 +0,0 @@
-23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00
-00 00 02 00 00 00 00 00 2C 00 90 A8 90 C0 08 60
-04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 8A 00 F0 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
-20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

spd/lp5/set-1/spd-9.hex

@@ -1,11 +1,11 @@
-23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00
+23 11 13 0E 85 19 F9 18 00 40 00 00 0A 02 00 00
 00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0
 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 C9 00 93 00 00
+00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/Kconfig

@@ -142,8 +142,6 @@ choice
 	prompt "Option backend to use"
 	default USE_MAINBOARD_SPECIFIC_OPTION_BACKEND if HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
 	default USE_OPTION_TABLE if NVRAMCUI_SECONDARY_PAYLOAD
-	default USE_UEFI_VARIABLE_STORE if DRIVERS_EFI_VARIABLE_STORE && \
-		PAYLOAD_EDK2 && SMMSTORE_V2
 
 config OPTION_BACKEND_NONE
 	bool "None"
@@ -155,15 +153,6 @@ config USE_OPTION_TABLE
 	  Enable this option if coreboot shall read options from the "CMOS"
 	  NVRAM instead of using hard-coded values.
 
-config USE_UEFI_VARIABLE_STORE
-	bool "Use UEFI variable-store in SPI flash as option backend"
-	depends on DRIVERS_EFI_VARIABLE_STORE
-	depends on SMMSTORE_V2
-	help
-	  Enable this option if coreboot shall read/write options from the
-	  SMMSTORE region within the SPI flash. The region must be formatted
-	  by the payload first before it can be used.
-
 config USE_MAINBOARD_SPECIFIC_OPTION_BACKEND
 	bool "Use mainboard-specific option backend"
 	depends on HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND
@@ -573,7 +562,7 @@ config CBFS_SIZE
 	# Default value set at the end of the file
 	help
 	  This is the part of the ROM actually managed by CBFS, located at the
-	  end of the ROM (passed through cbfstool -o) on x86 and at the start
+	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
 	  of the ROM (passed through cbfstool -s) everywhere else. It defaults
 	  to span the whole ROM on all but Intel systems that use an Intel Firmware
 	  Descriptor.  It can be overridden to make coreboot live alongside other
@@ -711,12 +700,6 @@ config MAX_CPUS
 
 source "src/console/Kconfig"
 
-config ACPI_S1_NOT_SUPPORTED
-	bool
-	default n
-	help
-	  Set this to 'y' on platforms that do not support ACPI S1 state.
-
 config HAVE_ACPI_RESUME
 	bool
 	default n
@@ -889,11 +872,10 @@ config SMBIOS_PROVIDED_BY_MOBO
 	bool
 	default n
 
-if GENERATE_SMBIOS_TABLES
-
 config MAINBOARD_SERIAL_NUMBER
 	prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
 	string
+	depends on GENERATE_SMBIOS_TABLES
 	default "123456789"
 	help
 	  The Serial Number to store in SMBIOS structures.
@@ -901,6 +883,7 @@ config MAINBOARD_SERIAL_NUMBER
 config MAINBOARD_VERSION
 	prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
 	string
+	depends on GENERATE_SMBIOS_TABLES
 	default "1.0"
 	help
 	  The Version Number to store in SMBIOS structures.
@@ -908,6 +891,7 @@ config MAINBOARD_VERSION
 config MAINBOARD_SMBIOS_MANUFACTURER
 	prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
 	string
+	depends on GENERATE_SMBIOS_TABLES
 	default MAINBOARD_VENDOR
 	help
 	  Override the default Manufacturer stored in SMBIOS structures.
@@ -915,6 +899,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
 	string
+	depends on GENERATE_SMBIOS_TABLES
 	default MAINBOARD_PART_NUMBER
 	help
 	  Override the default Product name stored in SMBIOS structures.
@@ -922,15 +907,13 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
 config VPD_SMBIOS_VERSION
 	bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
 	default n
-	depends on VPD
+	depends on VPD && GENERATE_SMBIOS_TABLES
 	help
 	  Selecting this option will read firmware_version from
 	  VPD_RO and override SMBIOS type 0 version. One special
 	  scenario of using this feature is to assign a BIOS version
 	  to a coreboot image without the need to rebuild from source.
 
-endif
-
 endmenu
 
 source "payloads/Kconfig"
@@ -1093,11 +1076,10 @@ config X86EMU_DEBUG
 
 	  If unsure, say N.
 
-if X86EMU_DEBUG
-
 config X86EMU_DEBUG_JMP
 	bool "Trace JMP/RETF"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print information about JMP and RETF opcodes from x86emu.
 
@@ -1108,6 +1090,7 @@ config X86EMU_DEBUG_JMP
 config X86EMU_DEBUG_TRACE
 	bool "Trace all opcodes"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print _all_ opcodes that are executed by x86emu.
 
@@ -1120,6 +1103,7 @@ config X86EMU_DEBUG_TRACE
 config X86EMU_DEBUG_PNP
 	bool "Log Plug&Play accesses"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print Plug And Play accesses made by option ROMs.
 
@@ -1130,6 +1114,7 @@ config X86EMU_DEBUG_PNP
 config X86EMU_DEBUG_DISK
 	bool "Log Disk I/O"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print Disk I/O related messages.
 
@@ -1140,6 +1125,7 @@ config X86EMU_DEBUG_DISK
 config X86EMU_DEBUG_PMM
 	bool "Log PMM"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print messages related to POST Memory Manager (PMM).
 
@@ -1151,6 +1137,7 @@ config X86EMU_DEBUG_PMM
 config X86EMU_DEBUG_VBE
 	bool "Debug VESA BIOS Extensions"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print messages related to VESA BIOS Extension (VBE) functions.
 
@@ -1161,6 +1148,7 @@ config X86EMU_DEBUG_VBE
 config X86EMU_DEBUG_INT10
 	bool "Redirect INT10 output to console"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Let INT10 (i.e. character output) calls print messages to debug output.
 
@@ -1171,6 +1159,7 @@ config X86EMU_DEBUG_INT10
 config X86EMU_DEBUG_INTERRUPTS
 	bool "Log intXX calls"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print messages related to interrupt handling.
 
@@ -1181,6 +1170,7 @@ config X86EMU_DEBUG_INTERRUPTS
 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
 	bool "Log special memory accesses"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print messages related to accesses to certain areas of the virtual
 	  memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
@@ -1192,6 +1182,7 @@ config X86EMU_DEBUG_CHECK_VMEM_ACCESS
 config X86EMU_DEBUG_MEM
 	bool "Log all memory accesses"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print memory accesses made by option ROM.
 	  Note: This also includes accesses to fetch instructions.
@@ -1203,6 +1194,7 @@ config X86EMU_DEBUG_MEM
 config X86EMU_DEBUG_IO
 	bool "Log IO accesses"
 	default n
+	depends on X86EMU_DEBUG
 	help
 	  Print I/O accesses made by option ROM.
 
@@ -1213,14 +1205,12 @@ config X86EMU_DEBUG_IO
 config X86EMU_DEBUG_TIMINGS
 	bool "Output timing information"
 	default n
-	depends on HAVE_MONOTONIC_TIMER
+	depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
 	help
 	  Print timing information needed by i915tool.
 
 	  If unsure, say N.
 
-endif
-
 config DEBUG_SPI_FLASH
 	bool "Output verbose SPI flash debug messages"
 	default n

src/acpi/Kconfig

@@ -8,11 +8,12 @@ config ACPI_AMD_HARDWARE_SLEEP_VALUES
 
 config ACPI_CPU_STRING
 	string
-	default "CP%02X"
+	default "\\_SB.CP%02X"
 	depends on HAVE_ACPI_TABLES
 	help
-	  Specifies the ACPI name format string used by the acpigen
-	  function to generate the processor scope. Default is CPxx.
+	  Sets the ACPI name string in the processor scope as written by
+	  the acpigen function. Default is \_SB.CPxx. Note that you need
+	  the \ escape character in the string.
 
 config ACPI_HAVE_PCAT_8259
 	def_bool y if !ACPI_NO_PCAT_8259
@@ -29,22 +30,10 @@ config ACPI_SOC_NVS
 	  Set to indicate <soc/nvs.h> exists for the platform with a definition
 	  for global_nvs.
 
-config ACPI_CUSTOM_MADT
+config ACPI_NO_MADT
 	bool
-	default n if ACPI_NO_CUSTOM_MADT
-	default y
 	help
-	  Selected by platforms that need to expose custom MADT entries.
-
-config ACPI_NO_CUSTOM_MADT
-	bool
-	default y if ACPI_COMMON_MADT_LAPIC && ACPI_COMMON_MADT_IOAPIC
-
-config ACPI_COMMON_MADT_LAPIC
-	bool
-
-config ACPI_COMMON_MADT_IOAPIC
-	bool
+	  Selected by platforms that don't expose a useful MADT.
 
 config ACPI_NO_PCAT_8259
 	bool

src/acpi/acpi.c

@@ -17,7 +17,6 @@
 #include <acpi/acpi_ivrs.h>
 #include <acpi/acpigen.h>
 #include <arch/hpet.h>
-#include <arch/smp/mpspec.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>
@@ -123,7 +122,7 @@ int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base,
 	return sizeof(acpi_mcfg_mmconfig_t);
 }
 
-static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
+int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 {
 	lapic->type = LOCAL_APIC; /* Local APIC structure */
 	lapic->length = sizeof(acpi_madt_lapic_t);
@@ -134,7 +133,7 @@ static int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 	return lapic->length;
 }
 
-static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic)
+int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic)
 {
 	lapic->type = LOCAL_X2APIC; /* Local APIC structure */
 	lapic->reserved = 0;
@@ -146,53 +145,28 @@ static int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 api
 	return lapic->length;
 }
 
-unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id)
-{
-	if (lapic_id <= ACPI_MADT_MAX_LAPIC_ID)
-		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index,
-						  lapic_id);
-	else
-		current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index,
-						    lapic_id);
-
-	return current;
-}
-
-/* Increase if necessary. Currently all x86 CPUs only have 2 SMP threads */
-#define MAX_THREAD_ID 1
-/*
- * From ACPI 6.4 spec:
- * "The advent of multi-threaded processors yielded multiple logical processors
- * executing on common processor hardware. ACPI defines logical processors in
- * an identical manner as physical processors. To ensure that non
- * multi-threading aware OSPM implementations realize optimal performance on
- * platforms containing multi-threaded processors, two guidelines should be
- * followed. The first is the same as above, that is, OSPM should initialize
- * processors in the order that they appear in the MADT. The second is that
- * platform firmware should list the first logical processor of each of the
- * individual multi-threaded processors in the MADT before listing any of the
- * second logical processors. This approach should be used for all successive
- * logical processors."
- */
-static unsigned long acpi_create_madt_lapics(unsigned long current)
+unsigned long acpi_create_madt_lapics(unsigned long current)
 {
 	struct device *cpu;
-	int index, apic_ids[CONFIG_MAX_CPUS] = {0}, num_cpus = 0, sort_start = 0;
-	for (unsigned int thread_id = 0; thread_id <= MAX_THREAD_ID; thread_id++) {
-		for (cpu = all_devices; cpu; cpu = cpu->next) {
-			if (!is_enabled_cpu(cpu))
-				continue;
-			if (num_cpus >= ARRAY_SIZE(apic_ids))
-				break;
-			if (cpu->path.apic.thread_id != thread_id)
-				continue;
-			apic_ids[num_cpus++] = cpu->path.apic.apic_id;
-		}
-		bubblesort(&apic_ids[sort_start], num_cpus - sort_start, NUM_ASCENDING);
-		sort_start = num_cpus;
+	int index, apic_ids[CONFIG_MAX_CPUS] = {0}, num_cpus = 0;
+
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
+		if (!is_enabled_cpu(cpu))
+			continue;
+		if (num_cpus >= ARRAY_SIZE(apic_ids))
+			break;
+		apic_ids[num_cpus++] = cpu->path.apic.apic_id;
+	}
+	if (num_cpus > 1)
+		bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
+	for (index = 0; index < num_cpus; index++) {
+		if (apic_ids[index] < 0xff)
+			current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
+					index, apic_ids[index]);
+		else
+			current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current,
+					index, apic_ids[index]);
 	}
-	for (index = 0; index < num_cpus; index++)
-		current = acpi_create_madt_one_lapic(current, index, apic_ids[index]);
 
 	return current;
 }
@@ -226,24 +200,6 @@ int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr)
 }
 #endif
 
-static u16 acpi_sci_int(void)
-{
-#if ENV_X86
-	u8 gsi, irq, flags;
-
-	ioapic_get_sci_pin(&gsi, &irq, &flags);
-
-	/* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */
-	if (!CONFIG(ACPI_HAVE_PCAT_8259))
-		return gsi;
-
-	assert(irq < 16);
-	return irq;
-#else
-	return 0;
-#endif
-}
-
 int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
 		u8 bus, u8 source, u32 gsirq, u16 flags)
 {
@@ -257,38 +213,7 @@ int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride,
 	return irqoverride->length;
 }
 
-int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride)
-{
-	u8 gsi, irq, flags;
-
-	ioapic_get_sci_pin(&gsi, &irq, &flags);
-
-	if (!CONFIG(ACPI_HAVE_PCAT_8259))
-		irq = gsi;
-
-	irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */
-	irqoverride->length = sizeof(acpi_madt_irqoverride_t);
-	irqoverride->bus = MP_BUS_ISA;
-	irqoverride->source = irq;
-	irqoverride->gsirq = gsi;
-	irqoverride->flags = flags;
-
-	return irqoverride->length;
-}
-
-static unsigned long acpi_create_madt_ioapic_gsi0_default(unsigned long current)
-{
-	current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR);
-
-	current += acpi_create_madt_irqoverride((void *)current, MP_BUS_ISA, 0, 2,
-						MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
-
-	current += acpi_create_madt_sci_override((void *)current);
-
-	return current;
-}
-
-static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
+int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
 				u16 flags, u8 lint)
 {
 	lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */
@@ -300,7 +225,7 @@ static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
 	return lapic_nmi->length;
 }
 
-static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
+int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu,
 				 u16 flags, u8 lint)
 {
 	lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */
@@ -315,10 +240,12 @@ static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32
 	return lapic_nmi->length;
 }
 
-unsigned long acpi_create_madt_lapic_nmis(unsigned long current)
+unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current)
 {
 	const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH;
 
+	current = acpi_create_madt_lapics(current);
+
 	/* 1: LINT1 connect to NMI */
 	/* create all subtables for processors */
 	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
@@ -331,14 +258,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current)
 	return current;
 }
 
-unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current)
-{
-	current = acpi_create_madt_lapics(current);
-	current = acpi_create_madt_lapic_nmis(current);
-	return current;
-}
-
-static void acpi_create_madt(acpi_madt_t *madt)
+void acpi_create_madt(acpi_madt_t *madt)
 {
 	acpi_header_t *header = &(madt->header);
 	unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t);
@@ -362,13 +282,7 @@ static void acpi_create_madt(acpi_madt_t *madt)
 	if (CONFIG(ACPI_HAVE_PCAT_8259))
 		madt->flags |= 1;
 
-	if (CONFIG(ACPI_COMMON_MADT_LAPIC))
-		current = acpi_create_madt_lapics_with_nmis(current);
-
-	if (CONFIG(ACPI_COMMON_MADT_IOAPIC))
-		current = acpi_create_madt_ioapic_gsi0_default(current);
-
-	if (CONFIG(ACPI_CUSTOM_MADT))
+	if (!CONFIG(ACPI_NO_MADT))
 		current = acpi_fill_madt(current);
 
 	/* (Re)calculate length and checksum. */
@@ -386,7 +300,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 }
 
 /* MCFG is defined in the PCI Firmware Specification 3.0. */
-static void acpi_create_mcfg(acpi_mcfg_t *mcfg)
+void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 {
 	acpi_header_t *header = &(mcfg->header);
 	unsigned long current = (unsigned long)mcfg + sizeof(acpi_mcfg_t);
@@ -570,7 +484,7 @@ static void acpi_ssdt_write_cbtable(void)
 	acpigen_pop_len();
 }
 
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
+void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 {
 	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
 
@@ -617,19 +531,6 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
 	return lapic->length;
 }
 
-int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic)
-{
-	memset((void *)x2apic, 0, sizeof(acpi_srat_x2apic_t));
-
-	x2apic->type = 2; /* Processor x2APIC structure */
-	x2apic->length = sizeof(acpi_srat_x2apic_t);
-	x2apic->flags = (1 << 0); /* Enabled (the use of this structure). */
-	x2apic->proximity_domain = node;
-	x2apic->x2apic_id = apic;
-
-	return x2apic->length;
-}
-
 int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,
 				u32 flags)
 {
@@ -1042,7 +943,7 @@ void acpi_create_slit(acpi_slit_t *slit,
 }
 
 /* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */
-static void acpi_create_hpet(acpi_hpet_t *hpet)
+void acpi_create_hpet(acpi_hpet_t *hpet)
 {
 	acpi_header_t *header = &(hpet->header);
 	acpi_addr_t *addr = &(hpet->addr);
@@ -1383,7 +1284,7 @@ unsigned long acpi_write_hpet(const struct device *device, unsigned long current
 	return current;
 }
 
-static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,
+void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,
 		      int port_type, int port_subtype,
 		      acpi_addr_t *address, uint32_t address_size,
 		      const char *device_path)
@@ -1504,7 +1405,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
 	return current;
 }
 
-static void acpi_create_facs(acpi_facs_t *facs)
+void acpi_create_facs(acpi_facs_t *facs)
 {
 	memset((void *)facs, 0, sizeof(acpi_facs_t));
 
@@ -1681,7 +1582,7 @@ void acpi_write_hest(acpi_hest_t *hest,
 }
 
 /* ACPI 3.0b */
-static void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length)
+void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length)
 {
 	acpi_header_t *header = &(bert->header);
 
@@ -1709,7 +1610,7 @@ __weak void arch_fill_fadt(acpi_fadt_t *fadt) { }
 __weak void soc_fill_fadt(acpi_fadt_t *fadt) { }
 __weak void mainboard_fill_fadt(acpi_fadt_t *fadt) { }
 
-static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
 
@@ -1738,17 +1639,10 @@ static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	/* should be 0 ACPI 3.0 */
 	fadt->reserved = 0;
 
-	/* P_LVLx latencies are not used as CPU _CST will override them. */
-	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
-	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
-
-	/* Use CPU _PTC instead to provide P_CNT details. */
-	fadt->duty_offset = 0;
-	fadt->duty_width = 0;
-
 	fadt->preferred_pm_profile = acpi_get_preferred_pm_profile();
 
-	fadt->sci_int = acpi_sci_int();
+	if (CONFIG(USE_PC_CMOS_ALTCENTURY))
+		fadt->century = RTC_CLK_ALTCENTURY;
 
 	arch_fill_fadt(fadt);
 
@@ -1761,7 +1655,7 @@ static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	    acpi_checksum((void *)fadt, header->length);
 }
 
-static void acpi_create_lpit(acpi_lpit_t *lpit)
+void acpi_create_lpit(acpi_lpit_t *lpit)
 {
 	acpi_header_t *header = &(lpit->header);
 	unsigned long current = (unsigned long)lpit + sizeof(acpi_lpit_t);
@@ -1857,7 +1751,6 @@ unsigned long write_acpi_tables(unsigned long start)
 		for (void *p = (void *)current; p < (void *)fw; p += 16) {
 			if (valid_rsdp((acpi_rsdp_t *)p)) {
 				rsdp = p;
-				coreboot_rsdp = (uintptr_t)rsdp;
 				break;
 			}
 		}
@@ -1906,7 +1799,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	    || dsdt_file->length < sizeof(acpi_header_t)
 	    || memcmp(dsdt_file->signature, "DSDT", 4) != 0) {
 		printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n");
-		cbfs_unmap(dsdt_file);
 		return current;
 	}
 
@@ -1916,7 +1808,6 @@ unsigned long write_acpi_tables(unsigned long start)
 		|| slic_file->length < sizeof(acpi_header_t)
 		|| (memcmp(slic_file->signature, "SLIC", 4) != 0
 		    && memcmp(slic_file->signature, "MSDM", 4) != 0))) {
-		cbfs_unmap(slic_file);
 		slic_file = 0;
 	}
 
@@ -2001,17 +1892,8 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += slic_file->length;
 		current = acpi_align_current(current);
 		acpi_add_table(rsdp, slic);
-		cbfs_unmap(slic_file);
 	}
 
-	/*
-	 * cbfs_unmap() uses mem_pool_free() which works correctly only
-	 * if freeing is done in reverse order than memory allocation.
-	 * This is why unmapping of dsdt_file must be done after
-	 * unmapping slic file.
-	 */
-	cbfs_unmap(dsdt_file);
-
 	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
 	ssdt = (acpi_header_t *)current;
 	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);

src/acpi/acpigen.c

@@ -388,48 +388,36 @@ void acpigen_set_package_element_namestr(const char *package, unsigned int eleme
 	acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */
 }
 
-void acpigen_write_processor_namestring(unsigned int cpu_index)
-{
-	char buffer[16];
-	snprintf(buffer, sizeof(buffer), "\\_SB." CONFIG_ACPI_CPU_STRING, cpu_index);
-	acpigen_emit_namestring(buffer);
-}
-
-/* Processor() operator is deprecated as of ACPI 6.0, use Device() instead. */
 void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
 {
 /*
 	Processor (\_SB.CPcpuindex, cpuindex, pblock_addr, pblock_len)
 	{
 */
+	char pscope[16];
 	acpigen_emit_ext_op(PROCESSOR_OP);
 	acpigen_write_len_f();
-	acpigen_write_processor_namestring(cpuindex);
+
+	snprintf(pscope, sizeof(pscope),
+		 CONFIG_ACPI_CPU_STRING, (unsigned int)cpuindex);
+	acpigen_emit_namestring(pscope);
 	acpigen_emit_byte(cpuindex);
 	acpigen_emit_dword(pblock_addr);
 	acpigen_emit_byte(pblock_len);
 }
 
-void acpigen_write_processor_device(unsigned int cpu_index)
-{
-	acpigen_emit_ext_op(DEVICE_OP);
-	acpigen_write_len_f();
-	acpigen_write_processor_namestring(cpu_index);
-	acpigen_write_name_string("_HID", "ACPI0007");
-	acpigen_write_name_integer("_UID", cpu_index);
-}
-
 void acpigen_write_processor_package(const char *const name, const unsigned int first_core,
 				     const unsigned int core_count)
 {
 	unsigned int i;
+	char pscope[16];
 
 	acpigen_write_name(name);
 	acpigen_write_package(core_count);
-
-	for (i = first_core; i < first_core + core_count; ++i)
-		acpigen_write_processor_namestring(i);
-
+	for (i = first_core; i < first_core + core_count; ++i) {
+		snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING, i);
+		acpigen_emit_namestring(pscope);
+	}
 	acpigen_pop_len();
 }
 
@@ -440,8 +428,10 @@ void acpigen_write_processor_cnot(const unsigned int number_of_cores)
 
 	acpigen_write_method("\\_SB.CNOT", 1);
 	for (core_id = 0; core_id < number_of_cores; core_id++) {
+		char buffer[DEVICE_PATH_MAX];
+		snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, core_id);
 		acpigen_emit_byte(NOTIFY_OP);
-		acpigen_write_processor_namestring(core_id);
+		acpigen_emit_namestring(buffer);
 		acpigen_emit_byte(ARG0_OP);
 	}
 	acpigen_pop_len();
@@ -711,7 +701,7 @@ void acpigen_write_empty_PCT(void)
 	acpigen_emit_stream(stream, ARRAY_SIZE(stream));
 }
 
-void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt)
+void acpigen_write_empty_PTC(void)
 {
 /*
 	Name (_PTC, Package (0x02)
@@ -719,35 +709,31 @@ void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt)
 		ResourceTemplate ()
 		{
 			Register (FFixedHW,
-				0x00,               // Duty Width
-				0x00,               // Duty Offset
-				0x0000000000000000, // P_CNT IO Address
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
 				,)
 		},
 
 		ResourceTemplate ()
 		{
 			Register (FFixedHW,
-				0x00,               // Duty Width
-				0x00,               // Duty Offset
-				0x0000000000000000, // P_CNT IO Address
+				0x00,               // Bit Width
+				0x00,               // Bit Offset
+				0x0000000000000000, // Address
 				,)
 		}
 	})
 */
 	acpi_addr_t addr = {
-		.bit_width   = duty_width,
-		.bit_offset  = duty_offset,
+		.space_id    = ACPI_ADDRESS_SPACE_FIXED,
+		.bit_width   = 0,
+		.bit_offset  = 0,
 		.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
-		.addrl       = p_cnt,
+		.addrl       = 0,
 		.addrh       = 0,
 	};
 
-	if (addr.addrl != 0)
-		addr.space_id = ACPI_ADDRESS_SPACE_IO;
-	else
-		addr.space_id = ACPI_ADDRESS_SPACE_FIXED;
-
 	acpigen_write_name("_PTC");
 	acpigen_write_package(2);
 
@@ -760,11 +746,6 @@ void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt)
 	acpigen_pop_len();
 }
 
-void acpigen_write_empty_PTC(void)
-{
-	acpigen_write_PTC(0, 0, 0);
-}
-
 static void __acpigen_write_method(const char *name, uint8_t flags)
 {
 	acpigen_emit_byte(METHOD_OP);
@@ -821,17 +802,6 @@ void acpigen_write_STA_ext(const char *namestring)
 	acpigen_pop_len();
 }
 
-void acpigen_write_BBN(uint8_t base_bus_number)
-{
-	/*
-	 * Method (_BBN, 0, NotSerialized) { Return (status) }
-	 */
-	acpigen_write_method("_BBN", 0);
-	acpigen_emit_byte(RETURN_OP);
-	acpigen_write_byte(base_bus_number);
-	acpigen_pop_len();
-}
-
 void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries)
 {
 	/*
@@ -1389,14 +1359,6 @@ void acpigen_write_store_int_to_namestr(uint64_t src, const char *dst)
 	acpigen_emit_namestring(dst);
 }
 
-/* Store ("namestr", dst) */
-void acpigen_write_store_namestr_to_op(const char *src, uint8_t dst)
-{
-	acpigen_write_store();
-	acpigen_emit_namestring(src);
-	acpigen_emit_byte(dst);
-}
-
 /* Store (src, dst) */
 void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst)
 {
@@ -1405,14 +1367,6 @@ void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst)
 	acpigen_emit_byte(dst);
 }
 
-/* Store ("namestr", "namestr") */
-void acpigen_write_store_namestr_to_namestr(const char *src, const char *dst)
-{
-	acpigen_write_store();
-	acpigen_emit_namestring(src);
-	acpigen_emit_namestring(dst);
-}
-
 /* Or (arg1, arg2, res) */
 void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res)
 {
@@ -1448,33 +1402,6 @@ void acpigen_write_not(uint8_t arg, uint8_t res)
 	acpigen_emit_byte(res);
 }
 
-/* Concatenate (str1, str2, res) */
-void acpigen_concatenate_string_string(const char *str1, const char *str2, uint8_t res)
-{
-	acpigen_emit_byte(CONCATENATE_OP);
-	acpigen_write_string(str1);
-	acpigen_write_string(str2);
-	acpigen_emit_byte(res);
-}
-
-/* Concatenate (str, val, tmp_res) */
-void acpigen_concatenate_string_int(const char *str, uint64_t val, uint8_t res)
-{
-	acpigen_emit_byte(CONCATENATE_OP);
-	acpigen_write_string(str);
-	acpigen_write_integer(val);
-	acpigen_emit_byte(res);
-}
-
-/* Concatenate (str, src_res, dest_res) */
-void acpigen_concatenate_string_op(const char *str, uint8_t src_res, uint8_t dest_res)
-{
-	acpigen_emit_byte(CONCATENATE_OP);
-	acpigen_write_string(str);
-	acpigen_emit_byte(src_res);
-	acpigen_emit_byte(dest_res);
-}
-
 /* Store (str, DEBUG) */
 void acpigen_write_debug_string(const char *str)
 {
@@ -1507,33 +1434,6 @@ void acpigen_write_debug_namestr(const char *str)
 	acpigen_emit_ext_op(DEBUG_OP);
 }
 
-/* Concatenate (str1, str2, tmp_res)
-   Store(tmp_res, DEBUG) */
-void acpigen_write_debug_concatenate_string_string(const char *str1, const char *str2,
-	uint8_t tmp_res)
-{
-	acpigen_concatenate_string_string(str1, str2, tmp_res);
-	acpigen_write_debug_op(tmp_res);
-}
-
-/* Concatenate (str1, val, tmp_res)
-   Store(tmp_res, DEBUG) */
-void acpigen_write_debug_concatenate_string_int(const char *str, uint64_t val,
-	uint8_t tmp_res)
-{
-	acpigen_concatenate_string_int(str, val, tmp_res);
-	acpigen_write_debug_op(tmp_res);
-}
-
-/* Concatenate (str1, res, tmp_res)
-   Store(tmp_res, DEBUG) */
-void acpigen_write_debug_concatenate_string_op(const char *str, uint8_t res,
-	uint8_t tmp_res)
-{
-	acpigen_concatenate_string_op(str, res, tmp_res);
-	acpigen_write_debug_op(tmp_res);
-}
-
 void acpigen_write_if(void)
 {
 	acpigen_emit_byte(IF_OP);
@@ -1563,20 +1463,6 @@ void acpigen_write_if_lequal_op_op(uint8_t op1, uint8_t op2)
 	acpigen_emit_byte(op2);
 }
 
-/*
- * Generates ACPI code for checking if operand1 is greater than operand2.
- * Both operand1 and operand2 are ACPI ops.
- *
- * If (Lgreater (op1 op2))
- */
-void acpigen_write_if_lgreater_op_op(uint8_t op1, uint8_t op2)
-{
-	acpigen_write_if();
-	acpigen_emit_byte(LGREATER_OP);
-	acpigen_emit_byte(op1);
-	acpigen_emit_byte(op2);
-}
-
 /*
  * Generates ACPI code for checking if operand1 and operand2 are equal, where,
  * operand1 is ACPI op and operand2 is an integer.
@@ -1591,20 +1477,6 @@ void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val)
 	acpigen_write_integer(val);
 }
 
-/*
- * Generates ACPI code for checking if operand is greater than the value, where,
- * operand is ACPI op and val is an integer.
- *
- * If (Lgreater (op, val))
- */
-void acpigen_write_if_lgreater_op_int(uint8_t op, uint64_t val)
-{
-	acpigen_write_if();
-	acpigen_emit_byte(LGREATER_OP);
-	acpigen_emit_byte(op);
-	acpigen_write_integer(val);
-}
-
 /*
  * Generates ACPI code for checking if operand1 and operand2 are equal, where,
  * operand1 is namestring and operand2 is an integer.
@@ -1619,20 +1491,6 @@ void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val)
 	acpigen_write_integer(val);
 }
 
-/*
- * Generates ACPI code for checking if operand1 and operand2 are equal, where,
- * operand1 is namestring and operand2 is an integer.
- *
- * If (Lgreater ("namestr", val))
- */
-void acpigen_write_if_lgreater_namestr_int(const char *namestr, uint64_t val)
-{
-	acpigen_write_if();
-	acpigen_emit_byte(LGREATER_OP);
-	acpigen_emit_namestring(namestr);
-	acpigen_write_integer(val);
-}
-
 /*
  * Generates ACPI code to check at runtime if an object named `namestring`
  * exists, and leaves the If scope open to continue execute code when this
@@ -1939,8 +1797,7 @@ void acpigen_write_CPPC_package(const struct cppc_config *config)
 void acpigen_write_CPPC_method(void)
 {
 	char pscope[16];
-	snprintf(pscope, sizeof(pscope),
-		 "\\_SB." CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0);
+	snprintf(pscope, sizeof(pscope), CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0);
 
 	acpigen_write_method("_CPC", 0);
 	acpigen_emit_byte(RETURN_OP);
@@ -2033,26 +1890,40 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_write_field(opreg.name, l, 2, FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
 
 	/* Store (Arg0, Local0) */
-	acpigen_write_store_ops(ARG0_OP, LOCAL0_OP);
+	acpigen_write_store();
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_emit_byte(LOCAL0_OP);
 
 	/* Store (Arg1, Local1) */
-	acpigen_write_store_ops(ARG1_OP, LOCAL1_OP);
+	acpigen_write_store();
+	acpigen_emit_byte(ARG1_OP);
+	acpigen_emit_byte(LOCAL1_OP);
 
 	/* ACPI SPEC requires to return at maximum 4KiB */
 	/* If (LGreater (Local1, 0x1000)) */
-	acpigen_write_if_lgreater_op_int(LOCAL1_OP, 0x1000);
+	acpigen_write_if();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_write_integer(0x1000);
 
 	/* Store (0x1000, Local1) */
-	acpigen_write_store_int_to_op(0x1000, LOCAL1_OP);
+	acpigen_write_store();
+	acpigen_write_integer(0x1000);
+	acpigen_emit_byte(LOCAL1_OP);
 
 	/* Pop if */
 	acpigen_pop_len();
 
 	/* Store (Local1, Local3) */
-	acpigen_write_store_ops(LOCAL1_OP, LOCAL3_OP);
+	acpigen_write_store();
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_emit_byte(LOCAL3_OP);
 
 	/* If (LGreater (Local0, length)) */
-	acpigen_write_if_lgreater_op_int(LOCAL0_OP, length);
+	acpigen_write_if();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_integer(length);
 
 	/* Return(Buffer(Local1){0}) */
 	acpigen_emit_byte(RETURN_OP);
@@ -2066,7 +1937,10 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_pop_len();
 
 	/* If (LGreater (Local0, length - 4096)) */
-	acpigen_write_if_lgreater_op_int(LOCAL0_OP, length - 4096);
+	acpigen_write_if();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_write_integer(length - 4096);
 
 	/* Subtract (length, Local0, Local2) */
 	acpigen_emit_byte(SUBTRACT_OP);
@@ -2075,10 +1949,15 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_emit_byte(LOCAL2_OP);
 
 	/* If (LGreater (Local1, Local2)) */
-	acpigen_write_if_lgreater_op_op(LOCAL1_OP, LOCAL2_OP);
+	acpigen_write_if();
+	acpigen_emit_byte(LGREATER_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_emit_byte(LOCAL2_OP);
 
 	/* Store (Local2, Local1) */
-	acpigen_write_store_ops(LOCAL2_OP, LOCAL1_OP);
+	acpigen_write_store();
+	acpigen_emit_byte(LOCAL2_OP);
+	acpigen_emit_byte(LOCAL1_OP);
 
 	/* Pop if */
 	acpigen_pop_len();
@@ -2114,7 +1993,9 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_emit_namestring("TMPB");
 
 	/* Store (TMPB, ROM1) */
-	acpigen_write_store_namestr_to_namestr("TMPB", "ROM1");
+	acpigen_write_store();
+	acpigen_emit_namestring("TMPB");
+	acpigen_emit_namestring("ROM1");
 
 	/* Return (ROM1) */
 	acpigen_emit_byte(RETURN_OP);
@@ -2167,7 +2048,6 @@ void acpigen_get_tx_gpio(const struct acpi_gpio *gpio)
 void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, u16 range_min,
 			   u16 range_max, u16 translation, u16 length)
 {
-	/* Byte 0: Type 1, Large Item Value 0x8: Word Address Space Descriptor */
 	acpigen_emit_byte(0x88);
 	/* Byte 1+2: length (0x000d) */
 	acpigen_emit_byte(0x0d);
@@ -2191,7 +2071,6 @@ void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran
 void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, u32 gran,
 			    u32 range_min, u32 range_max, u32 translation, u32 length)
 {
-	/* Byte 0: Type 1, Large Item Value 0x7: DWord Address Space Descriptor */
 	acpigen_emit_byte(0x87);
 	/* Byte 1+2: length (0023) */
 	acpigen_emit_byte(23);
@@ -2221,7 +2100,6 @@ static void acpigen_emit_qword(u64 data)
 void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran,
 			    u64 range_min, u64 range_max, u64 translation, u64 length)
 {
-	/* Byte 0: Type 1, Large Item Value 0xa: QWord Address Space Descriptor */
 	acpigen_emit_byte(0x8a);
 	/* Byte 1+2: length (0x002b) */
 	acpigen_emit_byte(0x2b);
@@ -2241,34 +2119,6 @@ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gra
 	acpigen_emit_qword(length);
 }
 
-void acpigen_resource_bus_number(u16 bus_base, u16 bus_limit)
-{
-	acpigen_resource_word(RSRC_TYPE_BUS, /* res_type */
-			      ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
-			      | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
-			      | ADDR_SPACE_GENERAL_FLAG_DEC_POS, /* gen_flags */
-			      BUS_NUM_RANGE_RESOURCE_FLAG, /* type_flags */
-			      0, /* gran */
-			      bus_base, /* range_min */
-			      bus_limit, /* range_max */
-			      0x0, /* translation */
-			      bus_limit - bus_base + 1); /* length */
-}
-
-void acpigen_resource_io(u16 io_base, u16 io_limit)
-{
-	acpigen_resource_word(RSRC_TYPE_IO, /* res_type */
-			      ADDR_SPACE_GENERAL_FLAG_MAX_FIXED
-			      | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED
-			      | ADDR_SPACE_GENERAL_FLAG_DEC_POS, /* gen_flags */
-			      IO_RSRC_FLAG_ENTIRE_RANGE, /* type_flags */
-			      0, /* gran */
-			      io_base, /* range_min */
-			      io_limit, /* range_max */
-			      0x0, /* translation */
-			      io_limit - io_base + 1); /* length */
-}
-
 void acpigen_write_ADR(uint64_t adr)
 {
 	acpigen_write_name_qword("_ADR", adr);
@@ -2407,17 +2257,3 @@ void acpigen_write_delay_until_namestr_int(uint32_t wait_ms, const char *name, u
 	acpigen_emit_byte(LOCAL7_OP);
 	acpigen_pop_len(); /* While */
 }
-
-void acpigen_ssdt_override_sleep_states(bool enable_s1, bool enable_s2, bool enable_s3,
-					bool enable_s4)
-{
-	assert(!(enable_s1 && CONFIG(ACPI_S1_NOT_SUPPORTED)));
-	assert(!(enable_s3 && !CONFIG(HAVE_ACPI_RESUME)));
-	assert(!(enable_s4 && CONFIG(DISABLE_ACPI_HIBERNATE)));
-
-	acpigen_write_scope("\\");
-	uint32_t sleep_enable = (enable_s1 << 0) | (enable_s2 << 1)
-		| (enable_s3 << 2) | (enable_s4 << 3);
-	acpigen_write_name_dword("OSFG", sleep_enable);
-	acpigen_pop_len();
-}

src/acpi/acpigen_dptf.c

@@ -62,8 +62,6 @@ static const char *namestring_of(enum dptf_participant participant)
 		return "TCHG";
 	case DPTF_FAN:
 		return "TFN1";
-	case DPTF_FAN_2:
-		return "TFN2";
 	case DPTF_TEMP_SENSOR_0:
 		return "TSR0";
 	case DPTF_TEMP_SENSOR_1:
@@ -125,7 +123,7 @@ void dptf_write_scope(enum dptf_participant participant)
  * are used to increase the speed of the fan in order to speed up cooling.
  */
 static void write_active_relationship_table(const struct dptf_active_policy *policies,
-					    int max_count, bool dptf_multifan_support)
+					    int max_count)
 {
 	char *pkg_count;
 	int i, j;
@@ -156,11 +154,7 @@ static void write_active_relationship_table(const struct dptf_active_policy *pol
 
 		/* Source, Target, Percent, Fan % for each of _AC0 ... _AC9 */
 		acpigen_write_package(13);
-		if (dptf_multifan_support)
-			acpigen_emit_namestring(path_of(policies[i].source));
-		else
-			acpigen_emit_namestring(path_of(DPTF_FAN));
-
+		acpigen_emit_namestring(path_of(DPTF_FAN));
 		acpigen_emit_namestring(path_of(policies[i].target));
 		acpigen_write_integer(DEFAULT_IF_0(policies[i].weight, DEFAULT_WEIGHT));
 
@@ -211,10 +205,9 @@ static void write_active_cooling_methods(const struct dptf_active_policy *polici
 	}
 }
 
-void dptf_write_active_policies(const struct dptf_active_policy *policies,
-		int max_count, bool dptf_multifan_support)
+void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count)
 {
-	write_active_relationship_table(policies, max_count, dptf_multifan_support);
+	write_active_relationship_table(policies, max_count);
 	write_active_cooling_methods(policies, max_count);
 }
 
@@ -359,29 +352,7 @@ void dptf_write_charger_perf(const struct dptf_charger_perf *states, int max_cou
 	acpigen_pop_len(); /* Scope */
 }
 
-int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed,
-		uint16_t noise_level)
-{
-	/*
-	 * Some _FPS tables do include a last entry where Percent is 0, but Power is
-	 * called out, so this table is finished when both are zero.
-	 */
-	if (!percent && !power)
-		return 1;
-
-	acpigen_write_package(5);
-	acpigen_write_integer(percent);
-	acpigen_write_integer(DEFAULT_TRIP_POINT);
-	acpigen_write_integer(speed);
-	acpigen_write_integer(noise_level);
-	acpigen_write_integer(power);
-	acpigen_pop_len(); /* inner Package */
-
-	return 0;
-}
-
-void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
-						enum dptf_participant participant)
+void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count)
 {
 	char *pkg_count;
 	int i;
@@ -389,49 +360,29 @@ void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count,
 	if (!max_count || !states[0].percent)
 		return;
 
-	dptf_write_scope(participant);
+	dptf_write_scope(DPTF_FAN);
 
 	/* _FPS - Fan Performance States */
 	acpigen_write_name("_FPS");
-
 	pkg_count = acpigen_write_package(1); /* 1 for Revision */
 	acpigen_write_integer(FPS_REVISION); /* revision */
 
 	for (i = 0; i < max_count; ++i) {
-		(*pkg_count)++;
-		if (dptf_write_fan_perf_fps(states[i].percent, states[i].power,
-			states[i].speed, states[i].noise_level))
+		/*
+		 * Some _FPS tables do include a last entry where Percent is 0, but Power is
+		 * called out, so this table is finished when both are zero.
+		 */
+		if (!states[i].percent && !states[i].power)
 			break;
-	}
 
-	acpigen_pop_len(); /* Package */
-	acpigen_pop_len(); /* Scope */
-}
-
-void dptf_write_multifan_perf(
-		const struct dptf_multifan_perf
-			states[DPTF_MAX_FAN_PARTICIPANTS][DPTF_MAX_FAN_PERF_STATES],
-		int max_count, enum dptf_participant participant, int fan_num)
-{
-	char *pkg_count;
-	int i;
-
-	if (!max_count || !states[fan_num][0].percent)
-		return;
-
-	dptf_write_scope(participant);
-
-	/* _FPS - Fan Performance States */
-	acpigen_write_name("_FPS");
-
-	pkg_count = acpigen_write_package(1); /* 1 for Revision */
-	acpigen_write_integer(FPS_REVISION); /* revision */
-
-	for (i = 0; i < max_count; ++i) {
 		(*pkg_count)++;
-		if (dptf_write_fan_perf_fps(states[fan_num][i].percent, states[fan_num][i].power,
-				states[fan_num][i].speed, states[fan_num][i].noise_level))
-			break;
+		acpigen_write_package(5);
+		acpigen_write_integer(states[i].percent);
+		acpigen_write_integer(DEFAULT_TRIP_POINT);
+		acpigen_write_integer(states[i].speed);
+		acpigen_write_integer(states[i].noise_level);
+		acpigen_write_integer(states[i].power);
+		acpigen_pop_len(); /* inner Package */
 	}
 
 	acpigen_pop_len(); /* Package */
@@ -449,8 +400,6 @@ void dptf_write_power_limits(const struct dptf_power_limits *limits)
 	dptf_write_scope(DPTF_CPU);
 	acpigen_write_method("PPCC", 0);
 
-	acpigen_emit_byte(RETURN_OP);
-
 	pkg_count = acpigen_write_package(1); /* 1 for the Revision */
 	acpigen_write_integer(PPCC_REVISION); /* revision */
 

src/arch/arm/include/armv7/arch/cache.h

@@ -192,7 +192,7 @@ static inline uint32_t read_clidr(void)
 	return val;
 }
 
-/* read cache size ID register (CCSIDR) */
+/* read cache size ID register register (CCSIDR) */
 static inline uint32_t read_ccsidr(void)
 {
 	uint32_t val = 0;

src/arch/arm64/armv8/mmu.c

@@ -35,8 +35,8 @@ static uint64_t get_block_attr(unsigned long tag)
 {
 	uint64_t attr;
 
-	attr = (tag & MA_NS) ? BLOCK_NS : 0;
-	attr |= (tag & MA_RO) ? BLOCK_AP_RO : BLOCK_AP_RW;
+	attr = (tag & MA_NS)? BLOCK_NS : 0;
+	attr |= (tag & MA_RO)? BLOCK_AP_RO : BLOCK_AP_RW;
 	attr |= BLOCK_ACCESS;
 
 	if (tag & MA_MEM) {

src/arch/arm64/include/armv8/arch/barrier.h

@@ -21,7 +21,7 @@
 #define wmb()		asm volatile("dsb st" : : : "memory")
 
 #if CONFIG(SMP)
-#define barrier() __asm__ __volatile__("" : : : "memory")
+#define barrier() __asm__ __volatile__("": : :"memory")
 #endif
 
 #define nop()		asm volatile("nop");

src/arch/ppc64/Makefile.inc

@@ -12,6 +12,7 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y)
 bootblock-y = bootblock_crt0.S
 bootblock-y += arch_timer.c
 bootblock-y += boot.c
+bootblock-y += rom_media.c
 bootblock-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -37,6 +38,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y)
 romstage-y += arch_timer.c
 romstage-y += boot.c
 romstage-y += stages.c
+romstage-y += rom_media.c
 romstage-y += \
 	$(top)/src/lib/memchr.c \
 	$(top)/src/lib/memcmp.c \
@@ -62,6 +64,7 @@ endif
 ################################################################################
 ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)
 
+ramstage-y += rom_media.c
 ramstage-y += stages.c
 ramstage-y += arch_timer.c
 ramstage-y += boot.c

src/arch/riscv/Makefile.inc

@@ -25,21 +25,15 @@ endif
 # suffixes in ARCH_SUFFIX_riscv.
 simple_riscv_flags = $(riscv_flags)
 
-ifeq ($(CONFIG_COMPILER_GCC),y)
-MARCH_SUFFIX=$(ARCH_SUFFIX_riscv)
-else
-MARCH_SUFFIX=
-endif
-
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
-riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
+riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 else
 riscv_flags += $(_rv_flags)
 simple_riscv_flags += $(_rv_flags)
 endif
 
-riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(MARCH_SUFFIX) -mabi=$(CONFIG_RISCV_ABI)
+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI)
 
 COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name)
 

src/arch/riscv/trap_handler.c

@@ -150,7 +150,7 @@ void trap_handler(trapframe *tf)
 /* This function used to redirect trap to s-mode. */
 void redirect_trap(void)
 {
-	write_csr(stval, read_csr(mtval));
+	write_csr(sbadaddr, read_csr(mbadaddr));
 	write_csr(sepc, read_csr(mepc));
 	write_csr(scause, read_csr(mcause));
 	write_csr(mepc, read_csr(stvec));

src/arch/riscv/trap_util.S

@@ -80,7 +80,7 @@
   csrrw  t0,mscratch,x0
   csrr   s0,mstatus
   csrr   t1,mepc
-  csrr   t2,mtval
+  csrr   t2,mbadaddr
   csrr   t3,mcause
   STORE  t0,2*REGBYTES(x2)
   STORE  s0,32*REGBYTES(x2)
@@ -110,7 +110,7 @@ trap_entry:
 .Lsmp_hang:
   bnez sp, .Lsmp_hang
 
-  # Use a different stack than in the main context, to avoid overwriting
+  # Use a different stack than in the main context, to to avoid overwriting
   # stack data.
   # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if
   # the previous mode was M, because it would be a very bad idea to use a stack

src/arch/x86/Makefile.inc

@@ -112,10 +112,8 @@ add_bootblock = \
 	$(cbfs-autogen-attributes) $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
 endif
 
-ifneq ($(CONFIG_CBFS_VERIFICATION),y)
 $(call src-to-obj,bootblock,$(dir)/walkcbfs.S): $(obj)/fmap_config.h
 bootblock-y += walkcbfs.S
-endif
 
 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
 

src/arch/x86/acpi.c

@@ -2,8 +2,6 @@
 
 #include <acpi/acpi.h>
 #include <cf9_reset.h>
-#include <cpu/x86/smm.h>
-#include <pc80/mc146818rtc.h>
 
 void arch_fill_fadt(acpi_fadt_t *fadt)
 {
@@ -19,20 +17,4 @@ void arch_fill_fadt(acpi_fadt_t *fadt)
 
 		fadt->flags |= ACPI_FADT_RESET_REGISTER;
 	}
-
-	if (permanent_smi_handler()) {
-		fadt->smi_cmd = APM_CNT;
-		fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-		fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	}
-
-	if (CONFIG(PC80_SYSTEM)) {
-		/* Currently these are defined to support date alarm only. */
-		fadt->day_alrm = RTC_DATE_ALARM;
-		fadt->mon_alrm = RTC_MONTH_ALARM;
-	}
-
-	/* Careful with USE_OPTION_TABLE. */
-	if (CONFIG(USE_PC_CMOS_ALTCENTURY))
-		fadt->century = RTC_CLK_ALTCENTURY;
 }

src/arch/x86/car.ld

@@ -140,7 +140,7 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
 _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
 #endif
 _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
-#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE)
+#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE)
 _bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
 _bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
 #endif

src/arch/x86/cpu.c

@@ -196,7 +196,7 @@ struct cpu_driver *find_cpu_driver(struct device *cpu)
 		for (id = driver->id_table;
 		     id->vendor != X86_VENDOR_INVALID; id++) {
 			if ((cpu->vendor == id->vendor) &&
-			    cpuid_match(cpu->device, id->device, id->device_match_mask))
+				(cpu->device == id->device))
 				return driver;
 			if (id->vendor == X86_VENDOR_ANY)
 				return driver;
@@ -211,6 +211,24 @@ static void set_cpu_ops(struct device *cpu)
 	cpu->ops = driver ? driver->ops : NULL;
 }
 
+/* Keep track of default APIC ids for SMM. */
+static int cpus_default_apic_id[CONFIG_MAX_CPUS];
+
+/* Function to keep track of cpu default apic_id */
+void cpu_add_map_entry(unsigned int index)
+{
+	cpus_default_apic_id[index] = initial_lapicid();
+}
+
+/* Returns default APIC id based on logical_cpu number or < 0 on failure. */
+int cpu_get_apic_id(int logical_cpu)
+{
+	if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0)
+		return -1;
+
+	return cpus_default_apic_id[logical_cpu];
+}
+
 void cpu_initialize(void)
 {
 	/* Because we busy wait at the printk spinlock.