mb/system76/rpl: darp9: Add SSD RTD3 configs

Some drives block the CPU from reaching C10 on suspend without the RTD3
config.

Fixes suspend with the following drives:

- Kingston KC3000 (SKC3000D/4096G)
- Kingston HyperX (SHPM2280P2H/240G)
- Solidigm P44 Pro (SSDPFKKW010X7)

The following drives continue to work:

- Samsung 970 Evo (MZVLB250HAHQ)
- WD Black SN770 (WDS250G3X0E)
- WD Green SN350 (WDS240G2G0C-00AJM0)
- WD Blue SN570 (WDS100T3B0C)

Change-Id: I205d78377fa2b0db8d37542cdb94ba86ded1d66e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>

.gitmodules

@@ -1,67 +1,67 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk

Documentation/mainboard/index.md

@@ -207,12 +207,16 @@ The boards in this section are not real mainboards, but emulators.
 - [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
+- [Lemur Pro 11](system76/lemp11.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
+- [Oryx Pro 9](system76/oryp9.md)
+- [Oryx Pro 10](system76/oryp10.md)
 
 ## Texas Instruments
 

Documentation/mainboard/system76/gaze17.md

@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+  - Intel Core i5-12500H
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3050
+    - NVIDIA GeForce RTX 3050 Ti
+    - NVIDIA GeForce RTX 3060
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+  - Gigabit Ethernet
+    - 3050: Realtek RTL8111H controller
+    - 3060: Onboard Intel I219-V
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX201
+- Power
+  - 3050: 150W (20V, 7.5A) AC barrel adapter
+  - 3060: 180W (20V, 9A) AC barrel adapter
+      - Lite-On PA-1181-76, using a C5 power cord
+  - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone/microphone jack
+  - Dedicated 3.5mm microphone jack
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | GigaDevice          |
++---------------------+---------------------+
+| Model               | GD25B256E           |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.

Documentation/mainboard/system76/lemp11.md

@@ -0,0 +1,62 @@
+# System76 Lemur Pro 11 (lemp11)
+
+## Specs
+
+- CPU
+  - Intel Core i5-1235U
+  - Intel Core i7-1255U
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - Intel Iris Xe Graphics
+  - eDP 14.0" 1920x1080@60Hz LCD
+  - 1x HDMI 2.1
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Channel 0: 8-GB on-board DDR4 (Samsung K4AAG165WA-BCWE)
+  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM @ 3200 MHz
+- Networking
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 65W (19V, 3.42A) AC barrel adapter (AcBel ADA012)
+  - USB-C charging, compatible with 65W+ chargers
+  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
+- Sound
+  - Realtek ALC256 codec
+  - Internal speakers and microphone
+  - Combined 3.5 mm headphone/microphone jack
+  - HDMI, USB-C DisplayPort audio
+- Storage
+  - M.2 PCIe NVMe Gen 4 SSD
+  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-A
+  - 1x USB 3.2 (Gen 1) Type-A
+- Dimensions
+    - 1.65cm x 32.2cm x 21.68cm, 1.15kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp10.md

@@ -0,0 +1,69 @@
+# System76 Oryx Pro 10 (oryp10)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options:
+    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
+    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
+  - eDP options:
+    - 15.6" 3840x2160@60Hz OLED (Samsung ATNA56WR14-0)
+    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
+    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
+  - 80Wh 6-cell Lithium-ion battery
+- Sound
+  - Realtek ALC1220 codec
+  - Realtek ALC1306 smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 2x M.2 PCIe NVMe Gen 4 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 2x USB 3.2 (Gen 1) Type-A
+- Dimensions
+  - 15": 35.814cm x 24.003cm x 2.489cm, 2.4kg
+  - 17": 39.599cm x 26.213cm x 2.489cm, 2.8kg
+
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.

Documentation/mainboard/system76/oryp9.md

@@ -0,0 +1,67 @@
+# System76 Oryx Pro 9 (oryp9)
+
+## Specs
+
+- CPU
+  - Intel Core i7-12700H
+- EC
+  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options:
+    - NVIDIA GeForce RTX 3070 Ti (Max-Q)
+    - NVIDIA GeForce RTX 3080 Ti (Max-Q)
+  - eDP options:
+    - 15.6" 1920x1080@144Hz LCD (BOE NV156FHM-NY5)
+    - 17.3" 1920x1080@144Hz LCD (BOE NV173FHM-NY1)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
+- Power
+  - 230W (20V, 11.5A)  AC barrel adapter (Lite-On PA-1231-26)
+  - 80Wh 6-cell Lithium-ion battery
+- Sound
+  - Realtek ALC1220 codec
+  - TI TAS5825M smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 2x M.2 PCIe NVMe Gen 4 SSD
+  - MicroSD card reader (RTS5227S)
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 1x USB 3.2 (Gen 2) Type-C
+  - 2x USB 3.2 (Gen 1) Type-A
+- Dimensions
+  - 15": 35.814cm x 24.003cm x 2.489cm, 1.99kg
+  - 17": 39.599cm x 26.213cm x 2.489cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type                | Value               |
++=====================+=====================+
+| Socketed flash      | no                  |
++---------------------+---------------------+
+| Vendor              | Macronix            |
++---------------------+---------------------+
+| Model               | MX25L25673G         |
++---------------------+---------------------+
+| Size                | 32 MiB              |
++---------------------+---------------------+
+| Package             | WSON-8              |
++---------------------+---------------------+
+| Internal flashing   | yes                 |
++---------------------+---------------------+
+| External flashing   | yes                 |
++---------------------+---------------------+
+```
+
+The flash chip (U61) is left of the DIMM slots.

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,38 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	depends on DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Dynamic Boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	int "Total processor power offset from default TGP in watts"
+	default 45
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This identifies the available power for the CPU or GPU boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
+	int "Minimum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the GPU to the CPU
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	int "Maximum TGP offset from default TGP in watts"
+	default 0
+	depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	help
+	  This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+	PVID,   16,
+	PDID,   16,
+
+	Offset (0x248),
+		,   7,
+	L23E,   1,      /* L23_Rdy Entry Request */
+	L23R,   1,      /* L23_Rdy to Detect Transition */
+
+	Offset (0xC20),
+		,   4,
+	P0AP,   2,      /* Additional power savings */
+
+	Offset (0xC38),
+		,   3,
+	P0RM,   1,      /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 1
+	P0AP = 3
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	L23R = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23R) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+
+	P0RM = 0
+	P0AP = 0
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (JT_DSM_GUID)) {
+		If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+			Return (NVJT(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported JT revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
+		If (ToInteger(Arg1) == GPS_REVISION_ID) {
+			Return (GPS(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+	Printf("  GPU GPS")
+	Switch(ToInteger(Arg0)) {
+		Case(GPS_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS)
+			))
+		}
+		Case(GPS_FUNC_PSHARESTATUS) {
+			Printf("    Power Share Status")
+			Return(ITOB(0))
+		}
+		Case(GPS_FUNC_PSHAREPARAMS) {
+			Printf("    Power Share Parameters")
+
+			CreateField(Arg1, 0, 4, QTYP) // Query type
+
+			Name(GPSP, Buffer(36) { 0x00 })
+			CreateDWordField(GPSP, 0, RSTS) // Response status
+			CreateDWordField(GPSP, 4, VERS) // Version
+
+			// Set query type of response
+			RSTS = QTYP
+			// Set version of response
+			VERS = 0x00010000
+
+			Switch(ToInteger(QTYP)) {
+				Case(0) {
+					Printf("      Request Current Information")
+					// No required information
+					Return(GPSP)
+				}
+				Case(1) {
+					Printf("      Request Supported Fields")
+					// Support GPU temperature field
+					RSTS |= (1 << 8)
+					Return(GPSP)
+				}
+				Case(2) {
+					Printf("      Request Current Limits")
+					// No required limits
+					Return(GPSP)
+				}
+				Default {
+					Printf("      Unknown Query: %o", SFST(QTYP))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+	#include "power.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+	Device(NPCF) {
+		#include "utility.asl"
+		#include "nvpcf.asl"
+	}
+}
+#endif

src/drivers/gfx/nvidia/acpi/common/nvjt.asl

@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID_MIN 0x00000100
+#define JT_REVISION_ID_MAX 0x00000200
+#define JT_FUNC_SUPPORT 0x00000000
+#define JT_FUNC_CAPS 0x00000001
+#define JT_FUNC_POWERCONTROL 0x00000003
+
+//TODO: SMI traps and EGIN/XCLM
+#define JT_GPC_GSS 0 // Get current GPU GCx sleep status
+#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh
+#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh
+#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh
+#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update
+
+#define JT_DFGC_NONE 0 // Handle request immediately
+#define JT_DFGC_DEFER 1 // Defer GPC and GPCX
+//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests
+
+// Deferred GC6 enter/exit until D3-cold (saved DFGC)
+Name(DFEN, 0)
+
+// Deferred GC6 enter control (saved GPC)
+Name(DFCI, 0)
+
+// Deferred GC6 exit control (saved GPCX)
+Name(DFCO, 0)
+
+Method (NVJT, 2, Serialized) {
+	Printf("  GPU NVJT")
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << JT_FUNC_SUPPORT) |
+				(1 << JT_FUNC_CAPS) |
+				(1 << JT_FUNC_POWERCONTROL)
+			))
+		}
+		Case (JT_FUNC_CAPS) {
+			Printf("    Capabilities")
+			Return(ITOB(
+				(1 << 0) | // G-SYNC NSVR power-saving features are enabled
+				(1 << 1) | // NVSR disabled
+				(2 << 3) | // Panel power and backlight are on the suspend rail
+				(0 << 5) | // self-refresh controller remains powered while panel is powered
+				(0 << 6) | // FB is not on the suspend rail but is powered on in GC6
+				(0 << 8) | // Combined power rail for all GPUs
+				(0 << 10) | // External SPI ROM
+				(1 << 11) | // No SMI handler for kernel panic exit while in GC6
+				(0 << 12) | // Supports notify on GC6 state done
+				(1 << 13) | // Support deferred GC6
+				(1 << 14) | // Support fine-grained root port control
+				(2 << 15) | // GC6 version is GC6-R
+				(0 << 17) | // GC6 exit ISR is not supported
+				(0 << 18) | // GC6 self wakeup not supported
+				(JT_REVISION_ID_MAX << 20) // Highest revision supported
+			))
+		}
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("    Power Control: %o", SFST(Arg1))
+
+			CreateField (Arg1, 0, 3, GPC) // GPU power control
+			CreateField (Arg1, 4, 1, PPC) // Panel power control
+			CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold
+			CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control
+
+			// Save deferred GC6 request
+			If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) {
+				DFEN = DFGC
+				DFCI = GPC
+				DFCO = GPCX
+			}
+
+			// Buffer to cache current state
+			Name (JTBF, Buffer (4) { 0, 0, 0, 0 })
+			CreateField (JTBF, 0, 3, CGCS) // Current GC state
+			CreateField (JTBF, 3, 1, CGPS) // Current GPU power status
+			CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on)
+
+			// If doing deferred GC6 request, return now
+			If (ToInteger(DFGC) != 0) {
+				CGCS = 1
+				CGPS = 1
+				Return (JTBF)
+			}
+
+			// Apply requested state
+			Switch (ToInteger(GPC)) {
+				Case (JT_GPC_GSS) {
+					Printf("    Get current GPU GCx sleep status")
+					//TODO: include transitions!
+					If (GTXS(DGPU_RST_N)) {
+						// GPU powered on
+						CGCS = 1
+						CGPS = 1
+					} ElseIf (GTXS(DGPU_PWR_EN)) {
+						// GPU powered off, GC6
+						CGCS = 3
+						CGPS = 0
+					} Else {
+						// GPU powered off, D3 cold
+						CGCS = 2
+						CGPS = 0
+					}
+				}
+				Case (JT_GPC_EGNS) {
+					Printf("    Enter GC6 without self-refresh")
+					GC6I()
+					CPSS = 1
+				}
+				Case (JT_GPC_EGIS) {
+					Printf("    Enter GC6 with self-refresh")
+					GC6I()
+					If (ToInteger(PPC) == 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGXS) {
+					Printf("    Exit GC6 and stop self-refresh")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Case (JT_GPC_XGIS) {
+					Printf("    Exit GC6 for self-refresh update")
+					GC6O()
+
+					CGCS = 1
+					CGPS = 1
+					If (ToInteger(PPC) != 0) {
+						CPSS = 0
+					}
+				}
+				Default {
+					Printf("    Unsupported GPU power control: %o", SFST(GPC))
+				}
+			}
+
+			Return (JTBF)
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/nvpcf.asl

@@ -0,0 +1,111 @@
+#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
+#define NVPCF_REVISION_ID 0x00000200
+#define NVPCF_ERROR_SUCCESS 0x0
+#define NVPCF_ERROR_GENERIC 0x80000001
+#define NVPCF_ERROR_UNSUPPORTED 0x80000002
+#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
+#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
+#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
+
+Name(_HID, "NVDA0820")
+
+Name(_UID, "NPCF")
+
+Method(_DSM, 4, Serialized) {
+	Printf("NVPCF _DSM")
+	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
+		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
+			Return(NPCF(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
+			Return(NVPCF_ERROR_GENERIC)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return(NVPCF_ERROR_GENERIC)
+	}
+}
+
+Method(NPCF, 2, Serialized) {
+	Printf("  NVPCF NPCF")
+	Switch(ToInteger(Arg0)) {
+		Case(NVPCF_FUNC_GET_SUPPORTED) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << NVPCF_FUNC_GET_SUPPORTED) |
+				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
+				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
+			))
+		}
+		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
+			Printf("    Get Static Config")
+			Return(Buffer(14) {
+				// Device table header
+				0x20, 0x03, 0x01,
+				// Intel + NVIDIA
+				0x00,
+				// Controller table header
+				0x23, 0x04, 0x05, 0x01,
+				// Dynamic boost controller
+				0x01,
+				// Supports DC
+				0x01,
+				// Reserved
+				0x00, 0x00, 0x00,
+				// Checksum
+				0xAD
+			})
+		}
+		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
+			Printf("    Update Dynamic Boost")
+
+			CreateField(Arg1, 0x28, 2, ICMD) // Input command
+
+			Name(PCFP, Buffer(49) {
+				// Table version
+				0x23,
+				// Table header size
+				0x05,
+				// Size of common status in bytes
+				0x10,
+				// Size of controller entry in bytes
+				0x1C,
+				// Other fields filled in later
+			})
+			CreateByteField(PCFP, 0x04, CCNT) // Controller count
+			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
+			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
+			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
+
+			Switch(ToInteger(ICMD)) {
+				Case(0) {
+					Printf("      Get Controller Params")
+					// Number of controllers
+					CCNT = 1
+					// AC total processor power offset from default TGP in 1/8 watt units
+					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
+					// AC maximum TGP offset from default TGP in 1/8 watt units
+					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
+					// AC minimum TGP offset from default TGP in 1/8 watt units
+					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Case(1) {
+					Printf("      Set Controller Status")
+					//TODO
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Default {
+					Printf("      Unknown Input Command: %o", SFST(ICMD))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NVPCF_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/drivers/gfx/nvidia/acpi/common/power.asl

@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: evaluate sleeps
+
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+Field (PCIC, DwordAcc, NoLock, Preserve) {
+	Offset (0x40),
+	SSID, 32, // Subsystem vendor and product ID
+}
+
+// Enter GC6
+Method(GC6I, 0, Serialized) {
+	Printf("    GPU GC6I START")
+
+	// Enter L23
+	^^DL23()
+	Sleep(5)
+
+	// Put GPU into reset
+	Printf("      Put GPU into reset")
+	CTXS(DGPU_RST_N)
+	Sleep(5)
+
+	Printf("    GPU GC6I FINISH")
+}
+
+// Exit GC6
+Method(GC6O, 0, Serialized) {
+	Printf("    GPU GC6O START")
+
+	// Bring GPU out of reset
+	Printf("      Bring GPU out of reset")
+	STXS(DGPU_RST_N)
+	Sleep(5)
+
+	// Exit L23
+	^^L23D()
+	Sleep(5)
+
+	Printf("    GPU GC6O FINISH")
+}
+
+Method (_ON, 0, Serialized) {
+	Printf("  GPU _ON START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCO)) {
+			Case (JT_GPC_XGXS) {
+				Printf("    Exit GC6 and stop self-refresh")
+				GC6O()
+			}
+			Default {
+				Printf("    Unsupported DFCO: %o", SFST(DFCO))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power on")
+		STXS(DGPU_PWR_EN)
+		Sleep(5)
+		GC6O()
+	}
+
+	Printf("  GPU _ON FINISH")
+}
+
+Method (_OFF, 0, Serialized) {
+	Printf("  GPU _OFF START")
+
+	If (DFEN == JT_DFGC_DEFER) {
+		Switch (ToInteger(DFCI)) {
+			Case (JT_GPC_EGNS) {
+				Printf("    Enter GC6 without self-refresh")
+				GC6I()
+			}
+			Case (JT_GPC_EGIS) {
+				Printf("    Enter GC6 with self-refresh")
+				GC6I()
+			}
+			Default {
+				Printf("    Unsupported DFCI: %o", SFST(DFCI))
+			}
+		}
+		DFEN = JT_DFGC_NONE
+	} Else {
+		Printf("    Standard RTD3 power off")
+		GC6I()
+		CTXS(DGPU_PWR_EN)
+		Sleep(5)
+	}
+
+	Printf("  GPU _OFF FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PWRR._ON")
+
+		// Restore SSID
+		^^SSID = DGPU_SSID
+		Printf("  Restore SSID: %o", SFST(^^SSID))
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PWRR._OFF")
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })

src/drivers/gfx/nvidia/acpi/common/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/drivers/gfx/nvidia/acpi/tigerlake.asl

@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */
+
+// Port mapped PCI express config space
+OperationRegion (PCIC, PCI_Config, 0x00, 0xFF)
+
+Field (PCIC, AnyAcc, NoLock, Preserve) {
+	Offset(0x52),  /* LSTS - Link Status Register */
+	, 13,
+	LASX, 1,       /* 0, Link Active Status */
+
+	Offset(0x60),  /* RSTS - Root Status Register */
+	, 16,
+	PSPX, 1,       /* 16,  PME Status */
+
+	Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+	, 30,
+	HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+	PMEX, 1,       /* 31,  Power Management SCI Enable */
+
+	Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */
+	SCB0, 1,       /* Scratch bit 0 */
+
+	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	, 2,
+	L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+	L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+}
+
+Field (PCIC, AnyAcc, NoLock, WriteAsZeros) {
+	Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+	, 30,
+	HPSX, 1,       /* 30,  Hot Plug SCI Status */
+	PMSX, 1        /* 31,  Power Management SCI Status */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+	Printf("      GPU PORT DL23 START")
+
+	L23E = 1
+	Sleep (16)
+	Local0 = 0
+	While (L23E) {
+		If ((Local0 > 4)) {
+			Break
+		}
+
+		Sleep (16)
+		Local0++
+	}
+	SCB0 = 1
+
+	Printf("      GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+	Printf("      GPU PORT L23D START")
+
+	If ((SCB0 == 1)) {
+		L23R = 1
+		Local0 = 0
+		While (L23R) {
+			If ((Local0 > 4)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+
+		SCB0 = 0
+		Local0 = 0
+		While ((LASX == 0)) {
+			If ((Local0 > 8)) {
+				Break
+			}
+			Sleep (16)
+			Local0++
+		}
+	}
+
+	Printf("      GPU PORT L23D FINISH")
+}
+
+Method (HPME, 0, Serialized) {
+	Printf("  GPU PORT HPME START")
+
+	If (PMSX == 1) {
+		Printf("    Notify GPU driver of PME SCI")
+		Notify(DEV0, 0x2)
+		Printf("    Clear PME SCI")
+		PMSX = 1
+		Printf("    Consume PME notification")
+		PSPX = 1
+	}
+
+	Printf("  GPU PORT HPME FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+	Name (_STA, 1)
+
+	Method (_ON, 0, Serialized) {
+		Printf("GPU PORT PWRR._ON")
+
+		HPME();
+		If (PMEX == 1) {
+			Printf("  Disable power management SCI")
+			PMEX = 0
+		}
+
+		^^DEV0._ON()
+
+		_STA = 1
+	}
+
+	Method (_OFF, 0, Serialized) {
+		Printf("GPU PORT PWRR._OFF")
+
+		^^DEV0._OFF()
+
+		If (PMEX == 0) {
+			Printf("  Enable power management SCI")
+			PMEX = 1
+			HPME()
+		}
+
+		_STA = 0
+	}
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus Graphics Device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(10);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(25);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(10);
+}

src/drivers/intel/dtbt/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_INTEL_DTBT
+	bool
+	default n
+	help
+	  Support for discrete Thunderbolt controllers

src/drivers/intel/dtbt/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c

src/drivers/intel/dtbt/chip.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
+#define _DRIVERS_INTEL_DTBT_CHIP_H_
+
+struct drivers_intel_dtbt_config {};
+
+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */

src/drivers/intel/dtbt/dtbt.c

@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <acpi/acpigen.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+
+#define PCIE2TBT 0x54C
+#define PCIE2TBT_GO2SX ((0x02 << 1) | 1)
+#define PCIE2TBT_GO2SX_NO_WAKE ((0x03 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED ((0x04 << 1) | 1)
+#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED ((0x05 << 1) | 1)
+#define PCIE2TBT_SET_SECURITY_LEVEL ((0x08 << 1) | 1)
+#define PCIE2TBT_GET_SECURITY_LEVEL ((0x09 << 1) | 1)
+#define PCIE2TBT_BOOT_ON ((0x18 << 1) | 1)
+#define TBT2PCIE 0x548
+
+static void dtbt_cmd(struct device *dev, u32 command) {
+	printk(BIOS_INFO, "DTBT send command %08x\n", command);
+
+	pci_write_config32(dev, PCIE2TBT, command);
+
+	u32 timeout;
+	u32 status;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status = pci_read_config32(dev, TBT2PCIE);
+		if (status & 1) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status %08x\n", command, status);
+	}
+
+	printk(BIOS_INFO, "DTBT command %08x status %08x\n", command, status);
+
+	pci_write_config32(dev, PCIE2TBT, 0);
+
+	u32 status_clear;
+	for (timeout = 1000000; timeout > 0; timeout--) {
+		status_clear = pci_read_config32(dev, TBT2PCIE);
+		if (!(status_clear & 1)) {
+			break;
+		}
+		udelay(1);
+	}
+	if (timeout == 0) {
+		printk(BIOS_ERR, "DTBT command %08x timeout on status clear %08x\n", command, status_clear);
+	}
+}
+
+static void dtbt_fill_ssdt(const struct device *dev) {
+	printk(BIOS_INFO, "DTBT fill SSDT\n");
+
+	if (!dev) {
+		printk(BIOS_ERR, "DTBT device invalid\n");
+	}
+	printk(BIOS_INFO, "  Dev %s\n", dev_path(dev));
+
+	struct bus *bus = dev->bus;
+	if (!bus) {
+		printk(BIOS_ERR, "DTBT bus invalid\n");
+	}
+	printk(BIOS_INFO, "  Bus %s\n", bus_path(bus));
+
+	struct device *parent = bus->dev;
+	if (!parent || parent->path.type != DEVICE_PATH_PCI) {
+		printk(BIOS_ERR, "DTBT parent invalid\n");
+		return;
+	}
+	printk(BIOS_INFO, "  Parent %s\n", dev_path(parent));
+
+	const char *parent_scope = acpi_device_path(parent);
+	if (!parent_scope) {
+		printk(BIOS_ERR, "DTBT parent scope not valid\n");
+		return;
+	}
+
+	{ /* Scope */
+		printk(BIOS_INFO, "  Scope %s\n", parent_scope);
+		acpigen_write_scope(parent_scope);
+
+		struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+
+		/* Indicate that device supports hotplug in D3. */
+		acpi_device_add_hotplug_support_in_d3(dsd);
+
+		/* Indicate that port is external. */
+		acpi_device_add_external_facing_port(dsd);
+
+		acpi_dp_write(dsd);
+
+		{ /* Device */
+			const char *dev_name = acpi_device_name(dev);
+			printk(BIOS_INFO, "    Device %s\n", dev_name);
+			acpigen_write_device(dev_name);
+
+			acpigen_write_name_integer("_ADR", 0);
+
+			uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
+			                      + (((uintptr_t)(bus->secondary)) << 20);
+			printk(BIOS_INFO, "      MMCONF base %08lx\n", mmconf_base);
+			const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
+			const struct fieldlist fieldlist[] = {
+				FIELDLIST_OFFSET(TBT2PCIE),
+				FIELDLIST_NAMESTR("TB2P", 32),
+				FIELDLIST_OFFSET(PCIE2TBT),
+				FIELDLIST_NAMESTR("P2TB", 32),
+			};
+			acpigen_write_opregion(&opregion);
+			acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
+					    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
+
+			{ /* Method */
+				acpigen_write_method_serialized("PTS", 0);
+
+				acpigen_write_debug_string("DTBT prepare to sleep");
+
+				acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", PCIE2TBT_GO2SX_NO_WAKE);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_store_int_to_namestr(0, "P2TB");
+				acpigen_write_delay_until_namestr_int(600, "TB2P", 0);
+
+				acpigen_write_debug_namestr("TB2P");
+
+				acpigen_write_method_end();
+			}
+
+			acpigen_write_device_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+
+	{ /* Scope */
+		acpigen_write_scope("\\");
+
+		{ /* Method */
+			acpigen_write_method("TBTS", 0);
+
+			acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
+
+			acpigen_write_method_end();
+		}
+
+		acpigen_write_scope_end();
+	}
+}
+
+static const char *dtbt_acpi_name(const struct device *dev) {
+	return "DTBT";
+}
+
+static struct pci_operations dtbt_device_ops_pci = {
+	.set_subsystem = 0,
+};
+
+static struct device_operations dtbt_device_ops = {
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
+	.acpi_name 		  = dtbt_acpi_name,
+	.scan_bus         = pciexp_scan_bridge,
+	.reset_bus        = pci_bus_reset,
+	.ops_pci          = &dtbt_device_ops_pci,
+};
+
+static void dtbt_enable(struct device *dev)
+{
+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
+		return;
+
+	//TODO: check device ID
+
+	dev->ops = &dtbt_device_ops;
+
+	printk(BIOS_INFO, "DTBT controller found at %s\n", dev_path(dev));
+
+	printk(BIOS_INFO, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	printk(BIOS_INFO, "DTBT set security level SL0\n");
+	dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL);
+
+	printk(BIOS_INFO, "DTBT get security level\n");
+	dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL);
+
+	if (acpi_is_wakeup_s3()) {
+		printk(BIOS_INFO, "DTBT SX exit\n");
+		dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED);
+	} else {
+		printk(BIOS_INFO, "DTBT boot on\n");
+		dtbt_cmd(dev, PCIE2TBT_BOOT_ON);
+	}
+}
+
+struct chip_operations drivers_intel_dtbt_ops = {
+	CHIP_NAME("Intel Discrete Thunderbolt Device")
+	.enable_dev = dtbt_enable
+};

src/drivers/pc80/tpm/tis.c

@@ -114,6 +114,7 @@ static const struct device_name infineon_devices[] = {
 #if CONFIG(TPM2)
 	{0x001a, "SLB9665 TT 2.0"},
 	{0x001b, "SLB9670 TT 2.0"},
+	{0x001d, "SLB9672 TT 2.0"},
 #else
 	{0x001a, "SLB9660 TT 1.2"},
 	{0x001b, "SLB9670 TT 1.2"},

src/drivers/smmstore/ramstage.c

@@ -57,6 +57,7 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
+	for (int retries = 0; retries < 3; retries++) {
 		/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
 		__asm__ __volatile__ (
 			"outb %%al, %%dx"
@@ -66,9 +67,12 @@ static void init_store(void *unused)
 			  "d" (APM_CNT)
 			: "memory");
 
-	if (eax != SMMSTORE_RET_SUCCESS) {
-		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");
-		return;
+		if (eax == SMMSTORE_RET_SUCCESS) {
+			printk(BIOS_INFO, "SMMSTORE: Installed com buffer\n");
+			break;
+		}
+
+		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer: 0x%x\n", eax);
 	}
 }
 

src/ec/system76/ec/Kconfig

@@ -8,12 +8,12 @@ config EC_SYSTEM76_EC_BAT_THRESHOLDS
 	bool
 	default y
 
-config EC_SYSTEM76_EC_COLOR_KEYBOARD
+config EC_SYSTEM76_EC_DGPU
 	depends on EC_SYSTEM76_EC
 	bool
 	default n
 
-config EC_SYSTEM76_EC_DGPU
+config EC_SYSTEM76_EC_LOCKDOWN
 	depends on EC_SYSTEM76_EC
 	bool
 	default n

src/ec/system76/ec/Makefile.inc

@@ -2,6 +2,7 @@
 ifeq ($(CONFIG_EC_SYSTEM76_EC),y)
 
 all-y += system76_ec.c
+ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c
 smm-$(CONFIG_DEBUG_SMI) += system76_ec.c
 
 endif

src/ec/system76/ec/acpi/ec.asl

@@ -90,9 +90,6 @@ Device (\_SB.PCI0.LPCB.EC0)
 			// Notify of changes
 			Notify(^^^^AC, 0)
 			Notify(^^^^BAT0, 0)
-
-			// Reset System76 Device
-			^^^^S76D.RSET()
 		}
 	}
 

src/ec/system76/ec/acpi/s76.asl

@@ -16,10 +16,8 @@ Device (S76D) {
 	Method (RSET, 0, Serialized) {
 		Printf ("S76D: RSET")
 		SAPL(0)
-		SKBL(0)
-#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+		SKBB(0)
 		SKBC(0xFFFFFF)
-#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
 	}
 
 	Method (INIT, 0, Serialized) {
@@ -67,53 +65,63 @@ Device (S76D) {
 		}
 	}
 
-#if CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
-	// Set KB LED Brightness
-	Method (SKBL, 1, Serialized) {
+	// Get Keyboard Backlight Kind
+	// 0 - No backlight
+	// 1 - White backlight
+	// 2 - RGB backlight
+	Method (GKBK, 0, Serialized) {
+		Local0 = 0
 		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 6
-			^^PCI0.LPCB.EC0.FBUF = Arg0
-			^^PCI0.LPCB.EC0.FBF1 = 0
-			^^PCI0.LPCB.EC0.FBF2 = Arg0
+			^^PCI0.LPCB.EC0.FDAT = 2
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
 		}
+		Return (Local0)
 	}
 
-	// Set Keyboard Color
-	Method (SKBC, 1, Serialized) {
-		If (^^PCI0.LPCB.EC0.ECOK) {
-			^^PCI0.LPCB.EC0.FDAT = 0x3
-			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
-			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
-			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
-			^^PCI0.LPCB.EC0.FCMD = 0xCA
-			Return (Arg0)
-		} Else {
-			Return (0)
-		}
-	}
-#else // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
-	// Get KB LED
-	Method (GKBL, 0, Serialized) {
+	// Get Keyboard Brightness
+	Method (GKBB, 0, Serialized) {
 		Local0 = 0
 		If (^^PCI0.LPCB.EC0.ECOK) {
 			^^PCI0.LPCB.EC0.FDAT = 1
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
 			Local0 = ^^PCI0.LPCB.EC0.FBUF
-			^^PCI0.LPCB.EC0.FCMD = 0
 		}
 		Return (Local0)
 	}
 
-	// Set KB Led
-	Method (SKBL, 1, Serialized) {
+	// Set Keyboard Brightness
+	Method (SKBB, 1, Serialized) {
 		If (^^PCI0.LPCB.EC0.ECOK) {
 			^^PCI0.LPCB.EC0.FDAT = 0
 			^^PCI0.LPCB.EC0.FBUF = Arg0
 			^^PCI0.LPCB.EC0.FCMD = 0xCA
 		}
 	}
-#endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+
+	// Get Keyboard Color
+	Method (GKBC, 0, Serialized) {
+		Local0 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 4
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+			Local0 = ^^PCI0.LPCB.EC0.FBUF
+			Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16
+			Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8
+		}
+		Return (Local0)
+	}
+
+	// Set Keyboard Color
+	Method (SKBC, 1, Serialized) {
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			^^PCI0.LPCB.EC0.FDAT = 3
+			^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
+			^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
+			^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
+			^^PCI0.LPCB.EC0.FCMD = 0xCA
+		}
+	}
 
 	// Fan names
 	Method (NFAN, 0, Serialized) {

src/ec/system76/ec/lockdown.c

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <commonlib/region.h>
+#include <fmap.h>
+#include <spi_flash.h>
+
+#include "system76_ec.h"
+
+static int protect_region_by_name(const char *name)
+{
+	int res;
+	struct region region;
+
+	res = fmap_locate_area(name, &region);
+	if (res < 0) {
+		printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	res = spi_flash_ctrlr_protect_region(
+		boot_device_spi_flash(),
+		&region,
+		WRITE_PROTECT
+	);
+	if (res < 0) {
+		printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res);
+		return res;
+	}
+
+	printk(BIOS_INFO, "protected '%s'\n", name);
+	return 0;
+}
+
+static void lock(void *unused)
+{
+	uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	if (system76_ec_security_get(&state) < 0) {
+		printk(BIOS_INFO, "failed to get security state, assuming unlocked\n");
+		state = SYSTEM76_EC_SECURITY_STATE_UNLOCK;
+	}
+
+	printk(BIOS_INFO, "security state: %d\n", state);
+	if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) {
+		// Protect WP_RO region, which should contain FMAP and COREBOOT
+		protect_region_by_name("WP_RO");
+		// Protect RW_MRC_CACHE region, this must be done after it is written
+		protect_region_by_name("RW_MRC_CACHE");
+		//TODO: protect entire flash except when in SMM?
+	}
+}
+
+/*
+ * Keep in sync with mrc_cache.c
+ */
+
+#if CONFIG(MRC_WRITE_NV_LATE)
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL);
+#else
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL);
+#endif

src/ec/system76/ec/system76_ec.c

@@ -3,6 +3,7 @@
 #include <arch/io.h>
 #include <console/system76_ec.h>
 #include <timer.h>
+#include "system76_ec.h"
 
 // This is the command region for System76 EC firmware. It must be
 // enabled for LPC in the mainboard.
@@ -11,15 +12,22 @@
 
 #define REG_CMD 0
 #define REG_RESULT 1
+#define REG_DATA 2
 
 // When command register is 0, command is complete
 #define CMD_FINISHED 0
 
 // Print command. Registers are unique for each command
 #define CMD_PRINT 4
-#define CMD_PRINT_REG_FLAGS 2
-#define CMD_PRINT_REG_LEN 3
-#define CMD_PRINT_REG_DATA 4
+#define CMD_PRINT_REG_FLAGS REG_DATA
+#define CMD_PRINT_REG_LEN (REG_DATA + 1)
+#define CMD_PRINT_REG_DATA (REG_DATA + 2)
+
+// Get security state command
+#define CMD_SECURITY_GET 20
+
+// OK result, any other values are errors
+#define RESULT_OK 0
 
 static inline uint8_t system76_ec_read(uint8_t addr)
 {
@@ -59,3 +67,81 @@ void system76_ec_print(uint8_t byte)
 	if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
 		system76_ec_flush();
 }
+
+// Issue a command not checking if the console needs to be flushed
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_unsafe(uint8_t cmd, uint8_t * data, int length) {
+	// Error if length is too long
+	if (length > (SYSTEM76_EC_SIZE - REG_DATA)) {
+		return -1;
+	}
+
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Write command data
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, data[i]);
+	}
+
+	// Start command
+	system76_ec_write(REG_CMD, cmd);
+
+	// Wait for command completion, for up to 10 milliseconds, with a
+	// test period of 1 microsecond
+	wait_us(10000, system76_ec_read(REG_CMD) == CMD_FINISHED);
+
+	// Error if command did not complete
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Read command data
+	for (int i = 0; i < length; i++) {
+		data[i] = system76_ec_read(REG_DATA + i);
+	}
+
+	// Check result
+	if (system76_ec_read(REG_RESULT) != RESULT_OK) {
+		return -1;
+	}
+
+	return 0;
+}
+
+// Wrapper to allow issuing commands while console is being used
+// Do not print from this command to avoid EC protocol issues
+static int system76_ec_command(uint8_t cmd, uint8_t * data, int length) {
+	// Error if command is in progress
+	if (system76_ec_read(REG_CMD) != CMD_FINISHED) {
+		return -1;
+	}
+
+	// Flush print buffer if it has data
+	// Checked for completion by system76_ec_unsafe
+	if (system76_ec_read(CMD_PRINT_REG_LEN) > 0) {
+		system76_ec_flush();
+	}
+
+	// Run command now that print buffer is flushed
+	int res = system76_ec_unsafe(cmd, data, length);
+	if (res < 0) {
+		return res;
+	}
+
+	// Clear command data (for future prints)
+	// Length is checked by system76_ec_unsafe
+	for (int i = 0; i < length; i++) {
+		system76_ec_write(REG_DATA + i, 0);
+	}
+
+	return 0;
+}
+
+// Get security state
+int system76_ec_security_get(uint8_t * state) {
+	*state = 0;
+	return system76_ec_command(CMD_SECURITY_GET, state, sizeof(uint8_t));
+}

src/ec/system76/ec/system76_ec.h

@@ -0,0 +1,16 @@
+#ifndef EC_SYSTEM76_EC_H
+#define EC_SYSTEM76_EC_H
+
+// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_LOCK 0
+// Flashing is allowed, cannot be set with CMD_SECURITY_SET
+#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1
+// Flashing will be prevented on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2
+// Flashing will be allowed on the next reboot
+#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3
+
+// Get security state
+int system76_ec_security_get(uint8_t * state);
+
+#endif /* EC_SYSTEM76_EC_H */

src/include/cpu/intel/cpu_ids.h

@@ -62,7 +62,11 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
-#define CPUID_RAPTORLAKE_P_J0		0xb06a2
-#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
+#define CPUID_RAPTORLAKE_E_S_HX_B0	0xb0671
+#define CPUID_RAPTORLAKE_HX_S_8_8_C0	0xb06f2
+#define CPUID_RAPTORLAKE_H_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_S_6_0_C0	0xb06f5
+#define CPUID_RAPTORLAKE_S_A0		0xb0670
+#define CPUID_RAPTORLAKE_U_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -3462,6 +3462,35 @@
 #define PCI_DID_INTEL_RPL_P_PCIE_RP2			0xa70d
 #define PCI_DID_INTEL_RPL_P_PCIE_RP3			0xa72d
 
+#define PCI_DID_INTEL_RPP_S_PCIE_RP1			0x7a38
+#define PCI_DID_INTEL_RPP_S_PCIE_RP2			0x7a39
+#define PCI_DID_INTEL_RPP_S_PCIE_RP3			0x7a3a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP4			0x7a3b
+#define PCI_DID_INTEL_RPP_S_PCIE_RP5			0x7a3c
+#define PCI_DID_INTEL_RPP_S_PCIE_RP6			0x7a3d
+#define PCI_DID_INTEL_RPP_S_PCIE_RP7			0x7a3e
+#define PCI_DID_INTEL_RPP_S_PCIE_RP8			0x7a3f
+#define PCI_DID_INTEL_RPP_S_PCIE_RP9			0x7a30
+#define PCI_DID_INTEL_RPP_S_PCIE_RP10			0x7a31
+#define PCI_DID_INTEL_RPP_S_PCIE_RP11			0x7a32
+#define PCI_DID_INTEL_RPP_S_PCIE_RP12			0x7a33
+#define PCI_DID_INTEL_RPP_S_PCIE_RP13			0x7a34
+#define PCI_DID_INTEL_RPP_S_PCIE_RP14			0x7a35
+#define PCI_DID_INTEL_RPP_S_PCIE_RP15			0x7a36
+#define PCI_DID_INTEL_RPP_S_PCIE_RP16			0x7a37
+#define PCI_DID_INTEL_RPP_S_PCIE_RP17			0x7a40
+#define PCI_DID_INTEL_RPP_S_PCIE_RP18			0x7a41
+#define PCI_DID_INTEL_RPP_S_PCIE_RP19			0x7a42
+#define PCI_DID_INTEL_RPP_S_PCIE_RP20			0x7a43
+#define PCI_DID_INTEL_RPP_S_PCIE_RP21			0x7a44
+#define PCI_DID_INTEL_RPP_S_PCIE_RP22			0x7a45
+#define PCI_DID_INTEL_RPP_S_PCIE_RP23			0x7a46
+#define PCI_DID_INTEL_RPP_S_PCIE_RP24			0x7a47
+#define PCI_DID_INTEL_RPP_S_PCIE_RP25			0x7a48
+#define PCI_DID_INTEL_RPP_S_PCIE_RP26			0x7a49
+#define PCI_DID_INTEL_RPP_S_PCIE_RP27			0x7a4a
+#define PCI_DID_INTEL_RPP_S_PCIE_RP28			0x7a4b
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3536,6 +3565,7 @@
 #define PCI_DID_INTEL_MTL_SATA			0x7e63
 #define PCI_DID_INTEL_RPP_P_SATA_1		0x51d3
 #define PCI_DID_INTEL_RPP_P_SATA_2		0x51d7
+#define PCI_DID_INTEL_RPP_S_SATA		0x7a62
 
 /* Intel PMC device Ids */
 #define PCI_DID_INTEL_SPT_LP_PMC		0x9d21
@@ -3671,6 +3701,13 @@
 #define PCI_DID_INTEL_ADP_M_N_I2C4		0x54c5
 #define PCI_DID_INTEL_ADP_M_N_I2C5		0x54c6
 
+#define PCI_DID_INTEL_RPP_S_I2C0		0x7a4c
+#define PCI_DID_INTEL_RPP_S_I2C1		0x7a4d
+#define PCI_DID_INTEL_RPP_S_I2C2		0x7a4e
+#define PCI_DID_INTEL_RPP_S_I2C3		0x7a4f
+#define PCI_DID_INTEL_RPP_S_I2C4		0x7a7c
+#define PCI_DID_INTEL_RPP_S_I2C5		0x7a7d
+
 #define PCI_DID_INTEL_MTL_I2C0			0x7e78
 #define PCI_DID_INTEL_MTL_I2C1			0x7e79
 #define PCI_DID_INTEL_MTL_I2C2			0x7e7a
@@ -3748,6 +3785,11 @@
 #define PCI_DID_INTEL_ADP_M_N_UART2		0x54c7
 #define PCI_DID_INTEL_ADP_M_N_UART3		0x54da
 
+#define PCI_DID_INTEL_RPP_S_UART0		0x7a28
+#define PCI_DID_INTEL_RPP_S_UART1		0x7a29
+#define PCI_DID_INTEL_RPP_S_UART2		0x7a7e
+#define PCI_DID_INTEL_RPP_S_UART3		0x7a5c
+
 #define PCI_DID_INTEL_MTL_UART0			0x7e25
 #define PCI_DID_INTEL_MTL_UART1			0x7e26
 #define PCI_DID_INTEL_MTL_UART2			0x7e52
@@ -3833,6 +3875,12 @@
 #define PCI_DID_INTEL_ADP_M_N_SPI1		0x54ab
 #define PCI_DID_INTEL_ADP_M_SPI2		0x54fb
 
+#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI		0x7a24
+#define PCI_DID_INTEL_RPP_S_SPI0		0x7a2a
+#define PCI_DID_INTEL_RPP_S_SPI1		0x7a2b
+#define PCI_DID_INTEL_RPP_S_SPI2		0x7a7b
+#define PCI_DID_INTEL_RPP_S_SPI3		0x7a79
+
 #define PCI_DID_INTEL_SPR_HWSEQ_SPI		0x1bca
 
 #define PCI_DID_INTEL_MTL_HWSEQ_SPI		0x7e23
@@ -3983,6 +4031,10 @@
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
+#define PCI_DID_INTEL_RPL_HX_GT1			0xa788
+#define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
+#define PCI_DID_INTEL_RPL_HX_GT3			0x4688
+#define PCI_DID_INTEL_RPL_HX_GT4			0x468b
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
@@ -4106,6 +4158,14 @@
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
+#define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
+#define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
+#define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
+#define PCI_DID_INTEL_RPL_HX_ID_4		0xa72a
+#define PCI_DID_INTEL_RPL_HX_ID_5		0xa719
+#define PCI_DID_INTEL_RPL_HX_ID_6		0x4637
+#define PCI_DID_INTEL_RPL_HX_ID_7		0x463b
+#define PCI_DID_INTEL_RPL_HX_ID_8		0x4647
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
@@ -4136,6 +4196,7 @@
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
 #define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 #define PCI_DID_INTEL_RPP_P_SMBUS			0x51a3
+#define PCI_DID_INTEL_RPP_S_SMBUS			0x7a23
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4172,6 +4233,7 @@
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 #define PCI_DID_INTEL_RPP_P_TCSS_XHCI		0xa71e
+#define PCI_DID_INTEL_RPP_S_XHCI		0x7a60
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4240,6 +4302,14 @@
 #define PCI_DID_INTEL_ADP_S_AUDIO_8		0x7ad7
 #define PCI_DID_INTEL_ADP_P_AUDIO		0x51c8
 #define PCI_DID_INTEL_RPP_P_AUDIO		0x51ca
+#define PCI_DID_INTEL_RPP_S_AUDIO_1		0x7a50
+#define PCI_DID_INTEL_RPP_S_AUDIO_2		0x7a51
+#define PCI_DID_INTEL_RPP_S_AUDIO_3		0x7a52
+#define PCI_DID_INTEL_RPP_S_AUDIO_4		0x7a53
+#define PCI_DID_INTEL_RPP_S_AUDIO_5		0x7a54
+#define PCI_DID_INTEL_RPP_S_AUDIO_6		0x7a55
+#define PCI_DID_INTEL_RPP_S_AUDIO_7		0x7a56
+#define PCI_DID_INTEL_RPP_S_AUDIO_8		0x7a57
 
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1		0x54c8
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2		0x54c9
@@ -4296,6 +4366,10 @@
 #define PCI_DID_INTEL_ADP_M_CSE1		0x54e1
 #define PCI_DID_INTEL_ADP_M_CSE2		0x54e4
 #define PCI_DID_INTEL_ADP_M_CSE3		0x54e5
+#define PCI_DID_INTEL_RPP_S_CSE0		0x7a68
+#define PCI_DID_INTEL_RPP_S_CSE1		0x7a69
+#define PCI_DID_INTEL_RPP_S_CSE2		0x7a6c
+#define PCI_DID_INTEL_RPP_S_CSE3		0x7a6d
 #define PCI_DID_INTEL_MTL_CSE0			0x7e70
 
 /* Intel XDCI device Ids */
@@ -4319,6 +4393,7 @@
 #define PCI_DID_INTEL_MTL_XDCI			0x7e7e
 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
+#define PCI_DID_INTEL_RPP_S_XDCI		0x7a61
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4459,6 +4534,10 @@
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1		0x7e41
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0		0x7a70
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1		0x7a71
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2		0x7a72
+#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3		0x7a73
 
 /* Intel Crashlog */
 #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM		0x9a0d
@@ -4469,6 +4548,7 @@
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
+#define PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM		0x7a27
 
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32

src/include/spd_bin.h

@@ -35,6 +35,18 @@
 #define DDR4_SPD_PART_OFF	329
 #define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
+#define MAX_SPD_PAGE_SIZE_SPD5	128
+#define MAX_SPD_SIZE		(SPD_PAGE_LEN * SPD_SN_LEN)
+#define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
+#define SPD5_MR11		0x0B
+#define SPD5_MR0		0x00
+#define SPD5_MEMREG_REG(addr)	((u8)((~0x80) & (addr)))
+#define SPD5_MR0_SPD5_HUB_DEV	0x51
+
+struct spd_offset_table {
+	u16 start;		/* Offset 0 */
+	u16 end;		/* Offset 2 */
+};
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

src/lib/spd_cache.c

@@ -209,7 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk)
 
 	dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE);
 
-	if (dram_type == SPD_DRAM_DDR4)
+	if (dram_type == SPD_DRAM_DDR4 || dram_type == SPD_DRAM_DDR5)
 		blk->len = SPD_PAGE_LEN_DDR4;
 	else
 		blk->len = SPD_PAGE_LEN;

src/mainboard/system76/addw1/Kconfig

@@ -3,10 +3,12 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD
 	select EC_SYSTEM76_EC_DGPU
 	select EC_SYSTEM76_EC_OLED
 	select HAVE_ACPI_RESUME

src/mainboard/system76/addw1/Makefile.inc

@@ -1,4 +1,4 @@
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/addw1/devicetree.cb

@@ -58,6 +58,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,8 +22,20 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	// Allow higher memory speeds
-	memupd->FspmConfig.SaOcSupport = 1;
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Disable higher memory speeds
+	memupd->FspmConfig.SaOcSupport = 0;
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/adl-p/Kconfig

@@ -1,70 +0,0 @@
-if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_I2C_HID
-	select DRIVERS_INTEL_PMC
-	select DRIVERS_INTEL_USB4_RETIMER
-	select EC_SYSTEM76_EC
-	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8
-	select HAVE_ACPI_TABLES
-	select HAVE_CMOS_DEFAULT
-	select HAVE_OPTION_TABLE
-	select INTEL_GMA_HAVE_VBT
-	select INTEL_LPSS_UART_FOR_CONSOLE
-	select MAINBOARD_HAS_TPM2
-	select MEMORY_MAPPED_TPM
-	select NO_UART_ON_SUPERIO
-	select SOC_INTEL_ALDERLAKE_PCH_P
-	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select SOC_INTEL_CRASHLOG
-	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
-	select SPD_READ_BY_WORD
-	select SYSTEM_TYPE_LAPTOP
-
-config MAINBOARD_DIR
-	default "system76/adl-p"
-
-config VARIANT_DIR
-	default "darp8" if BOARD_SYSTEM76_DARP8
-	default "galp6" if BOARD_SYSTEM76_GALP6
-
-config OVERRIDE_DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-
-config MAINBOARD_PART_NUMBER
-	default "darp8" if BOARD_SYSTEM76_DARP8
-	default "galp6" if BOARD_SYSTEM76_GALP6
-
-config MAINBOARD_SMBIOS_PRODUCT_NAME
-	default "Darter Pro" if BOARD_SYSTEM76_DARP8
-	default "Galago Pro" if BOARD_SYSTEM76_GALP6
-
-config MAINBOARD_VERSION
-	default "darp8" if BOARD_SYSTEM76_DARP8
-	default "galp6" if BOARD_SYSTEM76_GALP6
-
-config CBFS_SIZE
-	default 0xA00000
-
-config CONSOLE_POST
-	default y
-
-config DIMM_SPD_SIZE
-	default 512
-
-config POST_DEVICE
-	default n
-
-config TPM_MEASURED_BOOT
-	default y
-
-config UART_FOR_CONSOLE
-	default 0
-
-# PM Timer Disabled, saves power
-config USE_PM_ACPI_TIMER
-	default n
-
-endif

src/mainboard/system76/adl-p/Kconfig.name

@@ -1,5 +0,0 @@
-config BOARD_SYSTEM76_DARP8
-	bool "darp8"
-
-config BOARD_SYSTEM76_GALP6
-	bool "galp6"

src/mainboard/system76/adl/Kconfig

@@ -0,0 +1,146 @@
+config BOARD_SYSTEM76_ADL_COMMON
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select DRIVERS_GENERIC_BAYHUB_LV2
+	select DRIVERS_GENERIC_CBFS_SERIAL
+	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_LOCKDOWN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select MEMORY_MAPPED_TPM
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_ALDERLAKE_S3
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_CRASHLOG
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config BOARD_SYSTEM76_DARP8
+	select BOARD_SYSTEM76_ADL_COMMON
+
+config BOARD_SYSTEM76_GALP6
+	select BOARD_SYSTEM76_ADL_COMMON
+
+config BOARD_SYSTEM76_GAZE17_3050
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_DGPU
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_DGPU
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
+	select TPM_RDRESP_NEED_DELAY
+
+config BOARD_SYSTEM76_LEMP11
+	select BOARD_SYSTEM76_ADL_COMMON
+	select HAVE_SPD_IN_CBFS
+
+config BOARD_SYSTEM76_ORYP9
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select DRIVERS_I2C_TAS5825M
+	select EC_SYSTEM76_EC_DGPU
+
+config BOARD_SYSTEM76_ORYP10
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+	select EC_SYSTEM76_EC_DGPU
+
+if BOARD_SYSTEM76_ADL_COMMON
+
+config MAINBOARD_DIR
+	default "system76/adl"
+
+config VARIANT_DIR
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Darter Pro" if BOARD_SYSTEM76_DARP8
+	default "Galago Pro" if BOARD_SYSTEM76_GALP6
+	default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
+	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config MAINBOARD_VERSION
+	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+	default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
+	default "oryp9" if BOARD_SYSTEM76_ORYP9
+	default "oryp10" if BOARD_SYSTEM76_ORYP10
+
+config CMOS_DEFAULT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
+	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
+
+config CONSOLE_POST
+	default y
+
+config DIMM_SPD_SIZE
+	default 512
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config TPM_MEASURED_BOOT
+	default y
+
+config UART_FOR_CONSOLE
+	default 0
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif

src/mainboard/system76/adl/Kconfig.name

@@ -0,0 +1,20 @@
+config BOARD_SYSTEM76_DARP8
+	bool "darp8"
+
+config BOARD_SYSTEM76_GALP6
+	bool "galp6"
+
+config BOARD_SYSTEM76_GAZE17_3050
+	bool "gaze17 3050"
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+	bool "gaze17 3060-b"
+
+config BOARD_SYSTEM76_LEMP11
+	bool "lemp11"
+
+config BOARD_SYSTEM76_ORYP9
+	bool "oryp9"
+
+config BOARD_SYSTEM76_ORYP10
+	bool "oryp10"

src/mainboard/system76/adl/Makefile.inc

@@ -1,4 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
@@ -8,3 +11,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
+
+SPD_SOURCES = samsung-P4AAF165WA-BCWDE

src/mainboard/system76/adl/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }

src/mainboard/system76/adl/board.fmd

@@ -0,0 +1,15 @@
+FLASH 32M {
+	SI_DESC 4K
+#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION
+	SI_GBE 8K
+#endif
+	SI_ME 4824K
+	SI_BIOS@16M 16M {
+		RW_MRC_CACHE 64K
+		SMMSTORE(PRESERVE) 256K
+		WP_RO {
+			FMAP 4K
+			COREBOOT(CBFS)
+		}
+	}
+}

src/mainboard/system76/adl/cmos.default

@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable

src/mainboard/system76/adl/devicetree.cb

@@ -11,8 +11,6 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
-	register "s0ix_enable" = "1"
-
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 
@@ -72,9 +70,8 @@ chip soc/intel/alderlake
 		device ref heci1 on end
 		device ref sata on
 			register "sata_salp_support" = "1"
-			register "sata_ports_enable[1]" = "1" # SSD1
-			# FIXME: DevSlp breaks S0ix
-			#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
+			register "sata_ports_enable[1]" = "1"
+			register "sata_ports_dev_slp[1]" = "1"
 		end
 		device ref pch_espi on
 			register "gen1_dec" = "0x00040069" # EC PM channel

src/mainboard/system76/adl/ramstage.c

@@ -23,6 +23,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
 
 	params->SataPortsSolidStateDrive[1] = 1;
+
+	// Enable reporting CPU C10 state over eSPI
+	params->PchEspiHostC10ReportEnable = 1;
 }
 
 static void mainboard_init(void *chip_info)

src/mainboard/system76/adl/spd/samsung-P4AAF165WA-BCWDE.spd.hex

@@ -0,0 +1,33 @@
+# Samsung P4AAF165WA-BCWDE
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
+F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 DE DE
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 50 34 41 41 46 31 36
+35 57 41 2D 42 43 57 44 45 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -1,10 +1,9 @@
 chip soc/intel/alderlake
-	# HACK: Limit PL4 to PL2 to prevent power-off when system is booted on
-	# battery power. This seems to only happen with the i7 units.
+	register "s0ix_enable" = "1"
+
 	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 56,
-		.tdp_pl4 = 56, // FIXME: Set to 65
 	}"
 
 	# GPE configuration
@@ -154,12 +153,6 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
-				register "srcclk_pin" = "4" # SSD1_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux

src/mainboard/system76/adl/variants/galp6/overridetree.cb

@@ -2,7 +2,6 @@ chip soc/intel/alderlake
 	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
 		.tdp_pl1_override = 28,
 		.tdp_pl2_override = 60,
-		.tdp_pl4 = 90,
 	}"
 
 	# GPE configuration

src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze17-3050
+Release year: 2022

src/mainboard/system76/adl/variants/gaze17-3050/gpio.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
+	PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN
+	PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST#
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+	PAD_NC(GPP_C3, NONE), // SML0_CLK
+	PAD_NC(GPP_C4, NONE), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP
+	PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL
+	PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
+	PAD_NC(GPP_D13, NONE),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+	PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE#
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
+	PAD_NC(GPP_E18, NONE),
+	PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE),
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST#
+	PAD_NC(GPP_F11, NONE), // ADDS_CODE
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
+	PAD_NC(GPP_F17, NONE),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+	PAD_NC(GPP_F21, NONE),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2#
+	PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA
+	PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
+	PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	PAD_NC(GPP_H12, NONE),
+	_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
+	//PAD_NC(GPP_H14, NONE),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	//PAD_NC(GPP_H16, NONE),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK
+	PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x1558866d, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558866d),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {
+	// Adjust mic coefficient
+	0x02050007,
+	0x02040202,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x866d1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -0,0 +1,132 @@
+chip soc/intel/alderlake
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+	device domain 0 on
+		subsystemid 0x1558 0x866d inherit
+
+		device ref pcie5_0 on
+			# PCIe PEG2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
+		end
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 off end
+		device ref tbt_pcie_rp0 off end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			device ref tcss_root_hub on
+				device ref tcss_usb3_port1 on end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+		end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x4, Clock 1 (SSD)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x1, Clock 6 (GLAN)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp10 on
+			# PCIe RP#10 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+		device ref pcie_rp11 on
+			# PCIe RP#11 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+		end
+	end
+end

src/mainboard/system76/adl/variants/gaze17-3050/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze17-3060-b
+Release year: 2022

src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16)
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+	//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD
+	PAD_NC(GPP_A16, NONE), // USB_OC3#
+	PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+	_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE#
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	//PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	//PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24
+	//PAD_CFG_GPO(GPP_B19, 0, DEEP),
+	//PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	//PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	//PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ#
+	//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ#
+	PAD_NC(GPP_D9, NONE),
+	PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24
+	PAD_NC(GPP_D11, NONE),
+	PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2
+	PAD_NC(GPP_D15, NONE),
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN#
+	PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
+	// GPP_E18 (TBT_LSX0_TXD) configured by FSP
+	// GPP_E19 (TBT_LSX0_RXD) configured by FSP
+	PAD_NC(GPP_E20, NONE),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
+	//PAD_CFG_GPO(GPP_F8, 0, DEEP),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST#
+	PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24
+	PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+	PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD
+	PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD
+	PAD_NC(GPP_H12, NONE),
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1
+	//PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	//PAD_NC(GPP_H16, NONE),
+	PAD_NC(GPP_H17, NONE),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC
+	PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC
+	PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS
+	//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+	PAD_NC(GPP_R5, NONE),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1
+	PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x1558867c, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1558867c),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x867c1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -0,0 +1,141 @@
+chip soc/intel/alderlake
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Thermal
+	register "tcc_offset" = "10"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+	device domain 0 on
+		subsystemid 0x1558 0x867c inherit
+
+		device ref pcie5_0 on
+			# PCIe PEG2 x8, Clock 3 (DGPU)
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 3,
+				.clk_req = 3,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
+		end
+		device ref igpu on
+			# DDIA is eDP
+			register "ddi_portA_config" = "1"
+			register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""FTCS1000""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 off end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			device ref tcss_root_hub on
+				device ref tcss_usb3_port1 on end
+			end
+		end
+		device ref tcss_dma0 on end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
+		end
+		device ref pcie_rp5 on
+			# PCIe root port #5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie_rp6 on
+			# PCIe root port #6 x1, Clock 5 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 6 (GLAN)
+			# Clock source is shared with LAN and hence marked as free running.
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
+			}"
+			register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+		end
+		device ref gbe on end
+	end
+end

src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}

src/mainboard/system76/adl/variants/lemp11/board_info.txt

@@ -0,0 +1,2 @@
+Board name: lemp11
+Release year: 2022

src/mainboard/system76/adl/variants/lemp11/gpio.c

@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT#
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	// GPP_B9 missing
+	// GPP_B10 missing
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	// GPP_B19 missing
+	// GPP_B20 missing
+	// GPP_B21 missing
+	// GPP_B22 missing
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	// GPP_C8 missing
+	// GPP_C9 missing
+	// GPP_C10 missing
+	// GPP_C11 missing
+	// GPP_C12 missing
+	// GPP_C13 missing
+	// GPP_C14 missing
+	// GPP_C15 missing
+	// GPP_C16 missing
+	// GPP_C17 missing
+	// GPP_C18 missing
+	// GPP_C19 missing
+	// GPP_C20 missing
+	// GPP_C21 missing
+	// GPP_C22 missing
+	// GPP_C23 missing
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	// GPP_D5 (SSD0_CLKREQ#) configured by FSP
+	// GPP_D6 (SSD1_CLKREQ#) configured by FSP
+	// GPP_D7 (WLAN_CLKREQ#) configured by FSP
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE,  DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	// GPP_E18 (TBT_LSX0_TXD) configured by FSP
+	// GPP_E19 (TBT_LSX0_RXD) configured by FSP
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	// GPP_F5 (CNVI_CLKREQ) configured by FSP
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	// GPP_F8 missing
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	// GPP_F19 (CARD_CLKREQ#) configured by FSP
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST#
+	PAD_NC(GPP_H1, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	// GPP_H10 (UART0_RX) configured in bootblock
+	// GPP_H11 (UART0_TX) configured in bootblock
+	PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1), // SATA1_DEVSLP1
+	PAD_NC(GPP_H13, NONE),
+	// GPP_H14 missing
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	// GPP_H16 missing
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE), // DMIC_CLK
+	PAD_NC(GPP_R7, NONE), // DMIC_DAT
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/adl/variants/lemp11/gpio_early.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/adl/variants/lemp11/hda_verb.c

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256,
+	0x15587718,
+	11,
+	AZALIA_SUBVENDOR(0, 0x15587718),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;