darp7 SD card does not support RTD3

Change-Id: Ie393e9cd42f58d2b3b7172c99b9cd5a1b3a41d87

.gitmodules

@@ -1,60 +1,60 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

src/Kconfig

@@ -720,6 +720,12 @@ config ACPI_NHLT
 	help
 	  Build support for NHLT (non HD Audio) ACPI table generation.
 
+config ACPI_LPIT
+	bool
+	default y
+	help
+	  Build an ACPI Low Power Idle Table.
+
 #These Options are here to avoid "undefined" warnings.
 #The actual selection and help texts are in the following menu.
 

src/acpi/acpi.c

@@ -1264,6 +1264,78 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	    acpi_checksum((void *) fadt, header->length);
 }
 
+/*
+ * The value of residency couneter register address is MSR value and
+ * implementation specific.e.e.g, scenerios:
+ * 1. For CNL: space_id:0,residency_counter.addrl:0x632 and ACPI_LPIT
+ * selected in soc Kconfig sysfs file thet kernel creates is
+ * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us.
+ * 2. For CNL: space_id:0, residency_counter.addrl:0xfe000000 + 0x193C
+ * and ACPI_LPIT elected in soc Kconfig sysfs file thet kernel creates is
+ * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
+ * which gets populated with integer values whenever system goes in s0ix.
+ */
+__weak void soc_residency_counter(struct acpi_lpit_native *lpit_soc)
+{
+	lpit_soc->header.unique_id = 0;
+
+	lpit_soc->residency = 0x7530;
+	lpit_soc->latency = 0xBB8;
+
+	lpit_soc->entry_trigger.space_id = 0x7f;
+	lpit_soc->entry_trigger.bit_width = 0x01;
+	lpit_soc->entry_trigger.bit_offset = 0x02;
+	lpit_soc->entry_trigger.addrl = 0x60;
+
+	lpit_soc->residency_counter.space_id = 0x7f;
+	lpit_soc->residency_counter.bit_width = 0x40;
+	lpit_soc->residency_counter.addrl = 0x632;
+}
+
+__weak void system_residency_counter(struct acpi_lpit_native *lpit_system)
+{
+	lpit_system->header.unique_id = 1;
+
+	lpit_system->counter_frequency = 0x256c;
+	lpit_system->residency = 0x7530;
+	lpit_system->latency = 0xBB8;
+
+	lpit_system->entry_trigger.space_id = 0x7f;
+	lpit_system->entry_trigger.bit_width = 0x01;
+	lpit_system->entry_trigger.bit_offset = 0x02;
+	lpit_system->entry_trigger.addrl = 0x60;
+
+	lpit_system->residency_counter.space_id = 0x00;
+	lpit_system->residency_counter.bit_width = 0x20;
+	lpit_system->residency_counter.access_size = 0x03;
+	lpit_system->residency_counter.addrl = 0xfe00193c;
+}
+
+static void acpi_create_lpit_generator(acpi_table_lpit *lpit)
+{
+	acpi_header_t *header = &(lpit->header);
+
+	memset((void *)lpit, 0, sizeof(acpi_table_lpit));
+
+	memcpy(header->signature, "LPIT", 4);
+	header->revision = 2; /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	header->oem_revision = 42;
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+	header->length = sizeof(acpi_table_lpit);
+	lpit->lpit_soc.header.length = sizeof(struct acpi_lpit_native);
+	lpit->lpit_system.header.length = sizeof(struct acpi_lpit_native);
+
+	soc_residency_counter(&lpit->lpit_soc);
+	system_residency_counter(&lpit->lpit_system);
+
+
+	/* (Re)calculate length and checksum. */
+	header->checksum = acpi_checksum((void *)lpit, header->length);
+}
+
 unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
 {
 	return 0;
@@ -1284,6 +1356,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_tcpa_t *tcpa;
 	acpi_tpm2_t *tpm2;
 	acpi_madt_t *madt;
+	acpi_table_lpit *lpit;
 	struct device *dev;
 	unsigned long fw;
 	size_t slic_size, dsdt_size;
@@ -1489,6 +1562,18 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += madt->header.length;
 		acpi_add_table(rsdp, madt);
 	}
+
+	if (CONFIG(ACPI_LPIT)) {
+		printk(BIOS_DEBUG, "ACPI:     * LPIT\n");
+
+		lpit = (acpi_table_lpit *)current;
+		acpi_create_lpit_generator(lpit);
+		if (lpit->header.length >= sizeof(acpi_table_lpit)) {
+			current += lpit->header.length;
+			acpi_add_table(rsdp, lpit);
+		}
+	}
+
 	current = acpi_align_current(current);
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);

src/drivers/i2c/tas5825m/Kconfig

@@ -0,0 +1,5 @@
+config DRIVERS_I2C_TAS5825M
+	bool
+	default n
+	help
+	  Enable support for TI TAS5825M Amplifier.

src/drivers/i2c/tas5825m/Makefile.inc

@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += tas5825m.c

src/drivers/i2c/tas5825m/chip.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+struct drivers_i2c_tas5825m_config {
+    // Used to uniquely identify the AMP
+    int id;
+};

src/drivers/i2c/tas5825m/tas5825m.c

@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include "chip.h"
+#include "tas5825m.h"
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) {
+	return smbus_write_byte(dev, addr, value);
+}
+
+//TODO: use I2C block write for better performance
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length) {
+	int res = 0;
+	for (uint8_t i = 0; i < length; i++) {
+		res = smbus_write_byte(dev, addr + i, values[i]);
+		if (res < 0) return res;
+	}
+	return (int)length;
+}
+
+int tas5825m_set_page(struct device *dev, uint8_t page) {
+	return tas5825m_write_at(dev, 0x00, page);
+}
+
+int tas5825m_set_book(struct device *dev, uint8_t book) {
+	int res = tas5825m_set_page(dev, 0x00);
+	if (res < 0) return res;
+	return tas5825m_write_at(dev, 0x7F, book);
+}
+
+__weak int tas5825m_setup(struct device *dev, int id) {
+	printk(BIOS_ERR, "tas5825m: setup not implemented\n");
+	return -1;
+}
+
+static void tas5825m_init(struct device *dev) {
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C &&
+		ops_smbus_bus(get_pbus_smbus(dev))) {
+		printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev));
+
+		struct drivers_i2c_tas5825m_config *config = dev->chip_info;
+		if (config) {
+			printk(BIOS_DEBUG, "tas5825m id %d\n", config->id);
+			int res = tas5825m_setup(dev, config->id);
+			if (res) {
+				printk(BIOS_ERR, "tas5825m init failed: %d\n", res);
+			} else {
+				printk(BIOS_DEBUG, "tas5825m init successful\n");
+			}
+		} else {
+			printk(BIOS_ERR, "tas5825m: failed to find config\n");
+		}
+
+	}
+}
+
+static struct device_operations tas5825m_operations = {
+	.read_resources		= noop_read_resources,
+	.set_resources		= noop_set_resources,
+	.init			= tas5825m_init,
+};
+
+static void tas5825m_enable_dev(struct device *dev) {
+	dev->ops = &tas5825m_operations;
+}
+
+struct chip_operations drivers_i2c_tas5825m_ops = {
+	CHIP_NAME("TI TAS5825M Amplifier")
+	.enable_dev = tas5825m_enable_dev,
+};

src/drivers/i2c/tas5825m/tas5825m.h

@@ -0,0 +1,12 @@
+#ifndef TAS5825M_H
+#define TAS5825M_H
+
+#include <device/device.h>
+
+int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value);
+int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length);
+int tas5825m_set_page(struct device *dev, uint8_t page);
+int tas5825m_set_book(struct device *dev, uint8_t book);
+int tas5825m_setup(struct device *dev, int id);
+
+#endif // TAS5825M_H

src/drivers/intel/gma/acpi/configure_brightness_levels.asl

@@ -148,7 +148,7 @@
 	{
 		If (LEqual(^BOX3.XBCM (Arg0), Ones))
 		{
-			^LEGA.XBCM (Arg0)
+			//TODO: fix Windows initial setup ^LEGA.XBCM (Arg0)
 		}
 	}
 

src/drivers/system76/dgpu/Kconfig

@@ -0,0 +1,12 @@
+config DRIVERS_SYSTEM76_DGPU
+	bool
+	default n
+	help
+		System76 switchable graphics support
+
+#TODO: make this cleaner, use device tree?
+config DRIVERS_SYSTEM76_DGPU_DEVICE
+	hex
+	default 0x01
+	help
+		System76 switchable graphics root device number

src/drivers/system76/dgpu/Makefile.inc

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-$(CONFIG_DRIVERS_SYSTEM76_DGPU) += ramstage.c

src/drivers/system76/dgpu/acpi/dgpu.asl

@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (\_SB.PCI0.PEGP) {
+	Name (_ADR, CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON) {
+			Debug = "PEGP.PWRR._ON"
+			If (_STA != 1) {
+				\_SB.PCI0.PEGP.DEV0._ON ()
+				_STA = 1
+			}
+		}
+
+		Method (_OFF) {
+			Debug = "PEGP.PWRR._OFF"
+			If (_STA != 0) {
+				\_SB.PCI0.PEGP.DEV0._OFF ()
+				_STA = 0
+			}
+		}
+	}
+
+	Name (_PR0, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR2, Package () { \_SB.PCI0.PEGP.PWRR })
+	Name (_PR3, Package () { \_SB.PCI0.PEGP.PWRR })
+}
+
+Device (\_SB.PCI0.PEGP.DEV0) {
+	Name(_ADR, 0x00000000)
+	Name (_STA, 0xF)
+	Name (LTRE, 0)
+
+	// Memory mapped PCI express registers
+	// Not sure what this stuff is, but it is used to get into GC6
+	OperationRegion (RPCX, SystemMemory, CONFIG_MMCONF_BASE_ADDRESS + 0x8000, 0x1000)
+	Field (RPCX, ByteAcc, NoLock, Preserve) {
+		PVID,   16,
+		PDID,   16,
+		CMDR,   8,
+		Offset (0x19),
+		PRBN,   8,
+		Offset (0x84),
+		D0ST,   2,
+		Offset (0xAA),
+		CEDR,   1,
+		Offset (0xAC),
+			,   4,
+		CMLW,   6,
+		Offset (0xB0),
+		ASPM,   2,
+			,   2,
+		P0LD,   1,
+		RTLK,   1,
+		Offset (0xC9),
+			,   2,
+		LREN,   1,
+		Offset (0x11A),
+			,   1,
+		VCNP,   1,
+		Offset (0x214),
+		Offset (0x216),
+		P0LS,   4,
+		Offset (0x248),
+			,   7,
+		Q0L2,   1,
+		Q0L0,   1,
+		Offset (0x504),
+		Offset (0x506),
+		PCFG,   2,
+		Offset (0x508),
+		TREN,   1,
+		Offset (0xC20),
+			,   4,
+		P0AP,   2,
+		Offset (0xC38),
+			,   3,
+		P0RM,   1,
+		Offset (0xC74),
+		P0LT,   4,
+		Offset (0xD0C),
+			,   20,
+		LREV,   1
+	}
+
+	Method (_ON) {
+		Debug = "PEGP.DEV0._ON"
+
+		If (_STA != 0xF) {
+			Debug = "  If DGPU_PWR_EN low"
+			If (! GTXS (DGPU_PWR_EN)) {
+				Debug = "    DGPU_PWR_EN high"
+				STXS (DGPU_PWR_EN)
+
+				Debug = "    Sleep 16"
+				Sleep (16)
+			}
+
+			Debug = "  DGPU_RST_N high"
+			STXS(DGPU_RST_N)
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  Q0L0 = 1"
+			Q0L0 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L0"
+			Local0 = 0
+			While (Q0L0) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L0 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 0"
+			P0RM = 0
+
+			Debug = "  P0AP = 0"
+			P0AP = 0
+
+			Debug = Concatenate("  LREN = ", ToHexString(LTRE))
+			LREN = LTRE
+
+			Debug = "  CEDR = 1"
+			CEDR = 1
+
+			Debug = "  CMDR |= 7"
+			CMDR |= 7
+
+			Debug = "  _STA = 0xF"
+			_STA = 0xF
+		}
+	}
+
+	Method (_OFF) {
+		Debug = "PEGP.DEV0._OFF"
+
+		If (_STA != 0x5) {
+			Debug = Concatenate("  LTRE = ", ToHexString(LREN))
+			LTRE = LREN
+
+			Debug = "  Q0L2 = 1"
+			Q0L2 = 1
+
+			Debug = "  Sleep 16"
+			Sleep (16)
+
+			Debug = "  While Q0L2"
+			Local0 = Zero
+			While (Q0L2) {
+				If ((Local0 > 4)) {
+					Debug = "    While Q0L2 timeout"
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  P0RM = 1"
+			P0RM = 1
+
+			Debug = "  P0AP = 3"
+			P0AP = 3
+
+			Debug = "  Sleep 10"
+			Sleep (10)
+
+			Debug = "  DGPU_RST_N low"
+			CTXS(DGPU_RST_N)
+
+			Debug = "  While DGPU_GC6 low"
+			Local0 = Zero
+			While (! GRXS(DGPU_GC6)) {
+				If ((Local0 > 4)) {
+					Debug = "    While DGPU_GC6 low timeout"
+
+					Debug = "    DGPU_PWR_EN low"
+					CTXS (DGPU_PWR_EN)
+					Break
+				}
+
+				Sleep (16)
+				Local0++
+			}
+
+			Debug = "  _STA = 0x5"
+			_STA = 0x5
+		}
+	}
+}

src/drivers/system76/dgpu/bootblock.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: do not require this to be included in mainboard bootblock.c
+
+#include <console/console.h>
+#include <delay.h>
+#include <gpio.h>
+
+static void dgpu_power_enable(int onoff) {
+	printk(BIOS_DEBUG, "system76: DGPU power %d\n", onoff);
+	if (onoff) {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 1);
+		mdelay(4);
+		gpio_set(DGPU_RST_N, 1);
+	} else {
+		gpio_set(DGPU_RST_N, 0);
+		mdelay(4);
+		gpio_set(DGPU_PWR_EN, 0);
+	}
+	mdelay(50);
+}

src/drivers/system76/dgpu/ramstage.c

@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <device/pci.h>
+
+static void dgpu_read_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_read_resources %s\n", dev_path(dev));
+
+    pci_dev_read_resources(dev);
+
+	int bar;
+	// Find all BARs on DGPU, mark them above 4g if prefetchable
+	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		printk(BIOS_INFO, "  BAR at 0x%02x\n", bar);
+
+	    struct resource *res;
+		res = probe_resource(dev, bar);
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "    marked above 4g\n");
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_INFO, "    not prefetch\n");
+			}
+		} else {
+			printk(BIOS_INFO, "    not found\n");
+		}
+	}
+}
+
+static void dgpu_enable_resources(struct device *dev) {
+	printk(BIOS_INFO, "system76: dgpu_enable_resources %s\n", dev_path(dev));
+
+	dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID;
+	dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID;
+	printk(BIOS_INFO, "  subsystem <- %04x/%04x\n", dev->subsystem_vendor, dev->subsystem_device);
+	pci_write_config32(dev, 0x40, ((dev->subsystem_device & 0xffff) << 16) | (dev->subsystem_vendor & 0xffff));
+
+	pci_dev_enable_resources(dev);
+}
+
+static struct device_operations dgpu_pci_ops_dev = {
+	.read_resources   = dgpu_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = dgpu_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+static void dgpu_above_4g(void *unused) {
+	struct device *pdev;
+
+	// Find PEGP
+	pdev = pcidev_on_root(CONFIG_DRIVERS_SYSTEM76_DGPU_DEVICE, 0);
+	if (!pdev) {
+		printk(BIOS_ERR, "system76: failed to find PEGP\n");
+		return;
+	}
+	printk(BIOS_INFO, "system76: PEGP at %p, %04x:%04x\n", pdev, pdev->vendor, pdev->device);
+
+    int fn;
+    for (fn = 0; fn < 8; fn++) {
+	    struct device *dev;
+
+        // Find DGPU functions
+        dev = pcidev_path_behind(pdev->link_list, PCI_DEVFN(0, fn));
+        if (dev) {
+            printk(BIOS_INFO, "system76: DGPU fn %d at %p, %04x:%04x\n", fn, dev, dev->vendor, dev->device);
+            dev->ops = &dgpu_pci_ops_dev;
+        } else {
+            printk(BIOS_ERR, "system76: failed to find DGPU fn %d\n", fn);
+        }
+    }
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, dgpu_above_4g, NULL);

src/ec/system76/ec/Kconfig

@@ -12,3 +12,13 @@ config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	depends on EC_SYSTEM76_EC
 	bool
 	default n
+
+config EC_SYSTEM76_EC_DGPU
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
+config EC_SYSTEM76_EC_OLED
+	depends on EC_SYSTEM76_EC
+	bool
+	default n

src/ec/system76/ec/acpi/battery.asl

@@ -30,29 +30,29 @@ Device (BAT0)
 
 	Name (PBIF, Package (0x0D)
 	{
-		One,
-		0xFFFFFFFF,
-		0xFFFFFFFF,
-		One,
-		0x39D0,
-		Zero,
-		Zero,
-		0x40,
-		0x40,
-		"BAT",
-		"0001",
-		"LION",
-		"Notebook"
+		One, // 0 - Power Unit
+		0xFFFFFFFF, // 1 - Design Capacity
+		0xFFFFFFFF, // 2 - Last Full Charge Capacity
+		One, // 3 - Battery Technology
+		0xFFFFFFFF, // 4 - Design Voltage
+		Zero, // 5 - Design Capacity of Warning
+		Zero, // 6 - Design Capacity of Low
+		0x40, // 7 - Battery Capacity Granularity 1
+		0x40, // 8 - Battery Capacity Granularity 2
+		" ", // 9 - Model Number
+		" ", // 10 - Serial Number
+		" ", // 11 - Battery Type
+		" " // 12 - OEM Information
 	})
 	Method (IVBI, 0, NotSerialized)
 	{
-		PBIF [One] = 0xFFFFFFFF
-		PBIF [0x02] = 0xFFFFFFFF
-		PBIF [0x04] = 0xFFFFFFFF
-		PBIF [0x09] = " "
-		PBIF [0x0A] = " "
-		PBIF [0x0B] = " "
-		PBIF [0x0C] = " "
+		PBIF [1] = 0xFFFFFFFF
+		PBIF [2] = 0xFFFFFFFF
+		PBIF [4] = 0xFFFFFFFF
+		PBIF [9] = " "
+		PBIF [10] = " "
+		PBIF [11] = " "
+		PBIF [12] = " "
 		BFCC = Zero
 	}
 
@@ -61,20 +61,20 @@ Device (BAT0)
 		If (^^PCI0.LPCB.EC0.BAT0)
 		{
 			Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF)
-			PBIF [One] = Local0
+			PBIF [1] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF)
-			PBIF [0x02] = Local0
+			PBIF [2] = Local0
 			BFCC = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF)
-			PBIF [0x04] = Local0
+			PBIF [4] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF)
-			PBIF [0x05] = Local0
+			PBIF [5] = Local0
 			Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF)
-			PBIF [0x06] = Local0
-			PBIF [0x09] = "BAT"
-			PBIF [0x0A] = "0001"
-			PBIF [0x0B] = "LION"
-			PBIF [0x0C] = "Notebook"
+			PBIF [6] = Local0
+			PBIF [9] = "BAT"
+			PBIF [10] = "0001"
+			PBIF [11] = "LION"
+			PBIF [12] = "Notebook"
 		}
 		Else
 		{
@@ -98,17 +98,17 @@ Device (BAT0)
 
 	Name (PBST, Package (0x04)
 	{
-		Zero,
-		0xFFFFFFFF,
-		0xFFFFFFFF,
-		0x3D90
+		Zero, // 0 - Battery state
+		0xFFFFFFFF, // 1 - Battery present rate
+		0xFFFFFFFF, // 2 - Battery remaining capacity
+		0xFFFFFFFF // 3 - Battery present voltage
 	})
 	Method (IVBS, 0, NotSerialized)
 	{
-		PBST [Zero] = Zero
-		PBST [One] = 0xFFFFFFFF
-		PBST [0x02] = 0xFFFFFFFF
-		PBST [0x03] = 0x2710
+		PBST [0] = Zero
+		PBST [1] = 0xFFFFFFFF
+		PBST [2] = 0xFFFFFFFF
+		PBST [3] = 0xFFFFFFFF
 	}
 
 	Method (UPBS, 0, NotSerialized)
@@ -139,10 +139,10 @@ Device (BAT0)
 
 			Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF)
 			Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF)
-			PBST [Zero] = Local0
-			PBST [One] = Local1
-			PBST [0x02] = Local2
-			PBST [0x03] = Local3
+			PBST [0] = Local0
+			PBST [1] = Local1
+			PBST [2] = Local2
+			PBST [3] = Local3
 			If ((BFCC != ^^PCI0.LPCB.EC0.BFC0))
 			{
 				Notify (BAT0, 0x81) // Information Change

src/ec/system76/ec/acpi/ec.asl

@@ -62,9 +62,13 @@ Device (\_SB.PCI0.LPCB.EC0)
 		}
 	}
 
+	Name (S3OS, Zero)
 	Method (PTS, 1, Serialized) {
 		Debug = Concatenate("EC: PTS: ", ToHexString(Arg0))
 		If (ECOK) {
+			// Save ECOS during sleep
+			S3OS = ECOS
+
 			// Clear wake cause
 			WFNO = Zero
 		}
@@ -73,6 +77,9 @@ Device (\_SB.PCI0.LPCB.EC0)
 	Method (WAK, 1, Serialized) {
 		Debug = Concatenate("EC: WAK: ", ToHexString(Arg0))
 		If (ECOK) {
+			// Restore ECOS after sleep
+			ECOS = S3OS
+
 			// Set current AC state
 			^^^^AC.ACFG = ADP
 
@@ -97,6 +104,9 @@ Device (\_SB.PCI0.LPCB.EC0)
 	Method (_Q0B, 0, NotSerialized) // Screen Toggle
 	{
 		Debug = "EC: Screen Toggle"
+#if CONFIG(EC_SYSTEM76_EC_OLED)
+		Notify (^^^^S76D, 0x85)
+#endif // CONFIG(EC_SYSTEM76_EC_OLED)
 	}
 
 	Method (_Q0C, 0, NotSerialized)  // Mute

src/ec/system76/ec/acpi/ec_ram.asl

@@ -3,168 +3,47 @@
 OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
 Field (ERAM, ByteAcc, Lock, Preserve)
 {
-	NMSG,   8,
-	SLED,   4,
-	Offset (0x02),
-	MODE,   1,
-	FAN0,   1,
-	TME0,   1,
-	TME1,   1,
-	FAN1,   1,
-		,   2,
 	Offset (0x03),
-	LSTE,   1,
-	LSW0,   1,
-	LWKE,   1,
-	WAKF,   1,
-		,   2,
-	PWKE,   1,
-	MWKE,   1,
-	AC0,    8,
-	PSV,    8,
-	CRT,    8,
-	TMP,    8,
-	AC1,    8,
-	BBST,   8,
-	Offset (0x0B),
-	Offset (0x0C),
-	Offset (0x0D),
-	Offset (0x0E),
-	SLPT,   8,
-	SWEJ,   1,
-	SWCH,   1,
+	LSTE,   1, // Lid is open
+	    ,   1,
+	LWKE,   1, // Lid wake
+		,   5,
+	Offset (0x07),
+	TMP1,	8, // CPU temperature
 	Offset (0x10),
-	ADP,    1,
-	AFLT,   1,
-	BAT0,   1,
-	BAT1,   1,
-		,   3,
-	PWOF,   1,
-	WFNO,   8,
-	BPU0,   32,
-	BDC0,   32,
-	BFC0,   32,
-	BTC0,   32,
-	BDV0,   32,
-	BST0,   32,
-	BPR0,   32,
-	BRC0,   32,
-	BPV0,   32,
-	BTP0,   16,
-	BRS0,   16,
-	BCW0,   32,
-	BCL0,   32,
-	BCG0,   32,
-	BG20,   32,
-	BMO0,   64,
-	BIF0,   64,
-	BSN0,   32,
-	BTY0,   64,
-	Offset (0x67),
+	ADP,    1, // AC adapter connected
+	    ,   1,
+	BAT0,   1, // Battery connected
+	    ,   5,
+	WFNO,   8, // Wake cause (not implemented)
+	Offset (0x16),
+	BDC0,   32, // Battery design capacity
+	BFC0,   32, // Battery full capacity
+	Offset (0x22),
+	BDV0,   32, // Battery design voltage
+	BST0,   32, // Battery status
+	BPR0,   32, // Battery current
+	BRC0,   32, // Battery remaining capacity
+	BPV0,   32, // Battery voltage
+	Offset (0x3A),
+    BCW0,   32,
+    BCL0,   32,
 	Offset (0x68),
-	ECOS,   8,
-	LNXD,   8,
-	ECPS,   8,
-	Offset (0x6C),
-	BTMP,   16,
-	EVTN,   8,
-	Offset (0x72),
-	PRCL,   8,
-	PRC0,   8,
-	PRC1,   8,
-	PRCM,   8,
-	PRIN,   8,
-	PSTE,   8,
-	PCAD,   8,
-	PEWL,   8,
-	PWRL,   8,
-	PECD,   8,
-	PEHI,   8,
-	PECI,   8,
-	PEPL,   8,
-	PEPM,   8,
-	PWFC,   8,
-	PECC,   8,
-	PDT0,   8,
-	PDT1,   8,
-	PDT2,   8,
-	PDT3,   8,
-	PRFC,   8,
-	PRS0,   8,
-	PRS1,   8,
-	PRS2,   8,
-	PRS3,   8,
-	PRS4,   8,
-	PRCS,   8,
-	PEC0,   8,
-	PEC1,   8,
-	PEC2,   8,
-	PEC3,   8,
-	CMDR,   8,
-	CVRT,   8,
-	GTVR,   8,
-	FANT,   8,
-	SKNT,   8,
-	AMBT,   8,
-	MCRT,   8,
-	DIM0,   8,
-	DIM1,   8,
-	PMAX,   8,
-	PPDT,   8,
-	PECH,   8,
-	PMDT,   8,
-	TSD0,   8,
-	TSD1,   8,
-	TSD2,   8,
-	TSD3,   8,
-	CPUP,   16,
-	MCHP,   16,
-	SYSP,   16,
-	CPAP,   16,
-	MCAP,   16,
-	SYAP,   16,
-	CFSP,   16,
-	CPUE,   16,
-	Offset (0xC6),
-	Offset (0xC7),
-	VGAT,   8,
+	ECOS,   8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver
+	Offset (0xC8),
 	OEM1,   8,
 	OEM2,   8,
 	OEM3,   16,
-	OEM4,   8,
-	Offset (0xCE),
-	DUT1,   8,
-	DUT2,   8,
-	RPM1,   16,
-	RPM2,   16,
-	RPM4,   16,
-	Offset (0xD7),
-	DTHL,   8,
-	DTBP,   8,
-	AIRP,   8,
-	WINF,   8,
-	RINF,   8,
-	Offset (0xDD),
-	INF2,   8,
-	MUTE,   1,
-	Offset (0xE0),
-	RPM3,   16,
-	ECKS,   8,
-	Offset (0xE4),
-		,   4,
-	XTUF,   1,
-	EP12,   1,
-	Offset (0xE5),
-	INF3,   8,
-	Offset (0xE7),
-	GFOF,   8,
-	Offset (0xE9),
-	KPCR,   1,
-	Offset (0xEA),
-	Offset (0xF0),
-	PL1T,   16,
-	PL2T,   16,
-	TAUT,   8,
+	OEM4,   8, // Extra SCI data
+	Offset (0xCD),
+	TMP2,   8, // GPU temperature
+	DUT1,   8, // Fan 1 duty
+	DUT2,   8, // Fan 2 duty
+	RPM1,   16, // Fan 1 RPM
+	RPM2,   16, // Fan 2 RPM
+	Offset (0xD9),
+	AIRP,   8, // Airplane mode LED
+	WINF,   8, // Enable ACPI brightness controls
 	Offset (0xF8),
 	FCMD,   8,
 	FDAT,   8,

src/ec/system76/ec/acpi/s76.asl

@@ -6,6 +6,7 @@
 //   0x82 - backlight down
 //   0x83 - backlight up
 //   0x84 - backlight color change
+//   0x85 - OLED screen toggle
 Device (S76D) {
 	Name (_HID, "17761776")
 	Name (_UID, 0)
@@ -111,4 +112,57 @@ Device (S76D) {
 		}
 	}
 #endif // CONFIG(EC_SYSTEM76_EC_COLOR_KEYBOARD)
+
+	// Fan names
+	Method (NFAN, 0, Serialized) {
+		Return (Package (2) {
+			"CPU fan",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU fan",
+#endif // CONFIG(EC_SYSTEM76_EC_DGPU)
+		})
+	}
+
+	// Get fan duty and RPM as a single value
+	Method (GFAN, 1, Serialized) {
+		Local0 = 0
+		Local1 = 0
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT1
+				Local1 = ^^PCI0.LPCB.EC0.RPM1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.DUT2
+				Local1 = ^^PCI0.LPCB.EC0.RPM2
+			}
+		}
+		If (Local1 != 0) {
+			// 60 * (EC frequency / 120) / 2
+			Local1 = 2156250 / Local1
+		}
+		Return ((Local1 << 8) | Local0)
+	}
+
+	// Temperature names
+	Method (NTMP, 0, Serialized) {
+		Return (Package (2) {
+			"CPU temp",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU temp",
+#endif // CONFIG(EC_SYSTEM76_EC_DGPU)
+		})
+	}
+
+	// Get temperature
+	Method (GTMP, 1, Serialized) {
+		Local0 = 0;
+		If (^^PCI0.LPCB.EC0.ECOK) {
+			If (Arg0 == 0) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP1
+			} ElseIf (Arg0 == 1) {
+				Local0 = ^^PCI0.LPCB.EC0.TMP2
+			}
+		}
+		Return (Local0)
+	}
 }

src/include/acpi/acpi.h

@@ -257,6 +257,63 @@ typedef struct acpi_madt {
 	u32 flags;			/* Multiple APIC flags */
 } __packed acpi_madt_t;
 
+/*******************************************************************************
+ *
+ * LPIT - Low Power Idle Table
+ *
+ * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014.
+ *
+ ******************************************************************************/
+
+typedef struct acpi_lpi_state_flags {
+	u32 disabled:1;
+	u32 counterunavailable:1;
+	u32 reserved:30;
+} __packed acpi_lpi_state_flags;
+
+/* LPIT subtable header */
+
+typedef struct acpi_lpit_header {
+	u32 type;               /* Subtable type */
+	u32 length;             /* Subtable length */
+	u16 unique_id;
+	u16 reserved;
+	acpi_lpi_state_flags flags;
+} __packed acpi_lpit_header;
+
+/* Values for subtable Type above */
+
+enum acpi_lpit_type {
+	ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
+	ACPI_LPIT_TYPE_RESERVED = 0x01  /* 1 and above are reserved */
+};
+
+/* Masks for Flags field above  */
+
+#define ACPI_LPIT_STATE_DISABLED    (1)
+#define ACPI_LPIT_NO_COUNTER        (1<<1)
+
+/*
+ * LPIT subtables, correspond to Type in struct acpi_lpit_header
+ */
+
+/* 0x00: Native C-state instruction based LPI structure */
+
+struct acpi_lpit_native {
+	struct acpi_lpit_header header;
+	struct acpi_gen_regaddr entry_trigger;
+	u32 residency;
+	u32 latency;
+	struct acpi_gen_regaddr residency_counter;
+	u64 counter_frequency;
+};
+
+typedef struct acpi_table_lpit {
+	struct acpi_table_header header;        /* Common ACPI table header */
+	struct acpi_lpit_native lpit_soc;
+	struct acpi_lpit_native lpit_system;
+} __packed acpi_table_lpit;
+
 /* VFCT image header */
 typedef struct acpi_vfct_image_hdr {
 	u32 PCIBus;
@@ -897,6 +954,9 @@ struct acpi_spmi {
 
 unsigned long fw_cfg_acpi_tables(unsigned long start);
 
+void soc_residency_counter(struct acpi_lpit_native *lpit_soc);
+void system_residency_counter(struct acpi_lpit_native *lpit_system);
+
 /* These are implemented by the target port or north/southbridge. */
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);

src/mainboard/system76/addw1/Kconfig

@@ -0,0 +1,80 @@
+if BOARD_SYSTEM76_ADDW1
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COFFEELAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/addw1"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "addw1"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Adder WS"
+
+config MAINBOARD_VERSION
+	string
+	default "addw1"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/addw1/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW1
+	bool "addw1"

src/mainboard/system76/addw1/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/addw1/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/addw1/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/addw1/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: addw1
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/addw1/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/addw1/devicetree.cb

@@ -0,0 +1,332 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Disable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+	register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "0"
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "0"
+	register "PchHdaAudioLinkDmic1" = "0"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 9 (SSD1)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[9]" = "8"
+
+	# PCI Express root port #14 x1, Clock 5 (GLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[5]" = "13"
+
+	# PCI Express root port #15 x1, Clock 7 (Card Reader)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[7]" = "14"
+
+	# PCI Express root port #16 x1, Clock 6 (WLAN)
+	register "PcieRpEnable[15]" = "1"
+	register "PcieRpLtrEnable[15]" = "1"
+	register "PcieClkSrcUsage[6]" = "15"
+
+	# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+	register "PcieRpEnable[16]" = "1"
+	register "PcieRpLtrEnable[16]" = "1"
+	register "PcieRpHotPlug[16]" = "1"
+	register "PcieClkSrcUsage[0]" = "16"
+
+	# PCI Express root port #21 x4, Clock 10 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[10]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Disable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x65e1 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on  end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 on  end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+		end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/addw1/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/addw1/gpio.h

@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_C12
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK), // NC
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // NC
+		PAD_CFG_GPI(GPD7, NONE, PWROK), // NC
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
+		PAD_CFG_NF(GPD9, NONE, PWROK, NF1), // NC
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000), // NC
+		PAD_CFG_NF(GPD11, NONE, DEEP, NF1), // NC
+		PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), // SB_KBCRST#
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
+		PAD_CFG_GPI(GPP_A7, NONE, DEEP), // SCI#_GPP_A7
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // ECCLKRUN#
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // NC
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN#
+		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP), // NC
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP), // AMP_TYPE_DET
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), // SB_BLON
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP), // PEX_WAKE#
+		PAD_CFG_GPI(GPP_A21, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // SMARTAMP_SW
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP), // SMART AMP PWR (L:3.3VS H:3.3V)
+		PAD_CFG_GPI(GPP_B0, NONE, DEEP), // TPM_PIRQ#
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP), // NC
+		PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), // PCH_GPP_B3 (touchpad interrupt)
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B7, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // GLAN_CLKREQ#
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), // PLT_RST#
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT STRAP
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B20, NONE, DEEP), // SMI#_GPP_B20
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT BIOS STRAP
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP), // DCI-OOB STRAP
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+		_PAD_CFG_STRUCT(GPP_C2, 0x40880100, 0x0000), // CNVI_WAKE#
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP), // WLAN_WAKEUP#
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID2
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP), //  BOARD_ID1
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_C13, NONE, DEEP), // TPM_DET
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP), // GPU_EVENT#
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP), // 100K pull-down
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // TP_DAT_PCH_I2C0
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // TP_CLK_PCH_I2C0
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C1_SDA
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C1_SCL
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+		PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), // UART2_RTS#
+		PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), // UART2_CTS#
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // NC
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // NC
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // SATA_DEVSLP1
+		PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP), // PCH_MUTE#
+		PAD_CFG_GPI(GPP_E7, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATAHDD_LED#
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_F3, 1, NONE, DEEP), // GPP_F3_LAN_RST#
+		PAD_CFG_TERM_GPO(GPP_F4, 1, NONE, DEEP), // GPP_F4_TBT_RST#
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS RECOVERY ENABLE STRAP
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP), // GSYNC_DET
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP), // NVSR_DET#
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP), // SWI#_GPP_G6
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SD4.0_CLKREQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+		PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+		PAD_CFG_GPI(GPP_H5, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
+		PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP), // GPP_H8_LAN_RST#
+		PAD_CFG_GPI(GPP_H9, NONE, DEEP), // TBT_GPIO_WAKE#
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP), // ESPI FLASH SHARING STRAP
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP), // RESERVED STRAP
+		_PAD_CFG_STRUCT(GPP_H16, 0x44000101, 0x0000), // TBT_RTD3_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, PLTRST), // TBT_FORCE_PWR
+		PAD_CFG_TERM_GPO(GPP_H18, 1, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_H20, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP), // XTAL FREQUENCY SELECT STRAP
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT#
+		PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), // ANX7411_HPD
+		PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD
+		PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD
+		PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // MDP_A_TBT_HPD
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
+		PAD_CFG_TERM_GPO(GPP_I5, 1, NONE, DEEP), // TBT_GPIO_RST#
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP), // SATA_PWR_EN
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPP_J1
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP), // NC
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), // GPP_K0_SPK_MUTE
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), // GPP_K1_WOOFER_MUTE
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), // SCI#_GPP_K3
+		PAD_CFG_GPI(GPP_K4, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_GPP_K6
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP), // GPP_K7_LAN_WAKEUP#
+		PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), // GPP_K8_LAN_RTD3
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K12, 1, NONE, DEEP), // PCH_GPP_K12
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), // GPP_K14_TEST_R
+		_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000), // GPP_K15_INTP_OUT
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP), // NC
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP), // GPP_K18_TBT_WAKE#
+		_PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), // SMI#_GPP_K19
+		PAD_CFG_GPI(GPP_K20, NONE, DEEP), // NC
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP), // NC
+		_PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000), // NC
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP), // NC
+};
+
+#endif
+
+#endif

src/mainboard/system76/addw1/hda_verb.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865d1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865d1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/addw1/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/addw1/romstage.c

@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+ 	.rcomp_targets = { 50, 25, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd) {
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/addw2/Kconfig

@@ -0,0 +1,88 @@
+if BOARD_SYSTEM76_ADDW2
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select EC_SYSTEM76_EC_OLED
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/addw2"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "addw2"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Adder WS"
+
+config MAINBOARD_VERSION
+	string
+	default "addw2"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 16
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9bc4.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9bc4"
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/addw2/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_ADDW2
+	bool "addw2"

src/mainboard/system76/addw2/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/addw2/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/addw2/acpi/mainboard.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "../gpio.h"
+#include <drivers/system76/dgpu/acpi/dgpu.asl>
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#define EC_COLOR_KEYBOARD 1
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/addw2/acpi/sleep.asl

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+
+	// Turn DGPU on before sleeping
+	\_SB.PCI0.PEGP.DEV0._ON()
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/addw2/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: addw2
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/addw2/bootblock.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <drivers/system76/dgpu/bootblock.c>
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	dgpu_power_enable(1);
+}

src/mainboard/system76/addw2/devicetree.cb

@@ -0,0 +1,332 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Disable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 45,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 90,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+	register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "0"
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "0"
+	register "PchHdaAudioLinkDmic1" = "0"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2
+	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT)
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock  (NVIDIA GPU)
+	register "PcieClkSrcUsage[8]" = "0x40"
+
+	# PCI Express root port #9 x4, Clock 9 (SSD1)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[9]" = "8"
+
+	# PCI Express root port #14 x1, Clock 5 (GLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[5]" = "13"
+
+	# PCI Express root port #15 x1, Clock 7 (Card Reader)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[7]" = "14"
+
+	# PCI Express root port #16 x1, Clock 6 (WLAN)
+	register "PcieRpEnable[15]" = "1"
+	register "PcieRpLtrEnable[15]" = "1"
+	register "PcieClkSrcUsage[6]" = "15"
+
+	# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
+	register "PcieRpEnable[16]" = "1"
+	register "PcieRpLtrEnable[16]" = "1"
+	register "PcieRpHotPlug[16]" = "1"
+	register "PcieClkSrcUsage[0]" = "16"
+
+	# PCI Express root port #21 x4, Clock 10 (SSD2)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[10]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Disable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x65e1 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A14_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on  end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 on  end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+		end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/addw2/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/addw2/gpio.h

@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#define DGPU_RST_N GPP_F22
+#define DGPU_PWR_EN GPP_F23
+#define DGPU_GC6 GPP_K21
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD7, NONE, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+		_PAD_CFG_STRUCT(GPD10, 0x04000601, 0x0000),
+		PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A0, NONE, DEEP),
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+		PAD_CFG_GPI_APIC(GPP_A14, NONE, PLTRST, EDGE_SINGLE, INVERT), // TCHPD_INT#
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A16, DN_20K, DEEP),
+		PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_A21, 0x46080100, 0x0000),
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000),
+		PAD_CFG_GPI(GPP_B1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B6, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B9, NONE, DEEP),
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B11, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B18, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B19, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_B20, 0x42840101, 0x0000),
+		PAD_CFG_GPI(GPP_B21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B23, NONE, DEEP),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C11, NONE, DEEP), // TBT_DET#
+		PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH
+		PAD_CFG_GPI(GPP_C13, NONE, PLTRST),
+		PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_GPI(GPP_D7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D8, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D16, NONE, DEEP),
+		PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D22, NONE, DEEP),
+		PAD_CFG_GPI(GPP_D23, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+		PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_E6, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_E9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP), // GPP_F3_LAN_RST#
+		PAD_CFG_GPI(GPP_F4, NONE, DEEP), // GPP_F4_TBT_RST#
+		PAD_CFG_GPI(GPP_F5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F7, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), // PS8331_SW
+		PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+		PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+		PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
+		PAD_CFG_GPI(GPP_G0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G3, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G4, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G5, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_G7, NONE, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CR_CLKREQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ#
+		PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ#
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD2_CLKREQ#
+		PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H6, 1, NONE, DEEP), // PCIE_SSD1_RST#
+		PAD_CFG_TERM_GPO(GPP_H7, 1, NONE, DEEP), // PCIE_SSD2_RST#
+		PAD_CFG_GPI(GPP_H8, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H9, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H13, NONE, DEEP), // TBTA_HRESET
+		PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, DEEP), // TBT_RTD3_PWR_EN_R
+		PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
+		PAD_CFG_GPI(GPP_H18, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H21, NONE, DEEP),
+		PAD_CFG_GPI(GPP_H22, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_H23, 0x82880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 1, UP_20K, PLTRST), // TBT_GPIO_RST#
+		PAD_CFG_GPI(GPP_I6, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I8, 1, NONE, DEEP), // SSD1_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP), // SSD2_PWR_EN
+		PAD_CFG_GPI(GPP_I10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I13, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, NONE, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J2, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J3, NONE, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_J11, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K2, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_K4, 0x44000101, 0x0000),
+		PAD_CFG_GPI(GPP_K5, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000),
+		PAD_CFG_GPI(GPP_K7, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K10, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K11, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K13, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		_PAD_CFG_STRUCT(GPP_K15, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_K16, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K17, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K20, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K23, NONE, DEEP),
+};
+
+#endif
+
+#endif

src/mainboard/system76/addw2/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x155865e1, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155865e1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x15, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/addw2/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/addw2/romstage.c

@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+ 	.rcomp_targets = { 50, 25, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd) {
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/bonw14/Kconfig

@@ -0,0 +1,82 @@
+if BOARD_SYSTEM76_BONW14
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_TAS5825M
+	select DRIVERS_SYSTEM76_DGPU
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_CANNONLAKE_PCH_H
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+# Hack for correct FSP headers until coreboot is updated
+config FSP_HEADER_PATH
+	default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/"
+
+# Hack for correct FSP blobs until coreboot is updated
+config FSP_FD_PATH
+	default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/FSP.fd"
+
+config MAINBOARD_DIR
+	string
+	default "system76/bonw14"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "bonw14"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Bonobo WS"
+
+config MAINBOARD_VERSION
+	string
+	default "bonw14"
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 20
+
+config DIMM_MAX
+	int
+	default 4
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/bonw14/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_BONW14
+	bool "bonw14"

src/mainboard/system76/bonw14/Makefile.inc

@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c
+ramstage-y += tas5825m.c

src/mainboard/system76/bonw14/acpi/dgpu.asl

@@ -0,0 +1,113 @@
+Device (\_SB.PCI0.PEG0) {
+	Name (_ADR, 0x00010000)
+
+	Device (PEGP) {
+		Name (_ADR, Zero)
+
+		// Convert a byte to a hex string, trimming extra parts
+		Method (BHEX, 1) {
+			Local0 = ToHexString(Arg0)
+			Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+		}
+
+		// UUID to string
+		Method (IDST, 1) {
+			Local0 = ""
+			Fprintf(
+				Local0,
+				"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+				BHEX(DerefOf(Arg0[3])),
+				BHEX(DerefOf(Arg0[2])),
+				BHEX(DerefOf(Arg0[1])),
+				BHEX(DerefOf(Arg0[0])),
+				BHEX(DerefOf(Arg0[5])),
+				BHEX(DerefOf(Arg0[4])),
+				BHEX(DerefOf(Arg0[7])),
+				BHEX(DerefOf(Arg0[6])),
+				BHEX(DerefOf(Arg0[8])),
+				BHEX(DerefOf(Arg0[9])),
+				BHEX(DerefOf(Arg0[10])),
+				BHEX(DerefOf(Arg0[11])),
+				BHEX(DerefOf(Arg0[12])),
+				BHEX(DerefOf(Arg0[13])),
+				BHEX(DerefOf(Arg0[14])),
+				BHEX(DerefOf(Arg0[15]))
+			)
+			Return (Local0)
+		}
+
+		// Safe hex conversion, checks type first
+		Method (SFST, 1) {
+			Local0 = ObjectType(Arg0)
+			If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+				Return (ToHexString(Arg0))
+			} Else {
+				Return (Concatenate("Type: ", Arg0))
+			}
+		}
+
+        Method (_DSM, 4, Serialized) {
+            Debug = "NVIDIA _DSM"
+            Printf("  Arg0: %o", IDST(Arg0))
+            Printf("  Arg1: %o", SFST(Arg1))
+            Printf("  Arg2: %o", SFST(Arg2))
+            Printf("  Arg3: %o", SFST(Arg3))
+
+            If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) {
+                If (Arg1 != 0x0102) {
+                    Printf("  Invalid Arg1, return 0x80000002")
+                    Return (0x80000002)
+                }
+
+                If (Arg2 == 0) {
+                    Printf("  Arg2 == 0x00, return supported functions")
+                    Return (Buffer (4) {
+                         0x01, 0x00, 0x10, 0x00
+                    })
+                }
+
+                If (Arg2 == 0x14) {
+                    Printf("  Arg2 == 0x14, return backlight package")
+					Return (Package (9) {
+						0x8000A450,
+						0x0200,
+						Zero,
+						Zero,
+						One,
+						One,
+						200,
+						32,
+						1000
+					})
+                }
+
+                Printf("  Unknown Arg2, return 0x80000002")
+                Return (0x80000002)
+            }
+
+            Printf("  Unknown Arg0, return 0x80000001")
+            Return (0x80000001)
+        }
+
+        Method (_DOD, 0, NotSerialized)  // _DOD: Display Output Devices
+        {
+            Return (Package (3) {
+                0x80008320,
+                0x80006330,
+                0x8000A450
+            })
+		}
+
+        Device (HDM0) {
+            Name (_ADR, 0x80008320)
+        }
+
+        Device (DSP0) {
+            Name (_ADR, 0x80006330)
+        }
+
+        Device (DSP1) {
+            Name (_ADR, 0x8000A450)
+        }
+	}
+}

src/mainboard/system76/bonw14/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_K6 SCI
+Method (_L06, 0, Serialized) {
+	Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/bonw14/acpi/mainboard.asl

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x03 /* GPP_K3 */
+#define EC_GPE_SWI 0x06 /* GPP_K6 */
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}
+
+#include "dgpu.asl"

src/mainboard/system76/bonw14/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/bonw14/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: bonw14
+Category: laptop
+Release year: 2020
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/bonw14/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/bonw14/devicetree.cb

@@ -0,0 +1,326 @@
+chip soc/intel/cannonlake
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Enable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 125,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 160,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
+		[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
+	register "SataPortsEnable[2]" = "0"
+	register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
+	register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "0"
+	register "PchHdaAudioLinkDmic1" = "0"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
+	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+	# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
+	register "PcieClkSrcUsage[7]" = "0x40"
+
+	# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpLtrEnable[0]" = "1"
+	register "PcieRpHotPlug[0]" = "1"
+	register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
+
+	# PCI Express root port #5 x4, Clock 10 (USB 3.2)
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpLtrEnable[4]" = "1"
+	register "PcieClkSrcUsage[10]" = "4"
+
+	# PCI Express root port #9 x4, Clock 8 (SSD)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[8]" = "8"
+
+	# PCI Express root port #13 x1, Clock 0 (WLAN)
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
+	register "PcieClkSrcUsage[0]" = "12"
+
+	# PCI Express root port #14 x1, Clock 1 (GLAN)
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpLtrEnable[13]" = "1"
+	register "PcieClkSrcUsage[1]" = "13"
+
+	# PCI Express root port #15 x1, Clock 4 (Card Reader)
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpLtrEnable[14]" = "1"
+	register "PcieClkSrcUsage[4]" = "14"
+
+	# PCI Express root port #17 x4, Clock 14 (SSD2)
+	register "PcieRpEnable[16]" = "1"
+	register "PcieRpLtrEnable[16]" = "1"
+	register "PcieClkSrcUsage[14]" = "16"
+
+	# PCI Express root port #21 x4, Clock 15 (SSD3)
+	register "PcieRpEnable[20]" = "1"
+	register "PcieRpLtrEnable[20]" = "1"
+	register "PcieClkSrcUsage[15]" = "20"
+
+    # Set all clocks sources to the same clock request
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+	register "PcieClkSrcClkReq[6]" = "6"
+	register "PcieClkSrcClkReq[7]" = "7"
+	register "PcieClkSrcClkReq[8]" = "8"
+	register "PcieClkSrcClkReq[9]" = "9"
+	register "PcieClkSrcClkReq[10]" = "10"
+	register "PcieClkSrcClkReq[11]" = "11"
+	register "PcieClkSrcClkReq[12]" = "12"
+	register "PcieClkSrcClkReq[13]" = "13"
+	register "PcieClkSrcClkReq[14]" = "14"
+	register "PcieClkSrcClkReq[15]" = "15"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# TODO: painfully verify this shit
+	# Power
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS3MinAssert" = "3" # 50ms
+	# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpS4MinAssert" = "1" # 1s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpSusMinAssert" = "4" # 4s
+	# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
+	# WARNING: must then be mapped from FSP value to PCH value
+	register "PchPmSlpAMinAssert" = "4" # 2s
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "13"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_K"
+	register "gpe0_dw1" = "PMC_GPP_G"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		subsystemid 0x1558 0x7714 inherit
+		device pci 00.0 on  end # Host Bridge
+		device pci 01.0 on  end # GPU Port
+		#TODO: is this enough to disable iGPU?
+		device pci 02.0 off end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Shared SRAM
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1b.0 on  end # PCI Express Port 17
+		device pci 1b.1 off end # PCI Express Port 18
+		device pci 1b.2 off end # PCI Express Port 19
+		device pci 1b.3 off end # PCI Express Port 20
+		device pci 1b.4 on  end # PCI Express Port 21
+		device pci 1b.5 off end # PCI Express Port 22
+		device pci 1b.6 off end # PCI Express Port 23
+		device pci 1b.7 off end # PCI Express Port 24
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on  end # PCI Express Port 13
+		device pci 1d.5 on  end # PCI Express Port 14
+		device pci 1d.6 on  end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on
+			chip drivers/i2c/tas5825m
+				register "id" = "0"
+				device i2c 4e on end # (8bit address: 0x9c)
+			end # tas5825m
+			chip drivers/i2c/tas5825m
+				register "id" = "1"
+				device i2c 4f on end # (8bit address: 0x9e)
+			end # tas5825m
+		end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/bonw14/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/bonw14/gpio.h

@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#ifndef __ACPI__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+		//TODO: add early GPIO settings
+		PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+		//TODO: GPIO names and verify everything
+		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		PAD_CFG_GPI(GPD2, NATIVE, PWROK),
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
+		PAD_CFG_GPI(GPD7, UP_20K, PWROK),
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPD11, UP_20K, PWROK),
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
+		_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
+		PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A15, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A19, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
+		PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ#
+		PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R
+		PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R
+		PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ#
+		PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT#
+		PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP),
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000),
+		PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_C9, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C10, DN_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C15, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
+		PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1),
+		PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1),
+		PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N
+		PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL
+		PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI#
+		PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+		PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
+		PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
+		PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, RSMRST), // GPP_F2_TBT_RST#
+		PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2),
+		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+		PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
+		PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP), // SSD1_PWR_DN#
+		PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_F21, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
+		PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // GC_OFF_EN
+		PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ#
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ#
+		PAD_CFG_GPI(GPP_H3, NONE, PLTRST),
+		PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
+		PAD_CFG_GPI(GPP_H5, NONE, PLTRST),
+		PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N
+		PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), // PCIE_SSD2_RESET
+		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ#
+		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ#
+		PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+		PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), // SSD3_PWR_DN#
+		PAD_CFG_GPI(GPP_H12, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H13, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000),
+		PAD_CFG_GPI(GPP_H16, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H17, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
+		_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
+		_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
+		PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+		PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP), // GPIO_TBT_RESET
+		PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP),
+		PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
+		PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
+		PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
+		PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
+		PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1),
+		PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE
+		PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE
+		PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD
+		_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
+		PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R
+		PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), // DP_MUX_SW
+		_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
+		PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN
+		PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // SSD4_PWR_DN#
+		PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET
+		PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH
+		PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH
+		_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000),
+		PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R
+		PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
+		PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
+		PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
+		PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
+		PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
+		PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
+};
+
+#endif
+
+#endif

src/mainboard/system76/bonw14/hda_verb.c

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC1220 */
+	0x10ec1220, /* Vendor ID */
+	0x15587714, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15587714),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x14, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4094022d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x04451120),
+};
+
+const u32 pc_beep_verbs[] = {
+    // Enable DMIC microphone on ALC1220
+    0x02050036,
+    0x02042a6a,
+};
+
+AZALIA_ARRAY_SIZES;
+
+#endif

src/mainboard/system76/bonw14/ramstage.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/bonw14/romstage.c

@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa2},
+	},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa6},
+	},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 75, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+ 	.rcomp_targets = { 50, 26, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd) {
+	// Allow memory clocks higher than 2933 MHz
+	memupd->FspmConfig.SaOcSupport = 1;
+	// Set primary display to PCIe graphics
+	memupd->FspmConfig.PrimaryDisplay = 1;
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/bonw14/tas5825m-normal.c

@@ -0,0 +1,971 @@
+static int tas5825m_setup_normal(struct device * dev) {
+	int res = 0;
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x02);
+		amp_write_at(0x01, 0x11);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x46, 0x11);
+	}
+
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x02, 0x00);
+		amp_write_at(0x53, 0x00);
+		amp_write_at(0x54, 0x00);
+		amp_write_at(0x29, 0x7C);
+		amp_write_at(0x03, 0x02);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x29, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x12);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x48, 0x0C);
+	}
+
+	amp_set_book(0x64);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
+			0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
+			0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
+			0x60, 0x00, 0x01
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
+		});
+		amp_write_block_at(0x27, {
+			0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
+			0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
+			0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
+			0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
+			0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
+			0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
+			0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
+			0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
+			0x1C, 0x11, 0xAB
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
+			0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
+			0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
+			0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
+		});
+		amp_write_block_at(0x46, {
+			0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
+			0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
+			0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
+			0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
+		});
+		amp_write_block_at(0x65, {
+			0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
+			0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
+			0x1C, 0x51, 0xBB
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
+			0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
+			0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
+			0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
+		});
+		amp_write_block_at(0x46, {
+			0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
+			0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
+			0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
+			0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
+			0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
+			0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
+			0x27, 0x80, 0xEA
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
+			0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
+			0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
+			0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
+			0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
+			0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
+			0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
+		});
+		amp_write_block_at(0x65, {
+			0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
+			0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
+			0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
+			0xC1, 0x01, 0x9D
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
+			0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
+			0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
+			0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
+			0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
+			0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
+			0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
+			0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
+			0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
+			0x82, 0x04, 0x07
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
+			0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
+			0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
+			0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
+		});
+		amp_write_block_at(0x46, {
+			0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
+			0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
+			0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
+			0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
+			0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
+			0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
+			0x1F, 0x31, 0xA8
+		});
+	}
+
+	amp_set_page(0x08);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
+			0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
+			0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
+			0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
+		});
+		amp_write_block_at(0x46, {
+			0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
+			0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
+			0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
+			0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
+			0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
+			0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
+			0xA1, 0x01, 0xC6
+		});
+	}
+
+	amp_set_page(0x09);
+	{
+		amp_write_block_at(0x08, {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
+			0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
+			0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
+			0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
+			0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
+			0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
+			0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
+		});
+		amp_write_block_at(0x65, {
+			0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
+			0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
+			0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
+			0xC3, 0x03, 0x5F
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
+			0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
+			0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
+			0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
+		});
+		amp_write_block_at(0x46, {
+			0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
+			0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
+			0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
+			0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
+		});
+		amp_write_block_at(0x65, {
+			0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
+			0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
+			0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
+			0xD0, 0x04, 0x09
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
+			0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
+			0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
+			0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
+		});
+		amp_write_block_at(0x46, {
+			0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
+			0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
+			0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
+			0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
+			0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
+			0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
+			0x60, 0x06, 0x12
+		});
+	}
+
+	amp_set_page(0x0C);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
+		});
+		amp_write_block_at(0x27, {
+			0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
+			0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
+			0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
+			0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
+			0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
+			0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
+			0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
+		});
+		amp_write_block_at(0x65, {
+			0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
+			0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
+			0xC2, 0x04, 0x00
+		});
+	}
+
+	amp_set_page(0x0D);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
+		});
+		amp_write_block_at(0x27, {
+			0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
+			0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
+			0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
+			0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
+		});
+		amp_write_block_at(0x46, {
+			0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
+			0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
+			0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
+			0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x18);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1B);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x54, {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x74, {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x5B, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x7A, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x0C, {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x24, {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x44, {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+
+		});
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
+		});
+		amp_write_block_at(0x7B, {
+			0xC1, 0xF8, 0x59, 0x7F, 0x63
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
+		});
+		amp_write_block_at(0x27, {
+			0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
+			0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
+			0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
+			0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
+		});
+		amp_write_block_at(0x46, {
+			0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
+			0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
+			0xBB, 0x98, 0xC8
+		});
+	}
+
+	amp_set_page(0x10);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x40, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_block_at(0x7D, {
+			0x11, 0xFF
+		});
+	}
+
+	amp_set_page(0x01);
+	{
+		amp_write_at(0x51, 0x05);
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_at(0x19, 0xDF);
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x2C, {
+			0x00, 0x71, 0x94, 0x9A
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x0C, 0xCC, 0xCD,
+			0x00, 0x0C, 0xCC, 0xCD, 0x00, 0x80, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x28, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xA9, 0x15, 0xB8,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x5C, {
+			0x7F, 0xF9, 0x2C, 0x60, 0x01, 0x33, 0x51, 0x50,
+
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x6C, {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0xAA);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x30, {
+			0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
+			0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
+			0xF8, 0x5C, 0x9F, 0x28, 0x07, 0xD1, 0x27, 0x3E,
+			0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27
+		});
+		amp_write_block_at(0x4F, {
+			0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F,
+			0x28, 0x08, 0x00, 0x00, 0x00, 0xF0, 0x71, 0x4C,
+			0x87, 0x07, 0x91, 0xC6, 0x22, 0x0F, 0x8E, 0xB3,
+			0x79, 0xF8, 0x6E, 0x39, 0xDE, 0x08, 0x00
+		});
+		amp_write_block_at(0x6E, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B,
+			0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5,
+			0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57,
+			0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51
+		});
+		amp_write_block_at(0x27, {
+			0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0,
+			0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92,
+			0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D,
+			0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F
+		});
+		amp_write_block_at(0x46, {
+			0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0,
+			0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0,
+			0x3F, 0x52, 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50,
+			0x29, 0xD7, 0x05, 0x3A, 0xF8, 0x0F, 0x0C
+		});
+		amp_write_block_at(0x65, {
+			0xAF, 0xD6, 0x29, 0xFB, 0x3E, 0x46, 0x00, 0x08,
+			0x17, 0x5D, 0x4C, 0xF0, 0xBC, 0xDB, 0x13, 0x07,
+			0x34, 0x29, 0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8,
+			0xB4, 0x78, 0xEA
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFC, 0xDB, 0x0F, 0xF0, 0x3A, 0xC4, 0xBE,
+			0x07, 0xC9, 0x51, 0x50, 0x0F, 0xC5, 0x3B, 0x42,
+			0xF8, 0x39, 0xD3, 0xA1, 0x07, 0xFC, 0x38, 0xBF,
+			0xF0, 0x47, 0x14, 0xF2, 0x07, 0xBE, 0x4A
+		});
+		amp_write_block_at(0x27, {
+			0x80, 0x0F, 0xB8, 0xEB, 0x0E, 0xF8, 0x45, 0x7C,
+			0xC1, 0x07, 0xEB, 0xF6, 0xEF, 0xF1, 0x08, 0x7E,
+			0x56, 0x07, 0x17, 0x63, 0xC3, 0x0E, 0xF7, 0x81,
+			0xAA, 0xF8, 0xFC, 0xA5, 0x4E, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+			0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, 0x07,
+			0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8,
+			0x5C, 0x9F, 0x28
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
+			0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
+			0xF8, 0x5C, 0x9F, 0x28, 0x08, 0x00, 0x00, 0x00,
+			0xF0, 0x71, 0x4C, 0x87, 0x07, 0x91, 0xC6
+		});
+		amp_write_block_at(0x27, {
+			0x22, 0x0F, 0x8E, 0xB3, 0x79, 0xF8, 0x6E, 0x39,
+			0xDE, 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7,
+			0x0B, 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08,
+			0xF5, 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58
+		});
+		amp_write_block_at(0x46, {
+			0xFE, 0x57, 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4,
+			0x51, 0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2,
+			0xB0, 0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE,
+			0x92, 0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x6D, 0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09,
+			0x6F, 0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02,
+			0xE0, 0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB,
+			0xB0, 0x3F, 0x52
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7,
+			0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29,
+			0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C,
+			0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29
+		});
+		amp_write_block_at(0x27, {
+			0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78,
+			0xEA, 0x07, 0xFB, 0x25, 0x84, 0xF0, 0x49, 0xA3,
+			0xCE, 0x07, 0xC7, 0xA6, 0xCB, 0x0F, 0xB6, 0x5C,
+			0x32, 0xF8, 0x3D, 0x33, 0xB1, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x86, 0x43, 0x99, 0xFF, 0x02, 0xE6, 0x50,
+			0x00, 0x77, 0xAC, 0xFD, 0x0F, 0xD7, 0xE6, 0xBF,
+			0xF8, 0x27, 0x42, 0x5B
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
+			0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49
+		});
+		amp_write_block_at(0x27, {
+			0x81, 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB,
+			0xA1, 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18,
+			0x9F, 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A,
+			0x64, 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
+			0x71, 0xC7
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x30, 0x00);
+		amp_write_at(0x60, 0x02);
+		amp_write_at(0x62, 0x09);
+		amp_write_at(0x4C, 0x30);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x64, 0x02);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x4E, 0xBB);
+		amp_write_at(0x4F, 0xB0);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	return 0;
+}

src/mainboard/system76/bonw14/tas5825m-sub.c

@@ -0,0 +1,971 @@
+static int tas5825m_setup_sub(struct device * dev) {
+	int res = 0;
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x02);
+		amp_write_at(0x01, 0x11);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x46, 0x11);
+	}
+
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x02, 0x04);
+		amp_write_at(0x53, 0x00);
+		amp_write_at(0x54, 0x00);
+		amp_write_at(0x29, 0x7C);
+		amp_write_at(0x03, 0x02);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	{
+		amp_write_at(0x29, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x03, 0x12);
+	}
+
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+	amp_set_page(0x00);
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x48, 0x0C);
+	}
+
+	amp_set_book(0x64);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
+			0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
+			0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
+			0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
+			0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
+			0x60, 0x00, 0x01
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
+			0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
+			0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
+			0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
+		});
+		amp_write_block_at(0x27, {
+			0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
+			0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
+			0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
+			0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
+			0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
+			0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
+			0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
+			0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
+			0x1C, 0x11, 0xAB
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
+			0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
+			0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
+			0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
+			0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
+			0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
+			0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
+		});
+		amp_write_block_at(0x46, {
+			0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
+			0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
+			0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
+			0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
+		});
+		amp_write_block_at(0x65, {
+			0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
+			0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
+			0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
+			0x1C, 0x51, 0xBB
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
+			0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
+			0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
+			0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
+			0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
+			0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
+			0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
+		});
+		amp_write_block_at(0x46, {
+			0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
+			0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
+			0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
+			0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
+			0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
+			0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
+			0x27, 0x80, 0xEA
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
+			0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
+			0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
+			0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
+			0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
+			0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
+			0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
+			0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
+			0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
+			0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
+		});
+		amp_write_block_at(0x65, {
+			0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
+			0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
+			0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
+			0xC1, 0x01, 0x9D
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
+			0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
+			0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
+			0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
+			0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
+			0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
+			0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
+			0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
+			0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
+			0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
+			0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
+			0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
+			0x82, 0x04, 0x07
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x08, {
+			0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
+			0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
+			0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
+			0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
+			0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
+			0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
+			0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
+		});
+		amp_write_block_at(0x46, {
+			0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
+			0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
+			0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
+			0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
+		});
+		amp_write_block_at(0x65, {
+			0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
+			0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
+			0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
+			0x1F, 0x31, 0xA8
+		});
+	}
+
+	amp_set_page(0x08);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
+			0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
+			0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
+			0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
+			0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
+			0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
+			0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
+		});
+		amp_write_block_at(0x46, {
+			0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
+			0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
+			0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
+			0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
+			0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
+			0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
+			0xA1, 0x01, 0xC6
+		});
+	}
+
+	amp_set_page(0x09);
+	{
+		amp_write_block_at(0x08, {
+			0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
+			0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
+			0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
+			0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
+			0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
+			0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
+			0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
+			0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
+			0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
+			0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
+		});
+		amp_write_block_at(0x65, {
+			0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
+			0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
+			0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
+			0xC3, 0x03, 0x5F
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
+			0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
+			0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
+			0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
+		});
+		amp_write_block_at(0x27, {
+			0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
+			0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
+			0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
+			0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
+		});
+		amp_write_block_at(0x46, {
+			0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
+			0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
+			0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
+			0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
+		});
+		amp_write_block_at(0x65, {
+			0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
+			0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
+			0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
+			0xD0, 0x04, 0x09
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
+			0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
+			0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
+			0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
+			0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
+			0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
+			0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
+		});
+		amp_write_block_at(0x46, {
+			0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
+			0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
+			0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
+			0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
+		});
+		amp_write_block_at(0x65, {
+			0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
+			0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
+			0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
+			0x60, 0x06, 0x12
+		});
+	}
+
+	amp_set_page(0x0C);
+	{
+		amp_write_block_at(0x08, {
+			0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
+			0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
+			0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
+			0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
+		});
+		amp_write_block_at(0x27, {
+			0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
+			0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
+			0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
+			0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
+		});
+		amp_write_block_at(0x46, {
+			0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
+			0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
+			0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
+			0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
+		});
+		amp_write_block_at(0x65, {
+			0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
+			0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
+			0xC2, 0x04, 0x00
+		});
+	}
+
+	amp_set_page(0x0D);
+	{
+		amp_write_block_at(0x08, {
+			0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
+			0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
+			0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
+			0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
+		});
+		amp_write_block_at(0x27, {
+			0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
+			0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
+			0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
+			0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
+		});
+		amp_write_block_at(0x46, {
+			0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
+			0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
+			0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
+			0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x18);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1B);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
+			0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x54, {
+			0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
+			0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1C);
+	{
+		amp_write_block_at(0x74, {
+			0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x1C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1D);
+	{
+		amp_write_block_at(0x3C, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x5B, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x7A, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x0C, {
+			0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x24, {
+			0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
+			0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0xFD, {
+			0x00, 0x00
+		});
+	}
+
+	amp_set_book(0x78);
+
+	amp_set_page(0x1E);
+	{
+		amp_write_block_at(0x44, {
+			0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
+
+		});
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
+			0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
+			0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
+			0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
+		});
+		amp_write_block_at(0x7B, {
+			0xC1, 0xF8, 0x59, 0x7F, 0x63
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
+			0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
+		});
+		amp_write_block_at(0x27, {
+			0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
+			0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
+			0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
+			0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
+		});
+		amp_write_block_at(0x46, {
+			0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
+			0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
+			0xBB, 0x98, 0xC8
+		});
+	}
+
+	amp_set_page(0x10);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
+			0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
+			0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
+
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x40, 0x00);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_block_at(0x7D, {
+			0x11, 0xFF
+		});
+	}
+
+	amp_set_page(0x01);
+	{
+		amp_write_at(0x51, 0x05);
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_at(0x19, 0xDF);
+	}
+
+	amp_set_book(0x8C);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x2C, {
+			0x00, 0x71, 0x94, 0x9A
+		});
+	}
+
+	amp_set_page(0x0A);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x80, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x0B);
+	{
+		amp_write_block_at(0x08, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x5A, 0x84,
+			0x00, 0x1E, 0x5A, 0x84, 0x00, 0x40, 0x26, 0xE7,
+			0x00, 0x40, 0x26, 0xE7, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x28, {
+			0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x5C, {
+			0x00, 0x03, 0x69, 0xC5, 0x00, 0xEB, 0x8F, 0xA8,
+			0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
+
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x5C, {
+			0x7F, 0xF9, 0x2C, 0x60, 0x01, 0xEB, 0x55, 0xAC,
+
+		});
+	}
+
+	amp_set_page(0x07);
+	{
+		amp_write_block_at(0x64, {
+			0x00, 0x80, 0x00, 0x00
+		});
+		amp_write_block_at(0x6C, {
+			0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
+
+		});
+	}
+
+	amp_set_book(0xAA);
+
+	amp_set_page(0x01);
+	{
+		amp_write_block_at(0x30, {
+			0x00, 0x01, 0x0A, 0x7A, 0x00, 0x02, 0x14, 0xF5,
+			0x00, 0x01, 0x0A, 0x7A, 0x0F, 0x7B, 0xDB, 0x58,
+			0xF8, 0x7F, 0xFA, 0xBE, 0x00, 0x01, 0x0A, 0x7A,
+			0x00, 0x02, 0x14, 0xF5, 0x00, 0x01, 0x0A
+		});
+		amp_write_block_at(0x4F, {
+			0x7A, 0x0F, 0x7B, 0xDB, 0x58, 0xF8, 0x7F, 0xFA,
+			0xBE, 0x07, 0xFD, 0xF9, 0x62, 0xF0, 0x25, 0x7A,
+			0x1B, 0x07, 0xDC, 0xC4, 0xC6, 0x0F, 0xDA, 0x85,
+			0xE5, 0xF8, 0x25, 0x41, 0xD8, 0x08, 0x00
+		});
+		amp_write_block_at(0x6E, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x02);
+	{
+		amp_write_block_at(0x08, {
+			0x07, 0xF7, 0xFF, 0xB5, 0xF0, 0x4F, 0x8C, 0x33,
+			0x07, 0xBA, 0x32, 0x37, 0x0F, 0xB0, 0x73, 0xCD,
+			0xF8, 0x4D, 0xCE, 0x15, 0x07, 0xFA, 0x6B, 0x45,
+			0xF0, 0x68, 0xC7, 0x1B, 0x07, 0x9E, 0xF0
+		});
+		amp_write_block_at(0x27, {
+			0xFB, 0x0F, 0x97, 0x38, 0xE5, 0xF8, 0x66, 0xA3,
+			0xC0, 0x07, 0xFE, 0x8C, 0x9C, 0xF0, 0x34, 0xCF,
+			0xDE, 0x07, 0xCD, 0x94, 0xFF, 0x0F, 0xCB, 0x30,
+			0x22, 0xF8, 0x33, 0xDE, 0x65, 0x07, 0xFE
+		});
+		amp_write_block_at(0x46, {
+			0x73, 0xDB, 0xF0, 0x38, 0x93, 0x60, 0x07, 0xCA,
+			0x38, 0xAE, 0x0F, 0xC7, 0x6C, 0xA0, 0xF8, 0x37,
+			0x53, 0x77, 0x07, 0xF8, 0xC1, 0xBE, 0xF0, 0x88,
+			0xCB, 0x7D, 0x07, 0x82, 0x08, 0xA9, 0x0F
+		});
+		amp_write_block_at(0x65, {
+			0x77, 0x34, 0x83, 0xF8, 0x85, 0x35, 0x99, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x03);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4,
+			0xF0, 0x22, 0x72, 0x97, 0x07, 0xEE, 0xC6
+		});
+		amp_write_block_at(0x27, {
+			0xB4, 0x0F, 0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C,
+			0xCB, 0x07, 0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67,
+			0xAD, 0x07, 0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98,
+			0x53, 0xF8, 0x33, 0xBE, 0x30, 0x08, 0x13
+		});
+		amp_write_block_at(0x46, {
+			0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C, 0x07, 0xDE,
+			0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85, 0xF8, 0x0E,
+			0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x04);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x65, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00
+		});
+	}
+
+	amp_set_page(0x05);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4, 0xF0, 0x22,
+			0x72, 0x97, 0x07, 0xEE, 0xC6, 0xB4, 0x0F
+		});
+		amp_write_block_at(0x65, {
+			0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C, 0xCB, 0x07,
+			0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67, 0xAD, 0x07,
+			0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98, 0x53, 0xF8,
+			0x33, 0xBE, 0x30
+		});
+	}
+
+	amp_set_page(0x06);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x13, 0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C,
+			0x07, 0xDE, 0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85,
+			0xF8, 0x0E, 0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+		});
+		amp_write_block_at(0x27, {
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00
+		});
+	}
+
+	amp_set_page(0x0E);
+	{
+		amp_write_block_at(0x6C, {
+			0x00, 0x85, 0xC0, 0x8D, 0xFF, 0x02, 0x2B, 0x75,
+			0x00, 0x78, 0xBE, 0x6E, 0x0F, 0xE2, 0x46, 0xF6,
+			0xF8, 0x1D, 0x0E, 0x9A
+		});
+	}
+
+	amp_set_page(0x0F);
+	{
+		amp_write_block_at(0x08, {
+			0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xAA, 0xC3,
+			0xFF, 0xFD, 0x55, 0x85, 0xFF, 0xFE, 0xAA
+		});
+		amp_write_block_at(0x27, {
+			0xC3, 0x0F, 0x2F, 0x01, 0x62, 0xF8, 0xCB, 0xA9,
+			0xA8, 0x07, 0x98, 0xD5, 0xEF, 0xF0, 0xCE, 0x54,
+			0x23, 0x07, 0x98, 0xD5, 0xEF, 0x0F, 0x2F, 0x01,
+			0x62, 0xF8, 0xCB, 0xA9, 0xA8, 0x00, 0x00
+		});
+		amp_write_block_at(0x46, {
+			0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+			0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
+			0x71, 0xC7
+		});
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x30, 0x00);
+		amp_write_at(0x60, 0x02);
+		amp_write_at(0x62, 0x09);
+		amp_write_at(0x4C, 0x30);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x60, 0x00);
+		amp_write_at(0x64, 0x02);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x4E, 0xBB);
+		amp_write_at(0x4F, 0xB0);
+		amp_write_at(0x03, 0x03);
+	}
+
+	amp_set_book(0x00);
+
+	{
+		// Page 0
+
+		amp_write_at(0x78, 0x80);
+	}
+
+	return 0;
+}

src/mainboard/system76/bonw14/tas5825m.c

@@ -0,0 +1,31 @@
+#include <delay.h>
+#include <drivers/i2c/tas5825m/tas5825m.h>
+
+#define R(F) { \
+	res = F; \
+	if (res < 0) return res; \
+}
+
+#define amp_write_at(A, V) R(tas5825m_write_at(dev, A, V))
+
+#define amp_write_block_at(A, ...) { \
+	const uint8_t _values[] = __VA_ARGS__; \
+	R(tas5825m_write_block_at(dev, A, _values, ARRAY_SIZE(_values))); \
+}
+
+#define amp_set_page(P) R(tas5825m_set_page(dev, P))
+
+#define amp_set_book(B) R(tas5825m_set_book(dev, B))
+
+#include "tas5825m-normal.c"
+#include "tas5825m-sub.c"
+
+int tas5825m_setup(struct device * dev, int id) {
+	if (id == 0) {
+		return tas5825m_setup_normal(dev);
+	} else if (id == 1) {
+		return tas5825m_setup_sub(dev);
+	} else {
+		return -1;
+	}
+}

src/mainboard/system76/cml-u/Kconfig

@@ -0,0 +1,94 @@
+if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP6
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs
+	select SOC_INTEL_COMETLAKE
+	select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+	select USE_OPTION_TABLE
+	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+
+config MAINBOARD_DIR
+	string
+	default "system76/cml-u"
+
+config VARIANT_DIR
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "galp4" if BOARD_SYSTEM76_GALP4
+	default "darp6" if BOARD_SYSTEM76_DARP6
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,9b41.rom"
+
+config VGA_BIOS_ID
+	string
+	default "8086,9b41"
+
+config PXE_ROM_ID
+	string
+	default "10ec,8168"
+
+config POST_DEVICE
+	bool
+	default n
+
+endif

src/mainboard/system76/cml-u/Kconfig.name

@@ -0,0 +1,5 @@
+config BOARD_SYSTEM76_GALP4
+	bool "galp4"
+
+config BOARD_SYSTEM76_DARP6
+	bool "darp6"

src/mainboard/system76/cml-u/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+       Name (BRIG, Package (22)
+       {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/cml-u/acpi/gpe.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// GPP_D9 SCI
+Method (_L29, 0, Serialized) {
+	Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
+	If (\_SB.PCI0.LPCB.EC0.ECOK) {
+		If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
+			Notify(\_SB.LID0, 0x80)
+		}
+	}
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x50 /* GPP_E16 */
+#define EC_GPE_SWI 0x29 /* GPP_D9 */
+
+#if defined(CONFIG_BOARD_SYSTEM76_DARP6)
+	#define EC_COLOR_KEYBOARD 1
+#elif defined(CONFIG_BOARD_SYSTEM76_GALP4)
+	#define EC_COLOR_KEYBOARD 0
+#else
+	#error Unknown Mainboard
+#endif
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}
+
+Scope (\_GPE) {
+	#include "gpe.asl"
+}

src/mainboard/system76/cml-u/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Method called from _PTS prior to enter sleep state */
+Method (MPTS, 1) {
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+}
+
+/* Method called from _WAK prior to wakeup */
+Method (MWAK, 1) {
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}

src/mainboard/system76/cml-u/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: cml-u
+Category: laptop
+Release year: 2019
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/cml-u/bootblock.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/cml-u/cmos.default

@@ -0,0 +1 @@
+DisplayPort_Output=Mini_DisplayPort

src/mainboard/system76/cml-u/cmos.layout

@@ -0,0 +1,33 @@
+#*****************************************************************************
+#
+#  This file is part of the coreboot project.
+#
+#  Copyright (C) 2019 System76
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+#start  length  type    id      name
+0       384     r       0       reserved_memory
+384     1       e       1       DisplayPort_Output
+984     16      h       0       check_sum
+
+enumerations
+
+#ID     value   text
+1       0       Mini_DisplayPort
+1       1       USB-C
+
+checksums
+
+#checksum   start   end     location
+checksum    384     983     984

src/mainboard/system76/cml-u/devicetree.cb

@@ -0,0 +1,261 @@
+chip soc/intel/cannonlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		/* Touchpad */
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+# ACPI (soc/intel/cannonlake/acpi.c)
+	# Disable s0ix
+	register "s0ix_enable" = "0"
+
+	# PM Timer Enabled
+	register "PmTimerDisabled" = "0"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+# CPU (soc/intel/cannonlake/cpu.c)
+	# Power limit
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 30,
+	}"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+	register "SaGv" = "SaGv_Enabled"
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART
+	}"
+
+	# SATA
+	register "SataMode" = "Sata_AHCI"
+	register "SataSalpSupport" = "0"
+
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "0"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "0"
+	register "SataPortsEnable[4]" = "0"
+	register "SataPortsEnable[5]" = "0"
+	register "SataPortsEnable[6]" = "0"
+	register "SataPortsEnable[7]" = "0"
+
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
+	register "SataPortsDevSlp[3]" = "0"
+	register "SataPortsDevSlp[4]" = "0"
+	register "SataPortsDevSlp[5]" = "0"
+	register "SataPortsDevSlp[6]" = "0"
+	register "SataPortsDevSlp[7]" = "0"
+
+	# Audio
+	register "PchHdaDspEnable" = "0"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkDmic0" = "1"
+	register "PchHdaAudioLinkDmic1" = "1"
+	register "PchHdaAudioLinkSsp0" = "0"
+	register "PchHdaAudioLinkSsp1" = "0"
+	register "PchHdaAudioLinkSsp2" = "0"
+	register "PchHdaAudioLinkSndw1" = "0"
+	register "PchHdaAudioLinkSndw2" = "0"
+	register "PchHdaAudioLinkSndw3" = "0"
+	register "PchHdaAudioLinkSndw4" = "0"
+
+	# USB
+	register "SsicPortEnable" = "0"
+
+	# USB2
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"		# 3G / LTE
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C port 3
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"		# USB Board port 4
+	register "usb2_ports[4]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"			# Finger print
+	register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"			# T17, T18
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
+	register "usb2_ports[10]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[11]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[12]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[13]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[14]" = "USB2_PORT_EMPTY"			# NC
+	register "usb2_ports[15]" = "USB2_PORT_EMPTY"			# NC
+
+	# USB3
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" 	# Type-A port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# 4G
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type C port 3
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# USB Board port 4
+	register "usb3_ports[4]" = "USB3_PORT_EMPTY"				# Used by TBT
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"				# Used by TBT
+	register "usb3_ports[6]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[7]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[8]" = "USB3_PORT_EMPTY"				# NC
+	register "usb3_ports[9]" = "USB3_PORT_EMPTY"				# NC
+
+	# PCI Express Root port #5 x4, Clock 4 (TBT)
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpLtrEnable[4]" = "1"
+	register "PcieRpHotPlug[4]" = "1"
+	register "PcieClkSrcUsage[4]" = "4"
+	register "PcieClkSrcClkReq[4]" = "4"
+
+	# PCI Express Root port #9 x1, Clock 3 (LAN)
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+	register "PcieClkSrcUsage[3]" = "8"
+	register "PcieClkSrcClkReq[3]" = "3"
+
+	# PCI Express Root port #10 x1, Clock 2 (WLAN)
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpLtrEnable[9]" = "0"
+	register "PcieClkSrcUsage[2]" = "9"
+	register "PcieClkSrcClkReq[2]" = "2"
+
+	# PCI Express Root port #13 x4, Clock 5 (NVMe)
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
+	register "PcieClkSrcUsage[5]" = "12"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# Misc
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "0"
+	register "Heci3Enabled" = "0"
+	register "AcousticNoiseMitigation" = "1"
+	#register "dmipwroptimize" = "1"
+	#register "satapwroptimize" = "1"
+
+	# Power
+	register "PchPmSlpS3MinAssert" = "3"		# 50ms
+	register "PchPmSlpS4MinAssert" = "1"		# 1s
+	register "PchPmSlpSusMinAssert" = "2"		# 500ms
+	register "PchPmSlpAMinAssert" = "4"		# 2s
+
+	# Thermal
+	register "tcc_offset" = "12"
+
+	# Serial IRQ Continuous
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+# Graphics (soc/intel/cannonlake/graphics.c)
+    register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+# LPC (soc/intel/cannonlake/lpc.c)
+	# LPC configuration from lspci -s 1f.0 -xxx
+	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+	register "gen1_dec" = "0x000c0081"
+	# Address 0x88: Decode 0x68 - 0x6F (PMC)
+	register "gen2_dec" = "0x00040069"
+	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+	register "gen3_dec" = "0x00fc0E01"
+	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+	register "gen4_dec" = "0x00fc0F01"
+
+# PMC (soc/intel/cannonlake/pmc.c)
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "0"
+	register "deep_s3_enable_dc" = "0"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
+	register "deep_sx_config" = "0"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0" = "PMC_GPP_C"
+	register "gpe0_dw1" = "PMC_GPP_D"
+	register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 13.0 off end # Integrated Sensor Hub
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		#chip drivers/intel/wifi
+		#	register "wake" = "PME_B0_EN_BIT"
+			device pci 14.3 on  end # CNVi wifi
+		#end
+		device pci 14.5 off end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 off end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 off end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 on  end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 on  end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 off end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on # LPC Interface
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 off end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end

src/mainboard/system76/cml-u/dsdt.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/system76/cml-u/gpio.h

@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+#define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C22),
+		// NC
+		PAD_CFG_NC(GPP_C23),
+};
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+// GPD
+	// Power Management
+		// PM_BATLOW#
+		PAD_CFG_NC(GPD0),
+		// AC_PRESENT
+		PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPD2),
+		// PWR_BTN#
+		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+		// SUSB#_PCH
+		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+		// SUSC#_PCH
+		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+		// SLP_A#
+		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPD7),
+
+	// Clock Signals
+		// SUS_CLK
+		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+	// Power Management
+		// GPD9_RTD3
+		PAD_CFG_NC(GPD9),
+		// NC
+		PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPD11),
+
+// GPP_A
+	// LPC
+		// SB_KBCRST#
+		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+		// LPC_AD0
+		PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+		// LPC_AD1
+		PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+		// LPC_AD2
+		PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+		// LPC_AD3
+		PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+		// LPC_FRAME#
+		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+		// SERIRQ with pull up
+		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+	// GSPI0
+		// TPM_PIRQ#
+		PAD_CFG_NC(GPP_A7),
+
+	// LPC
+		// PM_CLKRUN# with pull-up
+		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+		// PCLK_KBC
+		PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+		// NC
+		PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+	// GSPI1
+		// NC
+		PAD_CFG_NC(GPP_A11),
+
+	// ISH_GP
+		// PCH_GPP_A12
+		PAD_CFG_NC(GPP_A12),
+
+	// Power Management
+		// SUSWARN#
+		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+
+	// LPC
+		// NC
+		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+	// Power Management
+		// SUS_PWR_ACK
+		PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
+
+	// SD
+		// NC
+		PAD_CFG_NC(GPP_A16),
+		// LIGHT_KB_DET#
+		PAD_CFG_NC(GPP_A17),
+
+	// ISH_GP
+		// NC
+		PAD_CFG_NC(GPP_A18),
+		// SATA_PWR_EN
+		PAD_CFG_GPO(GPP_A19, 1, DEEP),
+		// NC
+		PAD_CFG_NC(GPP_A20),
+		// NC
+		PAD_CFG_NC(GPP_A21),
+		// PS8338B_SW
+		PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
+		// PS8338B_PCH
+		PAD_CFG_NC(GPP_A23),
+
+// GPP_B
+	// Power
+		// CORE_VID0
+		PAD_CFG_NC(GPP_B0),
+		// CORE_VID1
+		PAD_CFG_NC(GPP_B1),
+
+	// Power Management
+		// CNVI_WAKE#
+		PAD_CFG_NC(GPP_B2),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_B3),
+		// NC
+		PAD_CFG_NC(GPP_B4),
+
+	// Clock Signals
+		// NC
+		PAD_CFG_NC(GPP_B5),
+		// NC
+		PAD_CFG_NC(GPP_B6),
+		// WLAN_CLKREQ#
+		PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+		// LAN_CLKREQ#
+		PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+		// TBT_CLKREQ#
+		PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+		// SSD_CLKREQ#
+		PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+
+	// Power Management
+		// EXT_PWR_GATE#
+		PAD_CFG_NC(GPP_B11),
+		// SLP_S0#
+		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+		// PLT_RST#
+		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	// SPKR
+		// PCH_SPKR
+		PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+
+	// GSPI0
+		// NC
+		PAD_CFG_NC(GPP_B15),
+		// PCH_GPP_B16
+		PAD_CFG_NC(GPP_B16),
+		// PCH_GPP_B17
+		PAD_CFG_NC(GPP_B17),
+		// PCH_GPP_B18 - strap for disabling no reboot mode
+		PAD_CFG_NC(GPP_B18),
+
+	// GSPI1
+		// NC
+		PAD_CFG_NC(GPP_B19),
+		// NC
+		PAD_CFG_NC(GPP_B20),
+		// NC
+		PAD_CFG_NC(GPP_B21),
+		// PCH_GPP_B22
+		PAD_CFG_NC(GPP_B22),
+
+	// SMBUS
+		// NC
+		PAD_CFG_NC(GPP_B23),
+
+// GPP_C
+	// SMBUS
+		// SMB_CLK_DDR
+		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+		// SMB_DAT_DDR
+		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+		// PCH_GPP_C2 with pull-up
+		PAD_CFG_NC(GPP_C2),
+		// NC
+		PAD_CFG_NC(GPP_C3),
+		// NC
+		PAD_CFG_NC(GPP_C4),
+		// NC
+		PAD_CFG_NC(GPP_C5),
+		// LAN_WAKEUP#
+		PAD_CFG_NC(GPP_C6),
+		// NC
+		PAD_CFG_NC(GPP_C7),
+
+	// UART0
+		// NC
+		PAD_CFG_NC(GPP_C8),
+		// TBCIO_PLUG_EVENT
+		_PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000),
+		// TBT_FRC_PWR
+		PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST),
+		// NC
+		PAD_CFG_NC(GPP_C11),
+
+	// UART1
+		// GPP_C12_RTD3
+		PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST),
+		// SSD_PWR_DN#
+		PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
+		// TBTA_HRESET
+		PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST),
+		// TBT_PERST_N
+		PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST),
+
+	// I2C
+		// T_SDA
+		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+		// T_SCL
+		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C18),
+		// SWI
+		PAD_CFG_NC(GPP_C19),
+
+	// UART2
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_C22),
+		// TP_ATTN#
+		PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT),
+
+// GPP_D
+	// SPI1
+		// NC
+		PAD_CFG_NC(GPP_D0),
+		// NC
+		PAD_CFG_NC(GPP_D1),
+		// NC
+		PAD_CFG_NC(GPP_D2),
+		// NC
+		PAD_CFG_NC(GPP_D3),
+
+	// IMGCLKOUT
+		// NC
+		PAD_CFG_NC(GPP_D4),
+
+	// I2C
+		// NC
+		PAD_CFG_NC(GPP_D5),
+		// NC
+		PAD_CFG_NC(GPP_D6),
+		// NC
+		PAD_CFG_NC(GPP_D7),
+		// SB_BLON
+		PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP),
+
+	// GSPI2
+		// SWI#
+		_PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000),
+		// NC
+		PAD_CFG_NC(GPP_D10),
+		// RTD3_PCIE_WAKE#
+		_PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000),
+		// PCH_GPP_D12
+		PAD_CFG_NC(GPP_D12),
+
+	// UART0
+		// NC
+		PAD_CFG_NC(GPP_D13),
+		// NC
+		PAD_CFG_NC(GPP_D14),
+		// NC
+		PAD_CFG_NC(GPP_D15),
+		// RTD3_3G_PW R_EN
+		PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK),
+
+	// DMIC
+		// NC
+		PAD_CFG_NC(GPP_D17),
+		// NC
+		PAD_CFG_NC(GPP_D18),
+		// GPPC_DMIC_CLK
+		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+		// GPPC_DMIC_DATA
+		PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	// SPI1
+		// TPM_DET#
+		PAD_CFG_NC(GPP_D21),
+		// TPM_TCM_Detect
+		PAD_CFG_NC(GPP_D22),
+
+	// I2S
+		// NC
+		PAD_CFG_NC(GPP_D23),
+
+// GPP_E
+	// SATA
+		// PCH_GPP_E0 with pull-up
+		PAD_CFG_NC(GPP_E0),
+		// SATA_ODD_PRSNT#
+		PAD_CFG_NC(GPP_E1),
+		// SATAGP2
+		PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_E3),
+
+	// DEVSLP
+		// NC
+		PAD_CFG_NC(GPP_E4),
+		// NC
+		PAD_CFG_NC(GPP_E5),
+		// DEVSLP2
+		PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
+
+	// CPU Misc
+		// NC
+		PAD_CFG_NC(GPP_E7),
+
+	// SATA
+		// PCH_SATAHDD_LED#
+		PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	// USB2
+		// GP_BSSB_CLK
+		PAD_CFG_NC(GPP_E9),
+		// GPP_E10
+		PAD_CFG_NC(GPP_E10),
+		// GPP_E11
+		PAD_CFG_NC(GPP_E11),
+		// USB_OC#78
+		PAD_CFG_NC(GPP_E12),
+
+	// Display Signals
+		// MUX_HPD
+		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+		// HDMI_HPD
+		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+		// SMI#
+		_PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0),
+		// SCI#
+		_PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000),
+		// EDP_HPD
+		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+		// MDP_CTRLCLK
+		PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+		// MDP_CTRLDATA
+		PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+		// HDMI_CTRLCLK
+		PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+		// HDMI_CTRLDATA
+		PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+		// NC
+		PAD_CFG_NC(GPP_E22),
+		// NC
+		PAD_CFG_NC(GPP_E23),
+
+// GPP_F
+	// CNVI
+		// CNVI_GNSS_PA_BLANKING
+		PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPP_F1),
+		// NC
+		PAD_CFG_NC(GPP_F2),
+		// NC
+		PAD_CFG_NC(GPP_F3),
+
+	// CNVI
+		// CNVI_BRI_DT
+		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+		// CNVI_BRI_RSP
+		PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+		// CNVI_RGI_DT
+		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+		// CNVI_RGI_RSP
+		PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+		// CNVI_MFUART2_RXD
+		PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+		// CNVI_MFUART2_TXD
+		PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+	// GPIO
+		// NC
+		PAD_CFG_NC(GPP_F10),
+
+	// EMMC
+		// NC
+		PAD_CFG_NC(GPP_F11),
+		// NC
+		PAD_CFG_NC(GPP_F12),
+		// NC
+		PAD_CFG_NC(GPP_F13),
+		// NC
+		PAD_CFG_NC(GPP_F14),
+		// NC
+		PAD_CFG_NC(GPP_F15),
+		// NC
+		PAD_CFG_NC(GPP_F16),
+		// NC
+		PAD_CFG_NC(GPP_F17),
+		// NC
+		PAD_CFG_NC(GPP_F18),
+		// NC
+		PAD_CFG_NC(GPP_F19),
+		// NC
+		PAD_CFG_NC(GPP_F20),
+		// NC
+		PAD_CFG_NC(GPP_F21),
+		// NC
+		PAD_CFG_NC(GPP_F22),
+
+	// A4WP
+		// A4WP_PRESENT
+		PAD_CFG_GPI(GPP_F23, DN_20K, DEEP),
+
+// GPP_G
+	// SD
+		// EDP_DET
+		PAD_CFG_NC(GPP_G0),
+		// NC
+		PAD_CFG_NC(GPP_G1),
+		// NC
+		PAD_CFG_NC(GPP_G2),
+		// ASM1543_I_SEL0
+		PAD_CFG_NC(GPP_G3),
+		// ASM1543_I_SEL1
+		PAD_CFG_NC(GPP_G4),
+		// BOARD_ID
+		PAD_CFG_NC(GPP_G5),
+		// NC
+		PAD_CFG_NC(GPP_G6),
+		// TBT_Detect
+		PAD_CFG_NC(GPP_G7),
+
+// GPP_H
+	// CNVI
+		// NC
+		PAD_CFG_NC(GPP_H0),
+		// CNVI_RST#
+		PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
+		// CNVI_CLKREQ
+		PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+		// NC
+		PAD_CFG_NC(GPP_H3),
+
+	// I2C
+		// T23
+		PAD_CFG_NC(GPP_H4),
+		// T22
+		PAD_CFG_NC(GPP_H5),
+		// NC
+		PAD_CFG_NC(GPP_H6),
+		// NC
+		PAD_CFG_NC(GPP_H7),
+		// NC
+		PAD_CFG_NC(GPP_H8),
+		// NC
+		PAD_CFG_NC(GPP_H9),
+
+	// I2C
+		// NC
+		PAD_CFG_NC(GPP_H10),
+		// NC
+		PAD_CFG_NC(GPP_H11),
+
+	// PCIE
+		// NC
+		PAD_CFG_NC(GPP_H12),
+		// NC
+		PAD_CFG_NC(GPP_H13),
+		// G_INT1
+		PAD_CFG_NC(GPP_H14),
+		// NC
+		PAD_CFG_NC(GPP_H15),
+
+	// Display Signals
+		// NC
+		PAD_CFG_NC(GPP_H16),
+		// NC
+		PAD_CFG_NC(GPP_H17),
+
+	// CPU Power
+		// CPU_C10_GATE#
+		PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	// TIMESYNC
+		// NC
+		PAD_CFG_NC(GPP_H19),
+
+	// IMGCLKOUT
+		// NC
+		PAD_CFG_NC(GPP_H20),
+
+	// GPIO
+		// GPPC_H21
+		PAD_CFG_NC(GPP_H21),
+		// TBT_RTD3_PWR_EN_R
+		PAD_NC(GPP_H22, NONE),
+		// NC, WIGIG_PEWAKE
+		PAD_CFG_NC(GPP_H23),
+};
+
+#endif
+
+#endif

src/mainboard/system76/cml-u/ramstage.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/cml-u/romstage.c

@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct cnl_mb_cfg memcfg = {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	.spd[0] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa0},
+	},
+	.spd[1] = {.read_type = NOT_EXISTING},
+	.spd[2] = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {.spd_smbus_address = 0xa4},
+	},
+	.spd[3] = {.read_type = NOT_EXISTING},
+
+	/*
+	 * For each channel, there are 3 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, but the last 3 sets are
+	 * not used in CNL, so we only define the three sets that are used
+	 * and let the meminit_lpddr4() routine take care of clearing the
+	 * unused fields for the caller.
+	 */
+	.dq_map[DDR_CH0] = {
+		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
+		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+	.dq_map[DDR_CH1] = {
+		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
+		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
+	},
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7},
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	.rcomp_resistor = { 121, 81, 100 },
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
+	 */
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	.dq_pins_interleaved = 1,
+
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	.vref_ca_config = 2,
+
+	/* Early Command Training */
+	.ect = 0,
+};
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
+}

src/mainboard/system76/cml-u/variants/darp6/hda_verb.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581404, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581404),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11050),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x02451130),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/darp6/overridetree.cb

@@ -0,0 +1,15 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		subsystemid 0x1558 0x1404 inherit
+		device pci 15.0 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""Synaptics Touchpad""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x20"
+				device i2c 2c on end
+			end
+		end # I2C #0
+	end
+end

src/mainboard/system76/cml-u/variants/galp4/hda_verb.c

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 System76
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC293 */
+	0x10ec0293, /* Vendor ID */
+	0x15581403, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15581403),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211020),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41738205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* Intel GPU HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/cml-u/variants/galp4/overridetree.cb

@@ -0,0 +1,8 @@
+chip soc/intel/cannonlake
+	device domain 0 on
+		subsystemid 0x1558 0x1403 inherit
+		device pci 15.0 on
+			# I2C HID not supported on galp4
+		end # I2C #0
+	end
+end

src/mainboard/system76/darp7/Kconfig

@@ -0,0 +1,73 @@
+if BOARD_SYSTEM76_DARP7
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select HAVE_ACPI_TABLES
+	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select PCIEXP_HOTPLUG
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	string
+	default "system76/darp7"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "darp7"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	string
+	default "Darter Pro"
+
+config MAINBOARD_VERSION
+	string
+	default "darp7"
+
+#TODO: subsystem IDs
+
+config CBFS_SIZE
+	hex
+	default 0xA00000
+
+config CONSOLE_POST
+	bool
+	default y
+
+config DIMM_MAX
+	int
+	default 4 # Hack to make soc code work
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config MAX_CPUS
+	int
+	default 8
+
+config POST_DEVICE
+	bool
+	default n
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+endif

src/mainboard/system76/darp7/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_SYSTEM76_DARP7
+	bool "darp7"

src/mainboard/system76/darp7/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += bootblock.c
+ramstage-y += ramstage.c
+ramstage-y += hda_verb.c

src/mainboard/system76/darp7/acpi/backlight.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0) {
+       Name (BRIG, Package (22) {
+                40, /* default AC */
+                40, /* default Battery */
+                 5,
+                10,
+                15,
+                20,
+                25,
+                30,
+                35,
+                40,
+                45,
+                50,
+                55,
+                60,
+                65,
+                70,
+                75,
+                80,
+                85,
+                90,
+                95,
+               100
+       })
+}

src/mainboard/system76/darp7/acpi/mainboard.asl

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6E
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
+}

src/mainboard/system76/darp7/acpi/sleep.asl

@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}

src/mainboard/system76/darp7/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: darp7
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/darp7/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <gpio.h>
+#include "gpio.h"
+
+void bootblock_mainboard_init(void) {
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/darp7/devicetree.cb

@@ -0,0 +1,362 @@
+chip soc/intel/tigerlake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# ACPI (soc/intel/tigerlake/acpi.c)
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	# Enable s0ix, required for TGL-U
+	register "s0ix_enable" = "1"
+
+# CPU (soc/intel/tigerlake/cpu.c)
+	# Power limits
+	register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 28,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 51,
+	}"
+	register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
+		.tdp_pl1_override = 28,
+		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
+		.tdp_pl2_override = 51,
+	}"
+
+# Finalize (soc/intel/tigerlake/finalize.c)
+	# PM Timer Disabled, saves power
+	register "PmTimerDisabled" = "1"
+
+# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+	# System Agent dynamic frequency support
+	register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
+	register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
+	register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
+
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Read LPM_EN, make sure to invert the bits
+	# sudo devmem2 0xfe001c78
+	# 0x9
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "12"
+
+# PM Util (soc/intel/tigerlake/pmutil.c)
+	# GPE configuration
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	# 0x432
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		#From CPU EDS(575683)
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP
+			register "DdiPortAConfig" = "1"
+			register "DdiPortAHpd" = "1"
+			register "DdiPortADdc" = "0"
+
+			# DDIB is HDMI
+			register "DdiPortBConfig" = "0"
+			register "DdiPortBHpd" = "1"
+			register "DdiPortBDdc" = "1"
+
+			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+		end
+		device ref dptf on
+			register "Device4Enable" = "1"
+		end
+		device ref peg on
+			# PCIe PEG0 x4, Clock 0 (SSD1)
+			register "PcieClkSrcUsage[0]" = "0x40"
+			register "PcieClkSrcClkReq[0]" = "0"
+			#TODO: causes failure on resume
+			# chip soc/intel/common/block/pcie/rtd3
+			# 	register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
+			# 	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
+			# 	#TODO: Support disable/enable CPU RP clock
+			# 	register "srcclk_pin" = "-1" # SSD1_CLKREQ#
+			# 	device generic 0 on end
+			# end
+
+			#TODO: Hybrid storage mode?
+			register "HybridStorageMode" = "0"
+		end
+		device ref tbt_pcie_rp0 on end # J_TYPEC2
+		device ref gna on end
+		device ref north_xhci on # J_TYPEC2
+			register "TcssXhciEn" = "1"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 3)"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref tbt_dma0 on # J_TYPEC2
+			chip drivers/intel/usb4/retimer
+				register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+				device generic 0 on end
+			end
+		end
+
+		# From PCH EDS(576591)
+		device ref cnvi_bt on end
+		device ref south_xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 UJ_USB1""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Fingerprint""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 J_TYPEC2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						register "group" = "ACPI_PLD_GROUP(1, 3)"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH0""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_USB3_1""
+						register "type" = "UPC_TYPE_A"
+						register "group" = "ACPI_PLD_GROUP(1, 1)"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 J_TYPEC1 CH1""
+						register "type" = "UPC_TYPE_A"
+						#TODO register "group" = "ACPI_PLD_GROUP(1, 2)"
+						device ref usb3_port4 on end
+					end
+				end
+			end
+		end
+		device ref shared_ram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""PNP0C50""
+				register "generic.desc" = ""FocalTech Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
+				register "generic.probed" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 38 on end
+			end
+		end
+		device ref i2c1 on
+			#TODO: USB-PD?
+			register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
+		end
+		device ref heci1 on
+			#TODO Disable ME and HECI
+			register "HeciEnabled" = "1"
+		end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
+		device ref sata on
+			# SATA1 (SSD0)
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			register "SataPortsEnableDitoConfig[1]" = "1"
+			register "SataSalpSupport" = "1"
+		end
+		device ref pcie_rp6 on
+			# PCIe root port #6 x1, Clock 2 (CARD)
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpLtrEnable[5]" = "1"
+			register "PcieClkSrcUsage[2]" = "5"
+			register "PcieClkSrcClkReq[2]" = "2"
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 3 (GLAN)
+			register "PcieRpEnable[6]" = "1"
+			register "PcieRpLtrEnable[6]" = "1"
+			register "PcieClkSrcUsage[3]" = "6"
+			register "PcieClkSrcClkReq[3]" = "3"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
+				#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
+				register "srcclk_pin" = "3" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp8 on
+			# PCIe root port #8 x1, Clock 1 (WLAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[1]" = "7"
+			register "PcieClkSrcClkReq[1]" = "1"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 4 (SSD0)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[4]" = "8"
+			register "PcieClkSrcClkReq[4]" = "4"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
+				register "srcclk_pin" = "4"
+				device generic 0 on end
+			end
+		end
+		device ref pch_espi on
+			# LPC configuration from lspci -s 1f.0 -xxx
+			# Address 0x84: Decode 0x80 - 0x8F (Port 80)
+			register "gen1_dec" = "0x000c0081"
+			# Address 0x88: Decode 0x68 - 0x6F (PMC)
+			register "gen2_dec" = "0x00040069"
+			# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
+			register "gen3_dec" = "0x00fc0E01"
+			# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
+			register "gen4_dec" = "0x00fc0F01"
+			# LPC TPM
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref pmc hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC2
+						register "usb2_port_number" = "6"
+						register "usb3_port_number" = "1"
+						# SBU & HSL follow CC
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref hda on
+			register "PchHdaAudioLinkHdaEnable" = "1"
+		end
+		device ref smbus on
+			register "SmbusEnable" = "1"
+		end
+		device ref fast_spi on end
+	end
+end

src/mainboard/system76/darp7/dsdt.asl

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//TODO: cleaner solution for ACPI brightness
+#define SYSTEM76_ACPI_NO_GFX0
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+			#include <soc/intel/tigerlake/acpi/tcss.asl>
+		}
+	}
+
+	Scope (\_SB.PCI0.LPCB) {
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}