This fixes the following:
- Fix smmstore_read_region to actually read stuff
- Make the API ARCH independent (no dependency on size_t)
- clean up the code a little
- Change the loglevel for non error messages to BIOS_DEBUG
Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
This patch clarifies the definition of google_chromeec_command.
Currently absence of the definition isn't causing any problem because
wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an
interface which returns only negative error codes.
However, there is a chance that a new wrapper API will be addedl which
check 'ret < 0' to catch errors, assuming other interfaces behave the same.
Or existing wrapper APIs will be broken as soon as they're compiled for
another interface.
BUG=chromium:935038
TEST=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f
Reviewed-on: https://review.coreboot.org/c/31613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On flapjack, retrieve the board information via CBI interface.
Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.
BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Cavium DRAM init might use the RNG for pattern generation.
Initialize it before running DRAM init.
Tested on OpenCellular Elgon.
The RNG generates non identical numbers.
Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.
Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.
Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add an implementation for Bubble sort. For now, only integers can be
sorted in an ascending or descending order. It can be later simply
extended to cover other datasets like strings if needed.
The reasons for choosing bubble sort are:
* it is a simple algorithm
* bubble sort is stable, i.e. it does not exchange entries which are not
needed to be sorted as they are already in order
Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rather than attempt to maintain patches against upstream Tianocore, use
MrChromebox's coreboot framebuffer branch as the default build target.
Rework the Makefile to default to MrChromebox's coreboot_fb branch, but
also allow for aribitrary commits from upstream Tianocore to be used
as build targets.
Ensure the branch is synced on each build, as long as working directory
is clean, and that switching between commits or trees is handled sanely.
Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched
it is unlikely to boot on any device. It can easily be specified via
the 'revision' option if desired.
Test: build for the default stable target, for upstream/master
as the specified revision, and for an arbitrary valid commit hash.
Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMI handler on qemu returned early, due to missing SMM-Revision
Level support.
Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64.
Fixes booting tianocore payload with SMM variable store on qemu.
Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change default VESA/native framebuffer mode (needed for bootsplash and
graphical framebuffer console) from 117h (1024x768 64k-color (5:6:5))
to 118h (1024x768 16.8M-color (8:8:8)) mode.
This provides console output at Lenovo G505S even if e.g. GRUB is the
payload, while it is unlikely to cause any downsides for the other
boards.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ia348199bbd430532b1399706dd84490c9680b5f5
Reviewed-on: https://review.coreboot.org/c/31595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.
However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.
Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Issue spotted using IASL 20190215 on mainboard GIZMOSPHERE_GIZMO2:
"Object is created temporarily in another method and cannot be accessed"
Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This change fixes the power status events for AC and battery
events from the EC. The register that was being used is not
returning the expected information.
BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.
Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On every call of hwilib_find_blocks() the CBFS file will be mapped and
the contents are parsed to get the offsets for every single block. This
is not needed if the CBFS file name is the same for the different calls.
This patch adds a storage for the currently opened CBFS file name in
CAR_GLOBAL and checks on each call if the file to open is already open.
If yes, the file will not be mapped again which saves execution time.
Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex
is only mapped once across several following hwilib_find_blocks() calls.
In addition a test was done to ensure that files with different names
get mapped correctly.
Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was
getting selected for cometlake soc also. Since FSP is not yet upstreamed
for cometlake, compilation was failing due to FSP was not found.
So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only
and excluding for cometlake.
Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
For some reason, wake does not currently work from GPP_D21, but IRQs
are working fine from that gpio. Thus, we have to switch IRQ to
GPP_D21 and wake to GPP_A21, which was previously used for IRQs from
the trackpad. Additionally, we need to use two gpios for irqs and
wake source at the moment because of b:123967687, where FSP is locking
down PCR and configuring ITSS. We need to configure the wake source
gpio as inverted and the IRQ gpio as non-inverted until the bug is
resolved.
BUG=b:121212459
BRANCH=None
TEST=run evtest with trackpad
Use trackpad with ChromeOS UI and make sure it reacts as expected.
Run powerd_dbus_suspend and press trackpad and make sure DUT
wakes.
Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest rev. of the atlas board moves the WiFi wake source from
WAKE# to GPP_B7. The original GPP_A0 in the device tree is just
wrong. This also reconfigures DW1 to the GPP_B group so we can use
GPP_B7 as a wake source.
GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't
actually enable WiFi wake. We'll follow up with another patch to set
up GPP_B7 properly on boards that support it.
BUG=b:122327852
BRANCH=none
TEST=atlas still boots
Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix up the logic of when to include VBOOT2_WORK symbols on x86,
which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled.
Also correct the value of the __PRE_RAM__ macro in the case that
VBOOT_STARTS_IN_ROMSTAGE is selected. In this case, DRAM is
already up and verstage should not be considered pre-ram.
BUG=b:124141368, b:124192753
TEST=Build locally for eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
VBT on Intel(R) systems is available via sysfs as
/sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d
Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We experienced booting issues during FSP-M phase. Applying fix that was
introduced for wedge100s - 817994c1be (mb/ocp/wedge100s/romstage:
Workaround broken platform state) - helped and systems started to
boot properly.
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab
Reviewed-on: https://review.coreboot.org/c/31435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Updating from commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)
to commit id 1e177741:
2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE)
This brings in 11 new commits.
Change-Id: I59d83de49006a6d081b206716002697d39099aa4
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The BL31 on RK3399 is split into multiple segments... the majority goes
into DRAM, but small parts must be put into SRAM and PMUSRAM. With
CB:31123 only the DRAM part was added to memlayout, so the SRAM parts
will not be correctly marked in bootmem and BL31 loading fails the
selfload check. This patch adds the remaining regions to fix the
problem.
Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.
BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The default mapping was probably copy-pasted from a random
board and disabled some interrupts (by implicitly clearing
some register bits).
We provide a new default mapping with some reasoning, that
tries to be most compatible (i.e. avoids to use PIRQ E-H
that are not shareable on some boards).
The following functions had their interrupt pin disabled
before:
o SATA 2 (explicitly, no board seems to enable the device)
o PCIe Root Port #4, #6-#8 (probably by accident)
PIRQs used before this change: A-D, F and H. After this
change: A-D.
Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31498
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We used .aml as the file extension for preprocessed ASL code. That
file gets overwritten with the compilation results, fix that.
Change-Id: I11a03dfbcebb0fd762da7b27862a7bdb9a581b92
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Variants of Hatch need to accommodate single channel DDR. Also,
removing const modifier as we'll need to set these fields
incrementally now. For the single channel configuration, we set
MemorySpdPtr10 to 0. For the dual channel configuration, we set
MemorySpdPtr10 to MemorySpdPtr00.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31262
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The requirements read a bit as if we only encourage coreboot experts to
try to take on these projects. These requirements should be understood
as "this is what you'll need to learn", hopefully guiding interested
people in picking a project that suits their interests.
Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31480
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Static scan-build indicates a possible invalid return from function
spi_flash_cmd_erase(). The root cause is because the scan believes it's
possible for offset to be above the end address in the first pass, thus
not setting a value for variable ret. Assign initial value of -1 to
variable ret to make checker happy.
BUG=b:112253891
TEST=build grunt
Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
A couple people discussed recently how it's a shame that on some
architectures we can bring up a device but then have nothing to do with
it afterwards. Having payloads to choose from would help a lot there.
Change-Id: Ia66f22947d09afe3076cc2ee12f5b652fe80fc3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix
the device configuration in the devicetree.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change sets default bus speed as I2C_SPEED_FAST instead of
I2C_SPEED_STANDARD when board does not provide any speed. This makes
it similar to all other i2c drivers in coreboot.
BUG=b:124403846
BRANCH=nocturne,atlas
Change-Id: I877d837eea2dfebf78ad7d97a32ee2071500625e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Allow EC region to be readable by BIOS/CPU so that flashrom
can read it.
BUG=b:123199222
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set,
run firmware_LockedME test.
Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change bumps up the BIOS region to 28MiB to use the hole
between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only
the top 16MiB actually gets memory mapped. Thus, the change ensures
that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737
TEST=Verified that hatch still boots up. Ensured that fmap dump looks
correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE
SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose
The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2
so it needs to be initialized as per board config
BUG=b:123702398
Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Sarien board may have different touchscreen devices that use the
same I2C slave address but have different requirements such as needing
a special driver or ACPI configuration.
In order to support this the devicetree may be configured with multiple
devices at the same address and at boot time the unused devices will be
disabled.
Because there is no GPIO for selecting the device that is present it can
instead be selected with Kconfig, or by setting a VPD key to the HID of
the touchscreen device that is present. The default for Sarien devices
is to not enable a touchscreen for the OS.
The touchscreen selection is currently limited to the Sarien variant but
this also adds the touchscreen HID for Arcada to Kconfig so it would not
complain about the key not being set.
BUG=b:122019253
TEST=This was tested on a Sarien board by adding a second entry to the
devicetree at the same address. Without this change the SSDT is not
loaded by the kernel because of the address conflict. After this change
no touchscreen is enabled by default, but one can be selected with
Kconfig or by setting the 'touchscreen_hid' VPD key.
Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Under some scenarios the key ladder on the Cr50 can get disabled. If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.
BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>
Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16)
pad in non-inversion mode i.e Rx PAD state is not inverted as
it is sent from GPIO to IOAPIC.
BUG=b:123315212
TEST=Tested for below:
-> Verify touchpad is working fine.
-> TPM init is successful and boot with fixed boot media.
Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
`off_t` is supposed to be signed, but has no (minimum) width
specified. We'll assume 32-bit minimum, like a `signed long int`.
Also include `sys/types.h` in `libpayload.h` so everything is
available through the latter.
Change-Id: I6c0c1bc1a959db7863cbad2ba29318da162431be
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
This macro was unnecessarily complex. Trying to avoid an overflow
for unknown reasons, and instead shifted the result into the sign
bit in C. Using a plain number literal that forces C to use an
adequate integer type seems to be safe. We start with 0xffffffff,
subtract `x` and add 1 again. Turned out to be a common pattern
and can't overflow for any positive 32-bit `x`.
Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It needs to tune usb2eye setting for these ports:
USB2[4] - type-c port
USB2[6] - camera
BUG=b:122878632
BRANCH=octopus
TEST=built and passed usb2eye SI test
Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CAR setup is almost identical to the cpu/intel/non-evict
CAR setup, with the only difference that L2 cache needs to be
separately enabled. Currently this assumes that it is possible
to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short,
it takes nearly 5000ms for my keyboard to become ready.
Timing out before it's ready leads to pretty bad behavior: I cannot use
my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance.
Linux is fine though, possibly because it does its own keyboard init.
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2
Reviewed-on: https://review.coreboot.org/c/31279
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is not mentioned in the FSP spec and doesn't seem to be implemented
for any other FSP than the Broadwell-DE one.
Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.
BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)
Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I think our docs inside of the codebase might not be the ideal place
to announce future events.
First, they might be scheduled so shortly before the conference that the
change, if at all done, would barely make it to the repo and the web. Also,
_if_ really maintained, it would churn the docs unnessesarily. But, I doubt
that anyone of us would want to maintain this here at all. Lastly, I think
that nobody out there would _look for_ upcoming events in coreboot's
documentation. We have bigger problems in the Documentation directory than
this :)
Change-Id: I918e17a427405a05722c6e0d61dc422f94cac809
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/31266
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Philipps great 35c3 talk and Davids and Andreas fosdem talk to the
conferences page. linuxboot adds those to their website too but they
can't be linked to too often :)
Change-Id: I1e7ce078020dc5e9c9d9d47210c70ee16ef2f82e
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/31265
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Core Performance Boost feature in automatic mode.
Also enable C6 state which is a dependency for proper CPB operation.
CPB allows to raise single core frequency from 1000MHz to 1400MHz
during high load if other cores idle. The processor has additional
boosted P-states when CPB is enabled, but these are hidden from OS.
TEST: Higher single-core CPU performance is indicated by increased
memory bandwidth as reported by memtest86+.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2
Reviewed-on: https://review.coreboot.org/c/31229
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are defined for __SIMPLE_DEVICE__ when PCI
enumeration has not happened yet. These should not
really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge
being located on bus 2 and available for configuration, so
I rather leave the code unchanged. Just move these out of
arch/io.h because they cause build failures if one attempts
to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to
avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Traditionally, we have always allocated 1 DRAM ID per part number.
However, on nami, we have run out of DRAM IDs because we have
supported so many different parts. We are now adopting the use of
generic SPD files that are feature-based rather than specific to each
part, allowing us to support multiple parts with a single SPD.
The common SPDs were created by taking current SPDs in Nami (which is
using the same DDR4 parts as Hatch) and zeroing out all the
manufacturer information and part names. Additionally, we zeroed out
bytes 128 (raw card extension, module nominal height), 129 (module
maximum thickness), and 130 (reference raw card used) after verifying
that they are not used in FSP. We verified with these fields zeroed
out, all nami devices could boot up without errors. We also verified
on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic
SPDs boot properly.
BUG=b:122959294
BRANCH=None
TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4
devices that we currently have.
Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
df7aecd "cpu/intel: Configure IA32_FEATURE_CONTROL for alternative
SMRR" introduced a regression because it unconditionally writes to
IA32_FEATURE_CONTROL, which if it is already locked results in an
unhandled exception. The lock bit is already set on a system reboot.
Change-Id: I7d2df9e1b9d767809da7a61ccd877c6c40f132eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31255
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"is_wakeup_source" flag is used to indicate if the concerned device can
trigger a wakeup. This flag is redundant with the "wake" GPE event
definition. So remove the redundant flag and use the "wake" GPE event to
mark the wakeup source.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source
in SSDT if wake GPE is configured. Ensure that the system can suspend
and the device acts as a wakeup source
Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP-S is currently configuring GPIOs that it should not. This results
in issues where mainboard devices don't behave as expected e.g. host
unable to receive TPM interrupts as the pad for the interrupt is
re-configured as something else.
Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.
All mainboards need to call cnl_configure_pads instead of
gpio_configure_pads so that SoC code can maintain a reference to the
GPIO table and use that to re-configure GPIOs after FSP-S is run.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and
CONSOLE could end up non aligned. Currently this is only possible if
the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be
safe than sorry.
Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30420
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.
Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.
BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.
Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current coreboot size is not adequate for adding new features.
Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.
BUG=chromium:903833
TEST=emerge-reef coreboot
Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add maximum width and height options and set the default to 2560x1600
(WQXGA). The framebuffer will be scaled up to the displays' native
resolutions. So this should help with tiny fonts on high-DPI displays.
For laptops, reasonable defaults can be set at the mainboard level.
Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We generate a $(obj)/cb-config.ads once and copy it per stage that uses
it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The
Ada package is called `CB.Config`. As there was no `CB` package yet, add
that too.
Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- improve descriptions of Purism and ChromeOS hardware
- add entry for Libretrend Librebox
- improve description of Mr Chromebox and John Lewis'
3rd party ChromeOS firmware offerings
Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.
Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.
Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
his either sets unwanted or unnecessary settings.
Also this RCBA replay did not even originate from the T400 as this
code was copied from the Thinkpad x200 code on which this replay was
already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay'
Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We already had such a page on the wiki, but it's outdated and the wiki
is supposed to go the way of the dodo anyway.
This is a fresh start to make sure that all ideas we're coming up with
are still current and that there are mentors willing to support them.
Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30972
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.
TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.
Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Neither payloads nor distributors are an integral part of the coreboot
source tree, but they're very important parts of the coreboot
ecosystems, so add some descriptions.
Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's what the doc.coreboot.org docker container is running and when
using its livehtml feature, it listens at localhost, which isn't always
desirable.
With `docker run -e SPHINXOPTS="-H $localip" ...` it now listens at
localip, which is more flexible.
Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31128
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the appropriate system type for the different variants of
the Sarien board.
This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.
Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.
This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c
Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.
The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.
The virtual power button is used during S0ix for the EC to wake
the system with an SCI. There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.
BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.
Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are more common system types and in some cases it is important
to know when a device is a convertible or a tablet or detachable
instead of just a laptop.
This change will select the appropriate SMBIOS enclosure type based
on the selected system type.
This is important for the Intel Virtual Button driver as it does a
check on the SMBIOS enclosure type and only enables the tablet mode
events if it is set to convertible:
https://patchwork.kernel.org/patch/10236253/
Change-Id: I148ec2329a1dd38ad55c60ba277a514c66376fcc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ACPI spec has an asl example for _PLD in the form:
Name (_PLD, Package (0x01) { ToPLD (PLD_Revision = 0x2) })
When I ported this to acpigen and diffed the results I noticed that
the binary blob was no longer provided within a package. The ACPI
spec (section 6.1.8 in version 6.2) defines _PLD as "a variable-length
Package containing a list of Buffers". This commit changes
acpigen_write_pld to use a package (the one existing caller I found
isn't wrapping the result in a package so it doesn't look like
it was intended for the callers of acpigen_write_pld to be responsible
for using a package.
BUG=none
BRANCH=none
TEST=Verified that after this change a package is use and the result
of acpigen matches what was used in the original asl.
Change-Id: Ie2db63c976100109bfe976553e52565fb2d2d9df
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If an acpi_dp table has children but no properties then acpi_dp_write()
will write out a properties UUID and package that contains no properties.
The existing function will avoid writing out a UUID and empty package
when no children exist, but it seems to assume that properties will
always be used. With this change properties are handled in a manner
akin to children so that a UUID and package are only written if
properties exist.
BUG=none
BRANCH=none
TEST=Confirmed that prior to this change a UUID and empty package was
present for a device that had children but no properties. Verified that
after this change the UUID and empty package are no longer present but
the child UUID and package are still present.
Change-Id: I6f5597713a1e91ca26b409f36b3ff9eb90a010af
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.
Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really
doesn't go anywhere today or on previous revs of the board.
BUG=b:110614620
BRANCH=none
TEST=atlas still boots
Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 7696290004.
We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz. So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.
BUG=b:123650686
Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use memory map from fw_cfg e820 map to find cbmem_top in romstage to
avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as
fallback.
Change-Id: I6465085020125fc790257f09eb157030c6ceabcb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.
BUG🅱️123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
in SSDT and BT is functional in discrete and integrated mode.
Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA doesn't detect invalid NV data during AmdInitResume(). In
cases where the data has been erased, or cannot be found, reboot
the system. Otherwise the user will experience a hang when cbmem
isn't recovered and the postcar frame cannot be initialized.
BUG=b:122725586
TEST=Write S3 NV save data with 0xff and force reboot
Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately. Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.
BUG=b:119046283
TEST=veriy device exists in DSDT
Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.
Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The structure is placed inside CBMEM, one should
use types with fixed size. Seems we prefer to
prepare for 64-bit builds even for MMIO pointers.
Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We need sizeof(struct ehci_dbg_info) of 88 but only
reserved 64 bytes. If usbdebug_hw_init() was called
late in romstage, for some builds it would corrupt
CAR_GLOBALs like console_inited variable and stop
logging anything.
Also change pointer initialisation such that
glob_dbg_info will hit garbage collection for
PRE_RAM stages.
Change-Id: Ib49fca781e55619179aa8888e2d859560e050876
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
1. Simplify payload code and convert it to C
2. Save the FDT pointer to HLS (hart-local storage).
3. Don't use mscratch to pass FDT pointer as it is used for exception handling.
Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8
Signed-off-by: Xiang Wang <wxjstz@126.com>
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31179
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures to enable IFD GBE region only for required
CFL RVP8 and 11 supported by Intel IOTG team.
TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected
for CFL-U and WHL-U boards
Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO
pin number instead of the raw GPIO number when possible.
This is necessary if the OS uses a different numbering for GPIOs
that are reported in ACPI than the actual underlying GPIO number.
For example, if the SOC OS driver declares more pins in an ACPI GPIO
bank than there are actual pins in the hardware it will have gaps in
the number space.
This is a reworked version of 6217e9beff
which does not try to convert CROS_GPIO_VIRTUAL.
BUG=b:120686247
TEST=pass firmware_WriteProtect test on Sarien
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7
Reviewed-on: https://review.coreboot.org/c/31080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Datasheets describe the used command as 'I2C Read' but adding the
word 'eeprom' in between should avoid further confusion with other
block commands.
Followups will add a symmetrical pair of commands i2c_block_read()
and i2c_block_write() that operate via I2C_EN bit and have a 32
byte size restriction on block transfers. For some hardware revision
these block commands are available, while 'I2C Read' was not.
Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Convert vboot_platform_prepare_reboot() to call a function in
soc//stoneyridge. A subsequent patch will add another call to
the new function, and this change removes any inference of a
dependency on vboot.
BUG=b:122725586
Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.
BUG=chromium:925961
Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable ASPM L1.2 support for embedded realtek card reader, after change
the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A
TEST=Build and boot up on Arcada platform, check the PCI configuration
on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader
is also 0x0f.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0
Reviewed-on: https://review.coreboot.org/c/31145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI
configuration in devicetree. This change enables exporting the bluetooth
reset GPIO to the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS
Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
XHCI is currently named as XHC1. This leads to namespace lookup error in
the kernel when children USB ACPI devices are added under the scope of
XHCI device.
BUG=b:123296264
BRANCH=octopus
TEST=Boot to ChromeOS; Ensure that the below error is resolved in the
kernel dmesg
[ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup
failure, AE_NOT_FOUND (20170728/dswload-210)
Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reduce the number of fw_find_file calls by returning the file structure
at fw_cfg_check_file. The file structure can then be used to allocate memory
and access the file content directly without recurrence searching.
Remove now unnecessary function fw_cfg_load_file.
Fixed breaking function calls and add include guard at fw_cfg_if.h.
Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Currently, selflock_check() verifies that the binary is loaded in an
usable RAM area.
Extend its functionality so we can also check that BL31 is loaded in
a manually reserved area, and fail early if the range is not protected.
Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently SMBUS registers are accessed through IO, but with stoneyridge
they can be accessed through MMIO. This reduces the time of execution by
a tiny amount (MMIO write is faster than IO write, though MMIO read is about
as fast as IO read) as most of the time consumed is actually transaction
time. Convert code to MMIO access.
BUG=b:117754784
TEST=Used IO to write and MMIO to read, to confirm a one to one relationship
between IO and MMIO. Then build and boot grunt.
Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend. Also create a task to initialize the hostevent
wake mask properly.
BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
from EC console: hostevent (make sure wake mask set)
from EC console: gpioset PCH_WAKE_L 0
Make sure device wakes up
Also, checked to make sure keyboard press wakes up
device from S3.
Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.
Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL moves some initialization steps from bootblock to verstage. This
will save us about 2700 bytes (before compression) / 1024 bytes (after
LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled,
these initialization steps will be done in romstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Separate WDT reset function from WDT driver, then we can use the common
WDT driver and have a board-specific reset function on different boards.
In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config
"MISSING_BOARD_RESET" in Kukui to pass the build for now.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot;
Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31121
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.
BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.
BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the VTd feature is enabled, there will be up to two fixed resources
which are set up by the FSP. Add these resources to the list of system
resources so that the PCI enumerator will know them.
Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents.
In addition turned off Vtd and verified that no DMAR table is generated
at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation of generating DMAR tables, provide the hook in SoC scope
for the systemagent to write ACPI tables. The complete functionality is
SoC-specific. Therefore the entry hook is defined as a weak function which
can be overridden by SoC code. If the SoC does not have support for
generating DMAR tables this hook will do no harm.
Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Select FSP_M_XIP if MAINBOARD_USES_FSP2_0, since all SkyKabylake
boards require FSP-M XIP when FSP 2.0 is used, and since not
having it selected results in a non-booting image.
Also, put select FSP_T_XIP if FSP_CAR in proper alphabetical order.
Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In some cases (e.g. Arm architecture variants), include paths are stuck
into <stage>-generic-ccopts rather than CPPFLAGS_<stage> (in fact, the
whole redundancy between these two is kinda stupid and we should
probably eliminate the latter, but I don't want to get into that right
now). This patch makes sure those paths are also correctly translated
when invoking $(MAKE) for vboot.
Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Working:
- USB (Partially. Check "Not working")
- PCIe
- PCIe graphics
- All SATA ports
- Native memory init
- On-board audio (back and front)
- S3 (Sleep and wake)
Not working:
- Fan control
- USB (If the keyboard has a USB Hub or if the keyboard
is connected through 2 or more hubs then it doesn't
initialize in time. A simple reboot allows the
keyboard to be used in SeaBIOS and the bootloader)
Untested:
- PS/2
- On board graphics
Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ELAN touchpad supports up to 400KHz, so we need to limit its CLK
frequency to 400HKz.
BUG=b:123376618
BRANCH=octopus
TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz
Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Current Melfas touchscreen driver cannot unregister ifself when
connecting without Melfas touchscreen or connecting with other devices.
And Melfas touchscreen FW can use I2C and HID over I2C driver, so
switch to using HID over I2C driver.
BUG=b:122710830
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186
Reviewed-on: https://review.coreboot.org/c/31062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.
sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.
BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.
Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Intel RTC common code driver need to turn on RTC itself.After the
change, cannonlake and icelake platform will have RTC enabled.
BUG=b:123372643
TEST=build and boot up on sarien platform, check .config to see
CONFIG_RTC is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536
Reviewed-on: https://review.coreboot.org/c/31112
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a
conditional preprocessor directive, but its condition was incorrect
because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an
explicit check for !SOC_INTEL_COFFEELAKE is required.
While we are at it, clean up the comment above a bit.
BUG=b:123184474
Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31095
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Port the existing denverton tables to intelblock
- Add C-States table for denverton
Note: Removed code is functionally identical to corresponding
common code.
Tested-on: scaleway/tagada
Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
By default this board is configured to not power up after an
EC reset. However in the case of a cr50 firmware update that
will reset the EC it will end up powered off. In order to have
it stay powered up configure the board to power up. This will
get reset to the configured default when it boots again.
BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.
Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to allow the mainboard to configure the system before a
cr50 initiated update reset add a weak function that the mainboard
can override if necessary.
This will allow a board that would otherwise be configured to
stay off after an EC reset to instead power up after the reset and
not end up in a shut down state after a cr50 update.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot
Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Export the SOC level function to set the After G3 state so it
can be changed by the mainboard. The setting will be restored
by a normal boot but in some circumstances coreboot wants to
ensure that it will be powered up again after a reset.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot and ensure the
host does not power off after the cr50 initiated reset.
Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot. This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.
Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.
BUG=b:123305400
TEST=reliably enter recovery mode on sarien
Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for
upcoming payloads.
BUG=b:121169122
TEST=Build and boot up fine into OS on sarien and arcada platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237
Reviewed-on: https://review.coreboot.org/c/31054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.
BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.
Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The iGPU always needs access to its stolen memory. For proper IOMMU
support, we have to make the OS aware of that.
Directly below TOLUD lies the data stolen memory (BDSM) followed by
the GTT stolen memory (BGSM), the iGPU needs access to both.
Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The ratio_max step is appearing twice when (ratio_max - ratio_min)
is evenly divisible by the ratio step.
This is because in this case there are no rounding down of ratio_max in
the for loop.
Thanks Jay Talbott for the step calculation algorithm.
Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A programmable logic device used by Kontron as EC on their COM express
modules. The name `kempld` is taken from Linux kernel sources, as is the
I2C driver. The meaning of the acronym is unclear, probably: Kontron
Embedded Module PLD.
Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to support the physical recovery GPIO on sarien it needs
to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO
number in the coreboot table appropriately so that depthcharge can
correctly determine the GPIO number. The same is done for the
write protect GPIO in this table.
Additionally since we are reading a recovery request from H1 it
needs to cache the result since H1 will only return true on the
first request. All subsequent queries to H1 will not indicate
recovery. Add a CAR global here to keep track of the state and
only read it from H1 the first time.
BUG=b:121380403
TEST=test_that DUT firmware_DevMode
Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31043
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable gpio_keys driver for bobba and add required configuration in the
device tree to handle the pen eject event.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder.
Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently without any trigger the wakeup event is generated on both the
rising and falling edges of the GPIO input. Add support to specify the
trigger explicitly so that the configuration can be passed to the
kernel.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder and ejected from its holder.
Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add new helper macros to enable configuring debounce duration for a
GPIO input. Also ensure that the debounce configuration is not masked
out.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce
duration is configured as expected.
Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.
Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL adds a new function mt8183_early_init, which includes all
initializations that should be done in early stages. All mainboards
using MT8183 should manually call it in either bootblock or verstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Added new routine cr50_i2c_probe() which ensures that communication
with the Cr50 over I2C is good prior to attempting other initialization
of the Cr50 and TPM state. This avoids a race condition when the Cr50
is first booting that it may reset it's I2C slave interface during the
first few I2C transactions initiated from coreboot.
BUG=b:120009037
BRANCH=none
TEST=Run the Cr50 factory update against Careena board. Confirm that
I2C reads are retried until the DID VID is valid. Tested against debug
Cr50 firmware that forced failure of cr50_i2c_probe() and verfied that
coreboot shows recovery screen.
Change-Id: I47c59a32378ad00336277e111e81ba8d2d63e69a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to
enable USB 2 port 6 and USB3 port 5 which is already enabled in device
tree related changes.
BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.
Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable PCIe WLAN for hatch
1. Enable PCI port 14 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 3 for PCI port 14
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Intel DG41WV, the stage cache gets properly created and used
on S3 resume.
Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Foxconn D41S.
Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25605
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Lenovo thinkpad X200: on cold boot the external stage cache
gets created and the cached ramstage gets successfully used on the S3
resume path.
Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25604
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Intel D945GCLF and Lenovo Thinkpad X60, on cold boot the
external stage cache gets created and the stage cache gets properly
used on S3 resume.
Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25603
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some CPUs, (Intel core2 and pineview) have slightly different SMRR
MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different
location, have slightly different semantics and need SMRR enable in a
locked down IA32_FEATURE_CONTROL MSR.
This change takes away the possibility to (not) lock
IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to
work. Since sockets cover multiple CPUs of which only some support
SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place,
even though it gets meaningless on those CPUs. Locking that bit was
the default anyway.
With this patch Intel Netburst CPUs also configure
IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures
Software Developer's Manual those CPUs support that MSR so issues are
not to be expected.
Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27586
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the common start of transaction.
Fixes a problem where smbus_wait_until_active()
can miss SMBHSTSTS_HOST_BUSY being set, if
transaction completes very fast. Or if we are
single-stepping or executing under SerialIce
emulation.
Change-Id: Icb27d7d6a1c54968950ca292dbae05415f97e461
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implements the common parts of any SMBus transaction
with a stub to log and recover (TBD) from timeout
errors.
Bits in SMBHSTCTL register are no longer preserved
between transactions.
Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Add support for the SuperIO part of IT8528E
* Based on the IT8528E datasheet and tests on vendor firmware
TODO: Add support for accessing EC space, which should be
implemented in src/ec/ instead, as it's a separate logical unit.
No datasheet is publicy available.
Tested on wedge100s.
The serial works under the OS without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It is possible to configure debounce, but leave it disabled by specifying
a 0 value for the timeout. Add a define for allowing to do so via the
PAD_DEBOUNCE() macro.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=compile
Change-Id: I9de61297b0677cc904535a51c16970eecb52021d
Reviewed-on: https://review.coreboot.org/c/30998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"
- Remove support for testing coreboot not in a git repo. Many of
the other linters already don't support this.
- Use git grep to find offending files, then xargs to print out
the lines.
Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kukui with vboot enabled will build with `detachable_ui`, which needs
larger space in CBFS for more complicated assets. So we need to revise
FMAP sections:
- BOOTBLOCK (not really used) only needs <= 32K.
- GBB can be much smaller since assets moved from GBB to CBFS.
- FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can
get larger continuous space.
- COREBOOT(CBFS) should take all space left.
Since FMAP and COREBOOT have changed location, the system will need to
reflash EC (which contains the new bootblock) as well.
BUG=b:123202015
TEST=Builds and boots on Kukui P1
Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove guards around CPU code on which all platforms use parallel MP
init code.
This removes the option to disable HT siblings.
Tested on Foxconn D41S.
Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use parallel MP init code to initialize all AP's.
Also remove guards around CPU code where all platforms now use
parallel MP init.
This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.
Tested on Intel DG41WV, shaves off about 90ms on a quad core.
Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.
Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.
This removes the option to disable HT siblings.
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This places the parallel mp ops up in the model_1067x dir and is
included from other Intel core2 CPU dirs that can use the same code.
Tested on Thinkpad X200 on which boot time is reduced by ~35ms.
Change-Id: Iac416f671407246ee223075eee1aff511e612889
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/23434
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config
and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged
since boards were initially shipped with 13v2 firmware, and changing
it now would cause flashrom to throw a board mismatch error.
Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Followup removes SIPI_VECTOR_IN_ROM and it seems reasonable
enough to force the alignment unconditionally to page size.
Reason for the conditionals is the alignment is not possible
with romcc bootblocks having total size less than 4 kiB.
Change-Id: I0ff2786f80a319ebb3215d4fd696cda3e15c3012
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After merging util/crossgcc: derive date and version from latest commit
(https://review.coreboot.org/c/coreboot/+/30804),
crossgcc build is broken in internal repository due to long version
name;coreboot.org repository is ok because it uses short tag name.
The patch uses "git describe" which is dependent on git tag name.
If tag name is little bit long, it can cause crossgcc build failed.
To avoid this issue, use only short version of hash string
which is fixed length. And it's enough as version string,
because we also use date(CROSSGCC_DATE) together.
TEST=Build crossgcc in both coreboot.org and internal repository
which uses longer tag name and check version string in build log.
Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/31001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.
Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen
Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
Reviewed-on: https://review.coreboot.org/c/30997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Fix regression after commits
4ad7f5b AGESA: Use pcidev_on_root()
33ff44c binaryPI: Use pcidev_on_root()
Previously used call dev_find_slot() returned
pointers to PCI device nodes that were actually
not present in the hardware at all. Register
reads would come back with invalid (0xff) values
and writes would be ignored.
After change to pcidev_on_root(), attempting to
do register operations with non-present PCI
hardware immediately halts with error
get_pbus: dev is NULL!
Change-Id: I785350c171a642207c5fab884a953d45a3bfe592
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds a few southbridge calls needed for parallel MP init.
Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.
Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU.
Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel pineview has the same alternative SMRR MSR and
IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for
that before enabling this feature.
This also exposes a function to fetch whether alternative SMRR MSR's
ought to be used.
Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30868
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit b82afce18a.
Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit.
e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch.
We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs.
Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some usb devices exhibit signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.
BUG=b:122671995
TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link
control" register and usb operation successfully.
Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/30948
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).
Documentation added.
Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)
Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the i82801gx code automatically disabling devices ethernet
NICs attached to the southbridge PCIe ports can now be disabled
during the ramstage.
Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30245
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The implementation is a simplified version of the haswell/broadwell
code. This also adds a chip option to enable coalescing from the
devicetree.
Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Sometimes, it’s not clear, what log level is configured (in Kconfig and
CMOS), so print the log level in the banner.
coreboot-4.9-354-gff6e99cebe Tue Jan 15 15:23:20 UTC 2019 bootblock starting (log level: 7)...
Change-Id: I82c87ae90cd53fd47458fc6df3ef2c7f238f0f3d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
```
if (!(a & (0xffff << 16))) {
^~
src/lib/libgcc.c:40:18: error: result of '255 << 24' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xff << 24))) {
^~
src/lib/libgcc.c:45:17: error: result of '15 << 28' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xf << 28))) {
^~
```
Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/23361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support
set HeciEnabled = 1, To Enable heci communication
set speed_shift_enable = 1 To Enable Speed Shift Technology support
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c
Reviewed-on: https://review.coreboot.org/c/30929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on
comparison. The result is that the limit is effectively FFFFFh.
Add one MiB to the register value to make TSEG 8MiB instead of 7MiB.
Fixes a crash related to SMRR not matching the TSEG region.
Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
RISCV parts can be created with any one of four CPU modes enabled,
with or without PMP, and with either 32 or 64 bit XLEN.
In anticipation of parts to come, create the Kconfig variables for these
architecture attributes.
Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30348
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC
memory mapped register but not pci config spaces. Change the programming
to affect that difference.
BUG=b:122425492
TEST=Change System Power State after failure to "s5 off", and boot up
onto sarien platform, check the register with iotools mmio_read32
0xfe001020 and bit 0 is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e
Reviewed-on: https://review.coreboot.org/c/30945
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The general rule is to configure GPIOs used by coreboot in bootblock
(using the reset table), and GPIOs used by OS in RAM stage.
However, GPIO_9 will be used as both, and we need to reconfigure it to
properly set up debounce, however, it is no longer possible to change
bootblock, so we also configure it in RAM stage to make the new
debounce configuration take affect.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03
Reviewed-on: https://review.coreboot.org/c/30922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
FT4 has a strange property where whenever the debounce registers for any
one gpio are changed, the FT4 disables interrupt propagation for ALL
gpio irqs for ~4ms.
In other words, if an edge interrupt of one gpio happens exactly during
this debounce-irq-off window immediately following the configuration of
another gpio, the interrupt will be lost.
It is quite difficult to deal with this in the kernel, since during kernel
boot time, drivers & devices are probed asynchronously, meaning it may
happen that an already loaded driver may miss an interrupt when some
later driver is being probed and configuring its gpio interrupt.
To eliminate this possibility, we pre-configure the debounce registers in
ram stage for all gpios that will be used as irqs later by the kernel
using the same configuration as used by the kernel, as per this table:
IRQ Debounce
Edge Remove Glitch
Level High Preserve Low Glitch
Level Low Preserve High Glitch
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
tpm tpm0: Timeout waiting for TPM ready
Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b
Reviewed-on: https://review.coreboot.org/c/30921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Declaring a Kconfig symbol ahead to override its default also always
sets implicit dependencies. If the original symbol doesn't have any,
Kconfig gets confused.
Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.
Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Whiskeylake processor have an internal device called Camarillo
dedicated for thermal management support, turn it on so processor
thermal driver can be loaded.
BUG=N/A
TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0
can be seen.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7
Reviewed-on: https://review.coreboot.org/c/30858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set PL1 and PL2 values to 25W and 51W respectively for
processor power limits control.
BRANCH=None
BUG=b:122343940
TEST=Built and tested on Arcada system
Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform.
This patch add following chages
- Add overridetree.cb for RVP11
- Select skylake PCH-H chipset config for RVP11.
- Add GPIO table as per board schematics.
- Add audio verb table for RVP11.
- Set the UserBd UPD to BOARD_TYPE_DESKTOP.
BUG=None
TEST= Build and flash, confirm boot into yocto OS on KBL RVP11
platform. verified PCI, USB, ethernet, SATA, display,
audio and power functionalities.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Id86f56df06795601cc9d7830766e54396d218e00
Reviewed-on: https://review.coreboot.org/c/29809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new Kconfig NO_BOOTBLOCK_CONSOLE to disable the BOOTBLOCK_CONSOLE
option completely. The commit message of fbb11cf (ARM: Separate the
early console (romstage) from the bootblock console.) states that it
doesn't work before romstage on Exynos 5420.
Change-Id: I9b56a52f2555b5233300f27031a9ef50e7ab7cea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 392211f0:
2018-04-23 13:07:25 -0700 - (Update Android signing to support signature scheme v2)
to commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)
This brings in 159 new commits.
Change-Id: I7fea9ff1e4109d4dbc979289172191f677438933
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.
BUG=N/A
TEST=Build and boot up on Arcada platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Reviewed-on: https://review.coreboot.org/c/30280
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.
This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Route IO 0x6e/0x6f to LPC bus
* Setup ITE8526 in early_mainboard_romstage_entry
* Fix romstage serial console by disabling internal uart default setting
* Unselect CONFIG_INTEGRATED_UART, as it doesn't use internal UARTs
* Select CONFIG_DRIVERS_UART_8250IO, as it has a SuperIO serial
* Configure UPDs related to serial
Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Default to FSP binary and headers shiped in 3rdparty/fsp.
* Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de
* Select HAVE_FSP_BIN to build test the platform
* Fetch FSP repo as submodule
* Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0
* Introduce FSP_SRC_PATH for FSP source file
* Add sane defaults for FSP_FILE
Tested on wedge100s.
Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Invert the default instead of selecting it everywhere. Restores the
ability to use its Kconfig prompt.
Beside Qemu targets, the only platforms that didn't select it seem
to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The
latter two were about to be patched anyway.
Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30891
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board has more or less the same as the p5qpl-am except for DDR3
memory and different colors on the ports. Tested with Arch Linux with
kernel 4.20.0-arch1-1-ARCH.
What is tested and works:
- 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz
Some bugs are still present in the DDR3 raminit code though.
- Ethernet
- Internal programmer with both coreboot and stock firmware.
- PCI and PCIe x1 slots
- All USB ports
- S3 resume
- SATA ports
- PEG
- Rear audio output
Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27089
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the only valid GTT setting being 1M, TSEG_BASE can only be
aligned to TSEG_SIZE if it is also 1M. This alignment requirement
comes from the desire to use SMRR to protect the SMM RAM.
Tested on Foxconn D41S.
Change-Id: Ibd879529923a1676f2e78500797a52d8a37b8eef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On CPU's with a non eviction mode we cache the whole ROM to speed up
finding the microcode updates, remove the caching to fill in the non
eviction mode and then turn on caching the whole ROM again to speed
executing XIP code in flash.
Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30682
Reviewed-on: https://review.coreboot.org/c/30813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch revises the pad reset config of speaker reset GPIO pin from
RSMRST to PLTRST. Audio engineer suggested to reset the amps with
warm reset.
BUG=b:122441567
BRANCH=None
TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the
speakers are working well.
Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Update mainboard UART Kconfig for Whiskylake RVP.
TEST=Build and test on Whiskylake RVP.
By default we can still get console from cbmem, and
enable CONSOLE_SERIAL can get logs from UART port2.
Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled.
Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/30861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
PLT_RST_L was asserted twice at boot-up and a glitch was observed
when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE
from HIZCRx1 to be masked.
BRANCH=octopus
BUG=b:117302959
TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high
3.3v during S0ix.
Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30815
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When rmodule is loaded CPU stack alignment is only guaranteed
to 4kiB. Implementation of cpu_info() requires that each
CPU sees its stack aligned to CONFIG_STACK_SIZE.
Add one spare CPU for the stack reserve, such that alignment can
be enforced runtime.
Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26302
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some usb devices exhibits signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.
BRANCH=octopus
BUG=b:115699781
TEST=Verified usb operation successfully.
Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30817
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide options to disable xHCI Link Compliance Mode. Default is FALSE
to not disable Compliance Mode. Set TRUE to disable Compliance Mode.
BRANCH=octopus
BUG=b:115699781
TEST=Verified booting to kernel.
Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30816
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead.
Note that IOTR[0123] is a 64-bit width variable.
Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Note that IMC must sleep while SPI writes are in progress.
Instead of using these ACPI methods, flashrom currently does
raw IO to achieve the same.
Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18537
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only a few boards are using IMC for the onboard fan control,
so regarding the availability of IMC selection it should be opt-in,
not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2
because Gizmo 2 could use IMC for the onboard fan control.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16
Reviewed-on: https://review.coreboot.org/c/30756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017)
chips in a way similar to S25FL116K (ID 0x4015) chip from the same family.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7
Reviewed-on: https://review.coreboot.org/c/30874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In these cases we have to expect a NULL pointer because the IGD
device 0:2.0 may be disabled.
The behaviour still differs from using dev_find_slot(), which may
return a disabled device. Though, if you'd try to read its config
space you'd only read garbage (0xff) and in cases where we filled
ACPI data with devicetree information, the information shouldn't
be interpreted by the OS because of the disabled device.
Change-Id: I1bab8fa3a82daca71d03453315cdd69d8951fc24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30879
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Superseeded with DEBUG_CONSOLE_INIT.
For dbgp_print_data() return early and skip reading
registers when dprintk() would not get printed anyways.
Change-Id: Idf470b8572ad992c8d4684a860412d9140f514ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Under normal circumstances no printk() goes through until
console_hw_init() has completed. This is wanted behaviour,
except when you need to debug the setup of one of consoles.
Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This was used to check romcc-built bootblock and romstage
agree about the location of 16-bit entrypoint. There was
no need to customize it as bootblock size requirement did
not grow. Just check for a fixed location at 4 GiB - 4 KiB.
With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol
for the purpose, since it appears in the same compilation
unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes.
Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=B:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
and ensure bit10 is set.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.
BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This way date and version are automatically updated when util/crossgcc
was changed, the version contains the commit ID and we have less churn
on these variables.
Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reverts commit 6fffd70435.
Doing more tests on the Asus KGPE-D16, it seems to cause a reboot loop
quite often. Therefore, revert the commit.
The problem might be caused by the spinlocks used by `get_option()`, and
which are not used by `read_option()`.
Change-Id: Ic25129aa71c8e8e40a65bb2658de78005766fea8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data
areas before device init." which states that the purpose of setting up
these area's is just to make sure they are sane. On the S3 path doing
this is not needed and can even thrash data set up by payloads (mostly
SeaBIOS) that used that memory.
Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards
that support it. Also removing unnecessary IO standby support since we
don't use this pin to wake up the SoC.
BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=CTS tests with changes
Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30788
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCI_ADDR() is tightly coupled with different setup_resource_map()
variants so move the declaration away from global namespace.
In the implementation of setup_resource_map() use the bottom
12 bits as the register mask like the other variants do already.
Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.
Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
What you see in the table are not the PCI devices
that will be written to. Use a helper MCP55_DEV()
to make you look twice what is actually done.
Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
What you see in the table are not the PCI devices
that will be written to. Use a helper CK804_DEV()
to make you look twice what is actually done.
Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix regression introduced with commit
ad7674e device: Introduce pcidev_on_root() and friends
Function pci_scan_bus() breaks bus->children link
in the devicetree topology while scanning a bus.
While the scan is in progress, accessing PCI
devices with number higher than what is being probed
was not possible because new pcidev_on_root() relies
on having proper topology present at any time.
Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Most boards currently do not use EC firmware from SPI flash in the
IFD, this hides this option by default and shows it only for boards
that need it.
A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to
enable this option for boards that need it.
The following list of boards requiring this was provided by
Lijian Zhao:
1. intel/cannonlake_rvp
2. intel/coffeelake_rvp
3. intel/icelake_rvp
4. google/sarien
5. google/hatch
Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Kukui is going to use ADC#4 as SKU ID, and utilizing EC BoardID as
global board_id (i.e., board revision).
BUG=b:122060615
TEST=make; manually tested on Kukui P1 board.
Change-Id: I7bba368c141a7ba6db11f24b8e8e7158f0fc729e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The ID from ADC on Kukui supports 16 different values and we should list
all voltage values ahead.
BUG=b:80501386
TEST=make; manually verified on Kukui P1
Change-Id: Ic3abe07abfe818ca68e180c262fd431d1167b801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
From `boardid.h`, the uninitialized ID values should be BOARD_ID_INIT
instead of BOARD_ID_UNKNOWN.
BUG=b:80501386
TEST=make; manually verified on Kukui P1
Change-Id: Ie5267e575e38b92ec64a7317defbd00ee153fa0a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume
What does not work:
- Using the second DIMM slot on a channel
G41 can only handle 2 ranks per channel and on this mainboard 1 rank
per DIMM slot. Supporting this would require too much raminit rework
and is not worth it (at least for me)
Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1) Add a Platform Data Region called SI_PDR which is allocated in the flash
descriptor for this platform
2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile
storage.
3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG
so it is clear they are associated.
4) Move the RW_DIAG region to the start of the RW region so that once we can
re-enable a larger BIOS region this sub-region will be in the uncached area
since it is not accessed on a normal boot.
BUG=b:119435206
TEST=tested on Arcada board to ensure expected regions are present
Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Build with TSC_CONSTANT_RATE must fail when this function
is not implemented for the platform. Weak implementation
causes division by zero in timer_monotonic_get() and
turns udelay() into no delay.
Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The option to specify a binary file name was added later for platforms
that do not provide microcode updates in our blobs repository. Alas,
it wasn't visible what platforms these are. And if you specified a file
for a platform that already had one, they were all included together.
Make it visible which platforms don't provide binaries with the new con-
figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and
MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to
include binaries by default or explicitly show that no files are inclu-
ded (default to CPU_MICROCODE_CBFS_NONE).
Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit
CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS.
And clean up the visibility of options: Don't show CBFS related options
on platforms that don't support it and don't show external file options
if the platform uses special rules for multiple files (CPU_MICROCODE_
MULTIPLE_FILES).
Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29934
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.
As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.
Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Sdram config sdram-lpddr3-hynix-4GB.inc for H9CCNNNBKTMLBR-NTD can't
boot on Mickey. It's confirmed that the right config for Hynix
H9CCNNNBKTMLBR-NTD is sdram-lpddr3-hynix-2GB-BK.inc.
BUG=b:122239609
BRANCH=master
TEST=boot on mickey
Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a
Signed-off-by: Loop_Wu <Loop_Wu@asus.com>
Reviewed-on: https://review.coreboot.org/c/30761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add 2 helper function get_board_id() & get_spd_index()
to read board id & spd index from EC.
Rename the old get_board_id() function to get_ec_boardinfo().
BUG=None
TEST= Tested on KBL RVP11, able to read the Board id (0x44)
and verified in serial logs. not verified on KBL RVP8.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ie20bf0d45a3568c2c433e5b844bea86aac07c47d
Reviewed-on: https://review.coreboot.org/c/30306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch add devicetree.cb in baseboard and overridetree.cb
for RVP3, RVP7 and RVP8 variants.
BUG= None
TEST= build with BUILD_TIMELESS=1, static.c remains same on before &
after enabling overridetree.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ib7d492e2a92aed10ad0426d57640d0ed56733847
Reviewed-on: https://review.coreboot.org/c/30623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If HOP_COUNT_TABLE doesn't exist AmdInitLate() returns error when
creating CDIT, which scaries users. This patch turns off CDIT generation.
After this patch AGESA_UNSUPPORTED is returned due to a bug in
AGESA which cannot be walked around without disabling DMI table
generation (`AGESA_STATUS Status = TRUE`, present in open source
version of AGESA too).
Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30475
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix warnings on the console.
coreboot-4.9-214-g0dd2014390 Mon Jan 7 15:17:13 UTC 2019 romstage starting...
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Change-Id: I8501ff256676cd0ec4b59b28f4f1e0f2a9f74cac
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The issue in question was resolved with commit 334be3289d
("nb/intel/haswell: Add support for PEG").
Also add a link to the known issues for Haswell, which has some
information on PCIe.
Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch provides an option to enable or disable IPU (image processing unit),
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on devicetree entry.
Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reading nvdata from non-volatile flash storage. With this patch, it will
pass the firmware test that corrupts FW_MAIN_A and boots up with
FW_MAIN_B.
BUG=b:80501386
BRANCH=none
Test=test_that --board=kukui 172.23.213.147 firmware_CorruptFwSigA
Change-Id: I9ef6bff019ee986ff018202bfd4d4a875526ec6c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/30701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reading rdmsr(IA32_FEATURE_CONTROL) in function set_feature_ctrl_lock()
will generate an exception if the CPU do not support this MSR.
Tested on pentium4 (CPUID F65).
Change-Id: I72e138e3bcffe1dcd4e20739a8d07c9abfab4f80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Explicitly configure the minimum assertion width values to ensure
that they are set as expected and are not using unknown defaults.
Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Enable the active-low recovery mode GPIO now that new boards are
available which have an external pull-up instead of a pull-down so
it can be asserted properly by servo.
This was tested on a Sarien system by holding the recovery button
on the servo board and tapping the cold reset button and ensuring
that it enters recovery mode.
Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
These platforms use the standard fixed function power button
and do not need a second power button device declared or the
kernel will end up with two devices reporting the same event.
Change-Id: I6fe2b201a6a6f6307a0c4bd6a61f56cfcdd88bf4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Expose the FSP tunables for the chipset minimum assertion width
settings which can be configured per-board.
The defaults appear to be different from what is listed in the FSP
header documentation so I tried to list what the actual default is
based on the source rather than what is stated the header comments.
Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add logging of chipset events on boot into the flash event log.
This was tested on a google/sarien board to ensure that events
like "System Reset" are added to the log as expected.
Change-Id: I38498cef36d8cc9c8a1f63d12618ea768b65254c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.
This is useful for cbfs access in pre-CAR environments.
Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch fixes icelake build brokenness due to bootblock size
issue.
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a icelake board it is over
the current 32K limit.
BUG=b:122485106
TEST=Able to build dragonegg
Change-Id: I66706e66ac1bce677fe11022d0eef44b9efc2e76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
For these platforms, the first PCI node on devicetree
is not the root of PCI bus hierarchy, and the topology
(bus->children and dev->sibling links) are getting
manipulated during HyperTransport enumeration.
This workaround reverts back to old dev_find_slot() with
its bad semantics.
Change-Id: I19745c3070c12e562ffab2f0243c9d91dd051c72
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit dropped the "draft" concept and replaced it with private commits
and work-in-progress commits, options that can be used independently
from each other.
Change-Id: I6abe267c2091c750fc234057be3a4e62adb59c4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Following changes are done to enable touch screen support on hatch
1. Enable I2C1 device at 400Khz at 3.3V
2. Configure GPIO for touch screen
3. Add ACPI entry for ELAN touch panel
4. update GPIO table with not connected GPIO pins for panel
BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.
Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If requested EHCI function is not on bus 0, we would
need to open MMIO windows and configuration register
space for the connected upstream PCI bridge for it
to work. We don't plan to do so.
Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The first stage attempting to initialise usbdebug
gadget will leave it marked as non-present if none
is detected. This allows further stages to bypass
usbdebug init sequence.
Change-Id: I1491d7fab3c89f210fb03b32481f697bc7a1d1e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The EHCI hardware needs to be initialized only once during CAR stages.
Some exception need to be made when a blob messes with the EHCI
hardware. To achieve this add a fixed location in the car.ld linker
script such that the ehci debug information can be shared across CAR
stages.
Currently this means only romstage and bootblock, but verstage can
also be hooked up later on.
Tested on google/peppy: Both the bootblock and the romstage properly
output console.
Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
BUG=b:119899987
TEST=build and flash to rammus, log into rammus and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.
Signed-off-by: marxwang <marx.wang@intel.com>
Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b
Reviewed-on: https://review.coreboot.org/c/30607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Elan touchpad require connected i2c clock to be running at 400Khz, with
the modification can get 404Khz speed from Arcada EVT platform.
BUG=b:119628524
TEST=Build and boot up on Arcada platform, measure the i2c clock is
around 400Khz.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087
Reviewed-on: https://review.coreboot.org/c/30653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The vbt was extracted from the option rom found on stock images.
The vbt.bin is the same across all variants.
The VBT has a modified BDB block 43, the 'Backlight info block' such
that the inverter type for the panel in use is set to
2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE).
This only seems to matter on Windows, as without it changing the
backlight duty cycle does not work.
Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30487
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Without eist enabled, fizz's CPU clocks are locked at the
base frequency, and don't scale up or down. This prevents
fizz from idling properly and turbo boost from functioning,
so enable it (as is done for all other KBL boards)
Test: build/boot google/fizz, ensure CPU clocks scale as expected
Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Expose the function that can unconditionally re-initialise
EHCI debug host and gadget.
Given the missing header in soc/intel files that prevented
building with USBDEBUG_IN_ROMSTAGE=y, it is not actually
known if those SOCs work at all for usbdebug.
Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
currently, if the IA32_FEATURE_CONTROL lock bit is already
set, VMX status isn't reported. Adjust debug output to
provide more useful infomation on both VMX and lock bit statuses.
Test: build/boot google/chell, observe useful output in cbmem log
regardless of lock bit status.
Change-Id: Ie50f214f7e3fcfd6c3d0d2de034a93518c0a6b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add possibility to update microcode from BLOBs repo.
No need to copy headers around which have an unclear license.
Tested on wedge100s:
* Microcodes are included into FIT.
* Still boots to Linux.
* 3rdparty/blobs at dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1
Change-Id: I8ecfb7302a7fc847a51934942f6d323a4f96abba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Note that while these boards had entry 0x0ff0 in comparison
to 0x0ffc of the get_default_pci1234() initialisation, the
implementation of get_pci1234() unconditionally overrides
the first entry.
Change-Id: I8bec612f84fe3c3a0c21fc1e10629368857e9c5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All these boards use the same default initialiser.
As this is initialized late after device enumeration,
it can't really be used to alter platform configuration.
Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Semantics of dev_find_slot() are ill in the sense that
it only works after device enumeration has completed in
ramstage. Plan is to declare it as deprecated.
Introduce pcidev_on_root() and pcidev_path_on_root()
functions to replace cases where this was called with
static argument bus == 0. New implementation only walks
the root bus of the PCI tree, while old one walked
the entire linked list of devices.
Introduce pcidev_path_behind() to replace cases where
argument bus != 0. The required parent node is typically
one of the PCIe root functions that you locate using
pcidev_on_root() above.
New forms are safe to use with early devicetree and
before PCI bus numbers have been assigned.
Change-Id: Ie20598d48b4cf6e35e45fc90804bad4728437fc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.
Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the `git-format' tool to sanitise coreboot commits such that
they conform to coreboot's coding style.
This fancy piece of machinary allows one to have LibFormat from
Clang to automatically check your commit conforms to coreboot's
coding style, fix any issues automatically and provides you a
diff you may review and apply at your convenience.
N.B. When the `clang-format' binary is not found we issue a warning
that the test was skipped and carry on as usual. Hence, this is
strictly non-enforcing at this current time. You may use it at your
leisure.
Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/c/8037
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update to latest version of iasl:
(From the acpica.org changelogs)
* Fixed a regression introduced in version 20180927 that could cause the
compiler to fault, especially with NamePaths containing one or more
carats (^). Such as: ^^_SB_PCI0
* Added a new remark for the Sleep() operator when the sleep time
operand is larger than one second. This is a very long time for the
ASL/BIOS code and may not be what was intended by the ASL writer.
* Implemented detection of extraneous/redundant uses of the Offset()
operator within a Field Unit list. A remark is now issued for these.
For example, the first two of the Offset() operators below are
extraneous. Because both the compiler and the interpreter track the
offsets automatically, these Offsets simply refer to the current
offset and are unnecessary. Note, when optimization is enabled, the
iASL compiler will in fact remove the redundant Offset operators and
will not emit any AML code for them.
Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/28944
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Write a range of memory with special pattern, and read it back to check
whether the read value same as write.
The test pattern include 8bit offset read write, 16 bit offset read
write, 32bit offset read write, and cross testing.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28845
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is from Linux, commit 3856081eede2. The commit message there
is:
> commit 3856081eede297b617560b85e948cfb00bb395ec
> Author: Y.C. Chen <yc_chen@aspeedtech.com>
> Date: Thu Feb 23 15:52:33 2017 +0800
>
> drm/ast: Fix AST2400 POST failure without BMC FW or VBIOS
>
> The current POST code for the AST2300/2400 family doesn't work properly
> if the chip hasn't been initialized previously by either the BMC own FW
> or the VBIOS. This fixes it.
>
> Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
> Acked-by: Joel Stanley <joel@jms.id.au>
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
Tested on a Supermicro X10SLM+-F with an AST 2400 where the BMC flash
chip has been completely erased. Before the patch, the display resembled
a rainbow. After the patch, the display works well.
Original-Signed-off-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Original-Tested-by: Y.C. Chen <yc_chen@aspeedtech.com>
Original-Signed-off-by: Dave Airlie <airlied@redhat.com>
Change-Id: I72efcf907fbd1263fe21d4f36fe900b305419c44
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This means that any PCIe device placed in a PEG slot should now work.
During S3 resume, link training sometimes does not complete before
device enumeration. However, no tangible issues have been observed.
Fixing it would introduce a rather large delay in S3 resume.
There are a few minor shortcomings:
- Using PEG for display output is not yet supported.
- Only PEG2 is supported. An extra (unknown) training sequence is said to
be needed for PEG3.
- The ACPI _PRT method is not yet generated, so legacy interrupt routing
doesn't work for devices with multiple functions.
Tested on an ASRock H81M-HDS. Using a Radeon HD 6450 graphics card works
under GNU/Linux, with PRIME [1]. An x1 PCIe card was also tested in the
PEG slot, and it appears functional.
[1]: https://wiki.archlinux.org/index.php/PRIME
Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL.
The existing Lynx Point systems probably don't end up dereferencing
NULL pointers this way. However, it might occur on a system using
Flexible I/O to remap PCIe root ports to other functions.
Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues
presented themselves.
Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30079
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing SATA ACPI code for Lynx Point implements some methods and
devices, but not completely. These methods are optional and only used in
IDE mode. The code was likely copied from bd82x6x, where it has since
been removed.
As a result, many remarks produced by iasl about unreferenced objects
are eliminated.
Tested on an ASRock H81M-HDS and an Acer C720. No issues with SATA
were observed.
Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30149
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing code has several messages that are only printed when the
DEBUG variable is set. These messages are not verbose, and are quite
useful to see how the script is progressing. So, print them
unconditionally.
Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
crosfirmware.sh has dependencies that might not be installed on some
systems. If a dependency is missing, provide a clear message about the
issue and how to resolve it.
Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30549
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's quite useful to know the download progress, as it can take a while
even with a fast connection. For example, the peppy recovery image is
~600 MiB. It also lets the user know that disk space is being filled.
Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some systems, such as Debian 9.6, `parted` and `debugfs` are located
in /sbin. Adding /sbin to PATH means that this script can work when run
as a regular user.
Change-Id: I151dba467e2b196f13093334273dae8a05865491
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.
Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.
Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add reset delay in power resource to prevent from failing to bind after
unbinding. And boards including yorp series - bobba / phaser and bip series
- ampton are affected.
BUG=b:121286833
BUG=b:117474421
BUG=b:121019320
BRANCH=None
TEST=emerge-octopus coreboot,
verified that WACOM touchscreen can re-bind successfully.
Change-Id: Icf690fc8e9450d559b642d1c88e29ff5d52c5488
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch enables the SATA for hatch,
* Enable the SATA port 1.
* Configure the GPIO for SATA.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30435
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The feature is used to enable PCI MMIO accesses behind
PCIe links (or bridges) before PCI enumeration has been
completed.
Add the feature for bootblock, verstage and postcar, it
is required with add-on PCIe serial cards for early
console output. It's up to the board specific code to
configure PCIe root port prior to calling console_init()
for this to work.
Remove feature from ramstage, it bypasses any resource
allocations and bus number assignments.
For the moment PCI configuration support before ramstage
is available only on ARCH_X86.
Also switch from device_t to pci_devfn_t.
Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Platforms with SSE=y or SSE2=y will invoke romcc with -mcpu=k7.
This implicitly enabled romcc to consume MMX registers, if XMM
set was consumed first.
Explicitly tell romcc not to clobber MMX set.
Change-Id: I37f1d6ea01873036712dfbb32bb1dcd5d769e85d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This board runs well with coreboot. The documentation part of this
commit lists what works and what doesn't.
Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then
boots FreeBSD 11.2. It has also been tested with GRUB directly booting
Debian GNU/Linux 9.6 (kernel 4.9).
Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Processor graphics is disabled on, for example, the C222 and C224
chipsets.
The change to resource assignment in northbridge.c prevents the following
warning that occurs when the IGD is disabled:
> skipping PCI: 00:00.0@3 fixed resource, size=0!
Tested on a Supermicro X10SLM+-F, which has the IGD disabled by the
chipset. The graphics memory is reclaimed and no issues were observed.
Also tested on an ASRock H81M-HDS. This board has an IGD, but no
regressions were observed.
Change-Id: I86d4aef50b6588f08b86c9758a4b95ccd65e9a96
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The existing code sets DEVEN with the intention of enabling the IGD and
Mini-HD audio. However, according to the datasheet [1] and some testing
on hardware, the bits in DEVEN are set by default if and only if the
straps/fuses say the device should be enabled. To illustrate this, here
are a few initial values of DEVEN on some Haswell systems:
Supermicro X10SLM+-F: 0x0000002d
ASRock H81M-HDS: 0x00000039
Acer C720: 0x000000b1
On the X10SLM+-F, the IGD is disabled by default, and PEG10 & PEG11
are enabled by default. On the C720, the PEG devices are all disabled
by default, while the IGD and Mini-HD audio are already enabled.
There are two issues that result from the existing behaviour: PEG
devices are unconditionally disabled, and devices are set as enabled
when it's not actually possible to enable them.
So, don't touch the DEVEN register at this stage, as there are no
benefits.
Interestingly, on an Acer C720 (Google Peppy), a PCI device 00:04.0
appears. It is a thermal sensor. `powerstat` was used to measure idle
power usage over 30 minutes under Debian GNU/Linux 9.6. There was no
change in reported power draw.
[1] Desktop 4th Generation Intel® Core TM Processor Family, Desktop
Intel® Pentium® Processor Family, and Desktop Intel® Celeron®
Processor Family Datasheet – Volume 2 of 2.
December 2013, revision 003, document number 328898.
Change-Id: I242f9138472de5a0b26b5852f632b53b2920132d
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This allows devices to be properly disabled when they are set to `off`
in the devicetree, or when a device has its `enabled` property set to
false.
A message is printed stating that a device is being disabled, even if
it was already disabled via DEVEN. However, it could be useful to have
this information, so such messages are kept.
The device 00:04.0 is a thermal sensor on the Acer C720, but it has not
been named as such in this patch. This is because the public datasheets
never formally acknowledge what the device is, and how it might differ
across platforms.
Tested on a Supermicro X10SLM+-F. The Mini-HD audio is disabled now,
silencing a warning from Linux.
Also tested on an Acer C720 (Google Peppy). Disabling "device 4" from
devicetree.cb works.
Also tested on an ASRock H81M-HDS. For this device, and all other test
devices, there were no regressions observed.
Change-Id: If1504e620967449a09f113a7c771a1ec30380644
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30270
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on sarien platform, able to boot up into OS and stay
at power up state.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf
Reviewed-on: https://review.coreboot.org/c/30374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.
Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CPUID 0xf47 tested on on 945G-M4 board.
Needs more MSR's consistency tests.
To do: test if speedstep.c and speedstep/acpi.c
are ok for model_f4x.
Change-Id: I285ad33804592e3df510d61dd24f14f944e05142
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/17409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Commit 8cf8aa2 [ec/google/chromeec: Use common MEC interface]
changed the return mechanism for the checksum on reads/writes
for MEC devices, but incorrectly handled the passed-in csum
parameter by not dereferencing. This led to the returned csum
value always being zero, which causes all EC commands with non-
NULL data_in to fail with a checksum error.
Fix this by storing the returned checksum in a temp variable,
and only assigning to csum when the pointer isn't NULL;
Test: build/boot google/chell, verify EC hello command succeeds,
keyboard backlight turned on at boot.
Change-Id: I7122c3fdc5a19f87f12975ee448728cf29948436
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root
ports, all others have 8 [1]. The existing PCIe code assumed that all
non-LP chipsets had 8 root ports, which meant that port 6 would not be
considered the last root port on H81, so `root_port_commit_config()`
would not run. Ultimately, while PCIe still worked on H81, all the root
ports would remain enabled, even if disabled in the devicetree.
Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they
are unused, and the MAX constant is incorrect.
Interestingly, this fixes an issue where GRUB is unable to halt the
system.
Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree
do indeed end up disabled.
[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
(PCH) Datasheet, revision 003, document number 328904.
Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30077
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to issue tracker b:119238959 #4 & #6.
Hardware modify design to make GPP_E3 to be a switch of touchscreen
I2C CLK and SDA.
Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during
power on initialization to avoid data transfer during this time.
After touchscreen IC initial complete, control GPP_E3 to high to
make touchscreen I2C CLK and SDA work normally.
Depending on touchscreen IC specification, device take 105ms for
power on initialization.
Change delay time from 120ms to 105ms.
BUG=b:119238959
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, run S5 stress test and verify the result
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86452c1445243c499aeaf931dba286db169c5628
Reviewed-on: https://review.coreboot.org/c/30180
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies the hatch flash layout to support
IFWI 1.6 with the following regions,
Flash Region 0: Descriptor
[0x0 - 0xFFF]
Flash Region 1: IFWI (consist of ME and PMC FW)
[0x1000 - 0x3FFFFF]
Flash Region 2: BIOS
[0x1400000 - 0x1FFFFFF]
Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30413
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard has the BSEL straps hooked up to the SuperIO
similar to the ASUS P5GC-MX and might therefore require a restart.
Tested:
- FSB 800, 1067 and 1333MHz CPUs
- USB
- Ethernet
- Serial
- 2 DIMM slots
- SATA
- Libgfxinit (VGA)
TESTED with SeaBIOS (sercon disabled) and Linux 4.19.
Change-Id: Id845289081751ff8900e366592745f16d96f07c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Any board that uses the AST driver will have support for native graphics
init. So, select the option in the driver instead of every board.
Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix the following warning shown in dmesg:
"ACPI BIOS Warning (bug): Incorrect checksum in table [FACP]"
The table checksum was wrong as it was calculated twice and with the second
time the checksum field wasn't set to zero.
Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.
This also removes all references to LATE_CBMEM_INIT
in comments.
Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the
usgae of Sarien choose to only use USB interface but not over pci
express, so totally disable pci express root port 12.
BUG=b:1246720
TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10
cyles can still device can be listed under lsusb.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d
Reviewed-on: https://review.coreboot.org/c/30350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Some boards may want to initialize watchdog in verstage instead of
bootblock or ramstage, so we need to add watchdog support in verstage.
BRANCH=none
BUG=b:120588396
TEST=build successfully
Change-Id: I13ab84f54d576a0e8c723070b5d9aadd9d63f87c
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Updates to current master.
This includes:
- A fix for textmode scaling on G45
- Refactor things to rely less on inline proving
- Increased width of modeline fields to 32 bits
Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30311
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These chips are still using LATE_CBMEM which was agreed upon to
be removed after release 4.7. It is now more than 1 year later
and they still linger around.
The work and review to bring this code up to date can happen on
the 4.9 branch and then squashed together and merged back into
mainline when done.
Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These boards are still using LATE_CBMEM which was agreed upon to
be removed after release 4.7. It is now more than 1 year later
and they still linger around.
The work and review to bring those boards up to date can happen on the 4.9
branch and then squashed and merged back into mainline when done.
Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A release may be done from an older commit. It's also not a problem as
commits are stored in the reflog (unlike local changes that the script
guards properly).
Change-Id: I26f1c16c1cdfc9e77e28528b3327ce30c5b82b19
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).
This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.
Test: build/boot each affected platform, ensure no change in functionality
Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 999b916015.
The DMIC doesn't have an ACPI id. The patch which enables ACPI
device with id DMIC may create conflict in the feature. Also the
ACPI id "DMIC" doesn't comply with ACPI naming conventions. The
issue for which the patch was introduced, is already addressed in
kernel DMIC driver and the patches are upstreamed in to the Linux
kernel.
Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/c/30151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Similar to i686 on x86_32, compile for nocona on x86_64.
Nocona is the first Pentium 4 CPU that has long mode support.
Required for 64bit support.
Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29877
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without this patch, Sphinx 1.7.9 prints the following warning, and
doesn't emit the table as HTML:
/.../Documentation/mainboard/intel/kblrvp11.md:1: WARNING: Malformed table.
+------------------+---------------------------------------------------+
| CPU | Kaby lake H (i7-7820EQ) |
+------------------+---------------------------------------------------+
| PCH | Skylake PCH-H (called SPT-H) |
+------------------+---------------------------------------------------+
| Coprocessor | Intel ME |
+------------------+---------------------------------------------------+
Change-Id: I17920398126d57eb8815c45e4a0d4b100f46004a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused
us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then
wake early from sleep when waiting for a cr50 reset to turn on a cr50
update.
BUG=b:121203745
TEST=Careena remains in S5 until cr50 reset after cr50 update, and
ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog.
Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Sometimes the platform boots in an invalid state, that will cause
FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()
as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.
Tested on wedge100s. After full reset the system behaves as normal.
Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
When the old syntax is used, gerrit now respends with:
remote: WARNING: deprecated topic syntax. Use %topic=TOPIC instead
Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29983
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's easy to misinterpret or miss altogether the instruction to
run 'make gitconfig', which will cause strange problems a few
commands later. Revise the documentation to make it clearer.
Also adds a blurb further down with a link to find Gerrit
workflow docs.
detached from FETCH_HEAD
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: I49734c724c4d6da716a358cd849938ef14dab3b1
Reviewed-on: https://review.coreboot.org/c/30060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Carl-Daniel made this script a long time ago but it never was picked up
in the tree. Now that USB debugging is way more common it makes
sense to include it.
I have made a number of changes to the original version:
* -h help text
* check for running as root
* enhanced readability (test -> if)
* new execution flow and refined output that better shows the device(s)
attached to the debug port(s)
* handling of Intel rate-matching hubs
* hiding of (bogus) error messages from lspci and lsusb
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305
Reviewed-on: https://review.coreboot.org/c/9305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Expose the FSP interface to enable SATA and PCH side DMI power optimize
options. Actual step executed in FSP, step defined in cannonlake pch
BIOS spec(CDI# 570374).
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Reviewed-on: https://review.coreboot.org/c/30211
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv(system Agent Dynamic Frequency) have 4 settings
Disabled, Fixedlow, Fixedhigh, Enabled.
This patch add all 4 settings in enum definition and
used in devicetree.
BUG=None
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95
Reviewed-on: https://review.coreboot.org/c/30305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller.
This speeds up boot on nocturne by 1.3 seconds:
Before change:
[2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using
the ext4 subsystem
After change:
[0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using
the ext4 subsystem
BUG=b:120960844
BRANCH=none
TEST=build, flash, and boot nocturne; check dmesg to verify that
boot is faster and that you don't see the following log in dmesg:
[0.671501] i8042: Probing ports directly.
Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/30283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TXE PCI device serves no function under Linux, and doesn't
work properly under Windows, so disable/hide it from the OS.
Test: Boot Windows 10 on google/squawks, verify TXE not visible
under Device Manager.
Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...]
in additon to changing the touchpad/touchscreen interrupts from
edge to level triggered, also marked them as maskable. This not only
broke the touchpad functionality, but caused issues with the touchpad
as well. Revert the touchpad to being non_maskable for all cyan
variants with a touchscreen.
Test: boot GalliumOS on google/cyan with a range of kernel versions
(4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional,
touchpad working properly (not jittery)
Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Quoting from the RISC-V Privileged Architecture manual version 1.10,
chapter 3.1.11:
The FS and XS fields use the same status encoding as shown in Table
3.3, with the four possible status values being Off, Initial, Clean,
and Dirty.
Status FS Meaning XS Meaning
0 Off All off
1 Initial None dirty of clean, some on
2 Clean None dirty, some clean
3 Dirty Some dirty
Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28987
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When I debug with HiFive Unleashed, I found that hart 4 could not be
running. Then find the duplicate MAX_CPUS definition. The correct
MAX_CPUS is located in src/soc/sifive/fu540/Kconfig
Change-Id: I583f6ba548daeeb6c7e341dc3fa8817e7dec5697
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/30179
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output
TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation
TESTED with SeaBIOS (sercon disabled), Linux 4.19
Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table]
only generates DMAR tables for boards using FSP 2.0, which
leaves out Skylake Chromebooks, which use FSP 1.1.
Correct this omission by adding the same functionality for
FSP 1.1 boards.
Test: build/boot on U-series Skylake Chromebook, observe
IOMMU fully functional with intel_iommu=on kernel parameter.
Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.
BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When I added the cmos.layout file, I did not realise that the
southbridge code cleverly emulated the "keep state" option.
Tested on an ASRock H81M-HDS. The `Keep` option works as it should.
Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The deleted line crept in with commit 562db3bb3f ("libpayload: find
source of input characters").
Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable`
via CMOS. After this patch, the system no longer powers on as soon as
power is restored after a power failure.
Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine if RAM must be reserved.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces
inside compat strings aren't nice, so let's convert all spaces to
dashes.
Change-Id: I46f2b2d7091782e04df5476e50698001511f664b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The previous settings caused the I2C frequency for the audio bus to be
too high, at 417kHz. The settings in this commit correct the frequency
to 396kHz.
BUG=b:119423345
Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
commit msg copied from
commit id: 64c9f1584c
The GPIO drivers in Windows and Linux for the Icelake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
Change-Id: I94fafd8af13cf229f5c467de5179aed021465739
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
When the BMC firmware module is installed on the KGPE-D16, the
RAM SPD multiplexer lines are disconnected by hardware from the
SP5100 GPIOs and attached to BMC GPIO lines instead.
Set the BMC GPIOs to match the state of the SP5100 GPIOs during
RAM setup.
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/19820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The device ID is documented in "Intel Xeon Processor E3-1200 v3
Product Family Datasheet volume 2" section 2.2.
Tested with ASRock H81M-HDS with Xeon E3-1271 v3. SeaBIOS payload can
find the boot devices, and GRUB payload can boot Debian GNU/Linux on
the SATA disk.
Change-Id: I999391c9bbc6b39526ad7aec8a6d8fe1a9b5f921
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Intel GMA ACPI opregion address needs to be set on S3 resume,
otherwise the Windows display driver fails to re-initialize correctly.
Fix by ensuring the address is set correctly regardless of display
init type used (GOP or VBIOS).
Test: build/boot on google/edgar, ensure internal display functional
following S3 resume under Windows 10.
Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Mirrors addition to Braswell SoC in commit d3d0f07.
Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU
in all kahlee variants, but omitted the explaining comment only in
liara's devicetree.cb. Copy this comment to liara.
Change-Id: I564013a16217445003467e2a0579abd50597b205
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In commit eceba31c7f ("util/lint: Set "acknowledgement" correct"), the
word "acknowledgement" was removed from util/lint/spelling.txt. A more
robust solution is to comment it out, as done for "sepc" in commit
afa5ec8d5f ("util/lint: Update spelling.txt to latest linux version").
Change-Id: Ia976dedc9b31190d22e7b946f14709d5c4577f71
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
They are hopefully stable enough by now.
TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS,
with and without this patch, results in the same coreboot.rom.
Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
util/util_readme/util_readme.sh is specifically a bash script and
requires bash-specific features such as "[[". It doesn't work when run
with a "sh" shell that only implements POSIX features, such as dash.
Thus, tell the user to run the script directly, in which case the #!
line is used.
Change-Id: I5706ffe857c5a148e9776571a377ad8647f9a4c2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
94b761c8e (util/board_status: run dmesg with sudo) attempted to
fetch the console as root locally but instead sudo was put in front
of the remote path which runs as root anyways.
Also unless quotation marks are used the cmd function will see 'sudo'
and 'dmesg' as separate aruguments.
Change-Id: Ib9e9e4b443f4e3ad04c5fda2c2ce626255a190f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bobba would prefer to use different SAR values per sku-id for regulatory
compliance. This commit uses the newly added interface for custom wifi
SAR CBFS filenames.
CQ-DEPEND=CL:*729429
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd
Reviewed-on: https://review.coreboot.org/c/30223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using a fixed filename only allows for one SAR configuration to be
checked into CBFS. However, we have devices with shared firmware that
would desire separate SAR configurations. This change allows boards to
define a function to select one of multiple files stored in CBFS to be
used.
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: Ib852aaaff39f1e9149fa43bf8dc25b2400737ea5
Reviewed-on: https://review.coreboot.org/c/30222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This function returns APIC id for respective cpu core.
BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.
Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements board reset on the Cheza board. The real board
reset used by the operating system uses the PMIC, but unfortunately the
PMIC needs to be configured right for that to work. The PMIC
configuration currently happens in the Qualcomm blob (QcLib) that is run
from romstage, but vboot needs to be able to reboot during verstage
already. Porting all the PMIC initialization code to run in the
bootblock seems excessive (and at odds with the goal of doing as little
as possible before verification), so we'll just do a little hack and ask
the EC to perform a cold reset instead. For vboot purposes, this should
work just as well.
BUG=b:118501305
TEST=Hacked vboot code to call vboot_reboot(), confirmed that board
reset and came back up as expected.
Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO pin map for CNL-H does not match with the OS expected
pin numbers. This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.
I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c
Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO drivers in Windows and Linux for the Cannonlake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
BUG=b:120686247
TEST=tested with write protect GPIO on sarien board. Before this
change the ACPI pin number was 220 which did not correspond to the
pin number in Linux. After this change the ACPI number is 303,
which maps to the correct GPIO in Linux. Now the GPIO value reported
by the kernel changes when the WP pin is toggled in hardware.
Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the generic GPIO library is enabled the code that generates the
GPIO table in ACPI should attempt to get the GPIO pin value from
the gpio_acpi_pin() function.
BUG=b:120686247
TEST=Tested on Sarien board to ensure that GPIO pin exported by
Chrome OS for the Write Protect signal is correct.
Change-Id: I267694b576009f79bacac6eda5f32bbf51742d78
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Creating skeleton files and directories in mainboard for the new Hatch
board. This is to facilitate development for different parties
involved.
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a
wakeup source
BUG=b:119598593
BRANCH=octopus
TEST=Ensure that the system wakes up on trackpad events. Ensure that the
suspend_stress_test runs successfully for 25 iterations.
Change-Id: I28292682cf9c8037abb87d265e49a60139550db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/30171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When building coreboot from scratch with 'make -j4', I sometimes see
this error:
CREATE build/mainboard/emulation/qemu-riscv/cbfs-file.wblRgZ.out (from /.../coreboot/.config)
HOSTCC cbfstool/cbfstool (link)
make[1]: execvp: build/util/kconfig/conf: Permission denied
make[1]: *** [/.../coreboot/util/kconfig/Makefile:92: savedefconfig] Error 127
It happens, I think, because the rule generated by
cbfs-files-processor-defconfig runs 'make savedefconfig', which builds
build/util/kconfig/conf, and something also builds it, at the same time.
Fix this case, by making this rule depend on $(objutil)/kconfig/conf.
The same fix is also precautiously applied to the rule for
$(KCONFIG_AUTOHEADER) in Makefile.
Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are 2 vendor BIOS's for the Lenovo X200 with the difference being the
settings in the VBT blob to accommodate different backlight frequencies.
Linux however sticks with the setting set by the firmware.
Tested on Lenovo X200 with CCFL backlight.
Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not very helpful to tell somebody who feels wronged "that their
mail was probably lost" (in just as many words).
State why we don't go for a mailing list or ticket system for grievances
and encourage contact multiple people from the outset.
Change-Id: Idac4bcdf8b596a7325e463036c580b17a8b2f27b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
PEN_EJECT GPIOs are active high and also require an internal pull-up.
Update the GPIO configuration appropriately.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus
tools open on pen eject. Ensure that the system can enter S0ix and S3
states successfully when the pen is inserted. Ensure that the system
wakes on Pen Eject. Ensure that the system does not enter S0ix and S3
states when the pen is placed in its holder. Ensure that the
suspend_stress_test runs successfully for 25 iterations with the pen
placed in its holder.
Change-Id: Ibf9cb214a8ce7561efbb77a7e99d1e386cf064c3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add mechanism to configure GPE wake event which in turn can be used as ACPI
Power Resources for Wake
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the wake GPE event is added to ACPI Power Resource for
Wake.
Change-Id: Iacc12b8636aaac98a8689a211cbe1dcfe306f342
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update the GPIOs for the next board build. Mostly minor changes but
the polarity change on GPP_E8/RECOVERY on sarien will result in it
booting to recovery every time unless using new hardware.
For this reason the recovery mode GPIO that is passed to vboot is
commented out for sarien. It is only used for testing and currently
it is useful to have an image that works on both board versions.
Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30062
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.
This affects the display-related SOC pads with the following UPD variables:
UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17
Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.
This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg
As well as the current top-of-tree for the FSP sources.
BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel
Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The
concerned GPIO is not connected and hence wont trigger a wakeup. Fix the
GPE wake configuration for synaptics trackpad.
BUG=b:120666158
BRANCH=octopus
TEST=Ensure that the wake on trackpad works with Synaptics touch pad.
Ensure that the system can enter S0ix successfully(run
suspend_stress_test -c 25).
Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30105
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
console->scroll_up() was hanging when console->rows is 0. This
was happening on delan if no screen was attached. If there are no
rows, just return.
BUG=b:119234919
TEST=Boot delan with no flat panel. System boots to OS
Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
FSP defined a special clock source usage 0x70 for PCH LAN device, update
that to google sarien platform.
BUG=b:120003760
TEST=Boot up into OS, ethernet able to be listed in ifconfig.
Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A new liara specific VBIOS updating eDP power sequence is available now,
Change Kconfig to use it if board is google liara.
BUG=b:120534087
TEST=Build liara, booted, tested eDP test compliance.
Change-Id: I444cfa0bd755480e006f11c0d692b25b96129c29
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A liara specific VBIOS was released and merged to blobs. Now coreboot
need to point to the updated blob, so it can use liara specific VBIOS.
Liara Chromebook Stoney VBIOS BRT39865
BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504
Major Changes included:
1. First Stoney VBIOS released to Liara update eDP power up sequence.
BUG=b:120534087
TEST=none
Change-Id: I3b060b1ccfb311584afd0fb66258eb7cc942408d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Recently there has been a change to print ME version. But the stage at
which the version is printed causes the HECI device to remain in D0 state.
This in turn prevents the SoC from entering S0ix state.
This change moves printing ME version a little earlier so that the HECI
device is put into D0i3 state by FSP and the SoC can enter S0ix state
successfully.
BRANCH=octopus
BUG=b:120571529
TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that
the device boots to ChromeOS. Ensure that the device enters S0ix
successfully(using suspend_stress_test -c 25).
Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use CONFIG_CPU_MAX which defaults to 1 instead of CONFIG_RISCV_HART_NUM.
The default value of CONFIG_RISCV_HART_NUM was 0 and cause a jump to address 0.
Add a die() call to fail gracefully.
Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/29993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Correct a build error that occurs when HUDSON_UART is selected.
Replace sizeof() of a nonexistent variable with the intended type.
This was introduced in
bd48b23 "southbridge//hudson: Get rid of void pointer math".
BUG=b:118484178
TEST=Build Bettong with Chipset/"UART controller for Kern"
Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The code annotated by the comment is dealing with root port 7, so update
the comment to reflect that. It looks like the comment was copied from
the root port 3 case, but not updated.
Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The code is based on autoport and that for T430s
Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
Linux payload (Heads), Seabios may also work.
Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram
Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
corresponding SPD datum (3 observed) from CBFS (the mechanism may be
similar to that on x1_carbon_gen1 and s230u, but I do not know how
to find gpio ports for that, and SPD data stored in vendor firmware.)
Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Provide rise/fall times as measured on existing boards. This will
need adjusted for new boards but provides a starting point that
makes I2C clocks look reasonable.
Tested by measuring I2C bus speed and rise/fall times with a scope.
Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add an entry to the soc_clock table for a 216MHz clock so that
the I2C controller clock is calculated correctly when the I2C
bus is used in coreboot.
This was tested by measuring the I2C clock speed on H1 I2C bus
on a sarien board in coreboot and ensuring it is ~400KHz.
Change-Id: I6c3cacdad318a5ce41bc41e3ac81385c2d4f396c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The input clock for the I2C controllers was set at 133MHz but should
really be 216MHz according to the kernel:
https://patchwork.kernel.org/patch/10408729/
"Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C."
This change was tested on a sarien board where an I2C trackpad that was
measuring ~700MHz on I2C and is now measuring ~380MHz.
Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of the memory mapped BIOS region is covered by SRAM, check
that CBFS always fits the effectively mapped region of flash. This
is usually taken care of by reserving the SRAM range in the FMAP
(e.g. as BIOS_UNUSABLE), but can be missed.
Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
I fried my mainboard because I tried to orient my chip by lining a blue dot on
the corner of my chip with a dot depicted on the chip datasheet. They
apparently have nothing to do with each other, and this is normal. Add
warning about this to the docs to hopefully spare others from a similar fate.
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Ib634589aaa11f75bde2ef2e13d2cacc4cae19a3f
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.
BUG=b:119267832
TEST=Build and boot fine on sarien platform.
Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
AMD traditionally claims the resource at I/O port 61 for the onboard
PC-AT speaker. In later designs, the speaker may be omitted in favor
of routing the SPKR signal to the codec.
Some systems implement neither, and for those it is not correct to
identify the resource as a speaker. Modify the EISAID reported to
the OS depending on the system design. The default is that port 61
is reported as reserved. In order to report a speaker, add #define
in mainboard//dsdt.asl.
TEST=check /proc/ioports and iasl -d for both ways using a Grunt
BUG=b:117818432
Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When building grunt with flags set to detect variables that get a value but
then are unused, there are 5 instances that causes error (unused variable).
In most cases it's enough to simply remove the variable. Other instances,
is better to simply use the variables (one instance it's a return value, on
the other instance using the variables makes code more readable).
BUG=b:120260448
TEST=Build and boot grunt.
Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29985
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch lets spike boot to "Payload not loaded" again.
Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to the mainboard-specific directories
for Spike and QEMU.
Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ,
implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM
interrupt.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch does the following:
- improve the style by removing tabs in front of jmp addresses
- Make the code for zeroing variable MTRR more readable (copied from
cpu/intel/car)
- Fetch PHYSMASK high from cpuid instead of Kconfig
Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a raw fmap region SMMSTORE for the SMMSTORE mechanism, while
keeping the initial option to use a cbfsfile.
TESTED on Asus P5QC, (although it looks like the tianocore patches
using it might need some love as they can't seem to save properly).
Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We alwas define uint64_t as unsigned long long, even on x86_64.
Fix PRIu64 to match the definition of the datatype, to prevent
compilation errors when compiling for x86_64.
Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the USB device information for the sarien/arcada variants.
This includes the ACPI _PLD group definitions for the external
ports that indicate which USB2 and USB3 ports share the same
physical interface.
Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add ACPI _PLD group definitions for the external ports
that indicate which USB2 and USB3 ports share the same
physical interface.
Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Linux kernel can use the ACPI _PLD group information to
determine peer ports. Currently to define the group information
the devicetree must provide a complete _PLD structure. This
change pulls the group information into a separate structure that
can be defined in devicetree. This makes it easier to set for
USB devices in devicetree that do not need a full custom PLD.
This was tested on a sarien board with the USB devices defined
by verifying that the USB 2/3 ports are correctly identified
with their peer in sysfs.
Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the ACPI device names for the USB ports to match what
is in the DSDT so USB ports can be defined in the SSDT.
Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a cannonlake board it is over
the current 32K limit.
Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable DPTF support for sarien/arcada boards. This is currently
using placeholder values that are identical that will be updated
after thermal tuning is done.
Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is a dependency issue with the EC DPTF code accessing
methods that are external, but once the mainboard includes the
relevant code they become internal and the current version of
IASL used by jenkins will fail to compile it.
Until the new IASL is deployed everywhere wrap the EC DPTF code
and expect that the mainboard will explicitly enable it.
Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the support needed for DPTF. This includes the methods to
write trip point values, read temperatures, and handle events.
This was tested on a sarien board by inspecting AML debug output
with the kernel while monitoring temperatures and trip points in
sysfs and controlling temperatures with a fan to ensure that when
a trip point is crossed an SCI is generated and the event is
handled properly.
Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29761
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Disable debug output from read/write methods by default
- Use argument to _REG to disable SCI when EC is unregistered
- Change read/write macros to sync level 2 so they can be called
when a mutex is already held
- Define some missing events
Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29760
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code. For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.
Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method to convert from 1/10 Kelvin to Celsius. This
is useful for EC devices where the sensor temperature are
stored in Celsius instead of Kelvin.
Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support using the common ACPI code on more platforms
than just Apollo Lake the DPTF code needs to be told what the
PCI address is for the CPU thermal device.
Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extended events will be handled by the OS kernel driver, but that
driver needs a method exposed by ACPI to read the event data from
the EC and into a buffer.
Tested by generating a hotkey event and reading the buffer from
the Linux kernel driver with acpi_evaluate_object().
Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29674
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC command to enable WiFi radio and send that command at
startup. Tested to ensure WiFi is functional on a sarien board.
Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the COM1 ACPI device based on the existing Kconfig option
CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to
also define another value for ACPI.
Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet
the logic output for WWAN_PERST#_R to high.
BUG=120004153
TEST=Boot up Sarien board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The different PLLs in the fu540 use the same register layout, so use one
function (configure_pll) to program a PLL and wait for it to lock. This
also makes it possible to dynamically calculate the PLL settings later.
TEST=Boot until "Payload not loaded" on HiFive Unleashed
Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29356
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Verify the flash write protection on each boot
* Program non-volatile write protection on first boot
Tested using I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc.
The bootblock is write-protected as long as the #WP pin is asserted low:
* Reprogramming of the status register fails.
* Trying to write to WP_RO region fails.
Programming the WP_RO is only possible if #WP pin is high.
Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/29532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
update the new sku ids of bard/ekko
BUG=b:120257865
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
write the new sku id in cbi and verify the fw to
check it can get the correct settings by the sku id
Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30031
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables mode change as a wake source from S3 and
S0ix. Thus, any time the device switches between clamshell and tablet
mode while it is suspended, it will be treated as a valid user event
and hence wake source.
BUG=b:120349473
BRANCH=octopus
TEST=Verified that octopus wakes up on mode transitions.
Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/30001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to print ME version if UART_DEBUG is
enabled. Check for UART_DEBUG is necessary because talking to ME to
get the firmware version adds ~0.6 seconds to boot time.
TEST=Verified on octopus that ME version printed is correct.
Change-Id: I41217371558da1af694a2705e005429155d62838
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29989
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI registers can be accessed through IO or through MMIO. However, the
offset relationship is not one to one. Therefore, definitions with the
correct offset for MMIO access are needed.
BUG=b:118049037
TEST=Use Chrome OS IOTOOLS io_readxx and mem_readxx to find the correct
relationship between ACPI IO and ACPI MMIO.
Change-Id: Id20754c0fc0af35bc9eb1a4b40c62fbf9ed6304d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add myself as a maintainer of the four mainboards I ported. For those
which were added as a variant, add myself as a maintainer of the whole
mainboard group.
Change-Id: I0e1b54279027fae82ea9f2825e6f27d38ef3c746
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The finalise handler is not called during S3 resume when using the
`BS_PAYLOAD_BOOT` approach. So, adopt the `lpc_final` approach used by
bd82x6x and others.
Tested on an ASRock H81M-HDS. The finalise handler is now called on
the normal boot path, and during S3 resume.
Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The ASRock H81M-HDS doesn't implement a finalise handler. To fix
this, and reduce code duplication in the process, make a common
implementation. There should be no functional change to boards with
existing finalise handlers, since the code is identical among them and
the new, common implementation.
Tested on an ASRock H81M-HDS. The finalise handler works.
Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive
and causes "failed to change power setting" errors in the kernel, so
this change increases the power-up delay to 20mS which allows enough
time for the WACOM device's i2c controller to wake up.
BUG=b:120090384
BRANCH=none
TEST=flash and boot nocturne, log into kernel, execute the following
command and make sure the string is not found :
dmesg | grep "failed to change power setting"
Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We discovered that the gpios previously used for FPMCU_INT_L were in
two different groups with two different voltages (C group was at 3.3V
and D group was at 1.8V). Moving both to B group which is at 3.3V.
BUG=b:119447525
BRANCH=Nami
TEST=unlock OS with fingerprint
register fingerprint
run powerd_dbus_suspend and see if it goes int s0ix
Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that the relationship between IO access and MMIO access has been
established, create read/write functions to access ACPI standard registers
through MMIO.
BUG=b:118049037
TEST=Build grunt
Change-Id: I32c26f342885c0d99b082be98730edcf16ab5dfc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration
is different when a external PCIe device is connected to mPCIe2 slot
which is routed to first PCIe bridge. The first NIC is then assigned
BDF 2:0.0, because it is connected to the second PCIe bridge.
Read the secondary bus number from the NIC PCIe bridge before attempting
to read MAC adress and calculating serial number.
Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel d945gclf and Lenovo Thinkpad X60.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common Intel code to set up smm and the smihandler.
This is expected to break S3 resume and other smihandler related
functionality as this code is meant to be used with CONFIG_SMM_TSEG.
The platform (x4x) using this southbridge will adapt
the CONFIG_SMM_TSEG codepath in subsequent patches.
Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25596
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=on Chromebook Kevin with 64bit userland, it works well.
Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153
Signed-off-by: Adam Kallai <kadam@inf.u-szeged.hu>
Reviewed-on: https://review.coreboot.org/c/29978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This sets up initial clock configuration for QUP and QSPI,
and includes configuration of Root Clock Generators(RCG) and
clock branches enablement.
TEST=build & run
Change-Id: I0b1d7f6daa179c0b24a97d42b66c1a9ee596b0a3
Signed-off-by: David Dai <daidavid1@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/25454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
POWER8 is a specific implementation of ppc64, which is by now outdated
(POWER9 has been on the market for a while). Rename arch/power8/ to
potentially cover a wider range of hardware.
TEST=Toolchains built before/after this commit can build coreboot for
emulation/qemu-power8 from before/after this commit.
Change-Id: I2d6f08b12a9ffc8a652ddcd6f24ad85ecb33ca52
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Makes vboot measured boot mode available for all boards.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add missing files for Intel apollolake and
AMD stoneyridge as TPM driver target.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.
* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries
Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add myself as a maintainer for legacy Intel-based ChromeOS devices
for which I provide coreboot images as a comminuty member, and
as a maintainer for Purism devices in a professional capacity.
Change-Id: I70df3b9e4e36c2e5d73f8888fe0ec220aa8a91b7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the flag '--check=crc32' to the xz compression to use CRC32 for the
integrity check. The linux kernel does not support CRC64 for integrity
checks, which is the default flag on most xz applications.
Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.
Also fix a comment.
Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google
sarien and arcada board.
BUG=b:119058355,119054586
TEST=Confirm audio play back is working on Sarien and Arcada board.
Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Remove the __SIMPLE_DEVICE__ define from files used only in romstage.
This is not required since romstage always defines __SIMPLE_DEVICE__.
Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29821
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The PMIC wrapper is a proprietary hardware to connect the PMIC. This
patch implements PMIC wrapper driver for the communication with PMIC.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/29421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The aleena board uses a display that's not compatible with current VBIOS.
A VBIOS specific for aleena has been merged into blobs, so modify Kconfig
so that it loads the new VBIOS when building aleena, but load original VBIOS
for all other boards under kahlee folder.
BUG=b:112618193
TEST=Build each board under kahlee, one at a time. After each build, opened
build/config.h and searched VGA_BIOS_FILE to verify that the string only
changed for aleena, all other boards remained with original string.
Change-Id: Iccd0853692680908d951edd142a2d8e13a561391
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
When an untrusted OS is running, we would like to use the Cr50
vendor-specific VENDOR_CC_TPM_MODE command to disable TPM.
Before doing this, we should save TPM state. Implement
tlcl_save_state for this purpose.
This needs to live in coreboot codebase since on S3 resume path,
depthcharge is not reached.
Implement the function in both tcg-1.2 and tcg-2.0 for
completeness.
BUG=b:70681930,b:118202153
TEST=hack a call to tlcl_save_state into coreboot on S3 resume
verify in AP console that it is called
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510
Reviewed-on: https://review.coreboot.org/c/29646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clean and refactor the structure of the LinuxBoot payload integration,
to make it more modular and readable. The kernel and initramfs should
handled in separated makefiles.
tested with:
- qemu-i440fx (x86, x86_64)
- cavium CN8100 (arm64)
Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Some "magic" numbers became public available registers/bits after the code
was originally written. Find all magic numbers, and if available in a public
BKDG than replace them with literals.
BUG=b:117648026
TEST=Build and boot grunt.
Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for updating microcodes on FSP 1.0 platforms
before memory is initialized. This is a requirement to
fill other FIT entries except for microcode updates.
Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coming feature "measured boot" relies on VB2_LIB in romstage. In the
case where there is no separate verstage, compile the library just for
romstage as it will then be shared across verstage and romstage code. If
there is a separate verstage, compile the library separately for
verstage and romstage.
Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine is RAM must be reserved.
BUG=N/A
TEST=Intel BayTrail CRB
Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Make pch_early_iorange_init() function similar to
soc/intel/cannonlake/bootblock/pch.c while fixing below issue:
* COM1 not being enabled properly.
TEST=Able to get serial output from an 8250IO UART device at
the standard 0x3f8 base address.
Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ.
Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The sizes of IO_BASE and ILB_BASE areas a incorrect.
Correct IO_BASE_SIZE and ILB_BASE_SIZE values.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is an issue found by the new builder image and needs to be fixed
before we can upgrade to the new toolchain version:
In function `bdk_dram_get_size_mbytes':
src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c:198:
undefined reference to `bdk_pop'
In function `bdk_get_num_cores':
/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h:164:
undefined reference to `bdk_dpop'
In function `init_octeon3_ddr3_interface':
src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c:7550:
undefined reference to `bdk_pop'
Change-Id: Ibf71e4556014795bfedceccfe3837dc9deb29ad2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/29851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
On the updated builder image, the build is failing because the system
compiler has been updated to GCC 8.2.0. It complains about the
possibility of overflow when putting one 30 character buffer plus 2
characters into another 30 character buffer. To fix this, increase
the recipient buffer size by 2.
romcc.c:3645:2: note: 'sprintf' output between 3 and 32 bytes into a destination
of size 30 [-Werror=format-overflow=]
sprintf(buf, "\"%s\"", scratch);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
romcc.c:3649:2: note: 'sprintf' output between 3 and 32 bytes into a destination
of size 30 [-Werror=format-overflow=]
sprintf(buf, "\"%s\"", scratch);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Change-Id: I7879a7202cc3ff52301b10118fc49fcc601f133e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/29850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The resources of the local APIC are not reserved.
Use mmio_resource() to add local APIC resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
ACPI and GPIO base are used by LPC controller, but not reserved.
Both bases are added to the LPC device resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of code in variant.c to update enable
gpio at runtime.
BUG=b:119885949
Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
aligned_memcpy() was introduced to fix issues with platforms that don't
allow unaligned accesses to areas mapped with /dev/mem, but we missed a
few spots. Fix them.
Change-Id: I97ea953455b41a50023ceaca7eb148d60e6b8097
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change is to bump fsp_memory_mainboard_version in order to
trigger MRC full training
BUG=b:119481870
CQ-DEPEND=CL:*716558
BRANCH=reef, coral
TEST=make sure MRC retraining is triggered and the MRC cache is
updated to newer version.
Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/29647
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables HDA audio support on icelake rvp. Add ALC700 codec
verb table and selects SOC_INTEL_COMMON_BLOCK_HDA_VERB config to detect
and initialize codec configuration as specified in verb table.
BUG=none
TEST=verify codec is listed and audio playback is working
Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This implementation adds support of PNOT method included in cpu.asl.
It is needed to notify CPU APCI device to re-evaluate the _CST table
for list of supported C-states.
Change-Id: I135cc3aa32a912c8ad3449d063d533f8873fcc94
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use the common Intel code to set up smm and the smihandler. This is
expected to break S3 resume and other smihandler related
functionality as this code is meant to be used with
CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this
southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent
patches.
Tested on Intel D945GCLF, still boots fine but breaks S3 resume
support because it hangs on SMI.
Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:112332115
BRANCH=None
TEST=ensure at bootup that /sys/devices/pnp0/00:05 exists
and driver link to '../../../bus/pnp/drivers/i8042 kbd'
Also, can now see keyboard in evtest.
Change-Id: I2a6b382be84bc5201beafe21ff8ddee3738bc5c2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29750
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes support for both ICL ES0 and ES1 samples.
Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md
TEST=Able to build and boot dragonegg.
Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add documentation for Ice Lake processor family coreboot development.
Documented so far:
* What is Ice Lake
* Development Strategy
* Create coreboot Image
* Flashing coreboot
Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The touchpad and touch-panel CLK frequency should be smaller
than 400 kHz which described in spec.
Overwrite i2c speed parameters by overridetree.cb
BUG=b:119540449
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage
flash bios and check the touchpad i2c frequency meets the spec.
Change-Id: I32c3e1bbfc2cdf39e9b7865a69996e54346d5f93
Signed-off-by: Carl Yang <carl_yang@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change deprecates boards with id < 2. It updates touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable GPIO at
runtime. Additionally, it configures old enable GPIO as NC.
BUG=b:119885949
Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable gpio at
runtime.
BUG=b:119885949
Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change updates the configuration of GPIO_178 to be active low as
per latest revision on different octopus variants. This effectively:
1. Gets rid of early_gpio_table in different variants -- phaser, meep,
fleex, bobba.
2. Deprecates board id < 2 for bobba, board id < 1 for fleex and
phaser.
3. Adds special early_gpio_table in yorp which has GPIO_178 as an
active high signal.
BUG=b:119885949
Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
PL4 is a preemptive CPU package peak power limit,it will never be exceeded.
Power is preemptively lowered before limit is reached.
This change provides option in devicetree and feeds FSP PowerLimit4 UPD for
power limit purpose.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8
Reviewed-on: https://review.coreboot.org/c/29808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
One common issue with the toolchain is that it takes a very long time
to build while it's somewhat volatile inside the coreboot tree.
Installing the toolchain elsewhere helps keep it safe but since there
is no reliable default location outside the tree, keep the default
as is.
Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This bug/typo was spoted by Felix Held.
As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need
to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control"
located at 0xec.
Used address at 0x114 to enable GPEs is likely a typo.
Patch not tested.
Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The semantics in util/scripts/maintainers.go have changed in that a
file can be part of multiple components. This means that all files
are part of "the rest" now, which doesn't make much sense.
Change-Id: I220afe27e78aa5358fca61851242812f2d763992
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29657
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS used to have a special region for the x86 bootblock, which also
contained a pointer to a CBFS master header, which describes the
layout of the CBFS.
Since we adopted other architectures, we got rid of the bootblock region
as a separate entity and add the x86 bootblock as a CBFS file now.
The master header still exists for compatibility with old cbfstool
versions, but it's neatly wrapped in either the bootblock file or in a
file carefully crafted at the right location (on all other architectures).
All the layout information we need is now available from FMAP, a core
part of a contemporary coreboot image, even on x86, so we can just use
the generic master header locator in src/lib/cbfs.c and get rid of the
special version.
Among the advantages: the x86 header locator reduced the size of the
CBFS by 64 bytes assuming that there's the bootblock region of at least
that size - this breaks assumptions elsewhere (eg. when walking CBFS in
cbfs_boot_locate() because the last file, the bootblock, will exceed the
CBFS region as seen by coreboot (since it's CBFS - 64bytes).
TEST=emulation/qemu-q35 still boots
Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to newest TCG ACPI Specification for Family 1.2 and 2.0
Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA.
Update the table structure definition, create the log area for TPM2 in
coreboot tables and fill the missing fields in TPM2 table. TPM2 should be
now probed well in SeaBIOS rel-1.12.0 or master.
Tested on apu2 with Infineon SLB9665 TT2.0.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The power budget for this mainboard is very limited while the
performance demand is low. Set the CPU clock to the lowest value to
enable maximum efficiency and thus lowest power dissipation.
Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a Kconfig switch to be able to set the CPU clock to the lowest
possible ratio. If enabled the CPU will consume as little power as
possible while providing the lowest performance.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to its need.
Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Provide a library function to set the CPU frequency to minimum
value. This will result in the lowest possible CPU clock with
the lowest possible power consumption. This can be useful in mobile
devices where the power dissipation is limited.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to it's need.
Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
No need to hide prompts, it's a user choice anyway, they should know.
The help texts were just rephrasing the prompts or stating the obvious.
Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gather x86 specific debug options and deflate their code a little. We
keep their hiding rules and help texts, although they don't seem much
useful.
Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of ICL board variants
1. ICL-U
DDR4 - All possible DDR4 memory type
LPDDR4 - Memory down fixed DIMM configuration
2. ICL-Y
All LPDDR4 DIMM on platform
This patch ensures to have all proper SPD configuration.
Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
There is already a function with the name buffer_size(). Adding a local
variable with the same name will lead to the following error on older
GCC versions (e.g. version 4.4.7):
declaration of 'buffer_size' shadows a global declaration
To fix this rename the local variable to buffer_len.
Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
We need to default this to low so the speakers don't activate in S3.
BUG=b:118248953
TEST=Used a scope to look at the line and made sure depthcharge still
beeps.
Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29783
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.
BUG=NA
TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
SeaBIOS 1.12.0 has been tagged. News are
* Initial support for "TPM CRB" hardware
* Improved cdrom media reporting in the boot menu on QEMU
* Improved floppy support on real floppy hardware
* SeaVGABIOS support for QEMU "bochs-display" and QEMU "ramfb" displays
* Several bug fixes and code cleanups
among others, see http://seabios.org/Releases
Tested by running it on a Thinkpad X230.
Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/29724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
We are seeing problems (interrupt storm) with using the same gpio for
FP MCU wake and irq signals. Reverting back to using separate gpios
for wake and irq until we resolve the issue.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop
into S0ix in the EC console. Also, unlock from lock screen with
fingerprint.
Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.
Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?
Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Patches should be applied against edk2 release instead of arbitrary
commit. This aims to simplify Tianocore payload support by other
platforms.
Change-Id: Ib409f6f93eb64d7a9a2f09a75f8e637ab8689410
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/27615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.
BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards
Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The timer interrupts don't appear when HPET is enabled. This
result in Linux reporting 'MP-BIOS bug: 8254 timer not connected
to IO-APIC'
Enabling CONFIG_DISABLE_HPET disables OS use of HPET.
Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation
Hang or Slow Boot Issue.
BUG=Intel #4800413
TEST=Portwell PQ7-M107
Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change makes the early IO decode setup mirror that of other
Intel SOCs and fixes issues with COM1 not being enabled properly.
Tested by successfully successfully receiving serial output from
an 8250IO UART device at the standard 0x3f8 base address.
Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.
We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?
Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The purpose of this tool is to manipulate and get information about the
`Back Up Control, Top Swap` mechanism present on most Intel Southbridges.
This tool is initially written by Peter Stuge.
This tool makes it possible to have a backup mechanism for the
bootblock by using the southbridges Back Up Control Top Swap.
Sometimes it is also possible to circumvent vendor write protection mechanisms
in order to flash coreboot. An example of where this would be useful would be
the Lenovo Thinkpad X60 and T60.
Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18224
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Working:
- SATA on southbridge ports
- SATA on Marvell IDE controller ports
- USB
- COM1
- PS/2 keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCIe x1 ports
- PCI ports
- NIC (MAC address needs to be set in Kconfig or in a CBFS file)
- S3 resume
- Green audio line out connector (the rest is untested)
Not working:
- Floppy port. Does not seem to be mainboard-specific, though.
Untested:
- EHCI debug
TODO:
- Add documentation
Change-Id: I6ed434a691e8ef2a61e0acb1f986a59b8e1ad818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newer kernels only allow root to access the kernel log buffer.
In another case (cbmem) we use sudo to get past that, so we can
expect sudo to be available here, too.
Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/29670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl5 mainboard will follow in separate commits.
Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.
Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There's a typo in the cpu driver causing it to always use the weak
implementation defined in the devicetree instead of the real
implementation.
Tested on qemu-q35, the CPU driver contains valid values.
Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/icelake/acpi/
Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.
Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low. Keeps device awake otherwise.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
S0ix in the EC console.
Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting sku_id() is not enough to get a value to show up in the SMBIOS
tables, it also needs to be returned as a string for the table creation
to consume. This change defines the smbios_mainboard_sku() function
and returns a string constant of "sku#" as expected.
Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Trent Begin <tbegin@google.com>
Sometimes it is necessary to be able to see exact command lines used
when compiling and linking. Use the same scheme as some other
Makefile's - enable verbose output when variable V is set to 1.
TEST=tried building cbfstool with V=1, observed verbose output.
Change-Id: Iff25439aabff79e69d1d94a2c51c60bb0e0d7b80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/29431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bind a volume for .ccache to the `docker-run-local` targets. By default
the current user's $(HOME)/.ccache will be used, it can be overridden
via the DOCKER_CCACHE variable.
Also rearrange some docker parameters to keep the target readable.
Change-Id: I7d0bdb3861ac56361cacfa74aaf8b45c4f135e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9.
This board works quite well under coreboot. A list of what works and
what doesn't can be found in the documentation part of this commit.
The file `data.vbt` matches the VBT in the latest stable version of the
vendor firmware (version 2.20).
Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With this change, coreboot thinks we're running at 1MHz:
DW I2C bus 2 at 0xd1133000 (1000 KHz)
Elan eKT3644 IC Specification (trackpad) requires:
Low Time larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns.
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.
HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.
P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).
The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.
Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.
Verified by gaggery.tsai@intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177
BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
Waveforms measured with oscilloscope and screen shots attached
to bug (comment #177, #155, #100).
Operate trackpad/touchscreen
Review dmesg (kernel) output for correct speed, parameters, and
no errors (e.g. "lost arbitration" or "host controller timeout")
Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Signed-off-by: Grant Grundler <grundler@chromium.org>
Tested-by: gaggery.tsai@intel.corp-partner.google.com
Tested-by: grundler@chromium.org
Reviewed-on: https://review.coreboot.org/29553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Enable HDA controller coreboot driver for Whiskey Lake RVP platform on
top of common code.
BUG=N/A
TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback
is working.
Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Only input from the BJ port is wired to VSYS on Kalista. VBUS from
USB-C is for output only. In other words, Kalista is a source only
device from a USB/PD perspective.
This patch disables EC-EFS, which would be needed for the EC to jump
to RW to get PD power before the AP boots. Kalista will be always
supplied enough power to boot the AP through the BJ port.
CQ-DEPEND=CL:1330171
BUG=b:118386511
BRANCH=none
TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work.
Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29564
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot
Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.
Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/29570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0
for only 2nd SKU.
BUG=none
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/29631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPP_E1 gpio was incorrectly being defined as a no-connect.
Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic.
BUG=b:119508897
TEST=Build and flash nocturne, boot nocturne and
1) Verify nocturne can successfully suspend/resume from S3 and S0ix.
2) Verify wake from wlan wakes device from S3 and S0ix.
To do so,
a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT
b) connect DUT to mobile hotspot
c) sleep device via "powerd_dbus_suspend"
d) turn off hotspot, verify DUT wakes from S0ix
e) enable hotspot again
f) connect DUT to hotspot
g) sleep DUT via "sudo echo mem > /sys/power/state"
h) turn off hotspot, verify DUT wakes from S3
Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an unprocessed flag (-U) which modifies how files are exported.
In the case of a compressed raw file, extract without decompressing.
In the case of a stage or payload, extract without decompressing or
converting to an ELF.
This can be useful for verifying the integrity of a stage or payload,
since converting to an ELF may not be a deterministic process on
different platforms or coreboot versions.
BUG=b:111577108
TEST=USE=cb_legacy_tianocore emerge-eve edk2 coreboot-utils chromeos-bootimage
cd /build/eve/firmware
/build/eve/usr/bin/cbfstool image.bin extract -r RW_LEGACY \
-n payload -f /tmp/payload_1 -U
START=$((16#`xxd -s 20 -l 4 -p tianocore.cbfs`))
SIZE=$((16#`xxd -s 8 -l 4 -p tianocore.cbfs`))
dd if=tianocore.cbfs skip=$START count=$SIZE bs=1 > /tmp/payload_2
diff /tmp/payload_1 /tmp/payload_2
rm /tmp/payload_1 /tmp/payload_2
Change-Id: I351d471d699daedd51adf4a860661877f25607e6
Signed-off-by: Joel Kitching <kitching@chromium.org>
Reviewed-on: https://review.coreboot.org/29616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The common SPI controller driver in src/southbridge/intel/common does
match the SPI controller included in the PCH of Broadwell-DE SoC. Switch
to the usage of this driver and delete the dedicated one for the FSP
based Broadwell-DE implementation.
TEST: Boot mc_bdx1 with SPI driver active in romstage
Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a `docker-run-local` target that is used as a template for the
local build targets (`docker-build-coreboot`, `docker-abuild`, and
`docker-what-jenkins-does`).
Note this changes the user for `docker-what-jenkins-does` which has
(ccache) issues if it's not `root`. Will be fixed in a follow-up.
Change-Id: I9088fb9211726cddc37b17ddf70170c2c382679e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are several files under soc/amd that use units defined by file
porting.h. These units use upper case, and are not recognized by checkpatch,
thus causing problems when defining a pointer (request to use space before
and after the star symbol). These are the definitions from porting.h showing
the units that this patch will change and their coreboot definitions (not all
are actually used):
typedef uintptr_t UINTN;
typedef int64_t INT64;
typedef uint64_t UINT64;
typedef int32_t INT32;
typedef uint32_t UINT32;
typedef int16_t INT16;
typedef uint16_t UINT16;
typedef int8_t INT8;
typedef uint8_t UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
typedef unsigned char BOOLEAN;
typedef void VOID;
BUG=b:118775313
TEST=Build and boot grunt.
Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. In this particular
situation, dev->buf is already pointer to u8, and there's no need to convert
to void *.
BUG=b:118484178
TEST=Build libpayload.
Change-Id: Ib70b8ce11abc88c35be4092f097cfff385921f46
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build CBFS with original code, run objdump and saved output. Added
modifications, build cbfs again, run objdump again, compared objdump outputs.
Change-Id: I30187de8ea24adba41083f3bfbd24c0e363ee4b8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Function write_pci_cfg_irqs() has "no function" variables. One variable is
set and never used, the other is only used to control a print. Remove them.
BUG=b:117950052
TEST=Build grunt.
Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Currently mode-aware DPTF depends on Tablet Mode Switch to load the
right table. This does not scale well with device types and configuration.
This change helps to decouple the mode-aware DPTF from Tablet Mode Switch.
This change allows ACPI to load the appropriate DPTF table based on the
profile number as detected by EC.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29249
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support Multi-DPTF profile, Device DPTF Profile Number is
introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset
0x09. This bit field stays along with Tablet Mode Device flag.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29629
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/
Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a `util/gitconfig/test` subdirectory which will contain tests to run
as executable files, add a helper script.
Add a timeout test that verifies that gitconfig completes in under two
seconds (typical run time is ~30 ms). Add gitconfig tests to the
`testing` Makefile under the `test-tools` target.
Change-Id: Id46f905b9f782e67be97a65d10045c3345dc996b
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23280
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<vendor> seems to be confused about the meaning of our maintainers list.
I get the feeling some use it to organize corporate internal teams and
branches, adding names to the list that don't show up in Gerrit and even
if, often don't react to reviewing requests (within months). Maybe they
even don't know that this is about coreboot.org?
To clarify this:
o Add an introductory paragraph mentioning development on coreboot.org.
o Explicitly state that maintainers should be registered to Gerrit.
o If a topic is tagged as `Supported` or `Maintained`, expect that
somebody reacts to review requests.
Change-Id: I9ee038dc5ee1f4993ba1d230ef6e737f20e2ff8a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/29471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Current implementation works by luck as DCACHE area is actually RAM and
stack can grow and use that RAM outside of the area.
* Set DCACHE_BSP_STACK_SIZE to 0x4000.
* Add an assert to make sure it is set to a sane value on all platforms.
Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29611
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Help automated tools make sense of the output.
Instead of "[name 1 <email> name 2 <email>]", it now prints
"name 1 <email>, name 2 <email>". As long as there are no commas in the
maintainer names, they can be split easily.
Change-Id: I4a254f566404b081a08923bc7ceb49f02039aa2a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29604
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of checking only for three cases, just use a glob parser (that
translates the glob to regex).
After that, maintainers src/arch/x86/memlayout.h emits:
src/arch/x86/memlayout.h is in subsystem X86 ARCHITECTURE
Maintainers: []
src/arch/x86/memlayout.h is in subsystem MEMLAYOUT
Maintainers: [Julius Werner <jwerner@chromium.org>]
The latter entry was invisible to the maintainers tool because its path
description wasn't in one of the supported formats.
Change-Id: I7e5cf4269415269552e35f2c73952ce3dff487e1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a helper function specific to ramstage to add the boot count
information into event log at ramstage.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group event log state information together to manage them better during
different stages of coreboot.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some embedded controllers expect to be sent a command when the OS
calls the ACPI \_PTS and \_WAK methods. For example see the code
in ec/google/wilco/acpi/platform.asl that tells the EC when the
methods have been executed by the OS.
Not all ECs may define these methods so this change requires also
setting a Kconfig option to enable it.
Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ME Cleaner's component has an entry specifying its website, which this
parser didn't know how to handle. Avoid the resulting warning.
While at it, de-C the switch statement and make it work go-style. This
also fixes "R" statements being ignored.
Change-Id: Ifc23e28daba9d85bf690557a80134accea8bed21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Clear remalloced memory
* Fix check for invalid VBT offset in header
* Fix VBIOS checksum generation
* Fix VBIOS size field
* Align VBIOS size to multiple of 512
* Reassign pointers after use of remalloc
* Don't leak on error path
Current version is enough to allow the proprietary Windows Intel GMA
driver to find the VBT in the legacy VBIOS area and it doesn't BSOD
any more.
The LVDS screen remains black, due to an unknown issue with the
proprietary driver, while the VGA works.
Tested with libgfxinit and native graphics init.
Change-Id: If07b1bb51d8fb3499d13102f70fedb36c020fb72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.
Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary
Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35
Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working
Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Instead of having the code for the RAM init time stamps in each
mainboard’s `romstage.c`, factor it out to the northbridge code, done in
commit 771328f7 (intel/i945: add timestamps in romstage).
Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17994
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard also has an external RTC chip, but not on this bus. The
topic is currently in clarification and will be published with a later
patch. In a first step we enable all I2C busses.
Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 and then the reset button
is pressed the PCH will drive SLP_S3 active (low).
Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29513
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EC_SYNC_IRQ from EC to host is level-triggered in practice and
configuring it as edge-triggered on the host results in host missing
events if there are multiple events queued on the EC side. This is
because Linux kernel driver reads one event per irq and the EC does
not de-assert the interrupt line until all events are drained
out. This results in event queue being filled up completely on the EC
and the host failing to see any of those events.
This change configures EC_SYNC_IRQ as level triggered to allow the
host to read events from the the EC as long as the line is asserted.
BUG=b:118949877
Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
* Remove dead code
* Add support for types 2504 and 2505
* Print dock info at romstage entry
* Improve dock disconnect for type 2505
* Move defines into dock.h for future ACPI code
* Reduce timeouts according to spec to decrease boot time on error
* Fix no docking detection (reduces boot time by 1 second)
* Configure GPIO LDN before reading GPIOs
* Use Kconfig values instead of fixed defines
* Add documentation
Tested on Lenovo T500 with docking 2504 and 2505.
Change-Id: Ic4510ffadc67da95961cecd51a6d8ed856b3ac99
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change disables HECI1 device at the end of boot sequence. It uses
the P2SB messaging to disable HECI1 device before hiding P2SB and
dropping privilege level.
BUG=b:119074978
BRANCH=None
TEST=Verified that HECI1 device is not visible in lspci on octopus.
Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change 76ab2b7 ("arch/x86: allow global .bss objects without
CAR_GLOBAL") allowed use of global .bss objects and hence moved around
the macros resulting in car_active returning 0 even for those boards
where CAR is actually active but do not require global migration. This
resulted in boards getting stuck when doing a reset in verstage because
the code flow incorrectly assumed that there was no CAR active and
hence triggered a cache invalidate.
This change fixes the above issue by returning 1 for car_active if
ENV_CACHE_AS_RAM is set even if global migration is not required.
BUG=b:109717603
TEST=Verified that board reset does not trigger cache invalidate in
verstage and does not result in board hang.
Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
1. Add two parameters for panel initialization timing.
> lvds_poseq_varybl_to_blon
> lvds_poseq_blon_to_varybl
2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/
EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage,
and be enabled depends on SKU, thus we can control the delay
time by config APU_DP_VARY_BL.
BUG=b:118011567
TEST=emerge-grunt coreboot.
Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ strom after S3 resume.
For sarien/arcada these are all runtime IRQs only, not wake capable.
Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Select the option to disable eSPI when ACPI is enabled so the EC
is unable to assert an SMI when booted into the OS. There is a
kernel driver that implements the same mailbox interface so it
cannot also be used by the SMI handler.
Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an option that will disable eSPI SMI when ACPI mode is enabled,
and re-enable eSPI SMI when ACPI mode is disabled. Additionally it
ensures eSPI SMI is disabled on the ACPI OS resume path.
This allows a mainboard to ensure that the Embedded Controller will
not be able to assert SMI at runtime when booted into an ACPI aware
operating system.
This was tested on a Sarien board with the Wilco EC to ensure that
the eSPI SMI enable bit is clear when booted into the OS, and remains
clear after resume.
Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make the firmware slot configuration in VBOOT selectable. The following
three modes are available:
-RO only
-RO + RW_A
-RO + RW_A + RW_B
The mode "RO only" is the lowest mode with no safety during update.
You can select either RW_A or RW_AB via Kconfig which will add the
selected parttions to the final image.
Change-Id: I278fc060522b13048b00090b8e5261c14496f56e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_D9 and GPP_D10 to use PLTRST.
BUG=b:119202293
TEST=none
Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3.
Changed GPP_C11 configuration to use PLTRST instead.
BUG=b:114196791
TEST=Build, flash, boot nocturne, log in to kernel and execute
the following two commands and verify it passes :
echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd
sudo suspend_stress_test -c 2
Change-Id: I008532fce963c51a435378001440ac72b5ebfffc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change allows to redirect coreboot console output to COM2 by
setting appropriate UART index in Console menu in Kconfig.
Change is helpful for users which would like to use COM1 port for
other purposes, because COM1 is the only port with hardware flow
control.
Change-Id: I39f88d7e7794f603775a985afe07fef349172e5f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/29255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
VB2_LIB will be used across all stages to hash data. Add it to postcar
stage sources so that it is compiled if postcar exists. In this way the
new function tpm_measure_region() introduced in commit
61322d7 (security/tpm: Add function to measure a region device)
can be used in every stage.
Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Move all implementations to into common folder.
* Add rtc.c for rtc based functions
Allows all Intel based platforms to use VBOOT_VBNV_CMOS.
Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a sku_id() function that returns a static value to
differentiate the sarien and arcada boards.
Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.
This patch add FSP CAR support for kabylake by programming tempraminit
parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.
BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
for successful FSP CAR setup.
Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build AMD Bettong.
Change-Id: I4167c7eeb9339937b064e81e615ceb65f4689082
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A very common pattern in drivers is that we need to wait for a condition
to become true (e.g. for a lock bit in a PLL status register to become
set), but we still want to have a maximum timeout before we treat it as
an error. coreboot uses the stopwatch API for this, but it's still a
little verbose for the most simple cases. This patch introduces two new
helper macros that wrap this common application of the stopwatch API in
a single line: wait_ms(XXX, YYY) waits for up to XXX milliseconds to see
if the C condition 'if (YYY)' becomes true. The return value is 0 on
failure (i.e. timeout expires without the condition becoming true) and
the amount of elapsed time on success, so it can be used both in a
boolean context and to log the amount of time waited.
Replace the custom version used in an MTK ADC driver with this new
generic version.
Change-Id: I6de38ee00673c46332ae92b8a11099485de5327a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If remaining charge is more than x% of the full capacity, the
remaining charge is raised to the full capacity before it's
reported to the rest of the system.
Some batteries don't update full capacity timely or don't update it
at all. On such systems, compensation is required to guarantee
the remaining charge will be equal to the full capacity eventually.
On some systems, Rohm charger generates audio noise when the battery
is fully charged and AC is plugged. A workaround is to do charge-
discharge cycles between 93 and 100%. On such systems, compensation
was also applied to mask this cycle from users.
This used to be done in ACPI, thus, all software components except EC
was able to see the compensated charge. This patch is part of the
effort of moving the logic to EC. With this and the EC changes, EC
can see what the rest of the system sees, thus, can control LEDs
synchronously (to the display percentage).
Another rationale of this move is EC can perform more granular and
precise compensation than ACPI since it has more knowledge about the
battery and the charger.
CQ-DEPEND=CL:1312204
BUG=b:109954565,b:80270446,chromium:899120
BRANCH=none
TEST=Verify charge LED changes to white (full) on Sona synchronously
to the display percentage.
TEST=Verify charge LED changes to blinking white (low) on Sona
within 30 seconds synchronously to the display percentage.
Change-Id: I0b51911b90dc2e7fcf5c730c54d9fda1fea76aa9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Since S3 resume sometimes breaks when trying to find the wakeup vector,
it is useful to log whether it errors or not. Since it is an error,
print it as such.
Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build coreinfo with original code, run objdump and saved output. Added
modifications, build coreinfo again, run objdump again, compared objdump
outputs.
Change-Id: I1bbdc9499d257c5051fd7a86ca8b5c68bbf2e81d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29344
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we build one of the `all*` targets, build Clang first. Compiling
Clang (just for the host arch, I assume) takes more than half of the
time of the default build. When run as a separate step, we can make
use of Docker's cache if any step after Clang fails.
Change-Id: If67b458cde656f1dc6774215f6a575a48d12b797
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The choice of `gnat-6` was originally an optimization because the meta-
package `gnat` installs not only the current GNAT version but also other
unwanted (and hard to explain) dependencies. Later it was necessary
because GCC 8 couldn't compile our older crossgcc.
Now that we switched crossgcc to GCC 8.1, `gnat` should be fine.
Change-Id: Ica8a1f9d6d71a74ffc4ec76aa0cfbe4b604cde1b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29454
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current version in debian:sid is incompatible with our crossgcc
version. But it turned out that we don't use the optimization features
enabled by libisl at all: crossgcc builds with and without (a proper
version of) libisl-dev installed generate the same coreboot binaries.
Change-Id: I9f9115d8ab33cbe11aa77f16c98465e1c1dedeac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=Make the printk reachable, check with
`strings build/cbfs/fallback/romstage.elf | grep lowest`
that this patch changes "MHzas" to "MHz as".
Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build and boot grunt.
Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.
BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
with companion EC and kernel patches
Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each stage performs some basic initialization (stack, HLS etc) and then
call smp_pause to enter the single-threaded state. The main work of each
stage is executed in a single-threaded state, and the multi-threaded
state is restored by call smp_resume while booting the next stage.
Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
There are some small mistakes in these recently-added mainboards:
- board_info.txt: Lists board socket incorrectly.
- cmos.default: Loglevel was decreased some time ago.
- devicetree.cb: Spelling mistake.
- Kconfig: Mainboard name does not have a hyphen.
Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Get board id from AUXIN4 and RAM code from AUXIN3.
BUG=b:80501386
BRANCH=none
TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0.
AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1.
Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We plan to get board id and RAM code from AUXADC on Kukui. Add AUXADC
driver to support it.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I121a6a0240f9c517c0cbc07e0c18b09167849ff1
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/29061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The Sarien mainboard uses the newly added Wilco EC.
- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup
Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sarien is a new board using Intel Whiskey Lake SOC. It also uses
the newly added Wilco EC, enabled in a separate commit.
Sarien is not a true reference board, it is just one variant of
a very similar design. For that reason it is not considered the
baseboard but rather a standalone variant.
Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The function `acpi_fill_madt()` is identical among all the Lynx Point
boards and sb/intel/bd82x6x, so share a common function between them.
Earlier Intel platforms have similar implementations of this function.
The common implementation might only need minor alterations to support
them.
Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No
issues arose from this patch.
Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the file `southbridge/intel/lynxpoint/nvs.h` is included in a file
that does not already include <stdint.h>, compilation errors result.
Adding the necessary <stdint.h> inclusions fixes compilation for an
ASRock H81M-HDS.
Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.
Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.
Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.
Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.
[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
Volume 2c: Command Reference: Registers (Haswell)
https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family
Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
So, only change this setting for Haswell ULT CPUs, as suggested by the
BIOS Writer's guide.
Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS
with a Pentium G3258, the following exception is generated, causing the
system to hang.
CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
Code: 0 eflags: 00010006 cr2: 00000000
eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90
The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located
at 0x637. This MSR only exists on Haswell-ULT CPUs.
So, allow boards to use the TSC monotonic timer instead. They can do
this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig.
Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The super I/O setup needs to be done after the LPC is enabled. For
Lynx Point, configuring the super I/O in `mainboard_romstage_entry()`
is too early to get a serial console output. To remedy this, add a
function `mainboard_config_superio()` that will be called at the
appropriate time, and can be overridden by mainboard code.
Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Romstage is where DRAM comes online. Therefore, allow
raw CAR_GLOBAL object access in all cache-as-ram stages
that are not romstage. In practice, this should be a nop.
However, the explicit check for romstage is clearer.
Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For platforms utilizing CONFIG_NO_CAR_GLOBAL_MIGRATION there's
no need to automatically migrate globals. Because of this it's
possible to automatically allow for uninitialized global variables
which reside in the .bss section without needing to decorate those
objects with CAR_GLOBAL.
Change-Id: Icae806fecd936ed2ebf0c13d30ffa07c77a95150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where
possible), the register being read was changed accidentally from
HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5)
This doesn't return the correct value, and causes Grunt to reboot.
BUG=b:118721473
TEST=Boot grunt
Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The function domain_read_resources() didn't have any code to actually
reserve any resources - it was just creating an empty resource entry.
I looked at fixing it to actually reserve the space, but the values in
the registers at the point when this runs aren't the final values that
we want to reserve anyway, they're temp values with a range much larger
than we want to reserve.
I next looked at moving the amd_initcpuio() function earlier so that we
could get the correct values for the registers, but even that doesn't
give us what we really want.
Ultimately removing this whole function seems to be the right thing.
BUG=None
TEST=Verify that the only resource that changes is the empty resource:
PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080
Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The speakers start up muted, and the EC must be told by the BIOS
to unmute it. This helps prevent popping noises on boot/resume.
Change-Id: I693f1d01e46e19362ef8fd0d5b3f4930967b5a12
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.
The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.
Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add methods to handle ACPI EC events at runtime. Currently only
some common events are handled like lid switch and battery info,
and the event status is printed for debug on other events.
Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the expected objects (_BST, _BIF, _BIX) for reading battery
information and status from the embedded controller, and the
expected objects for reporting AC power status.
The battery was tested by booting with a battery attached and checking
that it is present in /sys/class/power_supply/BAT0 and that the values
are consistent and within expected ranges.
The AC device was tested by checking the AC status in sysfs when AC
is inserted or removed while the system is running.
Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the base ACPI support for the Wilco embedded controller, using
ASL 2.0 syntax throughout.
This includes the EC device and its resources, as well as the layout
for the EC RAM and the functions needed to read and write to the EC RAM.
The EC RAM address space is typically read/write, and so the ACPI EC
device expects that a defined Field can be read and/or written. With
this EC the read and write address spaces are different. For example,
a read from address zero will return data that is unrelated to what a
write to address zero expects.
This makes using a typical OperationRegion to describe the EC RAM
address space somewhat impracticle, since field definitions would
overlap. Instead, methods are provided for reading and writing to an
EC RAM offset, and the EC RAM layout is defined as a Package that
describes offset+mask for read or write fields within the EC RAM.
Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function for use in bootblock stage that performs early init
of the EC, in particular setting it up for UART passthrough so a
legacy serial port can be used by the host.
This needs to be called by the mainboard that intends to use it
in bootblock in order for the UART to be available in later stages.
Some of the PNP style programming may look odd, but it is following
the EC specification which is not entirely standard. This code has
been tested on a board with this EC and it is functional.
Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC handlers for specific SMM actions:
- on entry to sleep state tell the EC to save state and to prepare for
the host to enter sleep
- on ACPI enable/disable send command to the EC
- add a function to print SMI reasons when eSPI SMI is received
These need to be called by the mainboard handlers which will be done
when a board is added that uses this EC.
Change-Id: Ibabdc1462e0a8df405f9520244b83684e2ccf2f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC expects to receive updates about the BIOS boot progress. This is
used for the EC logging to track system boot completeness. If the EC is
not informed about BIOS progress it will turn the system off 30 seconds
after the boot starts.
Change-Id: I693c3930117db2b69a119aee0380d6f303c4881c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a chip_operations structure for Wilco EC and hook it into the device
tree so it can be initialized at boot.
Reserve the device resources specified in Kconfig, which will also
create the device IO windows if they have not been created in bootblock.
If the IO windows already exist (becauase they were specified in the
mainboard devicetree.cb) then this will find the existing entry instead.
During device init stage prepare the keyboard for use, which is required
for it to be functional in firmware and OS with this EC. Also send a
command to the EC telling it to pass the power button through to the
host for processing.
Change-Id: I0adb01cf394f939f4a28aeb47fe4d0bcda5957d9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC mailbox commands that are related to the power and state of the
system. These commands include:
- read the power status registers from the EC
- read & clear the power status registers
- helper function to read the current lid state
- tell the EC why the host is about to power off
- tell the EC that the host is about to enter a sleep state
Change-Id: Iaa7051b4006e3c1687933e0384d962516220621f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add basic supported mailbox commands for this embedded contrlller,
and define some command functions to retrieve and print information
about the EC.
Change-Id: Ibcef7d58e1852fdb2e52b97acd4b51a26dd8cd77
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add helper functions that make it more convenient to send and receive
the most common types of commands to the Wilco embedded controller.
Change-Id: I9cee1a3b2f9d507f6ecdfae9f4a34ba59056cb91
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29114
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Google "Wilco" Embedded Controller is a new embedded controller that
will be used in some future devices. The mailbox interface is simliar
to the existing Chromium EC protocol version 3, but not close enough
that it was convenient to re-use the full Chrome EC driver.
This commit adds the basic mailbox interface for ramstage which will be
used by future commits to send varous mailbox commands during the boot
process. The IO base addresses for the mailbox interface are defined in
Kconfig so they can be changed by the mainboard if needed.
Change-Id: I8520dadfa982c9d14357cf2aa644e255cef425c2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new function which can hash a given region device and extend a PCR
in the TPM with the result. The needed SHA algorithms are included from
3rdparty/vboot and thus not duplicated in the coreboot tree.
For now VB2_LIB is not usable in postcar stage. Follow-up commits will
add the ability to use the lib in postcar as well. Once this feature is
ready, the library will be included in postcar stage to make this
function available in every stage.
Change-Id: I126cc3500fd039d63743db78002a04d201ab18aa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Instead of forcing the IOMMU to be enabled, change it to only be enabled
if the device is enabled in devicetree.
BUG=b:118612241
TEST=Verify that IOMMU is disabled.
Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Unfortunately Stoney has an issue where enabling the IOMMU causes
a 10%-50% decrease in the integrated graphics performance. It is
also disabled by default on other stoney platforms.
BUG=b:118612241
TEST=Verify that IOMMU is disabled.
Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29342
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl3 mainboard will follow in separate commits.
Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
1. Add dot/period to the end of sentences
2. Remove blank line at the end of the file
3. Break lines after 75 characters
4. Use RISC-V spelling
5. Add comma for clarity
Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28654
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just disable the timer interrupt and notify supervisor.
To receive another timer interrupt just set timecmp and
enable machine mode timer interrupt again.
TEST=Run linux on sifive unleashed
Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/29340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that bounce buffers are gone, and we can elide the selfload checking
code at build time, it is safe to add selfboot to the romstage.
Make it so.
This required a few other tweaks to rules.h and selfboot.c
to make it buildon ARM.
Change-Id: Ib6540921ad7cd7d58bfeab881d3978325b303cc2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A stack overrun has been observed on AMD64 CPUs during the SMM module
relocation process. Change the assumed required size from equaling the
save structure's size to a Kconfig symbol.
A value of 0x400 doubles the size used by AMD64 systems and maintains
the size used by EM64T.
BUG=b:118420852
TEST=S3 on Grunt and verify 0x2f000-0x30000 uncorrupted
Change-Id: Ib1d590ee4afb06ca649afd6ad253cdfd969ae777
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification. GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like we must do it in the same way as in l520, t420, t420s,
t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be
handled differently.
Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29031
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.
Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
This commit follows up on commit 7dee9745 with Change-Id
I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio
map instead of including a header").
Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
IGD display handling was rewritten with commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). These
comments were removed as well (with some accidentally left behind).
Let's remove them and those who were introduced later with new ports.
Change-Id: I8d3e12d0c3b03b0de38e65f36b94ed706fbf893c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These ifdefs are the remains from the following commits:
* fa1d688a with Change-Id I9909a5b2bdb4b59219db6304fa4332802fe0301c
("sandy/ivy native: dedup romstage.c main()")
* 7dee9745 with Change-Id I88b5ef8e12ac606751952a493f626e1b146e98f7
("mb/lenovo/x201: Link gpio map instead of including a header")
Change-Id: If83189688151f531a05780a87db3409cbacfbeff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Clone entirely from mainboard/intel/cannonlake_rvp
commit id: af89f49b83
List of changes on top off initial cannonlake_rvp clone
1. Rename "Cannonlake" with "Icelake".
2. Replace "cannonlake_rvp" with "icelake_rvp".
3. Rename "cnl" with "icl".
4. Remove unwanted SPD file, will add correct SPD with mainboard
patches.
5. Remove NHLT related implementation.
6. Remove FSP configs, will add once FSP headers are available.
7. Removed smihandler.c, will add later if needed.
Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29164
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
icelake FSP is still under development and hence the FSP header files
and binaries are not available on github. Meanwhile add basic header
files required to compile the SoC and mainboard with FSP2.0.
BUG=None
BRANCH=None
TEST=Build for icelake_rvp board successfull.
Change-Id: I9ab8f180b572ec553e7531f7483d091f6897c462
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/29163
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clone entirely from Cannonlake
commit id: 3487095304
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove unused members in emi_mpu_regs and sdram_params. Change
mpu_ctrl_d to array so the offset (0x804) for D1 is corrected.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/29251
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.
BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.
Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The selfboot function was changed at some point to take a parameter
which meant "check the allocated descriptors to see if they target
regions of real memory."
The region check had to be buried deep in the last step of loading since
that is where those descriptors were created and used.
An issue with the use of the parameter was that it was not possible
for compilers to easily divine whether the check code was used,
and it was hence possible for the code, and its dependencies, to be
compiled in even if never used (which caused problems for the
rampayload code).
Now that bounce buffers are gone, we can hoist the check code
to the outermost level. Further, by creating a selfload_check
and selfload function, we can make it easy for compilers
to discard unused code: if selfload_check is never called, all
the code it uses can be discarded too.
Change-Id: Id5b3f450fd18480d54ffb6e395429fba71edcd77
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables override device tree for Fizz to allow variants to
provide their own overrides and also moves I2C5 realtek node to
fizz/overridetree.cb since it doesn't apply to some variants being
added for Fizz.
Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Accurately reflect the intention of the syslimit value returned
from AmdInitPost(). Assume FFs for the non-present bits.
BUG=b:118178425
TEST=Boot Grunt and verify reported value = TOM2-1.
Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Liara auto restart issue is caused by memory access error and consequent
kernel panic. To solve this issue, revert the CL:1243666 (Disable
NbP-state on Liara) and use 2T mode instead.
BUG=b:116082728
TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run
memtester passed 10 cycle.
Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.
The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.
Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27873
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DRAM init sequence is simply setting some values on register
for all DRAM modules, no logic involved;
so we can replace it by an array to configure easily.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Iacd3ce909ba7a0bdf699c5bfcb2b97f383d7bb6f
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Having cbmem floating between two ram regions is a bad idea and some
payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the
region between tom and cbmem as uma.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. Update PSV values for cpu and sensers.
2. Change PL1 min value from 3w to 4.5w.
3. Change TSR2 TRT source from charger to CPU.
Refer to 112448519#comment31.
BUG=b:112448519
TEST=Build coreboot for Octopus board
Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change uses CRFP ACPI name for FP device since user space
utilities expect this name for triggering different actions.
BUG=b:112974410
BRANCH=nocturne
Change-Id: I63309227c916b43917e529c223cf738fc3baa209
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29231
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on.
And add touchscreen device "PNP0C50" to I2C0.
According to touchscreen spec, device power on initialization takes
105 ms, so set "generic.enable_delay_ms" to 120.
We found there is i2c error log pop up when we set delay
time to be 110ms or 105ms. If we set delay time to be
120ms. System will not pop up i2c error log.
BUG=b:115944726
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change TSS layer tlcl_send_startup() to expose TPM_RC_INITIALIZE,
which gets mapped to TPM_E_INVALID_POSTINIT. The return value
is exposed to TSPI layer tpm_setup(), and dealt with as follows:
- Regular startup: TPM_E_INVALID_POSTINIT should count as failure.
- S3 resume: TPM_E_INVALID_POSTINIT can be assumed to mean that
TPM maintains power during S3, and is already initialized.
Also, correct an error where |response| could be erroneously accessed
when it is set to NULL.
BUG=b:114018226
TEST=compile coreboot
Change-Id: Ib0c3750386ae04279401c1dc318c5019d39f5ecf
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of
part_num_store that holds the number of DRAM part. It ensures that
host advertises the supported size to read part number from the EC.
BUG=b:115697578
Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Before entering the OS, the AP relies on the smi handler to shutdown the
system when the lid closes. Without the smi_events setting, the AP will
not receive the smi handler. As a result, the AP won't shutdown and will
always keep in S0.
This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983
and this patch adds the smi_events back to support the smi handler for
the lid close.
BRANCH=master
BUG=b:115572596
TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown
Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/29191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This change uses the newly added macros for configuring the same GPI
pad(GPIO_135) for IRQ (normal interrupt operations) and
wake (interrupt for waking from S3/S0ix) for the trackpad device. The
other pad GPIO_142 is now configured as not connected.
BUG=b:117553222
TEST=Verified that yorp and bobba wake from S3 and S0ix using
trackpad.
Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds new macros to GPIO common library helpers to allow
a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds
a helper macro to configure a pad for IRQ and wake.
Above macros are guarded using a newly added Kconfig option
SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only
by SoCs that have been validated to allow dual route of
GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that
have been validated to work with dual-routing of GPIs for IRQ and
wake.
BUG=b:117553222
Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates various PAD_CFG_GPI* macros to configure Tx as
Disabled in IO Standby state. This is done to ensure that the Tx
setting is same in IO Standby state as it was in active state i.e. Tx
disabled.
BUG=b:17553222
Change-Id: If462aee3884cc61a519fb358b84867c695ace251
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change does the following:
1. Adds a helper macro ACPI_IRQ_CFG that can be used by all other
ACPI_IRQ* macros to initialize acpi_irq structure.
2. Provides ACPI_IRQ_WAKE* versions to allow board to define an irq as
wake capable.
BUG=b:117553222
Change-Id: Ic53c6019527bbd270806897247f547178cd1ad3c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
recommonmark doesn't know about inline code, while all other software generating
documentation is able to handle it.
Add support for inline code by adding a wrapper class around the recommonmark
parser that converts code to docutils literal blocks.
Fixes invisible inline code in current documentation.
Change-Id: I0269d15a685ed0c0241be8c8acfade0e58363845
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.
Bug=b:116082248
Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a cosmetic one. It just removes some board names from comments
since these functions sometimes are very similar, so no need to add
extra difference between them.
Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We didn't have a hard_reset() implementation for these boards. So
select the board_reset() stub for them.
Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29170
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
And here comes the mess...
This just renames do_hard_reset() to do_board_reset() and keeps current
behaviour. As these are never called from chipset or board code but only
from common code, it's likely that their implementations are untested
and not what we actually want. Also note, that sometimes implementations
for rom- and ramstage differ considerably.
Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29058
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add an `amdblocks` internal API and rename
soft_reset() => warm_reset()
hard_reset() => cold_reset()
as these terms are commonly used in the surrounding code.
On Stoney Ridge, make board_reset() call cold_reset() to keep
current behaviour of common code calling hard_reset(). But add
a TODO if this is intended.
Note: Stoney Ridge is using CF9 for the actual reset but the
configuration for a cold reset doesn't use the usual full reset
bit but some other mechanism.
Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.
Currently only hard_reset() is used by common code. We replace these
calls and provide a fall-back to the current hard_reset() implemen-
tation. The fall-back will be removed along with hard_reset() after the
transition of all boards.
Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change udpates FMAP to wrap MRC training data in RW_PRESERVE
section so that we don't lose the data when performing full firmware
updates on octopus.
BUG=b:117882029
TEST=Verified that chromeos-firmwareupdate doing full firmware update
preserves training data on octopus.
Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Looks like we've got a race condition between commit ce8763fb with
Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d ("mb/lowrisc: Remove
the Nexys4DDR port") and commit 2e38dbe5 with Change-Id
I5524732f6eb3841e43afd176644119b03b5e5e27 ("riscv: update mtime
initialization"). Let's fix it.
Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29165
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers
New boards would then add themselves under their board name within
"variants" directory.
This is purely an organizational change.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514
Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I didn't change the offsets of all the other regions because I didn't
want to cause all dogfood devices to lose their corp enrollment.
BUG=b:117797131, b:117798830
BRANCH=none
TEST=Ran autotest and made sure the tests were skipped
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/29171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
this patch adds following changes
- Select config to initialize codecs in common HDA driver.
- Add audio verb table for coffee lake RVP11 & RVP8.
BUG: None
TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio
playback and record functionality over anolog audio jack & HDMI display.
Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch selects common HDA driver and adds audio controller device id
to enable audio on coffee lake platforms.
BUG= None
TEST= boot to yocto linux and windows os on CFL RVP11 & RVP8, verified audio
functionalities.
Change-Id: I4a60a4d7d8babcd0c14664a304ca81d47c668a6c
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29145
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.
Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds.
Use frequency as a proxy to determine SKU. The E3805, E3815,
E3825, and E3826 are all <= 1460MHz while the E3827 and E3845
are 1750MHz and 1910MHz, respectively. This will allow to boot
quad-core Minnowboard Turbot especially.
Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27989
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to using the common MEC interface instead of the
Chrome EC specific code.
Tested on a Chell chromebook that has a MEC based Chrome EC
to ensure that the EC interface is still functional.
Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to re-use the MEC interface code in the Chrome EC driver
move it to a common directory within the ec/google directory.
The Chrome EC driver itself is changed to use this interface in the
next commit, and future commits will introduce a new EC that also
uses this interface.
Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CB:26053 changed coreboot's default loglevel from SPEW to DEBUG. This
may be the most reasonable choice for most users that are mostly
interested in the UART console. However, on Chrome OS devices the UART
is disabled for production configurations anyway, and instead they rely
heavily on the CBMEM console for remote debugging and bug reports. For
these kinds of cases more info is almost always better, and you can't
easily reproduce a remotely filed bug if you notice that you need some
info that is only provided by BIOS_SPEW. On the other hand, the cost of
logging extra info to the CBMEM console is pretty negligible.
Therefore, let's bump the loglevel for CONFIG_CHROMEOS in particular
back up to the maximum. (Unfortunately, it seems that you can't 'select'
a choice option from another option, so this has to go in the
console/Kconfig file.)
Change-Id: I50724e3f7f8f57fdbc5846f21babc71798b21b65
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Register 0x40 of miscellaneous MMIO is double defined, with different names,
which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only
bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO
registers.
BUG=b:117818431
TEST=Build grunt.
Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the
definitions within MMIO definitions, as wideio is not related to MMIO.
BUG=b:117814228
TEST=Build grunt.
Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is
the same as SOC_PM_DEV. Remove the definition, and replace its use in
tsc_freq.c with SOC_PM_DEV.
BUG=b:117754424
TEST=Build and boot grunt.
Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIO control a mux base addresses are defined within MMIO definitions
and again bellow as GPIO specific base addresses. Eliminate those outside
MMIO bases. Rename them to something indicating that they are both MMIO
and related to GPIO.
BUG=b:117754420
TEST=Build grunt.
Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29156
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no indication that they are accessed through D0F0. Add a D0F0 header
and move IOAPIC definitions under it. The registers defined to be accessed
through index/data pair should be indented relative to the index/data pair
definition.
BUG=b:117754786
TEST=Build grunt.
Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29155
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Comparison should place the constant on the right side. Southbridge.c has 6
instances where the opposite happens. Reverse the order of six comparisons
to eliminate checkpatch warnings:
WARNING: Comparisons should place the constant on the right side of the test
BUG=b:117656929
TEST=Build grunt.
Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29153
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.
Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.
Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds two new post codes to indicate start and end of
memory param preparation in callbacks to SoC/mainboard code:
1. 0x34: Start of memory preparation
2. 0x36: End of memory preparation
These post codes are already used in coreboot. This change just
ensures that the codes are defined in post_codes.h for easy lookup.
These post codes are useful if SoC/mainboard decides to do a reset of
the platform before returning back to memory initialization.
Change-Id: I065518caedb7943d960a8a5c8708823b8eb3246d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead. Also removed FDD from l520
romstage (original value, 0x3c0c, means that FDD_LPC_EN was also
enabled).
Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets
disabled & vice versa.
FSP default config for EnableTcoTimer is disabled, this caused ACPI PM
timer & TCO to be disabled by FSP even when config PmTimerDisable = 0.
Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config
PmTimerDisable.
BUG=None
TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused
reboot after running shell command: cat >> /dev/watchdog0
Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/29108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add new mainboard variant coffee lake RVP8, which is CRB for
coffee lake-s processor, support U-DIMM DDR4 memory module.
- Modify cfl_h devicetree to enable IO devices, configure PCIE root
port clock source, usb over current pin as per board schematics.
- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.
- Add GPIO table as per board schematics.
BUG= None
TEST= Build and flash, confirm boot into yocoto & windows OS on both
cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,
display, power functionalities.
Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29066
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
L520 and T420 should also use it - platforms are very similar to t420s
and t530. Z61t is based on T60/X60, X131e is based on X230 so commit
with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be
applied as well.
All four platforms are using ec/lenovo/h8 embedded controller.
Change-Id: Ib177f024871e82979dd430da86f1551aef14d446
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
BUG=b:117139495
TEST=Check nxpc EC power to see power improvement
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/29007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU
microcode length and base address in CBFS to FSPT binary as init parameters.
Add new config FSP_T_XIP in Kconfig, which is selected by platform config.
If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS
so that it can be executed in place.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.
Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update CPU passive temperature threshold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
BUG=b:116400298
BRANCH=None
TEST=Manual performance testing on nocturne.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29044
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This define is no longer used by anyone. It was removed everywhere else
with commit with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757.
It seems that these two files were simply mislooked. So let's remove it.
Change-Id: Ifbb62441e16e97c0cae0713968844e296619a880
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard is quite similar to the p5qc. The main differences being a second
PEG slot, the IDE slot and being DDR2 only.
The following was tested:
- both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the
black slot)
- USB
- Ethernet NIC
- PS2 Keyboard
- COM1
- S3 resume
Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/29102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A shortcoming of this driver is that if multiple devices with the same PCI ID
are present and don't have an eeprom, they would all get the same macadress set.
The r8168 driver deals with such cases so it should be easy to implement if
needed.
Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS
support for ATA. It works fine in Linux afterwards.
Working:
- SATA on southbridge port
- SATA on marvel IDE controller ports (only in Linux)
- USB
- COM1
- PS2 Keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCI port
- NIC (needs a driver to set macaddress)
- S3 resume
Not working:
- SeaBIOS with ATA support (long timeout marvel controller so disabled)
- DDR3 fails because the proper clock signal does not get enabled. Even when
fixing this it fails later or during memtest, so it should be considered
unsupported for now
Untested:
- PCIe x1 ports (expected to work)
- sound (expected to work)
TODO:
add documentation
Change-Id: I4a81940707566776bd048904ca1387fea741fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
More platforms are not able to hibernate under certain circumstances,
such as when AC is plugged. This original path was conservatively put in
to prevent potential damage when cr50-update-caused asynchronous resets
occur. Julius' compelling argument that async resets from recovery mode
requests should have enough coverage of the design over the course of
project development. Remove the hibernate path and assume all is well
going forward.
Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29076
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While during the read training itself only the settings for rank 0 are used for
all ranks, the controller does use the separate settings for each rank later on.
It is unknown which register is responsible for this.
The signals are probably not generated separately and therefore need to have the
same settings for all ranks. Therefore program the results for all ranks instead
of for all populated ranks.
TESTED: Fixes DG43GT not booting with only the second DIMM slot of a channel
populated.
Change-Id: I7965a068ef4779847e62e966154764370c91302a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make #define definitions for PMxEF and replace the hardcoded values.
Note that this doesn't change the current functionality of the source.
The existing code has been propogated from the sb//hudson port, which
seems to attempt to enable 100% of all OHCI and EHCI controllers that
may be present in the system.
Change-Id: I6018b0062730de19e3283a010144dfedc2b11423
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29075
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove nonpreset controllers from the PCI device identifier function
(ignoring any CONFIG_USBDEBUG_HCD_INDEX). The extra devices appear
to be holdovers from the original sb/hudson source.
TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and
verify proper BDF is returned in romstage and ramstage.
Change-Id: I2e819d5e998922ad427c4a094c29a590f249a0d3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Delete an unmatched opening parenthesis in the definition for the EHCI
hub config register definition. This wasn't causing a problem unless
EHCI debug was enabled.
TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and
verify successful build
Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29073
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using
Intel's FSP repo (that we mirror) to build a complete BIOS ifd region
with a simple coreboot build, automatically drawing in headers and
binaries.
This commit covers Apollolake, Coffeelake, Skylake, and Kabylake.
Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's
also supports Skylake.
Another candidate (given 3rdparty/fsp's content) is Denverton NS, but
it requires changes to coreboot's FSP bindings to become compatible.
Cannonlake, Whiskeylake require an FSP release.
Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28593
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The arm32 GDB architecture code contains a little hack that allows it to
(sort of) correctly deal with a reentrant exception triggered from
within the GDB stub. The main logic for this isn't really arm32 specific
and could be useful for other architectures as well, so factor it out
into a separate function.
Change-Id: I3c6db8cecf1e86bba23de6fd2ac9fdf0cf69d3c6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch reworks the arm64 exception handling to be more similar to
how it works on arm32. This includes a bunch of features like actually
saving and restoring more exception state in the exception_state
structure and supporting the same sort of partial reentrancy that is
useful for GDB. Since there's no instruction to directly load into or
store out of SP on arm64, we can't do quite the same thing where we use
that to read an exception_state_ptr variable right after exception entry
when no other register is available. But we can do something very
similar by (ab-)using the "high" stack pointer (SP_EL2) as a pointer to
the exception_state struct and providing a function to change it.
Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.
This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).
Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.
Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Delete artifacts remaining from the original "hudson" and "yangtze"
controller hub designs.
Husdon devices had a configurable AcpiMmio base address, and a selection
for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO.
Remove the flash control register definitions for the old generations.
The manual reset register appears to not function as hudson.
PMIO_DEBUG is named differently now, and not used, so remove its
definition too.
Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This change adds a variant callback to read google_chromeec_event_info
from variant at runtime to allow override of any events based on
factors like board id.
This callback is used in ramstage and smm to get
google_chromeec_event_info structure for performing various actions
like setting masks and logging wake events from EC.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds ec_boardid.c to smm stage, which is required to allow
mainboards to query the ec to get board version in this
stage.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: Iccbba96ebb94a12745a62cbfe3496f9e6f921e3d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
There doesn't seem to be a reason why we would want to protect certain
chromeec functions with __SMM__ guard. So, this change gets rid of
it. If the functions remain unused, then they would be removed during
linking.
Change-Id: I8196406074b01fe8ea15173c55d45bb86384be1b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
stapm_time passed to smu via agesa is in msec. With earlier value
smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus
causing issue in S3, and audio in PsppBalanceLow state.
BUG=b:117569918, b:117252463
TEST=
1.) audio works with PsppBalanceLow
2.) S3 cycles
Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A colon usually indicates that something related follows. But in
Documentation/releases/index.md, nothing followed. Fix this by swapping
two lines.
Change-Id: I3e2750c208a2b725145b94615f64381ac763f0dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).
BUG=b:117284700
TEST=Verified that no spurious wakes are observed on nocturne.
Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Need to tune I2C bus 0 clock frequency under the 400KHz
since this bus attached the Stylus EMR pen and need meet the spec.
Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz
Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dimm_info and memory_info structs are used in devices that
don't strictly use DIMMs. Those platforms have the DRAM soldered
down so there's no DIMM part number that encapsulates the DRAMs
used in the DIMM. The full part number is desired to be exposed in
the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33
to accommodate longer part numbers
'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that
are desired to be maintained.
BUG=b:115697578
Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the new I2C slave reset function and reset all slaves connected to all
4 I2C. Do this in all boards.
BUG=b:114479395
TEST=Added debug code. Build and boot grunt. Examined output, confirmed
GPIO pins changing as required. Removed debug code.
Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.
BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.
Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up Kconfig file in order to support variants for fizz. Add
BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants
to use the common baseboard configs.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.
Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Legacy PME are enabled by default in FSP-S UPD. This policy sets
PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt
generation when RSTS.PS state has changed (either due to 0->1 transition
or due to this bit being set with RSTS.PS already set). Due to this
interrupt generation, system wakes from sleep immediately it enters.
This patch overrides root port legacy pme upd policy from coreboot to
ensure no false SCI is triggerd when system is in S3/S0ix state.
BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase
without any failure.
Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.
The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.
Datasheets used:
- SCH311X: DS00001872A
- SCH5127: DS00002081A
Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Setting default PSPP setting to BalancedLow was causing audio
playback issue in most of the units. With BalancedLow either there
was no sound or noise on playback.
Switching to BalancedHigh as default option.
BUG=b:116553085, b:112020107
TEST=Test playback and hear proper audio.
Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28967
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.
BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.
Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled. This change disables WAKE#.
BUG=b:117284700
TEST=none
Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Convert PNG to JPG and reduce image quality.
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.
Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Add Makefile dependency to source file
* Add argument support
* Add help support
* Print usage on wrong arguments
* Add support for parsing VBT binary file
* Add support for parsing PCI Option ROM
* Add support for writing VBT binary file
* Add support for patching PCI Option ROM
* Keep support for accessing legacy VGA area Option ROM
* Keep support for dumping VBT contents to stdout
Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed.
The required arguments have been changed:
./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename]
SOURCECMD set the VBT source. Supported:
inlegacy : Legacy BIOS area at phys. memory 0xc0000
invbt : Read raw Intel VBT file
inoprom : Read VBT from Intel Option ROM file
DESTCMD set the VBT destination. Supported:
outdump : Print VBT in human readable form
outvbt : Write raw Intel VBT file
patchoprom: Patch existing Intel Option ROM
Any combination of SOURCECMD and DESTCMD is possible.
Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
RISC-V is not a project of the University of California, Berkeley,
anymore; it stands on its own feet now.
Remove the "UCB" component from the RISC-V mainboards in the "emulation"
directory, and don't set MAINBOARD_VENDOR to UCB, either.
Change-Id: I301d9d0091a714e62375052e5af06a9197876688
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support in generic device driver to add properties to
DSD table. This driver can be used by all generic devices that do not
need any special handling other than simply adding device properties
to be used by OS.
BUG=b:112888584
Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.
BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.
Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:
1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.
2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.
3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.
4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.
Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.
BUG=b:112888584
Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since `#if 1` is rather useless, and the code inside it is just several
`printk(BIOS_SPEW)`, using `if (console_log_level(BIOS_SPEW))` instead
seems more reasonable.
Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber
test, but the root cause is unclear.
Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal
reset issue, so we would apply it until find root cause of this issue.
BUG=b:117130599
BRANCH=poppy
TEST=Built and passed on reliability test with modified coreboot
Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the ACPI controls for power sequencing the touchscreen.
The initial setting is to keep the touchscreen powered off and in
reset. When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.
BUG=b:110286344
TEST=verified touchscreen is functional in chromeos
Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the step of setting the SATA controller to S0 as the system is
entering S3. This had been duplicated from AMD's FchCarrizo.asl file,
but upon closer inspection, the conditions for this step to run cannot
be met. This does not affect Grunt's behavior, as the SATA controller
is disabled.
TEST=Suspend and resume Grunt
BUG=b:77602074
Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Setting the stapm parameters is causing S3 resume failures and
performance issues. Removing these settings until more testing is
done and the issues are solved.
BUG=b:117252463, b:116870267
TEST=boot grunt
Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.
Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, an entry being removed is cleared only if the next entry
is also null or deleted.
This patch ensures the entry being removed is cleared regardless of
the next entry type.
BUG=chromium:889716
BRANCH=none
TEST=Run cbfstool bios.bin remove -n ecrw.
Verify bios.bin has 0xFF in the space of the removed entry.
TEST=Run cbfstool bios.bin remove -n fallback/payload (located at the end).
Verify fallback/payload is removed.
TEST=Run sign_official_build.sh on recovery_image.bin. Extract
firmware contents from chromeos-firmwareupdate in the resigned image.
Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A
extracted from bios.bin. See the bug for details.
Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In CBFS layout:
oem.bin size is 10 bytes.
In cbfs_boot_load_file, buffer size will need to be larger
than decompressed_size, otherwise CBFS data can not be
extracted into buffer.
Then we need to check buffer whether it's empty string separately.
BUG=b:79874904
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I4f1bbb690ecca515ac920f5058ee19b5bfd8fa5e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This will make enabling the APIC safer by ignoring unknown interrupts
and not halting the system. Once all interrupt sources have been found
and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired.
BUG=b:116777191
TEST=Booted grunt, halted the kernel, and pushed the power button while
in S5. Verified that depthcharge logged the unknown exception.
APIC Init Started
APIC Configured
Ignoring interrupt vector 39
Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We should have a spurious interrupt vector just incase we get one. The
handler doesn't need to do anything.
BUG=b:116777191
TEST=Booted depthcharge on grunt and inspected the register. I can't
generate a spurious interrupt, so I can't validate that the handler gets
called.
Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Only set end of interrupt (EOI) when the APIC In-Service vector matches
the interrupt vector. This makes it so we don't EOI a non APIC
interrupt.
BUG=b:116777191
TEST=Booted grunt with APIC enabled and verified depthcharge still
works.
Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It seems to be the only user of the USB debug driver. So having to
enable it separately seems wrong.
It still depends on the selection of the EHCI debug driver.
Change-Id: I5f5f38a912423d9b8f1e71ae875b6a14fdee651c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move the FSP param initialization function to a separate file,
as being done on the SoC side and remove the empty romstage.c file.
Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move funtions callbacks used to override FSP upd values to
separate files. This serves as a base change for SoCs for which
FSP is still under development, and hence the FSP header files
are not available yet and in turn the UPDs cannot be referred.
These newer SoCs will implement empty callbacks. The code will
compile with basic header files which only include the architectural
FSP structures.
This allows plugging in these separate files for compilation in an
environment where FSP header files are available.
The fact is, FSP header files are not released externally until PRQ.
However the teams at intel and some partners have access to the development
version of these files. This code refactor helps to continue development
on the pre-PRQ silicons and submit related code to coreboot.org.
BUG=None
BRANCH=None
TEST=Build for cnlrvp
Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently src/mainboard/*/romstage.c is mandatory for compiling,
this makes having the file present even though there is nothing to
initialize in romstage on the mainboard side. Eliminate the need to
have empty romstage.c files using the wildcard function.
BUG=None
BRANCH=None
TEST= build cannonlake_rvp after removing the romstage.c file.
Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
GPP_C19 is not being set as the code is incorrectly setting
GPP_C16 instead, causing SAR sensor not to work, so this change
sets GPP_C19 to NF1.
GPP_E3 is not being initialized in the code. Initialize GPP_E3
to a no connect as documented in the board schematic.
BUG=b:117124878
TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and
verify that i2c transactions work for the left SAR sensor.
Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28867
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the reset delay for the touchscreen to 10 ms.
BUG=b:116857433
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, log in and execute the following two commands:
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind
and verify the bind command does not echo back a
"-bash: echo: write error: No such device" error.
Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28803
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers
on boot. print_num_status_bits() was already using BIOS_DEBUG.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28885
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the function vboot_platform_prepare_reboot() which is normally
a weak function.
The SlpTyp field of the PM1 register is not reset to its default value
when the APU restarts. This change prevents a failing condition if
vboot decides to reset the system instead of allowing an S3 resume to
continue.
TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead
BUG=b:117089826
Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28877
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS"
so that the audio topology file can be loaded properly by the
operating system.
BUG=b:112945714
BRANCH=master
TEST=There is no error message like "failed to load topology firmware" in
kernel v4.4 log.
Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so
don't use them when running the clang static analyzer. On the other
hand, __riscv and __riscv_xlen need to be defined in order to select
some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen
selects the floating-point paths in src/arch/riscv/misaligned.c.
-mabi is moved with -march for consistency.
A complete list of preprocessor definitions on RISC-V can be found at
https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
With this commit, scan-build produces a useful result on RISC-V.
Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some boards are adding a second pin used for synchronization between
the EC and AP. This is a direct connection between the EC and the SOC
that is intended to provide a lower latency interrupt signal for
sensors on the EC.
Currently the runtime EC interrupts assert an SCI before eventually
resulting in a Notify() on the MKBP device that the sensor driver users.
These extra layers add processing time and require additional EC
communication to determine the event source.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to enable the OS SPI driver to use the software interface of
this controller the OPCODE menu has to be set up properly before
locking the controller. This is done on baseboard level so that all
variants will get this done as well.
Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This heading should not be a top-level heading, because it's not at the
top of the file.
Also remove the trailing colon, because it's unnecessary in a heading.
Change-Id: I0685bb8734ad899c29618d24c0497e4fb8c0d01c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch ensures I2C controllers are out of reset without any
assumptions.
BUG=b:116191230
BRANCH=none
TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT
at reset (by reading Bit 0-1 as 3)
Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FCH ASL is now capable of controlling the D-states of most AOAC
devices, as well as properly reinitializing the xHCI firmware on a
resume. Call the FPTS and FWAK methods.
BUG=b:77602074
TEST=On Grunt, go to S3 and wake with a USB keyboard
Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28773
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add methods, and call them, for transitioning EHCI and xHCI to D0 or
D3cold. Add device objects necessary for waking the system via USB.
In order for USB to wake the system, it must be in the D3cold state.
Then on resume, its firmware must be reloaded.
This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI
package), and has been modified to fit the coreboot ASL names. In
addition, AMD's methodology is to generate a SW SMI for saving/restoring
certain settings. This has been ported into U3D0 and U3D3, as the
necessary registers are now publicly documented.
BUG=b:77602074
Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28772
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package)
that can put AOAC devices into D0 or D3cold. The argument numbers
coincide with the AOAC register offsets for the various devices.
SATA, USB, and SD require additional device configuration. Add a
placeholder and mark as todo.
BUG=b:77602074
Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28769
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Indicate the devices that are enabled. This is somewhat rudimentary, but
could be improved in a later patch (e.g. get settings from devicetree).
Calculate values that may be used for reinitializing the xHCI firmware.
Add the EHCI BAR's current base address to gnvs.
BUG=b:77602074
Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28767
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A later patch will rely on two USB settings from the BIOS. Add these
to the global_gnvs_t structure.
The first is a data that will be used to locate the xHCI firmware for
reloading after a resume. Although the existing calculations will be
somewhat simple, keeping this on the coreboot side will help in the
event multiple FWs are eventually in the build.
The second item is a usable EHCI base address that may be programmed
during S3 suspend and resume. At the time the PTS and WAK code runs,
the BAR will be clear.
BUG=b:77602074
Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and
IA32_MC0_CTL is at 0x400.
So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at
0x400 by IA32_MC0_CTL.
Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In order to minimize Electromagnetic Interference (EMI) on the LVDS
interface driven by PTN3460, clock spreading must be activated for
mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal
frequency.
Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28761
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add basic flashing tutorial
** Describe internal and external flashing
** Describe flash supply diode protection
** Gives general advices on flashing
** Describe how to use flashrom --ifd
* Describe basic flashing on Lenovo T4xx devices
** Describe how to disassemble and access the flash IC on T4xx
** Describe flash layout on Sandy Bridge and Ivy Bridge series.
Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
According to recommonmark's documentation the enable_auto_doc_ref is deprecated.
This is not true, as it's broken with Sphinx 1.6+ commit
12d639873953847de31ec99742b42e50e89ed58c.
recommonmark bug report is here: https://github.com/rtfd/recommonmark/issues/73
Instead of using this feature, which doesn't support top level directories in
the relative document path anyway, use the TOC tree or inline RST code.
Disable auto_doc_ref and document how to reference documents.
Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Linking this file instead of including a header makes it possible to easily
change gpio settings for a variant.
Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28628
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is pretty much like the G41M-GS, but with DDR3 memory
instead. The PCB layout is almost identical.
What works:
- S3/S4 resume
- RAM init
- Booting to Debian
- Display lights up w/ libgfxinit
- Both PS/2 work
- Ethernet
- Graphics card on PEG
- USB
- SATA ports
- NVRAM debug_level
- Internal flashing
- PCI slots (tested with CT4810 audio card)
- fancontrol (Only CPU fan can be regulated)
- Audio (Rear ports only)
What does not work:
- Hell knows what might be wrong
What is not tested:
- PCIe x1
- IDE
- Floppy
- Parallel port
Change-Id: I66b216af740680c390ea82e4fe07737c20227cc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set. This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.
Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Gigabit Ethernet network controller on whiskey lake rvp platform,
add NVM bin file as well.
BUG=N/A
TEST=Build and boot up into chromeos on whiskey lake rvp platform, and
check eth0 can get IP address assigned,
Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27848
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit
UPD, hence change the settings in coreboot side as well. The old options
in SiliconInit get deprecated, so leave the code as is will be
harmless. Make the changes limited to coffeelake itself.
Change-Id: If968de78117068668e4f0006c412442c50658ba9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28740
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sphinx displays a tab as four spaces, which makes code indented with
eight spaces per level stand out. Format the example configuration file
in fit.md consistently with tabs to make it look consistent everywhere.
Change-Id: Ia1d4c44e68e5267bac1f0f558421c6a0c7a9329c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change is required to apply patch
06_CorebootPayloadPkg_keep_cb_table since conflict in white space
between patch and target file in edk2 makes patch rejected while
building under coreboot-sdk:1.52.
Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl2 mainboard will follow in separate commits.
Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.
Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Increase power limit1 maximum value from 5W to 7W. This value as per
recent measurement on closed system which shows better performance
results.
BUG=None
TEST=Build and tested on Nocturne system. Performance tests
show better results.
Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous does not work well enough when testing with
high ambient temperature. Update DPTF settings to make
it work better.
List of tweaks:
1. Raise DRAM Critical temperature from 48C to 55C
Note that there are mechanisms in EC that complement
this because of DPTF limitation that we can't have
multiple passive temperatures.
2. Lower response time for DRAM temp sensor from 60s to 5s.
3. Increase throttle priority to the charger when DRAM hit
passive temperature from 100 to 200.
BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.
Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/28738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After emulating an instruction in the misaligned load/store handler, we
need to increment the program counter by the size of instruction.
Otherwise the same instruction is executed (and emulated) again and again.
While were at it: Also return early in the unlikely case that the
faulting instruction is not 16 or 32 bits long, and be more explicit
about the return values of fetch_*bit_instruction.
Tested by Philipp Hug, using the linuxcheck payload.
Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling")
Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This part of our documentation has bitrotted for a long time.
Any remaining information should ideally be moved to
Documentation/getting_started/kconfig.md.
Change-Id: I3920d002813c2838285446dc0ed8dacfa5364581
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28665
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FIT payloads do not support compression. Currently this would thrown an error
like the following:
E: FIT images don't support whole-image compression, compress the kernel component instead!
With this patch, menuconfig will correctly *not* show payload compression for
FIT payloads, and this will correctly set compression to NONE.
Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef
Signed-off-by: Andrea Barberio <insomniac@slackware.it>
Reviewed-on: https://review.coreboot.org/28732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The Cheza board contains a couple of non-standard FMAP sections that
contain per-board calibration data. When flashing new firmware to the
board, care should be taken to copy these sections over so that all
features can still function correctly afterwards. This patch wraps a new
RO_PRESERVE FMAP section around these sections to make them easier to
preserve as a group.
Change-Id: I77919336f609a1be399598736f46921c3da99e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Configuration of pins exposed by superIO are inconsistent between board
variants. Each platform should have UARTs enabled, this is expected
behaviour of these pins. Given that APU2_PINMUX_UART_x can be set for
all boards as default.
Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/28720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
My CPU (3770k) supports 9 MCE banks, but the code is hardcoded to reset
only 7. This causes Linux to spuriously log errors during boot and S3
resume.
Fix this by reading the real value from the right MSR.
Change-Id: Id05645009259fd77b4de49bde518361eeae46617
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/28443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This board doesn't support the newest RISC-V Privileged Architecture
spec (1.10), and it's based on an FPGA so it's a moving target.
Now that there's actual RISC-V silicon out there (from SiFive),
mb/lowrisc/nexys4ddr will only continue to bitrot.
Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since I2C bus 7 attached the touchscreen device however Phaser units
that haven't it. So for avoiding side effects, we need close I2C bus
7 SCL and SDA respectively.
BUG=none
TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3)
distinguish whether close these gpios.
Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28669
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following was tested:
- CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set)
- The VGA output with libgfxinit
- USB
- COM1
- Ethernet
- SATA
- PCIe
- PCI
Has the following problems:
- The Ethernet NIC is not usable after S3 resume and requires Linux to reload
the driver. Vendor firmware also has this problem so it is quite likely it
is just a atl1c driver problem.
TODO: Add documentation
Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().
BUG=b:116196626
TEST=build and boot grunt
Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit creates an ampton variant for Octopus. The initial settings
are copied from Bip, but the following changes are made to support
hardware differences:
* GPIO_66 is not connected (LTE).
* GPIO_67 is not connected (LTE).
* Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet.
* GPIO_143 is not connected.
* GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected.
* EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146.
* GPIO_213 is not connected.
* GPIO_214 is not connected.
BUG=b:111498206
TEST=None
Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add new mainboard variant of whiskey lake rvp, which is primary
validation platform for whiskey lake silicon, support socket DDR4 memory
module.
BUG=N/A
TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp
platform.
Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.
BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
boards and also check the margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No support for SoC D-1 stepping is available.
According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.
Also correct the RID_C_STEPPING_START value for C-0.
BUG=none
TEST=Built, Intel Cherry Hill Rev F.
Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)
The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.
Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC_IN_RW GPIO.
Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt variants need a way to customize the mainboard vendor based on the
platform. For future boards, this can probably be done via CBI, but
grunt doesn't support that method.
BUG=b:79874904
TEST=Build, boot, see updated mainboard vendor
Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
Update Power Limit1 and Power Limit2 values along with stepsize.
Correct the charger effect for Temperature sensor2.
BUG=b:112448519
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When preparing transition of AGESA calls to romstage, I placed a comment
indicating the place to move a particular call. Now that the AGESA call
has been moved to romstage, the comment became obsolete.
BUG=b:116095766
TEST=none.
Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It is much more convenient to view these files if there are 8 values per line,
not 1 value which results in a very long file. The contents remain the same:
these microcodes are still the latest publicly available at the time of writing.
Change-Id: I3e5296a5b5e895702a60aca1ded7418bb345263d
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28391
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This microcode update for CPU ID 0x300F10 should improve the system stability.
It is a part of microcode_amd.bin officially released by AMD at linux-firmware:
it starts at 0x217C offset, and size is 0x03C0 as specified priorly at 0x2178.
Old version: 0x300000F [2010-04-10]
replaced by
New version: 0x3000027 [2011-09-13]
Change-Id: I9650fab377d957904318ebb393323c2509cfea26
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28378
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT.
BUG=b:115965629
TEST=verified it in meep proto board which rework ram id.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363
Reviewed-on: https://review.coreboot.org/28658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.
To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.
TEST=Booted into Linux and checked coreboot log for resource assignment.
Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The DMAR table generation depends on the VT-d feature which is
implemented in its own PCI device located in PCI:00:05.0 for
Broadwell-DE. Add a new PCI driver for this device and move
DMAR table generation to this device driver.
Change-Id: I103257c73f5e745e996a441a2535b885270bc204
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address. Read the value from the PSP's
config space and sync each core's copy of the MSR to match.
BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg
Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28608
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD has tested careena, and for the time being is recommending a scalar
of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM
configuration code, set the desired values.
BUG=b:111561217
TEST=none, code was tested with grunt.
Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
While the pin was set to a pull-down, with the external pull-up, this
wasn't enough to keep the pin low. Set to output low to drive to 0V.
TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V.
BUG=b:115661061
Change-Id: Ife014b8a879274df5d892c1de386976808de1df0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Default STAPM percentage causes a lot of thermal throttling on grunt.
AMD experimented with 80%, it works for grunt. This is initial code to
provide easy change path for other grunt based platforms.
BUG=b:111608748
TEST=build and boot grunt.
Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron,
with the following changes:
- add buddy-specific variant code
- add handling to auron for buddy's lan init, which no other variants have
- add handling to auron's mainboard ACPI due buddy having different PCIe
port assigments than all other variants
Ported from Chromium branch firmware-buddy-6301.202.B, commit
ebb82ce [Buddy: Lock management engine + SPI descriptor]
Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads
Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use an empty weak function for variant_romstage_entry(), rather than
having separate empty functions for boards which don't utilize it.
Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add definition for PCH_GPIO_PIRQ_INVERT, which is needed
for google/buddy, a to-be-merged variant of google/auron.
Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53]
Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since CBMEM console became a ring buffer, logs from several boots can be
stored. We are only interested in the current boot.
> -c | --console: print cbmem console
> -1 | --oneboot: print cbmem console for last boot only
For CBMEM time stamps only the time stamps of the current boot are
stored, so only the commands for the CBMEM console need to be adapted.
Change-Id: I18caa4aeebbd5576b9e218d176a7db5a8e868b74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Using the cached CPU FSB setting can simply be wrong, in which case it won't
boot. Since the selected timings also depend on the CPU FSB, it is also best to
not use cached timings at all when a change is detected.
Tested on P5QC, swapped a 1333MHz FSB to a 800MHz FSB and it uses !fast_boot
boot path.
Change-Id: I12d91d0e892c15778409d7c00b27652ee52ca80c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To avoid mangled characters on serial output from iPXE we have to disable
serial from iPXE console. More to that to have correct serial input we
have to enable SeaBIOS SERCON option with default configuration.
The only limitation of this configs is that apu5 doesn't detect iPXE -
that platform is not for public use so it doesn't affect anyone.
Change-Id: I124705bd691b3c8dcd9a2636b17c019d02732c5a
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/28616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Extend the generic flash interface to probe for write protected regions.
Add Winbond custom code to return flash protection.
Tested on Cavium EVB CN81xx using W25Q128.
Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25082
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make XBCM `Serialized` (obvious), and check for the callee clearing the
request bit (we checked only the status for 0 which we potentially wrote
ourselves).
Change-Id: Ic92d525eda8d0a159fa5ddaacf230658d71c1578
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.
The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side,
pad R23) that is supposed to be high in S0, and low in S3 (and X/don't
care in S5).
This should be set as early as possible in bootblock.
BUG=b:113367227
TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high.
BRANCH=None
Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform
for easier collabration on newer platform. The setting in memory.c get
from board design itself.
BUG=N/A
TEST=Build and boot up with whiskey lake rvp platform.
Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28257
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.
The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
BUG=b:111812662
Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There are 8 possible BERT context errors, with table ctx_names being a
table to print their names. Thus the table is supposed to have 8 elements,
and indeed it has 8 lines... but some lines are missing commas, and when
compiling it becomes a 5 element table. Add the commas at the appropriate
places.
BUG=b:115719190
TEST=none.
Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
On the FU540 the bootblock runs on a core without lesser privilege
modes, so the medeleg/mideleg CSRs are not implemented on that core,
leading to a CPU exception when these CSRs are accessed.
Configure medeleg/mideleg only if the misa register indicates that
S-mode is implemented on the executing RISC-V core.
Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25791
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBLV is not kept up to date by Linux' i915. We should fix that too,
but it will likely take some years until we can always expect it to
work.
For now read the register values directly. To accomodate that we
are not the only one writing those, revise XBQC() to search for
the closest value in BRIG (instead of a lower equal one) and round
more accurately for better matches.
Change-Id: I4e2d8fa34e75463d4cf7242af3e2c67577cfa2a5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.
Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.
Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The pmh7 has at least a 9bit address space.
The h8s allows to access the 9th address space by using io port
0x15ed as second address register.
The pmh7 is connected via SPI to the h8s. The h8s is acting as
proxy to access the address space.
Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be
recalculated. Return correct tlck frequency in uart_platform_refclk.
Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The i386.c file uses standard 3f8 UART for some simple diagnostic
prints, and the libpayload console otherwise.
This payload was used to debug Linux as a rampayload and was very helpful
for that work.
Change-Id: I1cce5528780cd825fd91a88137fa70abd9f218e7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28600
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.
Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.
Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board version is part of EC's EEPROM, but is not being populated
from EEPROM. Instead a default Kconfig parameter is returned as board
version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable
requesting the EC for board version.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This modification for DVT build and use CBI method
enable all memory particles.
BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.
Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.
Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28582
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)
Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
GNU make is too smart (or too stupid?) for empty recipes. In the case of
empty recipes, GNU make doesn't consider the target as updated even if
its prerequisites are. So if we told make to rebuild `build/romstage/
lib/cbfs.o` for instance, and the FMAP changed, it rerun the fmaptool
recipe (as a prerequisite) but only considered `cbfs.o` to be updated
by chance.
Just not leaving the recipes empty seems to help here. I seeemed to
remember that it wasn't that easy, but it fixes the issue for me...
Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.
The SuperIO's datasheet was obtained by requesting it to Nuvoton.
Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.
Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.
Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.
Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This method has a pause instruction to help the CPU relax a little bit.
Measuring grunt it saves about 80mW.
BUG=b:109749762
TEST=Made sure that grunt boots.
Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The apic_delay method will halt the CPU and wait for a timer interrupt
to fire. I went with usec because nsec is too granular to guarantee.
This method will be called from an arch_ndelay() method when the delay
is large enough to justify a sleep.
BUG=b:109749762
TEST=Tested it on grunt by changing the _delay method to call
apic_delay().
Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is just the bare minimum required to initialize the APIC. I only
support xAPIC and chose not to support x2APIC. We can add that
functionality later when it's required.
I also made the exception dispatcher call apic_eoi so that the callbacks
won't forget to call it.
BUG=b:109749762
TEST=Booted grunt and verified that depthcharge continued to function
and that linux booted correctly. Also verified GDB still works.
Change-Id: I420a4eadae84df088525e727b481089ef615183f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of gpio_num, gpio_address should be used as the address in
write32. This lets us also get rid of a few casts.
Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed
one instance of this bug, but it was more widespread.
TEST=None
Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional
help text.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Expand the BERT reserved region size setting to account for the
possibility of no TSEG configuration. This change is only for
completeness, as stoneyridge must always use TSEG.
Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Fix the following compiler warning on the latest toolchain:
src/soc/sifive/fu540/otp.c:48:1: error: useless storage class specifier in empty declaration [-Werror]
} __packed;
^
Change-Id: Ice87c821de7650ac547394efa2a4bcc5ae1ea668
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28553
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix compilation issue
clint.c/mtime.c is needed as well in ramstage due to CR 28372 and 28355
Change-Id: I7c7768744a165b97978bb8f7f95acf7b32ca4aa4
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28551
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On rammus, headset uses DA7219 so that we need to enable it.
BUG=b:112945714
BRANCH=master
TEST=emerge-rammus coreboot chromeos-bootimage
Flash FW and check in kernel to see if DA7219 is up.
Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28537
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support for more situations: floating point, compressed instructions,
etc. Add support for redirect exception to S-Mode.
Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This patch sets the MRC UPD CmdTriStateDis for the
nocturne boards.Nocturne is LPDDR3 design without RTT
for CMD/CTRL.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: I0f593761dcbd121e7e758421af178931b9d78295
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I need to setup the APIC timer to fire interrupts. I would like to reuse
the existing interrupt table. So I extended it to support user defined
interrupts. I just added all 255 vectors so there wouldn't need to be
any additional build time configuration.
I'm going to deprecate exception_install_hook and remove it in a follow
up. It will be replaced with set_interrupt_handler. This way the
exception lookup does not have to manage a list of callbacks, or have to
worry about the order they are processed.
BUG=b:109749762
TEST=Wrote an interrupt handler and fired an APIC timer interrupt and
verified that vector 32 was returned.
Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
AMD chips don't hold off a reset to the end of I2C transitions, so
devices on the i2c bus can be left in a bad state. To avoid this,
make sure the trackpad and touchscreen chips get disabled
during boot.
BUG=b:114411165
TEST=build, reboot watch trackpad enable go low
Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28538
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coverity CID 1395334: (BAD_SHIFT) - In function _gpio_base3_value(), if
gpio_num is 32 and gpio[31] is floating, the end result is 1 << 32, which
does not fit into a int. To avoid a possible error, make it an error to have
num_gpio > 31. Function _gpio_base2_value also have the same issue, but the
limit would be 32. As in practice it'll never be used with more than 20 GPIO,
create a helper function to limit it to 31 and call it everywhere needed.
BUG=b:113788440
TEST=Add a fake code to southbridge_final calling the function and printing
the result. Build and boot grunt, check result.
Change-Id: I0b79725bcbaf120587c7440e176643aaa7a1d5bb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28445
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Boot Error Record Table to the ACPI information. Avoid a driver
error message by skipping the table altogether when no errors are found,
or support isn't built in.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28478
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to build a Boot Error Record Table region based on
settings found in the MCA registers.
Two entries are reported for each error due to the nature of the ACPI
driver. The first is a Generic Processor Error, which the OS recognizes
and parses. Generic errors cannot convey much error description or
processor context. Therefore an IA32/X64 Processor Error is also added,
which allows reporting the values found in the MCA MSR registers.
Follow-on work could decode the MC errors more precisely, and better
completing the Generic Error and the Check structure. The current
level of support is sufficient to identify a (i.e., human readable)
problem in dmesg, and provides adequate context information for
analysis.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28477
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert the Machine Check reporting to use a newly defined structure.
This will facilitate later patches that will pass pointers to the MSR
values.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28476
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the process of interrogating the Machine Check registers into
its own file. This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Carve out memory to be reported to the OS as reserved. This makes
room for a region usable for Boot Error Record Table information.
The BERT region reserved size is larger than likely requried, however
the SMM region's base must be on a boundary matching the granularity
of its size.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28474
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add more definitions to be used for Machine Check Architecture
support, mainly for determining the type of error that is being
interpreted. MCA is described in detail in the BKDG.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Create a structure for the Boot Error Record Table, and a generic
table generator function.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the proper table revision level for the Boot Error Record Table.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28471
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add code for generating the region pointed to in an ACPI Boot Error
Record Table.
The BERT region must be reported as Reserved to the OSPM, so this
code calls out to a system-specific region locator. cbmem is
reported as type 16 and is not usable for the BERT region.
Events reported via BERT are Generic Error Data, and are constructed
as follows (see ACPI and UEFI specs for reference):
* Each event begins with a Generic Error Status Block, which may
contain zero or more Generic Data Entries
* Each Generic Data Entry is identifiable by its Section Type field,
and the data structures associated are also in the UEFI spec.
* The GUIDs are listed in the Section Type field of the CPER
Section Descriptor structure. BERT doesn't use this structure
but simply uses its GUIDs.
* Data structures used in the Generic Data Entry are named as
Error Sections in the UEFI spec.
* Some sections may optionally include a variable number of
additional structures, e.g. an IA32/X64 processor error
can report error information as well as machine contexts.
It is worth noting that the Linux kernel (as of v4.4) does not attempt
to parse IA32/X64 sections, and opts to hexdump them instead.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28470
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
this enables spi console for wedge100s with broadwell_de. the console
size is 64kb. enabling spi console in `board.fmd` enables code which
calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and
`udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE`
in fsp_broadwell_de's Kconfig to satisfy that.
Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.
TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.
Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On rammus, system halt was observed because of gspi clk value being set to 0.
Log info from serial coreboot:
FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes)
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
VBNV: Restore from flash failed
ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443
gspi.c
442
443 assert(gspi_clk_mhz != 0);
444 assert(ref_clk_mhz != 0);
445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;
BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28405
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a function to set the Bios Interface Lock Down bit (bit 31)
in RTC Configuration register (0x3400). This bit when set prevents
the top swap enable bit (bit 0) in the RTC BUC register (0x3414)
from being changed.
Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Standardize on using vboot_handoff data structure for transferring
data between coreboot and depthcharge. chromeos_acpi_t.vdat is
undefined until set in depthcharge.
BUG=b:112288216
TEST=compile and run on eve
CQ-DEPEND=CL:1198814
Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9
Signed-off-by: Joel Kitching <kitching@gmail.com>
Reviewed-on: https://review.coreboot.org/28407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add ACPI Platform Error Interfaces definitions that will be used
for building a BERT table region in a subsequent patch. Two tables
are defined: the Generic Error Status Block, Generic Error Data
Entry.
For reference, see the ACPI specification 6.2-A tables 381 and 382.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add definitions from the UEFI appendix on Common Platform Error
Record (appx. N in revision 2.7-A). The structures and fields
defined are the minimum required for generating ACPI Boot Error
Record data in a subsequent patch.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Nautilus-Wifi with m3 AP got a halt issue during CTS test.
Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.
Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.
Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.
BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.
Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP 2.1 implementation is adding features on top of fsp2_0.
One such feature is a shared stack implementation that requires
coreboot to allocate stack for fspm and then fsp uses the same
stack as coreboot. This implementation adds support for shared
stack feature.
Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/28358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We already explicitly generated a dependencies file for the romcc
bootblock. Though, as it has its own rule and isn't registered
to any of our object-file classes, the dependencies file wasn't
included automatically.
Change-Id: I441cf229312dff82f377dcb594939fb85c441eed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/28442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.
Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Check payloads, the root Makefiles and toolchain.inc
- 3rdparty is already not checked, so remove
- The marks around COPYING, LICENSE, and README were not needed
- Skip checking .ico files
Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"
I found that changing this to other forms takes MUCH longer, so I left
the original method mostly unchanged except for moving the include &
exclude lists into variables.
Currently, I'm setting all non-linux operating systems to use the second
version. I'll update that if I find other that other OSes support the
first.
Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.
BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'
Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins
execution will enable cache, then CAR will disappear. So the
Stack will be separated.
Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable dGPU power handling on Lenovo ThinkPad T430, T530 via PMH7
register 0x50.
Although there's no Thinker-1 chip on these models according to
schematics, dGPU power control via PMH7 works the same as on T420/T520,
so they can be considered Thinker-1-compatible.
It can be tested from linux userspace using util/pmh7tool.
To turn dGPU power off:
pmh7tool -c 0x50 7
pmh7tool -c 0x50 3
To turn it on:
pmh7tool -s 0x50 3
pmh7tool -s 0x50 7
To check whether it is on (bash):
reg=0x$(pmh7tool -r 0x50)
echo "$(( (( reg & 0x08 )) >> 3 ))"
or just `pmh7tool -b 0x50 3` with
https://review.coreboot.org/#/c/coreboot/+/28388/
Tested on ThinkPad W530.
Change-Id: Ieab1a33b3c680c757cc0999660b5cb7e122474cc
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28392
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node.
Without DRIVERS_SPI_ACPI, the kernel will popped out the below error:
cr50-update[592]: Starting cr50 update
cr50_get_name[595]: updater is /usr/sbin/gsctool -s
cr50-update[609]: exit status: 3
cr50-update[613]: output: Could not open TPM: No such file or directory
cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod'
cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod
cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state
cr50-update[682]: not running
cr50-result[782]: Not running normal image. Skip setting Board ID
trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory
BUG=none
BRANCH=master
TEST=/dev/tpm0 is created
Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Like the 3rdparty/blobs repo this isn't checked out by default. Right
now you can manually check it out using
$ git submodule init --checkout
A follow up commit will add some automagic if USE_BLOBS and
MAINBOARD_USES_FSP2_0 are enabled.
Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/28303
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overhauls the Cheza FMAP, removing some sections we don't
seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of
RW_DDR_TRAINING), and adding new sections we're going to need soon or
should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY).
Make more use of implicit offsets and sizes, because we can and because
it should make future adjustments easier.
Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: T Michael Turney <mturney@codeaurora.org>
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.
BUG=N/A
TEST=N/A
Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f.
Through this we know that the length of the long's bit is equal to pointer.
So update this code. This's more flexible.
Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27768
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefore code needs to be
updated.
BUG=b:69231009
TEST=Build and boot grunt.
Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Also removed internal pull ups for CX_PREQ_L and
CX_PREQ_L signals as they have external pull ups.
BUG=b:110654510
TEST=On Yorp Proto 2, flashed image and verified that it boots to OS.
Checked Wake-on-Wifi works with both cnvi and pcie modules.
Also executed a few suspend resume cycles.
Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/28328
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC base address is different for CNP LP pch and CNP H pch.
Added logic to determine PMC base addrress dynamically based on PCH ID.
BUG=none
BRANCH=none
TEST=Boot Coffeelake U RVP board and check if PMC base address is
determined correctly.
Change-Id: I833395260e8fb631823bd03192a092df323250fa
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27523
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should always update BCLP, no matter if the driver is ready yet to
process the request. This way it will hold the current value when the
driver initializes.
Change-Id: I4b091d744f95da39abe542966f0a8589a187573b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.
Only affects brightness control using mailbox3.
Fixes: 6838aaebf9 ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Grunt takes a few seconds to update the EC, so display a notification
screen while that's happening.
BUG=b:113286040
TEST=Boot Grunt with old EC firmware, see update screen
Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return
of an undefined value, as no for loop will be executed. Assert that it's
not 0.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some ACPI interfaces introduced by Chrome or coreboot do not
need drivers outside ChromeOS, for example Chrome EC or
coreboot table; or will be probed by direct ACPI calls (instead
of trying to find drivers by device IDs).
These interfaces should be set to hidden so non-ChromeOS systems,
for example Windows, won't have problem finding driver.
Interfaces changed:
- coreboot (BOOT0000), only used by Chrome OS / Linux kernel.
- Chrome OS EC
- Chrome OS EC PD
- Chrome OS TBMC
- Chrome OS RAMoops
BUG=b:72200466
BRANCH=eve
TEST=Boot into non-ChromeOS systems (for example Windows)
and checked ACPI devices on UI.
Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1078211
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Trybot-Ready: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The firmware of devices connected to LPC should deassert the LPC CLKRUN#
signal when there is no bus activity on LPC.
Necessary changes:
- Enable LPC CLKRUN#
- Enable LPC PCE (Power Control Enable)
- Enable LPC CCE (Clock Control Enable)
- Remove I/O decoding range on LPC for COM 3
- Disable I/O UART driver
Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Only Ids.h had definitions still in use, and they were removed or moved to
AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed.
BUG=b:112885948
TEST=Build grunt
Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28299
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bayhub eMMC controller default runs SD base 50MHz at the first power on.
After boot into OS, mmc kernel driver will config controller to HS200/208MHz
and send MMC CMD21 (tuning block).
But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear
after system warm reset.
So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge.
It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to
load kernel and trap in 0x5B error (No bootable kernel found on disk).
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:113101335
BRANCH=atlas
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU0: Package temperature above threshold'
Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619
Reviewed-on: https://review.coreboot.org/28325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:67459049
BRANCH=nocturne
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU3: Package temperature above threshold'
Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458
Reviewed-on: https://review.coreboot.org/28324
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macro IDS_ERROR_TRAP is only defined, and never used. Also,
IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate
to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED.
BUG=b:112885948
TEST=Build grunt
Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Function IdsErrorStop() is only used within AmdLib.c function
LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and
three times inside AmdLib.c, all with well defined MSR addresses.
IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which
clearly it's not. Therefore it can be safely removed from AmdLib.c.
BUG=b:112885948
TEST=Build grunt
Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Update TSR1 trip point from 48C to 50C.
Also, change power limit2 minimum value from 8W to 10W.
These are the values as per recent thermal tuning.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28187
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the MADT table version to sync with the FADT table version.
All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0
and the MADT should be set to match.
This error was found by running FWTS:
FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with
the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead.
BUG=b:112476331
TEST-Run FWTS
Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Use a single function to set ACPI table versions. This allows us
to keep revisions synced to the correct levels for coreboot. This
is a partial fix for the bug:
FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not
in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0
instead.
BUG=b:112476331
TEST-Run FWTS
Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28276
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the datasheet (rev. 1.6) there is no SP2 (apart from
some typos) and the IR is actually implemented as SP3 in LDN 0x16.
Additionally, there is LDN 0x15 to set up CIR-specific options of the
IR serial port, which was missing as well.
Change-Id: I34d90d8c44f11a4f62ccc4b836409cc443fb7952
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since libpayload doesn't link against libgcc we need to define our own
cpuid macro. I didn't add any error checking since anything in the last
decade should support cpuid.
BUG=b:109749762
TEST=called it and made sure the correct flags were returned.
Change-Id: Id09878ac80c74416d0abca83e217516a9c1afeff
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With Alpine base, use pip to install Sphinx 1.7 and Sphinx-autobuild
Alpine, a 4.5MB base, is used over Debian Stable, 101MB, to cut down the
total size of the docker image.
Change-Id: I53f246206458b1de34cd7f3a42481b91ca285ff0
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On some detachables, the mere presence of attached base is not enough to
determine whether the device is in tablet mode or not, so we introducing
a new "switch" in EC, separate from "Tablet Mode" switch, to signal
whether the base is attached or not.
We also want the driver to be separate from cros_ec_keyb, so we create
a new ACPI device, C(hrome)B(ase)A(ttached)S(witch), with HID GOOG000B,
and guard it with EC_ENABLE_CBAS_DEVICE.
Change-Id: Id73a12f04a1a48f7fbd9365c2a501afadf3878fa
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/28260
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the 1st redesign of mc_apl1 mainboard some adjustments are
necessary:
- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings
Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
A FPGA is not necessarily available in further mc_apl1 variants. So we
move the loading of the driver and the notify function to the mc_apl1
variant.
Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary
for further variants.
Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This supports the Foxconn d41s, d42s, d51s, d52s.
The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:
- COM1
- S3 resume (with SeaBIOS needs sercon disabled)
- Native graphic init on VGA output
- SATA
- USB
- Ethernet
- PS2 keyboard
The base for this mainboard port was the Intel D510MO port.
Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28227
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This open-codes flash_cmd, but until the API is fixed for real, it uses
xfer's existing scatter-gather ability to write command and data in one
go.
BUG=chromium:446201
TEST=emerge-coral coreboot succeeds
Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since ifdfake has been deprecated in favor of better alternatives, such
as flashrom IFD parsing. Therefore, there is no need to support ifdfake
any further. Remove the IFD_*_REGION values on the few motherboards with
them.
Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28232
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a small window of opportunity when CPU is already in SMM but has
not yet entered S3 for a wake event to happen, which would cause a failed
S3 entry. Check for pending events at the very last moment possible, and
if there are pending wake events report them.
BUG=b:111100312
TEST=build and boot grunt.
Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For debug reasons, sometimes you not only want to log an event, but also
some extra information that would help debugging. Create an extended event
reporting event type with a dword complement, and define extended events
for failing to enter S3 due to pending wake event (one for pm1 and one for
gpe0).
BUG=b:111100312
TEST=Add a fake pending wake event, build and boot grunt, see the event in
eventlog.txt.
Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy code of depthcharge boot/coreboot.c and adapt it.
Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable
and prints the log.
Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There's nothing Sandy Bridge specific in this code.
Make it available on all platforms to reduce code duplication.
Tested on Lenovo T430: SMBIOS entry 17 is still valid.
Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Fix ACPI resume path compilation for TPM ramstage
driver
* Move enabling of the TPM prior activation and remove
reboot return status from TPM enable.
More information can be found via the TCG
specification v1.2
Tested=Elgon
Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28085
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no public datasheet available for this SuperIO so the resources are
guessed by looking at other ITE SuperIO's and the register dumps while running
vendor firmware.
The only board with this SuperIO in the tree is the asus m5a88-v. Most of the
devicetree entries would have been invalid here so one should not worry too much
about regressions.
Tested with Foxconn d41s.
Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When doing the receive enable training, the final mapping of the ranks is
already done, so we can be sure that that address 0x00000000 there will always
be a rank.
Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These
functions are used by PspBaseLib. Remove all functions that are not used,
directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite().
BUG=b:112688270
TEST=Build grunt
Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28194
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This small change is required for the successful loading of microcode
from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs,
such as A10-5750M found at coreboot-supported Lenovo G505S laptop.
Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode,
so the Richland RL-A1 IDs should be added to this equivalence table.
Function `GetPatchEquivalentId()` in
`src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c`
goes through the equivalence table like below.
for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
// check for equivalence
if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
*ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
return (TRUE);
}
}
Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28204
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: <awokd@danwin1210.me>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.
BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
2. Verify the MSR PL1 limitation is set correctly.
Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There were so many pitfalls that I wrote my own version of this even-
tually. This version is inspired by the procedure of Alex Thiessen[1].
Instead of generating a `build.h` on demand, we always generate a tem-
porary version that, if it differs from the current one, is added as
a dependency.
As we use .SECONDEXPANSION on the prerequisites, special care is taken
that we won't generate the file twice. As it would be too late to add
the dependency if we'd run `genbuild_h.sh` inside a recipe, we have
to run it through the `$(shell)` function. But that brings us to the
next issue: The make variables used by `genbuild_h.sh` are not expor-
ted to this shell like they would be in a recipe. So we export them
manually. We could also make these variables explicit parameters of
`genbuild_h.sh` instead.
An alternative to always creating the temporary `build.h` would be
to add a phony target as dependency instead, and finally calling
`genbuild_h.sh` again in case we need an update. But, um, we create
so many files anyway...
[1] https://review.coreboot.org/25685
Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC).
Linux has a driver that enables features like speed shift without
consulting ACPI. Other OSes instead rely on this information and need a
_CPC present. Prior to this change performance in Win10 never exceeds
80% and MSR 0x770 is 0, while with this change (and enabling eist) higher
speeds can be achieved and the MSR value is now 1.
Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds a method to init a cppc_config structure in a way that
should ideally work across Intel processors that support EIST.
Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is meant to solve an issue where the proximity sensor may fluctuate
between CLOSE / FAR in rapid succession upon the user removing their hand
from the unit, before settling on the correct output.
Using the hardware debouncing filter solves this issue and removes the
spurious fluctuations.
BRANCH=None
BUG=None
TEST=manual on Nocturne, observing events come in
Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/28112
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures
USB-C as device mode. Force USB-C into host mode.
BUG=b:111623911
TEST=Verified that USB-C being host mode once USB OTG is set.
Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
src/soc/intel/common/block/cpu/mp_init.c
Function init_cpus: Pointer dev checked for NULL may be
dereferenced.
src/soc/intel/common/block/graphics/graphics.c
Function graphics_get_bar: Pointer dev returned from
call may be NULL and will be dereferenced.
BRANCH=None
TEST=Built & booted Yorp board.
Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The romstage main() entry point on arm64 boards is usually in mainboard
code, but there are a handful of lines that are always needed in there
and not really mainboard specific (or chipset specific). We keep arguing
every once in a while that this isn't ideal, so rather than arguing any
longer let's just fix it. This patch moves the main() function into arch
code with callbacks that the platform can hook into. (This approach can
probably be expanded onto other architectures, so when that happens this
file should move into src/lib.)
Tested on Cheza and Kevin. I think the approach is straight-forward
enough that we can take this without testing every board. (Note that in
a few cases, this delays some platform-specific calls until after
console_init() and exception_init()... since these functions don't
really take that long, especially if there is no serial console
configured, I don't expect this to cause any issues.)
Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28199
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation to removing AmdLib, function LibAmdLocateImage() has to be
ported to be used by agesawrapper. The most important aspect of this porting
is that it has to obey coreboot format, specifically 8 character tab and 80
characters max. This required breaking the function in 2 (to solve
indentation) and rename some variables to shorter names.
One important aspect was breaking
(AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset)
into:
image_ptr = (AMD_IMAGE_HEADER *) current_ptr;
if (validate_image((void *)image_ptr->ModuleInfoOffset,
and, within validate_image completed by:
AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain;
BUG=b:112625809
TEST=Build grunt, functionality tested in next commit.
Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following Error:
FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
142
Line | AML source
--------------------------------------------------------------------------------
00139|
00140| Scope (\_SB.PCI0.IGFX)
00141| {
00142| Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory
| ^
| Remark 2120: Control Method should be made Serialized (due to creation of named objects within)
00143| {
00144| OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00)
00145| Field (ROMS, AnyAcc, NoLock, Preserve)
================================================================================
ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.
Use the acpigen_write_method_serialized() to correct the error.
BUG=b:112476331
TEST=Run FWTS.
Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fix the following FWTS error:
FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line
3038
Line | AML source
--------------------------------------------------------------------------------
03035| Return (One)
03036| }
03037|
03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query
| ^
| Warning 3115: Not all control paths return a value (_Q09)
03039| {
03040| If (Acquire (PATM, 0x03E8))
03041| {
================================================================================
ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths
do not return a value. All control paths that return must return a value
otherwise unexpected behaviour may occur. This error occurs because a branch on
an conditional op-code returns a value and another does not, which is
inconsistent behaviour.
_Q09 is a reserved method and can't return a value. Change the logic
so that no return is used and avoid this test error.
BUG=b:112476331
TEST=Run FWTS.
Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the following failure from FWTS:
FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
131
Line | AML source
--------------------------------------------------------------------------------
00128| }
00129| }
00130| })
00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
| ^
| Remark 2120: Control Method should be made Serialized (due to creation of named objects within)
00132| {
00133| Name (RBUF, ResourceTemplate ()
00134| {
================================================================================
ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.
BUG=b:112476331
TEST= Run FWTS.
Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28122
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the IASL build warnings:
Object is not referenced (Name [CDW2] is within a method [_OSC])
Object is not referenced (Name [CDW3] is within a method [_OSC])
Remove the not referenced objects. They are not needed.
BUG=b:112476331
TEST=IASL doesn't give the warning.
Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change adds 2 methods for Conginuous Performance Control that was
added in ACPI 5.0 and expanded twice in later versions. One function
will create a global table based on a provided struct, while the other
function is used to add a _CPC method in each processor object.
Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The existing code for modifying the power state after power loss of the system
only implemented the transitions from power off to either power on or power keep
properly.
Since I don't have a board with this chip, I couldn't test the patch on real
hardware. The two cases described above were tested before the original patch
was merged, so I'd expect this to work.
Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Update SPD details to match with Coffeelake U RVP board
BUG=none
BRANCH=none
TEST=Boot on coffelake U rvp board and check if memory training is
passing and board boots till payload.
Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Nami doesn't support wakeup from hibernation by CR50. This causes the
device to remain turned off after CR50 update.
This patch disables turning off EC on cr50 update. CR50 resets the
whole system. So, EC reset is not required.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709
Reviewed-on: https://review.coreboot.org/28113
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows boards to disable turning off EC on cr50 update.
If CR50 resets the whole system, an EC reset is not required.
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I60a7aa50a549e7a5a1a114245fbf7b9646d813bb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/28110
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change permits the subsystem ID to be specified via Kconfig for the
devices on the SoC.
Some devices are getting zero'ed subsystem IDs because the unset (and thus
zero'ed) config options are overwriting the fsp defaults. With this change
the fsp defaults will only be overwritten by non-zero config values.
Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when
VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed.
BUG=b:112602580
TEST=Build grunt and gardenia.
Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28093
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The specification updates for ICH 9 & 10 require to leave the
register in its default state by reserving all of its bits.
Writing to it does not seem to make a difference anyway since
reading it afterwards does not reflect the write (tested on ICH10).
Therefore we should omit the writes but document this fact in the
code because it is easy to miss from the datasheet alone.
Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All of the callers to acpigen_write_register() also make calls to
acpigen_write_resourcetemplate_[header|footer](). This change introduces
acpigen_write_register_resource() to unify all of those trio of calls
into one. I also made the input parameter const.
Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and
from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal
of VENDORCODE_FULL_SUPPORT from coreboot.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in
preparation to full removal of VENDORCODE_FULL_SUPPORT functions.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in
preparation to full removal of VENDORCODE_FULL_SUPPORT functions.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Id91e76282509743070e34c02082d3f3f46a14059
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Now that the functions that used them were safely removed, remove
LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW().
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The functions that use LibAmdPciRMW() are not used by coreboot and can be
safely removed in preparation to remove LibAmdPciRMW() itself. The
functions to be removed are:
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c:
ProgramPciByteTable().
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(),
RwXhci0IndReg() and RwXhci1IndReg().
From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci().
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The functions that use LibAmdMemRMW() are not used by coreboot and can be
safely removed in preparation to remove LibAmdMemRMW() itself. The
functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(),
both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c.
BUG=b:112541697
TEST=Build grunt and gardenia
Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Side effect was observed that after override BayHub EMMC
driving strength to the max, EMMC CLK will be reduced to
51.x Mhz from 200 Mhz.
This will cause OS installation fail on Samsung EMMC sku.
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This file contains two instances of "dptf_enable" = "1". This change
removes the 2nd instance (it doesn't have an explicit comment like the
1st instance).
The dptf devices still seem to be present even with this change, as
expected.
Change-Id: I890006644be9176ebaf555cc121c816e12f2b596
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The spec of the sx9310 says the I2C interface can handle standard
(100kb/s) and fast mode (400kb/s). The current setting is using fast
plus (1000kb/s) so this change is reducing the speed to fast mode.
I've been using the sensors with this change for a few weeks now, though
I also don't recall seeing an issue prior to this change.
Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This defines new GPIO pin for controlling the display panel CABC
function. The default value is high (enabled).
BUG=b:112154569
Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the DPTF sensor names to reflect the sensor locations on
the board.
BUG=b:75454415
TEST=verified new strings show up in
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description
Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28069
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Within procedure LzmaDecode(), the variable len can be assigned a value
that is never read after, thus causing a static analysis error. Tell the
coreboot scan-build static analysis we know it can happen.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I37bc3ff19ca85f819ba1cbb2a281c1ad55619da9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Under some conditions, cr50_i2c_read() can return without actually reading
the TPM, which will leave access uninitialized. Set an initial value for
access, and if TPM fails to respond in time check if at least TPM was read.
This way avoids printing an uninitialized value.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I5ec7a99396db32971dc8485b77158d735ab1d788
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
FAKE_IFD depends on out tree flashrom patches for which there are better
alternatives available now, so don't build with FAKE_IFD by default.
Change-Id: I2c6a6586da9a6d26b0a5bf7d3ba8f3ffe3205647
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the newest feature of me_cleaner to ifdtool
(https://github.com/corna/me_cleaner/ , Discussed in
https://github.com/corna/me_cleaner/issues/53 ) to
set AltMeDisable (or HAP for skylake/ME11) bit to the
IFD to disable ME.
In this commit I use (ifd_version >= IFD_VERSION_2) to
judge whether HAP instead AltMeDisable should be set,
since this condition is only fulfilled on skylake
or newer platforms.
This feature needs to guess ich revision, which needs
guess_ich_chipset() from flashrom to be ported here.
Routines to dump those bits are also added.
Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.
Within the chromeos_acpi_t structure, there is a member
called vdat. This (currently) holds a VbSharedDataHeader.
Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.
Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.
BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722
Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch updates Power Limit (PL) for AML.
- PL1 as 5W TDP as POR
- PL2 as 18W TDP as POR
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP.
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power
5000000 (5W TDP)
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power
18000000 (18W TDP)
Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/27427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates GPIO configuration for bobba boards with id >= 1
This follows the same model as fleex:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
BUG=b:112354568
TEST=Built firmware for bobba
Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28071
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for new board coffeelake RVP.
This patch is a copy patch and copies entire coffeelake_rvp folder from
cannonlake_rvp.
Changes done on top of copy:
1. Change copyright year from 2017 to 2018
2. Rename Cannonlake to Coffelake whenever applicable
3. Update entries in Kconfig and Kconfig.name
4. Rename variant directories to match coffeelake boards
Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
acpidump now creates dumps with 4 spaces instead of 2 in front of the hex dump,
so be a bit smarter about the input with regexp.
Tested with X220 autoport logs: Still creates the same coreboot code.
Change-Id: I8d48c09cdff9432f394b350540ea9765fc942781
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
No idea where the escaped parentheses come from but they
are no good. Without this patch I see errors with bash and dash:
./buildgcc: line 1198: (: command not found
./buildgcc: line 1199: (: command not found
The patch uses curly brackets for grouping since they don't
launch a subshell - unlike using unescaped parentheses which
would work too.
shellcheck is happy with either variant (and the original one(!)).
Change-Id: I44fbc659f5b54515e43e85680b1ab0a824b781a7
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Unfortunately stmicro.c does not distinguish the 1.8V version from
the 3.3V versions (yet) although they have distinct RDIDs.
I have at least ordered the ID macros accordingly and used a proper name
in this patch.
Change-Id: Id4fd8d46dcc9e51c1ae5504a32c2f8c5cfd863a1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
FAKE_IFD depends on out tree flashrom patches for which there are better
alternatives available now, so don't build with FAKE_IFD by default.
Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If BUILDDIR were an empty string, running `make clean` would result in
running `rm -rf /*`. Omitting the trailing /* prevents this.
With a valid BUILDDIR, the behaviour of `make clean` changes slightly in
that BUILDDIR itself is removed. However, this is probably more in line
with what one would expect from `make clean`.
Change-Id: I51b52bb6e7fe73a07fed6291a4f1cc253f2bf319
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27775
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This binary needs to be at a specific offset and will therefore always
be located in the COREBOOT fmap region.
This is needed when VBOOT_SEPARATE_VERSTAGE is selected.
Change-Id: Ia73d468ab23932f92331ef40b8e8066cef55af2c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Comment out 'sepc' and add a comment about it at the top so that it
doesn't get added back in accidentally in a future update.
Change-Id: Iaa909d97d0d97d7bf0799e48fc237a9673d549aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was blindly copied from logs created under vendor BIOS in non-descriptor
mode which apparently set LAND in BUC.
Change-Id: I94c917600421ee742ece7f6f71309da80261da28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since commit 372d0ff1d1 (arch/arm64: mmu: Spot check TTB memory
attributes), we already check the memory attributes that the TTB region
is mapped with to avoid configuration mistakes that cause weird issues
(because the MMU walks the page tables with different memory attributes
than they were written with). Unfortunately, we only checked
cachability, but the security state attribute is just as important for
this (because it is part of the cache tag, meaning that a cache entry
created by accessing the non-secure mapping won't be used when trying to
read the same address through a secure mapping... and since AArch64 page
table walks are cache snooping and we rely on that behavior, this can
lead to the MMU not seeing the new page table entries we just wrote).
This patch adds the check for security state and cleans up that code a
little.
Change-Id: I70cda4f76f201b03d69a9ece063a3830b15ac04b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In procedure smm_load_module, variables fxsave_size and fxsave_area are set
to 0 and NULL, but if CONFIG_SSE is enabled, they are overwritten. Change
the code setting the value to an "else" of the "if" testing CONFIG_SSE, thus
avoiding static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I3042b037017a082378b53ee419c769c535632038
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There's two instances od _UID 1 for PNP0C02. This change moves the
more system-specific instance of the two to a higher number. I
believe these are the 4 I'm seeing.
soc/intel/skylake/acpi/systemagent.asl
Device (PDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
soc/intel/skylake/acpi/lpc.asl
Device (LDRC)
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 2)
ec/google/chromeec/acpi/superio.asl
Device (ECMM) {
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 1)
ec/google/chromeec/acpi/superio.asl
Device (ECUI) {
Name (_HID, EISAID ("PNP0C02"))
Name (_UID, 3)
Change-Id: I2b0f1064726a1fa3940ccfb2a4627c79a26684e4
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- PRINTK_WITHOUT_KERN_LEVEL is a new warning that coreboot's printks
don't follow.
- UNDOCUMENTED_DT_STRING is ignored because we don't have any
documentation for .dt files.
- SPDX_LICENSE_TAG is another new warning. We can evaluate adding the
spdx license tags to our files, but at this point they aren't there, so
disable it for now.
Change-Id: I4b7fcfc0339b358a48e77188d85b47c022c7eb49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch changes the mapping of SRAM from non-secure to secure.
Without this patch, mmu_config_range() can not work when MMU is
enabled. The new config is still in non-secure cache since TTB section
is allocated in SRAM which is mapped as non-secure.
BUG=b:80501386
TEST=Boots correctly on Kukui and Elm
Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.
BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.
Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using recent versions of parecord produces the following:
Failed to open audio file.
According to the manual:
-r | --record
Capture audio data and write it to the specified file or to STDOUT if none is specified. If the
tool is called under the name parec this is the default.
so we suggest parec instead.
Change-Id: I8b821df67b10e9d6533c4cbe19c646c84d436c27
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.
Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.
BUG=b:112371978
Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.
BUG=b:112371978
Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is no need to add a special cnvi.asl file for the CNVi
device. This can be handled by drivers/intel/wifi just like a PCIe
WiFi device. This change gets rid of the cnvi.asl file and its usage
in southbridge.asl file.
BUG=b:112371978
Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.
BUG=b:112371978
Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.
BUG=b:112371978
Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change updates GPIO configuration for fleex boards with id >= 1
This follows the same model as phaser:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
d. Disable unused I2C devices in devicetree.
BUG=b:112458032
TEST=No errors observed on boot-up on fleex.
Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 3603). Tested with Linux 4.9 and everything works as
expected.
Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/28050
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move cbmem.c to cn81xx folder
* Store CBMEM below 4 GiB
* Make sure CBMEM doesn't overlap with ATF scratchpad
* Fix ATF scratchpad not marked as reserved due to wrong calculation
* The scratchpad is the last 1 MiB at the end of DRAM.
Tested on Cavium CN81xx EVB:
The ATF scratchpad is now marked reserved and the configuration tables
are located below 4 GiB. Linux still boots.
Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27955
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow for shared dram configuration by introducing a new table
that collapses the common settings after removing the part
numbers. When employing this scheme the part number comes
from CBI.
BUG=b:112203105
TEST=Placed part number in cbi. Faked out memory sku id. And enabled
DRAM part num always in cbi. Everything checked out.
Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Options that were deemed unneceesary on other code reviews have
been removed from the layout files. In addition, the checksummed
range has been extended to cover sata_mode and gfx_uma_size.
Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards.
Based on another mainboard's code review comments, this patch
improves the code quality of these three similar boards.
ga-h61m-s2pv is tested and confirmed to be working, but I cannot
say the same regarding the other two mainboards as I do not have them.
Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Curley brace expansion is a bash-ism, so we can't use it for the
u-root command list.
This unfortunately also breaks the current Kconfig option since the
list needs to be separated by space instead of commas.
Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c
BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.
Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Accesses to architectural registers should be really fast -- they're
just registers, after all. In fact, the arm64 architecture uses them for
some timing-senstive uses like the architectural timer. A read should be:
one instruction, no data dependencies, done.
However, our current coreboot framework wraps each of these accesses
into a separate function. Suddenly you have to spill registers on a
stack, make a function call, move your stack pointer, etc. When running
without MMU this adds a significant enough delay to cause timing
problems when bitbanging a UART on SDM845.
This patch replaces all those existing functions with static inline
definitions in the header so they will get reduced to a single
instruction as they should be. Also use some macros to condense the code
a little since they're all so regular, which should make it easier to
add more in the future. This patch also expands all the data types to
uint64_t since that's what the actual assembly instruction accesses,
even if the register itself only has 32 bits (the others will be ignored
by the processor and set to 0 on read). Arm regularly expands registers
as they add new bit fields to them with newer iterations of the
architecture anyway, so this just prepares us for the inevitable.
Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When we first created the arm64 port, we weren't quite sure whether
coreboot would always run in EL3 on all platforms. The AArch64 A.R.M.
technically considers this exception level optional, but in practice all
SoCs seem to support it. We have since accumulated a lot of code that
already hardcodes an implicit or explicit assumption of executing in EL3
somewhere, so coreboot wouldn't work on a system that tries to enter it
in EL1/2 right now anyway.
However, some of our low level support libraries (in particular those
for accessing architectural registers) still have provisions for
running at different exception levels built-in, and often use switch
statements over the current exception level to decide which register to
access. This includes an unnecessarily large amount of code for what
should be single-instruction operations and precludes further
optimization via inlining.
This patch removes any remaining code that dynamically depends on the
current exception level and makes the assumption that coreboot executes
at EL3 official. If this ever needs to change for a future platform, it
would probably be cleaner to set the expected exception level in a
Kconfig rather than always probing it at runtime.
Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of
others that are all accessed through the raw_(read|write)_${register}()
family of functions. There's no reason why this register in particular
should have an inconsistent accessor, so replace all instances of
set_cntfrq() with raw_write_cntfrq_el0() and get rid of it.
Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 3 new Kconfig options:
DRAM_PART_NUM_IN_CBI
DRAM_PART_NUM_ALWAYS_IN_CBI
DRAM_PART_IN_CBI_BOARD_ID_MIN
These control whether to 1. attempt to use CBI at all 2. always use cbi
and 3. conditionally use cbi based on board id. The intent is that the
MIN variant would be used for the tranisition period then cut over to
ALWAYS after full transition. Since multiple OEMs have different
schedules these options are there to bridge the gap. yorp. bip, and
octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case
someone does the MIN values are 255 to always take the old path.
BUG=b:112203105
TEST=Set correct part number on phaser during testing.
Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Within procedure arch_write_tables, the pointer "rom_table_end" is updated
every time a table is created. However, after creating last table, pointer
rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;"
at the end to avoid the static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Within procedure save_bsp_msrs, the structure pointer "msr_entry" is updated
every time procedure save_msr() is called. However, after the last call of
save_msr(), "msr_entry" is not used, thus causing a static analysis error.
Add a "(void)msr_entry;" at the end to avoid the static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: If0fb336fbf49eec3da255fadbe38b3a38768d0cf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure.
It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for
this issue.
CLK[6:4]
CMD,DATA[3:1]
original register value: 0x6B
enhanced: 0x7F
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27816
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In procedure spi_flash_cmd_erase(), parameter "len" is not validated and
could lead to the return of an invalid (non-initialized) value. Validate
the parameter early on.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I0b5129a15c9e0ea45f4dba4ab0729196cb64699b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
RK3288 has always been notoriously low on SRAM, to the point where its
boards have less than 100 bytes left in both their bootblock/verstage
sections. This becomes a problem every time we try to add a tiny amount
of code to common coreboot interfaces that are included in them.
This patch manages to add another KB to each, one from the CBMEM console
(which now might get cut off a bit, but that's life) and one by moving
the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write
accesses must always be exactly 4 bytes long or they hang the CPU, so we
mostly ignore it... but thankfully, page table entries are exactly 4
bytes long and that's the only thing we write to this region, so it
works out in this case.
Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The implementation of wpcd376i in coreboot is based on the
superiotool output which apparently was incorrect. This
patch refines the implementation to match the datasheet.
Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Within procedure cea_hdmi_block, the variable "b" is used as an index into
a buffer of EDID bytes. At the end, it's incremented but not used, thus
causing a static analysis error. Add a "(void)b;" at the end to avoid the
static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: Ibd0b4a21bf82fcc46a627bc75564a850b7374989
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27929
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skylake SoC code now sets the icc_max based on the CPU SKU, so we
should not hard-code it in the device tree.
BUG=b:110890675
BRANCH=None
TEST=boots on atlas
Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
In procedure tpm_unmarshal_response(), variable "rc" is used early to
decide if it should return NULL. Later however, the code proceeds to its
end even if one subroutine reports error. If "rc" is not 0, report that
there was a partial error in the procedure.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I7575bc75104fd97f138224aa57561e68f6548e58
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a target is interrupted in the middle of writing an output file, the
file could be left in a corrupt state. A subsequent make invocation will
see the file as up to date and can cause very confusing errors.
BUG=b:112267918
TEST=Made a target fail before completion and verified make deleted the
output file.
Change-Id: I865827ea769b4dffa638d4324fc7284f6cb2ddc0
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the ability to specify the fwid version via a file instead of
via config. This makes it so when doing an incremental build all
objects are not invalidated when bumping the fwid.
The coreboot ebuild will create this file to pass the latest version.
BUG=b:112267918
TEST=ran dmidecide -t 0 and verified version was present
Change-Id: I955106efd648a75a1311f24ede46bd238d1517e0
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This configures the ACPI FADT perferred power management profile to
PM_MOBILE instead of PM_DESKTOP.
I'm not sure what impact this actually has. I just noticed the other
boards have it set.
BUG=b:110971913
TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config
Change-Id: Iea1b8359b80d167e69745358f543f025713294ba
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
By setting this register in bootblock AmdInitEnv will no longer trigger
a reset in romstage. This fixes a few vboot test failures and also
speeds up boot time.
BUG=b:111610455
TEST=Built grunt and made sure bootblock only happens once on cold boot,
and S3 resume.
Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Extend the existing reset handling features in Stoney Ridge to plan for,
and recognize, warm resets. The ColdRstDet bit is always zero on a cold
reset, and is intended as a mechanism for the BIOS to determine the type
of a reset that occurred.
Set ColdRstDet=1 after all cores have been initialized, so that any
subsequent reset may be identified as warm/cold. A later patch will check
the value during mp_init.
Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear. The generations should have the following
number of banks:
* Family 10h: 6 banks
* Family 12h: 6
* Family 14h: 6
* Family 15h: 7
* Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The DRAM part number can be stored in the CBI data. Therefore, add
support for fetching the DRAM part number from CBI.
BUG=b:112203105
TEST=Fetched data from CBI on phaser during testing.
Change-Id: Ia721c01aab5848ff36e11792adf9c494aa25c01d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The current call for saving dimm info passed the lpddr4_cfg and
memory sku id. In order to prepare decoupling the part number
from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(),
which explicitly takes the part number. The previous API now
uses the new one internally.
BUG=b:112203105
Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR
is the number of clock cycles the LPDDR4-SDRAM device uses to determine the
starting point of an internal Pre-charge operation after a Write burst with
AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to
be set to 24 clock cycles. The nWR field, though, is only in the GLK
FSP, so just update that field conditionally based on the GLK Kconfig
option.
BUG=b:112062440
TEST= build test
Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In procedure generate_cpu_entries(), the code was copied from code that
could change variables "plen" and "pcontrol_blk" based on number of cores.
This is not the case with stoneyridge (2 cores only), and there's no need
to use the variables. Remove them and replace with fixed values.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27877
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In procedure pci_get_resource, when setting an IO mapped base address,
variable attr is &= with PCI_BASE_ADDRESS_IO_ATTR_MASK. However, in this
particular code flow variable attr is not used later. Remove the line.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: Ia4fdda1be92d22017a7a913a911db15aaa440b69
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This implementation updates the chip select control register
programming in gspi controller setup call to program the correct
bit fields for chip select state.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/27889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
cache_sync_instructions() has been superseded by
arch_program_segment_loaded() and friends for a while. There are no uses
in common code anymore, so let's remove it from <arch/cache.h> for all
architectures.
arm64 still has an implementation and one reference, but they are not
really needed since arch_program_segment_loaded() does the same thing
already. Remove them.
Leave it in arm(32) since there are several references (including in SoC
code) that I don't feel like tracking down and testing right now.
Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch replaces the UART in the bootblock of SDM845 with a bitbang
implementation. Since SDM845 hardware UART needs a firmware blob loaded
into it before it becomes usable, it is not really suited for use in the
bootblock (since by the time we can read blobs from SPI, the bootblock
is essentially over anyway). This solution allows us to still have some
console output during early SoC initialization.
Change-Id: I0c252ec83a7993edce5c4debc687f1fdd0d7b36d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change bce49c2 (security/tpm: Improve TCPA log generation) missed
checking for NULL pointer before accessing the tcpa_table returned by
tcpa_log_init. This change fixes the boot hang observed on octopus by
ensuring pointer is checked for NULL before using it.
BUG=b:111403731
TEST=Verified that octopus boots up fine.
Change-Id: I2e46197065f8db1dc028a85551546263e60d46b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Upper Map section in the descriptor contains a database of flash
chips (VSCC Table). Its offset is located at a fixed offset from
the beginning of the image. ifdtool falsely calculates the offset
from the descriptor signature which has moved by 16 bytes with
step b of the Ibex Peak (5 series) chipset. This produces bogus
output for all chipsets older than that.
This patch corrects the behavior by calculating the offset of
flumap by adding 4096 - 256 - 4 to the start of the image.
Change-Id: I14f029fe702c129dfd8069a58fbd41113700f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Apparently they were introduced when refining ICH7 support when
porting Kontron 986LCD-M and then copied over to ICH9 and 10.
Change-Id: I2d9ece608955310d22b79574b9113a1521b2076c
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on,
it may cause damage on the GPIO pad.
To prevent, we would set this pad to GPO on romstage before EDP power on.
Since we need to cover all systems in market, I put it into romstage
instead of early_gpio_table.
BUG=b:111860510
BRANCH=poppy
TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on
Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds variant callback to get GPIO configuration table in
romstage and configures these GPIOs before memory training is
performed.
BUG=b:111860510
BRANCH=poppy
Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that an updated bootloader with important fixes is available at coreboot
repository, all stoneyridge boards should use it. Move the selection of
SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge.
BUG=b:111428800
TEST=Build and boot grunt.
Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27844
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds AML IccMax for VR configuration. From doc #594883, the
IccMax for Core was changed to 28A, we need this patch to accommodate
the changes. Besides, removes unused sku information from
sku_icc_max_mapping structure.
BUG=b:110890675
BRANCH=None
TEST=Remove icc_max from DT &
emerge-atlas coreboot chromeos-bootimage &
Tested with AML-Y and KBL-Y SKUs.
Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27610
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update power limit1 value from 8W to 10W. There is an error
in the energy calculation for current VR solution on GLK.
Experiments show that when power limit1 set to 10W, gained
performance improvement with SoC TDP reaches max (6W) power.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
setup_spread_spectrum is called in early_init, meaning the console is
not initialized yet. So you won't see boot block booting twice.
BUG=b:111610455
TEST=booted grunt and verified that AmdInitReset does not reboot. I had
AGESA patched to skip the JTAG check.
Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.
Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/27814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Grunt boards don't use SATA, so it should be disabled to save power.
Check if SATA is enabled in devicetree, and enable/disable the device
based on that setting.
BUG=b:112139043
TEST=Buil and boot grunt, checked the absence of SATA PCI.
Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Add Mailbox 3 driver
* Request brightness change through Mailbox 3
* Return Ones on error or if unsupported
* Mark existing code as legacy
(still required if no GMA driver is running)
* Call legacy code if Mailbox 3 is unsupported, on error or
if gma driver isn't running
Tested on Lenovo T430:
* Brightness control still works
* Brightness is the same on S3 resume
Change-Id: I51554c819148336b204d28972cbf775a10c3fb8a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Make tcpa_log_init static and move init code into
the tcpa_log_add_table_entry routine.
* Add more checks for log initialization.
* Fix minor issues
Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the return type of gpio_base2_value() and related
functions from int to uint32_t. This makes more sense now that
board_id() and related functions (which are the primary use case) also
return that type. It's unlikely that we'll ever read a strapping of 32
GPIOs in a row, but if we did, we'd probably want to treat it as
unsigned.
Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9. This code is based on the output of autoport.
The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 4601).
This board works well under coreboot. A list of what works and what
doesn't can be found in the documentation part of this commit. To
summarise: the only known issues are that S3 suspend/resume doesn't
work, and that there is no automatic fan control via the super I/O.
Change-Id: I2a0579f486d3a44de2dd927fa1e76b90c3b48f62
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse.
This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and
4.17.8. In each case, the PS/2 mouse works automatically, whereas it was
not detected before.
Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the
following remark: "Control Method should be made Serialized (due to
creation of named objects within)". Making the appropriate methods
Serialized eliminates these remarks.
Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27796
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposing the parallel port via ACPI causes Linux to automatically detect
the parallel port and load the appropriate modules. Tested on an ASUS
P8H61-M LX with Linux 4.9.110 and 4.17.8.
However, no parallel port device has been tested.
Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Commit ef8c559e53
[nb/intel/sandybridge/report_platform: Move remaining code to sb folder]
moved reporting code to the southbridge, but missed a reference in the
non-default MRC raminit path (so testing missed it).
Remove invalid reference to fix compilation error.
Test: build google/link with MRC raminit option selected
Change-Id: I270a95ac53fbc9f8792f375908cf91585261f6a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment.
Clean up the code paths by employing CAR_GLOBAL for the global state
which allows the same code to be used in all stages.
Change-Id: I08fd1795508f76abdab1618585366bf9d06482ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.
Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.
Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes sure we deassert the USB hub reset pin so the hub will
work with the next board revision that drops the external pull-up.
(Actual USB support comes in a later patch.)
Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27790
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check if an argument is given and if not print the usage.
Check if all arguments are handled by getopt and if not print the usage.
Change-Id: I40dbd2a51d018eb549e9b2fa4365b3e4f9355bff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.
BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.
Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
Verify that suspend/resume and consecutive reboots are working
Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]
coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.
TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.
Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]
The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.
TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.
Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from chromium commit ee7a150
[Strago: do not hardcode virtual interrupt numbers]
Instead of hardcoding virtual interrupt numbers that may change as
the kernel changes, use GpioInt() resources to describe keyboard,
touchpad, and touchscreen interrupt lines.
TEST=Build and boot several cyan variant boards, verify keyboard,
touchpad and touchscreen work with newer kernels (4.14+).
Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iecfb45be433249d274532eb746588483fedb3f52
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To install this hook, run
make install-git-commit-clangfmt
This will install a pre-commit-msg hook that runs clang-format
on all .c and .h files that are staged.
It will add a clang-formatted-by: <git username>
line to the commit message to indicate that clang-format
was run on the files and that further processing of them
is not needed.
Change-Id: I1773f55b5b4677dad8f4bea017b6328fd93df20c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27779
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This effectively means it is possible to run another bootblock located at
top_of_flash - 64K.
The i82801gx southbridge has the ability to swap the two top 64K ranges by
flipping the BUC.TS bit (RCBA[3414] bit0).
This allows coreboot to build roms with a bootblock at the top swap offset by
selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK.
Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
src/arch/riscv/stages.c is an entry of romstage/ramstage, and does not
needs to be bootblock.
src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some
compile/board/time information, which is repeated with src/lib/version.c
Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27557
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2 bits of LPC host control were originally not public, and wrongly
identified as IMC related. Now that the bits are available in public BKDG,
fix the naming of the bits.
BUG=b:111912080
TEST=build and boot grunt.
Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27744
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings. Tested on Vayne and Akali.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch contains the parts that changed the hash of the generated binary;
probably due to the compiler optimizing things slightly different.
Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27725
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: I598b056d5fb1ce23b390b2f0ab4e9fb242d3685a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27242
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27243
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Iabfd15884ec8feb846d01b6af3c4afe5c1494feb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27245
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pci ops happen to work on this struct device since the device_path is an union.
This patch still keeps adding the fixed resources in the pci_domain
ops since moving it to the PCI ops which could properly use the
function argument for PCI operations would require all PCI IDs to be
added or else breakages are to be expected.
Change-Id: Id73c16fad4fb9ece78595844a39da993d169f057
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27244
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change f849972 (security/vboot: Enable TCPA log extension) enabled
support for adding TCPA log to CBMEM. However, if CBMEM is not online,
this function doesn't do anything and returns early. This condition is
not really a valid error condition as it depends on when the call to
tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry
returns -1 when cbmem is not online, tpm_extend_pcr prints an error
message with prefix "ERROR:". This can confuse any scripts trying to
catch errors in boot flow.
This CL makes the following changes:
1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry
already prints out appropriate ERROR messages in case of failure to
add log entry.
2. Since the return value of tcpa_log_add_table_entry is not used
anymore, return type for tcpa_log_add_table_entry is changed to void.
BUG=b:112030232
Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This never got enabled for fleex; we should enable this to make it
easier to have updated EC firmware.
With this commit, here's the relevant console messages:
sync_one_ec: devidx=0 select_rw=4
update_ec: Updating RW(active)...
Trying to locate 'ecrw' in CBFS
update_ec: image len = 137580
EFS: EC is verifying updated image...
send_packet: CrosEC result code 1
EFS: EC doesn't support EFS_VERIFY command
vboot_hash_image: No valid hash (status=0 size=0). Compute one...
print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd
Trying to locate 'ecrw.hash' in CBFS
sync_one_ec: jumping to EC-RW
send_packet: CrosEC result code 12
EC returned from reboot after 27753us
BUG=b:112038021
TEST=Successful boot after EC update via sync
Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When I tried to compile the RISC-V code (202e7d4f3c), I found some errors:
`PRIu64` is undefined
src/arch/riscv/timestamp.c does not exist
Currently RISC-V does not have the implementation and use of timestamp,
so I temporarily delete the code related to timestamp in the Makefile.
And define PRIu64.
Change-Id: I7f1a0793113bce7c1411e39f102cf20dbadda5d6
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix 6 new errors found by shellcheck 0.4.6
SC2155: Declare and assign separately to avoid masking return values.
4 x SC2086: Double quote to prevent globbing and word splitting.
SC2196: egrep is non-standard and deprecated. Use grep -E instead.
One of the SC2086 errors is masked because it needs word splitting.
Change-Id: I7f869e6d208f7247f739619c538be6075b802719
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
- Use TARGET variable for location of passing/failing boards files.
This should better handle the directory, wherever it is.
- Don't save make.log location if make.log is being deleted.
Change-Id: I28e55feef85c9b642ac5ff70ecef113cf7978707
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The careena board requires a different setting within VBIOS in order to
pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS.
CQ-DEPEND=CL:1153080
BUG=b:111673328
TEST=Verify, via SOME unspecified method, that the new vBIOS is built into
the Grunt/Careena ROM files.
Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27643
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per AMD, the Integrated Micro Controller is not a supported feature of the
Stoney Ridge APU. Systems are expected to implement an external EC for
desired features. Remove all stoney IMC files and functions from vendor code.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27652
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per AMD, the Integrated Micro Controller is not a supported feature of the
Stoney Ridge APU. Systems are expected to implement an external EC for
desired features. Remove IMC files and functions from gardenia.
BUG=b:111780177
TEST=Build gardenia
Change-Id: I570b7f8e364b0c2937592590cc033d5a6c9fade0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27650
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes i82801ix use the common smm southbridge code to set up smm
relocation and smi handler setup. This is needed in this change for the
the smm relocation code relies on some southbridge functions provided
in the common code. Some of the old code is kept for the Q35 qemu
target.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since this needs
the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled
properly in the subsequent parallel mp init patchset.
Tested on Thinkpad X200: boots and going to and resuming from S3 still
works fine.
Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.
This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.
Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Store the power on defaults in the _REG method after the ERAM region
is ready for use. It might not be ready when accessed from _INI.
Tested on Lenovo T430.
Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, AGESA environment needs eDP high vdiff enabled.
BUG=b:111673328
TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and
boot grunt. Add new code to grunt, build and boot, verify eDP changed.
Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, create code that allows changing eDP training parameter.
BUG=b:111673328
TEST=Tested in child patch.
Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers. Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).
I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?
Some of the _UIDs are also duplicated. This change makes them unique.
A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.
Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]
We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE)
We need to reduce this time to below 100ms for caroline device.
BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete
Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.
BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None
Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 4 helper functions to get microcode info.
* get_current_microcode_rev
return the the version of the currently running microcode.
* get_microcode_rev
extract microcode revision from the given patch.
* get_microcode_size
extract microcode size from the given patch.
* get_microcode_checksum
extract checksum from the given patch.
The simpler thing would be to just move the struct microcode
to microcode.h so that the structure members can be dereferenced.
To encapsulate the structure details added the helper functions.
This information will be used in future to compare microcodes for update.
Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RTC BUC control register provides a software interface to
configure the top swap feature. This patch adds implementation
to enable/disable top swap feature and gets it accessible in
romstage as well.
The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP
is selected.
To use the topswap feature a second bootblock has to be added
to the cbfs. Below configs aid in doing that,
INTEL_HAS_TOP_SWAP
INTEL_ADD_TOP_SWAP_BOOTBLOCK
INTEL_TOP_SWAP_BOOTBLOCK_SIZE
Enabling and Disabling topswap, using the added API enables user
to boot alternatively from either bootblock.
Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/25805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable nocturne to wake from lid attach/detach events.
BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.
Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For unused pins, configure them as GPIO input and use the default
termination. For the pins where board has an external termination,
remove SOC's internal termintation.
BUG=b:110654510
TEST=On Bip, flashed image and verified that it boots to OS. Also
executed a few suspend resume cycles.
Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These two da7219_aad properties are optional:
- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
[<2800>, <2900>]
- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
When the Mic Bias Higher Voltage feature is not required, firmware should
just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time
properties.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:111700809
TEST=On grunt:
No "Invalid micbias pulse level" in dmesg
Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9
Reviewed-on: https://review.coreboot.org/27613
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression introduced in commit f18dc5c7
"Add TCPA logging functionality":
Introduced TCPA log got overwritten in acpi.c of x86/arch, due to
CBMEM name collision. Use a different cbmem name to have two independent
TCPA logs.
Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.
We would set GPP_D21 to high to change LTE tx power to normal mode as
default.
BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default
Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All of the other SPDs are padded with spaces to make them use the full
size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not,
and that seems to be causing problems with some tools.
BUG=b:111903749
TEST=Mosys correctly identifies memory on board using that SPD.
Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
The rewrite simplifies the code and fixes the limit on the case of IO resources
with the length of 1 byte.
This patch is inspired by the comment of Nico Huber on
Ia99b785dcd9cf56fb236ad7ade54656851f88a5e
If the ones in the mask aren't a continuous block, now a warning message gets
printed.
Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Commit 74203de
"intel/sandybridge: Don't hardcode platform type"
changed the MRC layout.
Bump the version to prevent a boot error, if the cache isn't
cleared on flashing a new coreboot version.
Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27712
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A variant might talk to the EC to get board id in order to identify the
right GPIO configuration. Thus it is important to ensure that the LPC IO
windows are configured before this. This change moves the call to
perform EC init before configuring bootblock GPIOs.
BUG=b:111933657
TEST=Verified that reading board id does not fail on phaser.
Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27671
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add a function to return CPU platform ID bits
* Add a function to return platform type
** Platform id is 4 on Lenovo T430 (mobile)
** Platform id is 1 on HP8200 (desktop)
* Use introduced method to handle platform specific code
* Use enum for platform type
* Report platform ID
Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add internal graphics device 00.01.00 to the ACPI tables so that the
ACPI PCI option ROM save functions have a proper scope to save the
ROM to.
BUG=b:111697181
TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"
and check _ROM method is added in the SSDT1.
Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Additional diagnostic information about the EC and the most recent
reasons why it has reset the AP are read out and logged via printk.
This may aid in debugging spurious hangs and/or resets on the AP by
providing traceability to the EC when it triggered the reset. Merely
knowing that the EC was also recently reset may provide valuable
intelligence. See also https://crrev.com/c/1139028.
Change-Id: Ie6abe645d5acefb570b9f6a3c4a4b60d5bcd63cd
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://review.coreboot.org/27621
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update ec_commands.h to be a verbatim copy of upstream, except retain
the complete copyright notice found in coreboot's copy. Upstream refers
to a file not present in coreboot.
Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://review.coreboot.org/27620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets SPI flash related configs and inits SPI bus 1 to
support SPI NOR flash.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since we move mtk_mmu_init() from bootblock to decompressor, we don't
need to build mmu_opertations.c in bootblock and we don't need to
include <soc/mmu_operations.h> in bootblock.c.
BUG=b:80501386
TEST=manually flashed into kukui and boots into romstage.
Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Since ops was passed as override in the pnp_dev_info struct, the generic
pnp_ops that was passed to pnp_enable_devices was never used.
Change-Id: Ic35a232a9867936d3d84aa275ae50e3e3dd9bf97
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27396
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ops was passed as override in the pnp_dev_info struct, the generic
pnp_ops that was passed to pnp_enable_devices was never used.
Change-Id: I59eb60efeefcdbe8b2dc08e17453cf95bdfd39b1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27395
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ops was passed as override in the pnp_dev_info struct, the generic
pnp_ops that was passed to pnp_enable_devices was never used.
Change-Id: I10e2c6da0043eb291a8c6266b251054dbe599653
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27393
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicate FMCN package for I2C2, since already generated by
the devicetree-linked generic i2c driver. This fixes an ACPI parsing
error which resulted in the touchpad and touchscreen being non-functional.
Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and
touchscreen functioning properly, no ACPI errors in dmesg.
Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change provides override GPIO table for variant phaser depending
upon the board id. Additionally, early_gpio_table is also provided for
phaser since EN_PP3300_WLAN needs to be handled differently based on
board id.
BUG=b:111743717
TEST=Verified that GPIO configuration for the override GPIOs is
different than before with this change.
Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates mainboard_init to call
gpio_configure_pads_with_override instead of gpio_configure_pads to
allow variants to provide overrides for the GPIO config table provided
by the baseboard.
BUG=b:111743717
TEST=Verified on phaser that GPIO config with and without this change
is the same.
Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function adds support for gpio_configure_pads_with_override
which:
1. Takes as input two GPIO tables -- base config table and override
config table
2. Configures each pad in base config by first checking if there is a
config available for the pad in override config table. If yes, then
uses the one from override config table. Else, uses the base config to
configure the pad.
This is done to allow sharing of GPIO tables across baseboard-variants
for various boards i.e. Each board can have a base config table which
is provided by the baseboard and an optional override config table
that can be provided by a variant to configure certain GPIOs
differently. It is helpful when the variant GPIO diff list is not very
huge compared to the baseboard.
BUG=b:111743717
TEST=Verified that the GPIO config for phaser is same with and without
this change.
Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The next build for phaser swapped the gpio for the touchscreen
enable. In order to support previous builds the devicetree needs
to be updated at runtime based on board revision id.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I45ef05ea0b991d04d5bf410cd7a175913bf0bf5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27638
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The variants of the octopus family have their own schedule and needs
for modifying settings based on the phase of the build schedule while
also needing to maintain support for previous builds. Therefore, utilize
the SoC callback, mainboard_devtree_update(), but just callback into
the newly introduced variant_update_devtree(). The indirection allows
for the ability to move the call around earlier than the
mainboard_devtree_update() if needed while maintaining consistency in
the naming of the variant API.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: If1c2f60cabe65b5f1c6a04dd60e056e50c4993df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add a function, dev_bus_each_child(), which walks through all the
children for a given bus of a device. This helper allows one to
walk through all the children of a given device's bus.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: Iedceb0d19c05b7abd5a48f8dc30f85461bef5ec6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The variant_board_id() API was never used on octopus because all
boards in the octopus family used the EC to get board id, i.e. they
all use EC_GOOGLE_CHROMEEC_BOARDID. Therefore, remove the code
and declarations so as not to cause confusion.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I4f9a24b46dd4262120075d3d42daf22015a3dd50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch makes it possible to enter the config mode of the super IO chip, so
that changes can be made to the configuration registers.
Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Since ops was passed as override in the pnp_dev_info struct, the generic
pnp_ops that was passed to pnp_enable_devices was never used.
Change-Id: Id09c6cffb9a0cbbd9189c18801121449c9504422
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27394
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bus width has to be encoded where the lower 3 bits are the bus width
in multiple of 8 and the following two bits give the error checking
bits in multiple of 8.
Hardcode to 64 bit as done on haswell.
TODO: Make it dynamic once there's ECC support.
Change-Id: I3b83a098205455b1c820d0436c6984938f261466
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On desktop boards the PPD bit of MRS register MR0 is set and thus
DLL_Off mode shouldn't be used, as enforced by datasheet
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1.
Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Libgfxinit provides a better alternative to the native C init. While libgfxinit
mandates an ada compiler, we want to encourage use of it since it is in much
better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I9228fa7eadfe2a827c1f4de9d6710b60d3f1b121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
A fully functional bootblock (that can boot into verstage or romstage)
is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK)
is enabled, only 25088 (66%) bytes are needed.
Inspired from crosreview.com/1070018.
BUG=b:80501386
TEST=manually flashed into kukui and boots into romstage.
Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w
BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.
Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables p-states for nocturne which was disabled by commit
de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states
feature was disabled as a temporary work-around as system was getting
hung while booting up. Now with IMVP7 firmwware turning and hardware
rework the issue is not seen, so its safe to enable p-states.
BUG=b:79666828
BRANCH=none
TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage"
, flash spi image onto nocturne, boot to kernel and verify device stays
alive and responsive for several minutes without locking up.
Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27257
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig options to not build the Arm Trusted Firmware, but use
a precompiled binary instead. To be used on platforms that do not
have upstream Arm Trusted Firmware support and useful for development
purposes.
It is recommended to use upstream Arm Trusted Firmware where possible.
Change-Id: I17954247029df627a3f4db8b73993bd549e55967
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
For unused pins in octopus baseboard, configure them as GPIO input
and use the default termination. For the pins where board has an
external termination, remove SOC's internal termintation.
BUG=b:110654510
Change-Id: I67ec62913b0ef47105289838218f5d74c004223c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from APL
and relies completely on the fixed hardware power button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works as expected
on octopus.
Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.
Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set tREFIx9 to 8.9*tREFI/1024 as suggested in
xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1.
Use the minimum value of REFI*8.9 and tRASmax as suggested by
3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9.
Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I42469c844074db57071d0191d12d8fd64f462672
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I5bd525532c01b3b9f7ddbc8eab42caa8b7f30795
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: Ic6387032e043b6ad9e9ceefd2fcc1cdf843e2989
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When extracting a payload from CBFS, ignore compression fields for
these types of payload segments:
- PAYLOAD_SEGMENT_ENTRY
- PAYLOAD_SEGMENT_BSS
- PAYLOAD_SEGMENT_PARAMS
These types of payload segments cannot be compressed, and in certain
cases are being erroneously labeled as compressed, causing errors
when extracting the payload.
For an example of this problem, see creation of PAYLOAD_SEGMENT_ENTRY
segments in cbfs-mkpayload.c, where the only field that is written to
is |load_addr|.
Also, add a linebreak to an ERROR line.
BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs extract -m x86 -n payload -f /tmp/payload -v -v
Change-Id: I8c5c40205d648799ea577ad0c5bee6ec2dd7d05f
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27520
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coolstar's custom touchpad drivers for Windows require level triggering,
and the Linux drivers don't care/perform identically either way. Set
touchpad interrupt to level trigger, matching change made to other
Chromebooks.
Test: boot Windows 10 on google/chell, verify touchpad functional
Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Explicitly enable VMX, as some OSes (eg, Windows) need VMX
feature enabled and locked in order to fully support virtualization
Test: boot Windows 10 on google/chell, verify OS reports virtualization
enabled
Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Configure SuperIO on shutdown to keep devices enabled, set green LED
to fading on sleep and normal on wake.
Add SSDT to write LDN4 IOBASE addresses stored in devicetree.cb.
Tested on HP8200:
* Wakes from power button or USB keyboard.
* LED is fading
Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This fixes most of the simpler shellcheck errors in shellcheck 0.4.6.
There are still a few warnings left that weren't simple to fix or
would have required more testing before I was confident in them.
Change-Id: I79ab3614cc1d69d3dfe1e0374e930313f2011cbf
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add the Do-not-assume-glibc-glob-internals patch to fix segfaults.
- Update glob_interface_v2 patch to the patch directly from the
make git repository instead of translating it. This gives better
attributution to the original author.
Change-Id: Ibc936fc00925a4ca2170a6f5dca7c2b8d8d62f02
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Exclude build flags that generate warnings when scanbuild is running
- Add the SCANBUILD_ARGS variable to abuild so we can pass in arguments
to scanbuild.
- Set the default scanbuild argument to -k (--keep-going) so that even
if an error occurs it continues with the scan. This is similar to what
we do with coverity runs.
Change-Id: I82e7c13d7fd7432b43c17a31834ec82fca158a07
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change adds variant rammus derived from baseboard poppy.
The setting is copied from the poppy and will be modified later
BUG=b:111579386
BRANCH=master
TEST=emerge-rammus coreboot
Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable fast or extended DRAM test based on devicetree setting.
The fast DRAM test takes less than a second, while the
extended runs about 1 minute.
Tested on Cavium Soc.
Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This change provides implementation of smbios_mainboard_sku
that queries the EC for SKU ID using CBI. Currently,
get_board_sku() is implemented as a common function for all
variants since this is the only way used by all the octopus
variants to query SKU ID. If this changes in the future,
this function can be changed to a variant_* callback.
BUG=b:111671163
TEST=Verified following on phaser:
1. "mosys platform sku" returns the SKU ID programmed in CBI
2. "dmidecode -t 1" shows SKU information as "skuXYZ" where XYZ
is the SKU ID programmed in CBI.
Change-Id: Ic0d344b3c13632f2ca582adc36aa337b99959712
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This board is quite similar to the other ones in this dir an can be
supported with little code changes.
TODO what works:
* DDR2 dual channel PC2-6400;
* SATA;
* USB;
* Ethernet;
* Audio;
* Native graphic init;
* SuperIO Sensors;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot);
TODO how tested:
Tests were run with SeaBIOS and Debian stretch, using Linux 4.9.65.
Change-Id: I6844efacaae109cf1e0894201852fddd8043a706
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Both g41c-gs and g41c-s can be supported by the same code since the
only difference is ethernet NIC.
What is tested:
TODO: components
How tested:
TODO: payload + OS
Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enable DW9807 NVM support by adding required ACPI code
BUG🅱️110815821
TEST=On Nautilus board, execute "cat /sys/bus/i2c/devices/i2c-INT3499:00/eeprom"
in the terminal and see if there is any data to be dumped.
Change-Id: Ib83fa1a522402a59566e3f55fa5c1af4490266e4
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route,then
abnormal over-current is asserted on USB type-A port.
It causes USB type-A port to be blocked, so we need this internal pull-up.
BUG=b:111578984
BRANCH=poppy
TEST=Verified over-current not triggered abnormally on basic sku board
Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27413
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert Skylake reference board glados to variant setup in
preparation for merge with existing Skylake boards chell and lars,
and upstreaming of new boards asuka, caroline, cave, and sentry.
The following changes have been made:
- move DPTF to variant subdir
- move non-common EC defs to variant subdir
- adjust Kconfig for variant setup
- move non-common NHLT config to variant Kconfig
- make non-common NHLT ACPI code conditional
- move devicetree to variant subdir
- move board GPIO defs to variant subdir
- move board PEI data to variant subdir
- move SPD index calculation to romstage so available for
dual-channel determination during PEI for boards which need it
- move SPD compilation to variant makefile
- add weak function for determination of dual-channel RAM
- add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants
can override and power down rails as needed
Test: build google/glados
Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the GEO SAR feature for nocturne. OxM programs wifi_sar VPD key in factory.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:65155728
BRANCH=none
TEST= Set the wifi_sar VPD with below command (values are junk for test purpose only,
actual values would be set be OxM)
sudo vpd -f <coreboot.rom> -s wifi_sar=30313233343536373839303132333435363738393030313
24142433435364445463031324142433400364445463031323343444546303132333435
Flash the <coreboot.rom> and boot to kernel. Get ACPI table and WGDS would get created
with VPD values passed in.
Change-Id: I32ad591f15fdb34704c8d98d98646dfa2d8882ff
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch implements gpio_set_pull() and links the common MediaTek
GPIO code to support IO config for other drivers (ex. SPI) and the
requested functions in src/include/gpio.h.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/27417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The write_tables function was void. It is a bit more
useful for loading payloads from the romstage
if it returns a pointer to the table it creates.
Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27537
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We don't block commits for failing checkpatch in gerrit, and we
shouldn't block them here. This allows checkpatch to still run, so
users can see the issues, but won't prevent the commit.
Adds a delay if checkpatch fails so that the issues can be seen.
Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Implement ACPI S3 resume control to restore the state before entering
sleep.
* Store the requested state wake state for bluetooth and WWAN.
* Add new methods to init the state and apply the requested state on wake.
* Call the new method on all devices.
Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Add support for secure/unsecure split
* Use MMCONF to access devices in domain0
* Program MSIX vectors to fix a crash in GNU/Linux
Tested on Cavium CN81XX_EVB.
All PCI devices are visible.
Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25750
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures.
* Always compress kernel Image using xz
* Create FIT uImage containing the kernel, initramfs and DTB
* Add ARM64 defconfig for all SoCs
Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add support for SMBIOS table 'IPMI Device Information' and use it on
HP Compaq 8200 Elite SFF.
Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans
for IPMI compatible devices.
Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25386
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This config is used to provide the name of a region where a microcode
is located. The address of this will be added as the first entry in
the FIT of the topswap bootblock.
This adds a capability to associate two microcodes for each
of the two bootblocks, this allows for the CPU to boot with different
microcodes with 2 separate bootblocks.
Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Intel PCH/Southbridges have feature that it is possible
to have the southbridge/PCH look for the bootblock at a 64K or
128K/256K/512K/1MB (in case of newer SoCs) offset instead of
the usual top of flash.
Add configs to create a second bootblock and configure its size.
Change-Id: I4bbd19c35871891b762a0673f840858d972e129e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some types of payload segment headers do not use all fields.
If these unused fields are not initialized to 0, they can
cause problems in other software which consumes payloads.
For example, PAYLOAD_SEGMENT_ENTRY does not use the compression
field. If it happens to be a non-existent compression type,
the 'cbfstool extract' command fails.
BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86
cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v
xxd tianocore.cbfs | head # visually inspect compression field for 0
Change-Id: I359ed117ab4154438bac7172aebf608f7a022552
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was updating flags for ALL architectures, not just riscv.
That was bad, and gave us errors, although they weren't fatal for
some reason:
i386-elf-gcc: error: missing argument to '-mcmodel='
i386-elf-gcc: error: missing argument to '-march='
i386-elf-gcc: error: missing argument to '-mabi='
This issue started from commit 5fed693a (riscv: add support for
modifying compiler options)
Add comments to the other 'endif' statements since they're now
surrounded by a global ifeq
Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The linux trampoline was modifying the existing GDT
to add the 0x10 and 0x18 descriptors for Linux.
This will not work when the existing GDT is in ROM.
Change the code to set up a new GDT in what we know to be
RAM.
Tested by booting a linux payload. The main reason this works
is that Linux almost immediately loads its own GDT and then
segment registers. This GDT is a very temporary bridge.
Note that none of this change used to be necessary; the coreboot
GDT was originally compatible with Linux (ca 2000);
then Linux changed.
Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
busty workloads like Octane, Aquarium on open yorp board with heat sink,
sometime CPU temperature spikes till 99 degree Celsius and DPTF
initiates system shutdown. With reference to previous APL/reef/coral
platforms, this updates 105 degree Celsius for the CPU critical
temperature trip value to avoid shutdown. This patch also updates power
limit1 value to avoid the abrupt thermal shutdown by DPTF.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.
Note: This currently does not appear to have any effect on grunt.
BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff
With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1
Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We should use active-state power management where possible to reduce
power consumption during normal operation. Enable these options.
Linux does not seem to enable this for AMD, and the Intel code in coreboot
does enable these options.
PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it.
BUG=b:110041917
TEST=boot on grunt, see that WiFi and eMMC still run OK
Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27464
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This creates a meep variant for octopus.
The devicetree overrides are copied from yorp, otherwise everything
just defaults to baseboard settings.
BUG=b:111543000
TEST=None
Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pass the address of the chip-specific ops struct instead of the one of
the generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I0c820254e97e3f80470d148552af06940e147b74
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.
Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Even though we were setting V=1 in the build, this wasn't getting passed
to abuild, so the builds there didn't have additional debug information.
That made it difficult to debug issues on the builder. This sets the
verbose flag for abuild if V=1 is set.
Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.
BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.
Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add comments on the ops handling in pnp_enable_devices function and the
pnp_info struct.
Also remove the negation in the check if an LDN-specific override is used.
This patch doesn't change the logic though.
Change-Id: I3e80dbce1f29ee3e95e3b1d71c9b8479561d5c1a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Move vboot/tpm specific implementation to vboot.
* Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set.
* Preparation for software hash function support, no logic changed.
Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.
Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.
BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.
Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Extracted from the stock UEFI using UEFItool & intelvbttool.
Without it, the kernel complains about the missing VBT table.
Additionally, the invalid oprom signature warning given by i915
is also gone.
Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844
Signed-off-by: Pablo Moyano <42.pablo.ms@gmail.com>
Reviewed-on: https://review.coreboot.org/27482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Because earlier versions of debian set /dev as a standard tmpfs
filesystem, that was a simple place to build. Now, this has been
changed and /dev isn't a standard tmpfs that will grow to 50% of
memory. It's a fixed, very small size, and can no longer even be
resized.
Because of this, create a new directory to build in and add it to
/etc/fstab. Mount it when the container is started.
As long as we're at it, make the other build directories (ccache
and slave-root/workspace) tmpfs as well. The builders we're using now
have plenty of memory, so don't write any of the files to disk.
Update the Makefile to get rid of all references to ccache directory.
Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix an undefined reference error with GCC 8.1
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.o: In function `bdk_dram_get_size_mbytes':
/home/coreboot/slave-root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-test.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-init-ddr3.o: In function `init_octeon3_ddr3_interface':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk/libdram/dram-init-
ddr3.c:7550: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-l2c.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
make[1]: *** [src/arch/arm64/Makefile.inc:119: /cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/cbfs/fallback/romstage.debug]
Error 1
Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The BDK config subsystem can't store values in romstage.
Read frequency from DDR memory controller instead from
BDK config.
Fixes memory info showing always 0 MT/s.
Change-Id: Iaee33e57e27ca182f41be923cf950868f66d3638
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27451
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the backlight in the OS callback to SMI for APMC. This keeps
the backlight off until the OS is ready to display something.
BUG=b:72694972
TEST=Backlight turns on at ChromeOS splash screen
Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This device claims to run at 75MHz with dual read, but it is not always
reliable. Add an option to change the SPI flash speed to 16MHz, to avoid
any problems.
BUG=b:111363976
TEST=manually try to get my em100 running (it doesn't yet)
Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This applied to AMD devices as well as Intel, although the mechanism is
different. Move the option to a common place.
BUG=b:111363976
TEST=USE=em100-mode emerge-reef coreboot
See that a message appears:
* Enabling em100 mode (slow SPI flash)
Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD
BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.
Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enabling of TBMC device on AP side requires corresponding support on the
EC side as well. Since not all octopus variants have tablet mode support
enabled, this change enables TBMC device only for phaser.
BUG=b:111264961
Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.
Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.
BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.
Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to get better performance, map dram as cached after dram ready
in romstage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Need a futher check after dram
calibration code ready.
Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27304
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable MMU in bootblock for performance, link common code to provide
mtk_mmu_after_dram() to update MMU table in romstage after dram ready,
implement mtk_soc_disable_l2c_sram(), and call
mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.
Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add an extra space after 8th value on each line to make it easier
to count the values.
Update the empty spd to remove two random 0x80 values.
BUG=None
TEST=None
Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27423
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to BKDG for AMD Family 16h Models 30h-3Fh Processors
SDR50 tuning should be disabled in 0xA8 register.
Also fix clock frequency setting in 0xA4 for stepping >= A1
which caused reduced performance of SD cards transfer speed
even by half.
Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As *None* is special and not a payload, it makes sense to put it at the
top. Also, it was at before the latest addition of the FIT payload
choice.
Fixes: a892cde6 (lib: Add FIT payload support)
Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Configure and enable MMU.
* Cover the whole I/O space.
* A minimum of 512KB TTB space is required.
* Use secure mem attribute as firmware is running in ARM TZ region.
Tested on Cavium SoC.
Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Convert Cavium's BDK devicetree blob to a static C file.
The resulting file must be included in mainboard folder to provide
board specific configuration values to BDK functions.
Example call:
python devicetree_convert.py --in sff8104.dtb --out bdk_devicetree.c
Change-Id: I76a5588aefe4f680228eca46a0e4dba7e695931c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26228
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config ISH in SOC side by checking if ISH device is turned on.
"IshEnable" is not needed anymore since ISH device on/off will tell
if ISH should be enabled or not. "IshEnable" will be removed from chip.h
in separate CL.
Atlas board specific ISH setting is needed, which is committed in
separate CL.
BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.
Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Add SSDT generator to add dynamic ACPI code.
* Implement GBDC and SBDC for thinkpad_acpi kernel module.
Required for BDC power control from userspace.
Tested on Lenovo T430:
The bluetooth module is detected and can be powercycled using network manager.
Change-Id: Ida825196650966194a883945896a038b0790fe45
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In Windows Cygwin enviroment, compiler reports
redefinition error at cbfstool/ifwitool.c
on _packed and __aligned.
Skip new defines when vales are already defined.
Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GCC pre-defined some macros for detecting ISA extensions.
We should use these macros to detect ISA features.
Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475
Signed-off-by: XiangWang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Move the APCI HKEY device to a new file and include it.
The follow-up commits will extend it and this way it remains readable.
Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is
defined as IRQF_TRIGGER_LOW, so do not invert it twice.
BRANCH=poppy
BUG=b:78613978
TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not
increment wildly.
Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/27221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SeaBIOS 1.11.2 was tagged with the following changes:
```
f9626cc cbvga_set_mode: refine clear display logic
f88297a qemu: add qemu ramfb support
a2e4001 vgasrc: add allocate_pmm()
17b01f4 pmm: use tmp zone on oom
44b17d0 bochs_display_setup: return error on failure
4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator.
dd69189 cbvga_list_modes: don't list current mode twice
5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140
961f67c qemu: add bochs-display support
767365e cbvga: factor out cbvga_setup_modes()
7906460 optionrom: enable non-vga display devices
```
Tested by running it on a Thinkpad X230.
Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Tested-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/27326
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `files-in-dir` macro is supposed to return all files (out of a
given set) that reside directly (non-recursive) in a given directory.
While the current solution worked splendidly, we can achieve the same
without recursive macros that look at each parent dir individually.
Beside providing better readability, this also fixes a future make
error, as make doesn't like the variable name ` ` anymore ;)
Change-Id: Iac0eacdf91b8b5098592ad301c1f3fdb632454e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/27324
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It can not emit byte data without BytePrefix.
design to:
Or (Local5, GPIO_PIN_OUT, Local5)
error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means
nothing in AML spec.
so it will include next emitted string in Or:
Or (Local5, Local5, \_SB.GPW2)
fix:
Store (0x40, Local0)
Or (Local5, Local0, Local5)
BUG=b:110962003
BRANCH=master
TEST=emerge-grunt coreboot
extract SSDT then check ACPI syntax is correct
Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since SeaBIOS 1.11.0 implements serial console and etc/sercon-port
runtime config file is present in CBFS, SeaBIOS additionally
redirects iPXE output to configured IO port. For boards which use
the same UART for SeaBIOS and iPXE console it causes doubled
output.
The option is enabled by default and passes UART configuration
to iPXE Makefile as before. When unselected, only SeaBIOS handles
printing output from iPXE.
Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since none of the boards using chromeec select DRIVERS_PS2_KEYBOARD
now, there is no need to call pc_keyboard_init anymore. This change
gets rid of the call and adds an error message in case any mainboard
using chromeec tries to select this config.
BUG=b:110024487
Change-Id: Ia0b56abe0a5990e527277eaf3397e00dccda3e50
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the
keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the keyboard
in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
TEST=Keyboard works fine after booting to OS even if user hits keys
during BIOS to OS handoff.
Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Useful for debugging or for cases where we need to enter SMM.
Probably should be moved to commonlib or libpayload.
Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clang doesn't know the warning `packed-not-aligned`, so only add it
when GCC is used.
error: unknown warning option '-Wno-packed-not-aligned'; did you \
mean '-Wno-over-aligned'? [-Werror,-Wunknown-warning-option]
Change-Id: I86ee12a12fc24a0b8b92c4a0e665103ee4c4003d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/26879
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The two commits below are added to the BLOBs repository.
* fe7c6a3 pcengines/apu2: Disable ECC Exclusion range
* 3854ad2 cpu/amd/family_15h: Add latest AMD ucode file
The latest AMD microcode patches include Spectre mitigations.
Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to
function correctly.
BUG=b:110817463
TEST=ran firmware_CorruptFwSigB on grunt
Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.
BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.
Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change ensures that keyboard scanning is disabled and keyboard is
set to default state while disconnecting the keyboard. This is
required to ensure that the controller doesn't keep scanning and
buffering keystrokes which could lead to OS drivers reading stale
data.
BUG=b:110024487
TEST=Verified that kernel driver is able to probe correctly even if
multiple keys are pressed during handoff from payload to OS.
Change-Id: I1ffb8904d545284454c1825ee2e7c0087fc13762
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
None of the mainboards using Chrome EC set SCI mask for power
button. Thus, the EC will never generate SCI for power button
events. This change removes the Notify call for power button as part
of clean up for getting rid of the power button device in coreboot.
BUG=b:110913245
Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using common mtcmos code to power on audio and display modules in SOC.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Passes the status check at the end of
mtcmos_power_on()
Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable Image Processing Unit and CIO2 device that constitute IPU3.
BUG=None
TEST=Build and boot up into Nocturne platform and check with lspci.
Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
change sd_mmc_go_idle to be accessible from other files
so that we have an api to send CMD0 and reset the card.
BUG=b:78106689
TEST=Boot to OS
Change-Id: I064a9bded347be5d500047df92d1c448c3392016
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25066
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit c1072f2 [cbfstool: Update FIT entries in the second bootblock]
incorrectly changed the value of type_checksum_valid for microcode
entries from FIT_TYPE_MICROCODE to 0, breaking microcode loading on
Skylake/FSP1.1 devices (and others?). Correct this by reverting to the
previous value.
Test: build/boot google/chell, observe FspTempRamInit no longer fails,
device boots as expected.
Change-Id: Ib2a90137c7d4acf6ecd9f06cb6f856bd7e783676
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27266
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
An ACPI RMRR table is requried for IOMMU to work properly with an
iGPU (without using passthrough mode), so create one along with the
DRHD DMAR table if the iGPU is present and enabled.
Test: build/boot google/chell and purism/librem13v2 with kernel
parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated
graphics functional without corruption.
Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Add DMAR RMRR table entry and helper functions, using the existing
DRHD functions as a model. As the DRHD device scope (DS) functions
aren't DRHD-specific, genericize them to be used with RMRR tables as
well. Correct DRHD bar size to match table entry in creator function,
as noted in comments from patchset below.
Adapted from/supersedes https://review.coreboot.org/25445
Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27269
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add common code design document support Intel SoCs such as Skylake,
Cannonlake and Apollolake onwards.
Documented items:
*Introduction
*Design Principle
*Common code development and status
*Common code structure
*Benifits
Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
It used the sandybridge systemagent binary and mentioned that in the
help text which is simply wrong and won't work.
This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by
default.
Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both southbridges need to be done at once since this southbridge code
is used for different northbridges, which fails to compile when done
separately.
This needs an acpi_name functions in the northbridge code to be
defined.
TESTED on Intel DG43GT: show correct PIRQ ACPI entries in
/sys/firmware/acpi/tables/SSDT.
Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For this to work the northbridge and lpc bridge device need acpi_name
functions.
TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in
/sys/firmware/acpi/tables/SSDT
Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit changes the uid and desc fields for the sx9310 entries
in the devicetree to be unique, and correctly identify the position
of the respective sensors.
Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This enables the user to set the completion timeout value in PCI
Express Device Control 2 register via devicetree.cb.
Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release.
Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
If CPU 0's stack grows to large, it will overflow into CPU 1's stack.
If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop.
When the stack overflow occurs it will override the return pointer for
CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return
to a random address.
This method is not foolproof. If code allocates some stack variables
that overlap with the canary, and if the variables are never set, then
the canary will not be overwritten, but it will have been skipped. We
could mitigate this by adding a larger canary value if we wanted.
I chose to use the stack bottom pointer value as the canary value
because:
* It will change per CPU stack.
* Doesn't require hard coding a value that must be shared between the
.S and .c.
* Passing the expected canary value as a parameter felt like overkill.
We can explore adding other methods of signaling that a stack overflow
had occurred in a follow up. I limited die() to debug only because
otherwise it would be very hard to track down.
TEST=built on grunt with a small and large stack size. Then verified
that one causes a stack overflow and the other does not.
Stack overflow message:
canary 0x0 != 0xcdeafc00
SMM Handler caused a stack overflow
Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27229
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The stub flash driver is a temporary hack that planned to adapt eMMC to
SPI flash. Remove the hack since SPI flash is what we really expect.
BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui
Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
We would use GPP_B20 instead of board id to determine nautilus SKU.
BUG=b:80052672
BRANCH=poppy
TEST=Verified the new coreboot could determine SKU correctly
Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.
With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.
Only include cmos_layout.bin and cmos.default in RO region.
Add notes explaining the decisions.
Tested on Intel Sandybridge, builds and boots with vboot enabled.
Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Gigabyte was not in the list of vendors in the mainboard-specific
documentation. This made a newly added mainboard page difficult to
locate. This commit adds Gigabyte and links said mainboard in the
mainboard-specific documentation main page.
Change-Id: I8839e1c1176fbdc3dd9da616f68c58e8e1cf1b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel
Platforms) moved APL to use common SMM code. However, smi.c and smm.h
files under soc/intel/apollolake/ were not removed. This change
removes the dead files since they are not used anymore.
BUG=b:110836465
Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure
that we do not end up in a recursive SMI handler loop as mentioned in
change 74145f7 (intel/common/pmc: Disable all GPEs during
pmc_init). Thus, this call was added at the end of
pmc_fill_power_state as we want to ensure that all the GPE registers
are backed up before being cleared for identifying the wake source in
ramstage.
This resulted in a side-effect on APL where pmc_fixup_power_state was
called much later in the boot process. Even though we have got rid of
pmc_fixup_power_state, this change moves the call to
pmc_disable_all_gpe to happen just before enabling SMIs. This helps to
keep the disabling of GPEs logically before the enabling of SMIs and
any clean ups that happen in pmc or soc-specific code should not
affect the state of GPEs.
BUG=b:110836465
TEST=Verified that wake sources are correctly identified on KBL and
APL. Also, no SMI handler issues observed when resuming.
Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.
BUG=b:110836465
Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On APL, call to pmc_fixup_power_state was added because GPE0_EN
registers did not have the right bits set on resume from S3 -- this
was a result of GPE_CFG registers getting reset to their default state
on resume. GPE_CFG registers are programmed as part of pmc_gpe_init
which was previously done only in ramstage.
However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in
bootblock), call to pmc_gpe_init was added to bootblock which means
that GPE_CFG registers will have the right state by the time control
reaches romstage where pmc_fill_power_state is called. Thus, call to
pmc_fixup_power_state is totally redundant and in fact leads to
side-effects because of the call to pmc_disable_all_gpe at the end of
pmc_fill_power_state.
BUG=b:110836465
TEST=Verified on yorp that wake source is correctly identified on
resume from S3.
Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
%edx gets clobbered before the c handler is invoked. This is just a
cleanup cl to make the next cl look clean.
BUG=b:80539294
TEST=verified SMI still works on grunt.
Change-Id: I21bf41ed4fdeaaa8737c883f202a39cb57c2b517
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27228
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When generating a backtrace we need an indicator when we have hit the
beginning of the stack. The i386 ABI states that %ebp points to the next
stack frame. NULL can be used to indicate the end of the stack.
We could add a NULL return pointer at %ebp+4, but I decided to omit it
since a NULL stack pointer can be used as an indicator that there is no
return pointer.
BUG=b:80539294
TEST=built and tested on grunt
Change-Id: I8a48114d31a5c716335d264fa4fe4da41dc5bf11
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27226
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the cognitive overhead of referencing locals via esp since
it changes with every push.
BUG=b:80539294
TEST=built and booted on grunt.
Change-Id: Ib7eb98ce3483d4fc803696c1b2496d8384317536
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This makes it easier to spot unused RAM.
BUG=b:80539294
TEST=built and tested on grunt. Verified unused memory was set to 0xcdcdcdcd
Change-Id: I335eaf642bd8526f31819eaac95ce80c2df3c300
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
An unidentified combination of speculative reads and branch
predictions inside WRPROT-cacheable memory can cause invalidation of
cachelines and loss of stack on models based on NetBurst
microarchitecture.
Therefore disable WRPROT region entirely for all family F models.
As an extreme example, just changing the location of a constant string
passed to printk() has been witnessed to make a the boot fail early on
in romstage.
Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.
Using _program results with the same region being marked
as WRPROT-cacheble.
Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Disabling the MMU with proper cache behavior is a bit tricky on ARM64:
you can flush the cache first and then disable the MMU (like we have
been doing), but then you run the risk of having new cache lines
allocated in the tiny window between the two, which may or may not
become a problem when those get flushed at a later point (on some
platforms certain memory regions "go away" at certain points in a way
that makes the CPU very unhappy if it ever issues a write cycle to
them again afterwards).
The obvious alternative is to first disable the MMU and then flush the
cache, ensuring that every memory access after the flush already has the
non-cacheable attribute. But we can't just flip the order around in the
C code that we have because then those accesses in the tiny window
in-between will go straight to memory, so loads may yield the wrong
result or stores may get overwritten again by the later cache flush.
In the end, this all shouldn't really be a problem because we can do
both operations purely from registers without doing any explicit memory
accesses in-between. We just have to reimplement the function in
assembly to make sure the compiler doesn't insert any stack accesses at
the wrong points.
Change-Id: Ic552960c91400dadae6f130b2521a696eeb4c0b1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some arm64 files that were imported from other projects use the
__ASSEMBLY__ macro to test whether a header is included from a C or an
assembly file. This patch switches them to the coreboot standard
__ASSEMBLER__, which has the advantage of being a GCC builtin so that
the including file doesn't have to supply it explicitly.
Change-Id: I1023f72dd13857b14ce060388e97c658e748928f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With -D, the newly built toolchain isn't installed into $prefix/...
but into $DESTDIR/$prefix/... while being built for $prefix alone.
This is useful for distributions, but it breaks down when the build
host already has the toolchain installed in $prefix without proper
build isolation (cf. gentoo):
In such cases libgcc etc are built using the new compiler (as gcc's
build system is smart enough to state the path explicitly), but that
compiler then uses its regular algorithm to determine the path to as,
ld, ...
That makes it use the tools from $prefix, which might differ in formats
(assembly, certain object file flags, ...): nds32le-elf in particular
has rather unstable formats still, and so new compilers can't work
with old binutils.
The approach to deal with this is to take an unused path that's
specified by gcc's build system ($out/gcc/$arch/$version) and symlink
it to the new toolchain - these explicitly given directories take
precedence over the default search path, and so the new binutils
are used.
Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27241
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Limit is the maximum number of bits to be tested, however it's being checked
against the number of bytes of uint32_t. when it should be number of bits.
Create a macro to provide the number of bits, and use it instead of sizeof.
BUG=b:75996437
TEST=Add debug messages to see code passing beyond the check, build and
boot grunt, check that it passed the limit check, remove debug code.
Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Adds Open Cellular rotundu mainboard supports.
Working:
- 2x Ethernet support
- MSATA support
- CPU init
- Memory init
- USB support
- EMMC but disabled
Not working:
- TPM support
Create directory structure and Kconfig files for OpenCellular
Rotundu and copy sources from intel/minnowmax.
Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4
Signed-off-by: Hong Gan <hgan@fb.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This adds another camelbackmountain_fsp derivative, along with a .fmd
file for the board. For now it's been tested to build and boot.
Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.
Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.
BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A
Also try the failure scenarion by providing invalid topswap size.
Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.
BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.
Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.
TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.
Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that sconfig is able to support variant-specific override trees,
this change updates octopus boards to use this feature. Following
devices are moved from baseboard devicetree to variant specific
devicetree:
1. Touchscreen
2. Trackpad
3. Digitizer
4. Audio codec
BUG=b:80081934
TEST=Verified that the right devices show up in static.c for each
variant.
Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27219
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"ops" field was used in device structure only to add
default_dev_ops_root for root device. It was always set to NULL for
all other devices. This change gets rid of ops field from struct
device and instead hardcodes default_dev_ops_root in pass1 for root
device.
BUG=b:80081934
TEST=Verified that static.c generated with and without this change is
exactly the same.
Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to allow variants to override the devices and
properties in base device tree by providing an override device
tree. It works as follows:
1. Both base and override device trees are parsed from provided input
files.
2. Walk through the trees in lockstep fashion using depth-first
traversal checking if a node in override tree has a matching node in
base tree.
- If matching node is found, then update the properties of base node
using the override node. Continue walking the children of the nodes.
- If matching node is not found, then copy the entire override
subtree of the node under the current base parent. In addition to
that, chip instance pointers of the nodes in override tree need to be
updated if they were pointing to the override parents chip instance.
Since chip always expects a device to be present, it leads to a
side-effect that overriding chip registers requires that a device is
always provided for the chip in the override tree as well.
BUG=b:80081934
Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new config option OVERRIDE_DEVICETREE that allows
variants to provide an override devicetree file to override the
registers and/or add new devices on top of the ones provided by
baseboard devicetree using CONFIG_DEVICETREE.
BUG=b:80081934
Change-Id: Ica046b7e0d70d0f1e8d94da714d1e62032277916
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.
BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.
Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows sconfig utility to accept an extra optional
parameter to specify override device tree that can be used to override
the properties or add new devices in addition to that provided by base
device tree. This is helpful for variants that share most of the
devicetree but have to override certain registers or add some devices
which might not be applicable to base devicetree.
In order to support the override devicetree, following changes are
made in this CL:
1. override_root_dev and override_root_bus are provided.
2. main() function is updated to accept an optional argument.
3. If override device file is provided, then parse_devicetree is
called for override_devtree as well.
This change in itself does not provide the override feature. It is
only a small step towards the final goal. The override devicetree
parsed by sconfig is currently unused.
BUG=b:80081934
Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.
However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.
This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.
For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
During Speaker playback, quad Channel I/V feedback data is
captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data
needs to be given as echo ref stream.
So, adding stereo capture config to max98373_capture_formats.
BUG=b:110074225
TEST='Audio playback and Capture Stereo echo ref data'
Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.
Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.
Working:
- Serial port I/O
- S3 suspend/resume. Untested with SeaBIOS since it failed
to resume on a similar board. It is likely to be due to
low memory corruption, but I have not worked on it.
- USB ports and headers
- USB3 ports attached to the ASM1042 controller. SeaBIOS can
boot from them, and it is likely GRUB can detect devices on
those ports as well. The chip has a small SPI flash nearby,
which seems to hold an Option ROM.
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- VGA BIOS for integrated graphics init
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware.
- NVRAM settings. Only debug_level has been tested.
Untested:
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port. Thus, gma-mainboard.ads
has been setup accordingly.
- PS/2 port.
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port header.
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- Booting from devices attached to the ASM1061 controller.
Devices on ports work fine once Linux has loaded.
- Any SATA devices with Tianocore (payload issue)
Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Regarding "Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family",
Document Number: 307502-005, page 91, if Channel B is empty,
all of the C1DRBs are programmed with the same value as C0DRB3.
Mobile 945 express chipset datasheet doesn't mention this specific case.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27204
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board. The default is for bluetooth to be
enabled at this point.
BUG=b:110614620,b:110613353
BRANCH=none
TEST=none
Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.
As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.
Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.
Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a new driver for the SX9310 proximity detector device.
The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.
This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.
Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.
Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.
Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.
BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.
Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models
already. Enabling this option ensures that the NVIDIA GPU is powered.
More PCI devices can be observed when activating this setting. It was verified
on a W520, also by loading a VGA option ROM and achieving a working Dual
Graphics system.
The CMOS default has been kept to 'Integrated Only', as the usage of Dual
Graphics requires an option ROM and drains the battery more quickly.
Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/26114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for SKL and KBL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
DRAM_DMA section is used for the special SPI NOR controller on legacy
SOC. Remove it since no driver need it currently and we don't have the
special SPI NOR controller on mt8183.
BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui
Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Using common watchdog timer (WDT) code for reset. Set up watchdog timer
in mtk_wdt_init() to get reset status and disable auto-reboot. Link
common do_hard_reset() to support hard reset.
BUG=b:80501386
BRANCH=none
TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui.
Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27026
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move watchdog timer (WDT) code which can be reused into a common
directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27025
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a temporary hack to test camera presence before we have full
camera support implemented. Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.
BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.
Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.
BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking
Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.
BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS
Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.
BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot
Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a file for uncore ASL code that is common among
Broadwell-DE mainboards but is currently copy + pasted in each of
their dsdt.asl files.
This is only for clean-up purposes. It is unclear if the code itself is
really necessary, but until we can do further investigation and testing
it will be left in.
Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Collected timestamps indicate LZMA decompression of ramstage
is 4x slower when ROM is marked WP-cacheable, in contrast to
having ROM as US. A simple copy WP->WB with uncompressed
ramstage also appeared to be twice as slow as UC->WB copy.
It should be noted that if POSTCAR_STAGE was removed from build,
un-lzma takes 130 seconds instead of 45 milliseconds.
Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change fixes the following issues with EC_IN_RW signal:
1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in
GPIO table for baseboard and bip.
2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can
re-sample the GPIO at runtime.
BUG=b:110084012
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The endian conversion function be32toh() is defined in
src/include/endian.h, however this file is not used for cbfstool
compilation. Currently the one provided by the host is used and if the
host does not provide this endian.h file, the build will fail.
However, we do have endian conversion functions in commonlib/endian.h
which is available for cbfstool compilation.
Switch from be32toh() to read_be32() in order to avoid relying on a
host provided include file.
We use functions from commonlib/endian.h already in cbfstool.
Change-Id: I106274cf9c69e1849f848920d96a61188f895b36
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/27116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The DEVEN defines are wrong, but weren't used at all.
Fix them as they are needed by the hybrid_graphics_driver and
use the defines instead of magic values.
Tested on Lenovo T410: The IGD turns on with the correct value.
Change-Id: Idf9fc0115de5c72f7d5d88cbb09ae1d2fee0afd0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The dram controller cannot fully initialize the dram on warm
reset (receive enable calibration consistently fails) therefore
requiring cached timings.
This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.
Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All Grunt variants should identify as grunt in SMBIOS so that
they're recognized correctly as a unibuild Grunt variant.
BUG=b:110244268
TEST=Careena identifies as grunt
Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27117
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pin does not have a native function for eSPI. Nonetheless if we use
eSPI, it should be configured as a GPIO and kept unconnected to allow
S0ix entry.
Also removed initialization of LPC pins in mainboard code as they are
already initialized in chipset code. The settings fpr LPC pins in
chipset code were updated to those that were previously in mainboard
code and have been validated on LPC flavor of Geminilake RVP.
BUG=b:79251613
BRANCH=none
TEST=From kernel prompt in bip, type powerd_dbus_suspend.
Check on EC console that SOC enters S0ix.
Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.
Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.
Starting at this point a CBFS payload/ can be either of type FIT or SELF.
Tested on Cavium SoC.
Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable keyboard backlight by Careena SKUID
Set to 10% as the same as google/snappy project
BUG=b:110065836
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some things were coding errors, other things need to be fsb specific.
Most things here don't seem to matter all that much but better to get
it right.
Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It looks like this hardware has a bug where the display controller
does not work properly when dram is clocked 533MHz and the channels
are configured in non-stacked mode.
The workaround is to select stacked mode in this configuration.
Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There seems to be a hardware bug where the combination of non-stacked
channel settings, both channels populated and 533MHz dram speed cause
the display to be unusable.
The code to actually select stacked mode based on hardware
configuration will be add in a followup patch.
This patch does the following:
* Add option to the sysinfo struct for stacked mode
* Fix programming channel 1 DRB which needs special care for the last
populated rank in stacked mode
TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz)
Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GSMI Set Event Log is taking more than 1K in stack. This causes the
stack to overflow into the adjacent stack. This has the side effect of
causing any CPU waiting for the SMI handler to complete to crash when
the lock is unlocked because the return pointer has been smashed.
BUG=b:80539294
TEST=built on grunt and tested by running `halt` from the OS.
Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27033
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).
BUG=b:80089559
BRANCH=none
TEST=none
Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.
BUG=b:79667559,b:78122599
BRANCH=none
TEST=none
Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit. Define POWER_CTL_C1E_MASK to be used subsequently.
Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move generators for the board status report and the kconfig options
report into a common directory and wrap them in a docker container.
Also rework to emit HTML not wiki syntax.
Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of checking each directory in series, kick off the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder by 60%.
This could probably be sped up even more by splitting up src/mainboard
into smaller sections.
This method does skip a few control files at the top level - .gitignore,
.checkpatch.conf, gnat.adc, etc. These could be added to the list of
files to check, but I didn't think it was needed.
Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Per PCI specification, function 0 must be present,
so functions 1 to 7 can be skipped in this case.
For a device that is not multi-function, it may not
decode function number in the hardware at all. To
avoid registering such a device eight times, skip
scanning functions 1 to 7.
Without the latter fix, a single-function PCI bridge
may call pci_scan_bus() second time and secondary
side devices would get appended second time in the
array devices[]. At that point, quicksort() apparently
hits an infinite recursion loop.
Since pci_scan_bus() is called in part of the early
modules->init() sequence early in main(), the errors
here left coreinfo payload completely silent when
PCI module was built-in on affected system.
Terminal screen was cleared, though.
Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.
Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.
Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.
TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368
Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement an optional callout for AgesaHeapRebase which allows AGESA
to override any internal hardcoded heap addresses.
Designate a region in CAR that may be used for pre-mem heap and return
that address before DRAM is configured. After DRAM is up, the address
in cbmem is returned.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement a new AGESA callout that may be used to find the correct
temporary location in DRAM to store heap data.
Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based
location to a temporary region. Once cbmem has been established, the
heap will be relocated again in AmdInitEnv from the temp location to
the final one.
This patch does not materially affect the behavior of AGESA's heap
management. It only puts coreboot in control of the location. Future
work may refactor the copying.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new callout definition for AgesaGetTempHeapBase and displace
AgesaHeapRebase (which was merged too soon) in the ordering. Also
add its structure.
AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost. The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.
BUG=b:74518368
Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The -S flag of me_cleaner, in addition to the standard code removal,
sets the the AltMeDisable bit (ME 6.x-10.x) or the HAP bit (ME 11.x),
which asks Intel ME to stop the execution after the hardware
initialization.
This should bring some advantages:
* The state of Intel ME can be easily obtained by reading the Current
Operation Mode register to trigger specific adjustments in the
raminit (as already done in bd82x6x)
* Intel ME falls into a more defined state, instead of being in a
generic "Image Failure"
* Hopefully, less code is run by Intel ME, as the execution should
stop before even trying to load additional modules
Tested on:
* Nehalem, Sandy Bridge and Ivy Bridge (Nicola Corna)
* Broadwell, Skylake and Kabylake (Youness Alaoui)
If needed, the -S flag can be removed or integrated with other
board-specific options by overriding CONFIG_ME_CLEANER_ARGS.
Change-Id: I2c12d09124dcc39924d1dc4eaf53a2dc1f69a2ac
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
In preparation to allow devicetree overrides, it will be necessary to
use the same parsing functions to prepare two separate parse
trees. This change does the following things:
1. Updates root device and bus names to add base_ prefix.
2. Adds a function parse_devicetree that sets the root_parent and
linenum before calling yyparse().
3. Updates all uses of root_dev to refer to the next base_root_dev.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built using
abuild is the same with and without this change.
Change-Id: I403a90c1ebf07ac66115ddfe137daf0980dc1a18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
This adds stoneyridge specific versions.
BUG=b:79546790
TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS,
activate ACPI debug, activate S3 stress test. Interrupt stress test, do a
"cat /var/log/messages" saving the serial output. Examine the serial
output, see added debug code showing action taken. Confirm action by
reading proper register. Debug code removed.
Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of checking each directory in series, kick off all the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder from 31 seconds to 6.
Change-Id: I1252a68a723370389d399f3d1a2aff3fad64c365
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Copy the script `scripts/config` from Linux (commit 427fbe89 (Merge
branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux)) into the
newly created directory `scripts`. Here is the original commit message
from 2009.
> commit 8e54701ea85b0ab0971637825a628f5aa2b678a4
> Author: Andi Kleen <andi@firstfloor.org>
> Date: Sat Jan 3 03:21:41 2009 +0100
>
> kconfig: add script to manipulate .config files on the command line
>
> I often change single options in .config files. Instead of using
> an editor or one of the frontends it's convenient to do this from
> the command line. It's also useful to do from automated build scripts
> when building different variants from a base config file.
>
> I extracted most of the CONFIG manipulation code from one of my
> build scripts into a new shell script scripts/config
>
> The script is not integrated with the normal Kconfig machinery
> and doesn't do any checking against Kconfig files, but just manipulates
> that text format. This is always done at make time anyways.
>
> I believe this script would be a useful standard addition for scripts/*
>
> Sample usage:
>
> ./scripts/config --disable smp
> Disable SMP in .config file
>
> ./scripts/config --file otherdir/.config --module e1000e
> Enable E1000E as module in otherdir/.config
>
> ./scripts/config --state smp
> y
> Check state of config option CONFIG_SMP
>
> After merging into git please make scripts/config executable
>
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Change-Id: Ie32a4459398df8694956dd644f38692017a26388
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26243
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.
Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As a result of commit:
[711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device
fizz's chip_info for the LAN driver is being overwritten/nulled, as the
LAN device is on function 2 (PCIe port 3), but the driver info was set
for the post-swapped PCIe port (1).
Move the driver chip_info to function 2/port 3, so that it follows the
PCI device function when swapped after FSP-s, and is correctly passed
to the LAN driver.
Test: boot google/fizz (teemo variant), check cbmem console and
verify ethernet MAC address and LED config correctly set.
Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Why would that be a user visible option? Drop the prompt and the
`default n` and select it automatically when needed. I hope I
caught all its users.
TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile
and link.
Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean it up and add all flash chip drivers to postcar stage thereby.
There seem to be SPI controllers that don't need the individual
flash chip drivers. For those postcar support was added in b6b1b23
(console/flashconsole: Enable support for postcar). However for
SPI controllers that need the individual drivers (i.e. those with
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar
stage was broken.
For all other stages, the set of compilation units stays the same.
Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is no longer needed. Removing Kahlee options allows some
Kconfig options to be optimized.
BUG=b:77693343
TEST=Build Grunt, verify that nothing's changed.
Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform.
BUG=b:79559085
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0
flag is set in FACP table - FADT.Flags[21] bit.
Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/26940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This change gets rid of rescnt member in struct device since it is
redundant. "res" member can be used to determine if resource list is
present or not.
BUG=b:80081934
TEST=Verified that static.c generated with and without this CL is
exactly the same for all boards built using abuild.
Change-Id: I73a2361686ad1130716a7d29576f2d02b9ed33c1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change re-factors the device structure in parse tree to be able
to support multidev devices just like non-multidev devices.
With this change, every device has a bus under it which is the parent
of all devices that fall on the bus. If there are duplicate entries in
the devicetree, then there will be multiple buses under the device and
each bus will have its own set of children.
The tree starts out with a root device which has a root bus under
it. This is a special device which is created statically and its
parent is its own root bus. When parsing the device tree file, devices
get added under the root bus as children.
Since this change re-organizes the way devicetree is represented, it
gets rid of latestchild and next_sibling pointers from struct
device. Also, the tree traversal to generate static.c is changed to
breadth-first walk instead of using the next_sibling.
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: Ic8c8a73a247e8e992ab6b1b2cc3131e06fa2e5a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates queue handling routines to be more generic so that
it can be used by more than just chip queue. Additionally, it provides
functions to dequeue element from head and peek head of a queue which
will be used in a follow-up commit.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: Ibd2de85b48c5d4e2790bf974ea3bb1bd387f66ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Careena uses a different keyboard backlight method, so let the EC
handle the different SKUs and backlight methods.
BUG=b:80106042
TEST=None
Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Until these need to be separated out, use a common file for mainboard
and romstage to make upkeep easier.
BUG=b:80106042
TEST=Build Grunt and Careena
Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This fixes the following failure on certain google/peppy configs:
build/postcar/lib/reset.o: In function `__hard_reset':
/home/pgeorgi/coreboot/src/lib/reset.c:24: undefined reference to `do_hard_reset'
Change-Id: I448a8702a30108f1fc82179a766cbdd209336df7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looking at the 100MHz signal, we were violating the timing requirements.
66MHz still isn't great, but it's a good tradeoff between improving
the signal and losing boot speed time.
This slows down the boot time by about 20mS.
BUG=b:109583457
TEST=Boot grunt, look at signal on scope
Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
During compilation sconfig/main.c gives an error regarding number of
arguments passed in fprintf.
BUG=none
BRANCH=none
TEST=check if compilation warning has been fixed
Change-Id: Ia769cc606a1e3f7e1188cd82235442493d37f664
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change gets rid of unused 3rd parameter chips to the function
walk_device_tree.
BUG=b:80081934
TEST=Verified that abuild compiles successfully for all boards.
Change-Id: I255ff030562073b16310fc22a0981808bf2c062f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update to current master.
This includes:
- G45 support
- fixes scaling on eDP (needed for working textmode on eDP)
- gfx_test drawing and moving cursors
- Adding support for Tiling on <= Haswell
- Allow changes to the framebuffer configurarion without resetting the
pipe.
Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26823
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Scan-build refuses to run if the -fconserve-stack flag is added to
cflags. It fails with the cryptic message "could not find clang line".
Change-Id: Ib1b56ef7d217138a1a195fe993d8e8dd965bd855
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Last time there was a request to change a link from HTTP to HTTPS, also
it seems more ethical to use a link to the Free Software Foundation
server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad.
Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fixes two buffer overflows and opens a road to further improvements.
All the previous adjustments to libpayload_tint.patch (including the
latest "use the current time as random seed") have been preserved.
Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23852
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a common function to decode the TSEG size from the ESMRAM
register. This will come in handy when SMM in TSEG is implemented.
This function is used both in romstage and in ramstage.
Change-Id: I4e163598752fb6cd036aec229fce439ebad74def
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23448
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For enable_resource & set_resource, use default DEVICE_NOOP so that they
are not reported as missing during enumeration.
BUG=None
BRANCH=None
TEST= Build & boot soraka.
Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update GPIOs in baseboard to match latest schematics:
1. Get rid of STEST GPIOs(GPIO_{62,84-89})
2. Get rid of SD_CD_ODL(GPIO_134)
3. Get rid of KB control GPIOs(GPIO_{144-146})
4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the
configuration for other pen GPIOs.
BUG=b:109764138
Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26874
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path
to point to the mainboard dir and to select
INTEL_GMA_ADD_VBT_DATA_FILE by default.
Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds the release notes for all of our old releases that have notes
to the documentation directory. The release notes for the next release,
4.9 is added here as well.
I would request that people document their changes for the next release
themselves if they wish them to be in the release notes.
Change-Id: I7440a3130f2f7d80c4434d2b5a918e62bbd08fbb
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When the normal termination is None, the standby termination is
none also as per Doc# 572688. So when termination is only needed in
standby, use the IOSSTATE setting that drives low/high via the
Tx mode instead.
Also disabled Speaker in Standby state to save power.
BUG=b:79874891, b:79982669
BRANCH=None
TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles
pass. Checked that bluetooth is functional on resume. On Yorp, checked
that speaker is functional after a suspend/resume cycle.
Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Issue observed on the board is: too many jack interrupts.
cat /proc/interrupts | grep da7219
58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad
Updated pad configuration for Jack IRQ pin to fix the issue.
BUG=b:109655907
TEST=Jack insertion & removal detection is working.
Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
During measurement of signals during Elan touchscreen power on, saw
that the enable_gpio delay was not sufficient as there is a +1.5 ms
delay during power on. Adding more delay to take this into account.
BUG=b:78311818
BRANCH=None
TEST=probe power on signals to ensure meet timing requirements
Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Power off does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/power off.
BUG=b:78311818
BRANCH=None
TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled
Make sure delays are consistent with spec
Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a glue layer between SOC and common block IPs in terms
of PCH. All common IP blocks now can be selected based on
SOC_INTEL_COMMON_PCH_BASE config option.
BUG=none
BRANCH=b:78109109
TEST=Build and boot Cannonlake RVP and EVE.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).
All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.
A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.
BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option
Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables wake-over-wifi functionality for all octopus
variants by making the following changeS:
1. Configure GPIO_119 as SCI active-low
2. Update GPE0_DW1 to include the group that GPIO_119 falls under
3. Add wake property to wifi device
BUG=b:77224247
TEST=Verified that wake-over-wifi works on yorp.
Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit
64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect
this.
BUG=b:77224247
Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chips and devices are treated differently and the device tree
actually contains only devices, next and nextdev are exactly the same
for all devices in the tree. This change gets rid of nextdev pointer
and updates all uses of nextdev to next.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chips and devices are treated differently in sconfig, this
change gets rid of struct header and add_header function which were
responsible for maintaining list of headers that need to be added to
static.c.
Instead, struct chip is re-factored into struct chip and
struct chip_instance, where chip is a list of unique chips required by
the mainboard whereas chip_instance is an instance of the chip. One
chip can have multiple instances dependending upon the devices in the
system. Also, struct device is updated to hold a pointer to chip
instance instead of the chip structure. This unique list of chips is
then used to add appropriate headers to static.c
BUG=b:80081934
TEST=Verified using abuild that all boards compile successfully.
Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function s_alloc (sconfig alloc) that allocates memory
using calloc to get 0 initialized memory and checks to ensure it is
not NULL.
BUG=b:80081934
Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The only reason bus pointer existed in device structure in sconfig was
to allow a node to point to the parent which could be a chip and bus
which is the true parent in device tree hierarchy. Now that chip is no
longer a device, there is no need for separate bus and parent
pointers. This change gets rid of the redundant bus pointer in struct
device in sconfig.
BUG=b:80081934
TEST=Verified that static.c generated for all boards built by abuild
is same with and without this change.
Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change removes call to add_header from parsing functions and
moves it to a local function within main.c. It also adds a new
function emit_headers that is responsible for creating the linked list
for chip headers and emitting those to static.c
BUG=b:80081934
TEST=Verified that static.c for all files compiled using abuild is the
same with and without this change.
Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a new structure "struct chip" to identify elements of
type chip rather than re-using the structure for device. Until now
chip was treated as a device while generating the parse tree and then
device tree postprocessing skipped over all the chip entries in
children and sibling pointers of device nodes.
With this change, the device tree will only contain struct device in
the parsed tree. It helps by avoiding unnecessary pointers to chip
structure as children or next_sibling and then skipping those elements
in post processing. Every device can then hold a pointer to its chip.
When generating static.c, chip structure is emitted before device
structure to ensure that the device structure has chip within its
scope. Externally, the only visible change in static.c should be the
order in which chip/device elements are emitted i.e. previously all
chips under a particular device were emitted to static.c and then the
devices using those chips. Now, all chips are emitted before all the
devices in static.c
BUG=b:80081934
TEST=Verified that abuild is successful for all boards. Also, verified
that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is
unchanged from before in node definitions.
Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.
Also fix off-by-one error with the bitmasks.
Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20808
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.
Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes the following:
- compute amount variable MTRR's during runtime
- Wait for all CPU's to be in Wait for SIPI state after sending init
INIT IPI to all AP's
- compute the PHYSMASK high during runtime and preload it to the
MTRR_PHYS_MASK msr's
Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is
also needed for future C_ENVIRONMENT_BOOTBLOCK.
When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it
is identical.
Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
After FSP-S, a device on PCI function n will be function swapped
to function 0 if there is no device presnet on function 0.
It needs some modification for DT and causes mismatches between
software configuration and hardware schematic. This patch is
from d779605, which swaps the devfn of the first enabled device
in DT and function 0 resides in a PCI device.
BUG=b:80105785
BRANCH=None
TEST=Make sure the device is still enabled after coalescence with
device on bus 0 and w/o device on bus 0. Test with suspend
and resume and ensure it's consistent.
Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/26479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The generated file .dependencies shall be removed on invocation of
'make clean' as the clean target aims to delete all generated files.
Change-Id: I4ec291fe84136bbdf1c2563cc10195846652a36d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This allows to lock down spi among other things
Mostly copied from bd82x6x.
Tested on Intel DG41WV with the MRC_CACHE driver write protecting the
mrc_cache region.
Change-Id: If9c3a6118f4586d51c093edec896c347ba904b8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Based on Nicola Corna's work.
This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the
console output to the SPI flash.
TESTED to still work in ramstage on x220 (correctly writes MRC CACHE),
the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the
common Intel SPI code (untested though).
Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Could be useful to write protect regions like for instance the
MRC_CACHE region.
Tested on Intel DG41WV (i82801gx) and Lenovo Thinkpad X220 (bd82x6x)
to write protect the mrc_cache region.
Change-Id: Id0a9a0de639c5d6761a77a56ceba6d89110a4ea1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The yabel emulator depends on IO ports, that aren't available on
ARM and MIPS. Add additional dependencies to fix compilation errors
with the default configuration.
Change-Id: If0e28b356c01cb3ae0739a54aa3531a2acedbfbb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Name the CPU device structure as per processor brand string.
Before logs use to look like:
APIC: 01 (unknown)
Now logs looks like(depending on CPU on which it is tested):
APIC: 01 (Intel(R) Core(TM) m3-7Y30 CPU @ 1.00GHz)
BUG=None
BRANCH=None
TEST= Build & boot Soraka.
Change-Id: I6af0e29bbbdb59406baeae32f7874ff9036a9c81
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we have POSTCAR_STAGE there is no need for
romstage to include LZMA decompression code.
Reduces romstage by about 4 kiB on x86.
Change-Id: I4c475986b2a94e5cd540c3eead433ed6c0a815ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Non of the .c files is using a function from console.h directly.
Include console.h is moved to sd_mmc.h, where sdhc_error("msg..") is
defined.
Change-Id: Ic9283f227a37785056b9fac216fabcac054066a0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26752
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.
Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because of struct sci_source table of events that have to generate SCI or
SMI, <soc/smi.h> was included to kahlee/grunt gpio.c files. However, new
code transfered most of SCI/SMI/interrupt programming (with exception of
events not associated to a GPIO pin), and therefore smi.h is now included
by gpio.h. It was also added to some other files where they are not needed.
Only smihandler.c truly needs it. Remove the includes.
BUG=b:78139413
TEST=build and boot grunt.
Change-Id: I64cf0796103a5226ddace03d05d94160bf93aa69
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26721
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change may require board_mismatch=force if mainline firmware was
used. If vendor firmware was used this patch remove flashrom confusion
since system product name reported by SMBIOS tables will match mainline
firmware.
Change-Id: Ic6942bc36df1a02db61b035ddc892585688aa27b
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26757
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling. In newer versions
of IASL, this generates an error, as the method is defined in two
places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.
TEST=Build before and after, make sure correct code is included.
Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Along with other patches submitted for review to get the chipset
parts working, this allows Linux or other OS to use a TPM module
plugged into the 20-pin LPC header on the board, by exposing its
presence through the ACPI and PNP tables.
This patch adds to the Kconfig and devicetree.cb files.
Tested with the TPM/FW 3.19 and the trousers tools.
Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The file cache_as_ram_ht.inc is used across a variety
of CPUs and northbridges. We need to split it anyway
for future C_ENVIRONMENT_BOOTBLOCK and verstage work.
Split and rename the files, remove code that is globally
implemented in POSTCAR_STAGE framework already.
Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reducing two AGP aperture windows from default 256 MiB to
chipset minimum 4 MiB releases 504 MiB of unused MMIO space.
Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB.
Supported CPUs are 32-bit with PAE, so there is a little reason
to avoid overlarge MMIO region.
Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With implementation of LATE_CBMEM_INIT, top-of-low-memory
TOLM was adjusted late in ramstage. We do not allow that with
EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO
space is now used with statically set TOLM.
Also remove support code for the obsolete LATE_CBMEM_INIT
this northbridge used.
Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fixed resources have to be registered early during
read_resources() phase, such that device allocator
will avoid them.
Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Add some directories and files to the ignore list
- Add the LGPL as a recognized header. It's used in some files that
were pulled into coreboot from other sources.
Change-Id: I53423205f1cbf142a294ee5d24e885741a44dfcd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change adds and updates headers in all of the mainboard files that
had missing or unrecognized headers. After this goes in, we can turn on
lint checking for headers in all mainboard directories.
Change-Id: Ibe038a8f7468253b21fd2ac90c045d0c9cc89dfc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix regression after commit
6032018 console: only allow console messages after initialization
Fix it so that the two remaining platforms that are being
moved to EARLY_CBMEM_INIT have chance to send board-status
with non-dirty tags before and after the conversion is made.
This also leaves us with a record in the repository where
LATE_CBMEM_INIT was known to work on some platform.
Change-Id: Ie874f986a2c474bba117d7d6ae959decec8060a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver only supports streaming images flipped horizontally
and vertically. In order to ensure that all current users will
be fine if or when support for upright streaming is added,
require the presence of the "rotation" control now.
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Reviewed-on: https://review.coreboot.org/26727
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It now looks like this:
Check that files have license headers (lint-stable-000-license-headers): success
Check for superfluous whitespace in the tree (lint-stable-003-whitespace): success
Check that C labels begin at start-of-line (lint-stable-004-style-labels): success
Change-Id: I9d1f6adebae5b68a51e89c2833f8713f0ffcb616
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement method to access the SuperIO's harware monitor (HWM) IO space.
Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option
to all board that use NPCD378. In case no CMOS is set use the default
fan level 3.
The HWM space can be written to at any time, but the SuperIO has to be
notified that a write is ongoing. After clearing the write-lock bit all
changes are applied at once.
Tested on HP Compaq 8200 SFF.
Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.
Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It's a white list (configured through $(top)/.clang-format-scope) with
the expectation that the list will grow over time.
Once everything is covered, we can turn off the white-listing and keep
everything enforced.
To not drive people crazy, only check the files their commit touched.
Change-Id: I52c7ea73fd36aaa46c0bfce928158e1cd6304540
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.
The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.
Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.
Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When the i210 MACPHY is operated in the SERDES Backplane mode (which
depends on the programmed firmware image), its PCI-ID will be 0x1537.
This does however not change the programming interface for the MAC
address.
Therefore add this new PCI-ID to the driver so that the MAC address can
be programmed in this operation mode as well.
Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.
Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The included .c file also pulled in ancient files
amdk8/pre_f.h and amdk8/raminit.h
Do a dirty copy-paste to work around that.
Change-Id: Ie89a5f91d5234f1ef334d30a43dd56e0b722b5ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of requiring the user to enter their root password to set the
created files to their user, create a new user inside the docker
container with the correct UID & GID and build with that.
Change-Id: Ibbeff00211e8cf653f48204d285e06bca39b5fd2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Users can have non-default configurations as to how git diff et al are
presenting file names in diffs (default: a/ and b/ prefixes). checkpatch
expects that and trims the first element, so enforce that configuration
for the diff that's sent into it.
Change-Id: I099795119456a73c900b31ce191c2d9e898a5c7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The SPD files will be common to many of the mainboards, so move them out
of grunt and into the variants/baseboard directory.
BUG=b:80106042
TEST=Build grunt, make sure spd.bin is the same.
Change-Id: I53975a46a8c7d7e519bb6f7ef6ccd0b817ac4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files
Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
keyboard_getchar();
BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang
Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds and updates headers in all of the northbridge files
that had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all northbridge directories.
Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change adds and updates headers in all of the southbridge files
that had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all southbridge directories.
Change-Id: I09614730bfd4db923dda103bd07bab02836a4c92
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change adds and updates headers in all of the soc files that
had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all soc directories.
Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently the throttle event handler method THRT is defined as an extern,
then defined again in the platform with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On Ibex Peak (and maybe also on other platforms), when the AltMeDisable
bit is set (-S or -s option of me_cleaner), the ME PCI device disappears
from the bus and its configuration space is all ones.
This causes a freeze in intel_me_status(), as coreboot tries to access
an out of bounds array element.
Change-Id: I957abebe1db15ec2c9a2b439f0103106bfa56b33
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/26601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.
Furthermore, some of these pins were configured with normal termination
of None which would as per above mentioned document lead to a standby
termination of None anyways.
Instead of pull downs, use the IOSSTATE setting for driving low
via the Tx mode.
BUG=b:79874891, b:79494332, b:79982669
BRANCH=None
TEST=Flashed image and booted to OS on Yorp. Touchscreen does not
consume power in suspend state.
Change-Id: I7dcf3691b969d018b3cfb6af3f7467c9b523fee5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Max98373's NHLT capture configuration is used for IV feedback for
DSM algorithm.
Feedback is 4-channel data. Without this configuration below error
is seen in dmesg:
[ 315.784250] snd_soc_skl 0000:00:1f.3: Blob NULL for id 0 type 3 dirn 1
[ 315.784263] snd_soc_skl 0000:00:1f.3: PCM: ch 4, freq 48000, fmt 32
So, update nhlt configuration accordingly.
BUG=b:79362472
TEST=Audio playback works with IV feedback enabled
Change-Id: I75434a63fe030ed9bb963c6d300d833a8e7d2d66
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
The recursive method calling this function has been changed to
handle a null return from acpi_device_name and abort instead of
continuing and perhaps forming an invalid ACPI path.
Change-Id: Ic17c5b6facdcb1a0ac696912867d62652b2bf18e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This board was used a test target for the x4x DDR3 raminit patches and
has an easy to access DIP8 socket.
What is tested and works:
* S3 resume
* PEG, PCI, USB, SATA
* Sound
* Ethernet
* Native graphic init (textmode and linear fb) on the VGA output
* Passing memtest86+ with 2 2Rx8 4G dimms
* PS2 Keyboard
* Flashing coreboot internally from vendor BIOS.
What does not work:
* Running dram at 533 MHz (limited at 400MHz currently)
Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux
4.10.
Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves PL2 override to variant_devtree_update for two reasons:
1. This function was added to basically override devtree settings in
variant specific code. So, it would be a good idea to perform all the
overrides in a single place.
2. Adding a device for performing nami_enable would require changes to
devicetree and special handling for calling this device enable. Thus,
nami_enable was never getting called.
BUG=b:80148703
Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This creates a pin-route matrix first and then generates the ACPI
entries based on that. This approach has the advantage of being
simpler (no need for checks on double entries) and requiring less
access to the pci config space.
A few thing that are also fixed:
* Don't declare DEFAULT_RCBA redundantly.
* Only loop over PCI devices on bus 0
* Add a license header to rcba_pirq.c
* Remove inappropriate use of typedefs
* Fix the pin field: needs to be a byte
* Fix the source field: it should either be a byte or a path
(according to Advanced Configuration and Power Interface Specification
rev 2.0c)
Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22979
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to log post codes from a previous (failed) boot
if we are resuming from S3, since the previous boot has to have been
successful in order to enter S3 in the first place.
While we are at it, use a helper function to combine conditionals and
improve readability.
BUG=none
TEST=boot, suspend & resume grunt
Change-Id: I4f3bb8526a0c8c0ea1efd924628b33c147543b88
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26528
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were unconditionally adding a TYPE_BOOT message to the ELOG
on every boot (even S3 resume) if CONFIG_ELOG_BOOT_COUNT was disabled.
Now that boot_count_read() returns 0 for the !CONFIG_ELOG_BOOT_COUNT
case, the code becomes a bit simpler.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: I803fa4c3e03b6cc94751cf0ce34b78021ae2124e
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26527
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the
state of the BIOS FLASH Write Protect signal at boot.
The result of this read accumulated in the vboot state that's passed on
to the upper layers of the stack.
Therefore this GPIO must be configured as a "reset stage" GPIO, not
a "RAM" stage GPIO.
BUG=b:79866233
TEST=firmware_WriteProtect
Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26498
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In early stages (pre ramstage), we have two notions of devices.
To access the hardware, "simple device" handles are used. These
are plain numbers. To access the static information of the device
tree, we use `struct device` pointers. This is referred to as
DEVTREE_EARLY in the code.
This file is about the latter and its name reflects that the
tree remains unmodified.
Change-Id: I31aeb118615e86026f7111f83a7866d4e7426170
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add new port based on autoport.
The board uses a NPCD378 SuperIO, that is full of custom hardware.
The 8MiB flash SOIC-8 can be accessed after cutting of a part of the
DIMM slot holder. The flash IC has no diode, powering a part of the
board while flashing externaly, including the Standby-LED.
The following have been tested and is working:
* Native raminit with up to four DIMMs
* Libgfxinit on DisplayPort
* USB
* EHCI debug
* Serial on RS232
* Ethernet
* PCIe on x4
* PCIe on x16
* SATA
* Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload
* Flashing internaly
* PS/2 is working
Untested:
* PCI slot
* LPT port
* VBIOS
* S3 resume
Not working:
* PSU fan managment (runs at 100%)
* Half of SuperIO functionality is unknown
TODO:
* Reverse engineer remaining SuperIO registers
* Reverse engineer SMM
Fixes on follow-up commits:
* Added PSU fan control
* Reverse engineered some of Super IO's HWM registers
* Added SMBIOS tables for IPMI
Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with GRUB 2.02 as a payload, booting Arch Linux with
latest kernel. This code is based on the output of autoport
as well as existing ga-b75m-d3h and ga-b75m-d3v mainboards.
Working:
- Serial port I/O
- S3 suspend/resume (broken with SeaBIOS 1.11.1)
- USB ports and headers
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit (4+4GB, 4+2GB, 2+2GB, DDR3-1333)
- Native graphics init with libgfxinit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for integrated graphics init
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port.
- PS/2 ports
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- SATA devices with Tianocore (payload issue)
- PCIe to PCI bridge. It seems to be poorly supported on Linux,
it lacks a public datasheet and vendor BIOS behaves in the
same way: The bridge and the devices behind it appear, but
drivers fail to find devices attached to the bridge.
Change-Id: I598a0b75093a0f1aef2ac615035d66786a8c22cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When programming the final dram attribute and dram boundary settings,
on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM
Refresh Control) register as documented in "Intel ® 4 Series Chipset
Family" documentation.
Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
DDR3 adapted a fly-by topology which allows for better signal
integrity but at the same time requires additional calibration. This
is done by settings the targeted rank in write leveling mode while
disabling output buffer on the other ranks. After that the DQS signal
gets sampled over DQ until a transition from high to low is found.
Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)
This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.
The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.
Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
ApolloLake based reef platform is fan-less design. We do not need
these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef
variants as those are not being used.
Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/26468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This maps a bit field to the EC (EC_ACPI_MEM_USB_PORT_POWER) that can be
used to control the power state of up to 8 individual USB ports. Some
Chromeboxes have their GPIO pins for controlling USB port power wired to
the EC, so they cannot be accessed directly by coreboot.
Change-Id: I6a362c2b868b296031a4170c15e7c0dedbb870b8
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://review.coreboot.org/26471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.
BUG=b:76020953
TEST=Build grunt
Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.
BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.
Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows one to compile intelmetool with support for older ME
versions by setting the OLDARC preprocessor definition.
For example, compiling with OLDARC enabled avoids the "ME: GET FW
VERSION message failed:" error on the Lenovo X201i (ME version 6.0).
Change-Id: I5eb0da7663e795f790e2723bb334447380724b56
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Update the config files to 1.8.13
- Unify the coreboot and coreboot_simple configs. The only difference
now is that coreboot uses the graphviz library to generate call graphs
and other things, while coreboot_simple does not. This means that the
doxygen_simple target builds in just over a minute, while the doxygen
build target takes roughly an hour.
- Both targets now only document coreboot proper. While at times it
might be useful to see links to code from src/vendorcode, 3rdparty, or
util, these directories also really clutter up the doxygen output. To
make it easier to see the coreboot code, all of these directories are
excluded.
Change-Id: Iefc667ee2f65859f151f5a97b7b9d182e8ed31f7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Because the tegra124 & tegra201 lp0 builds weren't junit tests, the
builds weren't actually picked up by jenkins, so any failures were
not previously reported.
Change-Id: Ie443ca713912d01ccf6921ce49f846d7297163ef
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26422
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
The function prototype for "struct device *add_cpu_device"
is already correct and doesn't need to be fixed.
Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file
from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed
everything that we don't need. I did have to change
MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00.
This struct is used to extract the timestamps from AGESA.
BUG=b:64549506
TEST=built on grunt
Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 64KB to the reserved memory used for stage_cache. This corrects
an error observed when using a debug build of the AGESA blob.
Messages on initial boot
AGESA: Saving stage to cache
Error: Can't add stage_cache 57a9e101 to imd
and during resume
AGESA: Loading stage from cache
Error: Can't find stage_cache 57a9e101 in imd
TEST=boot/suspend/resume Grunt with debug and release builds
BUG=b:79154155
Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The firmware_Mosys FAFT test does not allow RW_SECTION_A, RW_SECTION_B or
RW_SHARED to be 0-sized, nor located at offset 0x00000000.
Swap UNIFIED_MRC_CACHE and RW_SECTION_A to pass this test.
BUG=b:79865447
TEST=test_that -b grunt ${IP} firmware_Mosys
Change-Id: If60919fd998ac786d58a5a258d7b5ded727db64b
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables the new bootblock compression feature on RK3399,
which requires moving MMU initialization into the decompressor stage and
linking the decompressor (rather than the bootblock) into the entry
point jumped to by the masked ROM.
RK3399's masked ROM seems to be using a bitbang SPI driver to load us
(very long pauses between clocking in each byte), with an effective data
rate of about 1Mbit. Bootblock loading time (as measured on a SPI
analyzer) is reduced by almost 100ms (about a third), while the
decompression time is trivial (under 1ms).
Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the CCACHE_EXTRAFILES variable to the list of exported
environment variables, which can be useful as a target-specific variable
to make ccache aware of extra dependencies that it cannot figure out on
its own. It also adds a CPPFLAGS parameter to define the __BUILD_DIR__
constant for the preprocessor so that the current output build directory
can be referenced in C code if necessary.
Change-Id: I4fdd08842972cfed8ef5e5a61ebf859c0571bcfb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch moves the objcopy invocation that changes the bootblock's
section flags to make sure .data and .bss are preserved in the binary
image from the generation of bootblock.raw.bin into a separate
bootblock.raw.elf file. Some SoCs (like SDM845) like to have an ELF
rather than a raw binary as input to their masked ROM wrapper
generation script.
Also move those objcopy flags out into a variable because I'll need them
again in a later patch.
Change-Id: I9557b184df7f753a442c7e0ceb58e81c5e19f2c5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26338
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new "rawcompress" command to cbfs-compression-tool,
that works exactly the same as "compress" except that it doesn't add the
custom 8-byte header to the file. This can be useful if you need to
compress something into a format that coreboot's decompression routines
can work with, but it's not supposed to go into CBFS.
Change-Id: I18a97a35bb0b0f71f3226f97114936dc81d379eb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bip should have different devicetree entries than Yorp; it doesn't have
a DA7219 audio codec (instead it uses ALC5682).
BRANCH=none
BUG=b:79771967
TEST=boot, no longer see DA7219 ACPI in console.
Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/26342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch adds two minor improvements to the way cbfs-compression-tool
parses the compression algorithm type that is passed through the -t
option of the 'compress' subcommand. These improvements are intended
to prevent accidents and unexpected behavior when using the
cbfs-compression-tool, in particular in automated contexts such as a
Makefile rule.
In the first part of this patch, a return statement is inserted after
the 'if (algo->name == NULL)' check of the compress() function. This
causes the function to exit immediately and subsequently abort the
program when the algorithm type was not detected correctly. Previously,
execution would continue with the 'algo' pointer pointing to the zeroed
out stopper entry of the types_cbfs_compression[] array. The ultimate
effect of this would be to pass 0 as 'algo->type' to the
compression_function() function, which happens to be the same
enumeration value as is used for CBFS_COMPRESS_NONE, leading to a valid
compression function result that matches the behavior of no compression.
Thus, if a script calling cbfs-compression-tool compress contained a
typo in the -t parameter, it would continue running with an unintended
compression result rather than immediately exiting cleanly.
In the second part of this patch, the strcmp() function is replaced with
strcasecmp() when comparing 'algo->name' with the 'algoname' parameter
that was passed to the compress() function. strcasecmp() uses an
identical function signature as strcmp() and is thus suitable as a
drop-in replacement, but it differs in behavior: rather than only
returning a result of 0 when the two NULL-terminated input strings are
character by character identical, the strcasecmp() function applies a
weaker concept of identity where characters of the latin alphabet
(hexadecimal ranges 0x41 through 0x5a and 0x61 through 0x7a) are also
considered identical to other characters that differ from them only in
their case. This causes the -t parameter of cbfs-compression-tool
compress to also accept lowercase spellings of the available compression
algorithms, such as "lz4" instead of "LZ4" and "lzma" instead of "LZMA".
As an unintended but harmless side-effect, mixed-case spellings such as
"lZ4" or "LZmA" will also be recognized as valid compression algorithms.
(Note that since the character "4" (hexadecimal 0x34) of the "LZ4"
compression type name is not part of the above-mentioned ranges of latin
alphabet characters, no new substitutions become valid for that part of
the "LZ4" string with this patch.)
Change-Id: I375dbaeefaa0d4b0c5be81bf7668f8f330f1cf61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Stack smashing was detected during raminit when not loading from MRC.
Adding CAR_GLOBAL to a struct inside raminit was suggested in
https://mail.coreboot.org/pipermail/coreboot/2018-May/086677.html in
order to fix the problem.
Adding CAR_GLOBAL to the ram timings variable solves the issue (adding
it to the ram_training or raminfo struct had no effect).
This is just a workaround and might need a proper fix in the future.
Tested on Lenovo X201i with 2+2 and 4+4 GB RAM.
Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/26388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Up to this point, junit.xml has only been used to build tools, as abuild
has handled the coreboot builds. To add additional tests not covered
by abuild, we need junit.xml to work with bare directories.
This also requires updating the build directory (BLD_DIR) for existing
builds using the junit.xml target.
Change-Id: If6e27e02e25e20f48e5a9372373de6058ca378dd
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
We use packed structs with unaligned members all the time, which is the
entire point of us using the packed attribute.
Change-Id: Ib26b422ba83257d1a7f26134ee20217fad5823cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It turns out that even with the `-gnatp` switch to suppress runtime
checks, the compiler is still allowed to generate them (it only doesn't
have to). If we can't control generation of checks, we also can't
make assumptions about propagation of their exceptions.
The compiler warning that led to this change seems spurious, though
(the check might be generated, but is dropped later). So we might
revert this decision if the compiler can be fixed.
Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch ensures that user can select a specific AP to run
a function.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
compare_timestamp_entries will fail for entries that are different by
at least 2^32 since entry_stamp is 64-bit and the return for compare
is 32-bit. This change fixes compare_timestamps by actually comparing
the entries to return 1, -1 or 0 instead of doing math on them.
TEST=Verified that "cbmem -t" sorts entries correctly on previously
failing entries.
Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the recent change 4c518e1 (timestamp: Add timestamps for TPM
communication) to add more timestamps for TPM communication, now we
are overflowing the TIMESTAMP region in verstage. This change
increases TIMESTAMP region size to 512 bytes to accomodate this.
BUG=b:79888151, b:79974682
Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
As I mention in the comment, this is valid ASL, which was added as
a warning with the comment "This would appear to be worthless in
real-world ASL code." While code using empty resource templates
could probably be rewritten, this seems like an arbitrary choice
to generate this as a warning, since it's valid.
This gets rid of warnings such as this one:
dsdt.aml 2975: Return (ResourceTemplate() {})
Warning 3150 - Empty Resource Template (END_TAG only)
Which is generated by this code in google/rambi/acpi/mainboard.asl:
Method (_CRS)
{
/* Only return interrupt if I2C1 is PCI mode */
If (LEqual (\S1EN, 0)) {
Return (^RBUF)
}
/* Return empty resource template otherwise */
Return (ResourceTemplate() {})
}
Change-Id: I9cfe9069c738a284aa85feada9d58e1aee97e433
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26352
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Describe the USB devices in the devicetree so they can get
generated into the SSDT and presented to the OS.
This was tested on an eve board and the resulting SSDT was
verified to show the expected values in _UPC and _PLD.
Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb. This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default. The _PLD can also be customized for more accurate
descriptions if necessary.
This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB 2.0 Type-A""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
end
end
end
It will generate the following ACPI code in the SSDT:
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB 2.0 Type-A")
Name (_UPC, Package (0x04)
{
0xFF,
0x00,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "RECTANGLE",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
)
}
Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of just checking the immediate parent for an device name,
walk up the tree to check if any parent can identify the device.
This allows devices to be nested more than one level deep and
still have them identified in one place by the SOC.
Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common mrc cache driver allows to save the raminit training
results to a separate fmap region which is more manageable than a
cbfsfile.
Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
In case the Option ROM isn't a multiple of 4KiB the last buffer was
truncated to prevent a buffer overrun. But tests on nouveau showed
that nouveau expects a buffer that has the requested size and is zero
padded instead.
Always return a buffer with requested size and zero pad the remaining
bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple
of 4 KiB.
Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
The `-t` argument was never required for `add-payload` and results in
a warning now because the type was renamed.
TEST=Built with BUILD_TIMELESS=1 and compared binaries with and without
this patch.
Change-Id: I6ccb70acc6e88a602b90c625040d4f05d8e3630a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26323
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CNVi wifi/bt module prevents entry into S5 by keeping internal
SoC clocks running. Therefore it's necessary to disable BT prior to
S5 entry.
BUG=b:79606769
TEST= Test if BT device works under following cases:
1. Power-on
2. Press powerbtn before OS entry
3. Power-on from S5 again
Change-Id: Ibc14b4080a27de48d197e16d0eed162603482de2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a valid ACPI path for coreboot's SSDT generators.
Fixes all ACPI errors found while booting GNU Linux 4.15 on
Lenovo T410.
Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Increase AP timeout limit for sgx_configure function. As per debug log
sgx_configure was not successful on all cores with given timeout value.
TEST=Ensures no timeout error in AP function execution.
Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
To calculate the CBMEM address we need to determine the framebuffer
size early in the ROMSTAGE. We now do the calculation before
cbmem_recovery() and configure the memory controller right away.
If the calculation was done from cbmem_top() instead, we'd loose some
logging that seems useful, since printk() would recurse to cbmem_top() too
with CONSOLE_CBMEM enabled.
If we didn't configure the memory controller at this point, we'd
need to store the result somewhere else. However, CAR_GLOBAL is not
practical at this point, because calling car_get_var() from cbmem_top()
would recurse back to cbmem_top().
Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.
BUG=b:72974136
TEST=Match the result.
Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.
BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.
Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the following changes to the blobs repository:
78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.
Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Program the Super I/O to turn the machine on or restore its power state
when AC power is restored.
Based on code from src/superio/nuvoton/nct5572d/superio.c.
Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/25463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.
Required to support PC keyboard and PC mouse at the same time.
Tested on Lenovo T500.
Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It’s unclear why this option was commented out. Activate the line, and
copy the CMOS layout and defaults from qemu-i440fx.
TEST=Boot 2.11.1(Debian 1:2.11+dfsg-1ubuntu7) and see that nvramcui
works. A changed value doesn’t survive a reboot though.
Change-Id: Ieef86f092d323c68a6d2d0cc6c04c395f743a935
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26265
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix dual LAN sku can't inherit correct MAC from VPD setting.
BUG=b:77836343
BRANCH=Fizz
TEST=Program the mac address to VPD in shell
vpd -s ethernet_mac0=<mac address1>
vpd -s ethernet_mac1=<mac address2> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/25587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is a special case for the Fizz firmware branch, when the device index
is 1, it will check "ethernet_mac" first and then "ethernet_mac0".
For single NIC: config.device_index = "1", maps to "ethernet_mac"
For multiple NICs: config.device_index = "1", maps to "ethernet_mac0"
BUG=b:77836343
BRANCH=Fizz
TEST=Add device index in device tree &&
Program the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/26051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.
Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.
Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some cases callers want to know if a file
exists and, if so, what its type is.
Modify cbfs_locate so that if the pointer is non-NULL,
but has the value 0, the type of the file that
matches the name will be returned.
Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update the gpio configuration structure to the intelblock format.
The resulting configuration is functionally similar (even if some
bits are not identical).
Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25424
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).
- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock
Note: There is no functional change in this patch.
Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The NPCD378 can be found on at least:
* HP Compaq 8200
* HP Compaq 8300
The datasheet is not publicly available, as HP implements lots of
custom hardware. Add basic support for it, based on HP Compaq 8200.
The first eight LDNs seem to be standard nuvoton compatible, except for
LDN4, which is used to control front LED and power in ACPI S3.
LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's
IOBASE with a size of 0x100 bytes.
The HWM consists of 16 pages with each holding 0xff bytes. The pages can be
selected by writing the page index to IOBASE + 0xff.
TODO:
Reverse engineer the HWM to support fan control.
WARNING:
The remaining LDNs have been guessed and might be wrong!
The serial has been tested and is working.
Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25384
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to extend the MP callback infrastructure prepare for
easier changes by making the AP callback get signalled by a
single pointer to a local variable on the signaller's stack.
When the APs see the callback they will copy the structure
to a local variable and then set the acknowledgement by
clearing out the slot.
The reading and writing to the slots were implemented using inline
assembly which forces a memory access and a compiler barrier.
BUG=b:74436746
Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some things in programming registers related to dual channel
interleaved operation were wrong.
This also adds some code that could in the future be used when me is
active and claims some memory for its UMA.
This also uses some more sensible variable names to clarify at least
some of the magic.
This fixes memtest86+ failing with some assymetric DIMM configuration.
TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM
configuration setups (would instantly fail at addresses above 4G on
many configurations).
Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add an lpc_acpi_name function to report its namespace as "LIBR"
rather than some fallback value which seems to vary. This repair
is required for the LPC TPM device to register its presence
without blowing up the table and preventing the payload from
seeing the SATA device.
Before change (but after other similar change to PCI0), the
TPM device reported itself as:
\_SB.PCI0.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LIBR.TPM
which is consistent with the tables AGESA generates.
Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a function domain_acpi_name to return "PCI0", rather than
falling back to the parent' device's "\_SB" label. This repair is
required for the LPC TPM device to register its presence without
blowing up the table and preventing the payload from finding SATA.
Before change, the TPM device reported as:
\_SB.\_SB.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LPC0.TPM
A separate change submission will correct "LPC0" as well.
Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I'm increasing the max because when AGESA tracing is enabled it will use
over 120 entries. I added some padding to the number incase more probes
are added. This only affects ramstage so the extra ram shouldn't matter.
BUG=b:64549506
TEST=boot on grunt and ran cbmem -t
Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This will allow loading of programs that are more than one type,
e.g. ramstage type might now be a stage or payload.
Further, unknown types of 0 are dangerous, make it a real value.
Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
If the timestamp entries are added out of order, the duration
calculation will be wrong.
AGESA collects timestamp data through all the stages. Then in AmdInitPost
it asks for a buffer to write TP_Perf_STRUCT into. agesawrapper will then
take the data and call timestamp_add on each entry. This results in
the entries being out of order.
TEST=Built firmware for grunt that manually added entries and then ran
cbmem -t/-T to verify the entries were in the correct order.
Change-Id: I6946a844b71d714141b3372e4c43807cfe3528ad
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26168
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is based on the code from the 8470p port. Tested on the quad
core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics
cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The
laptop must be completely disassembled down to the motherboard to
perform the initial flash, subsequent flashes can be done internally
via flashrom. There is a simple mod that can be performed to make
subsequent external flashes easier in case of a brick, I'll put more
information on this on the wiki later. The lack of an MXM structure
built in to the firmware causes the GPU to enter a mode with nerfed
performance, there is a workaround though, I'll add this to the wiki
as well. I have no info on EHCI debugging.
Tested and working:
- memory: 4G+4G, 4G+4G+4G+4G
- Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload
with graphics init disabled in coreboot. I allowed SeaBIOS to load the
VBIOS from the MXM.
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- VGA
- DisplayPort
- Audio
- Both HDD SATA ports, ODD SATA, eSATA
- S3 with SeaBIOS 1.11, SERCON must be disabled
- Brightness and volume FN keys
- Mute and calculator hotkeys
- Status LEDs
- Bluetooth
Not working:
- GRUB2 as payload will freeze. Has something to do with at_keyboard
module. The built in keyboard requires this module to function though.
- Sleep FN key
- WiFi toggle and internet browser hotkeys
- S3 fails to resume (restarts) if the laptop is removed from AC power,
or gets unplugged and then plugged back in while suspended. Sleep
status LEDs remain normal during this process.
Change-Id: Ic4ff64e9cf0c7a51ac48ca2fe6fe8beab02e9f9a
Signed-off-by: Robert Reeves <xiinc37@gmail.com>
Reviewed-on: https://review.coreboot.org/23651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Copies the common/env_ctrl support code from the it8728f driver.
Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload,
and booting userspace without a kexec call.
Prior to this change, an error was given during boot:
it87 it87.656: Detected broken BIOS defaults, disabling PWM interface
After this change, the message is gone, and PWM fan control works
through the /sys/class/hwmon interface.
Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26224
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.
BUG=b:79396300
Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.
BUG=b:79562868
Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms
BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different
Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Convert the purism/librem13v1 to a variant setup, in
preparation for adding the librem15v2 board as a new variant.
The Librem 13 v1 and Librem 15 v2 are nearly identical, so
this minimizes new code to add support for the latter.
Also update the URL in board_info to an archive.org link.
Change-Id: I00bb82b9e895e2464ddaa92915c01ce0e35933a2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit adds support for writing ACPI _PLD structures that
describe the physical location of a device to the OS.
This can be used by any device with a physical connector, but is
required when defining USB ports for the OS.
A simple function is provided that generates a generic _PLD
structure for USB ports based on the USB port type.
Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit adds support for writing ACPI _UPC structures that
help describe USB ports for the OS.
This is a simple structure format which indicates what type of
port it is and whether it is connectable. It should be paired
with an ACPI _PLD structure to define USB ports for the OS.
Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.
BUG=b:79444337
TEST=booted on atlas
Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This keeps Audio clock and data pins ON in S0ix to support
Wake on Voice.
BUG=b:77605180
BRANCH=none
TEST=Checked that S0ix suspend/resume works. Validation of WoV
was done on glkrvp previously. For Yorp, audio topology firmware
updates are required for testing WoV.
Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the blobs submodule marker forward to include the following:
b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.
Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The patch series ending in 64049be (lib/bootmem: Add method to walk OS
POV memory tables) expanded the bootmem framework to also keep track of
memory regions that are only relevant while coreboot is still executing,
such as the ramstage code and data. Mixing this into the exsting bootmem
ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE
boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE
which ends up getting translated back to LB_RAM in the OS tables. This
was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to
OS) for this specific case, but unfortunately Arm boards can have a
similar problem where their stack space is sometimes located in an SRAM
region that should not be made available as RAM to the OS.
Since both the resources made available to the OS and the regions
reserved for coreboot can be different for each platform, we should find
a generic solution to this rather than trying to deal with each issue
individually. This patch solves the problem by keeping the OS point of
view and the coreboot-specific ranges separate from the start, rather
than cloning it out later. Ranges only relevant to the coreboot view
will never touch the OS-specific layout, to avoid the problem of losing
information about the original memory type of the underlying region that
needs to be restored for the OS view. This both supersedes the
RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards.
Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
A name cannot be defined and declared external in the same table (GPID)
A name cannot be defined and declared external in the same table (CTOK)
Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26122
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Video Bios Table to improve user experience when running
coreboot's blob free graphics init.
As it's not a binary blob it should not be added to the blobs repo.
This is taken from vendor BIOS and contains purely documented
configuration data, so it should not be subjected to copyright.
Extracted using intelvbttool with applied patch
I8cbde042c7f5632f36648419becd23e248ba6f76 "util/intelvbttool: Rewrite tool"
Change-Id: I15573ddd37ee9738df1f7178f967131687a50f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Incorrect interrupt routing configuration prevented handling
interrupts for devices behind PCIe bridges 00:02.1 and 00:02.5.
With the new configuration, devices work as expected.
Tested with Linux 4.10 booted with the "pci=nomsi" parameter.
Change-Id: I3c95be7ba6207697afc7983d4b5f9d9a28584723
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Vendor code has several headers included into source code that are not
needed in order to build them. Remove unneeded #include. This is part of
controlling the build of unneeded procedures within vendor code.
BUG=b:78610011
TEST=Build grunt.
Change-Id: Id7d451b6be564632836fc64fd343131edb85183a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.
BUG=b:74617340
Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current PCH UART support for console is limited to UART2.
This change adds support for specifying UART0 or UART1 to be
used instead by changing CONFIG_UART_FOR_CONSOLE in the board
level Kconfig. The default is still 2.
This is tested with a board that uses UART0 for debug output.
Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/26140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From coreboot side, include DMIC 4ch NHLT configuration and its
DMIC blob. In OS side, cras picks the needed channels using UCM's
channel map configuration.
So, this patch updates to include DMIC 4ch config.
BUG=b:79158926
TEST=Verified 4-ch record with arecord
TEST=Also verified internal mic record with cras using
'cras_test_client --capture_file dmic.raw --rate 48000
--num_channels 2 --duration 10'
Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses GPIO macro to define rt5663 headset codec's irq as
ExclusiveAndWake. This change allows jack detection even when
device is in D3 state.
TEST=Plug in/out jack when the system is in deep sleep and wake up
the system to ensure that jack insertion/removal is detected.
Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26016
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new macros to define gpio with an option to either
enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable
it (mark it as just Exclusive flag in SSDT).
Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/25838
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.
Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Advanced Error Reporting capability was hardcoded in the PCIe
extended capability list, but it might not always be possible.
The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.
Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I finally found out why disabling the L1 sub state option did not
prevent some NVMe drives from locking up in L1 substate. I expect
that the disabled L1 substate initialization that coreboot does
is negated because Linux might itself configure it if it finds the
capability enabled on the PCIe root port.
Removing the capability from the PCIe root port when L1 sub states
are disabled in the configuration should fix the problem.
This was not tested because it's a difficult issue to reproduce and
I do not have the problematic hardware that caused it anymore.
Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add documentation for MP service PPI using EFI interface
on Intel 9th Gen Platforms.
Documented so far:
* Problem Statement
* New Design Proposal
* API interface
* Code Flow changes
* Benefits
BRANCH=none
BUG=b:74436746
TEST=none
Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25921
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This gpio should be active low, but is not currently configured that way.
Changing gpio configuration to reflect that.
BUG=b:73121017, b:77941823
BRANCH=None
TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen
is ejected, gpio is low and when pen is inserted, gpio is high.
Also tested that wake upon pen eject is working.
Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
BUG=None
TEST=Build pass Intel mainboard with 20180427 iasl.
Change-Id: I153e7d0e97f9a29919676fbb73a7c26fd22f252c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/26045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch does the following:
1. Copies mainboard/intel/camelback_fsp to mainboard/ocp/monolake
2. Adds Kconfig files to mainboard/ocp
3. Makes minor board-specific changes (board_info.txt, Kconfig
variables)
The OCP Mono Lake platform consists of up to 4 single-socket Xeon
D-1500 microservers in a Yosemite v1 chassis. More info is available
at http://www.opencompute.org/wiki/Server/SpecsAndDesigns.
Signed-off-by: David Hendricks <dhendricks@fb.com>
Change-Id: If358162abe67e9411fd2514d48f3b3411da15f68
Reviewed-on: https://review.coreboot.org/25669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Skylake used the inner function, wrapping it in the same set of tests as
the common code does, but expressed differently.
Change-Id: Ifa6912255e7874a6e80301d49128adda6f624209
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26037
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing logic to set up CsMux67 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
Commit cf1cb5b2d4 did the same
for CsMux45 but missed this one.
Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25994
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.
Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.
Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add device tree options to enable beeps when exceeding temperature,
voltage, and fan limits. As of this commit, setting voltage and fan
limits is not implemented.
Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a method to walk bootmem memory tables and call a function
for each memory range. The tables might not match with OS sight
of view.
Return true if the callback function returned false.
Required for FIT support in coreboot to find a usable RAM region.
Tested on Cavium SoC.
Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Non-dts based systems can pass mclk to da7219 driver by
this property.
BUG=b:74570989
TEST=Enabled clock in kernel driver using the property
Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit edf2f59b1d.
(google/kahlee: Resume on AC insertion)
The requirement to wake on AC insert is just to wake enough to charge,
not to wake the entire system.
BUG=b:77602394
TEST=None
Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add raydium controller
- Update elan controller with reset and enable GPIOs.
- Enable 'probed' so Linux will check which controller is being used.
BUG=b:78929054
TEST=Both elan and raydium touchscreen controllers work
Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix (assumed) regression with commit
ac63b41 vendorcode/amd/agesa: Fix variable length array declaration
The code used sizeof() on the struct where array length was
previously adjusted, but only f14 case was fixed accordingly.
Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26036
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Definition of S_PSTATE only allowed PStateStruct[0], while it is
effectively used as a flexible array. Since sizeof(S_PSTATE) is
reduced here by sizeof(S_PSTATE_VALUES), we have to account for
that when calculating PStateLevelingSizeOfBytes.
In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference.
GCC 7.2.0 warns about an out of bounds array subscript.
```
CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain':
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds]
PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
Change-Id: If9598a951c6b882432689b677a956c44650c7083
Found-by: gcc (Debian 7.2.0-2) 7.2.0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21297
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I get the error below when using the following command in combination
with sudo:
sudo command -v $SOME_COMMAND
sudo: command: command not found
Detection of the cbmem path is working fine without sudo.
Change-Id: I8788c190ffebde117e2abd3df924c48d8f6fd05d
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There might be certain requirement in user function where user
might not want to pass any timeout value, in those cases
run_ap_work() should consider infinity as timeout and perform
all APs initialization as per specification.
Set expire_us <= 0 to specify an infinite timeout.
BRANCH=none
BUG=b:74436746
TEST=run_ap_work() is running successfully with 0 expire_us.
Change-Id: Iacd67768c8a120f6a01baaa6817468f6b9a3b764
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25622
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In each stage keep GDT in the code region. This accommodates
platforms, such as glk, that are executing out of CAR. The
gdt is small and loading it is trivial so just do it unconditionally
instead of introducing another Kconfig.
BUG=b:78656686
Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK,
remove the complications in assembly_entry.S. There's no platform
utilizing romcc bootblock and needing to handle verified boot after
bootblock as well as not using verified boot. That combination makes
things very complicated. Clean up the complication as it's not a
combination that needs to be supported.
BUG=b:78656686
Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25968
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot on skylake originally did ship with romcc bootblock and
verstage running after it. However, that configuration makes boot
flows very complicated. No platform in the current code base uses
this combination. Make VBOOT_STARTS_IN_BOOTBLOCK depend on
C_ENVIRONMENT_BOOTBLOCK.
BUG=b:78656686
Change-Id: Ia9446f209521f71c91b83d579b9e2d89744292bc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
The tablet event handler method TPET is defined as an extern, then
defined again in skylake, the only platform that supports it. In newer
versions of IASL, this generates an error, as the method is defined in
two places.
Remove the extern and the CondRefOf check. That's not needed if we
only set the EC_ENABLE_TABLET_EVENT define on platforms that have a
TPET handler.
Change-Id: I8bee069fc95637446593dfaaae1254e931421517
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't
exist in the apollo lake code. Remove it from reef as part of the
cleanup to update to the new version of IASL.
This was in commit 4f803ac28f (mainboards/google/reef: Add support for
tablet mode switch.)
Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up
the boot process by over a half second. Also, increase the Normal
Read speed to 33MHz as supported by the W25Q128FW.
BUG=b:70558952
TEST=Run cbmem -t to get boot times.
Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's pretty well compressible which helps when space is tight.
The code encodes the assumption that the VBT is 8kb or less. Haven't
seen a larger one yet.
BUG=b:77971803,b:78541692
TEST=build, see that vbt.bin is compressed, boot, check log that the
reported VBT size is correct.
Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SPI chip in this board needs a custom OPMENU, otherwise flashrom
fails halfway during the write.
From the default OPMENU, Block Erase (0xd8) has been replaced by AAI
write (0xad) and Fast Read (0x0b) by Write Disable (0x04).
Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The X201 coreboot image is working well on the X201i. Besides, the
X201i seems to be almost identical to the X201 except for the CPU.
Change-Id: Iecc84faf78e7de34fb1add63c20904a5a28c5e9b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix regression after commit
7f5efd9 intel/bd82x6x: Use generated ACPI PIRQ
The call to inject generated PIRQ entry was not added when
the static entries as default_irq_route.asl file was removed
from boards using intel/nehalem southbridge.
Change-Id: I8097c1ab729d1eb91a6d547ef13948c1e21eca10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/25965
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes in pin usage between yorp and bip
- LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66
- I2S0 interface is not used in bip. It was used in
yorp for DMIC Wake on Voice through Nuvoton EC.
Also fix both bip and yorp pin settings for
LTE_OFF_ODL (Enable LTE and add an internal pull up).
Internal pull up can be removed later when sub-board (which
will have an external pull up for this signal) is available.
BUG=b:77869623
BRANCH=none
TEST=Build coreboot for octopus.
Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fixes a bug in the software_i2c (bitbang) framework where it
would previously not return an error when receiving a NACK on a write
transaction (deviating behavior from our hardware I2C drivers). It also
adds explicit error codes to be returned for the different kinds of
failure conditions so they are more useful for debugging when dumped.
Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Programming CxDRB should be cumulative as explained in "Intel ® 4
Series Chipset Family datasheet".
This does not seem to have any real impact but better do according to
the documentation and what vendor firmware does.
This also removes some dead code.
Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22911
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This training find the optimal write DQ delay and read DQS delay
settings. It does so on all lanes at the same time, like
vendor (training each lane individually has poor results).
The results are stored in the sysinfo struct and restored on next
boots and S3 resume.
This potentially increases stability as optimal settings are chosen
and is more necessary for DDR3 raminit where the write DQS delays are
leveled/variable due to the flyby topology.
TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the
results are quite close to the safe original ones (that previous
worked fine) and tested with memtest86+.
Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)
and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR
register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue
which became apparent with commit d533b16669.
More detailed, either setting the LSB of the 32 bit register at 0x98
of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or
setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the
intel_model_2065x_finalize_smm function) indepentenly causes a freeze
during bootup or a complete session loss on resuming from S3 as described
here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html
It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.
Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile
Processor Series, Datasheet Volume Two" indicates that registers of the
PCI device 00:00.0 cannot be locked manually. Instead, they can only be
locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.
Finally, the addresses and sizes of these registers were partially wrong.
Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT
support compared to the Core i5 and Core i7 processors of a X201).
Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25914
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Adapt to coreboot coding style.
* Use coreboot's endian conversion functions.
* Fix header and header guards.
* Get rid of unused functions.
* Add Kconfig to build it on ramstage.
* Replace size32 with ALIGN_UP and DIV_ROUND_UP.
* Add NULL pointer checks
* Convert constants to defines
Required for Cavium's BDK and uImage FIT support.
Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Besides the FSP codepath, Sandy Bridge has two codepaths, one native
and one in the form of a binary. This allows the use of the binary.
This can be useful to find flaws in the native raminit.
The native raminit is still selected by default.
Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
After commit 2188f57a (src/device: Update LTR configuration scheme)
coreboot will hang when reading resources on the ASMedia SATA
controller, although there is already an ASPM config override. So use
the ASPM blacklist driver instead of setting the ASPM override in the
devicetree.
Change-Id: I807d9bd4deef8c1528dff96c7646240ef75e1953
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/25819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures GPP_A23 as a wake source for the trackpad. We also
need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any
interesting signals in GPP_B, so we won't be missing it.
I don't have hardware with A23 wired up, so i just tested the wake
source using A19 which is essentially identical to A23.
BUG=b:78541883
TEST=verified we can trackpad can wake system from suspend
Change-Id: If800464c8b2319d758b1823850571919f85bdc6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port
is connected to a device with alternate mode(s) and the call is made
for the mode with the index higher than 0 (e.g. Zinger).
Cros EC manages alternative modes entered in an array (amode[]). The
command is designed to accept a query for an particular index and a
particular SVID.
Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries
first time for DisplayPort with index=0, EC says 'no' as expected.
AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00)
is sent instead because cmd_code is cleared by google_chromeec_command.
res.svid is supposed to be 0 when EC hits the last index + 1 but
res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because
EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to
the next index and this repeats forever.
Any USB-C device with non-DisplayPort alternate mode can cause this
hang unless HDMI port is used.
This patch resets all the fields of chromeec_command in each iteration
in case google_chromeec_command changes them.
BUG=b:78630899
BRANCH=none
TEST=Verify Fizz boots without monitors on Zinger. Verify the svid
enumeration happens as expected.
Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/25878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All ARM architecture boards are supposed to have a TTB region for their
page tables. ARM systems cannot use the data cache without enabling
paging, so it is imperative to do that as soon as possible. They will
also fault on unaligned accesses when not using the cache, which breaks
assumptions in CBFS code.
Unfortunately, we have some old boards in various stages of disrepair in
the tree that don't always follow these sorts of standard conventions.
It's not clear whether they actually boot anymore and if anyone still
has the respective hardware available to maintain them. I cannot really
fix and test them right now, but we should at least create a fake TTB
section for them so that common architecture code may make the correct
assumptions about which regions exist.
Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the
IOAPIC[0] and panics otherwise.
This might be a Linux bug. The MP Specification 1.4 does seem to mandate
sequential ordering for bus entries, but not for the I/O APICs.
Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.
BUG=b:78009842
Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
scan-build from Clang 4.0.1-3 from Debian Sid/unstable warns about the
issue below.
```
CC ramstage/southbridge/amd/cimx/sb800/lpc.o
src/southbridge/amd/cimx/sb800/lpc.c:102:6: warning: Value stored to 'end' is never read
end = resource_end(res);
^ ~~~~~~~~~~~~~~~~~
1 warning generated.
```
The variable is only used in the commented out print statement. So,
remove the unused variable, and directly use the value directly in the
print statement.
Change-Id: I3f759f6361ffeb07980cb10e17930e11d738a6a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This variable needs to be in byte so a division by 8 needs to happen.
This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD
decode and timing selection", but was probably not encountered because
such dimms are rather uncommon.
Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22991
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression after commit
0cc2ce4 arch/x86: Clean up CONFIG_SMP and MAX_CPUS test
In case PARALLEL_CPU_INIT=y BSP CPU no longer waited for APs to stop
before proceeding to next bootstates or device initialization.
Change-Id: Ie47e7896ed3d57d98a3ce6766e5c37b6dc22523b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/25874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, native VGA initialization takes 90 ms during resume. But, it
is not needed. So, skip it to save that time.
Note, it is assumed that ACPI aware operating systems ship the
appropriate drivers to initialize the graphics device. With Linux, if
the module/driver *i915* is not loaded, then the display will stay
black.
TEST=On Lenovo X60t with Debian and Linux 4.15.11-1~bpo9+1, suspend and
resume system and notice display is correctly initialized by the driver
i915 after resume. Notice the messages below.
```
PCI: 00:02.0 init ...
Skipping native VGA initialization when resuming from ACPI S3.
PCI: 00:02.0 init finished in 56 usecs
PCI: 00:02.1 init ...
```
Change-Id: I6cc9dde94c18671d077132daf648e8ba557e7887
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25676
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This helps with meeting the line length limit.
Also, join some lines with the one above, as the line length is now met.
Change-Id: If457b3b592211aba1a3218501146b17abb5b799f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change configures a weak internal pull-up on ESPI_IO1 line for
octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and
is expected to be open-drain. However, there is no external pull on
this line and so an internal pull-up is required to ensure proper eSPI
communication.
BUG=b:78497502
TEST=Verified that there is no eSPI communication failure between AP
and EC during boot-up and on suspend/resume.
Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Add support and enalbe cache-as-ram paging for glk to work around
a cache-as-ram corruption issue. glk executes verstage, romstage,
and FSP-M directly out of cache-as-ram (just like apl). However,
the front end on glk is very agressive about pulling cache lines
into L1I for potential execution. When the snoops hit in the L1D
and the cache lines are dirty the processor writes the line back.
However, there is no backing store for the dirty lines to go. As
such when the line is pulled back in the value is all 0xff's,
corrupting cache-as-ram.
To fix the issue one needs to enable paging with NX (no execute)
permissions which prevents the above actions from happening because
the TLB will indicate that shouldn't be fetched into the instruction
cache since data will be marked no execute.
The generated page tables are added to cbfs and only added to the
COREBOOT cbfs as they are only consumed in the early cache-as-ram
stages.
The page tables generated with:
$ go run util/x86/x86_page_tables.go \
--iomap_file=src/soc/intel/apollolake/glk_page_map.txt \
--metadata_base_address=0xfef00000 \
--pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \
--pt_output_c_file=src/soc/intel/apollolake/pt.c
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xfef00000.
BUG=b:72728953
Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.
This is preparation to have GPIO table/code also declare/program SCI/SMI.
BUG=b:72875858
TEST=Build grunt.
Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following things are specific characteristic of mc_apl1 board
variant:
- initialization for the eDP to LVDS converter
- enable decoding address range for COM 3
- legacy IRQ routing for PCI devices
- wait function for old legacy devices
- set coreboot ready LED
Change-Id: I5c853e6caae6cc880ead436f232cabddeee6d09a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25822
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver relies on I/O space access functions (inb, etc.), which are
only available on x86.
Rather than explicitly disallowing it on ARM, allow it only on x86.
TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not
available in the "Generic Drivers" menu anymore.
Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add a function that will check the various requirements to
enable USB Device Controller (UDC):
- developer mode enabled
- GBB flag set or VBNV flag set
If VBOOT is not enabled, then default is to allow UDC enabling.
BUG=b:78577893
BRANCH=poppy
Change-Id: Id146ac1065f209865372aeb423f66ae734702954
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25847
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock.
This setup is needed when moving AGESA out of the bootblock. It sets the
SPI bus speed of the TPM access in verstage.
BUG=b:70558952
TEST=Boot with AGESA moved out of the bootblock.
Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It was decided to not add the buffers definitions, so the todo message
is obsolete. Replace it with minimum instructions about when a new buffer
will be needed.
It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is
about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO.
BUG=b:77940747
TEST=None.
Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25740
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The grunt touchpad interrupt can be used as a wake source. For grunt,
the touchpad interrupt uses GPIO5 which corresponds to GEVENT7.
BUG=b:77602771
TEST=In OS: # cat /proc/acpi/wakeup
=> D015 S3 *enabled i2c:i2c-ELAN0000:00
TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3.
Change-Id: I510642108a1257f6601f18c77cf3107573427f39
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25827
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO24 maps to GEVENT (GPE) 15.
The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO2 maps to GEVENT (GPE) 8.
BUG=b:78461678
TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3.
TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3.
Change-Id: Ib1809740837e686992ff70b81933159a5dff7595
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses
GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI
definition format a bit to match the format in the baseboard/gpio.h.
BUG=b:78461678
TEST=build coreboot for kahlee
Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Updating from commit id e0b38418:
- image_signing: Add sha1sum of keys in keyset to VERSION.signer.
To commit id 392211f0:
- Update Android signing to support signature scheme v2
This fixes bulding with depthcharge master.
Change-Id: I07b570f54b26a937a5a7c53ade464e0c7a550312
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Now that an idt is available in every stage utilize it for exception
processing to help catch and debug issues.
BUG=b:72728953
Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that assembly code isn't processing the idt gates there's
no need to ensure each vector entry is the same amount of code.
BUG=b:72728953
Change-Id: I2b248b26b9df36d6543163762c74622f79278961
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having
the interrupt handling code available to all stages. In order
to do this the idt setup is moved to a C module. The vecX
entries are made global so that a table of references to all
the interrupt vector entry points can be used to dynamically
initialize the idt. The ramification for ramstage is that
exceptions are initialized later (lib/hardwaremain.c). Not
all stages initialize exceptions when this Kconfig variable
is selected, but bootblock for the C, stages using
assembly_entry.S, and of course ramstage do. Anything left
out just needs a call to exception_init() at the right
location.
BUG=b:72728953
Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fixes the following error when using "make -C Documentation sphinx":
/.../Documentation/Intel/NativeRaminit/Sandybridge.md:32: WARNING:
toctree contains reference to document
u'Intel/NativeRaminit/SandyBridge_registers' that doesn't have a title:
no link will be generated
Change-Id: Id273b8dbc96465833b8e2b2e78c3bac8cd217d4b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add a dash before the links to other files to mark those files as
subpages, and avoid the following error:
reading sources... [ 33%] Intel/NativeRaminit/Sandybridge
Exception occurred:
File "/usr/lib/python2.7/dist-packages/recommonmark/states.py", line 134, in run_role
content=content)
TypeError: 'NoneType' object is not callable
While at it, also spell these filenames correctly: Only
SandyBridge_registers.md is spelled in camel-case.
Change-Id: If92be7d2b61229d0315e1cc5204e951171612fee
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.
This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.
Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When employing PAGING_IN_CACHE_AS_RAM more areas need to be
mapped in at runtime. Therefore, paging_identity_map_addr() is
added to support adding identity mappings. Because there are a
fixed amount of pages in cache-as-ram paging only the existing
paging structures can be used. As such that's a limitation on
what regions and length one can map. Using util/x86/x86_page_tables.go
to generate page tables will always populate all the page directory
pages. Therefore, 2MiB mappings are easy to map in.
BUG=b:72728953
Change-Id: Ibe33aa12972ff678d2e9b80874529380b4ce9fd7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25718
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens will provide further boards based on Apollo Lake. These differ
only slightly. To avoid copying the complete directory of the reference
board we simply create variants that only contain the differences, like
google/reef does.
To further the ability of multiple variant boards to share code provide
a place to land the split-up changes. This patch provides the tooling
by using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing.
The directory layout with a single variant mc_apl1 (which is also the
baseboard) looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/mc_apl1 - code
variants/mc_apl1/include/variant - headers
New boards would then be added under their board name within the
'variants' directory.
No split has been done with providing different logic yet. This is
purely an organizational change.
Change-Id: Ia3c1f45daee3b9690a448b82edbeec552ee05973
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In some cases it may be useful to be able to bitbang a UART, such as
during early bring-up when a driver for the actual controller isn't
available yet. On some platforms we may even want to use this
permanently, such as on the SDM845 where the hardware UART controller
needs to have firmware loaded and is thus unavailable for most of the
bootblock.
This patch adds some helper code that makes it easy to implement this on
a platform, you just have to pass it a function to control the Tx pin
state and it will do the rest. It relies on the mono_time API and is
thus bound to microsecond timing granularity, but that seems to be
barely good enough for 115200 baud if the bit times are calculated
carefully.
Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's going to be necessary to know the i/o hole size as well
the amount of memory configured in the sytsem. Therefore, add
two helper functions:
memory_in_system_in_mib()
iohole_in_mib()
Both return values in units of MiB.
BUG=b:72728953
Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25738
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's broken for years and nobody noticed (%ei for %esi and stackerr for
.Lhlt). It would also leave CAR not zeroed out.
Change-Id: Ib1ca8e8e71ea8d1bf834c349fd6e2ca81538b6eb
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We need to ensure the cache as ram area is set to all zeroes so that
car_migrated works.
Despite a comment claims the previous value is a test pattern it's
actually not used for any testing. Drop the comment too.
Change-Id: I1c91acbca8a860c2ed9c691d08d18718604682d8
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch sets the NPK device off for octopus.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not
report "PCI: 00:00.2 not found, disabling it".
Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Found-by: Coverity (CID 1387031: Memory - illegal accesses
(BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of
19 bytes on destination array "dimm->module_part_number" of size 19 bytes
might leave the destination string unterminated. Fix the size parameter.
BUG=b:76202696
TEST=Build and boot kahlee, using special debug code to see the output
strings, which was later removed.
Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When GPIO tables were created, there was no study on which pins had to be
programmed ASAP and which could be programmed later. Execute such study and
move all non-critical gpios from reset to late.
BUG=b:76097508
TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video
playback, track pad, keyboard).
Change-Id: Icbc9370050d619800026035caaac3e89536a460a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With the increase of dimm->module_part_number size from 19 to 21 (commit
35b273eea3) "include/memory_info.h: Change part number field from 19 bytes
to 21", this code is now advancing outside DDR3 SPD designated space. The
correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make
sure to 0 terminate the string.
BUG=b:77943312
TEST=Build cyan.
Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
DDR4 reserves 20 bytes for part number without termination. Therefor
coreboot buffer for part number has to be increased to 21 bytes, to
account termination.
BUG=b:77943312
TEST=Build kahlee.
Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
In commit d87e4b34 (stage_cache: Add rmodule params in metadata)
the cbmem stage cache was updatd to keep track of the arg from
struct prog in the metadata. However, external stage cache did
not get the same change. Fix that.
BUG=b:72728953
Change-Id: Ifdaaa255cac0f413856410ff61bfb411a9554a31
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Certain platforms need to pass different stack pointer values to
postcar depending on S3 resume or not. Add comments to ease the
reader in understanding the point. If different stack values weren't
needed the program was already cached in stage cache with the correct
value.
Change-Id: I7202c62e6202a14416cb49ad5348740174747c7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Entry points from assembly to C need to have the stacks aligned
to 16 bytes with the newer compilers. This entry point was
missed. Correct it.
BUG=b:72728953
Change-Id: Idb29daf830c05fd5543c2194690364ce31b6a22c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently the idt setup and handling is only in ramstage. In
order to prepare having an exception handler in other stages
move the interrupt vector entry code to its own compilation
unit. vec0 and int_hand need to be global so c_start.S
references will resolve at link time.
BUG=b:72728953
Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add paging_set_default_pat() which sets up the PAT MSR according
to util/x86/x86_page_tables.go. Using page attribute types require
a matching of the PAT values with the page table entries. This function
is just providing the default PAT MSR value to match against the
utility.
BUG=b:72728953
Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add the following functions for use outside of the paging module:
void paging_enable_pae_cr3(uintptr_t cr3);
void paging_enable_pae(void);
void paging_disable_pae(void);
The functions just enable and/or disable paging along with PAE.
Disassembly shows equivalent output for both versions.
BUG=b:72728953
Change-Id: I9665e7ec4795a5f52889791f73cf98a8f4def827
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
In preparation for bringing in paging early always provide the
paging pae module to all stages. Since we cull unused symbols this
is a no-op. Compilation testing will happen all the time since the module
currently doesn't compile without <arch/cpu.h> include. The current
file is completely guarded with ENV_RAMSTAGE because it's using
cpu_index() which is a ramstage-only construct.
BUG=b:72728953
Change-Id: Ib4310b8206e5247fa220b42203bcd18d522d51ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
If one wants to check in generated page tables in C then coreboot
complains about there not being a license. Therefore, add the BSD
license to the generated page tables.
BUG=b:72728953
Change-Id: I980d7a7c0c14c1ed5aa8ce37a1484943a6a100f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The linux kernel uses the following mapping for PAT entries:
PTE encoding:
PAT
|PCD
||PWT PAT
||| slot
000 0 WB : _PAGE_CACHE_MODE_WB
001 1 WC : _PAGE_CACHE_MODE_WC
010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
011 3 UC : _PAGE_CACHE_MODE_UC
100 4 WB : Reserved
101 5 WP : _PAGE_CACHE_MODE_WP
110 6 UC-: Reserved
111 7 WT : _PAGE_CACHE_MODE_WT
Update the page table generator to match what the linux kernel is
using. This just makes things consistent with linux.
BUG=b:72728953
Change-Id: Ie5ddab5c86d4e03688d7e808fcae34ce954b64f9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
On a second look broadcom/cygnus and imgtec/pistachio appear to
support full duplex. Therefore, remove the use of spi_xfer_two_vectors().
For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such
a way that it does not support full duplex. Remove the use of
spi_xfer_two_vectors() and explicitly error out when a full duplex
transaction is requested.
Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These settings are identical to yorp settings except
overrides are not provided for sleep_gpio[] table which
is currently empty for yorp and cros_gpios[] table which
is not expected to change for bip.
BUG=b:77869623
BRANCH=none
TEST=Build coreboot for bip.
Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make sure to define __SIMPLE_DEVICE__ on x86 only, as other platforms
currently doesn't have support for it.
Fixes static.c devicetree compilation on non x86.
Change-Id: I75fb038681a8edf119415705af5da9f999fd8225
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check same IO ranges get programmed first, if so just skip it to avoid double
programming.
BUG=b:77944335
TEST=Boot up with mewoth board, and check serial log, there's no error
message about "LPC: Cannot Open IO Window: ".
Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When GDB support is compiled in, halt() in libpayload will call
gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in
<libpayload.h>. Usually files just include <libpayload.h> so this is not
a problem, but in some situatons a payload may just include <stdlib.h>
(or a file including it like <assert.h>), leading to an undeclared
identifier here. Move the GDB functions to <stdlib.h> to solve this.
Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are sections of code that are almost identical and they can be
converted to auxiliary procedures. For allocating heap, 3 sizes (the
buffer size of currently being examined node, the buffer size of the
current best fit node and the minimum size for a buffer that will need
to be split if selected as the best fit) are used often so they could
be stored in temporary variables. These 2 changes will make code shorter,
with less indentation problems and overall easier to read. The actual
logic of the code is not changed.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25703
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Force PCH LPC generic IO ranges are identical between PCH LPC pci config
space and DMI PCR registers. Reference documentation from 570374 chapter
2.4.1.
Bug=77944335
TEST=Boot up in OS in meowth board, using iotools to read LPC pci
config space offset 0x84~0x90 and compare with values read from DMI PCR
private register offset 0x2730~0x273c are identical.
Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25668
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets VmxEnable to 1 to match the kernel setting.
If this feature is enabled at the kernel level and not in FSP,
then there is an issue where FSP expects it to be disabled so
it forces a cold reboot on every warm reboot.
BUG=b:78129261
BRANCH=poppy
Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25698
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC code should not have been removed from devicetree when moving
over from grunt. This was causing various bewildering issues that
would happen on the first boot but not on subsequent reboots.
BUG=b:73235377
TEST=Grunt powers off and stays powered off at dev screen.
Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Fix the headline levels (only the document's title should be a top-level
document), and use "# " instead of "====" to mark headlines, because
it's more obvious what the different levels of that are. Also fix some
other things.
Arguably, the explicit table of contents could be removed.
Change-Id: Ie29b6393e9d7871ea3c900e016b5c3ed415538ac
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Updating some GPIOs based on changes in the latest schematics. Also
renaming signals to match that of latest schematics.
BUG=b:73749640
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Make sure different SKUs still boot.
Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With one additional EC change, Yorp is able to flash the EC as part of
software sync and successfully boot. This change is only made for Yorp
as we want this disabled for Bip bringup.
BRANCH=none
BUG=b:77874283
TEST=Successful flash and boot on Yorp with this change
TEST=Checked GBB flags on Yorp and Bip images with gbb_utility
CQ-DEPEND=CL:1014397
Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Displaying the whole receive enable procedure is very verbose should
only be done if CONFIG_DEBUG_RAM_SETUP is selected.
Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This replaces magic values by macros and adds some comments to improve
readability.
Adds a convenient function to fetch the test address of a rank.
Also fixes the temporary memory map by changing a write to MCHBAR
0x100 to 0x110, since this is what vendor does. (No difference
observed thus far)
TESTED on DG43GT
Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This patch pushes these large default delay tables to a different file
to reduce cluttering up the actual raminit source. While doing so it
also uses more but smaller arrays and also adds the respective default
delays for DDR3 which are not yet used in this patch.
This patch add a function to set the read DQS delays instead of just
programming magic values. (This will prove useful for DQS read
training)
To prepare for adding trainings on the delay values it stores these
default delays in the sysinfo struct to program those. Later when
trainings are implemented those trained values will be used instead of
these safe default values, via using the cached sysinfo in 'mrc'
cache.
TESTED on DG43GT (still works fine)
Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stores information obtained from decoding dimms and receive enable
results for future use.
Depreciates using rtc nvram to store receive enable settings.
A notable change is that receive enable results are always reused, not
just on a resume from S3.
This requires cbmem to be initialized a bit earlier, right after the
raminit finished to be able to add the sysinfo struct to cbmem which
gets cached to the SPI flash in ramstage.
TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in
raminit goes from 133,857ms (using i2c block read to fetch SPD) to
21,071ms for cached results.
Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The commit enables DPTF function. The DPTF parameters are provided by
thermal team.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot then check the parameters in DPTF ui tool
Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only try to unhide MEI if the PCI device wasn't found and
probe for RCBA before trying to use it.
Allows to run the utility on Skylake and newer hardware that
do not have RCBA any more.
TODO: Use sideband interface to unhide MEI.
Change-Id: I7926aa80b132d5be9fece0724516701d74dd4d3d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Copy script from Linux added in commit 7683e9e5 (Properly alphabetize
MAINTAINERS file) by Linus Torvalds.
> This adds a perl script to actually parse the MAINTAINERS file, clean
> up some whitespace in it, warn about errors in it, and then properly
> sort the end result.
>
> My perl-fu is atrocious, so the script has basically been created by
> randomly putting various characters in a pile, mixing them around, and
> then looking it the end result does anything interesting when used as
> a perl script.
Change-Id: I2eb4e3f9863d0fe242fb690f1121842c80d72d6a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1)
seem to need some delay between tis_wait_valid() and
tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0,
ending the loop immaturely with some bytes left unread, and fail to
pass the check below, causing the current command not finalized by
tis_command_ready(), and blocking any later tis_wait_ready().
This time the added delay is controlled by a Kconfig option
TPM_RDRESP_NEED_DELAY.
Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25322
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with a pair of GSkill F3-1866C9-8GSR.
This makes sure in particular that we honor the CMD rate requested by
the XMP profile. This memory kit needs a CMD rate of 2 to be stable at
DDR3-1600 and up, even though it passes training at 1.
Also respect requested CWL to match vendor firmware and for a potential
increase in performance. The tested kit requests a tighter value than
the per-frequency table provides and has shown to be stable using that
setting.
Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25664
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The table in Documentation/acpi/gpio.md is currently detected as
free-form text (at least by GitHub and recommonmark), instead of a
table. Wrap it in a code formatting block to preserve the manual
formatting.
Change-Id: If460d7f1ba1a6198d949886f0f55fd6254bc2f7a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In https://review.coreboot.org/25383 people were confused about the
ordering of bootmem calls w.r.t. when entries are exposed to the OS. To
alleviate this add a notion of bootmem being initialized. In addition to
that, only mark bootmem initialized when bootmem_write_memory_table() is
called. Any other calls to bootmem before that will report an error on
the console.
Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Also base the FSP/GOP related bail-out on the correct Kconfig option
to allow adding a VBT along with libgfxinit.
Most things should work, what doesn't is backlight control because
coreboot misses the settings (moved to FSP and need backporting).
Also, Kaby Lake is still unsupported.
TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with
text and linear framebuffer mode and viewed a FILO menu.
Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Remove unused header files in
src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first
clean up. Hopefully more headers will be removed in other commits.
Header files cannot be removed at this time. They are used by files in
vendorcode/amd/pi/00670F00/.
BUG=b:77944801
BRANCH=none
TEST=build Gardenia and Grunt
Change-Id: I99b77f6ba41ded30122a01bbe709681312561436
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25644
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
bt-pad-enable property is used by kernel driver to set
BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which
use these pins for BT I2S. By default the pins are set for UART.
BUG=b:72360151
TEST=Tested playback and capture on audio device connected to BT I2S
Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25653
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.
Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.
To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.
This issue is known already and was discussed on the mailinglist:
[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html
TEST=Boot mc_bdx1 with microcode version M1050663_07000012.
Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Required for other ACPI generators, like the one used for _ROM.
* Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms.
* Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators.
Needs test on real hardware.
Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22337
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn on keyboard backlight in romstage to indicate that the system is
booting.
BUG=b:77921345
TEST=Boot grunt, keyboard backlight comes on.
Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Due to an accuracy issue on IMON in the IDT PMIC, the reported system
power consumption was higher than the actual consumption. To prevent
this problem, a logic must be implemented in mainboard_init(). This logic
consists of slope and offset as constants for Vcc and Vnn, which need
to be programmed by coreboot. This fix compensates for the accuracy
issue.
Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device self INTA INTB INTC INTD
GPP 0 23 0 1 2 3
GPP 1 24 8 9 10 11
GPP 2 25 16 17 18 19
GPP 3 26 24 25 26 27
GPP 4 23 3 0 1 2
HDA none 22 23 20 21
GBIF none 6 7 4 5
Fix the routing table, considering that NB IOAPIC starts at interrupt 24.
BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.
Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update libgfxinit to current master. Changes include:
* a fix to decode the size stolen memory correctly on pre-SandyBridge
hardware,
* a PCI id based generation check, obsoleting the old check based
on PCH audio ids,
* some minor improvements around rarely used DDI ports (D and E), and
* added support for tiled and rotated framebuffers on Skylake+ hardware
(less interesting for coreboot, I guess?).
TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6
(Skylake) both with text and linear framebuffers and observed
FILO's prompt showing up.
Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25453
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The converter was setting SMBIOS values when dimm_info expects SPD
values.
dmidecode now shows the following:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 933 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 933 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Example debug output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): ' 00000000'
PartNumber(20): 'HMAA51S6AMR6N-UH '
CBMEM_ID_MEMINFO:
dimm_size: 8192
ddr_type: 0x1a
ddr_frequency: 933
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x4
bus_width: 3
serial: 0x00000000
module_part_number(18): 'HMAA51S6AMR6N-UH '
The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.
`mosys memory spd print all` is still failing though. I will look into
that next.
BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above
Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the recovery cache to speed up recovery flows. Also
enable clearing of the normal mrc cache on recovery forced retrains.
BUG=b:77871444
TEST=went into recovery twice. 2nd time it boots faster.
Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data
in SPD format. These methods will be used to update amd_late_init.c so
it sets the correct values.
BUG=b:65403853
TEST=Built and booted grunt. Methods are not called in this commit. So
they were tested with the later commit by verifying the output of
dmidecode.
Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For cannonlake_rvp, want to support two sound configurations based on
relevant daughter board connected (either of these configurations:
SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT).
By default SSDT included all codec entries.
This patch corrects and includes relevant codec entries in SSDT
BUG=None
BRANCH=master
TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully.
Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/24918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
By storing the FSP-M DRAM configuration parameter in the hwinfo block,
one becomes more flexible in case of a change of the DRAM type.
The configuration data from hwinfo block is a one-to-one representation
of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and
ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).
Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The list of supported architectures in the usage output of cbfstool is
currently hardcoded and outdated.
Use the arch_names array in common.c to provide and up-to-date list.
Change-Id: I3e7ed67c3bfd928b304c314fcc8e1bea35561662
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, "cbfstool -h | less" doesn't show any file types under
"TYPEs:". That's because the file types are printed with
print_supported_filetypes, which uses LOG, which prints to stderr. Use
printf print_supported_filetypes, and thus print to stdout, to make the
usage output more normal.
Change-Id: I800c9205c59383b63a640bc0798a1bd9117b0f99
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Grunt supports a keyboard backlight, so enable the ASL code.
BUG=b:77455525
Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT.
Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25470
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a few southbridge calls needed for parallel MP init.
Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.
Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU.
Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23432
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is required for clock parameter settings to take effect.
BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz
Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The missing space resulted in the following broken output:
> ERROR: Not enough MTRRs available! MTRR indexis 10 with 10 MTTRs in
total.
Put the string on one line to make it obvious where the spaces should be
and to help users of grep.
Change-Id: Ib9e8109d88c1bf38e7dda3dbf1c8d47fb0d23265
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows VGA output in SeaBIOS to be enabled using the
SEABIOS_VGA_COREBOOT Kconfig option. Currently, it’s impossible to select
the VGA text frame buffer in the Kconfig menu.
I'm not sure why this wasn't enabled in the first place, but
SeaVGABIOS seems to work just fine with this patch.
Tested on KCMA-D8.
Change-Id: Ic924a12fbe89940b5f26d211eb8de6cab0be767a
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/25554
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.
BUG=b:75306520
Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c
of all boards using stoneyridge must be available at romstage.
BUG=b:74236170
TEST=Build grunt and kahlee, actual test will be performed at a later patch.
Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25528
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Vayne.
We need to disable rear camera on all Vayne sku.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera shown on Vayne
Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
The code is mostly copied from src/cpu/intel/haswell.
TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.
Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that calc_var_mtrrs_with_hole() always chooses the optimal
allocation, there is no need for calc_var_mtrrs_without_hole()
any more. Drop it and all the logic to decide which one to call.
Tests performed compared to "upstream" (before "cpu/x86/mtrr:
Optimize hole carving strategy") on a Lenovo/X200s with 48MiB
GFX stolen memory.
2GiB total RAM: 3 MTRRs saved
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007ac00000 size 0x7ab40000 type 6
0x000000007ac00000 - 0x00000000d0000000 size 0x55400000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
upstream:
MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/8 > 6.
MTRR: default type WB/UC MTRR counts: 4/7.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0
MTRR: 1 base 0x000000007b000000 mask 0x0000000fff000000 type 0
MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0
patched:
MTRR: default type WB/UC MTRR counts: 7/5.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0
MTRR: 2 base 0x000000007b000000 mask 0x0000000fff000000 type 0
MTRR: 3 base 0x000000007c000000 mask 0x0000000ffc000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
4GiB total RAM: no MTRRs saved but slightly more accurate alignment
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6
0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000017c000000 size 0x7c000000 type 6
upstream:
MTRR: default type WB/UC MTRR counts: 7/6.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0
MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 5 base 0x0000000100000000 mask 0x0000000f00000000 type 6
patched:
MTRR: default type WB/UC MTRR counts: 7/6.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0
MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
MTRR: 5 base 0x0000000100000000 mask 0x0000000f80000000 type 6
8GiB total RAM: possible savings but WB still beats UC
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6
0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000027c000000 size 0x17c000000 type 6
upstream:
MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/11 > 6.
MTRR: default type WB/UC MTRR counts: 4/10.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0
MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0
patched:
MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/7 > 6.
MTRR: default type WB/UC MTRR counts: 4/6.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0
MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0
MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0
Change-Id: Iedf7dfad61d6baac91973062e2688ad866f05afd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For WB ranges with unaligned end, we try to align the range up and
carve a hole out of it which might reduce MTRR usage. Instead of
trying an arbitrary alignment, we try all and choose an optimal
one.
Also, restructure the cases when we try to find a hole. Which leads
us to the following three:
1. WB range is last in address space:
Aligning up, up to the next power of 2, may gain us something.
2. The next range is of type UC:
We may align up, up to the _end_ of the next range. If there
is a gap between the current and the next range, it would
have been covered by the default type UC anyway.
3. The next range is not of type UC:
We may align up, up to the _base_ of the next range. This is
the end of the gap, if there is one.
Change-Id: Iefb064ce8c4f293490a19dd46054b966c63bde44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the error below.
```
src/lib/lzmadecode.c: In function 'LzmaDecode':
src/lib/lzmadecode.c:77:2: error: macro expands to multiple statements \
[-Werror=multistatement-macros]
Range -= bound; \
^~~~~
src/lib/lzmadecode.c:300:7: note: in expansion of macro 'UpdateBit1'
UpdateBit1(prob);
^~~~~~~~~~
src/lib/lzmadecode.c:299:8: note: some parts of macro expansion are not \
guarded by this 'else' clause
} else
^~~~
cc1: all warnings being treated as errors
```
The macro is defined as below.
#define UpdateBit1(p) \
Range -= bound; \
Code -= bound; \
*(p) -= (*(p)) >> kNumMoveBits
Found-by: gcc-8 (Debian 8-20180402-1) 8.0.1 20180402 (experimental) [trunk revision 259004]
Fixes: 35af5c47 (src/lib: Fix spacing)
Change-Id: Ife0688541e23c05e26e429a6d8caee7e2d425b1b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till
98. Compute a crc16 over that data to provide a solid way to check
DIMM identify.
Reuse the crc16 function from ddr3.c to do this.
Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
checkpatch_json.py processes the output of checkpatch.pl &
generates json format output of comments.
This json format output can be used to post comment on particular
CL using gerrit.
BUG=None
BRANCH=None
TEST= Run following commands:
1. Capture output of checkpatch.pl to file say checkpatch.txt
nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl --no-signoff -q - |
tee checkpatch.txt
2. Generate json format file for the output.
util/lint/checkpatch_json.py checkpatch.txt comment.json
3. Post the comment.json using gerrit
ssh coreboot.org gerrit review -j "<CL number>,<patchset number>" < comment.json
Change-Id: I2471792796ab8e7d9855a6559fc731345ebd1525
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/23429
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with
kernel 4.9. This code is based on the output of autoport.
Working:
- S3 suspend/resume
- USB
- Gigabit Ethernet
- integrated graphics
- PCIe
- SATA
- eSATA
- PS/2 port (only a mouse has been tested)
- hardware monitor
- onboard audio
- front panel audio
- native raminit (2 x 4GB + 2 x 8GB, DDR3-1333)
- native graphics init with libgfxinit
- EHCI debug. The debug port is the port closest to the HDMI port.
- flashrom, using the internal programmer. Tested with coreboot,
untested with the vendor firmware.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for graphics init
- PCIe graphics
- S/PDIF audio
Not working:
- "clear CMOS" button
The CPUTIN sensor on the Super I/O is not connected. The PECI agent is
likely connected instead to give CPU temperature readings. However,
there does not appear to be enough information in the publicly available
datasheets to fully set up the PECI agent. As a result, there is
currently no accurate, automatic fan control via the Super I/O.
Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/24971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Broadwell-DE the FSP sets up DCACHE in the early call. The address
does not match the default FSP 1.0 address defined in
src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range
is used in pre-ramstage stages.
This patch provides the matching DCACHE_RAM_BASE value among with a
suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation.
The include order of Kconfig files makes sure that the Kconfig file in
the soc directory is sourced first and the defined values will override
the ones in src/drivers/intel/fsp1_0/Kconfig.
Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Changelog:
* Add support for the HAP/AltMeDisable bit
* Add support for selective partition removal
* Fix the ME permission removal on gen. 3
* Add public key match
* Print the compressed size of the Huffman modules on gen. 2
* Wipe the ME6 Ignition firmware images
* Fix the removal of the last partition on ME6
* Various region size fixes
* Add manpage
* Add setup.py
* Print the value of the HAP/AltMeDisable bit
The output image should be identical, except for the platforms affected
by bugs (ME 6.x, but it's not supported by coreboot and ME 11.x with the
-d option, but it's not being used in our build process).
Overall, nothing should change when it's used with the
CONFIG_USE_ME_CLEANER option.
Tested on a Lenovo X220 and Sapphire Pure Platinum H61.
Change-Id: I3d5e0d9af0a36cc7476a964cf753914c2f3df9d2
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This imports common BDK sources that will be used in subsequent
patches.
The BDK is licensed under BSD and will be reduced in size and optimized to
compile under coreboot.
Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Instead of hard-coding a lot of default values of the framebuffer config,
we use the values provided by Display_Probing.Scan_Ports() and only
overwrite what is necessary. This way we are more independent from
changes inside libgfxinit.
Change-Id: I121bbd926532c27321446282aa334cc45cdbeef1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Aligning the stride up to a multiple of 64 pixels was flawed: We want
to actually align up to one cacheline (64 bytes) as that's the mini-
mum what the hardware supports.
Change-Id: I3f824ffd7d12835935e4e4bde29fe82dc3e16f9d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
AgesaHeapRebase is an optional callout that allows AGESA to use a
coreboot-managed heap base address. Its internal default location
is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB.
Add a #define that AGESA may use once the feature is available.
BUG=b:74518368
Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.
This is necessary since there are no VR_CONFIG icc mappings for
Skylake SKUs, only KabyLake.
These values were copied from the Google Poppy devicetree.
Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set the Thermal Control Circuit (TCC) activaction value to 95C
even though FSP integration guide says to set it to 100C for SKL-U
(offset at 0), because when the TCC activates at 100C, the CPU
will have already shut itself down from overheating protection.
This was tested on Purism Librem 13 v2. A bisect showed that the
immediate shutdowns happened after commit [1] was merged which led
to this solution.
[1] ec5a947b (soc/intel/skylake: make tcc_offset take effect)
Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Although VmxEnable is currently ignored by FSP, a forthcoming patch
explicitly enables it in coreboot, so set it in anticipation of that.
Enable Intel SpeedStep to ensure the ACPI tables are generated for
the C-states/P-states which are required for the xen-acpi-processor
module to be loaded. Without it, the Qubes 4.0-rc4 installer will
complain at boot about modules that could not be loaded.
Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the GPIO to match the TPM-enabled motherboards, and add TPM
support in devicetree and enable the config.
After changing the GPIO table, the librem 13v2 and librem 15v3 now
have the same GPIOs, so use a single gpio.h file instead of one
file per variant.
Change-Id: I425654c1c972118aa81c27961246238c2eef782d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/23683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add FSP option to enable/disable VT-d (Intel Virtualization Technology
for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be
disabled once VT-d got disabled.
Bug=b:73655383
TEST=Build and flash image on meowth board with debug build FSP, in
serial log search for "VMXEnable" and "VtdDiable".
Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17
Offset 15h Speed report incorrectly issue.
BUG=None
TEST=Boot up with meowth platform and run dmidecode to see two dimm
entries under Type 17.
Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25378
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For some SPI chips (e.g. those with AAI writes), the default OPMENU
definitions don't work well. Thus, provide an option to override the
defaults in the devicetree.
Writing the OPMENU now happens in ramstage instead of the SMM finalize
handler. If you let coreboot call the finalize handler, nothing should
change. If you call the handler from your payload, OTOH, the OPMENU
might have been changed in between, so be careful what you lock.
Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.
The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).
We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.
Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
The WP signal to the AP isn't inverted as it is on other platforms, so
it was reporting incorrectly. Change the ACPI table to be active low,
and invert the signal when reporting it to everything else.
BUG=b:74946358
TEST=Boot grunt with battery inserted, WP signals both report 1. Remove
battery, WP_CUR reports 0, WP_BOOT still reports 1.
Change-Id: Ic1369dbda609e34b308af308880449643be6af39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets PL1 value to ~6W. Here, 8W setting gives
a run-time 6W actual measured power.
Also, this patch sets PL2 value to 15W.
BUG=None
BRANCH=None
TEST=Build and read the MSR 0x610.
Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/25341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.
This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.
Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The <gpio.h> API is supposed to include a gpio_set() function that just
toggles the state of a GPIO already configured as an output, even though
we rarely need it since gpio_output() can already be used to initialze a
GPIO to a default value while configuring it as an output. This function
was forgotten on Rockchip, so this patch adds it now.
Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change f43adf0 (intel/common/block/cpu: Change post_cpus_init after
BS_DEV RESOURCES) moved post_cpus_init to BS_OS_RESUME for S3
path. This results in BSP timing out waiting for APs to be
parked. This change increases the time out value for APs to be parked
to 250ms. This value was chosen after running suspend-resume stress
test and capturing the maximum time taken for APs to be parked for
100 iterations. Typical values observed were ~150ms. Maximum value
observed was 152ms.
BUG=b:76442753
TEST=Verified for 100 iterations that suspend-resume does not run into
any AP park time out.
Change-Id: Id3e59db4fe7a5a2fb60357b05565bba89be1e00e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
google_chromeec_command() may only write the 1 or 2 bytes to
variable r (4 bytes). However, this api returns 4 bytes data.
To avaid returning the incorrect data, we need to initialize the
local variable.
BUG=b:76442548
BRANCH=none
TEST=write 2 bytes data into the flash, then, read by cbi_get_uint32
Change-Id: I3395c97ab6bfd7882d7728310de8a29041190e76
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25460
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In case of all DMI Type 17 to be empty, the strip trailing whitespace
code will have a zero length Part Number entry, which will cause
exception when using (len - 1) where len is zero. Add extra code to
cover this corner case.
BUG=b:76452395
TEST=Boot up fine with meowth platform, without this patch system will
get stuck at "Create SMBIOS type 17".
Change-Id: Id870c983584771dc1b60b1c99e95bbe7c0d25c4c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/chell with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/edgar with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.
Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.
Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
me_progress_rom_values array provides detailed information maps to ME
HFSTS2 register value.
There is a chance that ME status value might be over the size of
me_progress_rom_values.
This commit adds a check before access the array.
BUG=b:77247550
Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/25425
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new variant of Poppy for the Atlas board.
BUG=b:75454415
TEST=tested on a P0 board. System boots and is mostly
functional, though some peripherals are not ready so there
are no touchpad/touchscreen devices configured yet.
Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates devicetree and GPIO configurations to match the
schematics:
1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and
deemphasis_enable for [2] need to be set instead of [0].
2. WLAN power enable, wifi disable and PERST# GPIOs need to be
configured correctly.
BUG=b:76180142
TEST=Verified that wlan0 scan works.
Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the sandybridge both smm setup and smihandler code to a
common place.
Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.
Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.
Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CONFIG_VBOOT is enabled then the xDCI controller should only be
enabled if the system is in developer mode. This prevents a system
in normal/verified mode from being used as a USB peripheral device
which could potentially be used to access user data.
This change adds a function to return whether xDCI can be enabled
or not, which will be used by the SOCs.
Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch disables debug consent in the devicetree. When debug
consent is set to DBC by default, it prevents some clocks from turning
off during S0ix. This blocks S0ix entry.
This patch also enables S0ix from the devicetree.
BUG=b:76163091
TEST=enter S0ix and check if slp_s0 is asserted
Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25312
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an SPD for this particular Hynix memory type to the poppy board
so it can be used by poppy variants.
BUG=b:75454415
Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds a call to heci_reset before attempting to read
ME firmware version. This is important to ensure that both ME and BIOS
are in sync.
BUG=b:76167737
BRANCH=poppy
TEST=Verfied that ME firmware version read does not fail on first boot
after power failure (i.e. removing battery and AC power).
Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current emmc tuning parameters for octopus were copied over from other
boards and result in failure to boot from emmc. This change gets rid
of the emmc tuning parameters in devicetree. Once emmc tuning tests
are run for octopus, these parameters can be added back.
BUG=b:75986903
BRANCH=None
TEST=Verified that octopus boots from eMMC without any errors in
depthcharge.
Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC needs to set the PPCM value depending on whether
Turbo is enabled or not, and the values differ between
Broadwell (0, 1) and Skylake (1, 2) platforms.
Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The LPC I/O ports for EC communication were not set properly,
causing ectool to fail to read the Index I/O from the EC.
The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.
Correct the value for the Librem 13v1, 13v2 and 15v3.
Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change remove work-around code for the power issue of MIPI and
USB cameras on previous board revision. With the work-around code,
PMOF ACPI method cannot turn off MIPI camera. So we need to remove
it.
BUG=b:74214248
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/25337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The code is based on autoport and that for revolve_810g1
Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Onboard USB2 interfaces (wlan slot, wwan slot, camera, smart card)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.17-1 within Debian GNU/Linux testing, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
Not working well:
- EHCI debug on port SSP2,(The USB port on the left, wired to ehci
before OS) it has always-on enabled by default (maybe via EC),
which disturbs FT232H's own power up, requiring a very critical
timing to plug it in for it to work.
Change-Id: I52e549ec18e8aa661a506a16dbc7f83417c0da78
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25218
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A change introduced by commit fe4983e5 [1] in order to prevent
re-initialization of the TPM if already set up in verstage
had the wrong logic in the if statement, causing the TPM
to never be initialized if vboot is disabled.
The RESUME_PATH_SAME_AS_BOOT config is enabled by default for
ARCH_X86, resulting in the if statement to always evaluate to
false. Remove that condition from the if statement to allow it
to function as intended.
This patch also enables TPM initialization for FSP 2.0 with
the same conditions.
[1] intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage
https://review.coreboot.org/#/c/coreboot/+/14106/
Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the support for KBL-S MCH and Z270, H270, B250 and
Q250 PCH chips.
BUG=None
BRANCH=None
TEST=Boot with KBL-S CPU and B250/H270 PCHs.
Change-Id: If03abb215f225d648505e05274e2f08ff02cebdc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/25305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr. Fix by reverting to previous (simpler) implementation.
[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566
Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.
Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a new Kconfig option for mainboard octopus "HAS_TPM"
that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA
is not selected.
BUG=b:76203913
TEST=Compiles fine with mocktpm.
Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Example output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): 00000000
PartNumber(20): HMAA51S6AMR6N-UH
CBMEM_ID_MEMINFO:
dimm_size: 0
ddr_type: 0x1a
ddr_frequency: 1200
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x1a
bus_width: 64
serial(4): 0000
module_part_number(23): HMAA51S6AMR6N-UH ��@
dimm_size, mod_type, bus_width need to be updated so they return the
correct values. module_part_number is missing a null terminator due to
the AGESA part number being larger than the dimm_info buffer.
Example dmidecode output:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 8 bits
Data Width: 8 bits
Size: No Module Installed
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 1200 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 0000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 1200 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
To enable the output set CONFIG_DEBUG_RAM_SETUP.
The Kconfig change is required in order to enable
CONFIG_DEBUG_RAM_SETUP, otherwise it's not a valid option.
BUG=b:65403853
TEST=Test output shown above
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eac00b9400056357915761287770a400b3f9f8b
Reviewed-on: https://review.coreboot.org/25303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
dmidecode used to print
'HMAA51S6AMR6N-UH '
it now prints
'HMAA51S6AMR6N-UH'
BUG=b:65403853
TEST=Verified using dmidecode
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia10ef434a2377e34ae7a8f733c6465c2f8ee8dfa
Reviewed-on: https://review.coreboot.org/25302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform. This also sets the
FSPUPD to indicate the status of S0ix on the platform.
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag
is set in FACP table - FADT.Flags[21] bit.
Change-Id: I6214ebb61f25ef8b704e60c8474808493c92e6f6
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25292
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always report that EC is in RO mode. This is a temporary workaround
for a hardware issue that is causing EC to appear to be in RW mode
when it is not. This change will be reverted once transition is made
to newer hardware.
BUG=b:74215817
BRANCH=master
TEST=Verify meowth can boot to recovery's insert screen.
Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.
The following changes were done to coreboot and libpayload:
* Use page table lvl 0
* Increase VA bits to 48
* Enable 256TB in MMU controller
* Add additional asserts
Tested on Cavium SoC and two ARM64 Chromebooks.
Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
SeaBIOS 1.11.1 was released with the changes below.
```
$ git log --oneline rel-1.11.0..rel-1.11.1
0551a4b paravirt: Only enable sercon in NOGRAPHIC mode if no other console
specified
a7aa43e pci: fix 'io hints' capability for RedHat PCI bridges
0e739f2 shadow: Don't invoke a shutdown on reboot unless in a reboot loop
5d9a515 build: Use git describe --always
```
Change-Id: Ia77e98edcd42b28677de9670ce13c2ea5d327315
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Print the wake status bits to the console. The format is kept similar
to Intel's to maintain compatilibity with inspection utilities. Add
relevant wake events from the register to the ELOG. Clear the register
before continuing.
TEST=Inspect console and ELOG for Grunt
BUG=b:75020968
Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This change defines IFD_CHIPSET as sklkbl to allow ifdtool to set the
right access control bits for SKL/KBL platforms.
BUG=b:76098647
BRANCH=poppy
TEST=Verified that the access control bits on KBL platforms are set correctly.
Change-Id: I7b2131caa06d6a975e703262931ec0ea519a86aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The default values used by ifdtool for setting region access control
do not match the expected values for SKL/KBL as per the SPI
programming guide. This change adds platform "sklkbl" that sets region
access control bits differently for SKL/KBL images.
BUG=b:76098647
BRANCH=poppy
TEST=Verified that the access control bits on KBL images is set
correctly.
Change-Id: I1328d8006c25be282b3223268d8f1fd0a64e2ed3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
it was idle.
Google CFM add-in card is going to use this I2C bus so it needs to be
re-enabled.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
working properly.
Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/25258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This creates a bip variant for octopus. Nothing is set in the variant
files here-- everything is picked up from baseboard.
BUG=b:75976864
TEST=None
Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to
read the sku id. In order to support "-1", we need to use
uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type.
Otherwise, tools/scripts will read 65535 instead of -1.
Another reason to change this is that sku_id can be
supported by ec up to 4 bytes.
BUG=b:73792190
TEST=mosys output "Platform not supported" for -1 sku id
arc-setup read -1 sku id
Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following PCI device ID can be included for jefferson peak wifi
devices driver support, and they are:
9df0 for jefferson peak on Cannonlake-LP w/CNVi
A370 for jefferson peak on Cannonlake-H w/CNVi
31dc for jefferson peak on Geminilake w/CNVi
BUG=None
TEST=None
Change-Id: I48886cea5578a302f6ef033cb35df4a38bd64ea8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO pad configurations for GPIO68-71 are incorrectly configured as
outputs. This change corrects them to be inputs.
BUG=b:74932341
TEST=None
Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25217
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires
it to be disabled. Therefore allow it to be configured via a
device tree setting.
TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when
de-emphasis is disabled in device tree.
Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.
BUG=None
TEST=None
Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We are enabling at the kernel level, but that is triggering an issue
where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot, clearing the ramoops logs. Enabling in BIOS so it
matches what the kernel expects.
This is the same change that were done for eve:
https://review.coreboot.org/#/c/22449/
BUG=None
BRANCH=None
TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT
check for /dev/pstore/console-ramoops
Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO
results in EC communication failure. This change removes the
configuration of GPIO_149 as GPO in ramstage so that it remains
configured for ESPI (as it was when AP came out of reset).
BUG=b:75348718
Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
glk has different memory profile values than apl. Therefore, a
translation is required to correctly set the proper profile value
depending on what SoC (and therefore FSP) is being used. Based on
SOC_INTEL_GLK Kconfig value use different profiles.
BUG=b:74932341
Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25249
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.
BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.
Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.
BUG=b:70338633
TEST=build kahlee.
Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. Create
a procedure that initializes all AOAC devices in a table and wait for all
AOAC to become alive, then call this new procedure before the call to
initialize the UART. Then change all procedures that initialize some AOAC by
moving the devices to the table and removing AOAC initialization code.
BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.
Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a
config option to enable hotplug only if explicitly requested by
mainboard. This changes the default behavior on all apollolake boards
to have hotplug disabled.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1) Set the critical temperature threshold to 100C to match changes
on other boards. This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.
2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware
Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in
the latest schematics.
BUG=b:74347464
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to generate ACPI OpRegion, save the
table address in ASLB, and restore table address upon S3 resume.
Implementation largely based on existing Haswell/Lynxpoint code.
Test: boot Windows 10 on google/lulu with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: I024f4f0784df3cbbb9977692e9ef0ff9c3552725
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we
need this memory to be writable. We normally over-ride this in the
SoC chip init code, so we'll do the same on cannonlake.
BUG=b:71722386
BRANCH=none
TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip
all the bits.
Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).
BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.
Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/25110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable System Agent dynamic frequency support by default.
BUG=None
TEST=Build and flash with debug version FSP, check SaGv in serial print
to be set to "4".
Change-Id: I7dd29db206b06e600407bb0b1d0bc7530f4ac93e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25093
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv(Sytem Agent Dynamic Frequency) have four settings, disabled,
disabled but running at fixed lower frequency, disabled but running at
fixed middle frquency, disabled but running at fixed high frequency and
totally enabled.
BUG=None.
Change-Id: Ib5fb648179e7889aaa64d91e6cf7a7a7503f4225
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In preparation for moving AGESA calls out of the bootblock:
* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to generate ACPI OpRegion, save the
table address in ASLB, and restore table address upon S3 resume.
Implementation largely based on existing Broadwell code.
Test: boot Windows 10 on google/squawks with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: Iab15e1de2bb7d8fbec2e8705a621cfca0f255d4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Most Intel platforms use separate registers for software-based
SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single
combined register (0xe0) for both. Adjust opregion implementation
to use the correct register for Atom-based platforms.
Test: Boot Windows on Atom-based ChromeOS device with Tianocore
payload and non-VBIOS graphics init; observe Intel display
driver loaded correctly and internal display not blank.
(requires additional change for Atom platforms to select
CONFIG_INTEL_GMA_SWSMISCI)
Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Since nami proto did not have any external pull on MEM_CONFIG_4, use a
weak internal pull down before reading it.
BUG=b:74420123
TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami.
Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current lpddr4 skus entries do not match the RAMID table in the
schematic. This commit updates that so they are consistent. Thankfully,
the values are the same as for glkrvp, so I just copied from there.
BUG=b:74392818
TEST=None
Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following gpios are no longer needed and are now configured as
no-connects : GPP_C6, GPP_H4, GPP_H5
BUG=b:74406599
BRANCH=master
TEST=none
Change-Id: I55769336195db0e57dfbaf5b5770e15050138341
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that fields that are not updated in
variant_memory_params keep a default value of 0.
In particular, use_sec_spd is intended to have a default value of
0 on all platforms. Without this patch, a random value is used
and all boards (except nami) get stuck on boot.
BRANCH=poppy
BUG=b:74439917
TEST=Nautilus and poppy can boot, and do not get stuck at
"CBFS: 'sec-spd.bin' not found."
Change-Id: I06c6511625de930903ae13788bdcd27667a17886
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
we had disabled software sync for bringup - we now have enough
functionality in place to turn on software sync.
Change-Id: Ib7f5a24ed8a47cb44b3f505e3cd49e0cb6931dc0
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit
[15:0] to the same value program in LPC PCI offset 82h. Also this
cycle decoding is only allowed to set when SRLOCK is not set.
Hence move the required programming from lpc.c to pch.c.
Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO
Kconfig is selected.
Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
By default all Intel platform has enable IO decode range for COMA if
CONFIG_DRIVERS_UART_8250IO is selected.
With this patch, COMB will get enable based on
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection.
Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid
an additional pci configuration read to get the same data.
Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
0xfed81ffff. Will be called by a later commit.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)
Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP can only output its traces when the HSUART PCI device is
available.
- Move the hiding to after last FSP call.
- Adapt coreboot PCI enumeration to keep the legacy configuration.
With UART configured as legacy Linux will not re-enumerate it but detects
it as legacy (ttyS0 instead of ttyS4).
Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since the timeout in bsp_do_flight_plan is bumped up to 1 second, this
change adds a print to indicate the amount of time it takes for all the
APs to check-in.
TEST=Verified on Nami that it prints:
"bsp_do_flight_plan done after 395 msecs."
Change-Id: I4c8380e94305ed58453ed18b341b3b923949d7a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly. Failure to do so confuses cr50.
BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.
Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
coreboot's PCI resource allocator doesn't assign BAR1 for
Braswell's LPE device because it doesn't exist, but is
required by Windows drivers for the device to function.
Manually add the required resource via the existing
lpe_read_resources function, and marked it as IORESOURCE_STORED
so pci_dev_set_resources ignores it.
TEST: boot Windows 10 on google/edgar, observe that memory resources
are properly assigned to LPE driver for BAR1 and no error reported.
Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add timestamps before and after the vBIOS load and after the vBIOS
run. This lets us see exactly how long it took to load it from the
ROM chip, and how long it takes to run.
BUG=b:64549506
TEST=Build & boot Grunt, see vBIOS load & initialization times.
Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hardware updates have suggested we need to configure the K&D panel's
power sequence in software, not in hardware. Without this change, K&D
panels will no longer power on correctly and will instead display a
black screen.
Per K&D's suggestion, we tweak these two commands. From the little HW
docs I have, this looks like it's:
(Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to
1
(Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from
MIPI_TE(0001b) to BC_CTRL (0010b)
BRANCH=scarlet
BUG=b:73133861
TEST=KD display with and without HW fix on Scarlet
Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/25023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allows eMMC in PCI mode to be seen/used by Windows.
Test: boot Windows installer on google/edgar, observe internal
eMMC storage available for installation when eMMC in PCI (vs ACPI) mode.
Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.
BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).
Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The LPEA device memory resources, required by Windows drivers,
were not being set. Allocate required resources per Inte'sl CHT
Tianocore reference code.
Test: boot Windows on google/edgar, observe LPEA device working properly.
Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Certain platforms need paging enabled during cache-as-ram because
dirty lines are being evicted by a heavy speculative frontend. Paging
needs to be enabled in order to utilize the NX (no execute) bit for
the regions that are strictly data (such as the stack). This utility
creates 32-bit PAE page tables using a static address space, and
the resulting tables have entries for all the PDPTEs such that it makes
it easy to enable 2MiB naturally aligned DRAM mappings once memory is
trained. Either binary files can be generated or C files. The pages that
are linked use a default base address of 0xaa000000 that can be changed at
runtime to reflect where the page tables are actually loaded. Or
specify a physical address on the command line that is known a priori.
iomap.txt:
0xd0000000, 0x100000000, UC, NX # All of MMIO
0xff000000, 0x100000000, WP, # memory-mapped SPI
0xffff8000, 0x100000000, WP, # XIP bootblock
0xfef00000, 0xfefc0000, WB, NX # CAR
0xfef40000, 0xfefc0000, WB, # verstage
0xfef20000, 0xfefc0000, WB, # romstage
0xfef40000, 0xfefc0000, WB, # fsp-m
$ go run util/x86/x86_page_tables.go --iomap_file=iomap.txt
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 UC NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xaa000000.
BUG=b:72728953
Change-Id: I47625a24979b196011e2293712a8cdbdbb880d79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24919
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by overriding the weak functions from smbios.c
Some values are hardcoded as they are characteristics of the
Tagada system. Other are retrieved from the BMC through the
bmcinfo interface.
Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23843
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB
to match Intel CHT reference code and fix Windows functionality.
Test: boot Windows on google/edgar, observe no error in Device Manager
for LPEA audio device due to BAR2 resource allocation.
Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Without PMAX correctly set, the calculation for PLEN is incorrect,
leading to a Windows BSOD on boot. Correct PMAX using code from
Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1).
Test: Boot Windows 10 on google/edgar without BSOD.
Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some type-c monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Also, if an HDMI monitor is connected, no wait is needed. If only
an HDMI monitor is connected, currently the API always loops until
the stopwatch expires.
This patch will make the AP skip DisplayPort wait loop if it detects
an HDMI monitor. And if an HDMI monitor is not detected, the AP will
wait for DisplayPort mode (like before) but also its HPD signal.
This patch also extends the wait loop time-out to 3 seconds.
BUG=b:72387533
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The MMCONF base address and length are set in Kconfig so it does
not need to be redefined by the SOC as the code can just use the
Kconfig variable directly.
Tested on a fizz board to ensure MCFG is still created properly.
Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24975
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI MCFG table is generated with a static end bus number of 255,
which expects that the reserved range in E820 is 256MB. However the
actual MCFG range is configurable with Kconfig, so these two values
may not match when the OS tries to determine the range:
PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!)
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
Instead of forcing the end bus number to be 255 use the Kconfig value
to set it based on the current configuration.
Tested on a fizz device to ensure that the kernel no longer complains:
PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24974
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot
and should not be used as a UART device. coreboot is setting the
pins to GPIO Mode but FSP is re-configuring them for Native Mode
and the behavior is unexpected when the kernel tries to initialize
the UART device.
The UART 0 device is PCI function 0 so it needs to be enabled for
other functions to be visible to the OS so it can't just be disabled.
Instead, set the device to PchSerialIoSkipInit so that FSP will not
change the pin state.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware to ensure the pin state
does not change when FSP runs or the kernel boots.
Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson. This means that the IOAPIC wasn't being
initialized in coreboot.
BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.
Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 2e81f394cf, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.
Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.
BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.
Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 1dfc2c3
[google/chromeec: Enable unified host event programming interface]
added support for UHEPI, but google_chromeec_is_uhepi_supported()
incorrectly treats negative error return codes from
google_chromeec_check_feature() as supported. Fix this check to only
treat positive return values as supported, as per the original intent.
Test: boot google/lulu, verify cbmem console reports UHEPI not
supported even if feature check returns error code, verify lid/kb
wake events correctly wakes the device from S3/sleep.
Change-Id: I7846efb340bc1546b074e8502daf906c444bd146
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.
BUG=b:73514687
Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.
BUG=b:74089135
Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, the AP check-in time-out in bsp_do_flight_plan is set to
100ms. However, as the number of APs increases, contention could
increase especially for resource like UART. This led to MP record
time-out issues on KBL platform with 7 APs and serial-console enabled
BIOS image.
This change increases the time-out value to 1 second to be on the safer
side and let APs check-in before continuing boot.
BUG=b:74085891
TEST=Verified that MP record time-out is not observed anymore on Nami.
Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a configurable delay in milliseconds before SLP_EN is set in
SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power
button SMIs.
On some platforms (Nami, Nautilus), it was observed that power button SMI
triggered by EC was competing with the SLP SMI triggered by keyboard
driver. Keyboard driver indicated power button press which resulted in
depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power
button press also causes the EC to send a pulse on PWRBTN# line, which is
debounced for 16ms before an interrupt is triggered. This interrupt was
generated after SLP_SMI is processed which resulted in the device waking back up
from S5.
This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is
used to add a delay before SLP_EN is set for S5. This change should only affect
CHROMEOS boards as the config option will be 0 in other cases.
BUG=b:74083107
TEST=Verified that nami, nautilus do not wake back from S5 on power button press
at dev mode screen.
Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The console subsystem allows printk() to be called prior to the
drivers and/or infrastructure is completely set up. In those
situations don't allow messages to be added until the console
is completely initialized.
BUG=b:73898539
Change-Id: Idc3840132d7f95f8e22045d7484c528d828bb0de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/24917
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When clearing events from the EC, an error is returned when we try
to clear an event that doesn't exist. This is normal, but can
be distracting when trying to track down an error, so add a message
saying that the error is expected.
BUG=None
Test=Build Grunt with SMM debug enabled. See message before
"EC returned error result code 1".
Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/24914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Intel DCI (direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0
only.
BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.
Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
If switch to VT2 on nautilus, screen flicker appears. We found if we
rollback the change of slew rate setting, then the flicker issue will
be gone: https://review.coreboot.org/c/coreboot/+/22588
But nautilus board needs slew rate tuning to reduce EE noise, so we
decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of
rollback the whole change of the CL:22588. It can remove the flicker on
VT2.
BUG=b:71397040
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Due to there are some chances USB devices can not be detected.
USB2 port#1 and #4 PHY register need to be overridden for variants
Santa/Lava/Blue/Bruce/Astronaut.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I401905685cc3078df657919b162272c3de320296
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/23881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.
BUG=b:73898539
TEST=Boot, see WLAN controller in lspci
Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24916
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The printk() calls in sb_program_gpios() aren't necessary, and incur a
13 second delay if the function is called from
bootblock_mainboard_early_init(). This commit removes them so GPIOs can
be set up earlier.
TEST=call sb_program_gpios from bootblock_mainboard_early_init
BUG=b:73898539
Change-Id: I064291decf47d86132e36469e029b3262ec20172
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- consolidate commonality in meowth and zoombini's SPD makefiles into
a common zoombini/spd/Makefile.inc
- move all SPD hex files into zoombini/spd directory
- move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc
BUG=b:69011806,b:71776625
BRANCH=master
TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot'
compile and boot successfully.
Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23874
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In PORTSC, Port Enabled/Disabled(PED) is RW1CS.
When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS.
This change is inspired by xhci_port_state_to_neutral in linux driver.
It will mask all RO and RWS bits and set WDE and WCE.
BUG=b:70777816
TEST=System won't be awakend from s3 automatically when usb devices
is attached. Also system can be awakend by hotplugging usb
devices under S3.
Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds a boot state callback to print ME version after
DEV_ENABLE is complete. Information is printed only if UART_DEBUG is
enabled because talking to ME to get the firmware version adds ~1
second to boot time.
TEST=Verified on Soraka that ME version printed is correct.
Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.
TEST=Check CBMEM table has correct RAM regions.
Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some DIMMs have invalid strings when it comes to device part number
(bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused
space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ),
all others should be ASCII.
Create a test that detects invalid strings and replace invalid
characters with *. If a replacement was made the output string then must
be <Invalid (replaced string)>.
BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Use code to examine SMBIOS,
while testing different valid and invalid strings.
Remove string injection before committing.
Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Kahlee DIMM have invalid string when it comes to part number
(bytes 0x149-0x15c). We currently force a NA string, but grunt has the
proper strings. Just let the string go through, and a second commit
within smbios.c will be responsible for testing the string and taking
proper action.
BUG=b:73122207
TEST=Build, boot and record serial output for kahlee while injecting
different strings to dmi17->PartNumber. Remove string injection before
committing.
Change-Id: I427262873f9ec80f459245e5f509e28a68de3074
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
* if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.
This patch fixes this issue. Thanks coverity!
Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change adds a config option to allow mainboard to override
the console loglevel. When the option is set, the platform has
to define the function get_console_loglevel returning a valid
loglevel value.
This allows a mainboard to sample a GPIO to switch the loglevel
value between different environments (qualification vs production)
without re-flashing.
Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.
BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.
Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.
TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858
Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.
TEST=None
BUG=b:72875858
Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on PCH iSCLK for meowth platform.
BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.
Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order for ddr2.h and ddr3.h to be included in the same file it
cannot have conflicting definitions, therefore rename a few things and
move some things to a common header.
Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Updating from commit id 9fb10386a: 2017-06-21 04:19:06 -0700
(Poppy: Configure camera PMIC to low power mode.)
to commit id 927b64a0b: 2018-02-15 00:10:45 -0800
(meowth: zoombini: enable CONFIG_CMD_PD_CONTROL)
This brings in 1205 new commits.
Change-Id: I3f7a1ceb1ea8c70d57a8f067023358b93df2670b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.
Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Funtion fstat will return -1 if there's any error, 0 if successful.
Check that fstat return is equal to 0, print error message and exit if
not 0.
This fixes CIDs 1353018 and 1353020
BUG=b:72062481
TEST=Build no errors
Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since FSP version 7.x.11.43, more HDA Audio link options are exposed,
so included that into coreboot. Users can modify that base on platform
implementations.
BUG=None
TEST=Boot up with debug build version FSP and check the debug print
result on meowth platform.
Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This function performs SBI communication
Input:
* PID: Port ID of the SBI message
* Offset: Register offset of the SBI message
* Opcode: Opcode
* Posted: Posted message
* Fast_Byte_Enable: First Byte Enable
* BAR: base address
* FID: Function ID
* Data: Read/Write Data
* Response: Response
Output:
* 0: SBI message is successfully completed
* -1: SBI message failure
Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23809
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow bootblock to get access to the entire static device tree
as other stages can access independently.
TEST=SMM code now can access devicetree.cb variables.
Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The rationale is to allow the mainboard to override the default
baudrate for instance by sampling GPIOs at boot.
A new configuration option is available for mainboards to select
this behaviour. It will then have to define the function
get_uart_baudrate to return the computed baudrate.
Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some assumptions are made with respect to CONFIG_ROM_SIZE being the
actual size of the boot medium, e.g. when automatically creating an
fmap with and RW_MRC_CACHE region. With this patch the user is
warned when this is detected.
Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GRUB2 doesn't support all architectures that coreboot supports.
Furthermore, coreboot's build script for GRUB2 doesn't support all of
these architectures.
Let the user select GRUB2 only when building for x86 and ARM, which are
known to work.
Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".
This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.
Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.
Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.
Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Due to changes in the RISC-V Privileged Architecture specification,
Linux can now be started in physical memory and it will setup its own
page tables.
Thus we can delete most of virtual_memory.c.
Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.
NOTE: Spike does support RVC, but currently doesn't select
ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
support RVC.
Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.
Add the necessary alignment directive before trap_entry.
Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
... and fix them in the process.
The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.
Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ATF tegra210 platform supports more than the currently used
'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h
in the ATF tree.
Add the missing parameters and set them accordingly. The passed UART id
is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the
same port for console output as coreboot.
Successfully tested with UARTB.
Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Don't always set up UARTA, but instead honor
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the
chosen UART.
Now the matching clock for the used UART is set up.
(The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which
in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.)
Change-Id: Ife209d42af83459136a019c21c2a069396ab36db
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In case of console dump for only the last boot, cbmem utility checks
for a list of regex in provided order. When pre-cbmem console
overflows, "Pre-CBMEM <stage> console overflowed.. " message is added
before "... <stage> starting" message. This change fixes the order of
regex in cbmem utility to match this.
Test=Verified on soraka that "cbmem -1" correctly dumps the data
starting from Pre-CBMEM romstage overflowed.
Change-Id: I9c5667bbd02ed3e93ac77a4f42e87d754a062919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch syncs ec_commands.h with the one in chromeec.
BUG=b:70294260
BRANCH=none
TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz.
Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.
With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.
The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.
BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)
Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The google_chromeec_wait_for_display API checks whether a display is
ready or not. It waits in a loop until EC says it entered DisplayPort
alternative mode or times out in 2 seconds.
BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"
Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The google_chromeec_pd_get_amode API checks whether TCPM is in a
specified alternate mode or not.
BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"
Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.
BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.
Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
board_status.sh was originally written for use cases where the DUT
is remote, i.e. accessed via serial port or SSH. This lead to some
issues when attempting to run the script on the DUT itself.
This patch attempts to handle the local use case more gracefully.
sudo is used when running the cbmem command, and the '-c' option
can be used to set cbmem path in case it's not in the default path
used by sudo.
Change-Id: I62957678ccae65fc46fd6ddf5ae92983d36cffad
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
AMD's fixed MTRRs have RdDram and WrDram bits that route memory
accesses to DRAM vs. MMIO. These are typically hidden for normal
operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to
BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at
reset, should be set for configuration during POST, then cleared for
normal operation.
Attempting to modify the RdDram and WrDram settings without unhiding
them causes a General Protection Fault. Add functions to enable and
disable MtrrFixDramModEn. Unhide/hide as necessary when copying or
writing the fixed MTRRs.
Finally, modify sipi_vector.S to enable the bits prior to writing
the fixed MTRRs and disable when complete.
This functionality is compiled out on non-AMD platforms.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SMBIOS structure type 17 is not being generated because memory info is
not being stored to cbmem. This has to happen after AGESA AmdInitLate
has run, but before SMBIOS is generated. There's a need to convert
format between AGESA generated info, and what is required in cbmem.
Create a procedure that transfers information between AGESA and cbmem,
and call it from agesawrapper_post_device() after AmdLateInit is called.
BUG=b:65403853
TEST=build and run kahlee, verify if SMBIOS structure type 17 is being
generated, and if associated strings are what should be expected.
Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.
BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK
Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.
Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, at the end of a build `CBFSPRINT` prints the content of all
CBFS regions. This is confusing, as they are identical. To avoid
confusion print the layout beforehand.
> layout [-w] – List mutable (or, with -w, readable) image regions
Change-Id: Ibf03b125ef6dae41c58b8ae867430047778cfff3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Kconfig variables TIANOCORE_REVISION and TIANOCORE_REVISION_ID
do not have an effect without this fix, the build process would
checkout the hard-coded stable hash even if these variables are set.
Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/22983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C
bus. Add a chip driver to support this chip.
Beside the pure chip driver two interface functions are provided to read
the state of the pins and write output values to the pins.
As the slave address of this chip is hardware configurable the function
pca9538_get_dev() is used to get the right slave address. This function
needs to be implemented in mainboard code if one needs to use the
interface functions to read and write I/O state.
Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a struct for registers along with some bits from ATF to
the generic PL011 driver. It also adds a naive implementation of
uart_tx_flush() which was previously stubbed out.
Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There are now a few architectural extensions available for ARMv8, some
of which introduce instructions or other features that may be useful.
This allows the user to select an extension implemented on their SoC
which will set the -march option passed into the compiler.
Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
AMD support in coreboot has typically not used the AmdS3FinalRestore()
Entry Point. Add a call to it immediately prior to resuming to the OS.
BUG=b:69614064
TEST=Check console log for execution
Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add new functions that can execute InitRtb, InitResume, LateResume,
and FinalResume.
Note that the name AmdInitRtb supersedes the deprecated AmdS3Save.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The AGESA spec states that "Failure to release a structure can cause
undesired outcomes."
Uncomment the one in AmdInitLate(). The function only dealocates the
structure used for the AGESA entry point, and not the internal data
used by coreboot.
Release the structure in AmdInitEnv(). This appears to have been an
omission years ago when duplicating agesawrapper.c for every mainboard
was still common.
BUG=b:70671742
TEST=Build and boot Kahlee, inspect console log
Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22888
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
* Non-volatile: Information that is the minimum required for bringing
the DRAM controller back online. This change uses the common
mrc_cache driver to manage the storage
* Volatile: May be stored in DRAM; information required to complete
the system restoration process.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Commit 07fe618 [chromeec: Add support for reading second battery info]
added a mutex as part of the ACPI code to determine battery statuses.
Windows is extremely picky about ACPI code, and attempting to acquire
a level 1 mutex without first having acquired a level 0 mutex causes
Windows to hang on boot. Since there's no reason to use a level 1
mutex here, change it to level 0.
Test: Boot Windows on device with ChromeEC without hanging
Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.
Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.
BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.
Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.
Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.
BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This change makes Nami platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:70646770
TEST=Verify kernel reads new strings.
Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Both GRUB and SeaBIOS can chainload lzma compressed payloads.
Therefore it is beneficial to compress secondary payloads
like Memtest86+, coreinfo, nvramcui,... for both size reasons and
often also speed reasons since the limiting factor is generally the
IO of the boot device.
Tested with SeaBIOS and memtest86+ master on Thinkpad X220.
Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from
Analog Devices. On some boards they are a used to convert a PDM audio
data stream from a DMIC to an I2S signal.
Add a driver for populating ACPI table entries for this part.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
When running 'make distclean' on coreboot, the build cleans the tools
as well. Since secimage didn't have a distclean target, it gave an error
that the distclean target didn't exist. This didn't actually affect
anything more than the secimage clean, but it was impossible to tell
that from the warning:
% make distclean
make[1]: *** No rule to make target 'distclean'. Stop.
Change-Id: I4b4bcc1ab48e767218d31e455d23527acedf4953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For system without secondary battery, current DSDT will report warning
during build time. Add a conditional check to make sure only battery
index 0 can return success.
TEST=Build pass.
Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.
Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.
Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for KBL RVP8 board
* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.
TEST= Build and boot RVP8.
Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out, it will:
- Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index
- Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value
- Then fetch the data
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23598
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Improve the file with:
* C99 inializations for structures
* reorder include files for aesthetics
* remove extraneous whitespace
* remove a stale comment
* make variable naming consistent
* make function arguments consistent
This change clears up all remaining checkpatch issues with the wrapper
with the exception of errors created with AMD definitions, e.g.
ERROR: need consistent spacing around '*' (ctx:WxV)
#32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32:
void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {}
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Leverage the stage_cache mechanism to store a non-specific type
of data. This is not interesting when the location for the cache
is in cbmem. However it will be more useful when an external
location is used, e.g. when the cache is in TSEG, locked from user
modification.
Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.
Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.
Add new Kconfig option to address this delta between different PCH.
Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).
Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.
BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In TPM 2.0 case, if the factory initialization is interrupted after
defining, say, the kernel tpm nvram space but before writing to this
space, the following will happen upon reboot when the factory
initialization will be re-attempted. Writing to this space will be
skipped, and coreboot will finish the factory initialization with
this space remained unwritten. At a later stage, when the rollback
logic will attempt to check the version in the kernel space, it will
fail (TPM2.0 returns an error when reading from unwritten spaces),
and the system will go into recovery with no way out (since the
kernel space will never be written).
This change fixes that by always writing to the kernel, MRC hash and
firmware spaces during factory initialization, even if the space
already existed by that time.
BUG=b:71884828
TEST=delete, define, but not write to the kernel space; trigger
factory initialization; coreboot should fill the kernel
space and continue booting.
Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b
Signed-off-by: Andrey Pronin <apronin@google.com>
Reviewed-on: https://review.coreboot.org/23456
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch stores the correct capabilities for EMMC media which in turn
sets the correct timing data for HS400 mode.
Without this code change, EMMC CMD13 is failing at the end of HS400 mode
switching.
BUG=none
BRANCH=none
TEST=Build and boot Soraka
Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23541
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.
Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.
BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.
Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the
use of fallback/normal with both the native raminit and the mrc.bin.
Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that
128MB less is available to devices using the native raminit. Most
devices reserve 2048M for non memory resources below 4G, which in most
cases is more than adequate. Devices with only 1024M (and that don't
already use the mrc.bin) are:
* lenovo/x220
* lenovo/x230
* lenovo/x131e
* lenovo/x1_carbon_gen1
Those could fail to allocate PCI resources, but on at least x220 with
a somewhat default configuration (USB3 expresscard, Wireless PCIe
card) it still boots fine, so one should not expect many problems from
this change.
Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.
This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.
Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The registers were taken from the wrong addess since the spibar offset
was not added to it.
This also fixes the endianness.
Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After adding NHLT and max98373 amp support, cnlrvp fails to boot
with error: out of memory (free_mem_ptr >= free_mem_end_ptr).
Increase HEAP_SIZE from 0x4000 to 0x8000.
BUG=None
TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp
and verify cnlrvp boots to kernel.
Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB
for size for video RAM.
Order the entries like in `cmos.layout`.
Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable HotPlug for the PCIe root port that the WiFi device
is on so the OS can re-train the link without needing a reboot
if it goes down unexpectedly at runtime.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in
linux that it is identified as a HotPlug capable root port.
Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a variable to fill out the FSP UPD variable for PCIe HotPlug,
which allows a mainboard to enable HotPlug on individual root ports.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux
that it is identified as a HotPlug capable root port.
Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.
BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
chromeos-mrc coreboot chromeos-bootimage" & ensure correct
PsysPmax value is passed to FSP-S through UPD. Verfied on
KBL-R and KBL-U SKUs.
Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On EVT, the USB and MIPI cameras share the same power source. As a result,
when the MIPI camera driver turns off the camera once probed, USB camera will
be disconnected. To make USB camera work on EVT devices, we will need a hack in
coreboot to leave the camera power always-on.
BUG=b:72839352
TEST: Verified the MIPI and USB camera function on DUT board
TODO: This power issue will be fixed on DVT build. Will revert this patch
once confirmed power sources for MIPI and USB camera could be supplied
individually.
Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/23546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andy Yeh
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails,
it falls back to GPIO pins.
BUG=b:70294260
BRANCH=none
TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz.
Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds EC_CMD_GET_CROS_BOARD_INFO and two APIs to fetch
OEM ID and SKU ID from cros EC.
CBI abbreviates Cros Board Info.
BUG=b:70294260
BRANCH=none
TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz.
Change-Id: Iff69a2dc0e562d87dd287f79c407f23aeb09fb9e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface.
BRANCH=none
BUG=none
TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also
check that lidclose/lidopen command from EC console wakes system up from
S3 or S0ix.
Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A file that has several methods cannot be included inside a method. It has
to be included inside a scope, but not inside a method or it'll cause
problems (instability).
There is an ugly construction in method _INI. It's needed because if AmdImc
is not included then the call to ITZE would break the build.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating from commit id a5efee5:
2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs)
to commit id 19dea8d:
2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9)
This brings in 2 new commits.
Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23562
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Cherry-pick from Chromium:
a60ac10 [Lars: Turn on keyboard backlight in romstage]
Use the keyboard backlight to provide indication that the system is
booting. This is useful for determining that a system is in S0 and
is running BIOS code.
TEST=boot on Lars and see keyboard backlight come on early
Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Combination of several commits from Chromium tree:
949037c [Lars: coreboot GPIO changes for EVT]
c286789 [Lars: Set USB Type A current limit to 2A]
0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]
4a0650d [Lili: Support touchscreen]
Disable unused GPIOs based on schematic and
adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.
Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A
charging from the USB Type-A port.
GPP_F_23 is set to NC currently and is floating, causing the on-board
speaker to have no audio or the audio has noise; set to output/low.
These commits bring lars' GPIO mapping in line with the Chromium tree.
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397
Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec
Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com>
Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com>
Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium:
99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig]
This string was left at the default for kunimitsu and should be
updated to indicate the proper mainboard.
Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Combination of several commits from Chromium tree:
3b875a2 [Lars: Update Memory ID for DVT board]
b6d7c63 [Lili: Update Memory IDs]
f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD]
a6571bf [Lili: Update Memory IDs]
80e1841 [Lili: Update Memory IDs]
58d4487 [Lili: Fix memory string show error in spd data]
These commits bring lars' SPD data in line with the Chromium tree.
Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084
Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39
Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b
Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991
Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab
Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit:
af3ec09 [Lars: Add sdmode-delay device property for maxim98357a]
Add "sdmode-delay" as a device property for the maxim98357a codec.
This speaker amp requires both SFRM & BCLK to active and stable
before it is unmuted. If there is a BCLK and no SFRM,
that results in a pop noise.
Adding a configurable delay parameter for all Skylake platforms
to allow sufficient time for the BCLK & SFRM on I2S to be stable
before the amp unmutes itself to avoid a pop noise at the start of playback.
Setting the delay to 5ms since the observed delay between SFRM and unmuting
of the amp is around 2ms.
Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.
Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit:
848ee3a [Lars: Add device properties for Nuvoton codec]
Update sar-threshold, sar-compare-time, sar-sampling-time
properties to match values in lars' Chromium branch.
Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.
Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium:
55c0eb3 [Lili: Set new thermal parameters]
Set new parameters of DPTF for both Lars and Lili.
The acoustic will have higher 1.6dB in transition mode,
when using Lili fan table on Lars.
Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.
BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
expected. Test on Fizz, which will set these values in
mainboard.
Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
read_resources in common/block/pmc/pmc.c is corrupting the BAR
at offset 0x20.
pch_pmc_read_resources
|
pci_dev_read_resources
|
pci_get_resource
Within pci_get_resource, the BAR is read and written back. Since read of
ACPI BAR does not return the correct value, the subsequent write
corrupts the BAR. Hence re-programming the BAR. Also, reading PMC
STATUSCOMMAND register does not return bit 0 correctly in
pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled.
Hence making sure IO ACCESS gets enabled by setting dev->command
TEST=Can boot to OS
Without this change coreboot will be stuck at "Disabling ACPI via APMC:"
Change-Id: I27062419d06127951ecbbb641835d06ca39ff435
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The wifi card was not being powered, and was being held in reset during
PCI enumeration, so it was not being brought up.
BUG=b:72738963
TEST=Verify wlan card shows up in lspci
Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23552
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change ensures that the RTC failure bit is cleared in PMCON1
after cmos_init checks for it. Before this change, RPS was cleared
in dev init phase. If any reboot occurred before dev init stage
(e.g. FSP reset) then RPS won't be cleared and cmos_init will
re-initialize CMOS data. This resulted in any information like VBNV
flags stored in CMOS after first cmos_init to be lost.
BUG=b:72879807
BRANCH=coral
TEST=Verified that recovery request is preserved when recovery is
requested without battery on coral.
Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the way coreboot builds ARM TF to pass the new
COREBOOT flag introduced with the following pull request:
https://github.com/ARM-software/arm-trusted-firmware/pull/1193
Since the new coreboot support code supports the CBMEM console, we need
to always enable LOG_LEVEL INFO. Supporting platforms will parse the
coreboot table to conditionally enable the serial console only if it was
enabled in coreboot as well.
Also remove explicit cache flushes of some BL31 parameters. Turns out we
never really needed these because we already flush the whole cache when
disabling the MMU, and we were already not doing it for most parameters.
Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Rockchip UARTs are tied directly to the 24MHz oscillator and are
thus clocked with exactly 24MHz. The reasons why our code instead uses
some 23.xxMHz value have long been lost in time. For the current shared
8250 implementation, the baud rate divisor for 115200 would be the same.
Correcting this does make the information in the coreboot table more
accurate and help payloads chose a better divisor, though.
Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch updates the arm-trusted-firmware submodule from:
commit 9fd4a36c408a254d887106e6e3960d496456be2c
(Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
to
commit 693e278e308441d716f7f5116c43aa150955da31
(Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch)
This brings in 79 new commits.
Change-Id: Ieceb07760178f8ddbb5cafebabeb78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We found when ambient temperature low, with now saradc frequency and
delay between saradc power up and start command, there may get wrong
adc value, then get the wrong ramid or boardid, so lower the saradc frequency
and add the delay time between power up and start command.
BUG=b:70692504
BRANCH=gru
TEST=test on Dru in 0C temperature, always get right adc value
Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is a line artifact in the lower third of the display with the
current initialization code. So update it with code provided by
Innolux to fix this issue.
BUG=b:69689064, b:72191820
TEST=boot on dru with an Innolux panel and artifact line disappear.
Change-Id: I9679c4f7f706fd6cd2e1dba7ec79e772fe3f227a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When booting kahlee, there's an error message: "Warning: Can't write PCI
IRQ assignments because 'mainboard_pirq_data' structure does not exist".
This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data.
BUG=b:70788755
TEST=Build and boot kahlee. Warning message must be gone.
Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The designware i2c controller indicates that the slave address
shouldn't be programmed while the controller is enabled. Therefore,
switch the ordering of the slave target address and the enable.
Additionally, ensure the controller is disabled prior to the
start of the slave programming sequence.
Lastly, chunk up the i2c_msg segments at differing slave address
boundaries. That allows for simpler programming for the controller
by only doing one slave address transaction chunk at a time.
BUG=b:70232394,b:69250772
Change-Id: Iebc08e2db847cb182fad98e0ff3d799b9a64aca7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Part of the original patch, commit 85a90e1, reverted edk2 commit:
1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED]
which had the unintended effect of causing memory above 2GiB
from being unavailable (marked reserved) when booting without a
connected display (aka headles mode).
This commit strips the patch to only the component needed to fix
reading of the coreboot table low memory pointer.
TEST: boot 4GB google/panther without connected display, verify
memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m'
Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
FSP_GOP needs a vbt.bin to work but before this patch it was able to
build with the default configuration which was an empty path for
vbt.bin.
To make Jenkins happy don't select FSP_GOP by default, at least until
all boards have the proper vbt blobs in the blobs repo.
Change-Id: Ibc36d6d4dd1a56c53819b169e6f4799ce3c23e03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Update the shared AGESA headers to 1.3.0.9.
This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.
BUG=b:72679320
TEST=build and boot Grunt
Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Communicate additional status to the console when the save and load
functions do not function as expected. The most likely scenario for
an error is when using a cache that is external to cbmem, and restricted
in size.
Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Revert most of 4f3f47b "amd/common: Define regions in cbmem". This
puts the management of the heap space back to its traditional
methodology. Subsequent patches that were to have used these
subregions have been reworked.
BUG=b:69614064
Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel requires the display oprom is loaded *and* ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:72400950
Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23506
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Certain platforms require that the option rom always needs to be
ran in order for display to work correctly. Therefore, provide
this ability for the platform to select such that we force option
rom loading.
BUG=b:72400950
Change-Id: I597bc8af7ac8b68fe8505aac5f1c7e1ccd34ac27
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23505
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit removes a manually written asl file in favor of configuring
the trackpad through devicetree.
BUG=b:72121803
TEST=cat /proc/interrupts with trackpad connected
Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23508
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.
Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The calculation to set up the PM timer emulation is using an
incorrect common timer clock value that was copied from Apollolake.
According to the PDG Skylake and Kabylake clocks are derived from a
24MHz XTAL, not 19.2MHz like Apollolake.
Fixing this value results in the proper "correction value" to be
programmed into the PM timer emulation MSR that matches the raw value
that would be programmed by FSP. (if it were doing MpInit)
Old PM timer correction value: 0x2fba2e25
New PM timer correction value: 0x262e8b51
Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Write _ROM method and store PCI Option ROM in CBMEM.
Allows an EFI compatible OS to retrieve the Option ROM without the need
to access the PCI BAR. As the Option ROM is no longer present in the
legacy VGA area it's required for mobile platforms. On hybrid devices,
like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to
retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to
map.
Tested on:
* Lenovo T530
* Linux Kernel 4.13.7
* nouveau
Change-Id: I548b730fb64833083cc05af5b21dd6959804224b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required
firmware information right after FSP-S.
TEST=Display FW information as below
>> Display FSP Version Info HOB
Reference Code - CPU = 7.1.20.52
uCode Version = 0.0.0.16
Reference Code - ME 11.0 = 7.1.20.52
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - CNL PCH = 7.1.20.52
PCH-CRID Status = Disabled
CNL PCH H A0 Hsio Version = 2.0.0.0
CNL PCH H Ax Hsio Version = 9.0.0.0
CNL PCH H Bx Hsio Version = 5.0.0.0
CNL PCH LP Ax Hsio Version = 13.0.0.0
CNL PCH LP B0 Hsio Version = 7.0.0.0
CNL PCH LP Bx Hsio Version = 6.0.0.0
CNL PCH LP Dx Hsio Version = 2.0.0.0
Reference Code - SA - System Agent = 7.1.20.52
Reference Code - MRC = 0.5.1.19
SA - PCIe Version = 7.1.20.52
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.0
SA-CRID New Value = 0.0.0.0
Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23387
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch locates FSP FVI hob in order to extract all firmware
ingredient version information.
So far this feature is only supported for CannonLake SoC onwards.
Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot
platform using CannonLake FSP new feature.
Expectation is that, FSP will provide version information of all Firmware
ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code,
CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version,
PCH Ref Code version etc.)
Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures MemInfoHob.h file can make use of existing UEFI
headers as is rather than redefining the same structure locally.
TEST=Download BIOS_Version_122.3 from external github and
build MemInfoHob.h without any compilation error.
Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Users are getting build error due to duplicate macro definitions
of same resource type between fsp driver code and UEFI headers.
Hence this patch ensures to refer a single source location for
macro definitions to avoid compilation error.
Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess"
Removed most of the writes to RCBA(FD) and renamed the function to
mainboard_rcba_config.
Writes to FD are properly handled in ramstage, so no need to do it in
romstage.
Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change GPIO settings for meowth rev 2 boards.
Changes include:
- GPP_B7 set to no-connect
- GPP_C1 set to no-connect
- GPP_D8 set to no-connect
- GPP_D9 (PP3300_WLAN_EN) set as output with initial value high
- GPP_E9 (DCI_CLK) set to no-connect
- GPP_E10 (DCI_DATA) set to no-connect
BUG=b:72202352
BRANCH=none
TEST=none
Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings
were causing false overcurrent conditions as OC0 and OC1 were used for
other purposes.
Remove initialization of unused usb3 ports, and configure the ports we
use (usb3 ports 0 & 1) to use OC2 and OC3, respectively.
BUG=b:72250084
BRANCH=none
TEST=Verify meowth can recognize and boot off a kernel on USB drive.
Change-Id: I528b67d80a1da84e5307facb40de545089979f57
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change selects EC tablet event and provides trip point
temperatures for tablet and non-tablet mode so that DPTF can
be supported depending upon device mode.
BUG=b:65467566
TEST=Verified by changing modes that the trip point temperatures are
updated in the
OS (/sys/devices/virtual/thermal/thermal_zone{2,3,4,5}).
Change-Id: I071868982fa87821550b870a6d8050cf2a030b49
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23463
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change decouples EC tablet event and TBMC device by guarding
TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It
allows mainboards to use tablet events without having to define a TBMC
device.
BUG=b:72554519
Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with
the tpm. This change allows devicetree entries to use a irq_gpio entry
to describe the interface with the TPM.
BUG=b:72655090
Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since the h1 i2c bus is required for verstage mark the bus
as needing to be initialized early. That way, the bus is initialized
in bootblock prior to verstage.
BUG=b:70232394,b:69250772
Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The spi flash host controller has a dedicated register for the
opcode. Therefore, indicate to the spi subsystem that the opcode
size should not be taken into account when determining maximum
payload size in spi_crop_chunk(). This allows the full use of
the fifo when doing transfers.
BUG=b:65485690
Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23492
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Innolux didn't deliver a working init sequence yet for devices without
OTP programming. The sequence in this change has been derived from a
register dump of a mostly working panel with OTP. It is not meant to
be final, but to make devices with unprogrammed OTP work, while Innolux
is figuring out a proper sequence. There is a known issue with an
artifact line in the lower third of the display.
Change-Id: I7096506208e4cb29c5f31a7ac502231a6c23ac92
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some panels need to transfer initial code, and some of them will be
over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi
dsi transfer function to support it.
Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set PsysPl2 values to 90% of max adapter power for all types of
adapters (typeC and barrel jack) to account for a 10% power loss from
the adapter to the soc.
BUG=b:71594855
BRANCH=None
TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set
with iotools rdmsr command on both U42 and U22 skus with both
typeC and barrel jack power adapters.
Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I measured the rise and fall times for I2C bus 1 from userspace
manually, using "i2cdetect 1" called from userspace and an oscilloscope.
This commit fixes the values there to reflect reality.
BUG=b:72442912,b:70232394
Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23459
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just
passing full size buffers to the spi controller ops. However, the
code wasn't honoring what the spi controller can actually perform.
This would cause failures to read on controllers when large requests
were sent in. Fix this by introducing a
spi_flash_cmd_read_array_wrapped() function that calls
spi_flash_cmd_read_array() in a loop once the maximum transfer size is
calculated based on the spi controller's settings.
BUG=b:65485690
Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Both early platform information reporting in bootblock and common code
CPU driver will add support for cannonlake D0 stepping processor.
BUG=None
TEST=Boot up system with D0 stepping CPU installed, check serial log
that can display as D0 stepping.
Change-Id: I76ee974ee027100d7853a110f95b1601987492e4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500. This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.
Note that BiosRam may only be accessed byte-by-byte. It does not decode
normally.
Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23436
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This uses the functions in include/mrc_cache.h instead of
northbidge/intel/common/mrc_cache.h
Tested working on Lenovo Thinkpad x220, mrc_cache region gets written
and S3 resume still works fine.
Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds _PRW property to CREC device that allows Linux kernel
to identify CREC as a wakeup source.
BUG=b:69118395
TEST=Verified following steps:
1. Under sys devices for CREC: "echo enabled > wakeup"
2. Lid close/Lid open -- Verified that wakeup_count increases
3. Mode change -- Verified that wakeup_count increases
Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The `lint-extended-015-final-newlines` script skips over executable
files and thus leaves script files unchecked.
Use `file` to find scripts and include them in the `final newlines`
checks. Whitelisting is used including bash, perl, python and sh
scripts.
Change-Id: I8649b261b7e2cbbac7f9b90a9ace3f1c7b0eedeb
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23325
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change updates the camera power enable GPIOs as per the latest
schematics. With this update, since one of the enable GPIOs is using a
UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that
FSP-S does not re-configure the UART0 GPIOs.
BUG=b:68964831
Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following two patches were independent, but they were
merged together. However, the first one changed the API
that the second was originally was written against. Fix build.
b94a2750 (i2c/designware: reduce API complication for bus config)
13101a7b (soc/amd/stoneyridge: Add I2C devicetree support)
BUG=b:72121803
Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some x86 platforms don't have a TSC that is invariant w.r.t.
rate to get accurate timestamps. As such a different timestamp
is required. Therefore, allow one to specify non-TSC timestamp
source and not compile in the default x86 TSC code.
BUG=b:72378235,b:72170796
Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I2C bus configuration is generally set up in devicetree.cb. This change
establishes listings for the buses so that they can be used (though
followup changes should update the buses to have correct timings).
BUG=b:72121803
Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required to add support for I2C devices on Kahlee to ACPI tables
via devicetree.cb. Without this, operations are not emitted for I2C
devices and the proper ACPI table entries are not generated.
BUG=b:72121803
Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add support for a mmio resource in the devicetree to allow
memory-mapped IO addresses to be assigned to given values.
AMD platforms perform a significant amount of configuration through
these MMIO addresses, including I2C bus configuration.
BUG=b:72121803
Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change disables SATA controller in order to make SATA IP enter
low power status.
BUG=b:72332817
TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status
and verify SATA IP enters low power state
Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the call to pch_enable_lpc() from romstage to bootblock.
In other words, it happens earlier in the boot process. Turns out, we
need this to talk to the EC to determine if we're in recovery mode or
not.
BUG=b:69011806
TEST=boots to linux
Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FSP 2.0 Memory_Info_HOB for KBL is not sending
"MemoryType" value as what is required for SMBIOS Table
according to SMBIOS Spec. Thus, converting the value
retrieved from FSP HOB to the correct value.
This change will not be required for upcoming SOCs since
FSP have fixed this issue in its next platforms and thus it
will take care and send the correct value in "MemoryType"
field based on SMBIOS spec. Thus this conversion from coreboot
will not be required in the next platfoms. "MemoryType" value
can be directly passed to dimm_info_fill() function.
BUG=none
BRANCH=none
TEST=Tested in Soraka, and getting the value as 0x1D for
LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17
will also show correct information. Currently, it was showing
"Unknown".
Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23384
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In payloads/nvramcui/payload.sh line 5:
DIR=`dirname $0`
^-- SC2006: Use $(..) instead of deprecated `..`
^-- SC2086: Double quote to prevent globbing and word \
splitting.
In payloads/nvramcui/payload.sh line 6:
lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1
^-- SC2086: Double quote to prevent globbing and word \
splitting.
^-- SC2086: Double quote to prevent \
globbing and word splitting.
^-- SC2069: The order of \
of the 2>&1 and the \
redirect matters. The \
2>&1 has to be last.
Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The function read() returns the number of bytes actually read. Program is
assuming it actually read the required number of bytes without checking.
This is wrong.
This fixes CIDs 1353019 and 1353021
BUG=b:72062481
TEST=Build no errors
Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For the internal eMMC to be used by non-chrome for installation,
the CARD device and _RMV methods are required. Without these,
other OSes does not show the eMMC as a valid installation target.
TEST= boot CNL-RVP with Tiano payload and install Windows 10
to the internal eMMC drive.
Change-Id: Icfdccd88bc113d97c2fabf4c63d8d772737a6057
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In ramstage the device_operations are needed for the i2c designware
host controller. Move the intel/common/block/i2c implementation
into the generic driver so other platforms can take advantage of it.
BUG=b:72121803
Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If one wants to implement both i2c_bus.h and i2c_simple.h APIs
the compilation unit needs to be guarded or coordinated carefully
with different compilation units. Instead, name the i2c_bus
functions with _dev such that it indicates that they operate on
struct device. One other change to allow i2c_bus.h to be built in
non-ramstage environments is to ensure DEVTREE_CONST is used for
the dev field in struct bus.
BUG=b:72121803
Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds AC and DC loadline settings since vr_config_enable is
set. Without correct AD/DC loadline settings, VRs reported incorrect
VID values which caused CPU freqency clipping. The clipping reason
could be retrieved from MSR 0x64F. From VRTT report, the AC/DC
loadline resistances are within spec, we can use default value defined
in Table 6-1, doc #543977.
BUG=b:70646304
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline
settings from DCI to ensure the values were programmed correctly.
Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23349
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice.
By doing this, SoC can see the DMIC DATA and use for WoV processing.
Thus configuring GPIO_173 as IGNORE IOSSTATE.
TEST=put DUT in S0ix, verify DUT wakes up
Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23246
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating from commit id f3bb31fee:
2017-09-08 (vboot: Support EC early firmware selection)
to commit 61cfcc3b:
2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2)
This brings in 57 new commits.
Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updating from commit id f6780a36:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)
to commit id e0b38418:
2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.)
This brings in 25 new commits.
Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updating from commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
to commit id 9fd4a36c:
2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state)
This brings in 596 new commits.
Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
File open function <open()> will return -1 if there's any error. Check that
the return is greater or equal to 0 before using fstat(). Print error message
and exit if there's an error.
This fixes CIDs 1353018, 1353020, 1353027 and 1353028
BUG=b:72062481
TEST=Build no errors
Change-Id: I77d6973d1ad1eadb93922866e618038045be5937
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune I2C params for I2C bus 5 to ensure that the frequency does not
exceed 400KHz.
BUG=b:65058277
BRANCH=None
TEST=Measured bus frequency for audio <= 400MHz
Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix
Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21610
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data
from agesa_board_gpios[], wrap format and delete agesa_board_gpios[].
Finally, make platform_FchParams_reset() an empty function.
BUG=b:64140392
TEST=Build gardenia.
Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[]
with data from agesa_board_gpios[], wrap format and delete
agesa_board_gpios[] and get_gpio_table(). Then remove the
get_gpio_table() call from BiosCallOuts.c. Finally, remove
get_gpio_table() from
google/kahlee/variants/baseboard/include/baseboard/variants.h.
BUG=b:64140392
TEST=Build grunt. Build and boot kahlee, recording serial output. Search
for "stage bootblock" and "stage ramstage", indicating GPIO being
programmed.
Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add new function sb_program_gpio to be called after AGESA init_reset
and some point within ramstage. For AGESA init_reset, change
amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init
(add the function after the call to AGESA function).
BUG=b:64140392
TEST=Build kahlee, grunt, gardenia.
Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22987
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings)
provides correct iccmax settings for kbl-u based on the SKU. Thus,
there is no need to override these values in devicetree. This change
gets rid of iccmax settings in the nami devicetree.
Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
PC10 is a necessary condition for S0ix entry. With the current C-state limits,
CPU fails to enter PC10 during S0ix. C-state Latency control limits
have to be tuned to new values for PC10 entry.
Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/23220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Linters try to determine whether they are running in a git worktree so
that `git grep` can be used instead of `grep`. These checks are done in
different not truly correct ways and thus the linters don't use `git
grep` when running from a worktree subdirectory, e.g. in a git subtree
environment.
Unify checks using `git rev-parse --is-inside-work-tree`.
Change-Id: I3f54afc99ad0f0e3052cffdd32bdd9649cf3d720
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
`genbuild_h.sh` checks whether it is running from a coreboot's own git
worktree to decide whether to use git as the time source. This check
fails when `${top}/.git` is a gitfile, e.g. when coreboot is a
submodule.
Add a proper `git rev-parse` call to check the condition, remove `$top`
which is not used anymore.
Change-Id: I8bb13d607a01f4f28fa8b165769e0a1f702da362
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some non-static declaration remains. If they were made
static, the compiler would output some warnings:
bincfg.y:30:1: warning: useless storage class specifier in empty declaration
};
^
bincfg.y:47:1: warning: useless storage class specifier in empty declaration
};
^
bincfg.y:22:12: warning: ‘yylex’ used but never defined
static int yylex (void);
^~~~~
bincfg.y:456:13: warning: ‘set_input_string’ used but never defined
static void set_input_string(char* in);
^~~~~~~~~~~~~~~~
Change-Id: I753e99c4a8290f9edd9abcda9af8e33b6ccfe406
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23243
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the code was moved from the Makefile.inc to a separate file in
commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script),`$(MAKE)`
was replaced by `remake`, introducing dependency on this tool which is
basically a `make` with debugging capabilities. Many developers don't
have `remake` installed, leading to pre-commit hooks being not executed
properly. Apparently this was an unintentional change.
Furthermore, special treatment of `make` tool via the `%MAKE%`
substitution performed during hooks' deployment is still desired. Use
case is calling `remake gitconfig` to set `remake` as the `make` tool in
the hooks. To accomplish this, add a parameter that is passed from the
Makefile.inc to gitconfig.sh.
Change-Id: Ia78e06567b904b342dc9b7778569201fe02e6897
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds a member device_index to r8168 chip information which
allows driver to identify which NIC card requests MAC address.
In this implementation, only 10 NIC cards are supported, the device
index is in the range of 0 to 10. Regarding to MAC address mapping,
when there is only one NIC on DUT, it is treated as a special case
mapping to "ethernet_mac" in VPD for backward compatibility. When
there are multiple NICs on DUT, they are mapping to "ethernet_macN"
where N is [0-9].
Device tree configuration:
For single NIC: .device_index = "0", maps to "ethernet_mac"
For multiple NICs: .device_index = "[1-10]", maps to
"ethernet_mac[device_index - 1]"
BUG=b:69950854
BRANCH=None
TEST=Added device_index = [0-10] under /drivers/net in device tree &&
Programmed the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
this enables the MRC recovery cache for zoombini & variants.
the Kconfig options are:
HAS_RECOVERY_MRC_CACHE
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
one note of caution: early board builds will likely fail to boot with:
tlcl_extend: response is 0
tlcl_extend: response is 0
tlcl_lock_nv_write: response is 0
tlcl_lock_nv_write: response is 28b
Failed to lock rec hash space(1f)
Saving nvdata
hard_reset() called!
the fix is to boot into recovery once, then it's business as usual.
using servo, this can be done with:
dut-control power_state:rec
BUG=b:71785303
BRANCH=chromeos-2016.05
TEST=boots on meowth...
Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23298
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this adds missing ACPI entries for the EC, CPU, and power button.
also, the EC to AP wakeup pin assignment is fixed.
BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth. /sys/class/power_supply now gets populated.
Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/23237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.
BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.
Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch removes IccMax settings from device tree since they
are handled in SoC code from patch e1a75d.
BUG=b:71369428
BRANCH=None
TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot
chromeos-bootimage" & ensure the IccMax settings passed
to FSP are from SoC code.
Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
With the tianocore payload on a Thinkpad X200 the filesize increased
by approximately 50% and the time to fetch and decompress the payload
increased by approximately %300 , so something is definitely wrong
with it and it shouldn't be used as the default compression method.
Change-Id: I9661c82750104d737596e7b3a8974324765938a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Turn on the load switch to the FP MCU at startup, so the kernel can
detect it and use it.
The load switch enable pin is connected to the GPP_A11 PCH pin (aka
PCH_FP_PWR_EN).
BRANCH=none
BUG=b:71986991
TEST=on Meowth, see the kernel detecting a cros_fp device at startup:
[ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected.
[ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure the FP MCU interface on GSPI1.
BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.
Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The `git sup-destroy` alias uses a subshell in order to make `git
submodule deinit` deinitialize all submodules. This isn't necessary as
the `--all` switch does the same.
Furthermore, `git submodule init && git submodule update` equals to `git
submodule --init`.
Change-Id: Ib690d66795da4049bb0bb350a0609cf2e6b5c4c4
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The variable t32 was originally used to do bitwise operations, but it is
not required anymore. Also, it was assigned twice accidentally, which
introduced a new Coverity Scan defect.
Found-by: Coverity (CID 1385126: (UNUSED_VALUE))
Change-Id: I77afd5064304a36991f63cf1328e13820144efb6
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This automatically generates an FMAP region for the MRC_CACHE driver
which is easier to handle than a cbfsfile.
Adds some spaces and more comments to Makefile.inc to improve
readability.
Tested on Thinkpad x200 with some proof of concept patches.
Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost. Add functions
to support read and write operations.
Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
A subsequent patch will use GetHeapBase() in more files than
heapmanager.c. Convert it to a format more similar to existing
coreboot source.
Change-Id: I8362af849fc9d7cb1b8a93113e8d78dcac51c20a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA
heap was moved completely into cbmem. This was a departure from the
"late cbmem init" method of adding it late in post, then storing the
S3 volatile data to the region. Remove the hardcoded base address
that was missed in that commit.
To prepare for S3 support, split the region into subregions for
heap, AGESA's S3 volatile storage, and an MTRR save area.
BUG=b:69614064
Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The default time for writing MRC data to flash is at the exit of
BS_DEV_ENUMERATE but this is too early for some implementations.
Add an option to Kconfig for allowing a late option to be selected.
The timing of the late option is at the entry of BS_OS_RESUME_CHECK.
TEST=Select option and inspect console log on Kahlee
BUG=b:69614064
Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22937
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ported from commit e6033ce1
soc/amd/common/block/pi: Fix AGESA heap deallocator
The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
Mainboards:
src/mainboard/a-trend/atc-6220
src/mainboard/a-trend/atc-6240
src/mainboard/abit/be6-ii_v2_0
src/mainboard/azza/pt-6ibd
src/mainboard/biostar/m6tba
src/mainboard/compaq/deskpro_en_sff_p600
src/mainboard/gigabyte/ga-6bxc
src/mainboard/gigabyte/ga-6bxe
src/mainboard/msi/ms6119
src/mainboard/msi/ms6147
src/mainboard/msi/ms6156
src/mainboard/nokia/ip530
src/mainboard/soyo/sy-6ba-plus-iii
src/mainboard/tyan/s1846
Change-Id: Id895963f9641bcaaa65e8a8cb21213a758a9ad80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23301
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i82810
Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000
Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for new memory stuffing options that will appear on
the P1 meowth boards.
new strap setting - associated SPD file
----------------------------------------
0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex
0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex
0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex
BUG=b:69011806
BRANCH=none
TEST=none
Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The `gitconfig.sh` script installs hooks to the according directories
(for coreboot and its submodules). It has the `hooks` directory
hard-coded to be `.git/hooks`, which makes the installation fail when
coreboot itself is a submodule because then `.git` becomes a gitfile.
Replace hard-coded path handling using the according `git rev-parse`
calls.
Change-Id: I778e20be24bb27d0081c9e1c12883117d6d50347
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The name blobtool is confusing as 'blob' is also used to
describe nonfree software in binary form.
Since this utility deals with binary configurations it
makes more sense to call it bincfg.
Change-Id: I3339274f1c42df4bb4a6b30b9538d91c3c03d7d0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/23239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Our current U22 skus (celeron and i3) actually don't support PL2,
but making sure that if we do decide in the future to use it to
make sure PL2 and PsysPl2 values are set appropriately.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42
and 65W with barrel jack for U22.
Change-Id: I084d0320128a6e05948023520a30c497c41be23b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PMC controller gets hidden during FSP Silicon initialization
using sideband interface on CNP-PCH. Hence unable to reserve
PMC IO resources during PCI enumeration process. This causes
hang issue on non-chrome platform with CNP-PCH due to ABASE
corruption.
This patch ensures PMC IO resource (ABASE) is getting reserved
(IO address 0x1800-0x1900) and ACPI base is not overwritten by
other devices.
TEST=ABASE range is reserved along with LPC IO range during PCI
enumeration.
PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0
flags c0000100 index 20
Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures common block has option to reserve IO resources
based on SOC requirements. Also add pch_lpc_ prefix to maintain
same function nomenclature across all intel common block.
Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to make VBOOT2 independent from the CHROMEOS
kconfig option a weak method for get_write_protect_state
and get_recovery_mode_switch() is required.
Introduce a kconfig option for controlling this
behaviour.
This is a temporary fix and will be removed afterwards.
Change-Id: I3b1555bd93e1605e04d5c3ea6a752eb1459e426e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix
Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Unified Host Event Programming Interface (UHEPI) enables a unified host
command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events.
Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E,
0x8F) is supported for backward compatibility. But newer version of
BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT)
The UHEPI also enables the active and lazy wake masks. Active wake mask
is the mask that is programmed in the LPC driver (i.e. the mask that is
actively used by LPC driver for waking the host during suspended state).
It is same as the current wake mask that is set by the smihandler on host
just before entering sleep state S3/S5. On the other hand, lazy wake masks
are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set
the active wake mask depending upon the type of sleep that the host has
entered. This allows the host BIOS to perform one-time programming of
the wake masks for each supported sleep type and then EC can take care
of appropriately setting the active mask when host enters a particular
sleep state.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix
1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix
2). suspend_stress_test with S3 and S0ix
3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm
wake sources (Lid, power buttton and Mode change)
4). Verified "mosys eventlog list" in S5 resume to confirm wake sources
(Power Button)
5). Verified above scenarios with combination of Old BIOS + New EC and
New BIOS + Old EC
Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The bash script `genrelnotes` checks for `.git` to be present to
determine whether the current directory is the top directory of a git
worktree. This check is rather weak and doesn't handle many edge cases
like that of a broken gitfile.
Add a proper `git rev-parse` call to check the condition.
Change-Id: I32b06ca982d55fd8e88e55651b6bc53014905823
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Right now the poppy baseboard camera topology allows to add maximum of 2
sensors. The sensors can be of different vendors. The current ASL code
structure doesn't allow sensor customization. Moving PMIC specific objects
from sensor objects to PMIC scope and having separate sensor ASL files will
help in unbinding the PMIC and sensor objects and allow some customizations.
BUG=None
BRANCH=None
TEST=Build and boot soraka, make sure both camera's are working fine
and also verify that the generated DSDT looks fine.
Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The variant boards can have a custom endpoints, splitting the ASL code
aids customizing the endpoints as per the variant board setup.
BUG=None
BRANCH=None
TEST=build boot soraka, verify that the cameras are working fine and
generated DSDT tables are same as before.
Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
BUG=b:71764350
TEST= Boot grunt.
BRANCH=none
Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
Removed boards:
amd/dinar
tyan/s2886
supermicro/h8scm
supermicro/h8qgi
Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch provides an option for non-chrome devices to make use of
FSP-T for performing cache-as-ram initialization. Majority of IOTG users
are using FSP-T for CAR implementation and aren't able to select FSP_CAR
Kconfig from SoC without conflicting with existing CAR config.
TEST=Ensure that both the Chrome platform and non Chrome OS platform
can select either CAR implementation based on Kconfig options
FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose
CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose
FSP_CAR by default.
Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs
to be programmed before it gets locked. Update lpc programming to add
decode programming on DMI side as well. Also enabled io port 0x200
decoding by default.
BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard
devicetree.cb, then read back IO port in depthcharge cli and check
that return is not zero.
Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i5000
Mainboards:
mainboard/supermicro/x7db8
mainboard/asus/dsbf
Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i855
Mainboards:
mainboard/lanner/em8510
Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/intel/sch
Mainboards:
mainboard/iwave/iWRainbowG6
Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/dmp/vortex86ex
Mainboards:
mainboard/dmp/vortex86ex
Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/amd/geode_gx2
northbridge/amd/gx2
southbridge/amd/cs5535
Mainboards:
mainboard/amd/rumba
mainboard/lippert/frontrunner
mainboard/wyse/s50
Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the option to use the lz4 compression method
to compress payloads.
Also sets LZ4 as the default compression method.
Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Primary to Sideband Bridge (P2SB) is the interface to Private Con-
figuration Registers (PCR) including GPIO configuration. Of course,
access is restricted to Intel partners and criminals, so the PCI device
is hidden from the OS. Probably we only need to fetch the SBREG_BAR
address and can hide the PCI device again after that.
Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GCC includes `sched.h` after poisoning calloc(). This results in a
build failure with Musl libc. We work around the issue by including
`sched.h` earlier and throw around some void pointers so we only
have to do it in one place.
Change-Id: I1d5462eb9a448147a95dd4ec50361b3f5a28910c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Looks like we were unnecessarily dragging this around for some time now.
GCC's installation manual doesn't mention libelf as a requirement and a
build of crossgcc-i386 doesn't show any sign of it being used.
This also fixes a lot issues on non-GNU distributions that were intro-
duced by switching to the elfutils version of libelf.
Change-Id: Iff308a9bed9ae3842557d251b75d1faadfafe0da
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the buildgcc script, there is a check that the tools required are
installed. When a tool is missing, a message is output suggesting an
installation method, e.g. `sudo apt-get install foo` on debian-based
systems.
When run on a true, vanilla debian system, the error message provides
only a generic hint because the `please_install()` function fails to
detect the OS kind. Detection is based on definition of `ID_LIKE` in
`/etc/os-release` yet such systems only define `ID` to `debian`.
This commit closes the detection gap. Tested on debian 9 (stretch).
Change-Id: I3c867837e9157bee13010bd0a005028c369ce55f
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some Dock events only need to happen based on the Dock Id (which
functions as a presence detect GPIO).
Inspired by vendor bios DSDT.
This fixes undock ACPI events being issued when pulling out the power
when docked or undocked (but still generates one when forcibly
undocked)
Tested on X200: pull power and see if undock events are generated in
dmesg.
Change-Id: I1eef971d49508bcd94d5d1cf2b70395b7cd80b1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the DRAM does *not* actually overlap the PCI space, the remap code
notices it is the case, but for some reason proceeds with the remapping,
attempting to remap a negatively sized chunk. Bummer.
With a single 1024M (two ranks of 512M) module:
Nothing to remap
Mem remapping enabled
Remapstart 5120(MB)
Remapend 6144(MB)
Top of RAM 1024MB
New top of RAM 2560MB
Wrote remap map a0101
Mem remapping enabled
Remapstart 4096(MB)
Remapend 2560(MB)
New top of memory is at 2560MB
Needless to say, subsequent ram_resource() ruins the memory map for the
OS -- Linux won't boot without a mem= argument and memtest quickly.
TEST=memtest and Linux boot on HP t5550 with 1024M of memory
Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
They both have a device id of 0x3c. The former is part of the PCI chip set
accessible via port 0x3f0 while the latter is a standalone LPC chip accessible
via 0x2e/0x4e depending on strapping.
They're not register compatible: the VT82C686 only provides a FDC, LPT and part
of UARTs.
The VT82C686 documentation suggests it has revision 0x00 while the VT1211
datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a
revision of 0x02. Thus the revision is probably not good enough to tell one
from the another.
Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The `secimage` utility uses OpenSSL to calculate HMAC, which it does in
a rather unorthodox way, using deprecated `HMAC_CTX_init` API and
repeated calling of `HMAC_Init_ex` without a clear reason. The former
causes build errors with OpenSSL 1.1 while the rest of the
`HmacSha256Hash` function is confusing and overly complex.
Make `HmacSha256Hash` use a single OpenSSL API call. Test passed:
resulting signed binary remains identical.
Change-Id: Ib23c0ad96f9d8cc30ad357de8c0b0ba967c7d724
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the variable `device` instead of `dev` in the predicate of
the if condition, as `dev` is not changed in the for loop.
The for loop was added in the following commit.
commit 8fed77ae4c
Author: Scott Duplichan <scott@notabs.org>
Date: Sat Jun 18 10:46:45 2011 -0500
ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Reviewed-on: http://review.coreboot.org/44
The assumption that the devices are ordered in the tree seem to
hold in this case (although it is not ensured) and therefore at
least with the ASRock E350M1 no (visible) change is experienced as
the children are all of type `DEVICE_PATH_PCI`.
Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.
* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner
Details are going to be published on the board's status page.
Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions. These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.
BUG=b:71867096
TEST=Build and boot grunt. Verify registers are set correctly.
Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.
Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.
BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.
Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt and Kahlee have different audio codecs.
Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.
Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.
BUG=b:69397774
TEST=Codec driver loads. Check dmesg.
Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot
boot messages from coreboot over the integrated RS-232 port (requires
use of included dongle).
Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The code is based on autoport and that for 8470p.
Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Soldered RAM 4GiB from Hynix (There may be more models here)
- Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from
SeaBIOS, or Linux payload (Heads)
Not work:
- An "NFC" device connected to LPC
Not implemented yet:
- Detecting the model of Soldered RAM at runtime, and loading
the corresponding SPD datum (3 observed) from CBFS
Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeron/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R/Y since device tree could not handle all
KBL-U/R combinations when multiple SKUs are adopted in a project.
Besides, it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.
+----------------+-------------+---------------+------+-----+
| Domain/Setting | SA | IA | GTUS | GTS |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A |
| | 4.5A(Others)| 29A(Celeron) | | |
| | | 32A(i3/i5) | | |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A |
+----------------+-------------+---------------+------+-----+
BUG=b:71369428
BRANCH=None
TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot
chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron
SKUs are identified correctly and IccMax settings are passed
to FSPS correctly.
Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The EC does enable bluetooth on wifi cards and BDC at the same time.
Check the new Kconfig to support bluetooth on wifi in case no BDC
is installed and the BDC detection fails.
Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Digitizer power is not controlled by SoC. Also, since the digitizer
uses I2C-HID driver in Linux kernel, the device is put into sleep
anytime system is suspended. Thus, there is no need to control the
reset gpio using ACPI power resource.
TEST=Verified that digitizer device is properly detected on boot-up
and after suspend/resume.
Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of duplicating code in each mainboard that supports HDA use
the common driver and provide the HDA verb table.
This was compile tested for both variants with "abuild -t intel/kblrvp"
Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is common HDA code in soc/intel/common that provides generic
HDA support functions, but it does not provide a driver.
This change adds a common block driver for HDA that provides a
ramstage driver for SOCs that need to initialize an HDA codec.
This was tested on a board with an HDA codec to ensure that it
properly detected it and ran the codec init steps.
Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable. After MTRR
setup, reenable the setting for the duration of POST.
TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683
Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The heap allocator would try to split a buffer node that
was too small for another node. In the failing case, the buffer
node was 0x140 bytes and the requested size was 0x133 bytes.
The logic would check that there was room for the header and
buffer and try to split the buffer node. The buffer node header
is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't
leave room for another node header and a little space for a buffer.
BUG=b:71764350
TEST= Boot grunt.
BRANCH=none
Change-Id: Iece5e12d5787415a335bb953985331a5dc312152
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine. Update this so the port works.
Also change disabled port to PcieUnusedEngine.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After running `lint-stable` in the pre-commit hook, its result is
ignored. This behavior was introduced in commit b18f522b
(lint/gitconfig: Enable checkpatch.pl checking of commits) and it
doesn't seem intentional. This issue was also mentioned in the revert
discussion (https://review.coreboot.org/c/coreboot/+/17440).
Enable `errexit` mode of the shell so that the hook fails when an error
occurs in any of the tests. Also, enable `nounset` mode to catch typos
easier.
Change-Id: I749963167660ea6a1a04d40a14ad1113e82f0f86
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If using type-C charger, then PsysPl2 may be lower than barrel jack
value of 90W, so need to override value to the max power of type-C
charger.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W
when using proper barrel jack adapter on and i7.
Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION
and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data
validity. With current implementation in S3 resume path, if mrc cache
data is invalid, the bootmode is not updated further and remains set
at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get
incorrect boot mode context and reinitialize memory in S3 resume
path. In correct flow fspm should have correct bootmode context
i.e. S3 resume and return error in case mrc cache data is invalid
or not found.
BUG=b:70973961
BRANCH=None
TEST=Verify correct bootmode is set on S3 resume, even when
mrc cache data is invalid.
Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/23156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In S3 resume, for cases if valid mrc cache data is not found or
RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer
would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION.
This gets memory to be retrained in S3 flow. Data context including
that of imdr root pointer would be lost, invoking a hard reset in
romstage post memory init. Issuing hard reset before memory init,
saves fsp memory initialization and training overhead.
BUG=b:70973961
BRANCH=None
TEST=Verify S3 resume flows on soraka.
Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The spd.bin file was not getting generated properly, so moved logic
to variant's makefile.
BUG=b:64395641
BRANCH=none
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully and spd.bin is found when booting.
Change-Id: I4642d6ddb5e65f721d1bde31ca0ca5b4438da554
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch fixes 2 edp display issues:
1. When rk_edp_prepare fails >3 times, edp_init isn't run because
while-condition is not satisfied. Then, only a partial init sequence is
ran. This causes all aux transactions to fail.
2. If rk_edp_prepare never succeeds, coreboot never leaves link training
stage due to infinite loop. Boot process is stuck.
TEST=Boot past eDP initialization stage and make sure AP logs don't have
show aux transaction fails.
Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/23152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
License header for the `gitconfig.sh` was copied from the Makefile it
was extracted from in commit 9ab8ae6a (util/gitconfig: Make gitconfig
a bash script).
License header for the pre-commit hook names Patrick Georgi as the
copyright holder as he is the original author.
Change-Id: Ie051e5e6ae7571050ece383e6be8236ed7d1ddd9
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The .spd.hex text is added to the name by the build process. This
was causing a failure because we were trying to add the files:
'file.spd.hex.spd.hex' to the build.
Remove the additional .spd.hex text.
BUG=b:71535311
TEST=Build
Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure
that required SPD hex files are included in the SPD binary.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Rainier, a scarlet derived board, was configured to use spi0 for tpm
driver by default. This patch switches it to spi2 to reflect recent
changes in scarlet-derived boards.
Change-Id: Ib67109786512c068bb957890f456bccff7addc86
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/23129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into
pre- and post-memory binaries when it is built. Building AGESA this way
is required when doing the new "load post-memory AGESA binary into ram"
feature.
Thus, condition this new path on the CONFIG option being enabled.
BUG=b:71641792
TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled
Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23141
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.
BUG=b:69613465
TEST=Build and run kahlee.
Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds the temperature sensor type device tree setting,
configured to be the default value as stated in the Fintek f71869ad
datasheet on page 60.
bit 7-4: reserved (0)
bit 3: T3_MODE 1 (default) = BJT, 0 = thermistor
bit 2: T2_MODE 1 (default) = BJT, 0 = thermistor
bit 1: T1_MODE 1 (default) = BJT, 0 = thermistor
bit 0: reserved (0)
This results in a default value of 0x0E
This change is needed to make sure behaviour does not change after
applying change 22935 which adds the temperature sensor type
devicetree configuration option
Change-Id: I42980988267621def6576f771f1d8a853500e867
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/22966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch makes it possible to set the "Temperature Sensor Type Register"
at index 6Bh from the devicetree, allowing the use of thermistors instead of
BJT type sensors.
Register documentation (from page 60 of the F71869 datasheet):
6.6.25 Temperature Sensor Type Register - Index 6Bh
Bit 7-4: reserved
Bit 3: T3_MODE (0: thermistor, 1: BJT [default])
Bit 2: T2_MODE (0: thermistor, 1: BJT [default])
Bit 1: T1_MODE (0: thermistor, 1: BJT [default])
Bit 0: reserved
Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/22935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Qemu q35 target doesn't support or needs Intel Firmware blobs so
it doesn't make sense to select that option on this hardware.
The result of this change will be that when changing the ROM chip
size, CBFS_SIZE will automatically fill the whole flash which is
desirable in this case.
Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23090
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Grunt's devicetree dropped some entries when it was split from the
kahlee variant. This commit restores:
spd_addr_lookup - memory information for AGESA
dram_clear_on_reset - keeps DRAM contents on reset
uma_mode - needed for vbios
uma_size - needed for vbios
Change-Id: I1d8cdc97594867f1d706318370055087976a5104
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
PMC and GPIO DWx definition is not identical, hence update that to
correct information. For cannonlake lp PCH, GPIO group C, group E and
group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add
function call to set up GPE routing in bootblock stage.
TEST=Boot up into OS, and manually check PMC GPE status
Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that the AGESA binary is split into two sections load the
post-memory AGESA binary into ram. It needs to be an rmdoule
so that it can be relocated into ram.
agesawrapper_amdinitenv() entry
CBFS: 'VBOOT' located CBFS at [10000:cfd40)
CBFS: Locating 'AGESA_POST_MEM'
CBFS: Found @ offset 875c0 size 11c5e
Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes)
Loading module at c7580000 with entry c7580000. filesize: 0x2bafc
memsize: 0x2bb0d
Processing 1112 relocs. Offset value of 0xc7780000
AGESA call 00020001 using c75818fe
AGESA call 00020003 using c75818fe
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
BUG=b:68141063,b:70714803
TEST=Booted kahlee.
Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
On debian systems, /bin/sh is `dash` which has built-in `echo` always
interpreting escape sequences such as '\n'. The pre-commit hook uses
the built-in for piping diff to checkpatch, interpreting the diff's
escape sequences in the process and leading to false negatives
and preventing commits despite conformance.
Use `printf` instead of `echo` when handling diff content. The bug was
introduced in commit ef869305 (util/gitconfig: update pre-commit
script).
Change-Id: I37edfe7b32721cb63d99299563cb11f26082c9a9
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Files agesawrapper.c and heapmanager.c have several non-conformity with
coreboot standards, including lines longer than 80 characters, use of
"} else {" after a return and wrong comment block formatting. Fix all
such issues, so that it passes commit tests.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just file
formatting).
Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The spd size of DDR4 is 512, but the size empty.spd.hex is 256.
With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data
loads spd data incorrectly due to the offset is wrong.
Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change is to enable SataPwrOptEnable.
With this change, we no longer see SError message in kernel during
suspend_stress_test.
BUG=b:70491485
Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides option in devicetree and feeds the option to
FSP SataPwrOptEnable UPD for power saving purpose
BUG=b:70491485
Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The cmos.layout files are copied from lenovo/x230 with EC options
removed.
It's tested on 8470p and the power_on_after_fail option works.
Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/22842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Don't allow the user to select this manually, since it doesn't build
on platforms that don't use it.
Don't set the bool value so that it doesn't show as not selected in
the .config file of platforms that don't use this.
Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Even though kaby lake and cannon lake are using the same GSPI
controller, bit meanings (for polarity and state) in SPI_CS_CONTROL
register are significantly different. This change provides a new
Kconfig option that can be selected by SoCs using these new bit
definitions of SPI_CS_CONTROL. Common code takes care of setting the
right value for polarity and state field depending upon the version
selected by SoC.
BUG=b:70628116
Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In commit 7a95204 (intel/dcp847ske: Add Intel NUC DCP847SKE)
the default_irq_route.asl file was removed, but this mainboard
was missed. Follow suit with the original intent of the commit
and fix the build breakage.
Change-Id: I909dad7cfc0fab37e29187b2358f7f056216a403
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22975
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Issue first reported at commit 1587dc8a2b, the call of functions
setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev()
to soc_init(). The function setup_uma_memory() no longer exists, its
functionality transfered to agesawrapper_amdinitpost.
Move setup_bsp_ramtop() as required.
BUG=b:62240756
TEST=Build and boot kahlee.
Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
If HECI gets times out when waiting for read slots, there's no need to
read back reply message to decide if the HECI recieve successed or not.
Otherwise, system will stuck after global reset required.
BUG=b:707290799
TEST=Boot up meowth board without battery, and confirm hard reset got
trigged after heci time out.
Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Falling through is intended here, so add a comment that GCC will notice
and stop warning about this.
Change-Id: I12637b6bc18844a3bc47f06208df7fee7a4feb3b
Found-by: gcc-7 (Debian 7-20170316-1) 7.0.1 20170316 (experimental) [trunk revision 246203]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Omar Pakker
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE
Created using autoport and manual edits.
mainboard_fill_pei_data copied and adjusted from samsung/lumpy.
Tested:
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V).
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V).
- SeaBIOS stable payload.
- Linux 4.13.14 payload.
- Booting into Linux 4.13.14 with Debian/unstable installed on the
internal mSATA slot.
- Non-native raminit (works).
- Native raminit
- KVR1333D3S9 doesn't work.
- KVR16LS11 only works at 1.5V.
- Native VGA init, HDMI port detection with libgfxinit.
- Basic ACPI functions (power button event; power-off; reboot).
- Suspend to RAM and resume works.
- PCIe WLAN in half-minicard slot.
- USB device in half-minicard slot.
- PCIe device in full-minicard slot.
- mSATA device in full-minicard slot.
- Fan spins up/down in response to CPU load.
Known issues:
- Native raminit fails timC calibration with the RAM I have.
- Technical Product Specification mentions overcurrent protection
for back panel and front panel USB connectors, but I haven't
been able to trigger it with either native fw or coreboot
(tried up to 2.5A load).
Untested:
- USB debug port.
Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch revises LED0 Green light behavior from patch 2ecf3f8c.
For 100Mb link speed, LED0 should be OFF.
BUG=b:65437780, b:68284778, b:69950854, b:65808944
BRANCH=None
TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe
LED0 is behaving as expected.
Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22964
Reviewed-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.
BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka
Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.
CQ-DEPEND=CL:*520658,CL:*520659
BUG=b:
BRANCH=None
TEST= Build and boot soraka
Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/22692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
firmware test team is requesting that default gbb flags set to 0x39
rather than 0x239 so that it's consistent with the default gbb flags
of other platforms.
BUG=b:70392534
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage
gbb_utility --get --flags image-fizz.bin and make sure
that it returns 0x39 instead of 0x239
Change-Id: Ib73e4619b13f6b7c2d01598c926fbbd7d7eb9bef
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22962
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
apu4 is new version of PC Engines platform, which contains 4 Ethernet
ports and 4GB of RAM. In functional way it is very similar to apu3.
Platform tested with booting Linux voyage (kernel 3.16.7) using USB and
SeaBIOS as 1st stage and GRUB as 2nd stage bootloader. Also Debian
(kernel 4.8.5) using iPXE.
Change-Id: Ia7a9971d25d4ecc215c392be1e46dc1c10129ba7
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22629
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
PMC config register need to program to define which state system
should be after reapplied power from G3 state.
0 = System will return to S0 state
1 = System will return to S5 state
2 = System will return to previous state before failure
Refer to EDS for detailed programming sequence.
Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22838
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In commit 7f5efd90e (intel/bd82x6x: Use generated ACPI PIRQ)
the default_irq_route.asl file was removed, but this mainboard
was missed. Follow suit with the original intent of the commit
and fix the build breakage.
Change-Id: Iac233b802239e4e5cfc66d9545bb637ec4f9f541
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22958
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds
mainboard espi handler function.
TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled.
Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the SMI bits for SMI_EN, SMI_STS and GPE
register in pm.h. The southbridge handler for espi smi is
also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is
bit 20 in GPE register and enables the setting of the
ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI.
TEST= Boot to OS.
Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot console output during POST shows that the EC
replay fails to communicate with the EC. Since the replay
has no effect, it should be removed from the boot process.
coreboot log:
Replaying EC dump
.......Timeout while sending command 0x81 to EC!
.......Timeout while sending data 0x00 to EC!
(snip)
.......Timeout while sending command 0x81 to EC!
.......Timeout while sending data 0xff to EC!
.......Timeout while sending data 0xff to EC!
done
Change-Id: I05fb6358b40f442337f5768afa6253cd9bc32ee1
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Fizz is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:65499724
BRANCH=None
TEST=Build and boot Fizz
Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Intel version of ThinkPad X131e can ship with Sandy Bridge or
Ivy Bridge processors. The mainboard uses 8MiB+4MiB flash chips, with
the 8MiB chip containing the IFD and ME, and the 4MiB chip containing
the BIOS. The flash chips can be accessed with an external programmer.
This port was primarily created using autoport, with some parts adapted
from lenovo/x230 and google/stout.
Tested and working:
- Machine type 3367AH5 / Intel Celeron 887 (Sandy Bridge)
- Boots Debian GNU/Linux 9.2 (Linux 4.9.51) via SeaBIOS
- Boot from internal SATA and USB
- Native RAM init
- Native VGA init
- libgfxinit
- VGA and HDMI display output
- Keyboard, trackpoint, touchpad
- Audio (speaker, headphones)
- Ethernet (Realtek)
- Display backlight
- USB 3.0 ports
- "Always on" USB port (EHCI debug)
- SD card reader
- Webcam
- Fan and temperature sensors
- ACPI S3 (Sleep)
- CMOS
- TPM
Not tested:
- WLAN/Bluetooth (Broadcom)
- WWAN/mSATA (no card)
- Other operating systems
Not working or not implemented:
- Fn keys
- ACPI S4 (Hibernation) "Image mismatch: memory size"
Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/20694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
While the older boards use a GPIO that has no state, the newer boards'
PMH7 does have a state, that even remains after reboot.
Don't assume default values in PMH7 and instead always program it.
Fixes dGPU doesn't show up when switching from integrated to discrete
GPU. The workaround of removing all power is no longer necessary.
Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It seems that RAM code 0 has been strapped with an incorrect resistor on
Kevin. The resulting voltage divide still puts it well within the ADC
value bucket reserved for that slot, but a little closer to the edge
than necessary. While this doesn't seem to cause any immediate problems
on its own, it still doesn't hurt to fix it (if only for the
documentation value).
On other boards (at least on my Scarlet) the strapping seems to be
correct.
Change-Id: Ic5199834fbeaf734e725ff45b04f45eefe149855
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22891
Reviewed-by: David Schneider <dnschneid@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Cannonlake FSP will send debug message on selected UART port, use same
coreboot UART debug port to FSP.
TEST=Boot up with board have UART port 0 and can see the print of FSP
Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After the PSP receives the MboxBiosCmdBootDone, it will no longer honor
any command where the command-response buffer exists outside of SMM
memory. Add the command and automatically execute it before booting
the payload.
BUG=b:69971683
TEST=Boot Kahlee and observe console log
Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the frequent setting/restoring of the PSP's bus-mastering and
memory decoding settings. It is up to the caller to ensure it is
already set properly.
Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A subsequent patch to the PSP library will rely on the device already
having its PCI command register set to allow memory decoding and
mastering enabled.
Program the command register ahead of loading the SMU FW1 blob in
bootblock. When the device has not been set up (e.g. when SMU FW
is not selectable), AGESA sets up the device. As a result, a
similar change is not required before sending the DRAM ready
command.
Change-Id: Id586106751286c4767b5c16ed7e1604523635492
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all SMM save state sizes equate to having enough stack in the
permanent SMM handler. Therefore, ensure 1KiB of stack is available for
each cpu's stack. Intel's save state size is 1KiB, but AMD's save state
size is only 512. Therefore, decouple save state size from the per
cpu stack size.
BUG=b:70027919
Change-Id: I54b9e6f3cc0ad6ca3d7b60b2b422b5dc5a78a552
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too.
Tested on lenovo/x230. Since both the bit that was masked wrongly and the
one that wasn't masked, but sould have been, are 0, the behaviour on
lenovo/x230 doesn't change.
Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/22596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This resolves the IASL remark:
dsdt.aml 2141: Method (\ISTR, 2, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/21668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The initial lookup for cbfs location for xip stages is implicitly
using the ELF size assuming it's relatively equivalent. However,
if the ELF that is being converted contains debug information or
other metadata then the location lookup can fail because the ELF is
considerably bigger than the real footprint.
BUG=b:70801221
Change-Id: I47024dcd8205a09885d3a3f76e255eb5e3c55d9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22936
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This platform shares most hardware components with first-gen Core
Lenovo laptops such as T60/X60, with much smaller EEPROM size as
one of notable differences. The port features Intel graphics,
ATI-based version should work with vendor VBIOS.
Tested peripherals:
- sleep/resume,
- USB ports,
- ACPI Fn key bindings/volume buttons,
- backlight control,
- ethernet,
- wireless (under Linux),
- sound/beep,
- dock handling,
- serial via dock.
Untested peripherals:
- IrDA,
- parallel port,
- PCMCIA,
- S-Video port,
- modem,
- FP reader (should just work),
- IEEE1394.
Linux 3.16 works with native gfxinit perfectly, with Intel VBIOS
console sometimes displays nothing when i915 framebuffer is used.
Windows 7 has an interrupt assignment issue with iw3945, otherwise
tested stuff is fine.
Change-Id: I84c89cc47d3db126d827f92d50270954bc42f224
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/21019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In commit decd0628 (drivers/mrc_cache: move mrc_cache support to
drivers) mrc.cache is always added, but CONFIG_MRC_SETTINGS_CACHE_SIZE
is not used in Sandy Bridge, which makes mrc.cache have zero size and
the machine will fail to boot after the first boot.
Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/22925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Procedure write_pci_int_table() does not validates intr_data_ptr. It must
be validated together with picr_data_ptr and idx_name.
BUG=b:69868534
TEST=Build fake kahlee with intr_data_ptr not initialized, boot and see
error message. Than build correct kahlee and verify that error message
is gone.
Change-Id: I5ee9a362600dbd6325254d7431172501181b52b0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
In function load_smu_fw1(), variable base receives one value and is
immediately overwritten. Remove the first line, as it's useless.
This fixes CID 1383612
BUG=b:70620140
TEST=Build kahlee and boot.
Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add initial files to support the Saddle Brook board. This board uses the
Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file.
Most of the code has been taken carried over from kunimitsu with changes
done for Saddle Brook.
Saddle Brook is a reference board for Skylake SOC and has DDR4.
TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully.
Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e
Signed-off-by: Anuj Mittal <anujx.mittal@intel.com>
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/21436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO
configuration for DEVSLP to match the latest version of schematics.
BUG=b:70160119
Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables customized NIC leds as below:
Green Orange (Amber)
100M off blinking
1000M on blinking
BUG=b:69950854
TEST=Boot on fizz dut and observe the LEDs are behaving as expected.
Perform suspend/resume test and the LEDs are still working as expected.
Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make a static function that can report the AmdInitPost() results. This
makes it easier to keep lines within 80 columns. Clean up surrounding
source.
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I6d288e76e7510528659436e61fdfa1d5db01f06c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should
it make any assumptions about the capabilities of a particular device.
Move these into stoneyridge northbridge and southbridge files.
BUG=b:70670425
TEST=Build and run Kahlee
Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There isn't a good reason to keep the checks for __PRE_RAM__. The global
variables are not used outside of ramstage and the linker removes them
cleanly in other stages.
BUG=b:70671590
TEST=Build and boot Kahlee
Change-Id: I7a35141f212f340c157d57fde8daf93c0c383af8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean up the source for agesawrapper_amdreadeventlog:
* shorten the name to help keep lines within 80 columns
* convert initializers to C99
* break the call from the callers' if() statements
* streamline the printk formatting
BUG=b:70671442
TEST=Build and run Kahlee, check console log
Change-Id: I402c75e4d65a592b9d1557c5852df03e48e206b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Seeing some instances were cr50 spi driver is starting a new
transaction without getting a ready interrupt from cr50, which means
that there are pending interrupts. Clearing these to be sure there
are not any stale irqs for the next transaction.
BUG=b:69567837
BRANCH=None
TEST=run FAFT and see if any 0x2b recovery boots occur
Change-Id: Ie099da9f2b3c4da417648ae10a5ba356b7a093ff
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.
BUG=b:69614064
Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A non-user configurable option that defaults to y should just be
auto-selected instead of instantiating an instance of an option.
BUG=b:69614064
Change-Id: I55cf28eaf0233182d4fa488cf4b31e8ad379b6c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The CPU_SPECIFIC_OPTIONS already auto-selects the option. There's
no point in having a selectable option that is already selected.
There's already an option to select it within intel/common.
BUG=b:69614064
Change-Id: I0c7ce7d3f344668587a75ec683343559a4caea99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is mostly written from scratch and uses common spd ddr2 decode
functions.
This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;
* Fixes tRFC computation; tRFC == 78 is a valid timing which is
excluded and 0 ends up being used; (TESTED)
* Timings selection does not use loops;
* Removes ddr3 spd decode and is re-added in follow-up patches using
common ddr3 spd functions;
* Raminit would bail out if a dimm was unsupported, now in some cases it
just marks the dimm slot as empty;
* It dramatically reduces stack usage since it does not allocate 4
times 256 bytes to store full SPDs, amongs other unused things that
were stored in sysinfo;
* Reports when no dimms are present;
* Uses i2c block read to read SPD which is about 5 times faster than
bytewise read, with a fallback to smbus mode in case of failure,
which does seem to happen when the system is forcefully powered
off.
Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There's no sense in having the nvm abstraction in its own files. Put
that support directly into mrc_cache.c.
BUG=b:69614064
Change-Id: I0f1a801c6e1a8c35f70faf9e4318bdc45955047a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Implement the spi controller flash_protect() callback. No need to
have a global spi_flash_protect() once implemented.
BUG=b:69614064
Change-Id: I83f4310d8f78ba64727ba75eb75708d0cbaa7d53
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the fast spi support implement the callback for flash_protect().
This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT
Kconfig option as well spi_flash_get_fpr_info() and separate
spi_flash.[ch].
BUG=b:69614064
Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Now that there is spi flash controller flash protection use that API
so the spi_flash_protect() API can be sunsetted since it was isolated
within the Intel code base.
BUG=b:69614064
Change-Id: I3908d0e3105b0ef9a0fbf4fc9426ac1be067f648
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide a spi controller specific protection callback to take
advantage of special spi flash controllers that have internal
protection registers built into the implementation. It's an
optional callback for spi controllers.
BUG=b:69614064
Change-Id: Ie50a6ce3bbda32620a25dd26fda1af944940bf28
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The gitconfig target has a few bashisms and would fail
silently on systems that use a POSIX standard sh (like Ubuntu dash).
Remove the code from the makefile and put it in a bash script that
is called by the gitconfig target.
Change-Id: I3bc8cf688a3ad211b57c8ca0e6b1e86c82dc6a37
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Melfas kernel TS driver (melfas_mip4.c) will look up "ce"
GPIO during driver probe in ACPI _DSD.
But FW does not report "ce-gpios" but "enable-gpios" in _DSD.
Kernel will obtain GPIO from _CRS by index "0" without ID.
Melfas driver does not have separate condition
for MIT-410 so driver will set TS IC power off in probe.
FW now may need to add back "reset" pin in order to hack
this condition to let Melfas driver get "useless" GPIO
so TS IC power (VTSP) will be not off during driver probe by itself.
BUG=b:70149336
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Solve issues related to agesawrapper_call.h that came up at review
75dd50e233 (review 19724). This includes a hard coded table size and
2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER().
Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with
the actual content of the macro.
BUG=b:62240989
TEST=Build kahlee with no errors, boot recording serial output and compare
to serial output from a build without these changes.
Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add parameters to configure the integrated LAN via FSP. Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.
This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.
Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22856
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the flashconsole driver in verstage so it can be used
with VBOOT enabled. This was tested on a VBOOT enabled system
using flashconsole to store the boot log.
Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The opregion and fields are left over from when ACPI ASL code was
reading registers to determine the current setup. Now that the
ACPI device is generated with the correct information already this
code is not used at all and can be removed from the tree.
Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22854
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the
SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on
SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore,
remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency
for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG.
BUG=b:70232394
Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22874
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Cannonlake rvp serial log has been regressed with commit
I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake:
Clean up UART code) because of common UART code is unable to
link all __weak function implementation from SoC uart.c due
to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI
device resource programming is different than what it's been programmed
before.
This patch ensures UART2 PCI device resource enumeration is
working and we are getting serial log as expected.
Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The overcurrent pins on kahlee weren't mapped correctly, causing
the USB-A port to stop working.
None of the EHCI only ports are used for external connectors, so all
of the overcurrent pins should go to the XHCI connections. This is
also true of the Grunt board.
On Grunt, this also means that we don't need OC3, as it doesn't map
to anything in the XHCI controller, as it's coming from an internal
hub.
BUG=b:70636233
TEST=Build & boot Kahlee, verify USB-A port is working again.
Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array
irq_association[], and change the print string in soc/amd/common/amd_pci_util.c
that use the names from "%s" to "%-20s". This sets a fixed field of 20
characters for the string name, allowing for variable length to the names
(up to 20 characters), thus saving memory space used by the strings.
BUG=b:70344551
TEST=Build and boot, record output of irq routing and verify alignment.
Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.
BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
noted each instance in Chrome OS build was relocated.
Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Currently, "tcc_offset" defined in devicetree is overwritten by
Intel FSP-S UPD "TccActivationOffset".
This patch will make "TccActivationOffset" refer to "tcc_offset".
TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset"
by iotools (rdmsr 0 0x1a2).
Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/22818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Intel common PCI driver is handle PCI subsystem ID
programming, hence no need to have an explicit soc
function to do the same.
TEST=PCI subsystem id is getting programming during
pci enumeration.
Change-Id: I3eb362ff1f3f6d5c81a0dbe854d8ecd59d5a0453
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Intel common PCI driver is handle PCI subsystem ID
programming, hence no need to have an explicit soc
function to do the same.
TEST=PCI subsystem id is getting programming during
pci enumeration.
Change-Id: Iead57a286b26d532e578cfff99f412c23fd4c2fe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to the PCH BIOS Spec (Doc#549921/Rev-2.3.4),
section 2.5.1.6, it is a requirement to program the same
value programmed in LPC "PCI offset 82h" into "PCR[DMI]+2774h"
to fully enable the Lpc IO enable decoding which is missing in
current source.
Without above changes, Skylake Saddlebrook platform with a
SIO does not boot.
Change-Id: Ief26e2718325b9d74ea0f83d47d2f917e0972173
Signed-off-by: praveen <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/22819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move AGESA related source files in soc/amd/common under block directory.
Folder soc/amd/common/block subfolders should mimic soc/intel/common/block
subfolders (one subfolder per subject).
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This fixes some bitwise logic errors that caused the coarse offset not
to be programmed.
This fixes a regression introduced by 6d7a8c
"nb/intel/x4x/raminit: Rework receive enable calibration"
where the coarse offset doesn't get programmed anymore.
TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable
delays are close but above and below the edge of a coarse delay setting.
Change-Id: I41869815f782a2ea1178bdea006e3a7587441323
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change provides implementation of variant_memory_params for
nami. Since it uses DDR4 memory, DQ-DQS mapping table is not
required. Also, Rcomp resistor values are provided based on SDP v/s
DDP memory.
BUG=b:70188937
Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates scl_lcnt value for I2C5 to bring the bus frequency
closer to 400kHz.
BUG=b:65062416
TEST=Verified that I2C5 frequency is between 389-396kHz.
Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Due to a schematic error, our code was written to configure more I2S0
pins than are actually used. We're also pinmuxing the whole bank of pins
over to the I2S controller even though we don't need them all. Restrict
the GPIO initialization and pinmuxing to the pins we really need so the
other ones can be correctly used as SKU ID pins on Scarlet.
Also, move the "audio" IO voltage domain selection to the other such
selections in the bootblock, since that covers two whole banks of GPIOs
and there's no guarantee that they're all used for audio (and thus not
needed before ramstage).
BUG=b:69373077
TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.
Change-Id: I9314617e725fe83d254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Adds Maxim98357a support for Nautilus using the generic driver
in drivers/generic/max98357
BUG=b:68686020
TEST=With entire merged audio should be enabled on max98357
speaker codec.
Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Nautilus board uses max989357a speaker codec and 4CH DMIC.
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on Speaker and captures on 4CH DMIC
Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add documentation for Intel native raminit on Intel SandyBridge.
Documented so far:
* Register
* Read training
* Frequency selection
* SMBIOS type 17 memory reporting
* Various Kconfig options and features
Change-Id: I3b977460ecb29c9a54e3fab82349982fca9918e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The default implementation uses inb/outb, that is not available on ARM
platforms and others. A dummy implementation allows building nvramtool
on these platforms.
Change-Id: I75e4a1a0cbd35ca40f7b108658686839ccf9784a
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/22562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Corrects MBSC/MBFS programming when initializing DRAM on boards with both
3 and 4 DIMM slots.
Reformats comments to current coreboot standards.
Drops some romcc "optimizations" no longer necessary.
Boot tested on asus/p2b-ls, where it fixes a memory related hang after
SeaBIOS resets the board with nothing to boot from.
Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Due to review 20b8c821e4 being abandoned and review 376dc82dca being
merged, file amd_pci_int_types.h became orphaned (not included by any
file), while an array similar to intr_types[] (but that also includes
the associated register index) was created in southbridge.c replacing
the original array functionality.
Remove the header amd_pci_int_types.h from the repository.
BUG=b:70328428
TEST=Build kahlee with no errors.
Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the original Chromium source, PcdMemorySpdPtr is only set for
cyan, but none of the other Braswell variants. When upstreamed,
it was left set for all boards as it didn't appear to be problematic.
In wider testing, I came across one reks board for which it caused
FSP memory init to fail, so restricting the parameter to cyan only
as it was originally.
TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,
observe board now successfully boots where it did not previously.
Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22782
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 3b80572:
2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data)
to commit id f6780a3:
2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge)
This brings in 19 new commits.
Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22777
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The touchscreen interrupt was moved from the GPIO 3, as originally
suggested to GPIO 11. This changes the gevent from 2 to 18.
- Add EMMC reset on GPIO 93.
- Add EMMC bridge PCIe reset on GPIO 40.
- Set device enables to high.
- Remove extra SCI comment from GPIO 130.
- Set individual device PCIe reset pins to high.
- Enable global PCIe reset on GPIO 26.
- Mark LPC_CLK1 as unused.
- Update net names based on latest schematics.
- Set Direction and level/edge correctly for SCIs/SMIs.
- Remove SCI for pen detect.
- Add comments.
BUG=b:70234300, b:69681660, b:69305596
TEST=build grunt
Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h
BUG=b:70255003
TEST=Build and boot Kahlee. Build Grunt.
Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch makes coreboot set the max current and voltage for barrel jack
adapters.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max current and
voltage are set as expected.
Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
overrides the max input current and voltage when a barrel jack
adapter supplies power.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max
current and voltage are set as expected.
Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes
EC clear AP_OFF flag then hibernate.
This is needed to make Chromebox boot when cr50 toggles the EC's reset
line after TURN_UPDATE_ON command.
BUG=b:69721737
BRANCH=none
CQ-DEPEND=CL:802632
TEST=Verify Fizz reboot after cr50 update.
Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds '-p' to the 'add' command. It allows the add
command to specify the size of the padding added with the file
being added. This is useful to reserve an extra space in case
the file is too big to be relocated.
BUG=b:68660966
BRANCH=none
TEST=emerge-fizz coreboot &&
cbfstool image.bin add -n ecrw -f EC_RW.bin -p 0x10 ...
Verify image.bin has extra space in the file header.
Change-Id: I64bc54fd10a453b4da467bc69d9590e61b0f7ead
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As noted on linux-pci, we have a weird way to handling "value" and
"scale" fields that are supposed to contain numerical values: we encode
them as a bitfield.
Instead define the two fields (offset and mask) and use numbers.
Another issue, not fixed in this CL, is that we write hard-coded values
while these fields really need to contain the max() of acceptable delays
of the downstream devices. That way the controller can decide whether or
not to enter a deeper power management state. It's noted as a TODO.
Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-on: https://review.coreboot.org/22740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings
for nasher to save the power consumption when the system in S0ix.
Change as below:
AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0.
AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0.
BUG=b:69025557
BRANCH=master
TEST=compile/verify the power consumption change from ~150mW to ~100mW
on clamshell SKU and from ~200mW to ~100mW for convertible SKU.
Change-Id: I9e0674f206426fddb3947273754774b310106334
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch ensures that all required information for pch/mch/igd
deviceid and revision are available in single stage and makes
use of local references.
TEST=Build and boot cannonlake_rvp to get PCH information as below
PCH: device id xxxx (rev xx) is Cannonlake-Y Premium
Change-Id: I420e94043145e8a5adcf8bb51239657891915d84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.
TEST=lspci from kernel console shows same pci device list
without and without this patch.
Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We only need the apu firmware in the RO region when building
for ChromeOS. Adding it to the RW regions is a waste of space.
BUG=b:70027919
TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections.
Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the old timing, the hblank time isn't large enough,
it may cause display artifacts. So fix it.
BUG=b:70160653
TEST=panel work on Scarlet rev2 board
Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rework ACPI tables based on a mix of previous work on asus/p2b,
other boards in tree with better ACPI support, and OEM BIOS.
To be pulled in by DSDTs of mainboards using this southbridge.
Disable on-the-fly generation of mainboard _CRS node. It is not working
as it should and causes runtime errors when booting Linux. This node
to be included in mainboard DSDTs in followup patches.
Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In preparation to deleting early_setup,c, change early_ec_init() to use new
southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>.
BUG=b:64033893
TEST=Build, boot and check serial output, search for "Covered by wideIO xx",
which should match earlier message "Range assigned to wide IO xx" generated
within modified early_ec_init().
Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the new wide IO functions from southbridge.c to simplify code in
functions set_child_resource and lpc_enable_childrens_resources.
BUG=b:64033893
TEST=Boot to OS, check serial output against previously recorded serial
output from an image without all 5 related changes.
Change-Id: I8533e8ff766df8a8261298559aace7666487826d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create new generic wide IO functions in southbridge.c. These new
functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.
BUG=b:64033893
TEST=Just build at this stage, full boot to OS and verify serial output
at related change 14fdd03a83. Some extra outputs for testing removed
when code was committed.
Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change updates memory SPD handling code in baseboard poppy to
allow variants to define either LPDDR3 or DDR4 memory types. In
addition to that, it also updates the function to print SPD info
considering offsets that might be different across the two memory
types.
BUG=b:70188937
Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice.
So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that
clock is ON in S0ix state.
BUG=None
TEST=put DUT in S0ix, verified DMIC_CLK
in scope when wov capture path is ON
Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This partially reverts commit a7b97510ae.
For the internal eMMC to be used by Windows for installation,
the CARD device and _RMV methods are required. Without them,
Windows does not see/show the eMMC as a valid installation
target.
TEST: boot google/chell with Tianocore payload and install
Windows 10 to the internal eMMC drive.
Change-Id: I04819ff16ab4cb0d2ea6e1c7f47179f5dacb7cfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22684
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.
Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"
BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.
Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This option should've been selected by RK3399 the whole time since the
SoC supports the <soc/gpio.h> interface. It wasn't really a big deal
until now where I'm trying to use a the base2 read helper, though.
Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22744
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On many recent Chrome OS boards, the desire to unite more configurations
under the same image has led to the need of a "SKU ID" that identifies
different configurations of the same board (e.g. with certain optional
components stuffed or not stuffed, or replaced with a comparable
component). This is markedly different from the existing "board ID",
because that is reserved to count "revisions" -- changes made to the
same configuration over time during the development process. This patch
adds support to have a mainboard define this SKU ID and pass it through
the coreboot table like we already have for board IDs.
Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22696
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.
Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the
Urara board which is now long dead, and have never been used anywhere
else. They were trying to do something that we usually handle with a
separate SKU ID these days, whereas BOARD_ID is supposed to be reserved
for different revisions of the same board/SKU. Get rid of it to make
further refactoring of other options easier.
Also shove some stuff back into the Urara mainboard that should've never
crept into generic headers.
Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22694
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variants nautilus and soraka currently provide the exact same
definition for variant_cros_gpios as provided by the baseboard. This
change removes the function defintions from variants so that the weak
definition in baseboard can be used.
Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22705
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow
variants to define ACPI tables for camera support. It also prevents
boards that do not need this from unnecessarily providing dummy files
for camera ACPI support.
Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the prefix for TPM options from POPPY_USE_* to
VARIANT_HAS_*. This makes it clear that these are variant specific
options.
Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to allow variants to select different Kconfig options, this
change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be
selected by each variant in Kcnonfig.name.
Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change removes the dynamic disabling of TPM based on config
options. Poppy and its variants will have only one type of TPM
supported and so there is no need to update it dynamically.
Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the USB over current pins for the Grunt baseboard and
Kahlee mainboard. Removes the ACPI ASL OC code, which is not
used on Stoney Ridge SOC.
BUG=b:69229635
TEST=Build and boot Kahlee. Not tested with OC test fixture.
Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch enables WOL feature.
BUG=b:69290148
BRANCH=None
TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure
the system could be woken up by WOL packet.
Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix a regression introduced by #212270709dc04
(ec/lenovo/h8/acpi/thermal: Add ACPI fan control).
The commit caused Windows to crash as EC reads aren't allowed in the fan
device or it's powerresource's methods. Implement the same approach as all
other platforms using a GNVS variable named FLVL instead of reading from EC.
In addition to EC reads writing to FIELD elements, in another ACPI scope,
seems to be broken. Introduce a new method to set the fan disengage mode.
Tested on Windows 7 and Lenovo T500.
Change-Id: Ia99f8814ac14194578dcd1aa50a63e3f35c042dd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Replace the unused DTS2 field with FLVL (fan level).
Required to use the fan level on all thinkpads to store and retrieve the
current fan level.
Possible additional use case is to modify the fan level from a SMI handler.
Change-Id: I1ee5348d24b018ab1b61067813c1db63d6706c12
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22513
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
1. Programs PNP values for AUNIT, BUNIT & TUNIT registers
as per reference code.
2. A new configuration option pnp_settings is introduced in
devicetree.cb to select PNP settings among performance,
power, power & performance.
TEST = built and booted glkrvp, verfied that the callback gets
control, verified warm and cold reboots.
Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code dealing with the old config string isn't needed anymore,
because the config string has been deprecated in favor of
OpenFirmware-derived devicetrees.
Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This Supervisor Binary Interface, which is based on a page of code
that's provided to operating systems by the M-mode software, has been
superseded by a different (currently not really documented) SBI, which
is based on directly executing ECALLs instructions. Thus some of our
code becomes obsolete. Just rip it out until we implement the new SBI.
Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
PMC controller gets hidden during FSP-Silicon initialization
using sideband interface on CannonLake platform. Hence accessing
PWRMBASE using PCI config space will return invalid BAR value as
0xFFFFF000. Also PMC PCI driver will not be able to initialize
PMC controller as its not showing over PCI bus.
coreboot PCI enumeration log shows:
PCI: Static device PCI: 00:1f.2 not found, disabling it.
This patch ensures PMC controller is getting initialized using
boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/
BS_ON_EXIT).
TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller
is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT.
Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for AGESA callbacks RunFcnOnAp() and RunFcnOnAllAp().
Update the wording on the AP errors. The functions are not missing,
they are not supported.
BUG= b:66690176
BRANCH=none
TEST=Check serial output for the AP calls from AGESA.
Change-Id: Id30cb2e0c6cc474158f3a7710dbb8ecf54f1ffe4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either
is valid, but since we use parentheses everywhere else, it's better to
be consistent.
BUG=b:69691210
TEST=Build grunt & kahlee
Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22656
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Convert functionality to use coreboot-centric functions and defined
values. This change should have no functional effect.
BUG=b:62241048
TEST=Build Gardenia; Build & boot Kahlee.
Change-Id: I62ae50af05d3ac770560368245c4ae81cf9c4395
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, having a keyboard connected to the PS/2 controller of the
ASRock E350M1, after suspending and resuming the system, the keyboard
does not work anymore. A similar problem is documented in commit
448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1].
There is no reason to not disable the controller during resume. Also,
that way, the PS2 ASL method does not need to be overriden.
[1] https://review.coreboot.org/13165
TEST=Resume system, and notice PS/2 keyboard works.
Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Infineon TPM chip used on these platforms doesn't use an IRQ
line; the Linux kernel has been patched to work around this, but better
to remove it completely.
Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0
kernel parameter, observe no abnormal delays in boot or resume from S3.
Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
southbridge/amd/pi/hudson/imc.c procedure enable_imc_thermal_zone was
identified by coverity as having out of bounds access. Copies of the
procedure are present in southbridge/amd/agesa/hudson/imc.c and in
soc/amd/stoneyridge/imc.c. Fix the procedure in all 3 files.
Fixes coverity CID 1260807: Out-of-bounds read.
BUG=b:69835834
TEST=Build and platform boot to OS
Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add coreboot support for CompuLab Intense-PC (Ivy Bridge)
Modifications:
- Memory SPDs have been fixed to detect both installed SODIMM modules
- Full-height Mini-PCIe slot defaults to PCIe mode
- mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA
Tested (Xubuntu 17.10/Linux 4.13 where applicable):
- 2+2GB DDR3-1600 SODIMMs pass memtest
- 4+4GB DDR3-1600 SODIMMs pass memtest
- 4+8GB DDR3-1333 SODIMMs pass memtest
- 8+8GB DDR3-1333 SODIMMs pass memtest
- Booting via USB working (with no SATA HDD present)
- Booting to main SATA HDD working
- DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS)
- DisplayPort and HDMI dual-head working in Linux
- Mini-PCIe devices (half/full-height) detected in Linux
- mSATA working (when chosen using ENABLE_MSATA)
- Onboard Intel 82579 GbE working
- Secondary Realtek 8111 GbE working
- Rear eSATA ports working
- Onboard analog audio output working
- HDMI audio output working
- USB 3.0 working
- Suspend to RAM (S3) working, but not tested extensively
- Mini PCIe WiFi
- FACE module FM-4USB (4 USB 2.0 ports)
Disabled/unsupported:
- TPM (BTO option, not included in base config)
- FACE modules:
- FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED
- FM-SER (serial) NOT SUPPORTED/TESTED
- FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED
- FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED
- FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED
- FM-VC (video capture) NOT SUPPORTED/TESTED
- FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED
Not tested:
- RS-232
Product information:
http://www.fit-pc.com/web/products/intense-pc/
Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Whenever there is a new EC event that could be wake-capable, notify
CREC device of this using notification value 0x2 i.e. device
wake. This allows Linux kernel to track active_count value correctly
for CREC device.
BUG=b:69118395
BRANCH=None
TEST=Verified on Soraka:
1. Put device into suspend
2. Wake up using mode change/lid open
3. Check that the active_count for GOOG0004 has increased
(cat wakeup_sources | grep GOOG0004)
Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the mainboard_spd_read function in romstage and call the variants
function. Grunt is the baseboard and has soldered down memory, so add
it for the default weak SPD functions and build the SPDs in cbfs.
Kahlee overrides the weak SPD function and falls back to the soc
I2C SPD functions.
BUG=b:67845441
TEST=Build and boot Kahlee.
Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change adds infrastructure to allow variants to define their own
camera.asl file.
- Poppy and soraka use the one provided by baseboard.
- Dummy file is added for nautilus since it does not have camera
support enabled yet.
TEST=Verified that DSDT table remains the same with and without this
change.
Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Refactor the mipi driver, so we can support dual mipi panel.
And pass the panel data from mainboard.c, that we can
support different panel with different board.
Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.
Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.
Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch correct Feedback divider setting:
1. Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
2. Make the previously configured Feedback divider(LSB)
factors effective
Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Accroding to datasheet, feedback divider register high value is only
4 bit, it currently uses 5 bit, so correct it.
Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.
Let's not waste time on the wake up ping when it is not necessary.
BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
generated only when the new coreboot stage or depthcharge start,
not on every SPI slave transaction.
Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SeaBIOS 1.11.0 was released on November 10th, 2017. Changes include
* Initial support for NVME drives
* Support for vga emulation over a serial port in SeaBIOS (sercon)
* Support for serial debugging using MMIO based serial ports
* Support for scsi devices with multiple LUNs
* Support for boot-to-boot persistent coreboot cbmem logs
* Improved coreboot vga (cbvga) mode setting compatibility
* Several bug fixes and code cleanups
See also https://www.seabios.org/Releases#SeaBIOS_1.11.0 and for all
details on the changes, use
git log --oneline rel-1.10.3..rel-1.11.0
in the SeaBIOS repository.
Change-Id: Ie46a526593177c5241fbd979c7fa1934478f7382
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a CBSDK tool set template that can be used in edk2 simply by
appending $prefix/share/edk2config/tools_def.txt to Conf/tools_def.txt.
After that, build -t CBSDK uses the coreboot compilers, providing a more
predictable compiler choice.
Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
- Remove SI_ALL section. This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.
BUG=b:65497959, b:67035984
TEST=Build & boot kahlee
Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz
TEST= boot ok and the system can enter and resume from S3.
Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.
BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
are filled correctly && put system into S3 && sudo etherwake -i
eth0 $MAC to make sure the system could be woken up by WOL package.
Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With this implementation it's possible to detect the state
of bootguard in intel based systems. Currently it's WIP and
in a testphase. Handle it with care!
Changes done:
* Add support for reading msr
* Read ME firmware version
* Print bootguard state for ME > 9.1
* Make argument -s legacy
* Add argument -b for bootguard (and ME) dumping
* Add argument -m for ME dumping
* Opt out early if CPU is non Intel
Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/16328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clean the code to fix all errors and warnings.
No functional change.
Changes:
* Fix lines over 80chars
* Fix typos
* Restructure code to reduce indent level
* Move RCBA handling into own files
* Introduce helper functions for RCBA access
* Move GPL string into header
* Fix whitespace in macros
Change-Id: Ib8e3617ebb34c47959d6619dfbc7189045e6b8f7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
We are disabling tpm over i2c, so the configs are not needed
anymore.
BUG=b:65056998
BRANCH=None
TEST=emerge fizz and make sure can still boot up.
Change-Id: Id88f32fa952801749544534442fc15d85fc1a892
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As cr50 has now switched to using SPI, no need to enable the i2c1
anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.
BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many)
reboots. cat /proc/interrupts. Make sure # interrupts for 16
after booting is reasonable (not > 10k) and idma64.0,
i2c_designware.0 are not listed with that interrupt line anymore.
Should look something like this:
16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP
Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When system enters S0ix, system fails to power gate SD card
controller.
This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.
Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Some Google boards are missing this selection, leading them to being
incorrectly identified as type 'Desktop' in SMBIOS type 3 table.
Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards'
Kconfigs.
TEST: boot Linux and check correct chassis type listed via dmidecode
Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If CSE fails to do a global reset with the calling sequence of heci
reset/send/receive, then invoke pmc and hard reset.
TEST= Force global reset from early or late romstage. The function
send_heci_reset_message has the calling sequence of heci reset/send/receive.
It is observed timed out error (associated with heci_receive) occurs
only if global reset is forced during early romstage. If global reset is
trigged at late stage (i.e, after fsp_memory_init), then no timed out error
and CSE handles reset properly.
Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, mosys just returns "fizz" as model/chassis values.
Returning proper OEM IDs so that mosys can return the proper
variant.
BUG=b:67732053
BRANCH=None
TEST=mosys platform model; mosys platform chassis;
Make sure returns the right variant string and not fizz.
Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.
BUG=b:69329196
Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using
GRU_BASEBOARD_SCARLET is enough, except for display related logic. In
those cases, use board specific logic instead of baseboard.
Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/22542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.
Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.
Affected boards: amd/gardenia and google/kahlee.
BUG=b:69368752
Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Cr50 i2c driver provides separate entry points for probing and
initialization, but probing function does not really do much.
It also claims and releases locality on every coreboot stage, but
there is no need for this - locality should be definitely claimed
after reset and then it could be retained through the boot process.
On top of that the driver does not properly account for long time it
could take the Cr50 chip to come around to reset processing if TPM
reset request was posted during a lengthy TPM operation.
This patch addresses the issues as follows:
- tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept
around to conform to the expected driver API.
- tpm_vendor_init() invokes a function to process TPM reset only in
the first stage using TPM (typically verstage), the function
checks if locality is claimed and if so - waits for it to be
released, which indicates that TPM reset processing is over.
- before claiming locality check if it is already taken, and if so -
just proceed.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=Verified that reef no longer hangs during EC reboot and
firmware_Cr50ClearTPMOwner (not yet merged) tests.
Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All coreboot stages using TPM start with the same sequence: check if
locality is claimed, if so, release it by writing 'active locality'
bit, then try claiming it.
This is actually not a proper procedure: section "5.5.2.3.1 Command
Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification
Level 00 Revision 00.430 Family 2" lists overwriting active locality
status bit as a means of triggering TPM command abort.
On top of that, none of the coreboot stages releases locality, it is
enough to claim it once when device starts booting.
In fact, locality being active when the device is in verstage is most
likely due to delayed TPM reset processing by the Cr50 TPM: reset is
an asynchronous event, and is processed once current command
processing completes.
The proper procedure is to wait if locality is active until it is
released (which will happen when Cr50 processes reset) and then
proceed to claim it. This needs to happen only during verstage, other
stages using TPM are guaranteed has been claimed earlier.
BRANCH=gru
BUG=b:65867313
TEST=the new autotest triggering EC reset during key generation
process does not cause boot failures on Fizz device any more.
Below are times verstage had to wait:
TPM ready after 3132 ms
TPM ready after 22120 ms
TPM ready after 4936 ms
TPM ready after 6445 ms
TPM ready after 11798 ms
TPM ready after 27421 ms
TPM ready after 4582 ms
TPM ready after 7532 ms
TPM ready after 27920 ms
TPM ready after 3539 ms
TPM ready after 12557 ms
TPM ready after 6773 ms
TPM ready after 1631 ms
TPM ready after 197 ms
TPM ready after 24330 ms
TPM ready after 3241 ms
Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Cr50 reset processing could take long time, up to 30 s in the worst
case. The TCO watchdog needs to be disabled before Cr50 driver starts,
let's disable it in bootblock.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=verified that resetting the device while keys are being generated
by the TPM does not cause falling into recovery.
Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation)
causes a crash on the mainboard mc_apl1. On this mainboard all internal
SOC UARTs in the devicetree are switched off. As a result, no resources
are allocated to the UARTs. The function find_resource() expects an
existing resource. Otherwise, the CPU will stop. It should therefore not
only be queried whether a device is present, but also whether it is
enabled.
Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller
driver". Pass a pointer to din to the do_command() function so the
caller's copy is correctly updated. The bug allowed reads <= 5 bytes
to work correctly (3 bytes consumed in the FIFO by the address) but
overwrote data in the din buffer on larger transfers.
Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove <#include amd_pci_int_defs.h> from amd_pci_util.h, as the user
of the functions declared in amd_pci_util.h don't need the contents of
amd_pci_int_defs.h.
BUG=b:62200907
Change-Id: I258d549d3eea3fb8919c0cddbb41dc2bc4738c4e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added
marketing names for many ChromeOS devices; add some that were left out,
correct some errors, and try to format model names/numbers consistently
(or as consistently as the manufacturers allow).
Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.
BUG=b:69473883
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.
Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is merit in having new boards use the pinouts and controls
in scarlet. This adds a config so new scarlet-derived boards can
easily use scarlet structure without going through every file
and adding new logic.
TEST=Run "emerge-scarlet coreboot"
Signed-off-by: egemih@chromium.org
Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3
Reviewed-on: https://review.coreboot.org/22517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.
Also, remove a unreferenced function prototype, smbus_readSpd().
Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy the two headers used by the Stoney BinaryPI implementation into
the 00670F00 directory so that any changes that are made to them don't
affect other platforms.
BUG=b:67299330
TEST=Build
Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The mainboard directory is included through the PI makefile - most
mainboard directories aren't in the include path at all. Move the
ec.h file into the baseboard/variant directory that is already in
the include path.
BUG=b:69220826
TEST=Build
Change-Id: I89d361b700c66ba576de724927574fdab9461fc6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into
the build, so it's obviously not needed.
BUG=b:69220826
TEST=Build
Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All AGESA headers should be included only through agesawrapper.h
I missed this file in the Kahlee cleanup.
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee
Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This fixes some issues with the initial implementation that was copied
from reef.
- The board ID value shouldn't be size_t - it's not a size.
- Kahlee doesn't even need the memory.c file - it uses an SoDIMM.
BUG=b:68293392
TEST=build stoney platforms, boot kahleebo
Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22515
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's sometimes hard to find the code name of a Chromebook. Add the
marketing names to Kconfig, since they are easily available.
Information (mostly) taken from:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices
Unknown boards (unreleased, etc.):
* Fizz
* Foster
* Nasher, Coral
* Purin
* Rotor
* Rowan
* Scarlet, Nefario
* Soraka
* Urara
* Veyron_Rialto
Baseboards:
* Glados
* Gru
* Jecht
* Kahlee
* Nyan
* Oak
* Poppy
* Rambi
* Zoombini
White label boards:
* Enguarde
* Heli
* Relm, Wizpig
TODO: How does this interact with the board_status code?
Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to
src/soc/amd/stoneyridge/include/soc/.
After much discussion, src/soc/amd/stoneyridge/include/soc is probably
the best location. It was found that there are other common code that
include headers from this folder.
BUG=b:62200907
Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device. AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard. DIMM
numbering and ordering is also affected by this value.
Replace hardcoded integers with defined values for DIMM slots and
number of channels.
Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21854
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the cpu.asl file in cnl. We are only defining
the PNOT method here in this patch as this is needed by the
ec/google/chromeec/acpi/ec.asl file for the AC methods.
TEST= code compiles and boots when we include the ec.asl file.
Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Program PMx08 to support SMIs when software writes the SlpTyp bit in
the Pm1Control register. The southbridge needs to send the SMI message
prior to the completion response of the I/O cycle. Also, disable
sending the STPCLK message before the completion response.
Disable the SlpTyp functionality, then enable the SMI source.
BUG=b:65595850
Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When an SMI occurs due to SlpType, interpret the type of request being
made. If it's S3 or higher, flush the cache and disable further SMIs.
Reenable SlpTyp functionality in the ACPI logic and reissue the cycle.
BUG=b:65595850
Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add more definitions for the controller registers and fields. Add
source that is adapted from hudson and updated for Stoney Ridge.
This was tested with follow-on patches that write S3 data to flash.
BUG=b:68992021
Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
coreboot doesn't need AGESA's version of Filecode.h. Some of the files
that have been copied from AGESA include the header, so we can't get rid
of it completely yet.
- Remove includes from files that weren't copied from the AGESA source.
- Remove FILECODE definitions from coreboot source.
BUG=B:69220826
TEST=Build Gardenia; Build & boot Kahlee.
Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and
update the 00670F00 Makefile to use it instead of using the common
version.
This allows changes to stoney without affecting the rest of the AMD
binary PI platforms.
BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee
Change-Id: I2fe4303f882938e9d917a3001476213f49426455
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times. This would
add a maximum of 30 seconds to boot time.
Mirroring changes done on i2c side in CL:756918
BUG=b:65867313, b:68729265
BRANCH=None
TEST=Make sure fizz boots up
Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the ACPI DBG2 table generation for Intel boards. This is
a Microsoft defined ACPI extension that allows an OS to know what
the debug port is on a system when it is not enabled by the
firmware, so it does not show up in the coreboot tables and
cannot be easily found by a payload.
broadwell: Use byte access device, set up only when enabled since
it relies on the port being put in byte access mode and using
this serial port for debug was not standard in this generation.
skylake: Enable for the configured debug port. Skylake uses
intelblocks for UART but not ACPI.
common: Enable for the configured debug port. This affects
apollolake and cannonlake.
Tested by compiling for apollolake/broadwell, tested by reading
the DBG2 ACPI table on kabylake board and using IASL to dump:
[000h 0000 4] Signature : "DBG2"
[004h 0004 4] Table Length : 00000061
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 3B
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Info Offset : 0000002C
[028h 0040 4] Info Count : 00000001
[02Ch 0044 1] Revision : 00
[02Dh 0045 2] Length : 0035
[02Fh 0047 1] Register Count : 01
[030h 0048 2] Namepath Length : 000F
[032h 0050 2] Namepath Offset : 0026
[034h 0052 2] OEM Data Length : 0000
[036h 0054 2] OEM Data Offset : 0000
[038h 0056 2] Port Type : 8000
[03Ah 0058 2] Port Subtype : 0000
[03Ch 0060 2] Reserved : 0000
[03Eh 0062 2] Base Address Offset : 0016
[040h 0064 2] Address Size Offset : 0022
[042h 0066 12] Base Address Register : [Generic Address Structure]
[042h 0066 1] Space ID : 00 [SystemMemory]
[043h 0067 1] Bit Width : 00
[044h 0068 1] Bit Offset : 00
[045h 0069 1] Encoded Access Width : 03 [DWord Access:32]
[046h 0070 8] Address : 00000000FE034000
[04Eh 0078 4] Address Size : 00001000
[052h 0082 15] Namepath : "\_SB.PCI0.UAR2"
Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
During S3 cycling, system entered S3 only once and falied to
enter S3 the second time. The system gets stuck at this point
and we have to do a cold reboot to restore the system.
Since XHCI IP is able to power gate during kernel freeze/suspend,
this patch removes unnecessary device gating from ASL. This helps
in continuous cycling of S3.
BUG=b:69115421
TEST=run powerd_dbus_suspend multiple times and check if
the system enters and resumes from S3.
Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This further allows compilation units to be re-used without
having to add macro guards because of declarations not being
around in the __SIMPLE_DEVICE__ case. These declarations are for
functions that operate on struct device. struct device is a known
type so just expose the functions using the correct type. Also,
DEVTREE_CONST is empty while in ramstage so there's no reason
to separate the declarations. Lastly, fix up device_util.c to
use the proper types. It's only compiled in ramstage and it only
operates on struct device.
Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This feature was enabled at the kernel level, but that is triggering an
issue where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot. Since we want this enabled anyway just set it this
way in the BIOS so it matches what the kernel expects.
BUG=b:68666100
TEST=pass firmware_FWtries on Eve with R63 OS image
Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/749733
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the rt5663 driver and provide values for the offsets which are
needed for providing manual values to compensate the DC offset for
L and R channels between headphone and headset.
BUG=b:62712227
TEST=build and boot on eve and ensure rt5663 is functional.
Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/611606
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org>
Reviewed-on: https://review.coreboot.org/22446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change the touchscreen power control back to coreboot instead of
under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L
pin back to an output.
This reverts previous changes to touchscreen GPIOs that were made
to get back to a known good/working state. Having ACPI control these
pins was resulting in a small percentage of touchscreen not being
discovered at boot. This platform is not intending to use S0ix so
the ACPI control is not needed.
BUG=b:63718744
TEST=manual testing on Eve devices.
Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/572692
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22445
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
- Create header files for the stoneyridge PI that pulls in AGESA pi
headers and encloses them in #pragma pack push/pop to keep the
'#pragma pack(1)' in Porting.h from leaking.
- Add that header to agesawrapper.h, replacing AGESA.h and Porting.h
Following patches will update the coreboot code to use only
agesawrapper.h to pull in the AGESA headers.
BUG=b:66818758
TEST=Build tested
Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add register HPPI and GSTS.
Add method WLSW that is used by thinkpad_acpi kernel module.
Seperate method by an empty newline.
Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add the ability to locate the SMRAM-based SMU firmware early and
call the PSP library to load it prior to DRAM initialization. This
is currently placed in bootblock to ensure the blob is loaded
before any reset occurs.
Add similar functionality in ramstage for SMU FW2 to the hook already
in place for running AmdInitEnv. Rename the hook to make more sense.
This patch was tested using a pre-released PSP bootloader on a
google/kahlee system.
Leave the option unused until the bootloader is ready.
BUG=b:66339938
Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Hudson code, the basis for soc//stoneyridge southbridge, has typically
contained direct calls to vendorcode/amd//ImcLib.c. In an effort to
keep #include files clean in other stoneyridge files, put the new calls
into imc.c.
Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
mainboard.h only had a single function definition. Move it into
baseboard/variants.h and get rid of the file.
TEST=Build grunt/kahlee
BUG=b:69164070
Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Print error message when using common i2c without default clock defined.
TEST=Do not define default clock in Kconfig, compile will stop for
assertion.
Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Default LPSS clock need to be defined for SOC.
TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.
Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Explicitly add #include files to romstage.c to ensure sizes of the
devicetree structures are correct. The AMD support headers have an
open #pragma pack(1) which causes structure sizes to change based on
include ordering in different compilation units. More concretely, this
fixes a bug where dev->chip_info is incorrectly detected as 0.
Also shorten a printk string to bring the source line within 80 columns.
Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Several SPD hex files for chell were missing from upstream coreboot
(as compared to the Chromium tree/branch), which resulted in the
incorrect type and amount of RAM being reported on chell boards
with > 4GB RAM. Add these missing files and their Makefile entries.
TEST: boot google/chell m7/16GB config and observe correct RAM
type and amount reported via dmidecode and cbmem console log.
Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ModuleIdentifier must be 8 bytes. Every other location else that uses
this value explicityly defines it as 8 bytes. If it's initialized here
to less than 8 bytes, it gets passed to those other locations with
garbage at the end and fails to load the AGESA binary.
TEST=Build & boot Kahlee
BUG=B:69165234
Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The revision level is not checked. This was probably left over from
trying to determine hudson variants.
Remove the unused SMI command port values. This was missed in:
e9b862e amd/stoneyridge: Use generic SMM command port values
Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.
Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.
Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.
BUG=b:62200225
Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device. AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard. DIMM
numbering and ordering is also affected by this value.
Replace hardcoded integers with defined values for DIMM slots and
number of channels.
Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.
Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.
Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.
TEST=Build and boot on soraka/eve/reef/cnl-rvp
Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.
Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.
Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.
Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.
BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
when the system is in S0ix. After the system goes back to S0, verify
that the SIM with PIN lock enabled doesn't request unlocking, and the
modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
cycle and the SIM with PIN lock enabled requests unlocking.
Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan@chromium.org>
Reviewed-on: https://review.coreboot.org/22415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This further allows compilation units to be re-used without
having to add macro guards because of declarations not being
around in the __SIMPLE_DEVICE__ case. These declarations are for
functions that operate on struct device. struct device is a known
type so just expose the functions using the correct type. Also,
DEVTREE_CONST is empty while in ramstage so there's no reason
to separate the declarations. They compile regardless of stage.
Change-Id: Idd4180437d30e7dfaa9f735416c108841e43129f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times.
BUG=b:65867313, b:68729265
TEST=Verified that Soraka no longer hangs during EC reboot test.
Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables customized NIC leds as follows:
Green Orange (Amber)
100M off blinking
1000M on blinking
BUG=b:65437780, b:68284778
TEST=Make sure the registers are programmed as expected and observe the
LEDs are behaving as expected. Perform suspend/resume test and the
LEDs are still working as expected.
Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.
Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.
BUG=b:66339938
Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
An upcoming PSP firmware change will allow coreboot to load the two
SMU firmware blobs (one runs in SRAM and the other in DRAM). The
traditional method is for the PSP to control most of the process,
e.g. loading the SRAM version prior to releasing the x86 reset.
Add a new command that can instruct the PSP to load a firmware blob
from a location in the flash.
The definition for commands 19 and 1a differ from others in that they
do not use a command/response buffer. Instead, the PSP will look in
the command/response pointer registers directly for the blob's
address.
BUG=b:66339938
Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.
BUG=b:62241048
Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that recovery button has been enabled through cr50,
we can add VBOOT_PHYSICAL_REC_SWITCH config and treat
the recovery button like on any other chromebox.
BUG=b:37751915, b:63893483
BRANCH=None
TEST=With DUT in normal mode, boot into recovery, press ctrl+d
followed by pressing the recovery button. Should successfully
boot into dev mode.
CQ-DEPEND=CL:737477
Change-Id: I72fb42508083295e317dd06900796dc0cda753f6
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SeaBIOS 1.10.3 was tagged on October 12th, 2017 with the following
changes.
```
$ git log --oneline rel-1.10.2..rel-1.10.3
b7661dd tcgbios: Fix use of unitialized variable
6055583 boot: Increase description size in boot menu
3551613 resume: Don't attempt to use generic reboot mechanisms on QEMU
```
Change-Id: I3a9ebf10a55118fc35aed688ea7ec794333c8227
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Both registers behave the same as on the previous generation
Taken from
* 6th Generation Intel Processor Families for S-Platform
Volume 2 of 2
* Page 55 and 62
* 332688-003EN
Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Register definitions were taken from
* 6th Generation Intel Processor Families for S-Platform Volume 2 of 2
* Page 117
* 332688-003EN
As well as
* 6th Generation Intel Processor Families for H-Platform Volume 2 of 2
* Page 117
* 332987-002EN
Tested on a 6th gen skylake mobile cpu and capability registers do match up
with the default values.
Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The warning is printed using Printf syntax but actually Println is used
resulting in printing the format string first and the arguments second:
"%s. (%s) Default:%s WARNING: [...]"
Change-Id: I411fc47832dd7a82752f233c4909b98190340ccb
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic
Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add APIs and required parameters for creating Dialog da7219 SSP
endpoints in NHLT table.
The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render vs capture) along with
their supported formats.
BUG=b:68686020
TEST=check that NHLT table for da7219 is created properly
Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4
platform, it is also critical to revisit the GPIO settings as they are
different. Remove unused GPIO setting for old platform, and clean up the
native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set
to GPIO mode is illegal.
TEST=Boot up in chromeos successfully.
Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
SCI trigger logic had to be inverted.
This patch enables the system to wake up from S3 when lid is opened
when the system is in suspend state.We are trying to match what a
external EC card running ChromeEC FW is sending on the signal.
TEST = Verified that system wakes up from S3 on toggling lid switch
back to open state.
Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Fix initial tool check.
- Admit that the script is coreboot specfic. Remove coreboot check.
- Fix some whitespace issues.
- Get rid of pushd/popd.
- Add keywords for section logging.
- Move code for getting SLOC into a subroutine.
- Find submodules to get patch count instead of having them hardcoded.
- Update specific change areas for 4.7 release
Change-Id: I115659a75604c24780c09605d7643e83e481f6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.
Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE
can be translated to string and shouldn't be translated by
"Unknown device path type: 0".
Makes console output a lot prettier and readable.
Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots.
Change-Id: I08d471d8217f966e80daefe2d9971e357defde62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When autoport is run on a system without supported southbridge
it won't populate the coresponding data structure. By sanitiy
checking after PCI detection autoport can exit cleanly and
provide a sufficient error message.
Error was:
panic: runtime error: invalid memory address or nil pointer dereference
[signal SIGSEGV: segmentation violation code=0x1 addr=0x30 pc=0x4be595]
goroutine 1 [running]:
main.FIXMEEC(0xc42014af80, 0x14, 0xc42014afe0, 0x1a, 0xc4200a914f,
0x4, 0xc4200a916f, 0xf, 0xc420149e60, 0x28, ...)
/coreboot/util/autoport/ec_fixme.go:14 +0x105
Change-Id: I6b0fcda76d33b0d3a0379c279f492160ce5add84
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.
Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Accessing the config string doesn't work anymore on current versions of
spike. Thus return dummy pointers until we have a better solution.
Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one
observed) garbage bytes may detained in the output queue of EC after power
up, and they should be cleared otherwise later communications will be
disrupted.
Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22181
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
EC's output could be considered as a queue, and sometimes (observed on
Thinkpad T400s during cold boot) a few (only one observed) garbage bytes
may detained in such queue after power up. Those garbage bytes should be
checked and discarded first before real interactions, otherwise they may
disrupt the interaction during EC's enablement, causing a locked rfkill.
Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When using microcode header and updating the header (due to a new
release of microcode during early development) the build system
doesn't detect the header change. This commit fixes this by adding
the appropriate dependency.
Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013.
select SSE2 per review suggestion
Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.
This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.
Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
bebitenc() just runs a downward loop over the same body as lebitenc().
That doesn't give you a byte-swapped result, it gives you the same final
value, just starting from the other side to fill it in. (Also, it
confused i++ and i--, so it really gives you a compiler error.)
The correct code needs to have the array index inverted relative to the
bit shift index to produce a big endian result.
Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.
Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
CQ-DEPEND=CL:*496012
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I580567decfccd78366c37181255015ac2cd76493
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In some cases users may want to build just one toolchain not all. This
patch introduces COREBOOT_CROSSGCC_PARAM, which by default is set to
all_without_gdb so previous behavior is not changed. Users can pass
different parameter eg. COREBOOT_CROSSGCC_PARAM=build-x64 to build just
x64 SDK.
Change-Id: I858ba09644b5b86a4b0e828e4f342aee5083be93
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Disengage the fan 10 degree below passive threshold as the automatic EC fan
control does not disengage the FAN even when CPU starts melting ...
* Add EC registers FAND and FANA.
* Add ACPI methods _AC0 and _AL0.
* Add fan device and PowerResource for fan control.
Tested on Lenovo T430:
* The fan disengages at 80°C and keeps running at full speed until temperature
drops below 80°C.
* Fan can be disengaged using sysfs:
/sys/devics/virtual/thermal/cooling_device0/cur_state
Tested on Lenovo T500:
* The fan disengages at 80°C and keeps running at full speed until temperature
drops below 80°C.
* Fan cannot be disengaged using sysfs, but the current state can be read:
/sys/devics/virtual/thermal/cooling_device0/cur_state
Change-Id: I075ff5c69676927db1c5e731294e18796884f97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21227
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI spec requires _TSP, _TC1, _TC2 and _PSL for passive cooling.
_TSP already has been added in a previous commit.
Copy the coefficients used on google devices to activate the feature.
Tested on Lenovo T430:
The CPU is throttled once the passive threshold has been reached.
Tested on Lenovo T500:
The CPU is throttled once the passive threshold has been reached.
Change-Id: I922923a9029de77158988ac254bab4aad9536935
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Emits a list of CPU cores, e.g.
Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 })
Tested on Lenovo Thinkpad T500.
Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Global variables that are unitialized in C programs reside
in the .bss section. By definition, this section is cleared
to 0. Therefore, remove the explicit NULL initialization because
it's completely unnecessary.
Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
memset() exists for a reason. There's 0 reason to duplicate the
functionality but add extraneous parameters that do nothing. This
is just poor coding practices. Remove LibAmdMemFill() usage.
BUG=b:62240746
Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
If CONFIG_COLLECT_TIMESTAMPS not set all timestamp
functions should be deactivated by using a pre-processor
statement.
Change-Id: I8ac63ba7e4485e26dc35fb5a68b1811f6df2f91d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In general more ME capabilities are considered harmfull, useless or
unwanted. Therefore an easy overview can be obtained by coloring in red
and green.
Taken from Change with id:
Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a
Add bootguard information dump support
https://review.coreboot.org/#/c/16328/
Change-Id: Ia911cc935d512174399aaf93bba982e071942212
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
In skylake based platforms, setting GPIO pad reset config
to DEEP will reset the gpio configuration across warm reset,
set it to RSMRST to preserve the configuration across warm resets.
Also, moving the configuration from early to late as appropriate.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...
Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.
1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021
Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit...
Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107.
Use get_ramid() to determine if override is necessary.
Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Once coreboot is ready and payload has been loaded a bit inside the NC
FPGA needs to be set to notify this event. As there are NC FPGAs with
different PCI device IDs save the BAR0 address in a global variable once
the driver evaluates this address. It can then be used to access the
register from the boot state machine callback without the need of searching
for all possible PCI devices again.
As this driver is only used at ramstage there is no need of using
CAR_GLOBAL for the global variable. Use a Kconfig switch to make this
feature selectable from mainboard as not every mainboard may have a FPGA
with that capability.
Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.
Plus combine the 3 lines that set 3 bits in XBCS into one.
Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark
below.
```
dsdt.aml 87: Method (_CRS, 0x0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized \
(due to creation of named objects within)
```
So, serialize the method.
Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad)
Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Use the correct conversion specifier for `size_t` to fix the error
below.
```
from src/soc/intel/quark/spi.c:18:
src/soc/intel/quark/spi.c: In function 'xfer':
src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \
of type 'long int', but argument 3 has type 'unsigned int' \
[-Werror=format=]
printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
^
```
Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Clang Static Analyzer warns about an unused assignment, when
building the image for the Lenovo X60.
```
src/arch/x86/gdt.c:39:6: warning: Value stored to 'num_gdt_bytes' \
during its initialization is never read
u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt;
^~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
If `CONFIG_RELOCATABLE_RAMSTAGE` is selected, the function returns
before the assignment is used. So, move the assignment below the if
statement.
Change-Id: Ibcb8bce743d8cb3625647804816fb97f937dc429
Found-by: clang version 4.0.1-6 (tags/RELEASE_401/final), Debian Sid/unstable
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Move files that are particularly specific to the mainboard into the
variant directory. Files that only have small areas of mainboard
specific pieces use #if to separate between the boards.
Add memory.c to split out the variant board id into a weak function.
Add baseboard/gpio.h to satisfy the build - this will be updated in the
next commit.
BUG=b:68293392
Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the warning below by making the integer literal unsigned.
```
CC bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
alignment = 1 << (log2_ceil(window_size));
~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)
Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the warning below.
```
CC bootblock/lib/reg_script.o
src/lib/reg_script.c:375:11: warning: Value stored to 'value' during its \
initialization is never read
uint64_t value = msr.hi;
^~~~~ ~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: fd461e39 (regscript: Add support for MSR type)
Change-Id: I218e45d12f2f00e2ad4cfe5410029f407b57568d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
On this mainboard there are PCI devices, which are connected to the PCIe
root port via a PCIe-2-PCI bridge. One of the devices only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 4 (Device 14.0).
The following routing is required:
INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA#
Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.
Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1
panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
CQ-DEPEND=CL:*493633
Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/22294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The x86 bsf and bsr instructions only allow for a memory
or register operand. The 'g' constraint includes immediate
operands which the compiler could choose to emit for the instruction.
However, the assembler will rightfully complain because the
instruction with an immediate operand is illegal. Fix the constraints
to bsf and bsr to only include memory or registers.
Change-Id: Idea7ae7df451eb69dd30208ebad7146ca01f6cba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.
TEST=Boot to OS and verify wifi
Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When Cr50 TPM is being reset, it continues replying to the SPI bus
requests, sends wrong register values in response to read requests.
This patch makes sure that the TPM driver does not proceed unless
proper value is read from the TPM device identification register.
If the read value is still wrong after 10 retries taken with 10 ms
intervals, the driver gives up and declares TPM broken/unavailable.
BRANCH=cr50
BUG=b:68012381
TEST=ran a script resetting the Fizz device as soon as the "index
0x1007 return code 0" string shows up in the AP console output.
The script keeps rebooting the Fizz indefinitely, before this
script Fizz would fail to read TPM properly and fall into
recovery after no more than four reboots.
Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a function to program a customized LED setting
for Realtek 81xx family. It reads the settings from devicetree under
target board and programs the setting to offset 0x18 and 0x19.
BUG=b:65437780
TEST=Add customized_leds register in devicetree.cb under target board,
enable RT8168_SET_LED_MODE flag. Make sure the setting is
programmed correctly to offset 0x18 and 0x19. Observed the
LEDs were behaving as expected. Executed suspend/resume and
the LEDs were still working as expected.
Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is to enable SPD word access to reduce boot time. It can save
80 ~ 100 ms per DIMM.
BUG=b:67021853
BRANCH=None
TEST=system boot, and boot time is reduced
Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Raydium, export reset GPIO as well as PowerResource.
Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode.
BUG=b:67879912
BRANCH=coral
TEST=emerge-coral coreboot
Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/22252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change increases the spd read performance by using smbus word
access.
BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm
Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it is fairly uncommon, add a weak call that may be done by
the platform if it has the support.
BUG=b:66690176
BRANCH=none
TEST=coreboot builds.
Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When building the Go version of cbmem I found that
LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP.
I am guessing that this tag was little used. In any event, move it
forward to 0x33.
Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/22218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This was moved out of northbridge/gm45 but was accidentally? commented
out in c5d972d073 "Move select UDELAY_LAPIC from nb/gm45/Kconfig to
cpu/model_1067x/Kconfig"
The intel eagleheights mainboard also uses UDELAY_LAPIC with this
change and is untested.
Change-Id: I70e51fa50935baf187cef60f2e636251b40d6475
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22172
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This enabled subdirs-y += * to work properly.
BUG=b:68384012
BRANCH=none
TEST=Run `abuild -t GOOGLE_CORAL -p none` and observe that
`find coreboot-builds/GOOGLE_CORAL -type d -name '\*'` doesn't return
any files called '*'.
Change-Id: Iba7866db339ae9b4063c4b4377500652eb1be13d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path),
BDA and EBDA are wiped in the resume path. It results in coreboot
forwarding table address being wiped out since it is stored in the
BDA. This issue was resolved for platforms using EARLY_EBDA_INIT in
commit f46a9a0d (arch/x86: restore forwarding table on resume for
EARLY_EBDA_INIT). However platforms that do not use EARLY_EBDA_INIT
still run into the same issue and hence cbmem does not work on
resume. This change fixes the issue by using the stash/restore of
forwarding table address for all platforms using BDA.
BUG=b:68412690
TEST=Verified that cbmem works on S3 resume for coral.
Change-Id: I42ae2ccb0b4ce8e989b1032d82b9bb34d0d84db0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add new libhwbase options and add a class for files generated during
build. This follows the same pattern as for libgfxinit.
Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds a column to the print command to show the compression
algorithm used for the file.
Name Offset Type Size Comp
fallback/romstage 0x0 stage 56236 none
ecrw 0xf2380 raw 62162 LZMA (131072 decompressed)
BUG=b:66956286
BRANCH=none
TEST=Run 'cbfstool image.bin print'
Change-Id: I4bbb60ab467adac4ae5486ddafec86ad9682a40e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using common p2sb driver instead of private one.
TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.
Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake
in the AGESA spec and the function is in the wrong section.
bug=b:66690176, b:67210418
branch=none
test=none
Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add new board librem15v3 as a variant of the librem_skl baseboard.
Changes from the librem13v2:
- Change board name and version
- Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO
- Enable PCI device 1c.4
- Change USB port definitions in devicetree
TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware
Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22048
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
intel/common's pmclib already keeps track of the power state (since
commit f073872e22 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.
BUG=b:67976359
BRANCH=none
TEST=builds
Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Convert the Purism Librem13v2 board to a variant setup,
in preparation of adding the librem15v3 as a new variant.
The 13v2 and 15v3 are nearly identical, so this minimizes new
code to add support for the latter.
Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22047
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused
array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These macros, broken since day one, should CreateByteField instead
of CreateWordField. Without the fix, any ASLs that try to use it
will fail to compile with a "ResourceTag smaller than Field"
warning.
Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Allows explicit ordering for vendors that share a common configuration
that must be sourced last.
The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.
Note: intel and amd soc chips now need to be added manually to the new
Kconfig file
BUG=b:62235314
TEST=make lint-stable
Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Although Intel's current spec[1] shows the OpRegion structure version
as being the top 16 bits of the field, Intel's Windows drivers
require the OpRegion structure version to be in the top 8 bits of
the field when not using a VGA BIOS (eg, NGI or GOP driver).
As the Linux i915 driver only checks that the version is >= 2,
there is no change in functionality there.
This change effectively matches Intel's implementation in TianoCore,
where the version is set to 0x0200 << 16.
[1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and
Legacy mode with libgfxinit, observe Intel GPU driver functional.
Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Migrate the Librem13v2 from using FSP 1.1 to
the public/GitHub FSP 2.0 Skylake/Kabylake release:
- select FSP 2.0 in Kconfig
- adjust romstage/ramstage functions as required
- refactor pei_data functions
- remove VR_RING domain from devicetree (unsupported in FSP 2.0)
- add SataSpeedLimit parameter to work around power-related issue
when operating at SATA 6.0Gbps speed
TEST: build/boot Librem13v2, observe successful boot, lack of
SATA-related errors in dmesg.
Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092
Increase the stack size from 4kiB to 8kiB to prevent stack overrun.
TEST=No stack overrun is observed and it boots to OS properly.
Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms. It allows to include a vbt.bin and
allows GNU/Linux to load the opregion as ASLB is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now
a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic
to set temperature offsets and limits is in the function that sets
thermal modes, it makes sense to treat PECI as yet another mode.
As of this commit, there are no boards that actually use peci_tmpin from
ite/common. There are three boards that have a similar device tree
option, but those boards use it8772f, which implements all superio
functions on its own.
The first user will probably be Gigabyte GA-Z77-DS3H.
Change-Id: I39da50c124ad767f8681302733cf004622975e81
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add devicetree options to set temperature limits that are used to alarm
user when temperature exceeds defined values.
Audio alerts by superio are not implemented yet, but since limits are
visible to userland, some software might use them as is. For instance,
lm-sensors displays "ALERT" when temperature exceeds limits.
Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.
As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.
I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.
TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The RComp values have been updated to match what is shown in the schematics.
Extracting the Memory configuration blob from the original BIOS (A blob
which contains the correct binary sequence matching the RComp values appears
in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find
and confirm the DQ and DQS mapping.
Small code cleaning in romstage.c with no effect.
Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Using ifdtool to change layout on a 'ifd v2' file causes an error
about region type 5 not being valid.
The limit to check against is dynamic depending on ifd version, not
static.
Change-Id: Id4cdce4eac18fb0d171d1bdfa2044340bf93056a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The ME status is the interpretation of the status registers, but
having the actual status registers printed is important and it doesn't
hurt to show them.
Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and
rely on the cbfs search 100% of the time. The change was initially
put in to avoid a hang when vboot presearched memory for the blob.
The implementation now supports early cbmem init and cbmem_top() is
careful to return 0 if DRAM has not yet been set up. As a result the
hang no longer occurs and the hack may be removed safely.
BUG=b:67747902
Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are still Ethernet drivers out there in the wild which expect
that the master enable bit was set by firmware. A missing master
enable bit will lead to a non-functional driver. Though it is clear the
task of the driver to set this bit it is too late now. So work around
this issue on firmware level...again!
Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add GPE configuration table.
Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).
Set the EC and PCIE/WLAN SCI GPIO signals.
Set GPE ASL methods for:
PCIE/WLAN 8h
EHCI 18h
XHCI 1fh
Note EC GPE3 methods are in the EC ASL.
BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.
Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add printout before EC hibernates during a cr50 update to clarify that
failure is due to EC rather than cr50. Ran into a situation where DUT
shut down during cr50 update and the EC was the culprit.
BUG=None
BRANCH=None
TEST=None
Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set PL2 based on either 90% of usb c charger's max power or sku id if
using a barrel jack.
BUG=b:37473486
BRANCH=None
TEST=output debug info for different skus and make sure
PL2 set correctly.
Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add google_chromeec_get_usb_pd_power_info(), which will
call the EC_CMD_USB_PD_POWER_INFO host command to retrieve
the current and voltage info of the usb c charger.
Returns power info in watts.
BUG=b:37473486
BRANCH=None
TEST=output debug info to make sure that correct power
is returned.
Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add functions for configuring the GPE ACPI SCI events.
BUG=b:63268311
BRANCH=none
TEST=With the Kahlee GPE setup patch, test lidswitch powers
the device on and off at the login screen.
Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Call sgx_fill_gnvs to update GNVS data, if
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.
- With this patch SGX ACPI device would get pached with enumaretd values
of ECP device status, base address and length
Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These functions are not currently used, and were not in the original
AGESA source code drop.
The structs involved here were marked "private" in AGESA headerfiles
and should not be exposed. They could be handled as anonymous structs
and required allocation size is communicated by other means.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: Iec346205470150257fd9d09131d54231b321740b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't
set it to VOID. 0 works for either UINT32 or VOID *, as demonstrated
by the other 7 places in this file where it's already set to 0 instead
of NULL.
Change this location to 0 to support either version of the headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The new test lets git check if $top is actually a git repo, instead of
just looking for clues.
BUG=chromium:776174
BRANCH=none
TEST=`mv .git .foo; mkdir .git; util/genbuild_h/genbuild_h.sh` provides
a valid build.h instead of failing because git is unhappy about the
.git directory.
Change-Id: I7fcc64d66e0b59fca1479b4c142fd0559aa984f4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Replace southbridge registers and register values from magic numbers to
literals, provided these registers are currently defined publicly or in
NDA datasheet.
Registers available only internally to AMD are left unchanged.
BUG=b:62199625
Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As long as user.name and user.email are set, gitconfig should pass. This
handles if values are only set for the local repo, or if values are
stored in ~/.config/git/config
BUG=none
TEST=make gitconfig
Change-Id: Ie01e7a155f9e6db35d5991e4303aad85fb277a06
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
needed for CNL.
TEST=Pre-OS screen comes up and VBT is getting passed to kernel.
Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add GPIO initialization for mc_bdx1 mainboard. Call init_gpios() as
early as possible as FSP will set up things (like hiding PCI devices)
rather early. If connections on the mainboard are dependent on GPIO
settings then FSP can screw things up (e.g. disabling not yet connected
PCI root ports).
Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
XMP profiles can have a restriction on max supported DIMMs per channel,
but many configurations work with more DIMMs.
This is relevant on mainboards with 2 DIMM slots per channel (usually 4
in total). Populating both slots with DIMMs that support XMP profiles only
with 1 DIMM per channel turns off said XMP profiles.
TEST=On a system with two DIMM slots per channel populate both slots on
one channel and ensure that DIMMs run with XMP profiles enabled.
Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Collecting time stamps is useful, especially for board status uploads,
and doesn’t come with any downsides. So enable it by default on as many
boards as possible.
The boards below currently fail to build properly, so only enable it by
default on x86.
1. board.CUBIETECH_CUBIEBOARD
2. board.EMULATION_QEMU_POWER8
3. board.EMULATION_QEMU_UCB_RISCV
4. board.EMULATION_SPIKE_UCB_RISCV
5. board.LOWRISC_NEXYS4DDR
6. board.TI_BEAGLEBONE
Change-Id: Ib01176fc2a4dffe37827c136bb8214083ce61180
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/11864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Earlier the EC expected the host to set appropriate masks before
reading host events. However, with recent change in EC, this is no
longer required. This change removes the setting of wake_mask before
and after reading the host events. However, in order to support older
versions of EC, a new feature flag is added on the EC side that
informs the host whether or not it is using the new way of reporting
host events without having to set wake mask.
CQ-DEPEND=CL:719578
TEST=Verified that EC wake events are correctly logged with both old
and new versions of EC.
Change-Id: Ib17e1296fb7d3bbc84fc7581fd0a9bd179ac87b9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22006
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If GPE_STS indicates that the wake source is internal PME, but none of
the controllers have the PME_STS bit set, then try probing individual
XHCI ports to see if one of those was a wake source. In some cases
e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi
callback and clears PME_STS_BIT in controller register. In such cases,
xhci port status might provide a better idea about the wake source.
BUG=b:67874513
Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Ensure that port_status read is not all 1s to ensure that read from
mmio address returned valid data.
2. If device connect/disconnect shows that it was a wake source, there
is no need to check for usb activity.
BUG=b:67874513
Change-Id: Id8b4a1fec7bfe530fe435a0f52944b273cdd89ad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a mask to allow SMI handlers to be run even in SCI
mode. This prevents any SMI handlers from accidentally taking
unnecessary action in SCI mode.
Add APM_STS and SMI_ON_SLP_EN_STS to this mask to allow gsmi and sleep
to work in SCI mode.
BUG=b:67874513
Change-Id: I298f8f6ce28c9746cbc1fb6fc96035b98a17a9e3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on skylake.
BUG=b:67874513
Change-Id: Ie1f81e956fe0bbe2e5e4c706f27997b7bd30d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:67874513
Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows the same functions to be used across ramstage and
smm without having to add checks for what stage is using it.
BUG=b:67874513
Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change creates a new function pmc_fill_pm_reg_info that fills
chipset_power_state structure with all the PM register
information. On the other hand, already existing pmc_fill_power_state
calls into pmc_fill_pm_reg_info and then checks and returns previous
sleep state information. This allows caller to get all the PM register
information when previous sleep state is not relevant.
BUG=b:67874513
Change-Id: Idc91e4aef5379549355aceb685f7afafa6a220c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22080
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add support for new GSMI commands to log S0ix entry/exit
information in elog.
2. In case of resume, provide callbacks to allow platform and
mainboard to log any wake source information.
BUG=b:67874513
Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path)
the BDA and EBDA are wiped in the resume path. However, the coreboot
table forwarding entry wasn't taken into account so that was wiped
which resulted in cbmem not working on the resume path. Fix this
by stashing the forwarding table in cbmem and restoring it on
the resume path.
Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.
TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.
Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.
BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
working well when system resumes from S3. Checked dmidecode
information and SMBIOS type 17 data is the same with cold
boot.
Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch implements soc override function to calculate reserve memory
size (PRMRR, ME stolen, PTT etc). System memory should reserve those
memory ranges.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.
Change-Id: I3052a255c4496dc81c8dfc6882d3ad504abae9c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses PMC common function to get previous sleep state
using cbmem or chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EC maintains a FIFO of all MKBP events and sets host event whenever
a new entry is added to the FIFO. Clearing only the host event for
MKBP creates an inconsistent state where there are pending MKBP events
in the FIFO but host event for MKBP is cleared. In order to maintain a
consistent view, host should clear all MKBP events in the FIFO if host
event is being cleared.
This change drains out all the MKBP events in the FIFO when
clear_pending_events is called.
TEST=Verified by adding debug logs in EC to verify that all the MKBP
events that occur before clear_pending_events is called get cleared
from the FIFO.
Change-Id: I131722dc01608dff30230fe341e6b23ae4cc409e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds a new helper function google_chromeec_get_mkbp_event
that allows coreboot to query EC for the next available MKBP event.
Change-Id: Ia6d64586ca62378d08025c96c2689c00c816041f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Instead of disabling all GPEs during PMC init in bootblock, this
change moves it to pmc_fill_power_state which allows romstage to
correctly fill up GPE_EN registers in chipset_power_state. This is
essential for correctly identifying the wake source.
Disabling all GPEs was added recently in change 74145f76
(intel/common/pmc: Disable all GPEs during pmc_init) because keeping
GPEs enabled in coreboot while enabling SMI could lead to
side-effects as explained in the change. Moving pmc_disable_all_gpe to
pmc_fill_power_state should be safe as that happens before SMI is
enabled in coreboot.
TEST=Verified that GPE-based wake source is correctly
identified. Also, no issues observed while resuming from S3.
Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's more consistent to re-initialize EBDA in all boot paths.
That way, the data living in EBDA is cleared prior to be
accessed (assuming it's after setup_ebda()).
Change-Id: I05ff84f869f7b6a463e52b4cb954acc5566475cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It's possible for chipsets utilizing ebda to cache the cbmem_top()
value to be called prior to the object being entirely setup. As
such it's important to check the signature to ensure the object
has been initialized. Do that in a newly introduced function,
retrieve_ebda_object(), which will zero out the object if the
signature doesn't match.
Change-Id: I66b07c36f46ed9112bc39b44914c860ba68677ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add hexdump.c to Makefile.inc and change an elog_debug format to
use %z for size_t arguments. This corrects build errors when ELOG_DEBUG
is used.
Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
> Could you make in a separate, independent change a update from the
> completely outdated LIBELF (from mr511.de/software/libelf ) to recent
> libelf? Those highly outdated libelf from this unmaintained mr511.de
> webpage should not be used any more since years. There are also a ton
> of security issues like for example: CVE-2017-7607, CVE-2017-7608, ...
> CVE-2017-7613. Recent version of this software is included in the
> elfutils that are available here: https://sourceware.org/elfutils/ ->
> download link:
> https://sourceware.org/elfutils/ftp/0.170/elfutils-0.170.tar.bz2
Remove the obsolete patch, which doesn’t apply anymore, and only
affected the build system, which is different now.
Increment the buildgcc version string as a tool version is changed.
TEST=Running `make crossgcc-i386` succeeds.
Change-Id: Iadd320a18c5d9fe2a82a347e39f01d8b7f8806c2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/21435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The code used to split up ranges >64MiB into 64MiB-aligned and
unaligned parts. However in its current state the next step,
calc_var_mtrr_range(), results in the same allocation, no mat-
ter if we split the range up before. So just drop the split-up.
Change-Id: I5481fbf3168cdf789879064077b63bbfcaf122c9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable CQOS on Geminilake.
In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.
Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.
Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right
bits.
BUG=None
TEST= Build for Geminilake platform i.e., glkrvp & check for successful
CAR setup. Even verified the same on APL platform i.e., on Reef
Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com
Reviewed-on: https://review.coreboot.org/21701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Stoney Ridge APU has only two internal UARTs. Add checks for
invalid settings. When enabling the UART, return if the console is
on any UART not equal 0 or 1. The base address returned is 0 if an
invalid configuration is used. All callers check the return value
before using the returned value. Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.
BUG=b:62201567
TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS.
Build without ST UART and inspect with objdump.
Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address. This is consistent with all other
functions that use the uart_platform_base() function.
This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0. Execution was able to complete
through depthcharge and into the OS.
Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test. Firmware shows up
inside CBFS. Set 'outside of cbfs' option, verify firmware gets
written to the correct location.
Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.
BUG=b:65484600
TEST=Build & boot
Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Factor out the code into separate functions.
Create set_lpc_resource that will set the resource for a particular child while
lpc_enable_childrens_resources finds all children and calls set_lpc_resource
for each child found. This creates well defined boundaries for each function.
Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This updates board info of PC Engines platforms, changes board names
to official manufacturer's names and adds info about ROM. Removing
"Clone of" option for ALIX platforms makes them independent.
Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the use of the SataPortsEnable and SataPortsDevSlp registers
which were being ignored from the devicetree and were not affecting
the resulting UPD parameters.
SataPortsEnable was only being copied for the first SATA port, while
the other ports were left ignored.
Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Support the required AGESA_DO_RESET in bootblock.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The AGESA RESET_WHENEVER request were never doing a reset in coreboot.
We don't have a way to collect a whenever and reset at some later time,
so just do the reset immediately.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21978
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50. SPI is more reliable
than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI.
BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
run cold_reset and warm_reset and make sure both
boot successfully.
CQ-DEPEND=CL:714237
Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.
LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.
BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.
Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
buildgcc -B (--bootstrap-only) builds only a bootstrap compiler. That
useful if you want to package the cross compilers: first build the
bootstrap compiler, then all required cross compilers in a separate
directory (using the bootstrap compiler through an adjusted PATH).
Change-Id: I089b51d1b898d4cf530845ba51283997fd229451
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.
Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.
It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.
Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a new common method to initialize ACPI OpRegion.
* Try to locate vbt.bin in CBFS.
* Try to locate VBIOS in CBFS.
* Keep existing code to probe at 0xc0000.
Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy
VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at
0xc0000.
Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake
vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS).
In all cases linux was successfully provided with VBT from ACPI
opregion.
Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If GPEs are not cleared during pmc_init, it could result in issues if
standard wake events are generated while coreboot is
initializing. e.g. (Observed on soraka):
1. Suspend to S3
2. Lidclose
3. Lidopen
4. EC wakes up the host using WAKE# pin
5. On wakeup, pmc_init occurs which does not clear GPEs
6. MP init enables SMI
7. In order to add wake event to elog, coreboot sets wake mask on the
EC, which causes the EC to assert WAKE#.
8. Since WAKE# is asserted, it results in an SMI#. However, EC does
not de-assert WAKE# until host queries and clears the host event
bit (which does not happen since coreboot is stuck in handling the
SMIs).
This is one of the issues that can occur when GPEs are unnecessarily
enabled in coreboot. Before the move to PMC common library, SKL PMC
driver set all GPEs to 0 and hence this issue did not occur.
This change explicitly disables all GPEs during pmc init in order to
avoid any side-effects.
BUG=b:67712608
TEST=Verified that device resumes fine using lidclose/lidopen to
suspend and resume.
Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21969
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Update gpe handling function names to explicitly mention if they
are operating on:
a. STD GPE events
b. GPIO GPE events
c. Both
2. Update comment block in pmclib.h to use generic names for STD and
GPIO GPE registers instead of using any one platform specific names.
BUG=b:67712608
Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21968
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Kconfig option to allow platforms to exclude specific files
from being copied from RO into RW sections.
BUG=b:65484600
TEST=Exclude apu/amdfw from the RW cbfs sections
Change-Id: I7723b63392c1620b75ceb6d8e25fe1ce2c75cf18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a little code to enable timestamps on FSP based implementation
of Broadwell-DE. I have tested it by reading back the timestamps
with cbmem utility once the board has booted into Lubuntu.
Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.
Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.
BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
depthcharge
Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Depthcharge was complaining that the GPIO for this flag wasn't set.
The GPIO also needs to be an input, not an output.
BUG=b:67614692
TEST=Depthcharge no longer complains that there is no GPIO set for flag5.
The system boots again.
Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Set default UART number to 2 if 32bit PCI got selected, the proper debug
print can be seen from serial port in case of switch between platforms,
especially when change to lpss uart from legacy uart or vise versa.
Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21544
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of a shell based parser for cbfstool print -k output.
BUG=b:65853903
BRANCH=none
TEST=`abuild -x -t GOOGLE_KEVIN -p none` creates a valid-looking image.
Change-Id: I33b7e1c483a69e66e82541c09582be2a71356a10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It does the opposite to "expand", removing a trailing empty file from
CBFS. It also returns the size of the CBFS post processing on stdout.
BUG=b:65853903
BRANCH=none
TEST=`cbfstool test.bin truncate -r FW_MAIN_A` removes the trailing
empty file in FW_MAIN_A. Without a trailing empty file, the region is
left alone (tested using COREBOOT which comes with a master header
pointer).
Change-Id: I0c747090813898539f3428936afa9d8459adee9c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common
code) changed the logic for obtaining previous sleep state by
unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep
S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep
S5/G3) and hence the check for power failure should be done only when
WAK_STS bit is not set. This is necessary to differentiate wakes from
deep S3 and G3.
This change restores the original logic by performing power failure
check only in cases where WAK_STS bit is not set.
BUG=b:67617726
TEST=Verified following:
1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot
correctly identifies that the system prev sleep state was S5.
2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly
identifies that the system prev sleep state was S3.
Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.
TEST=Boot to OS using Intel NVMe SSD Pro 6
Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.
Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.
TEST: build/boot google/cyan
Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change http to https on many URLs and update llvm.org URLs in buildgcc.
The old URLs are deprecated and now switched to a http forwarder that
can be attacked by MITM attacks.
Change-Id: I68d4fe1a6236ed8540803e11cfc84e44a1d1ca35
Signed-off-by: Doug Gale <doug16k@gmail.com>
Reviewed-on: https://review.coreboot.org/21729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).
However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.
BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.
Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Adapt code to latest schematic changes, revision 1.1.
Configure GPD2 for EC_PCH_WAKE_ODL,
GPP_D5 for EC_I2C_SENSOR_SDA,
GPP_D6 for EC_I2C_SENSOR_SCL,
GPP_D7 for WWAN_SAR_INT_ODL,
GPP_D9 for touchscreen power enable,
GPP_D10 for wifi power enable,
GPP_D11 for wwan power enable,
GPP_D13 change to "No Connect" (was VOL_UP_ODL),
GPP_D14 change to "No Connect" (was VOL_DOWN_ODL).
BUG=b:66265441
BRANCH=None
TEST=None
Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.
Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All callers of locate_vbt just care about the file content and
immediately map the rdev for its content.
Instead of repeating this in all call sites, move that code to
locate_vbt.
Change-Id: I5b518e6c959437bd8f393269db7955358a786719
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When reusing the same image across multiple devices, they sometimes need
different VBTs, so provide a hook for mainboard code to specify which
file is required.
Change-Id: Ic7865dc0e0c9ea3077b749d9d0482079877e9c4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The idea behind this not to enforce a license on autogenerated code
but is simply out of convenience in the case one wants to make the
result public (in which case it needs to have these license headers).
Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This generates better gpio.c files where structs are initialised as
static to be able to drop some entries since those would be
initialised as 0.
This makes these files less cluttered since only relevant things are
shown:
* GPIO direction, level, invert, blink depend on GPIO mode
* GPIO level is read only on input
* GPIO invert is only valid on input
* only show when GPIO are inverted, blinking, reset by RSMRST#
Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch helps managing power state variables from within the
library. Adds migrate_power_state which migrates the chipset
power state variable, reads global power variable and adds it
in cbmem for future use. This also adds get_soc_power_state_values
function which returns the power state variable from cbmem or
global power state variable if cbmem is not populated yet.
Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The amdfwtool now outputs firmware that is correctly built for the
new location.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix issues reported by coverity scan in the below files.
src/soc/intel/common/block/i2c
1375440: Improper use of negative value
1375441: Improper use of negative value
1375444: Improper use of negative value
src/soc/intel/apollolake/i2c.c
1375442: Unsigned compared against 0
Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update FSP header files to version 2.7.2.
New UPDs added
FspmUpd.h:
*CleanMemory
FspsUpd.h:
*IslVrCmd
*ThreeStrikeCounterDisable
Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.
CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.
Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.
Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD firmware directory can go in a number of different locations.
This patch allows amdfwtool to write the directory correctly for those
different locations.
If the --location switch is not added to the command line, the default
location at ROM base address + 0x20000 is used as before.
BUG=b:65484600
TEST=Set PSP firmware location, compare amdfw.rom to previously built
version. Verify new location pointers.
Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.
BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.
Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch implements a relatively simple hash-based verification scheme
for downloaded files (tarballs):
After buildgcc downloads a file or notices that it has already been
downloaded, it hashes the file, and compares the hash against the known
hash stored in util/crossgcc/sum/$filename.cksum. Two errors can occur:
1. The hash file is missing. In this case, crossgcc asks the user to
verify the authenticity of the downloaded file. It also calculates
its hash and stores it in util/crossgcc/sum/$filename.cksum.calc.
If the file is authentic, the user may rename the calculated hash
file to $filename.cksum, so that it can be found the next time
buildgcc is started.
2. The known hash and the calculated hash differ. This is the case that
this patch seeks to protect against, because it may imply that the
downloaded file was unexpectedly changed, either in transit
(Man-in-the-Middle attack) or on the file server that it was
downloaded from. If buildgcc detects such a hash mismatch, it asks
the user to delete the downloaded file and retry, because it can also
be caused by a benign network error. If, however, the error persists,
buildgcc can't continue without risking that the user runs malicious
code, and it stops.
Note: The hash algorithm may be changed in the future, but for now I
left it at SHA-1, to avoid bloating this patch.
Change-Id: I0d5d67b34684d02011a845d00f6f5b6769f43b4f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for following functionality:
1. Set up PCH LPC interrupt routing.
2. Set up generic IO decoder range settings.
3. Enable CLKRUN_EN for power gating LPC.
Change-Id: Ib9359765f7293210044b411db49163df0418070a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.
TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.
Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The Stoney Ridge UART and AMBA devices must be powered and report power
and clock OK prior to using the coreboot serial console. The code used
to have a delay to wait for the power and clock, but didn't check the
OK bits. This caused long delays on a reboot, as each byte would time out
until the console was reset again at romstage.
This change also removes the UART reset. The device has just been
powered and is in reset already. Testing indicates the reset isn't
needed.
BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.
Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rewrite the handler to be more compact and extendable. The old
functionality is duplicated after the rewrite. All SMI source registers
(except for SmiSciStatus) behave identically so these are consolidated.
Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on.
Create a table of mini-handlers to be supported in the soc directory.
As SMI sources are discovered, attempt to find the corresponding handler
and then execute it.
Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Use the currently programmed address of the SMI command port before
checking the passed command. This ensures we're reading the right
port in case the port was relocated without our knowledge.
Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.
BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.
Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook the new required AGESA callout functions into the callouts tables.
BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.
Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are required callout functions that currently are not implemented.
agesa_LateRunApTask does not seem to be called, but the others are.
BUG=b:66690176
TEST=Build Kahlee. Tested in next commit.
Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21707
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Ensure the stack is properly aligned in the SIPI handler. This
avoids an exception when an aligned instruction is performed on
stack data.
BUG=b:66003093
TEST=boot kahlee built with gcc 6.3
Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless
to use the variable in Makefile.inc. Make all files built into smm
unconditional.
Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the symbol SOC_AMD_COMMON is selected, include the soc/amd/common
directory. Until now this has been working due to the directory being
included as part of AGESA_INC in vendorcode. That one is still
necessary in order to build the AGESA code so it is left in place
for now.
Change-Id: Ia8191897d2030c475c9268ae86faaf01952c6ace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reorder code and put platform specific bits into update_igd_opregion.
Get rid of get_fsp_vbt and init_igd_opregion.
Write GMA opregion in case a VBT was provided, even when no FSP_GOP
is to be run.
Use SOC_INTEL_COMMON_GFX_OPREGION to reduce code duplication.
Change-Id: Ibabeb05a9d3d776b73f6885dcca846d5001116e7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
More will follow so better move them where they are used. Also remove
defaults and add dependencies to not clutter .config files up that
don't have any of these options selected.
Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It was either SAGE or AMD AES who implemented these for
binaryPI, and it is not part of the documented AGESA API.
My conclusions of these are:
AmdGetValue() returns values from build-time configuration,
these may not reflect the actual run-time configuration as
there are OEM customization hooks to implement overrides.
AmdSetValue() in __PRE_RAM__ will fail, as configuration
data is const. Also AmdSetValue() in ramstage may fail, if
said configuration data has already been evaluated.
Semamtics of these calls are unusable unless one also has
access to PI source to make exact decision on when they
can be called. Remove these now that stoneyridge does not
actually require them.
Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The cbmem utility has inherited some workarounds that originated
from the default 1 MiB mapping always working. This 1 MiB mmap
won't necessarily succeed if the 1 MiB encroaches on a subsequent
memory range that has different cacheability.
To fix this, map in only 4 KiB when the table size is not known which is
the case for any forwarding entry or any low table entries on x86. That
smaller mapping is then searched for a valid header. Once a valid header
is found the full table is mapped and parsed allowing a forwarding entry
to take precedence.
Lastly, the lbtable is kept mapped in such that other operations can
just operate on mapping that was previously parsed.
In order to allow multiple in-flight mappings a struct mapping was
added which caused the ripple within the code. However, there shouldn't
be any more reasons for putting weird heuristics for when to fail. If
the tables are bad then it's very much possible that mappings will fail.
Retrying when the exact sizes are already known won't fix those issues.
BUG=b:66681446
Change-Id: Ica0737aada8dc07311eae867e87ef2fd24eae98d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as
USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it
also should be selected for the BeagleBone Black.
Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/21486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make the spelling of *romstage* consistent without a space. Choose this
version, as *ramstage* is also spelled without a space, since commit
a7d924412a (timestamps: You can never have enough of them!).
Fixes: 0db924d74c (cbmem: print timestamp names)
Change-Id: I1b1c10393f0afb9a20ac916ff9dc140a51c716cd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
IMGU and CIO2 devices do support the hardware managed cache
coherency and hence removing the CCA object which was
reporting that cache coherency is not supported.
BUG=none
BRANCH=none
TEST=Build and boot soraka. Dump ACPI tables and verify that
CCA object is not present.
Change-Id: I14b0a92eafe193e9004d2dad0957a3fe8d05d313
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.
BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.
Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In current versions of spike, the config string is not available
anymore, because RISC-V is moving toward OpenFirmware-derived device
trees (either in FDT or text format). Using query_config_string leads to
a crash in these versions of spike.
With this commit and If0bea4bf52d ("riscv: Update register address"),
coreboot reaches the romstage again, on spike.
Change-Id: Ib1e6565145f0b2252deb1f4658221a4f816e2af4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change the cache-as-ram teardown to use invd instead of wbinvd.
Save the return and recover the call's return address in
chipset_teardown_car.
CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown. This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.
Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data. This
would likely cause corruption, e.g. during S3 resume.
Stoney Ridge now uses a postcar stage and this is no longer a
requirement.
BUG=b:64768556
Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.
BUG=b:64768556
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relocate the call to AGESA in preparation for implementing postcar.
This change should have no net effect as long as the ordering is
maintained and AmdInitEnv stays later than CAR teardown.
BUG=b:66196801
Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem,
allowing better control of its cacheability in subsequent patches.
This relocates the heap initialization from the common directory into
a romstage cbmem hook. The conversion relies on cbmem_add() first
searching cbmem for the ID before adding a new entry.
Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add an extra include file to northbridge.c for completeness. cpu/msr.h
is already included in cpu/amd/mtrr.h which allows the file to build
properly.
Remove include files that are no longer required for the file.
Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.
SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size. Add relocation attributes to be set by each
core a relocation handler.
Modify the definition of smi_southbridge_handler() to match TSEG
prototype.
BUG=b:62103112
Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Call into commmon SGX code to configure core PRMRR and follow
other SGX init seqeuence.
- Enable SOC_INTEL_COMMON_BLOCK_SGX for both GLK
- Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs
to be completed before calling into fsp-s for SGX.
Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Refactor the GPIO functions to use GPIO numbers. This is more consistent
with other GPIO code in coreboot.
BUG=b:66462235
BRANCH=none
TEST=Build and boot Kahlee
Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.
Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC.
Clean up northbridge.c by removing the check for the config value set.
Remove the CPU initialization code that clears the EnableCf8ExtCfg
bit. The location where it was set was removed in
c1d72942 Disable PCI_CFG_EXT_IO
BUG=b:66202622
Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21497
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Delete the obselete Kconfig symbols regarding the memory hole. Integrate
the hole check into domain_set_resources(). The hardware configuration
is done by AGESA, so only discover the setting and adjust the mmio_basek
accordingly.
BUG=b:66202887
TEST=Check settings with HDT
Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A regression is hidden in commit 7eb0157fca
(device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag ), which
breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set.
Maybe it had better implement "printram" and the like as inline
functions instead of macros.
Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.
AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.
Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".
Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression of IDS debugging after commit
1210026 AGESA buildsystem: Reduce include path exposure
Mainboard directory was removed from libagesa includes
path here, and this resulted with fam15tn and fam16kb using
a template OptionsIds.h file under vendorcode/ instead.
Add mainboard directory back to include path of libagesa
and remove those (empty) template files.
Change-Id: Iee4341a527b4c152269565cac85e52db44503ea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's already implemented like this with binaryPI API header.
That implementation is essentially the same with 'const' qualifier
just being ignored in the build process for PI blob.
For open-source AGESA build, work around -Werror=discarded-qualifier
using a simple but ugly cast.
Change-Id: Ib84eb9aa40f1f4442f7aeaa8c15f6f1cbc6ca295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17
is insufficient to use.
Using VPD to control could prevent H/W change.
BUG=b:65339688
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I55ab741354797e022dd945da9c8499ee5e041316
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
variant_board_sku() callback exists to allow some of the variants to
report the sku id differently based on board implementation. However,
there are cases where there are multiple ways to encode the sku id, but
the original way should be used as a fallback. As such expose a helper
function, sku_strapping_value(), such that there isn't code duplication
for the common fallback case.
BUG=b:65339688
Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.
Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We can't use $(CC) in case it's set to Clang.
TEST=Built one target with Ada sources before and after this change and
verified that the same compiler commands are emitted.
Change-Id: I9b8ea35352d74b364f09fc12d8d981ca42f8b7c8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It was only set by accident. `-gnatg` is a special mode for GNAT
internals and libgnat (we already set it explicitly for the latter).
TEST=Gave libgfxinit a shot on lenovo/t420.
Change-Id: Ie56a95da2dafd014bd6152cb419a2d315e7c78c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We don't output special ADAFLAGS in xcompile but its CFLAGS are
compatible with and necessary for Ada too. So use the latter and
make sure we use them for libgnat too.
Fixes i386 builds with x86_64 toolchain.
TEST=Gave libgfxinit a shot on lenovo/t420.
Change-Id: I0d13f182acfaa9bd1b608edd8a508c4ceedef3b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The original options were named and described under the false assumption
that the chipset lockdown would only be executed during S3 resume. Fix
that.
Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch implements soc override function to calculate reserve memory
size (PRMRR, TraceHub, PTT etc). System memory should reserve those
memory ranges.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.
Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With reset default of the clockgen on this board the SATA clock which
needs to be 100MHz depends on FSB BSEL straps.
This explains why SATA was originally tested to be working but fails
with CPUs operating at different FSB.
This change sets a bit in the clockgen configuration which fixes the
SATA clock.
TESTED on with a 1333MHz FSB CPU.
Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Generating a project file list used to do a rebuild of the project.
Instead, just make sure there's a coreboot.rom file present and if
it is, generate the list.
Change-Id: I9cc12ef3d1990c3422625630451b2a7b8d77829c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants
Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/banon (Acer Chromebook 15 CB3-531) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new banon variant
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Gardenia (with Stoney Processor) has a single memory channel, not two.
This corrects DMI type 17 reporting and the memory clear functions.
Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21602
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once w83627hf_set_clksel_48() is unified into
winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()),
this file is no longer needed and can be dropped.
Build tested on select affected mainboards.
Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The System Control Interrupt is routed per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI configurable on Apollo Lake.
Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable LTR for Root port 0, where wifi card is connected.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are a lot errors reported by AER driver for root port 0.
The erors are being caused by an unsupported request from the
device to the upstream port. Enabling LTR on the root port stops
these errors, it is because LTR is enabled on the device side but
not on the root port and hence root port was logging the LTR messages
from the device as unsupported.
The PCIe base spec (v3.1a) section 6.18 also states that:
LTR support is discovered and enabled through reporting and control
registers described in Chapter 7. Software must not enable LTR in an
Endpoint unless the Root Complex and all intermediate Switches indicate
support for LTR. Note that it is not required that all Endpoints support
LTR to permit enabling LTR in those Endpoints that do support it. When
enabling the LTR mechanism in a hierarchy, devices closest to the
Root Port must be enabled first.
If an LTR Message is received at a Downstream Port that does not
support LTR or if LTR is not enabled, the Message must be treated
as an Unsupported Request. FSP has a UPD for enabling/disabling
LTR on root port, use the same for configuring LTR on PCIe root ports.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's helpful to use the common vbnv_reset() function to
initialize the vbnv contents when backing store failures occur.
Therefore, allow that to happen.
BUG=b:63054105
Change-Id: I990639e8c163469733fdab0d3c72e064acc9f8d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to early_pch_common.c and
add a helper function to determine if failure occurred.
BUG=b:63054105
Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ic4bf99dc3a26fbc3bd508e484963b9298ef1b24b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I1d90cc557225ddbba1787bf95eae0de623af487e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I88bf9bdba8c1f3a11bc8301869e3da9f033ec381
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21554
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred. In addition actually
provide soc_get_rtc_failed() which properly indicates to the common
code that RTC failure did occur in the cmos_init() path.
BUG=b:63054105
Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ia0a38f00d2a5c7270e24bdd35ecab7fbba1016d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I1b02028a1830ff9b28b23da7a4a1fd343f329f0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add vbnv_init() which is responsible for doing any vbnv initialization
and reading the vbnv contents. Having this function allows for
putting vbnv backing store specific support in the main vboot logic
path.
BUG=b:63054105
Change-Id: Id8f0344e5de5338417ae2e353ae473d6909c860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21550
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of having each potential caller deal with the differences
of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the
correct logic within the callee, cmos_init(), for handling the
vbnv in CMOS. The internal __cmos_init() routine returns when the
CMOS area was cleared.
BUG=b:63054105
Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Linux Pstore area must not be cleared on a reboot. Set the option
to not clear the memory in AGESA.
BUG=b:64193190
BRANCH=none
TEST=Memory clear isn't called in AGESA.
Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21596
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee has a single memory channel, not two. This corrects DMI type 17
reporting and the memory clear functions.
BUG=b:65403853, b:64193190
BRANCH=none
TEST=AGESA DMI reports the correct number of DIMMs.
Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
vboot images come with multiple regions carrying CBFS file systems. To
expedite hashing (from slow flash memory), the FW_MAIN_* regions are
truncated since they typically have pretty large unused space at the
end that is of no interest.
For test purposes it can be useful to re-engage that space, so add a
command that creates a new empty file entry covering that area (except
for the last 4 bytes for the master header pointer, as usual).
BUG=b:65853903
BRANCH=none
TEST=`cbfstool test.bin expand -r FW_MAIN_A` creates a new empty file of
the expected size on a Chrome OS firmware image.
Change-Id: I160c8529ce4bfcc28685166b6d9035ade4f6f1d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21598
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Fix typo in comment
- Aphabetize package list and put each package on a single line
- Add environment variables into coreboot user's .bashrc file
- Add openssl, qemu, and shellcheck to installed packages
Change-Id: I37771be5d3ecaa61d76d99e689b422144a6d7dc6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/21582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
- Update checkpatch.pl to version 0547fa58
(checkpatch: add 6 missing types to --list-types)
- Update spelling.txt to version d9f91f8
(scripts/spelling.txt: add a bunch more spelling mistakes)
- Fix an additional unescaped left brace in a regex - causes warnings
in new versions of perl.
Change-Id: Ic443099e90a46280f18d58799afc72d00dc83793
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/21581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch outputs decoding errors with BIOS_WARNING instead of
depending on CONFIG_DEBUG_RAM_SETUP.
Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK
and doesn't try to create a valid setting if an invalid setting is
detected.
Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.
This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If results are uploaded the temporary directory in which they are
stored gets deleted, yet we currently point to the deleted directory in
the output.
This patch fixes it so that we point to the actual location in the local
repository where uploaded results are found.
Change-Id: I1f42c3296ec1d19fcfa4911307e07e67de289895
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The ACPI spec requires devices with children to have an HID,
and Windows enforces this strictly. Without the SIO device
having an HID, Windows will not detect the attached PS2 keyboard
and trackpad. Therefore, add the proper HID.
TEST: boot Windows on google/stout, observe PS2 keyboard and
trackpad detected and functional.
Change-Id: I61d7341c15483f8e1fe0e485a25591ceb92eaae1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
TEST: boot Windows on google/stout, observe battery data
reported correctly.
Change-Id: I974afcd6ff1c617301d0897d6bd1fe14200aa3b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
EC ACPI code is calculating the drain rate, but does not store it
in the battery status package before returning it. Correct this
omission, and set the drain rate to a preset minimum if calculated
value is less. Taken from vendor firmware ACPI dump.
Change-Id: I52837d5879112ab3103976bda28906fac8f880ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable
tells the ME to stop execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME reports opmode = 2.
This means the ME will not respond when we wait for an acknowledgement
about the DRAM being ready. The current code waits 5 seconds for a
response, that in this case, never comes.
If the ME is reporting opmode 2, don't delay or wait for a response
from the ME.
Tested on my X220, this patch fixed the five seconds before the payload
executed. Verified using the timestamp patch.
Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add find_fcba(), find_frba(), find_fmba(), find_fpsba()
and find_fmsba() to replace those copy-pasted addressings.
This commit is one separated from the original I6d05418c.
Change-Id: I98965711e4cb9792e5cc86cc4c1035559e0274f5
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Redesign some array-like structures as true arrays,
and rewrite functions to dump them as loops.
This commit is one separated from the original I6d05418c.
Change-Id: I161c9a2ae83d26e658d67d0804e943fff95fe076
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is no reason to keep a separate region_filenames array,
so I merge it into region_name(s).
This commit is one separated from the original I6d05418c.
Change-Id: I38489c6d3b3c161e9b0281188e6cdd0b62e38335
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21509
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Const-correct some functions which do not write back,
and use pointers to access existing region_t variables.
The last changeset is dismantled this time.
This commit is only focused on const-correctness.
Change-Id: I6d05418c8b32fa31dcd038a3e56f9aefe13fa9c4
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21288
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.
BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.
Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set keyboard backlight to 75% on boot, except when resuming
from S3. This enables the backlight at a reasonable level
prior to the OS driver taking over, providing early proof-of-life
and enhanced usability in grub etc.
Uses same method as other google boards with a keyboard backlight
(chell, link, samus). 75% value determined based on user feedback.
TEST: boot google/lulu,gandof boards, observe keyboard backlight
enabled in pre-OS environment.
Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the git:// protocol is unencrypted and unauthenticated, there's a
security risk associated with using it: A man-in-the-middle attacker
could replace e.g. the master branch with malicious code.
Mitigate this risk somewhat by cloning GRUB2 via HTTPS.
Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add support for google/reks (Lenovo Chromebook N22/N42) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new reks variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-reks-7287.133.B,
commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
variants other than cyan
Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data
Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add EC entries into chromeos.fmd file.
BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in
coreboot does not match intel flash map generated from fit.
Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sometimes the BUG/BRANCH/TEST metadata isn't separated by a newline
from the later git/gerrit metadata, which messes up further processing.
Add that newline to minimize the amount of human intervention required.
Change-Id: I37171bf6764b64e0ab0e81297a03f4d8b7744256
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To remove chip.h dependency from SGX common code
- Create API soc_fill_sgx_param() and use it in sgx.c
- Implement same API for skylake/kabylake
- define sgx_param structure
Also include intelblocks/sgx.h instead of soc/msr.h
Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.
Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a function to retrieve the elapsed time since boot. For that purpose
use the base time in the timestamp table among with the current
timestamp at call time of the function. So more precise the returned
time is the elapsed time since the timestamp was initialized scaled
in microseconds. This was chosen to get a reliable value even on
platforms where the TSC might not be reset on software reset or warm
start.
Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was originally designed such that if usbdebug_init() was called
before cbmem_initialize(), it would fetch the already-initialized
state from CBMEM. This changed when cbmem_find() behaviour changed
to require cbmem_initialize() to be called first. As a result,
ramstage had to reinitialize all of the EHCI controller and USB
endpoints on entry. This was slow, specially with AMD hardware
where one can scan USB ports to probe for the debug dongle.
For postcar and ramstage, move usbdebug entry such that it is
triggered from CBMEM_INIT_HOOK instead of console_init().
Side-effect of this is usbdebug console shows 'coreboot-xxx ...
starting...' line only for romstage.
Initialisation for usbdebug is never done in postcar. If you have
USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on
usb either.
While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE
and alike.
Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
An internal index `i` was previously allocated as
Elf64_Half which is uint16_t. Bumping to uint64_t
increases the number of allowed symbols and prevents
a segfault in processing a larger ramstage.debug file.
Also introduce a separate counter for the number of sections.
Change-Id: I9ad2f64c452cef2e7bf957f766600891cb5ae798
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
To avoid error with symbol redefinition (using clang):
src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition
".global find_fsp\n\t"
Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp.
Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fine tune usb 2.0 strength for port 4 to pass eye diagram.
BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.
Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Stoney Ridge APU can never be used in a multi-node system. Reduce
the feature set to a single node.
Remove the static variables for each D18Fn device and replace the routines
with coreboot config read and write functions.
Strip down domain_set_resources() to consider only a single node. A
follow-on patch will further simplify this.
Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the check for the southbridge link from Stoney Ridge. The APU
is an SoC which can never be installed in a multi-node system. It is
pointless to detect and remember the sblink value, which is set by
hardware and comes up 0. The BKDG marks this as a reserved field vs.
documentation for multi-node-capable Family 15h devices.
Because there is only one option for SB link now, relocate the register
write done by set_vga_enable_reg() and remove the function.
Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits. The code has no effect on modern
Family 15h APUs. The bits being modified come up set out of reset.
Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to
HAVE_SMI_HANDLER.
Change the value returned by cbmem_top() to carve out a range to be
used by TSEG. The SMM Mask register has a granularity of 128KB but
align the value to 16MB to keep down the number of variable MTRRs
required.
Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EC needs to have command to set SKU ID from APU to support
specific feature (ex: keyboard backlight) for variant board.
BUG=b:65359225
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8cd3b8f646d4134d6bfff2869f6df2d9c615c157
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS
macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress
for ACPI debug prints.
TEST= Build and boot soraka and fetch the ASL debug prints.
Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes coreboot set VBSD_EC_EFS flag if CONFIG_VBOOT_EC_EFS
is set. Depthcharge/Vboot uses this flag to determine whether it can
update EC when it's already running a RW copy.
BUG=b:65028930
BRANCH=none
TEST=Verify soft sync runs successfully on Fizz.
Change-Id: Ic51ddd4819262162a8d8519461c4ace57ee01cb5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21489
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 3f3a496a 2017-09-01 09:20:19
(image_signing: Fix loem.ini pattern for unibuilds)
to commit id 753e34e9 2017-08-31 10:12:40
(futility: Make rwsig sign command produce EC_RW image)
This brings in 5 new commits.
This also updates Depthcharge stable commit ID.
Updating from a843f262 2016-08-16 08:41:04
(kahlee: select emmc boot first if available)
to commit id f3bb31fe 2017-08-15 17:15:33
(vboot: Support EC early firmware selection)
This brings in 14 new commits.
Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This board uses the reset defaults for DxxIP and DxxIR.
The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family"
mistakenly says in the D31IP register that all function have INTB as
default. This is however not true as documented in the reset default
value.
This fixes the DSDT such that the SMBus device gets a route for the
INT C interrupt it uses.
Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21442
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.
For amd/inagua, the defined function was actually initial
GPIO programming.
For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.
Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because cpu/intel/car/romstage.c assumes a 8KiB stack size
when setting up stack guards, and all Slot 1 compatible
CPUs have enough L1 cache available for the increase.
Adjust DCACHE_RAM_BASE to match.
Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz
Tualeron. The latter actually requires this patch to boot
successfully.
Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE
and CONFIG_DCACHE_RAM_SIZE for consistency.
Do not set %ebp before and switch directly to stack returned by
romstage_main().
Remove an unneeded 4-byte gap in CAR stack.
The caching strategy for flash XIP area should be WRPROT.
Clarify the various comments in the file on the logic.
Together they lay the groundwork for bringing EARLY_CBMEM_INIT to
intel/slot_1 boards.
Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21503
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for detecting WWAN.
* Allows to turn off power to WWAN if no card is installed.
Add the following devicetree values:
* has_wwan_detection
Set to one to indicate that the following register are sane.
* wwan_gpio_num
SB GPIO num to read.
* wwan_gpio_lvl
SB GPIO level for card to be present (usually zero).
Don't enable WWAN power if no card is detected.
As there are no devicetree values yet, the new code doesn't have any effect.
Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.
Needs test on all boards.
Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
CONFIG_MAINBOARD_VENDOR is customizable by OEM for Chrome OS
devices. However, VBOOT_FWID_MODEL indicates the firmware vendor and
hence if CHROMEOS is selected, then VBOOT_FWID_MODEL should always
prefix "Google_" instead of CONFIG_MAINBOARD_VENDOR.
BUG=b:65493192
Change-Id: I0a2280bfd6d535586bc14d9a3c4a8198287f08bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig.
- Remove 2nd set of variables that are duplicates of the first set.
- Delete duplicate set of Prerequisites
Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21451
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Adapted from Chromium commit 9756af8.
Add SOC helper to identify BSW SoC stepping. Will be used to
override USB2 phy setting based on stepping in subsequent commit.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.
This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).
TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).
Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the common acpi code.ACPI code is very similar
accross different intel chipsets.This patch is an effort to
move those code in common place so that it can be shared accross
different intel platforms instead of duplicating for each platform.
We are removing the common acpi files in src/soc/intel/common.
This removes the acpi.c file which was previously in
src/soc/common/acpi. The config for common acpi is
SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's
Kconfig file in order to use the common ACPI code. This patch also
includes the changes in APL platform to use the common ACPI block.
TEST= Tested the patch as below:
1.Builds and system boots up with the patch.
2.Check all the ACPI tables are present in
/sys/firmware/acpi/tables
3.Check SCI's are properly working as we are
modifying the function to override madt.
4.Extract acpi tables like DSDT,APIC, FACP, FACS
and decompile the by iasl and compare with good
known tables.
5.Execute the extracted tables in aciexec to check
acpi methods are working properly.
Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch implements soc function to get previous sleep state
using chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.
Without the workaround, raminit fails on soft resets.
Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.
Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.
Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously the random seed was fixed, which led to the same sequence of
blocks for each run.
Now that libpayload has time(), no change is needed in the function
rand_init() of tint.
Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This recovers FCH configuration on S3 resume path.
Appearst to work, but other defects of HAVE_ACPI_RESUME
must be fixed also before S3 support is re-enabled.
Change-Id: I8d07d2e9dc161b67d854fcc8ec1da1f36900f989
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/
There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
a warning which points the user at LATE_CBMEM_INIT, if such a board is
selected.
Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.
Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Inspired by gm45 code, which sets this value the same way.
Some values for tRD on 800 and 1067MHz FSB were set wrong because the
CAS/Freq selection was wrong. CAS was often selected to low and when
fixing CAS this results in tRD being too high, due to an incorrect
lookup table which caused instability.
PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5
on GA-945GCM-S2L.
Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Include Makefile from site-local even in absence of DOTCONFIG.
This will allow execution of Makefile option from site-local in absence of
DOTCONFIG as well.
Change-Id: I62d1562687ffe18546add80fdde1196700a65236
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/21303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Cherry-pick from Chromium 414024e.
Update the FSP 1.1 header to version 1.1.7.0, required for
susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices.
As this header update doesn't shift offsets, only adds new fields
in previously unused/reserved space, it should not negatively impact
existing boards built against the older header version.
Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add support for detecting BDC.
* Allows to turn off power to BDC if no card is installed.
* Should fix https://ticket.coreboot.org/issues/99 .
Add the following devicetree values:
* has_bdc_detection
Set to one to indicate that the following register are sane.
* bdc_gpio_num
SB GPIO num to read.
* bdc_gpio_lvl
SB GPIO level for card to be present (usually zero).
Don't enable BDC power if no card is detected.
As there are no devicetree values yet, the new code doesn't
have any effect.
Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
We now require EARLY_CBMEM_INIT and romstage_handoff to
support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would
never call an externally defined acpi_get_sleep_type().
Name _sleep_type() was also inapproriate here, as it referred
to hardware-dependent SLP_TYP field of PM1CNT but still
returned ACPI_Sx value instead.
Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This changelist adds the capture format to be set for max98927. The
nhlt blob is the same but the format params for capture are different
from the render.
BUG=b:36724448
TEST=IV feedback data is of good quality
Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.
With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.
PMIC will be reset in first boot & across S3 & S0ix cycles.
Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.
BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera
Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat-
forms now. The SPI controller is initialized at start of BS_DEV_INIT
(dev_initialize()).
The SPI lockdown usually shouldn't be a problem but the SPI driver imple-
mentation lacks full support for the locked interface. Also, some options
exist to lock all flash regions read-only until the next reboot.
Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.
The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.
Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Add a missing line-break escape and, rather cosmetic, guard execution of
$CXX which we allow but don't force to be set.
Change-Id: Icf6d3b7de4b7999b8214489f28997964c490d1e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21307
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
The MPC.HPCE bit of the ExpressCard root port is not set in vendor
firmware, so autoport didn't generate the right pcie_hotplug_map to
support ExpressCard hotplug.
Also add comments for each PCIe root port.
Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/21310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The addr32 prefix is required by binutils, because even when
given an explicit address which is greater than 64KiB, it will
throw a warning about truncation, and stupidly emit the opcode
with a 16-bit addressing mode and the wrong address.
However, in the case of LLVM, this doesn't happen, and is happy
to just use 32-bit addressing whenever it may require it. This
means that LLVM never really needs an explicit addr32 prefix to
use 32-bit addressing in 16-bit mode.
Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Jenkins is giving warnings due tainted variables from the environment
and command line:
Insecure $ENV{PATH} while running setgid at util/lint/checkpatch.pl line
907, <$conststructs> line 39.
Insecure dependency in piped open while running setgid at
util/lint/checkpatch.pl line 907, <$conststructs> line 39.
This should fix those warnings.
Change-Id: I6a09915d13547bf9a86c011d44cbcd39c46f3fec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Without this remapping code enabled, the system fails to boot properly
if the amount of ram inserted is larger than 4G minus the mmio
space (hardcoded to 1G here).
Change-Id: I02e7ceed0cd9db7eb7182481b6989f80cef31ee5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,
*** CID 1380036: Control flow issues (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>> CID 1380036: Control flow issues (NO_EFFECT)
>>> "i" is converted to an unsigned type because it's compared to an unsigned constant.
80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81 if (config->PcieRpEnable[i])
82 mask |= (1 << i);
Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix dump_pci_device() broken by commit 65b72ab5 (Drop print_ implementation
from non-romcc boards) in 2015 (!) where only one in 16 bytes were being
dumped.
Also remove the #if made redundant by commit aef8542 (Compile debug.c
only if CONFIG_DEBUG_RAM_SETUP) as this whole file is only compiled in
that case.
Also clean up headers that were included twice.
Change-Id: I60e272b29417039feb15540e49d7300f86e5ed21
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch has been provided by Mentor Chih-Chyang Chang
on behalf of Andes Technology. It fixes using the coreboot
toolchain to compile the Chrome EC code base on the ITE8320
embedded controller.
The new patch incorporates a fix for the issue previously
fixed by patches/gcc-6.3.0_nds32.patch, so that patch can
be removed.
patches/gcc-6.3.0_riscv.patch needs to be slightly adjusted
to still apply cleanly (configure scripts only).
Change-Id: I0033888360f13ba951b692b3242aab6697ca61b3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot cannonlake RVP successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
6. Enable C6 DRAM with PRMRR size 0MB and boot to OS.
Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses smm common library function to get tseg base
address and size. Hence removing definitions of smm_region()
from soc directory.
BRANCH=none
BUG=b:63974384
TEST=Build and boot reef successfully.
Change-Id: I091ca90cf576c0da35cf3fe010f8c22a18ef82d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses system agent common library to
know tseg region start and size. Unable to remove smm_region()
function from soc code as SMM common library
is not yet available for skylake use.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: If98b65805753db2c30d6fea29e401a17cef39799
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario.
Also, remove DVS support for CENTERLOGIC.
BUG=b:64702054, b:63537905
TEST=build coreboot
Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/21176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enabling XHCI is additionally controlled with Kconfig
option HUDSON_XHCI_ENABLE. Even when it is enabled,
it EHCI debug works on the USB port next to the
DVD drive door.
Change-Id: I83738da6015f58ecd0819c553d333a176365dc78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Support code for Trinity and Richland is identical now.
I have also come across a unit with Trinity model CPU,
whose CPUID was not listed in f15rl while f15tn already
had support for f15rl.
Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
LLVM AS doesn't support as much GNU junk extensions, data16/32
is almost never needed in truth if we just use the correct op
suffix. So do that here, fixes clang/llvm builds with the
integrated-as toggled on.
Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is at least one I2C device (being used by Soraka) that has 3
controls -- enable, reset and stop. If the stop gpio is not put into
the right state when turning off the device in suspend mode, then it
causes leakage. Thus, we need control in power resource to be able to
stop the device when entering suspend state.
BUG=b:64987428
TEST=Verified on soraka that touchscreen stop is correctly configured
on suspend.
Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21249
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update cyan's SPD-related functions to more closely mirror
those of other Braswell boards, in order to simplify the upcoming
baseboard/variant setup for Braswell ChromeOS boards.
TEST: boot google/cyan, observe SPD correctly identified in
cbmem log, RAM-related data correct in SMBIOS tables.
Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.
It also features a mask to only touch certain bits of the clockgen.
TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.
Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch to add helper function to get SMM region start
and size based on systemagent common library.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: If10af4a3f6a5bd22db5a03bcd3033a01b1cce0b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to add helper function to get tseg memory base and
size for HW based memory layout design.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a 16ms delay to DMIC init by the kernel driver in order to
prevent an audible 'pop' noise when starting to record.
BUG=b:63413023
TEST=manual testing to ensure this device property is present in SSDT:
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package () {
Package () {
"realtek,dmic-init-delay",
0x10
}
}
})
Change-Id: If9160ce6992153ba49719029de336595bbf4ae72
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for providing additional free form device properties via
devicetree in order to make this driver suitable for kernel drivers
that need additional board-specific device properties.
This currently allows adding up to 10 additional properties to a device.
BUG=b:63413023
TEST=manual testing to ensure that newly added properties are in SSDT
Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide a new function that will allow adding arbitrary properties
to devicetree entries without needing a custom driver for the device.
This will allow the 'generic i2c' driver to support kernel drivers
that need additional device properties exposed and have those board
specific properties set with values from devicetree.
BUG=b:63413023
TEST=not used yet, compiles cleanly
Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21269
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On platforms with a PCH, some registers within host bridge should be
locked down on each normal boot path (done by either coreboot or
payload) and S3 resume (always done by coreboot).
A function to perform such locking is implemented in src/northbridge/
intel/*/finalize.c, and is designed as the handler of an #SMI triggered
with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only
triggered during s3 resume, and not on normal boot path. This problem
has beed discussed in
https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html .
This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/
intel/common/Kconfig is added to control the actual locking, which
depends on several compatibility flags, including
"HAVE_INTEL_CHIPSET_LOCKDOWN".
In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint"
have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected.
The change is only well tested on Sandy Bridge, my Lenovo x230.
Change-Id: I43d4142291c8737b29738c41e8c484328b297b55
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The EC side of the feature bits in ACPI EC space isn't stable yet, and
we're now going for matching them up with the EC host command of the
same purpose.
Change-Id: I9c1f0e5390e840ea0c32315a3da8eea6f3e12f54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We never had a board in the tree that implements this.
If you are interested in implementing such board, note
that also f12 and f14 had copies of the same refcode.
As part of the sourcetree cleanup it was not studied
which was the most up-to-date one for AM3r2.
Change-Id: Ic7dd065c0df08c22af6f3a2dcfc7ff47d6283a46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
"pcie_port_coalesce" will cause pcie being remapped under certain
conditions, but flags within "pcie_hotplug_map" should be updated
along with ports.
Test on my lenovo t430s.
Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21178
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is a bug introduced by this commit:
stoneyridge: Fix CPU ASL \_PR table [commit I870f81]
The following error is found in dmesg
ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND...
ACPI Exception: AE_NOT_FOUND, During name lookup/catalog...
ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table...
ACPI Error: 1 table load failures, 3 successful...
...
acpi-cpufreq: overriding BIOS provided _PSD data
And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work
The cause is that the Pstate SSDT table generated by AGESA expects CPU
variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot.
Use Kconfig to set the required string.
BRANCH=none
BUG=b:64885241
TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/
Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot
Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The guards in the header files were inconsistent. Some had no leading or
trailing underscores, some had one, some had both leading and trailing.
Change all to double leading & trailing underscores.
Change all comments to have a space before them instead of tabs
BUG=b:62235990
Test=Build Kahlee
Change-Id: I4466df529ab201c922096a31d7438381778b582f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
What is present is APIC and legacy interrupt routing and the soft-off sleep
state. Other sleep states are missing, so are the SuperIO devices.
Boots Linux with and without "noapic" and a Windows XP (installed with
factory BIOS, the installer reportedly requires legacy keyboard).
Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.
Copied from mainboard/bcom/winnetp680 which seems to be a similar
board with an extra PCI slot.
The p680 should probably be moved to winnet/ too, since the board is an
OEM WinNET board, with BCom being just a machine that happens to it.
Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Includes objects for interrupt links, the LPC bridge and interrupt
routing tables for the internal devices for both APIC and legacy
modes.
The default routing tables only includes peripherals internal to the
VT8237R, if a mainboard has PCI slots (mine does not have), it needs to
supply its own routing table.
Change-Id: I3a0cdafc19159fe6c38e4dde08ad0bf2bd0dd6b8
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch ensures skylake device using FSP1.1 can use HW based
DRAM top calculation which was broken due to skylake fsp1.1 not
honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size.
This WA is not needed for FSP2.0 implementation due to
PrmrrSize UPD is available and considering into hw based dram top
calculation.
BRANCH=none
BUG=b:63974384
TEST=Build and boot lars which is using skylake 1.1 fsp.
Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.
I2C0: 375 - 400
I2C1: 377 - 400
I2C2: 377 - 400
I2C4: 375 - 397
I2C5: 375 - 397
Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for board specific critical and passive
limits using GNVS table. Use default values if no
board specific limit exists.
* Add ACPI methods _TZP, _TSP and _PSV.
* Update ACPI method _CRT to use board specific if available.
Tested on Lenovo T500.
Change-Id: If438a909f4415f50cd7a764fb5fba7ec29599606
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch to ensure that coreboot is able to store memory
training data into SPI and perform platform lockdown after
PCI enumeration is done before handing over control to
NotifyPhase() - Post PCI enumeration.
Modified coreboot bootstate execution order below:
BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI
BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration
BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration
TEST=Please find test case and results for Chrome Devices as Apollolake- Reef,
Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS.
1.
Without patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Chrome CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
2.
With patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Yocto CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there
is no noticeable difference.
On a reboot, suspend resume from Chrome console, the mrc cache is found,
and utilized.
Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing SPI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence SPI lock down programming has been moved
right after pci resource allocation is donei, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS
bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set.
Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing DMI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence BIOS Interface lock down through Sideband
access has been moved right after pci resource allocation is done,
so that BILD lock down is getting executed along with LPC and SPI
BIOS interface lockdown settings before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure DMI register offset 0x274c bit 0 is set.
Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The LED polarity was set incorrectly, fix using values derived
from original Chromium sources:
branch firmware-mccloud-5827.B, ToT
src/mainboard/google/mccloud/smihandler.c
src/mainboard/google/mccloud/romstage.c
TEST: boot google/mccloud, observe power LED on normally,
blinking in S3/S4, and off in S5.
Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Cherry-pick from Chromium commit a162348.
Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.
Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit 1138727.
Elan touchscreen driver expects the first gpio resource in asl
to be the reset line.
The driver considers the gpio based irq line as reset gpio resource
and changes the direction to output.
This will cause irq registration to fail.
Solution is to pass Interrupt resource for touchscreen irq
instead of GpioInt.
Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit e49deb1.
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is board
specific.
Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing PMC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence PMC register lock down has been moved
right after pci resource allocation is done, so that
PMC registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.
Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing LPC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence lpc register lock down has been moved
right after pci resource allocation is done, so that
lpc registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure LPC register 0xDC bit 1 and 7 is set.
Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures that MRC cache data is already written
into SPI chip before SPI protected regions are getting locked
during BS_DEV_RESOURCES-BS_ON_EXIT.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence storing mrc cache data into SPI has
been moved right after pci enumeration is done, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure MRC training data is stored into SPI chip and power_
Resume autotest is passing.
Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017:
(ps8751: enable software sync.)
to commit id a843f262 - Wed Aug 16 23:37:52 2017:
(kahlee: select emmc boot first if available)
This brings in 20 new commits.
This matches with the updated vboot submodule.
Change-Id: If030bc3e75dd470838590540880213bd841154b8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)
to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)
This brings in 6 new commits.
Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change provides interface to override dev tree settings per
board due to many projects share same devicetree.cb.
BUG=b:64880573
TEST=Verify that dev tree settings can be overridden in mainboard
on coral
Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.
This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".
Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.
Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.
Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This enables adding the backlight driver to boards that may or may not
come with a keyboard backlight function.
It's the responsibility of the EC to report if that feature exists, but
that's not a big extra burden given that it already keeps track of
everything else related to the backlight.
BUG=b:64705535
BRANCH=none
CQ-DEPEND=CL:620595
TEST=configured KBLE manually and noticed the presence/absence of
/sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel,
corresponding to the value reported by the EC.
Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.
This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.
So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.
BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.
Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Passing a string containing output from strerror() to perror() causes
double error message display. It is also causing segfaults when the
error message is longer than temp_string capacity.
To fix the problems, sterror() call has been removed so the error
message is printed only once. This could be enough to avoid segfaults,
but it is a good practice to limit output size with snprintf().
Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To correct the SGX init sequence; PRMRR on all cores first
needs to be set, then follow the SGX init sequence. This
patch would refactor the common SGX code (and add needed
checks in the init sequence) so that SOC specific code can
call SGX init in correct order.
Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.
Build tested on select affected mainboards.
Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested:
- i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2
- debug output from serial port, EHCI debug port not found
- Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload
- all PCI and PCI Express slots
Issues:
- sometimes the machine fails to boot, with serial debug output it can
be seen it stucks after SMM initialization, and more likely to fail
to boot when serial cable is attached
- no S3 resume (not tested in vendor firmware)
Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add two additional LED IDs.
Add Kconfig menu entries to allow selecting the action
to execute on death.
Overwrite weak die_notify method to notify user on death.
Flash all LEDs and play beep code 10 depending on Kconfig
options.
Successfully tested on:
Tested on Lenovo T500.
Tested on Lenovo X200.
Tested on Lenovo T430, but only LEDs are flashing.
Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8
Signed-off-by: Patrick Rudolph <siro@das-labor.org
Reviewed-on: https://review.coreboot.org/19695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add mp_current_microcode() function to get the microcode patch pointer.
Use this function to avoid reading the microcode patch from the boot
media. init_cpus() would initialize microcode_patch global variable to
point to microcode patch in boot media and this function can be used
to access the pointer.
Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relevant changes (commit 2e8761e):
* Add an option to truncate the ME image file
* Add full support for Skylake (ME 11) and following, including
modules removal, truncation informations and partition
relocation
* Add two options to generate a shrinked ME image file and the
corresponding descriptor with a modified flash layout
* Update README.md
* Bug fixes
Also add a link to the usage guide in the Kconfig help.
Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clear LAST_BYTE flag at beginning of block commands.
For reads, slave device determines in the message format how
many bytes it has to transfer out, host firmware only dictates
the maximum buffer length. Return SMBUS_ERROR if only
partial message was received.
For writes, return SMBUS_ERROR if length > 32.
For writes, fix off-by-one error reading memory one
byte past the buffer end.
Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On this device libgfxinit successfully initializes textmode and
framebuffer mode on the device connected to the HDMI1 port.
VGA port is not tested, due to lack of VGA with valid EDID.
Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1.
Due to limitations within the libgfxinit's current build system,
it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is
PCH instead of CPU for which libgfxinit should be configured here.
Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fail at build-time if one of the following happens:
Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.
Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.
Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.
BUG=b:64811381
Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Do not use the global platform_i2c_transfer() function that can only be
implemented by a single driver. Instead, make a `struct device` aware
transfer() function the only interface function for I2C controller dri-
vers to implement.
To not force the slave device drivers to be implemented either above
generic I2C or specialized SMBus operations, we support SMBus control-
lers in the slave device interface too.
We start with four simple slave functions: i2c_readb(), i2c_writeb(),
i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec-
tive SMBus functions. But we keep aliases because it would be weird to
force e.g. an I2C EEPROM driver to call smbus_read_byte().
Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code is based on autoport. I'm using a machine with discrete GPU,
and gfx.* in devicetree.cb is from 2760p.
It can be debug with serial port on dock.
Tested:
- CPU and memory: i5-2540M, 4G+0
- Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted
from vendor UEFI firmware)
- USB ports
- SD card reader
- WLAN
- DP display
- S3
Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is based on autoport. The EHCI debug port is the upper USB
port beside the battery.
Tested and working:
- CPU and memory: i7-3720QM, 4G+4G
- Linux Mint with Linux 4.4 (SeaBIOS payload)
- All USB ports
- ExpressCard
- WLAN
- AC and battery status
- S3
- Other devices detected: DVD drive, smartcard reader, fingerprint, bluetooth
Not tested:
- VGA and DP
- Ethernet and modem
- Dock
Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is based on the code generated by autoport.
The EHCI debug port is between the DP port and eSATA port.
The serial port on dock can also be used for debugging.
The model with discrete graphics is not tested.
Tested and work:
- memory: 0+4G, 4G+0, 4G+4G
- Linux (Arch Linux with kernel 4.10.6) boot from SeaBIOS payload
with native graphics init
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- AC and battery status
(EC) blobs:
This laptop uses SMSC KBC1126 EC, and there are two blobs needed by it.
You can use the tools in util/kbc1126/ to extract them and insert them
to the coreboot image using the following configuration:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: Icbc051e2272b8ea73627940db15a56901d737472
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is generated by autoport.
The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.
Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- SD card reader
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
- AC and battery status
Issues:
- Wacom digitizer does not work (even after I add it in DSDT)
- GRUB payload will freeze (in all Elitebooks, including chainloading GRUB
from SeaBIOS)
Things that are not tested:
- smart card reader
- cable modem
(EC) blobs:
This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds few helper functions in CPU common libraray code
which are mainly needed for ACPI module. The functions those are
moved to cpu common code is removed from common acpi files.
TEST= System boots properly and no regression observed.
Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21051
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Chrome OS systems rely on the write status register to enable/disable
flash write protection and disabling this opcode breaks the ability
to enable or disable write protection with flashrom.
Add a configure option for this feature that will disable the opcode
for Write Status commands unless CONFIG_CHROMEOS is enabled.
Tested to ensure that a default build without CONFIG_CHROMEOS has this
option enabled while a build with CONFIG_CHROMEOS does not. Also
ensured that when this option is disabled (for Chrome OS) then flashrom
can be used with the --wp-enable and --wp-disable commands, depending
on the state of the external write protect pin.
Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/21021
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.
This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.
Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove cpu.h from the cache-as-ram setup and teardown files that rely
on the FSP implementation. The struct device statement causes a
build failure and there appears to be nothing needed from cpu.h in
the two .S files.
TEST: Build Google Reef with FSP_CAR selected on Chipset menu and add
FSP binaries on the Generic Drivers menu.
Change-Id: I560b730c18d7ec73b65f2e195b790e7dcacfd6bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21057
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16
are the industrial standard electrically erasable programmable
read only memory (EEPROM's) and this patch adds ACPI objects
and power resources for NVMEM device.
Update DOVD method to set sensor IO LDO voltage and remove repetitive
code from OVFI, VCMP and NVMP power resources.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Read the NVMEM content via sysfs interface.
Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We do not need or use the Management Engine MBP HOB so that
step can be skipped when FSP initializes the ME.
BUG=b:64479422
TEST=boot with FSP debug enabled binary and ensure that the
output indicates this step is being skipped:
Skipping MBP data due to SkipMbpHob set!
Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/20951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The final newline check is taking longer than we'd like to run. Since
it runs on every commit as part of the pre-commit check, we want that
to run faster than it currently does.
Remove LINT_SKIP_NEWLINE_CHECK as it's no longer needed.
Change-Id: Ie945dd6caba84e0d23af499d43367d70b1696089
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current signed-off-by check doesn't really work well as a lint
stable test being run by the pre-commit git hook. This test looks
at the PREVIOUS commit instead of the staged commit, which works well
on the server. In looking for a way to check the staged commit message,
I found the commit-msg hook, which is the correct way to check the
staged message.
- Update the commit message check from a lint-stable test to a
lint-extended test.
- Add the check for signed-off-by to the commit-msg hook
Change-Id: I8be8aef25730d988c7cf1586ae66ecb839d5f756
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Due to low-memory corruptions S3 support has now been
(at least temporarily) removed from AGESA platfroms.
Should we bring it back one day, CAR teardown on S3 path
will happen with an empty stack so ugly backup/recovery
of the stack will no longer be used.
If S3 feature is brought back, resume path code for FCH
will also see partial rewrite and agesawrapper.c file
will not be part of that.
Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
A decision has been made that boards with LATE_CBMEM_INIT
will be dropped from coreboot master starting with next
release scheduled for October 2017.
As existing implementation of CAR teardown in AGESA can only
do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former.
ACPI S3 support may be brought back at a later date for
these platforms but that requires fair amount of work fixing
the MTRR issues causing low-memory corruptions.
Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch fix the dependency for PMC common block code.
PMC block use SLP_TYP macros and acpi_sleep_from_pm1
function which is defined in arch/acpi.h and guarded
by CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES. So we need
PMC common block to depend on that config for proper
inclusion.
Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20964
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides the option to use the common CPU
Mp Init code by selecting a Config Token.
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config token can be
selected to use the Common MP Init Code, also where CPU MP Init is
done before FSP-S Init.
And if the config token is not selected, the old way of
implementation will exist, where MP Init is been done after
FSP-S.
CQ-DEPEND=CL:*397551
BUG=none
BRANCH=none
TEST=Build and boot Reef
Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581
Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We were explicitly passing CC and TARGET_CC to configure but overwrote
that decision later by passing CC (with the value of TARGET_CC) directly
to a recursive make call. The latter overwrite was introduced because
`unexport` alone doesn't work on variables that were specified on a make
command line (they are added to MAKEOVERRIDES and passed to further re-
cursive make calls).
Instead of unexporting random variables, unexport those that were actu-
ally passed from payloads/external/Makefile.inc and clear MAKEOVERRIDES.
Do not pass OBJDUMP as that is nowhere to be found in the GRUB sources.
And, last but not least, add --disable-werror because building GRUB is
very susceptible to changes in the flex version.
Change-Id: Iaff2c72e89a5a540fe365eacb84811d5cff9d4d4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
this adds convenience definitions for MSECS_PER_SEC, USECS_PER_MSEC,
and USECS_PER_SEC along the lines of the time units in coreboot's
<timer.h>.
Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
- Add lint-extended as a valid option
- Call lint-extend from what-jenkins-does and test-lint
- When logging to a junit.xml file, name the file extended-junit.xml
so it doesn't conflict with the stable junit.xml file.
Change-Id: I7e4156844b8c60790e03a0e43564610bb0c8f386
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call weak method die_notify.
The method should be overwritten in mainboard directory to signal that
a fatal error had occurred. On boards that do share the same EC and where
the EC is capable of controlling LEDs or a buzzer the method can be
overwritten in EC directory instead.
Tested on Lenovo T500.
Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19696
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This allows the use of the native VGA init on boards featuring DVI-I
ports. Digital output is not supported.
Change-Id: I11a4dd68746e06c7e27ecf3e765bdd0d8cf40515
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These Kconfig options can be reused for the same purpose of selecting
the correct i2c pins for probing the analog output EDID in C native
graphic init. For this purpose this patch makes those options
independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT.
Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Copy from chrome-ec codebase, except for keeping the long-form license
header.
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20945
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.
Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
- let the coreboot build system insert the two blobs to the coreboot image
- EC and Super I/O initialization
- ACPI support
Tested on 2760p, 8460p, 2570p, 8470p.
Issue:
Kernel gives the following error:
ACPI Error: No handler for Region [ECRM] (...) [EmbeddedControl]
ACPI Error: Region EmbeddedControl (ID=3) has no handler
TODO:
- consider moving the Super I/O initialization code to ramstage, or
reuse the existing sio/smsc/kbc1100 code (if so, how to add the
additional kbc1126 specific functions to sio/kbc1100)
- sort out the ACPI code which is mostly from the ACPI dump of vendor
firmware
- find out why the digitizer in hp/2760p doesn't work
- GRUB payload freezing on all HP Elitebooks may be related to EC
Change-Id: I6b16eb7e26303eda740f52d667dedb7cc04b4ef0
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/19072
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per default, GCC enables -fdelete-null-pointer-checks, which is
harmful and hence we should disable it:
"Assume that programs cannot safely dereference null pointers, and
that no code or data element resides there."
We want to be careful with our stack usage, hence enable
-fconserve-stack:
"Attempt to minimize stack usage. The compiler will attempt to use
less stack space, even if that makes the program slower."
Change-Id: I74eac2b07c986553f79898a2f2e57bbead4223f8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Create a directory patches, and add necessary patches to be applied to
upstream tianocore.
Patches include:
-Patch for no PCI address enumeration
-Patches to enable keyboard input
-Patch to disable serial to speed up boot process.
Patches pulled from https://github.com/MattDevo/edk2.
Additionally, modify tianocore Makefile to apply patches during build.
Change-Id: I4eaa602418995a68753b1ed13af8c6374eaa312f
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently the only testing we had was 'what-jenkins-does' and
'make lint'. While the lint testing is suitable for developers,
the 'what-jenkins-does' target really isn't, as it was designed
specifically for testing on jenkins.
This adds the infrastructure for basic tests that are more suitable
for the developer. Extended tests and improvements will follow.
Add the coreboot-builds directories to .gitignore.
TODO:
- Save/restore .config
- Update test-abuild to use existing COREBOOT_BUILD_DIR variable
Change-Id: I19e1256d79531112ff84e47a307f55791533806f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
In preparation for expanding the testing, move the test targets
out of the top level Makefile.inc and into a separate
subdirectory.
Change-Id: Ie252c7555223f9ce76b54e6f7b66d03f3cf60500
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
Added documentation on how to extract binaries from a ROM image,
including:
- Using ifdtool to extract binaries.
- Using cbfstool to extract binaries.
- Changing menuconfig to use the extracted binaries.
Change-Id: Ia31b01afc66789f95c7d21a0d41b532bc19a6430
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/20753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helper functions required by intel/common UARRT driver for
enabling controller on S3 resume.
BUG=b:64030366
Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20888
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed on a number of platforms (baytrail, kaby lake)
that if serial console is not enabled in coreboot, but is enabled in
kernel (v4.4), then on resume kernel hangs. In order to fix this, add
support for enabling UART debug port controller on resume.
In order to decide whether UART debug port controller should be
enabled in ramstage, following things are checked in given order:
1. If coreboot has serial console enabled, there is no need to
re-initialize the controller.
2. This special action is taken only for UART debug port controller.
3. If boot is not S3 resume, then initialization is skipped.
4. Callback into SoC to check if it wants to initialize the
controller.
If all the above conditions are met, then UART debug port controller
is initialized and taken out of reset.
BUG=b:64030366
TEST=Verified with the entire patchset series that:
1. If coreboot does not have serial console enabled, but Linux kernel
has console enabled, then on resume, coreboot initializes UART debug
port controller.
2. If coreboot and Linux do not have serial console enabled, then
coreboot does not initialize UART debug port controller.
3. If coreboot has serial console enabled, there is no change in
behavior.
Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add new API function lpss_is_controller_in_reset that returns whether
the LPSS controller is in reset. Also, add lpss.c to smm stage so that
lpss_is_controller_in_reset can be used in smihandler.
BUG=b:64030366
Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EvLoader is FSP module which loads and runs MMA tests.
With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader
needs to be enabled with UPD param from coreboot.
Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Introduce a chip_driver that uses devicetree instead of Kconfig.
The new driver has the following advantages:
* No more wasted IGD GFX stolen memory
* Can be used by T500 series
* Is even run on devices that do not have a dGPU installed
* Can disable unused PEG port on devices without dGPU (and save power)
* Use devicetree instead of Kconfig options
* Support for multiple hybrid GPIO active levels
* Support for backlight control GPIO
* Support for _ROM on Optimus capable devices
The driver is split into romstage part and ramstage part.
Every mainboard has to call the driver in romstage to get the requested
GPU state. The mainboard code then has to toggle GPU power or disable
the IGD or PEG port.
The ramstage part does handle the hygrid graphics GPIO, including
optional backlight mux GPIO. Every GPIO can have it's own active level,
as defined in devicetree. Devices are no longer disabled in ramstage.
The existing hybrid graphics driver does the same configuration and
should not interfere with this commit until it has been removed.
Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
working gbe in this configuration though)
* USB.
What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)
Not tested:
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If all strings in SMBIOS table are empty, smbios_string_table_len
function should return 2, cause every table must end with "\0\0".
Also replace "eos" field type in smbios structures
from char to u8.
Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Update the existing tianocore payload (which didn't do any more than
adding an elf payload with a specific name) to fetch and build the
UEFI corebootPayloadPackage, using the coreboot toolchain for
compilation. Only checkout the commit when changing commit IDs or if
version is master, instead of every time it builds.
Currently working if patches are merged into the upstream edk2
repository (to be included in a follow-on patch).
Change-Id: I0bf4cedec2d6821ae2a04184ebb5cf88979ccee3
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Evelyn Huang <evhuang@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Check for original LinuxBIOS header from LANL
- Check for the BSD style license used in x86emu
- Add top level checks for src/cpu and src/vboot
- Add drivers dir check for aspeed, emulation, and sil
- Add mainboard dir check for digitallogic
Change-Id: Ie1ef6a39fd1d184815d22235d43780caedb2ca95
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
libpayload needs a static copy of the out of line function
`font_glyph_filled()` in every TU that needs it. So make it static
inline.
This fixes a build error by gcc (Debian 7.1.0-12) 7.1.0 from Debian
Sid/unstable. This happens with any libpayload based payload like
coreinfo, nvramcui or tint.
```
[…]
LPCC build/coreinfo.elf (LINK)
/src/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(corebootfb.libc.o): In function `corebootfb_putchar':
/src/coreboot/payloads/libpayload/drivers/video/corebootfb.c:173: undefined reference to `font_glyph_filled'
[…]
```
Change-Id: I931f0f17b33abafdc49aa755a0dad65e28820750
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add smm common code for io trap handling. This feature is
mainly used by big core intel platforms. Commonizing io trap
handling will make bring up of big core platforms more
seamless.
Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The newline lint check takes forever as it checks every file
in the git repo -- not just the files changed. To add insult to
injury these checks are performed on every commit. Allow one to
skip this check by setting the LINT_SKIP_NEWLINE_CHECK environment
variable.
Change-Id: I1cd5c50627b73d68b0da2fcb2d9546eb874a7959
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch uses struct device explicitly for the ramstage functions
as that's the actual type it's working on. Additionally, the
declarations for types and functions are fully exposed so that
compliation units don't have to guard certain functions from use
because it's being compiled for multiple stages.
Change-Id: I8db23ed400a59073e1e66522d020a5928f71f3a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
the __must_check function attribute is pretty much straight from the
linux kernel - used to encourage callers to consume function return
values.
Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PMC util code is very similar accross different intel SOC's.
This patch is an effort to move those code in common place
so that it can be shared accross different intel platforms
instead of duplicating for each platform. This patch adds
pmclib.c file which contains the pmc utility functions
common accross SOC's. The config for common PMC is
SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's
Kconfig file in order to use the common PMC util code.
Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Internal PME is detected when bit PME_B0_STS is set. Following devices
causes internal PME.
- Integrated LAN
- HD Audio/Audio DSP
- SATA
- XHCI ('USB3')
- ME Maskable Host Wake
In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug.
So scan all PCIe RP for PME status bit & update event log accordingly.
BUG=b:36992859
TEST=Build for Soraka, Verify resume due to PME on root port is logged
in elog.
Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The schematics isn't available for the board, but other L*00 series boards
seem to use a different, compared to T*00 series, GPIO layout.
As it has never been tested, remove the broken driver.
Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Configuring the clockgen like vendor bios fixes the issue where the
display wobbles from left to right on the analog VGA output.
Note: This seems to be common issue/requirement on Intel devices from
that generation (also happens on dg43gt).
TESTED on Intel D510MO.
Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SPI controller initialization in finalize_chipset was failing
because FSP was setting FLOCKDN before finalize_chipset was called.
Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is
called before FSP notify function-Ready To Boot state.
TEST: run flashrom with -VVV and observe supported opcodes and SPI
flash chip are reported correctly, and write/erase operations succeeed.
Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When resuming from ACPI S3 suspend, EHCI controller
may be in D3 power-management state. Bring it to D0
early so it is functional for console.
NOTE: D3hot->D0 transition was observed to reset
previous programming of PCI_COMMAND register.
Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Starting with RK3399, PMUGPIO pull registers use the same write mask
format as normal GRF registers, so they need to use RK_CLRSETBITS()
rather than clrsetbits_le32().
BRANCH=None
BUG=None
TEST=boot from scarlet
Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Provide a hook to allow an optional one-time cbmem_top() initialization.
The new function, cbmem_top_init(), is called on the first expected
initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT
and EARLY_CBMEM_INIT.
Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For CAR platforms which don't migrate globals real globals can
be directly used. This alleviates the need to peform partial
recovery on every cbmem access which in turn acts like all non-CAR
platforms or any stages which execute entirely out of RAM.
Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This introduces support for font scaling with a factor provided via
Kconfig. In practice, the font itself is not scaled at any point in
memory and only the logic to determine whether a pixel should be filled
or not is changed.
Thus, it should not significantly impact either the access time or
memory use.
Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This introduces helpers for accessing the included font, instead of
using hardcoded values provided by the font's header itself.
It will allow painlessly adding support for font scaling in a subsequent
change. It should not introduce any functionality change.
Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under
Linux and Windows. All other Intel SoCs have this selected by
default, so this change simply corrects an omission on Braswell.
TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE
selected; observe that S3 resume fails without and succeeds with.
Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IOBP (I/O Buffer Programming) is an interface (indirect addresses space)
in the RCBA that is used to configure the high speed serial lanes on the
PCH, that are used for PCIe, USB3 and SATA.
This patch replaces the offsets in RCBA with the defines from pch.h, gives
the access functions and their parameters useful names and replaces two
magic addresses in IOBP space with their defines.
Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/16214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The code doesn't include much, but when compiled outside the coreboot
build (what the shipped Makefile is made for), we want to make sure that
the few files it includes are controlled by us.
TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works
Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We recently changed all PACKED, __PACKED, __attribute__((packed)) ... to
__packed to gain some consistency. In cbfstool we use compiler.h to
provide that where necessary.
The cross compiler I use doesn't provide __packed by itself, but liblz4
doesn't compensate for that. Therefore include compiler.h, and to avoid
adding dependencies to non-liblz4 code, do so through the command line.
Change-Id: I581e45639ac3e103af7c16793e8effe2e632dec7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This FCH_OEM_CALLOUT bypasses API and uses structures
that are private to AGESA. Attempt to clean it up by
first clarifying when it is used.
Change-Id: I63aa0f586f73e97d615b8596d73728edbaeb0a2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT.
This does not apply to family12 and family14 just yet, as
they do invalidate without write-back on CAR teardown.
Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.
As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.
Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi
Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently, the what-jenkins-does target doesn't stop if abuild fails.
This change gives a command line parameter to abuild with tells it to
exit with a non-zero exit status if any of the builds failed.
This will be particularly useful for concourse which doesn't parse the
junit.xml files, and only knows whether a build passed or failed by the
exit status.
Change-Id: Ic2be5deaedacd3f55db8e0b14a2b7b39cc44664e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
Updating from commit id 04b3835b:
2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.)
to commit id 8b714252:
2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field)
This brings in 19 new commits.
Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)
to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)
This brings in 373 new commits.
Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
For x86, we place the .id section at 4GiB - CONFIG_ID_SECTION_OFFSET.
To take effect, we have to guard the conflicting default placement in
`program.ld`. Also, as we only include the .id section into the boot-
block, guard it by ENV_BOOTBLOCK too.
Change-Id: Idc7cbd670ce4f75b7790ff8d95578683e355ba7e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20810
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The previous pre-commit script generates an error when a commit doesn't
actually generate a patch file. This happens in rare instances when the
only change in a patch is to update file permissions.
Update the pre-commit script to verify that there's actually a patch
before calling checkpatch. Also print that we're running checkpatch
so that it doesn't look like odd failures come from lint-stable.
Fixes Bug #132 - Problem with `lint-stable` when changing mode of file
Change-Id: I142610b6fc984b2b14fd6c634bc4e7f2880ba987
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In S3 resume, wifi is one of the wake sources.
If elog is enabled in config, then log wifi wakes in elog.
BUG=b:36992859
TEST= Build for Soraka. Do WoWlan during S3. Verify elog having update
on wake due to Wifi.
Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for dumping Intel Software Guard Extension (SGX)
status. --sgx or -x is the command line switch to get SGX status.
The code iterates through all cores and reads MSRs to check if SGX is
supported, enabled and the feature is locked.
Change-Id: I1f5046c1f6703f5429c8717053ffe9c981cedf6f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20758
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.
ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).
But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.
So, in coreboot, if we read the ME PG state in finalize.c, which
happens just after FSP Notify phase, where actually ME D0i3 bit
is set, we do not read the correct PG state values (i.e, 0xF9
and 0xFF).
But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.
So, removing the ME PG state prints from coreboot, since it is
actually showing wrong information, although ME Power Gating is
successful.
Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bettong board with the standard configuration is not capable of
running nvramui with the default size.
malloc error happens on PDC_makelines(). Resulting in:
Booting from CBFS...
Run img/nvramcui
Calling addr 0x00100000
initscr(): Unable to create stdscr.
exited with status 1
Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/20681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the unused support code from the old multi-device hudson
SD controller. The binaryPI blob contains the correct steps
for setting up SD and the public BKDG doesn't completely document
the controller.
The sd.c file was using device IDs not associated with the Stoney
Ridge APU. The hudson_enable() code removed was also looking for
incorrect device IDs and the PM_MANUAL_RESET register doesn't
behave as the source indicates.
The SD default settings may be overridden. Future improvements
may include a few Kconfig options and a weak call to the mainboard
for overriding additional defaults.
BUG=chrome-os-partner:62580062
Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apollo Lake SoC supports configuration of Running Average Power Limits
(RAPL) for package domain. This feature is not required for all APL
mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power
Limiting Control it is not necessary to enable the RAPL algorithm per
default. For that reason make the RAPL configuration selectable.
Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If we dont have a constant TSC rate, timestamp table
has odd leaps and may appear to run backwards. Add
functionality to apply a factor such that all stamps
are in the same timebase.
Change-Id: Idab9c2c00e117c4d247db8cc9a2897640fa01edd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC1 and PMIC2,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
init_igd_opregion itself is supposed to return cb_err so this adds
error handling, just like other implentations of write_acpi_tables do it.
this had been found by coverity:
*** CID 1378270: Error handling issues (CHECKED_RETURN)
/src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion()
141 /* If IGD is disabled, exit here */
142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
143 return current;
144
145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
146 opregion = (igd_opregion_t *)current;
CID 1378270: Error handling issues (CHECKED_RETURN)
Calling "init_igd_opregion" without checking return value
(as is done elsewhere 5 out of 6 times).
147 init_igd_opregion(opregion);
148 update_igd_opregion(opregion);
149 current += sizeof(igd_opregion_t);
150 current = acpi_align_current(current);
TEST=Built
Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4
Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN))
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a `for` instead of a `while` loop and use meaningful identifiers.
Also, don't use more than one variable for one and the same purpose,
don't use more (non-const) variables than necessary, don't alter more
than one variable per statement, don't compare pointers of different
types and don't do pointer arithmetic on `void *`.
This was meant as a fix up to a regression but that has already been
fixed.
Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This line has a weird history. It got a `|| exit 0` removed lately which
obviously was there to fix the presence of the superfluous `test` at the
beginning. Now, remove the `test` too to make the clean target always
succeed again ;)
Change-Id: I9e069cf5d9ac8416cf350161439aa60798ef7b6b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
SMBIOS memory HOB produced by glk FSP v52_27 has new structure
members, which are not available in current apl FSP. New FSP-m
header file in https://review.coreboot.org/#/c/20673/ lists new
SMBIOS structure members.
Break memory HOB save routine into different functions for glk
and apl to accomodate new changes.
Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit moves the register access from 8 bit to 32 bit so that this
function can be used with every platform.
Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Interrupt 11 is not used by legacy devices and so can always be used
for PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right.
Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The full path to the passed/failed build lists needs to be specified.
On the builders, the absolute path is passed in, which conflicted with
the ${TOP} value, causing this to fail on the builders. When TOP was
removed from the path, the builders worked correctly, but it failed when
run locally. This fixes the path in either case.
Change-Id: Ia4370f4a2b84991edccfc723a3136b88ca27db7d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
coreboot was setting SPI FPR register to protect the
mrc_cache data range stored in flash. This programming was being done
after FSP Notify 1.
But, FSP was locking the SPI by setting FLOCKDN Bit during Notify
phase 1, due to which coreboot was unable to protect that range.
As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip
the lockdown of flash on interest of bootloader. Set that UPD to 0
to skip the lockdown of FAST_SPI flash from FSP.
The same is being done from coreboot after end of Post at finalize.c
file.
BUG=b:63049493
BRANCH=none
TEST=FPR can be set properly to protect the mrc_cache range. The
issue reported in the bug doesn't come when both software and
hardware WP is enabled with this patch.
Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A new UPD named SpiFlashCfgLockDown is added in the FSP-S
header file.
This change is going to come in FSP in the next FSP release.
This patch is pushed to urgently fix the SPI FPR locking issue.
CQ-DEPEND=CL:*414049
BUG=b:63049493
BRANCH=none
TEST=Built and boot poppy
Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use 16bit write to avoid touching the upper two bytes that may cause
write cycle to fail in case a prior transaction has not completed.
This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the
SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,
writing both in the same cycle is guaranteed to work by design.
Avoid read->modify->write operation not to clear the RW1C bits
unintentionally.
Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Earlier 15ms time-out was kept for SPI transactions which was not
enough for SPI Erase transactions.
Increase the max time-out time to 5 secs which was present in SKL
before common code.
This increase in time-out won't disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.
BUG=b:63959637
BRANCH=none
TEST=Built and booted poppy and all SPI transactions succeeded.
Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The newline lint check just went in, and immediately broke the build
due to a commit that went in earlier today.
This fixes the build.
Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The romstage for both is line-for-line identical.
Merge both into P2B-DS so it benefits from my
modernization efforts.
Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage for both is line-for-line identical.
Merge both into P2B-LS so it benefits from my
modernization efforts.
Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I am able to complete a board-status run over onboard ethernet
(ie. it works) without this entry, so it's not necessary.
Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are 4 routines used in RAM init that most if not all
i440bx mainboards call in the same order. Implements a single
RAM init routine for them to allow for future consolidation.
Boards to be changed to use this one routine in a future change.
Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Add prompt so the defconfig can be selected for the build.
- Remove target rename code from makefile. The old versions don't build
with the latest vboot, so this isn't useful anymore.
- Change $(info ...) to an echo. info prints immediately when
evaluated, which made it print when it shouldn't have, on make clean
for example.
- Split up single line shell scripts into multiple lines
- Change checkout target to only update the commit id when actually
changing versions instead of on every build.
Change-Id: I46fc2822cf93c821b402e8961ceecedc088f486c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Update from commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)
to commit 5a086f5c - Tue Jul 11, 2017
(ps8751: enable software sync)
This brings the stable version of depthcharge forward by 74 commits.
Change-Id: I3a3719fa3a91824042d452de7774be85b884d96d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.
BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.
Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A few pieces of coreboot code (like the video bios emulator) are
imported from other code bases, and hence might call printf. In
order to see the output, we redefine printf to printk. However,
when we are re-importing this code in a userspace utility, we might
call printk instead of printf if we're not careful.
A good fix for this would be to not call printf in coreboot ever.
As a short term fix to keep testbios from segfaulting, we just
don't call printf from printk, so we don't cause our own stack to
overflow.
Change-Id: I789075422dd8c5f8069d576fa7baf4176f6caf55
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This does the following:
* Clarify that settings are set to the same value for each rank;
* Allows to program coarse
* Fix some style issues like white spaces between arithmetic
operators.
Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This does not use loops to compute timings but uses DIV_ROUND_UP.
Another thing affected by this patch are minimum timings. Presumably
those only need to be guarded against on DDR3. With this change
timings are set up like vendor (with tWTR below previous minimum)
TESTED on Intel D510MO
Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix an issue when setting an unaligned buffer where n is less
than the difference of the rounded up pointer and the pointer.
This was identified where n=1 was passed. n was decremented
once, as expected, then decremented again after the while()
evaluated to false. This resulted in a new n of 4GB.
Change-Id: I862671bbe7efa8d370d0148e22ea55407e260053
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The gpio numbers are global, but they have their respective place
within each community and the group within their community. For
all the calculations open coding this calculation convert them to
use the helpers.
Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A pad number is passed into gpi_status_get() to determine if its
associated bit is set from a generated event. However, the
implementation wasn't taking into account the gpi_status_offset
which dictates the starting offset for each community. Additionally,
the max_pads_per_group field is per community as well -- not global.
Fix the code to properly take into account the community's
gpi_status_offset as well as the max_pads_per_group.
Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in
`igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`.
Nobody missed it for nearly a year, plus, it's not applied on the GOP
path, let's drop it.
Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.
Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At a process _start, the stack is expected to be aligned to a
16-byte boundary. Upon entry to any function the stack frame
must have the end of any arguments also aligned. In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).
Align the stack down inside _secondary_start and preserve proper
alignment for the call to secondary_cpu_init.
Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.
1) http://wiki.osdev.org/System_V_ABI
See "Initial Stack and Register State" and "The Stack Frame"
in the supplements.
BUG=chrome-os-partner:62841664
Change-Id: I72b7a474013e5caf67aedfabeb8d8d2553499b73
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency
was I2C_SPEED_FAST.
This was due to incorrect register programming.
TEST= Build for Soraka, I2C frequency during firmware execution was
I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS.
Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the necessary changes to support Scarlet revision 1.
Since the differences to revision 0 are so deep, we have decided not to
continue support for it in the same image. Therefore, this patch will
break Scarlet rev0.
All the deviations from other Gru boards are currently guarded by
CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we
introduce more variants based on the newer Scarlet board design.
Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always enable tp-smapi and thermal managment.
The devicetree already configures the correct values. This patch makes
sure that invalid user-settings are ignored.
The tp-smapi bit is required for the SMM handler.
The thermal bit should be set to allow the EC to monitor thermal state
of the platform.
Change-Id: Ia5aa50e0b1148a7cc8e51480623368ee62edb849
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
HECI2 and HECI3 devices are “function disable” during FSP
Silicon Init phase. Device will not be visible over PCI bus
hence removing these devices from wake source list.
Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c. Build these into romstage from the makefile, and remove
the #includes.
Add a Kconfig option for platforms that do not use the
early smbus code.
Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Gentoo likes to use that variable for itself and insists on keeping it.
Meanwhile it doesn't seem to be set or used anywhere else in the gcc
build, and it seems there was a big $(P)-pruning going on in 2000,
so why is it even (still) there?
Related upstream change can be found at
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01015.html
Change-Id: I2c2bdf9cb215c489f760f43642a86592924e4e65
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some configurations of AGESA boards fail to boot after commit
61be360 AGESA: Fix UMA calculations
Implementation of cbmem_find() for ENV_ROMSTAGE expects
that CBMEM has already been initialized. In the case of
LATE_CBMEM_INIT boards, this is not the case and cbmem_top()
returned NULL prior to the offending commmit.
By definition LATE_CBMEM_INIT does not have known cbmem_top()
in ENV_ROMSTAGE except for possible ACPI S3 resume path.
Change-Id: Icb8f44661d479e5ad43b123600305dcbc3ce11e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
New post codes are
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT
This patch will make it more consistent to debug FSP hang
and reset issues.
Bug=none
Branch=none
TEST=Build and Boot on eve
Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Explicitly add LOGICAL to the reset macro name to make it explicit
that the values are logical.
2. Reword some of the comments and combine them into single comment
instead of scattering the comments throughout.
3. Use c99 struct initializers for the reset mapping array.
4. For the chipset specific values use literals that match the hardware.
5. Use 'U' suffixes on the literals so we don't trip up compiler being
over zealous on undefined behavior.
6. Use unsigned and fixed-width types for the reset mapping structure
since the code is reliant on matching up with a register definition.
7. Fix formatting that can fit < 80 cols.
Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sadly, small core and big core are not aligned with the OS driver's
expectation on the number of ACPI devices used for each community.
Big core uses a single device while small cores use one ACPI device
per community. Allow for this distinction within the common gpio
implementation and ensure apollolake is utilizing the new option
to retain the correct behavior.
Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The function find_fsp() parses the FSP header and returns either a valid
pointer to the FSP_INFO_HEADER or an error code. The caller of
find_fsp() only takes care about a NULL-pointer but not about a possible
error code. This leads to memory access violations in case of error when
FspTempRamInit is called.
To avoid this and to let the user know that there was an error while
parsing the FSP header show an error message and the error code.
Change-Id: I67fef0a53fb04c8ba5d18b5d4ef2fdc1aeba869e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a new kind of compile-time assertion based on Linux'
compiletime_assert(). The difference to the existing use of
_Static_assert() in coreboot (which should continue to be used where
appropriate) is that this new assertion only hits if the call to it is
not optimized out at compile time. It is therefore ideal to assert that
certain code paths are not included in the image if a certain Kconfig
option is (not) set. For example,
assert(!IS_ENABLED(CONFIG_THAT_MAKES_THIS_INAPPROPRIATE));
can be rewritten as
if (!IS_ENABLED(CONFIG_THAT_MAKES_THIS_INAPPROPRIATE))
dead_code("This code shouldn't be built for config X");
to turn it into a compile-time check.
Change-Id: Ida2911e2e4b3191a00d09231b493bf755e6f0fcb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I sent out an email to all of the maintainers asking to verify their
status.
- The email I sent to Marcin Wojciechowski bounced, so I'm removing the
Little Plains mainboard support.
- I'm removing myself from areas that I'm not currently maintaining.
- Due to Damien's schedule, he asked that the level for his pieces be
changed from "Maintained" to "Odd Fixes".
I've added a list of infrastructure owners and backup owners - This is
strictly informational.
Change-Id: I39715611e8025bb535cdf1012be2bf05bf91fdaa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Change register preservations and fix comments about register
usage accordingly. Do this to avoid use of %mm0-2 registers inside
macros defined in gcccar.inc, as future implementation of
C_BOOTBLOCK_ENVIRONMENT will use them as well.
Adjust caller side accordingly.
Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
After modifications:
f12 and f14 are identical
f10 is f14 with invd -> wbinvd modification added to HOOK_F10
f15 is f10 with invd -> wbinvd modification added to HOOK_F15
f15tn is f15 modified to use with TN / KV / KM
Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Including <fsp/gop.h> in util.h causes issues with
redeclarations when using SOC_INTEL_COMMON_GFX_OPREGION
along with FSP 1.1. Separating it out and including
directly in vbt.c has no negative side effects.
Change-Id: I2d82c2da40b067272d876929fc73b97f490146a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The memcpy(), memmove() and memcmp() functions use word by word
operations regardless of the pointer alignment. Depending on the
platform, this could lead to a crash.
This patch makes the memcpy(), memmove() or memcmp() operate byte per
byte if they are supplied with unaligned pointers.
Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar
is entirely RAM based there's no need to have an excessively large
stack for the lzma decompression buffer. Therefore, reduce the stack
required to 1 KiB like apollolake.
Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
At process _start, the stack is expected to be aligned to a
16-byte boundary. Upon entry to any function the stack frame
must have the end of any arguments also aligned. In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).
Align the stack down and change the method for executing
car_stage_entry from jmp to call which should preserve proper
alignment regardless of a 32- or 64-bit build.
Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.
1) http://wiki.osdev.org/System_V_ABI
See "Initial Stack and Register State" and "The Stack Frame"
in the supplements.
BUG=chrome-os-partner:62841664
Change-Id: I8a15514f551a8e17e9fe77b8402fe0d2b106972e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update my email address for Apollolake and FSP 2.0 driver. Also
downgrade support from "supported" to "maintained" as currently
no other Intel persons are assigned for the role.
Change-Id: I3033fc5ec8b0882ce79eeb15ee3eb13a228611a4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: Id98aa5f6dbdcbb8da4616d4fce6e7388f3ba4656
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Needs the ramstage configuration enabling of SuperIO GPIO pnp devices
for BSEL straps.
Also needs VSBGATE# to be on for ram to be powered during S3.
TESTED with 800MHz and 1067MHz FSB CPUs at the correct straps when
resuming from S3.
Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enable Azalia controller, HD Audio DSP and select
the HDAudio IoBuffer Ownership for rvp3.
Check if device is enabled in HDA codec init function
to avoid failure when Azalia controller is disabled in
the devicetree.cb.
BUG=None
TEST=Build for kblrvp3, Make sure booting is fine irrespective of HDA
enable/disable.
Change-Id: I87212fe16ecc6053d6d00372904a5fd5d6f6b209
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The optimization of the memset() function introduced by commit
dbadb1dd63 (libpayload: Reorder default
memcpy, speed up memset and memcmp) is provoking an issue on x86
platform when compiling without the CONFIG_GPL option.
GCC is making use of the movdqa instruction to copy words. This
instruction can raise a "General Protection Fault Exception" when it
is called on a non-aligned address argument.
Change-Id: I73382a76a4399d8e78244867f2ebb1dca176a6bf
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Due to reset signal, PMIC loses its internal register state. This
causes PMIC to be in improper state after sleep.
2. The intent of reset signal is to reset internal state of PMIC (which
happens once during power on), hence avoid asserting reset signal
when not needed.
3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode
when not in use to save max possible power.
To fix the same, do not reset PMIC while entering sleep.
By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto
3.63uW (Max). Refs: TPS68470 datasheet.
Measured value: 0.66uW
TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check
whether PMIC internal registers state are preserved.
Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 5535cead (intel/skylake: Disable SaGv in
recovery mode).
Commit 5535cead disables SaGv in recovery mode to save few seconds
booting time as we were doing memory training on every recovery flow.
Now we don't need to perform MRC training on every recovery boot
due to RECOVERY_MRC_CACHE implementation in place. Hence we don't
need to define different SaGv policy between Normal (developer) mode
and recovery mode to save few seconds.
Using different SaGv parameters between recovery and all other mode
has some significent drawbacks over warm reboot cycle. We are seeing
a MRC traning hang in eve/soraka/poppy devices with below use case.
Step 1: Boot system in developer mode (first time RW_MRC training)
Step 2: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 3: System will perform recovery mode MRC training and boot to
OS (first time RECOVERY_MRC training)
Step 4: Issue “reboot” from OS console.
Step 5: System wil boot in developer mode (using RW_MRC cache)
Step 6: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 7: System will pick RECOVERY_MRC_CACHE and will hang during
MRC training.
This patch fixes issue mentioned above and ensures system boot to
OS without any hang if we change mode (dev<->recovery) over warm
reset.
BUG=b:63515071
BRANCH=none
TEST=manual stress testing of dev<->recovery mode over warm boot.
No MRC hang with this fix on eve/soraka/poppy devices.
Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The macro FPGA_SET_PARAM was introduced to make the setting of different
FPGA registers with the appropriate values from hwinfo more
transparent. The hwilib takes care about the size of the provided buffer
where the requested value should be stored in. The fields in hwinfo have
not always the same size as the matching registers in the FPGA. So to
avoid errors resulting in a too small buffer when calling hwilib_get_field()
the buffer is now fixed to 32 bit and will be casted to the destination
type when the value is written into the FPGA register.
Changing the field size in hwilib would be the wrong way as the defined
lengths are specified this way to be expandable in the future.
In addition the number of maximum supported temperature sensors is
increased to 8 as the FPGA now supports more.
Change-Id: I0c697106783158420708a973c3cff2be90fa4fce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For distros that package and version gnat independently from gcc (such
as Ubuntu), try to build with gnatgcc first.
This fixes the issue of gcc -print-prog-name=gnat1 failing because gcc
is of a different version.
Change-Id: Icec6d1fba8855e88ac91d47842dcb7f6b9d35461
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20517
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix undefined behavior found by clang's -Wshift-sign-overflow, find,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Chell doesn't have a touchscreen, so remove the driver
definition from devicetree. Leave the PCI device function 0
enabled since disabling results in the touchpad (function 1)
being disabled as well.
Change-Id: I32619b7618bc0cdd99fa54fdda9bf2b5c1bb79a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist
directly before this check. Coverity had found this:
*** CID 1376664: Null pointer dereferences (REVERSE_INULL)
/src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan()
660 * this silicon. It is an SOC and can't have >= 16 APICs, but
661 * we will start numbering at 0x10. We also know there is only
662 * on physical node (module in AMD speak).
663 */
664
665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */
CID 1376664: Null pointer dereferences (REVERSE_INULL)
Null-checking "cdb_dev" suggests that it may be null, but it has already been
dereferenced on all paths leading to the check.
666 enable_node = cdb_dev && cdb_dev->enabled;
667 cpu_bus = dev->link_list;
668
669 for (j = 0; j <= siblings; j++ ) {
670 apic_id = lapicid_start + j;
671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n",
Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With the existing SSID, the driver loaded by Windows results
in the headphone jack and internal mic being non-functional.
With the new SSID, the a functional driver is loaded and
everything works correctly. Linux works correctly with
either SSID so the change has no impact there.
New SSID extracted from Windows drivers (.inf).
Change-Id: I4195d00d6b18dcd0039747d9883cdf8e1a76f461
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Returing FSL# for _STA causes Windows to BSOD. Re-work _STA to instead
return 0/1 based on FLVL, using google/beltino as a model.
Also correct serialization type for _CRS.
Change-Id: Ibf3af15bab3590f7c1c4401e1978dbcf2a495216
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix undefined behavior found by clang's -Wshift-sign-overflow. Left
shifting an int where the right operand is >= the width of the type
is undefined. Add UL suffix since it's safe for unsigned types.
Change-Id: Ieacf83d052bf4abfad639ef8e592bd8de17d16e6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Regarding the "System Management BIOS Reference Specification"
Version: 3.1.1, Date: 2017-01-12, Laptop system enclosure is 0x09
and for Notebook it is 0x0a
Change-Id: I5538be0b434eed20d76aef6f26247e46d1225feb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add I2C debugging support:
* Add I2C_DEBUG Kconfig value to enable debugging
* Display I2C segments before the transfer
* Display errors that occur during the transfer
* Display the number of bytes transferred for successful transfers
TEST=Build and run on Galileo Gen2
Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* Split the existing cflags to a second line to stay under 80 characters
* Correctly identify the libagesa "Stage" by adding the __LIBAGESA__
define to the files when they're compiled. This matches stage
defines such as __BOOTBLOCK__, __ROMSTAGE__, and __RAMSTAGE__. This is
needed to have printk actually show console information on whatever
interface the user has selected, such as the serial port, speaker,
SPI rom, or something else that hasn't been thought of yet.
Change-Id: I2a64414491130275ba06e5bd76e0b01e450174e8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Nothing in the amdlib.c file actually uses the StdHeader structure, so
remove the asserts verifying that it's not null, and remove references
to it from calls.
For now, I've left it in the parameters for the functions for
compatibility, but we might want to remove these at some point as well.
Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
Remove unnecessary memset().
Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add files for supporting the BIOS->PSP communication not
covered by AGESA. The first command implemented notifies the
PSP that DRAM is ready.
This patch also introduces the amd/common/block directory
structure similar to intel/common/block.
Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Toggle LEDs after successful dock and undock.
On boot the LED will light up and on undock button
press the LED will turn off again.
Tested on Lenovo T500.
Change-Id: Ib5851f4abcedf4041faae6b3b810102012f488cd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch basically does two things -
1) Remove unnecessary setting of flex_ratio to TDP nominal:
Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured
in MSR_PLATFORM_INFO(0xCE).
If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done
using MSR_FLEX_RATIO (0x194).
Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal
Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is
actually less than the factory configured Maximum Non TURBO Ratio (P1).
So, this code is actually not required.
Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor.
This Bit implies Processor Boot Max Frequency -
0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default)
This setting determines if the processor will operate at maximum frequency
at power-on and boot.
Thus this patch will avoid one extra platform warm reset now onwards.
2) Remove wrongly setting Max Frequency in Bootblock phase:
In the function set_max_frequency(), the P-State max ratio was set to
TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non
Trbo ratio.
But, when the cpu gets reset, it will operate with the Max-Non Turbo
ratio only, which is greater than the TDP Nominal ratio.
So, no need to set back the ratio to TDP Nominal which is lower than
the currently operating frequency.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the new PAD_CFG_GPI_INT macro to specify the headset codec
interrupt as specifically edge triggered (since it is registered
as EDGE_BOTH in the devicetree) in order to prevent the interrupt
from firing unexpectedly when the system is resuming.
Also change the DSP interrupt to edge triggered since the kernel
is registering with IRQF_TRIGGER_RISING in order to prevent an
interrupt storm when it asserts.
BUG=b:35582164
TEST=manual testing on Eve:
1) ensure the headset codec sends interrupt on insert and remove
2) ensure there is only one interrupt counted when DSP asserts irq
Change-Id: I40a8ee667de653e4e70770cd96b6417442c1b0ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for waking from and logging device events that
originate in the Embedded Controller. As this device uses
Deep S3 it relies on the EC to wake the AP from the trackpad
and DSP wake sources.
BUG=b:30624430
TEST=manual testing on Eve: wake from Deep S3 via trackpad and
DSP and verify the event log contains the expected device event.
Change-Id: I0d6a9c5bfd4cea85e13446ffaa6fe3dab0db96a2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for the new EC device event interface which is used to
report events from devices that are connected behind the EC.
This can be used to differentiate wake sources from the EC in the case
that the EC has the wake pins from various devices.
This can be used in case the AP is unable to directly wake from the
device itself, for example when using the Deep S3 state on Intel
platforms only a few pins can directly wake the AP.
BUG=b:30624430
TEST=build google/* boards that use chrome EC. Feature is used and
tested further in a subsequent commit.
Change-Id: I5126c6d6ffb6b0ef6e8db8dcd5aec62db925a371
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The architecture is determined by __riscv__ in the LZ4_copy8 function
(located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1.
But __riscv__ does not exist.
Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Signed-off-by: XiangWang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
The used RTC6110SA has issues to enter backup mode when the power supply
decreases too slow when the mainboard is turned off. Switch to backup
mode "primary cell" to make sure backup mode will be entered correctly
on power-off. In addition set IOCUTEN to minimize the backup current
consumption of the RTC.
Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
According to the datasheet the RTC needs a power rising slope of no more
than 100µs/V to ensure a correct power-on reset. If the mainboard that
hosts the RTC cannot guarantee this, a software reset sequence is needed
in the case where the battery was drained completely.
As the rising slope of the power supply depends on so many parameters
and is highly mainboard specific, refactor the initialization code to
perform a software reset every time a power loss event is recognized by
the RTC.
Change-Id: If64d672e51667523058041bd00e1e50ac047143d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When the C compiler expects 16-byte alignment of the stack it is
at the call instruction. Correct existing call points from assembly
to ensure the stacks are aligned to 16 bytes at the call instruction.
Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the TSC for the Stoney Ridge monotonic timer. Modern AMD
CPUs have invariant timestamp counters. This patch brings the
feature more in line with other devices and allows the use of
typical monotonic timer functions.
BUG=chrome-os-partner:62578062
Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Update checkpatch.pl to version 522b837
(checkpatch: warn when formats use %Z and suggest %z)
- This update moves the const_struct definitions into an external file.
coreboot will want to update this file, but for now I'm just pulling it
in directly from the linux tree.
- Update spelling.txt used by checkpatch.pl to version 505d308
(scripts/spelling.txt: add "overide" pattern and fix typo instances)
- Add better notes where things have been changed for coreboot to make
future merges easier.
Change-Id: I0ef067874fe7b1d23276a10e63858895d6083f69
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are up to two on-board PCI devices where bus master has to be
enabled in PCI config space. As there is no need for a complete PCI
driver for these devices just set the bus master bit in
mainboard_final().
In a perfect world that would be the task of the runtime driver which
unfortunately don't do that.
Change-Id: Ic2896d5e7568a455737af26b14b2c398caae5f72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Now that pci_devs.h is part of soc/ and not used for multiple
southbridges:
* Remove devices not present in the Stoney Ridge APU
* Complete the list to include additional devices besides
those in the FCH.
BUG=chrome-os-partner:62578372
Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20370
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a memmap file with a cbmem_top() function. Remove the
LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls
to the late-only set_top_of_ram() function.
Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Describe RT5663 headphone codec in ACPI so it can
be enumerated by the OS.
- Supply NHLT binaries for RT5663
BUG=b:62872377
TEST=Apply full patch set and UCM, verify basic audio works.
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076
Reviewed-on: https://review.coreboot.org/20305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the code we do the following in a number of places
to pre-initialize an array with a certain value before
overwriting some of the array with other values:
u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
}
clang does not like that behavior unless we specify
the option -Wno-initializer-overrides.
Remove the check for gcc in those places, too, because
1) it would silently change array contents between compilers
2) the check isn't sufficient to determine compilation on
clang vs gcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc
Reviewed-on: https://review.coreboot.org/20384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Wow, this one is disliked by clang for the empty for() loop, but
looking at the file just makes my eyes bleed a little bit. I remember
the circumstances under which we let this code go in. It was supposed
to save contributions from a vendor, but that never worked out.
Just to keep the little chunks down, here's an indent run and some of
the cruft removed that doesn't actually contribute to functionality in
any way.
Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Remove IDE from the Stoney Ridge source. This APU doesn't have
an IDE controller. The support was left over from pi/hudson.
BUG=chrome-os-partner:62580062
Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs. Remove this support from the source.
This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.
BUG=chrome-os-partner:62580062
Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. Some of the lines requiring a >80
break are indented too much currently.
Changes to agesawrapper.c cause the build to change, so this
file is also left as-is. Make hex values consistently lower-case.
BUG=chrome-os-partner:622407746
Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.
These changes were confirmed to cause no changes in a Gardenia
build.
BUG=chrome-os-partner:622407746
Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Don't ask for bootstrapping in case of a different host GCC major
version. GCC's versioning scheme changed starting with the release
of GCC 5. There are no big changes between the versions any more.
Instead, show the message when the host GCC's version is below 4.
In case GNAT can't be found, ask the user to abort and install it.
Also give hints for Ubuntu where the package versions are a little
messy (e.g. the meta packages gcc and gnat often point to different
versions).
In case GNAT is found but is too old (< 4.9), enable bootstrapping
by default and tell the user that building will take longer.
In all three cases show a timeout to draw the user's attention.
v2: Update GNAT check to also look for `gnatbind`. It has to be
somewhere in $PATH.
Change-Id: I4d9de11d7469e137ede8ad138296d20c0f8ba78f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20332
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
"quit" is a signal name. The FreeBSD `sh` interprets
trap quit 1 2 3 15
as command to reset all the respective signal handlers, instead
of setting quit() as handler.
Change-Id: I69b813ab583f15a9dd89a115f7aea66d966f981b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20391
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
... even though the author of the code probably wished he was
working on a (much faster) broadwell system instead. Let's fix
the header guard to reflect the right SOC.
Noteworthy: clang detected that this was wrong.
Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The warning -Wstack-usage= doesn't seem to exist on clang, so trying
to disable it makes the compiler unhappy about non-existent pragmas.
Catching this on gcc is good enough, so let's disable it for the clang
case
Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If SSE instructions are enabled in the build assume the SMM
modules are compiled with SSE instructions. As such enable
the SSE instructions in SMM mode by setting up the cr4 register.
In addition, provide a place to save and restore the SSE state
in both the relocation handler and permanent handler.
Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in acpi_name to return proper ACPI names.
To be used with SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl.
LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl.
RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl.
SATA is defined in sb/intel/bd82x6x/acpi/sata.asl.
SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl.
EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl.
XHC is defined in sb/intel/bd82x6x/acpi/usb.asl.
Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Update from commit bcffec7fd - reef: Cleanup battery code
to commit 9fb10386a - Poppy: Configure camera PMIC to low power mode.
Brings in 794 new commits from Jan 2, 2017 to Jun 21, 2017
Change-Id: I864679360bd3b211b6883a662e20812b49aefbba
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ChromeEC board directories for auron and rambi have been removed
from the latest version of ChromeEC. Remove them here so the submodule
can be brought forward.
Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Update the world facing camera sensor to OV13858 and also
add delay of 5ms after xshutdown rising which indicates system
ready status.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Add clock frequency property into _DSD ACPI object and set it
to 19.2MHz for camera sensors. Upstream camera kernel has added
a check for clock frequency in sensor probe function and without
this property sensor probe fails.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20294
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Some environments (<grumble>cros_sdk</grumble>) provide gcc as $CC and
clang++ as $CXX. The latter needs the higher bracket-depth while the
former has no idea what it means, so tell CC and CXX individually.
Change-Id: I72b75fb9bb5df3a9b1561ee8821ec43ada29b24f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/20365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the framebuffer address is zero the corebootfb_init() function
should abort and not attempt to use it for video, otherwise it
will likely hang.
This was tested by booting on a board that does not have a display
attached and includes the previous patch to zero the framebuffer
structure in the coreboot tables.
Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Zero the framebuffer structure so if it is not filled in (either if
no display is present or if there is an error) then it does not
provide garbage data to the payload.
This was noticed when booting a board without a display attached as
the payload wrote to the framebuffer at a random address.
With this change the payload can properly handle the case where a
display is not attached and not corrupt memory.
Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In the D0 and D3 ACPI methods use word access to the PME status and
control register. This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices
Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For the skylake/kabylake generation of PCH there is an ACPI workaround
for emmc/sd power state that involves disabling and re-enabling dynamic
clock gating after enabling power to the controller, before setting the
power state to D0.
Under certain conditions we have observed that the controller is not
powered and ready by the time the kernel attempts to read the PME
control and status register and so the system will hang while attempting
to read PCI config register 0x84.
To ensure that the controller is ready add a 2ms delay after re-enabling
dynamic clock gating and before setting the power state to D0.
This issue has been observed on eMMC, but the same workaround exists for
the SD card interface so the same delay is added there.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across many devices
shows no hard hang after 2 days.
Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a Kconfig value to enable building libpayload with the 586 compiler.
Update the cross compiler script to add the Kconfig value name that is
used when libpayload builds.
The Quark SOC does not support some of the instructions generated with
the 686 compiler (e.g. CMOV). Success occurs when
payloads/libpayload/build/config.h indicates that
CONFIG_LP_USE_MARCH_586=1.
TEST=Build and run on Galileo Gen2.
Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Also check for the presence of the given commands or "gcc", "cc" in this
order if $CC is empty. To untangle the given compilers from boostrapped
ones, introduce hostcc() and hostcxx() functions that return the respec-
tive compilers to be used.
Change-Id: Ic947be53eec25331173ac82ed742017ca3fbf83c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the default configuration file for the Galileo board. The Quark SOC
requires building libpayload with march=i586.
TEST=Build and run on Galileo Gen2
Change-Id: Ifd4b533feacbab6f0d357e13d8cebb64bc1c18c6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
clang, like gcc, needs a compiler runtime library. Unlike gcc, it can
use either its own runtime library (compiler-rt), or gcc's version
(libgcc). Also unlike gcc, the version of clang that is currently part
of our reference toolchain does not provide the necessary versions of
compiler-rt for all platforms we support. Hence, for now, use libgcc
even on clang builds. This patch allows switching between the two, but
switching to compiler-rt will break clang builds, unless someone fixes
our reference toolchain to provide libclang_rt.builtins-${ARCH}.a for
each of our supported platforms.
Change-Id: I5001a4b62ed34df19312f980b927ced8cbaf07db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It does not work to enable the LPC range in the function
mainboard_init() because the LPC bus driver closes the range during PCI
enumeration again. For this reason, enabling decoding of the address
range for COM 3 will be done at a later point in time -
mainboard_final().
Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Bifferboard was the only board that used this chip, and it has now
been removed. Removing the chip as well. If there is desire to
continue work on the board, it can be found in the 4.6 branch.
Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
rdrand64() is not clang friendly. Actually it looks like the
function is incorrect on 32bit x86 for all compilers including
gcc, but gcc won't care because the function is never called on
x86:
src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a'
: "=a" (*rand), "=qm" (carry));
^
1 error generated.
Guard the code correctly if ENV_X86_64 is not set.
Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
The vboot code tries reading rollback protection indices from the TPM,
and if the attempt to read returns TPM_E_BADINDEX, it decides that the
TPM has not yet been initialized for the Chromebook use, and needs to
be taken through the factory initialization sequence.
TPM_E_BADINDEX is an internal representation of the TPM error 0x28b,
generated on attempts to read a non existing NVMEM space.
If the space exists, but has never been written the TPM returns error
0x14a. This condition (the space exists but not written) could happen
if the previous factory initialization attempt was interrupted right
after the space was created.
Let's map this error to the same internal representation
(TPM_E_BADINDEX) so that the Chrome OS device could recover when this
condition occurs.
BRANCH=reef, gru
BUG=b:37443842
TEST=verified that the Pyro device stuck in TPM error state recovered
when this patch was applied.
Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/20299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Drop Edward's cfe patch because it has been implemented by
upstream clang differently. Instead of
$ clang --print-librt-file-name
the right way to get ahold of the compiler-rt builtin library is
$ clang -rtlib=compiler-rt --print-libgcc-file-name
Change-Id: I8aac5256da5bfb6f7bebeff0959f16b53867c581
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SMI code is very similar across Intel platforms. Move this code to
common/block/smi to allow it to be shared between platforms instead
of duplicating the code for each platform. smihandler.h has already
been made common so all it will contain is name changes and a move
to the common block location. Due to moving smihandler code, APL
changes are bundled here to show this change.
Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/19392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SPI driver code for the legacy SPI flash controller. Enable erase
and write support allowing coreboot to save non-volatile data into
the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable RT8168_GET_MAC_FROM_VPD in fizz Kconfig.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I00f63dcb56a2c9a4600c8461bc94e06ec5ab2d81
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If RT8168_GET_MAC_FROM_VPD selected, use r8168
driver with some slight mods to check the VPD
for a mac address. Otherwise, check for mac
address in cbfs. Use default mac address if
cannot find one.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
The report triggered for smbios_cpu_vendor(). Also fixes the same issue
in smbios_processor_name() found by inspection.
Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This patch adds mipi_camera.asl,
* Add TPS68470 PMIC related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fixes 2 reports found by undefined behavior sanitizer. Dereferencing
pointers that are not aligned to the size of access is undefiend
behavior.
Change-Id: Iaa3845308171c307f1ddc7937286aacbd00e3a10
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This might provide a minor speedup but more importantly it allows
skipping commits without Reviewed-on line (which we have a couple of
due to mistakes with git push).
To use, add a line starting with "Gerrit-Rebase-Ignore-CLs-Before:"
pointing out a match string (ie "something that comes after Reviewed-on")
prior to which no changes are considered on the originating branch. The
target branch is still fully considered to avoid issues with changes
that were retargetted out of order around the new cut and would then
make a reappearance (or be skipped).
Change-Id: I9f2679891e93f6d28a781315aebd2aa60a1e3b23
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The previous implementation was using a for loop. By it's
very definition the last statement in the for loop declaration
is done at the end of the loop. Therefore, if the conditional for
breaking out of the for loop because of a timeout would always
see a value of 0 for the number of APs accepted. Correct this
by changing to a while loop with an explicit timeout condition
at the end of the loop.
Change-Id: I503953c46c2a65f7e264ed49c94c0a46d6c41c57
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.
The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.
Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable libgfxinit.
Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)
All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.
Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
While building poppy board, build failed with following error message:
Writing new image to build/coreboot.pre.new
mv build/coreboot.pre.new build/coreboot.pre
util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null
This image does not contains a ME/TXE firmware NR = 0)
make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55:
add_intel_firmware] Error 1
Hence keeping CHECK_ME unset by default.
TEST=Succesfully built coreboot for Poppy & booted to OS.
Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled
the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull
resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected
2.2k resistor to i2c of TP device.
The default of this gpio status is pulled up during the start to bootup,
it's very weak drive for the TP device that maybe cause to trigger the
recovery process of elan's firmware.
Also, the Elan updated its firmware(102.0.5.0) to delay checking the
i2c of touchpad is greater than 1 second.
So we have to drive the stronger pull-up within 1 second of powering up
the touchpad to prevent its firmware from falling into recovery.
Change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This reverts commit f4835a85c0. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.
The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.
Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special
way: If it wasn't set, perform native gfx init in textmode, if it was
set, perform native gfx init in linear framebuffer mode. Test for
LINEAR_FRAMEBUFFER instead and make the native gfx init optional.
Also, make Kconfig reflect the actual behaviour.
Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was the single spot where VGA_BIOS_ID wasn't guarded by anything.
It resulted in the wrong default id if we didn't chose to add a VGA BIOS
at first but added one later (e.g. a board provided default guarded by
VGA_BIOS wasn't applied then, because the Via/CN700 value was already
set).
Change-Id: Ia16a5e6d194191d8da8c551d6eb3849bc65864a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A major regression was introduced with commit 6520e01a
(soc/intel/apollolake: Perform CPU MP Init before FSP-S Init)
where the APs execution context is taken away by FSP-S. It
appears that FSP-S is not honoring the SkipMpInit UPD because
it's been shown with some debug code that FSP-S is compeltely
hijacking the APs:
Chrome EC: Set WAKE mask to 0x00000000
Chrome EC: Set WAKE mask to 0x00000000
CBFS: 'VBOOT' located CBFS at [440000:524140)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 2e700 size 1a00
Running FSPS in 4 secs.. 315875 4315875
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
Running FSPS.. 4315875 4315875
ITSS IRQ Polarities Before:
ITSS IRQ Polarities Before:
IPC0: 0xffffeef8
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0x00ffffff
ITSS IRQ Polarities After:
IPC0: 0xffffeef8
IPC1: 0x4a07ffff
IPC2: 0x08000000
IPC3: 0x00a11000
This is essentially a revert of 6520e01a to fix the previous
behavior.
Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20215
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 2e7f6cc introduced the 'no graphics init' option for
FSP 1.1 SoCs using a GOP driver to init the display, but selecting
that option while including a VBT breaks compilation for Braswell
and Skylake devices because the VBT and GOP driver are intertwined.
This patch decouples the VBT from the GOP driver execution,
allowing the 'no graphics init' option to compile (and work)
properly when CONFIG_ADD_VBT_DATA_FILE=y.
Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20210
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20141
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Initial support for undefined behavior sanitizer in ramstage. Enabling
this will add -fsanitize=undefined to the compiler command line and
link with ubsan.c in ramstage. Code with UB triggers a report with
error, file, and line number, then aborts.
Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that is not aligned to the size of access is undefined behavior.
Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other
write16()s in setup_ebda() to memcpy() for consistency.
Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
USB port status register can be used to decide if a particular port
was responsible for generating PME# resulting in device wake:
1. CSC bit is set and port is capable of waking on connect/disconnect
2. PLC bit is set and port is in resume state
BUG=b:37088992
TEST=Verified with wake on USB2.0 port 3, mosys shows:
19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3
Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.
initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
src/ec/*/*/ec_lpc.c \
src/superio/*/*/superio.c \
src/superio/smsc/fdc37n972/fdc37n972.c \
src/superio/smsc/sio10n268/sio10n268.c \
src/superio/via/vt1211/vt1211.c
src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.
Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fix line over 80 characters, spaces required around comparisons,space
required after close brace '}', comma ',', semicolon ';', space
prohibited after ')' errors and warnings
Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O.
Tested, working:
* Booting Linux 4.11.3 and Windows 8.1 from USB and HDD
* Resume from S3 (Linux and Windows)
* Native raminit (DDR2-800)
* Native graphics init (SeaBIOS, Linux)
* Graphics init with VGA BIOS (SeaBIOS, Windows)
* PCI-E x16 PEG slot, PCI-E x1 slot from southbridge
* Realtek ALC888 HD Audio (including front panel and jack detection)
* Realtek R8168 Gigabit LAN
* Both SATA ports
* USB 1.1 and 2.0 devices (keyboard, mass storage)
* PC speaker beep
* COM header
* Super I/O Environment controller (temps, voltage, fans)
* PS/2 keyboard and mouse
* Flashing with `flashrom -p internal`
* 1MiB and 2MiB SPI flash chips
* CMOS gfx_uma_size
Appears, OS driver loads, but otherwise untested:
* IrDA header
* CIR header
* TPM header
Untested:
* S/PDIF digital audio
Tested, known broken:
* CMOS power_on_after_fail
* USB keyboard in secondary payloads
Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20027
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix line over 80 characters, unnecessary braces for single statement
blocks, spaces before close parantheses errors and warnings.
Signed-off-by: Evelyn Huang <evhuang@google.com>
Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d
Reviewed-on: https://review.coreboot.org/20097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix space prohibited between function name and open parenthesis, line
over 80 characters, unnecessary braces for single statement blocks,
space required before open brace errors and warnings
Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for google/rambi
as to not break compilation.
Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20056
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Unfortunately, some external websites and projects are spelling coreboot
with an uppercase C, so references to those pages can't be changed
without breaking the link.
Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This device is extremely similar to the IT8718F, so support is based on
existing support for the IT8718F. The CIR device is only detected by
Linux/Windows from the ACPI tables, so ACPI support is extended from the
IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K.
Tested, working:
* Serial port 1
* Environment controller
- Temperature monitoring
- Voltage monitoring
- Fan control (automatic and manual)
* PS/2 keyboard and mouse
Appears, OS driver loads, but otherwise untested:
* Serial port 2
* Consumer IR
Untested:
* Floppy controller
* Parallel port
* GPIO
Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an
input), SMBus SPD addresses are accepted from the mainboard and not
calculated within the spd_bin library routines. Use the addr_map
values to print correct address in dump_spd_info.
Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create Intel Common CPU library code which provides various
CPU related APIs.
This patch adds cpulib.c file which contains various helper
functions to address different CPU functionalities like -
cpu_set_max_ratio(),
cpu_get_flex_ratio(),
cpu_set_flex_ratio(),
cpu_get_tdp_nominal_ratio(),
cpu_config_tdp_levels(),
cpu_set_p_state_to_turbo_ratio(),
cpu_set_p_state_to_nominal_tdp_ratio(),
cpu_set_p_state_to_max_non_turbo_ratio(),
cpu_get_burst_mode_state(),
cpu_enable_burst_mode(),
cpu_disable_burst_mode(),
cpu_enable_eist(),
cpu_disable_eist(),
cpu_enable_untrusted_mode()
Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Since get_microcode_info() is aleady searching for the microcode in cbfs,
we can just add a intel_microcode_load_unlocked() call here to update
the microcode. No need to duplicate finding microcode step during
pre_mp_init() function.
Change-Id: I525cab0ecc7826554f0a1209862e6357d1c7a9a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.
But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.
BUG=none
BRANCH=none
TEST=Build and Boot poppy
Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20051
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Like the previous commit allow the declarations of functions to
be exposed to all stages unless ROMCC is employed.
Change-Id: Ie4dfc32f38890938b90ef8e4bc35652d1c44deb5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
cherry-pick from Chromium, commit 8fbe1e7
On Braswell and Baytrail devices, by userland 'perf top',
observed demanding clocks on __vdso_clock_gettime() since
chromeos_3.18 kernel; besides, evaluated massive calling of
clock_gettime() cost, up to 700 ns in average.
It turns out that Linux kernel of map_vdso() first call of
remap_pfn_range() does not fall into reserve_pfn_range()
due to size parameter, instead it relies on lookup_memtype()
and potentially be failed to be identified as eligible RAM
resource because the function of pat_pagerange_is_ram() actually
walks through root's sibling.
Meanwhile, on current BSW (and BYT) firmware implementation
makes System RAM resources located on child leaf, combining all
of these factors makes the kernel treat the vvar page of vdso
as a uncached-minus one leading slow access in result.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd
Original-Signed-off-by: Harry Pan <harry.pan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/368585
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update devicetree PCI config based on board spec:
- enable PCIe Root Ports 5 and 9 (wifi and nvme respectively)
- enable PCIe CLKREQ on RP9, disable on RP5
- enable USB OTG
- enable P2SB
Note: PCIe RP5 is on 0.1c.0 despite this being labeled as RP1
Change-Id: Ia71ed25bd41668df1ee3e4b4e28f54482722452c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The GPIO configuration matches the one from the original BIOS.
Some configs don't make much sense, but I kept it as is so it
would match (such as a NC pin with TX set to 1, or RXINV enabled).
Remove unnecessary early GPIO config.
Change-Id: Iaec8630cef9a523fb2e2503143aa4aa72fbedc1f
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19934
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Like other devices using ENE embedded controllers, the librem13v2
requires this config option for the PS2 keyboard and mouse
(trackpad) to function properly.
Change-Id: Ifba13b93a1fe2e76b2790d1c273fd9e2b5368ab0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the initial directory for the port of the Librem 13 v2.
The base implementation was copied from the google/chell directory
and the chell references were replaced. spd directory was removed
since the RAM is not soldered on the MB. The Kconfig, board_info.txt
and devicetree.cb files were modified to match the Librem 13 v2
hardware information. The romstage.c, mainboard.c, Makefile.in and
dsdt.asl were modified to remove chromeos specific code. The boardid.c,
chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c
files were removed from the tree, and the acpi directory was replaced
with the acpi directory from the purism/librem13 board.
These changes allow us to remove the references to chromeos specific
code and allow coreboot to compile when the librem13v2 board is selected.
Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Role-Based Error Reporting is not a configurable field,
it's a read only field in the Device Capability register.
This code was old and comes from commit f6eb88ad but evidently
is not useful in any way. The PCIe Specification [1] states
that it's read-only and must always be set to 1.
I have also done tests on purism/librem13 hardware, trying to
change that value, without any success.
[1]: PCI Express Base Specification Revision 3.0
Page 612
Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.
Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
A simple rename of the directory and the config values
and string in Kconfig/Kconfig.name/board_info.txt
It will be less confusing for users since the first models
are referred to as 'v1' everywhere now.
Change-Id: I23fa977717230c2001868741bb684e9633a2c0bb
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19931
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Adapted from Chromium commit 8fbe1e7 for soc/braswell
(also review.coreboot.org/#/c/20060/); same issue affects
baytrail as well.
This patch recollects TOLM accessing; as Aaron recalled some
core_msr_script turns off access to TOLM register, he suggests
to store tolm to avoid getting back a zero while setting acpi
nvs space.
Change-Id: Ib26d4fe229b3f7d8ee664f5d89774d1f4a997f51
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Baytrail/ValleyView UEFI reference code
Change-Id: Icc9b27aaa14583d11d325e43d9165ddda72ca865
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Each I2C controller should have a unique pair of DMA request lines,
and DMA channels should be assigned incrementally, rolling over as
necessary.
Source: Intel Braswell UEFI reference code
Change-Id: I1d97b5a07bf732c27caf57904c138b120b93ca81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit 7c634ae8 (msrtool: added support for Intel CPUs) adds `no-pic` to
the compiler flags.
GCC 7.0.1 20170316 fails to built with the error below.
```
/usr/bin/ld: msrtool.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: msrutils.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: sys.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: linux.o: relocation R_X86_64_32 against `.rodata.str1.1' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: freebsd.o: relocation R_X86_64_32S against `.data' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: final link failed: Nonrepresentable section on output
```
Removing the flag causes the build to succeed with GCC 7, 6.3, and clang
4.0.
Change-Id: I3d7aed27ce7f84aa27305c68e2d5f14607c58ec8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The RTC RX6110SA has several configuration options which might be
interesting to set. To make this setup independent of the driver itself
but let it still be configurable on mainboard level, add more
configuration options to the chip driver.
Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
GCC version 7 is being a bit picky about pointer and integer comparison
by default, which triggers a crossgcc build error.
This backports a patch from upstream GCC to fix the issue.
Change-Id: I8b1e806c10604c0df080ac5edc667bf1141e2c17
Signed-off-by: Paul Kocialkowki <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update libgfxinit to the latest master. Changes:
* Remove trailing whitespace in debug output.
* Change some types to make it verify with SPARK Pro.
* Add Broxton (Apollo Lake) support for eDP/DP/HDMI.
* Add Linux user-space test tool `gfx_test`.
* Add a README describing libgfxinit and the build process.
TEST=Booted lenovo/t420 and verified that internal and
external displays are working.
Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update libhwbase to the current master. Some noteworthy changes:
* Add prerequisites for upcoming Apollo Lake support in libgfxinit.
* Add some support for Linux user-space for libgfxinit's `gfx_test`.
* Fix compilation with GCC 7.
Change-Id: If3c65065ef9a2ff6fce221939fda43c9e30c1eb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix regression introduced by commit 5c026445
(drivers/intel/wifi: Add support for generating SSDT table)
In case the regular PCI path is taken, there're no chip_ops and the code
will segfault. The bug was covered by other bugs that caused this code
to never execute.
Add NULL pointer checks and only fill in device name if one is provided.
Tested on Lenovo T430 and wifi card 8086:0085.
Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Because the help block uses significant whitespace to determine whether
or not text is inside the help block, a mixture of spaces and tabs
confuses the parser.
If there's an unrecognized line, and the previous line was inside a help
block, it's likely that this line is too.
Additionally, this was found with a line that started ' configuration',
and threw a perl warning about an uninitialized value because the parser
thought this was the start of a new config line, but couldn't find the
symbol. Now we make sure that config statements have whitespace after
the 'config' statement.
Change-Id: I46375738a18903b266ea9fff3102a1a91235e609
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Turn the check for help text with no indentation from a warning to
an error.
- Show an error if the help text is at the same indentation level as
the 'help' keyword.
Change-Id: Ibf868c83e2a128ceb6c4d3da7f2cf7dc237054e6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This patch fixes ACPI debug print issue reported internally
while using APRT asl method. Potentially some junk characters
gets added into final print buffer due to LPSS MMIO register
space is 32 bit width and ADBG is one byte at a time.
TEST=Built and boo eve to ensure to be able to get ASL console
log without any corruption.
Change-Id: I0b6af789c0ffc79f7fee4652b4aa6a125b182296
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The comma-separated PCI vendor and device ID is used to associate the
VGA BIOS to the video device by using it as the file name of the VGA
Option ROM.
Change-Id: I755554eeb9a560d034d6e8fe49de619d800ea045
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Device ID is read from HP Elitebook 2760p.
Based on:
- superio/smsc/kbc1100 (LDNs, keyboard, EC)
- DSDT from OEM firmware (COM1 and mailbox)
- Datasheet "KBC1122 Priliminary DS Rev. 0.8"
Change-Id: Id172ae42411a6d42a4ae7c7f30f96aeda3e6c384
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
GCC7 has a new feature called -Wimplicit-fallthrough enabled by
default which checks for fallthrough in switch statements which is a
common error. When a fallthrough is actually intended a comment saying
so will satisfy GCC.
Fixes cbfstool not building with GCC7.
Change-Id: I83252fc96be7ce0971d4251b0fc88fbbd7440e71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.
The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.
Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is supposed to fill the `size[]` array with the actual sizes of
a device' MMIO ranges, but apparently isn't implemented for every
access method in libpci (we let the library choose one). It tells us
by clearing `PCI_FILL_SIZES` in the return value of `pci_fill_info()`
(which we don't check). Since we don't ever use `size`, we can just
make it clear and don't ask for it.
Change-Id: I3fb9334472f1c7563a9e17910190f73affbe067a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This typo existed in code before rewriting for using
defines and it's clearly visible after rewrite.
Previously it was writing to reserved area of GMBUS0 register,
while values are matching those of GMBUS1.
This line probably is a no-op since it's just sending the STOP
again (without an address set this time).
Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/16341
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
set_var_mtrr() and get_free_var_mtrr() don't need to be guarded
against various stages. It just complicates code which lives
in a compilation unit that is compiled for multiple stages by
needing to reflect the same guarding. Instead, just drop the
declaration guard. earlymtrr.c is still just compiled for earlier
stages, but if needed it's easy to move to a mtrr_util.c that
is compiled for all stages.
Change-Id: Id6be6f613771380d5ce803eacf1a0c8b230790b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20018
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each rambi variant has a different USB port config.
Port data currently available for only candy and squawks;
other variants to be added once data obtained.
Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem
messages to the 'CONSOLE' area in FMAP which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
TEST: boot Windows on google/butterfly, observe battery data
reported correctly.
Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/19992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a method to get the state of a bridge device.
Return true if at least one enabled device on the secondary
bus is found.
Useful to disable non hotplugable bridges without any devices attached.
Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19968
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The IO region defined for EC_HOST_CMD_REGION1 was incorrectly
using EC_HOST_CMD_REGION0 for the range maximum so the region
was showing a minimum of 0x880 and a maximum of 0x800.
Both min and max should report the same value as this region
is fixed and cannot be relocated by the OS.
Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In get_region, ifdtool assigns a not-known-to-be-aligned
pointer to a uint32_t *. Now you know and I know that it is
almost certainly aligned, but clang on OSX doesn't like this,
and it's a dicey thing to do in any event, just waiting
to hit someone hard at some future date.
Assign the pointer to a void * and use memmove to copy
the value to a uint32_t.
This usage is more portable to all little-endian architectures,
now, but is still not endian-safe. I doubt we'll ever care.
Change-Id: Ifb2f260c3363ab0f5b4a59e5a4e0b5ecf049fa96
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/19921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19965
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To unify the hwinfo handling along all Siemens MC boards the hwinfo
files have to be removed from the mainboard directory. They will be added
to cbfs in site-local/Makefile.inc.
Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The driver for the RTC RX6110SA is designed to be used with I2C bus.
This patch adds the possibility to use SMBus operations to access the
RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It
is not enabled per default so that I2C will be used. One can set this
switch on board level to use SMBus instead.
Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19978
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Caching is a very architecture-specific thing, but most architectures
have a cache in general. Therefore it can be useful to have a generic
architecture-independent API to perform simple cache management tasks
from common code.
We have already standardized on the dcache_clean/invalidate naming
scheme that originally comes from ARM in libpayload, so let's just do
the same for coreboot. Unlike libpayload, there are other things than
just DMA coherency we may want to achieve with those functions, so
actually implement them for real even on architectures with
cache-snooping DMA like x86. (In the future, we may find applications
like this in libpayload as well and should probably rethink the API
there... maybe move the current functionality to a separate
dma_map/unmap API instead. But that's beyond scope of this patch.)
Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).
Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig
guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be
selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro-
vide their own fill_lb_framebuffer() implementation.
Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so that its work is not lost even if AMD_DISABLE_STACK does
invalidation without writeback.
Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
GPP_C2 is being used as strapping option, so
should not be set to NF. Signal was floating
previously, which can lead to an assertion of
smbalert#.
BUG=b:37681121, b:35775024
BRANCH=None
TEST=powerd_dbus_suspend and ensure stays in suspend
Change-Id: I68091206014621419b886b723a5681541be989bc
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19904
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add more fine-grained details about what device caused the PME wake
event. This requires checking the PME status bit (bit 15) in PCI PM
control and status register for the PCI device.
BUG=b:37088992
TEST=Verifed that XHCI wake source was identified correctly:
135 | 2017-05-25 15:28:17 | ACPI Enter | S3
136 | 2017-05-25 15:28:26 | ACPI Wake | S3
137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0
Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all systems have sizeof(time_t) == sizeof(long), so
cast the delta here to a long to match the %ld format.
Change-Id: If235577fc35454ddb15043c5a543f614b6f16a9e
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://review.coreboot.org/19902
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19829
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
www.coreboot.org/Documentation is now built with hugo (www.gohugo.io)
based on files in this repo's /Documentation directory.
Also clarify that new additions to Documentation are under CC-BY 4.0 terms.
Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/19881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio
In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.
BUG=b:62028489
Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
CQ-DEPEND=CL:506453
Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Should result in a tiny speed bump in raminit since those addresses
are not checked for present DIMMs.
Checked in schematics of both Thinkpad X60 and T60 and tested to
configure raminit correctly for all DIMMs populated on X60.
Change-Id: I56c4f3176541bc75a8de3aac9f87526a77fc819b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It seems that the BootROM on the RK3399 overwrites some of the earlier
parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have
a persistent CBMEM console we want that area to survive in case of an
early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it
further back. (This reduces the stack size to 12KB which should still be
way more than enough.)
Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19692
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that all platforms are updated to provide spi bus map, there is no
need to keep the spi_setup_slave as a weak symbol.
BUG=b:38430839
Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Do not lock ETR3 CF9GR in early romstage.
As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done
in bd82x6x's finalize handler.
Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
** usb_always_on
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Submodule 3rdparty/arm-trusted-firmware 236c27d21f..3944adca59
This brings in 241 new commits from the upstream arm-trusted-firmware
repository, merged to the upstream tree between December 30, 2016 and
March 18, 2017.
3944adca Merge pull request #861 from soby-mathew/sm/aarch32_fixes
..
e0f083a0 fiptool: Prepare ground for expanding the set of images at
runtime
Also setup ATF builds so that unused functions don't break the build.
They're harmless and they don't filter for these like we do.
Change-Id: Ibf5bede79126bcbb62243808a2624d9517015920
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The 'cbmem -1' flag that cuts off console output before the last boot
will ignore content from earlier stages if it was truncated due to lack
of pre-CBMEM console space. This patch makes the "log truncated" message
more specific and adds it as an additional cut-off marker to 'cbmem -1'
to counteract that problem.
Also raise the log level of the coreboot banner one step to BIOS_NOTICE
to make it more likely to be included in the output for 'cbmem -1' to
find. (I believe NOTICE is reasonable but I wouldn't want to go as far
as WARN which should be reserved for actual problems. Of course this is
not ideal, but then again, our whole log-level system really isn't... it
would be better if we could make it always print a banner to the CBMEM
console without affecting the UART at the same time, but that would
require a larger amount of work.)
Change-Id: I58288593dfa757e14f4a9da4ffa7e27b0b66feb9
Reported-by: https://ticket.coreboot.org/issues/117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For some reason the "interface" for adding framebuffer information
is sitting in src/include/vbe.h while also guarding the call to
fill_lb_framebuffer() with vbe_mode_info_valid() along with some
macro if CONFIG_* for good measure.
Move the fill_lb_framebuffer() declaration to coreboot_tables.h and
provide a comment about how it should be used. Also, now that
there's no need for the notion of a global vbe_mode_info_valid()
remove it from the conditional call path of fill_lb_framebuffer().
Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
AGESA and binaryPI boards have no easy way to determine correct
cbmem_top() location early enough when GFXUMA is enabled, so they
will use these functions with EARLY_CBMEM_INIT as well.
At the end of AmdInitPost() the decisions of UMA base and size
have not been written to hardware yet. The decisions are stored
inside AGESA heap object we cannot locate from coreboot proper
until after AmdInitEnv().
Modify code such that weak backup functions are only defined
for LATE_CBMEM_INIT; they are somewhat troublesome to handle.
Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19306
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.
Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() has to be adapted.
Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19727
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero
default value.
TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and
build.
BUG=None
Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
disable_turbo function can be used to disable turbo mode
on each processor by settings MSR 0x1A0 bit 38.
This option will help to perform some quick test
without enabling turbo mode.
Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Put parameter comments and help text in the same order as the actual
parameters.
- Don't clone a new release tree from coreboot.org if a tree already
exists.
- Change COMMIT_ID parameter from optional to required. If it was
omitted previously, the head of the master branch would be used.
Change-Id: Ifa434a4911dec777004788e3cf4e3436875d929b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
They do 64bit accesses, and gcc does the necessary fix ups to handle
32bit values as zero-padded 64bit values.
clang, however, isn't happy with it.
Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is code to adjust the mapping down if a mmap fails
at a physical address. However, if the address is less
than the page size of the system then the physical offset will
underflow. This can actually cause a kernel panic on when
operating on /dev/mem.
The failing condition happens when the requested mapping at 0
fails in the kernel. The fallback path is taken and page size
is subtracted from 0 making a very large offset. The PAT code
in the kernel fails with a BUG_ON in reserve_memtype() checking
start >= end. The kernel needs to be fixed as well, but this
fallback path is wrong as well.
BUG=b:38211793
Change-Id: I32b0c15b2f1aa43fc57656d5d2d5f0e4e90e94ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19680
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19577
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the
ThinkLight from the Operating System. This patch adds partial support for
that method, enough to enable or disable the ThinkLight:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
With the original BIOS the UCMS method exposes a wide range of values
through a generic /proc/acpi/ibm/cmos interface. With the changes suggested
in this patch that interface is also exposed but only accepts the commands
to enable or disable the ThinkLight; all other commands are ignored.
This change would potentially benefit all currently supported Thinkpad
models, I only have an X201 available for tests though.
Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/19644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Only commented out code uses the variable `csr`, and GCC complains about
it, when enabling the warning *unused-but-set-variable*.
```
Checking for pciutils and zlib... me.c: In function ‘mei_dump’:
me.c:50:18: warning: variable ‘csr’ set but not used [-Wunused-but-set-variable]
struct mei_csr *csr;
^~~
```
As the code is commented, also comment out the declaration of the variable.
Change-Id: I4ecb2b5e9f32906ccfc8a0628d2e0f2d3ad39a02
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/19612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- set GPIO_183 to high level for enabling the power of SD card
- delete all GPIOs for JTAG interface because they lead to problems with
Lauterbach debug hardware
Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
s230u seems only have two sata ports: one for the 2.5in hdd and one for
msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5
(port 0 & 2) enables both.
Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19521
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/19293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel ® 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
Change-Id: I1288871769014f4c4168da00952a1c563015de33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use `uintptr_t` instead of `uint32_t`, fixing the error below on 64-bit
systems, where pointers are 64-bit wide.
```
cc -O0 -g -Wall -W -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-sign-compare -Wno-unused-function -c -o intelmetool.o intelmetool.c
intelmetool.c: In function ‘dump_me_memory’:
intelmetool.c:85:45: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
dump = map_physical_exact((off_t)me_clone, (void *)me_clone, 0x2000000);
^
```
BUG=https://ticket.coreboot.org/issues/111
Change-Id: Id8d778e97090668ad9308a82b44c6b2b599fd6c3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/19567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Wise (Debian) <pabs@debian.org>
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/19535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The AP sends the Cr50 a request to enable the new firmware image. If
the new Cr50 image was found and enabled, the AP expects the Cr50 to
reset the device in 1 second.
While waiting for the Cr50 to reset, the AP logs a newly defined event
and optionally shuts down the system. By default the x86 systems power
off as shutting those systems down is not board specific.
BRANCH=gru,reef
BUG=b:35580805
TEST=built a reef image, observed that in case cr50 image is updated,
after the next reboot the AP stops booting before loading depthcharge,
reports upcoming reset and waits for it.
Once the system is booted after that, the new event can be found
in the log:
localhost ~ # mosys eventlog list
...
7 | 2017-03-23 18:42:12 | Chrome OS Developer Mode
8 | 2017-03-23 18:42:13 | Unknown | 0xac
9 | 2017-03-23 18:42:21 | System boot | 46
...
Change-Id: I45fd6058c03f32ff8edccd56ca2aa5359d9b21b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide a common function to issue reboot commands to the EC.
Expose that function for external use and use it internal to
the module.
BUG=b:35580805
Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19573
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19553
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jenny Tc <jenny.tc@intel.com>
According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.
It should not harm the operation even if FSP was successful in switching
to HFM.
Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Board Scarlet doesn't use usbphy1.
BUG=b:37685249
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Even though the persistent CBMEM console is obviously awesome, there may
be cases where we only want to look at console output from the last boot.
It's easy to tell where one boot ends and another begins from the banner
message that coreboot prints at the start of every stage, but in order
to make it easier to find that point (especially for external tools),
let's put that functionality straight into the cbmem utility with a new
command line flag. Use the POSIX/libc regular expression API to find the
banner string for maximum compatilibity, even though it's kinda icky.
Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19055
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.
With xtal being active in S0ix state power impact is 1-2 mW.
Hence set xtal bypass bit in CIR31C for low power idle entry.
TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.
Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19442
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a configuration option to assign the binaryPI base address
for the ACPI registers. The binaryPI's assignment is determine
at build time and no run-time configuration is allowed.
Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19485
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19156
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
cbgfx currently does not support portrait screen which height >width.
so add it.
Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19474
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Create Intel Common FAST_SPI Controller code.
This code contains the code for SPI initialization which has
the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.
Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-01 14:02:19 +02:00
14315 changed files with 927275 additions and 1153984 deletions
The above configurations for git has been integrated into Makefile. You can run
{\small
\begin{verbatim}
$ make gitconfig
\end{verbatim}
}
\subsection{Work flow}
It is recommended that you make a new branch when you start to work, not pushing changes to master.
{\small
\begin{verbatim}
$ git checkout master -b mybranch
\end{verbatim}
}
After you have done your changes, run:
{\small
\begin{verbatim}
$ git add file_need_to_submit.c
$ git commit -m "my first change."
\end{verbatim}
}
% Does anyone have a better word to describe the phylosophy of spliting changes to patches?
You need to realize that the changes you have made should be well devided into
several commits. Each of them has one and only one meaning. You could use git rebase -i to
split, squash, remove, rewrite you comment.
Here is an example of a well-formatted commit message:
{\small
\begin{verbatim}
examplecomponent: Refactor duplicated setup into a function
Setting up the demo device correctly requires the exact same register
values to be written into each of the PCI device functions. Moving the
writes into a function allows also otherexamplecomponent to use them.
Signed-off-by: Joe Hacker <joe@hacker.email>
\end{verbatim}
}
Then you can push the code.
{\small
\begin{verbatim}
$ git push
\end{verbatim}
}
You can go to the ~\ref{sec:gerrit} gerrit to see if your changes is successfully pushed.
Often it might happen that the patch you sent for approval is not good
enough from the first attempt. Gerrit and git make it easy to track
patch evolution during the review process until patches meet our
quality standards and are ready for approval.
You can easily modify a patch sent to gerrit by you or even by someone
else. Just apply it locally using one of the possible ways to do it,
make a new local commit that fixes the issues reported by the
reviewers, then rebase the change by preserving the same Change-ID. We
recommend you to use the git rebase command in interactive mode,
Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master.
%
% Working with Gerrit
%
\section{Working with Gerrit}
\label{sec:gerrit}
If you are a coreboot user, not planning to contribute, you can skip this section.
\subsection{Get gerrit account}
You need to get an OpenID first. Currently Google account give you an OpenID. It means, if you have a gmail account, you have an OpenID. You can try to signed in.
Use the following steps to setup a build environment:
</p>
@ -118,7 +118,7 @@ edksetup.bat
<hr>
<h1><aname="QuarkFsp">Quark™ FSP</a></h1>
<h2><aname="QuarkFsp">Quark™ FSP</a></h2>
<p>
Getting the Quark FSP source:
</p>
@ -130,7 +130,7 @@ Getting the Quark FSP source:
<li>Use git to clone <atarget="_blank"href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li>
</ol>
<h2>Building QuarkFspPkg</h2>
<h3>Building QuarkFspPkg</h3>
<p>
There are two versions of FSP: FSP 1.1 and FSP 2.0. There are also two
different implementations of FSP, one using subroutines without SEC and
@ -157,7 +157,7 @@ Build commands shown building debug FSP:
</li>
</ul>
<h2>Copying FSP files into coreboot Source Tree</h2>
<h3>Copying FSP files into coreboot Source Tree</h3>
<p>
There are some helper scripts to copy the FSP output into the coreboot
added by <atarget="_blank"href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
added by <atarget="_blank"href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
added by <atarget="_blank"href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
added by <atarget="_blank"href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
added by <atarget="_blank"href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
added by <atarget="_blank"href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
added by <atarget="_blank"href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
added by <atarget="_blank"href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
\section{Kconfig variations}
Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
For variables set by the user, see src/console/Kconfig.
For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent.
Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
\section{Makefile and Makefile.inc}
There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
Make is not recursive. There is only one make process.
\subsection{subdirs usage}
Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
We define the common rules for which variation to use below.
\subsection{object file specification}
There are several different types of objects specified in the tree. They are:
\begin{description}
\item[obj]objects for the RAM part of the code
\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
\item[initobj]seperately-compiled code for the ROM section of coreboot
\end{description}
These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
\section{Example: AMD serengeti cheetah}
\subsection{mainboard/Kconfig}
Defines Vendor variables. Currently defined variables are:
Sources all Kconfig files in the vendor directories.
\input{ mainboardkconfig.tex}
\subsection{mainboard/Makefile.inc}
There is none at this time.
\subsection{mainboard/$<$vendor$>$/Kconfig}
We use the amd as a model. The only action currently taken is to source all Kconfig's in the
subdirectories.
\subsection{mainboard/$<$vendor$>$/Makefile.inc}
We use amd as a model. There is currently no Makefile.inc at this level.
The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
\subsubsection{devicetree.cb}
Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
properly, as it defines topology and chips that can be defined no other way.
Let's go through the tree.
\begin{verbatim}
chip northbridge/amd/amdk8/root_complex
device cpu_cluster 0 on
chip cpu/amd/socket_F
device lapic 0 on end
end
end
\end{verbatim}
This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
somewhere, since it runs memory.
What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
which connects to a {\it cpu/amd/socket\_F},
which has a local apic, which is on.
Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
BIOSes) that the BSP be CPU 0; any CPU will do.
\begin{verbatim}
device domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
\end{verbatim}
Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
\begin{verbatim}
chip southbridge/amd/amd8132
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
end
\end{verbatim}
This is the 8132, a bridge to a secondary PCI bus.
\begin{verbatim}
chip southbridge/amd/amd8111
# this "device pci 0.0" is the parent the next one
# PCI bridge
device pci 0.0 on
device pci 0.0 on end
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
end
\end{verbatim}
The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
\begin{verbatim}
device pci 1.0 on
chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
\end{verbatim}
The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
\begin{verbatim}
device pci 1.1 on end
device pci 1.2 on end
\end{verbatim}
More devices. These statements set up placeholders in the device tree.
\begin{verbatim}
device pci 1.3 on
chip drivers/i2c/i2cmux # pca9556 smbus mux
device i2c 18 on #0 pca9516 1
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 18 on #1 pca9516 2
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
chip drivers/generic/generic #dimm 1-2-0
device i2c 54 on end
end
chip drivers/generic/generic #dimm 1-2-1
device i2c 55 on end
end
chip drivers/generic/generic #dimm 1-3-0
device i2c 56 on end
end
chip drivers/generic/generic #dimm 1-3-1
device i2c 57 on end
end
end
end
end # acpi
\end{verbatim}
These are the i2c devices.
\begin{verbatim}
device pci 1.5 off end
device pci 1.6 off end
\end{verbatim}
More placeholders.
\begin{verbatim}
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
end # device pci 18.0
\end{verbatim}
These "register" commands set controls in the southbridge.
\begin{verbatim}
device pci 18.0 on end
device pci 18.0 on end
\end{verbatim}
These are the other two hypertransport links.
\begin{verbatim}
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
\end{verbatim}
The 18.1 devices are, again, northbridge control for various k8 functions.
\begin{verbatim}
end
\end{verbatim}
That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
\begin{verbatim}
chip northbridge/amd/amdk8
device pci 19.0 on # northbridge
chip southbridge/amd/amd8151
# the on/off keyword is mandatory
device pci 0.0 on end
device pci 1.0 on end
end
end # device pci 19.0
device pci 19.0 on end
device pci 19.0 on end
device pci 19.1 on end
device pci 19.2 on end
device pci 19.3 on end
end
\end{verbatim}
\subsection{cpu socket}
The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
of all defines and Makefile controls for building the CPU components of a board.
\subsubsection{ cpu/Kconfig}
Defines variables. Current variables are:
\input{cpukconfig.tex}
Sources all Kconfig files in the vendor directories.
\subsubsection{ cpu/Makefile.inc}
Unconditionally sources all Makefile.inc in the vendor directories.
\subsection{cpu/$<$vendor$>$/Kconfig}
The only action currently taken is to source all Kconfig's in the
subdirectories.
\subsection{cpu/$<$vendor$>$/Makefile.inc}
{\em Conditionally} source the socket directories.
Example:
\begin{verbatim}
subdirs-$(CONFIG_CPU_AMD_SOCKET_F)+= socket_F
\end{verbatim}
.
CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
The coreboot community is present at a number of conferences over the year,
usually at [FOSDEM](https://fosdem.org), [OSFC](https://osfc.io), and the
[Chaos Communication Congress](https://events.ccc.de/congress/).
The kind of presence differs, but there's usually a booth or other kind of
gathering where everybody is welcome to say hello and to learn more about
coreboot.
Depending on the nature of the conference, coreboot developers might bring
their development kit with them and conduct development sessions.
## Talks
[Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/) by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)
[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018)
[coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018
[A tale of reusability in coreboot](https://www.youtube.com/watch?v=p2bnEYKBDpI) by Furquan Shaikh at OSFC 2018
[How to enable AMD IOMMU in coreboot](https://www.youtube.com/watch?v=5JoEuh9qXx0) by Piotr Król at OSFC 2018
[ARM Trusted Firmware for coreboot developers](https://www.youtube.com/watch?v=UC35q4OJg3k) by Julius Werner at OSFC 2018
[Google Secure Microcontroller and Case Closed Debugging](https://www.youtube.com/watch?v=gC-lbMNmIsg) by Vadim Bendebury at OSFC 2018
[coreboot rompayload](https://www.youtube.com/watch?v=ukSh1n7wjSA) by Ron Minnich at OSFC 2018
[Run upstream coreboot on an ARM Chromebook](https://www.youtube.com/watch?v=N7_9okzPeHo) by Paul Menzel at ECC 2017
[DDR3 memory initialization basics on Intel Sandybrige platforms](https://www.youtube.com/watch?v=h-Lkkg03Erk) by Patrick Rudolph at ECC 2017
[Let's move SMM out of firmware and into the kernel](https://www.youtube.com/watch?v=6GEaw4msq6g) by Ron Minnich at ECC 2017
[SINUMERIK – step ahead with coreboot](https://www.youtube.com/watch?v=tq4xSipCWEU) by Werner Zeh at ECC 2017
[Booting UEFI-aware OS on coreboot enabled platform](https://www.youtube.com/watch?v=nt0BkqVUu3w) by Piotr Król and Kamil Wcisło at ECC 2017
[Reverse engineering MT8173 PCM firmwares and ISA for a fully free bootchain](https://www.youtube.com/watch?v=9rKxfo7Gkqo) by Paul Kocialkowski at ECC 2017
[A Tale of six motherboards, two BSDs and coreboot](https://www.youtube.com/watch?v=jlCGzML6zF8) by Piotr Kubaj at ECC 2017
[Enabling TPM 2.0 on coreboot based devices](https://www.youtube.com/watch?v=Yjb9n5p3giI) by Piotr Król and Kamil Wcisło at ECC 2017
[Porting coreboot to the HP ProLiant MicroServer Gen8](https://www.youtube.com/watch?v=BcmUSW2J53k) by Alexander Couzens and Felix Held at ECC 2017
[Implementing coreboot in a ground breaking secure system: ORWL](https://www.youtube.com/watch?v=D4oQjcP6AVI) by Wim Vervoorn and Gerard Duynisveld at ECC 2017
[Buying trustworthy hardware for federal agencies: How open source firmware saves the day](https://www.youtube.com/watch?v=DG_wfaw4zl0) by Carl-Daniel Hailfinger at ECC 2017
[Verified Boot: Surviving in the Internet of Insecure Things: Randall Spangler](https://www.youtube.com/watch?v=4EvTcfcYfMY) by Randall Spangler at coreboot conference 2016
[coreboot on RISC-V](https://www.youtube.com/watch?v=CDNIWuf1jAk) by Ron Minnich at coreboot conference 2016
[An Open Source Embedded Controller](https://www.youtube.com/watch?v=hQb8waUBVSQ) by Bill Richardson at coreboot conference 2016
[KB9012 EC Firmware Reverse Engineering](https://www.youtube.com/watch?v=B708jdCiW7o) by Paul Kocialkowski at coreboot conference 2016
[coreboot on ARM](https://www.youtube.com/watch?v=z-KpAA4_afs) by Julius Werner at coreboot conference 2016
[Intel FSP 2.0 overview](https://www.youtube.com/watch?v=uzfiTiP9dEM) by Giri Mudusuru and Vincent Zimmer at coreboot conference 2016
[coreboot Internals](https://www.youtube.com/watch?v=7YUXr1MH9d4) by Aaron Durbin at coreboot conference 2016
[Skylake FSP to coreboot integration overview](https://www.youtube.com/watch?v=SpL8LbquSVs) by Robbie Zhang at coreboot conference 2016
[S3 implementation on Braswell](https://www.youtube.com/watch?v=GfwTijFnFl0) by Hannah Williams at coreboot conference 2016
The above configurations for git has been integrated into Makefile. You can run
{\small
\begin{verbatim}
$ make gitconfig
\end{verbatim}
}
\subsection{Work flow}
It is recommended that you make a new branch when you start to work, not pushing changes to master.
{\small
\begin{verbatim}
$ git checkout master -b mybranch
\end{verbatim}
}
After you have done your changes, run:
{\small
\begin{verbatim}
$ git add file_need_to_submit.c
$ git commit -m "my first change."
\end{verbatim}
}
% Does anyone have a better word to describe the philosophy of splitting changes to patches?
You need to realize that the changes you have made should be well divided into
several commits. Each of them has one and only one meaning. You could use git rebase -i to
split, squash, remove, rewrite you comment.
Here is an example of a well-formatted commit message:
{\small
\begin{verbatim}
examplecomponent: Refactor duplicated setup into a function
Setting up the demo device correctly requires the exact same register
values to be written into each of the PCI device functions. Moving the
writes into a function allows also otherexamplecomponent to use them.
Signed-off-by: Joe Hacker <joe@hacker.email>
\end{verbatim}
}
Then you can push the code.
{\small
\begin{verbatim}
$ git push
\end{verbatim}
}
You can go to the ~\ref{sec:gerrit} gerrit to see if your changes is successfully pushed.
Often it might happen that the patch you sent for approval is not good
enough from the first attempt. Gerrit and git make it easy to track
patch evolution during the review process until patches meet our
quality standards and are ready for approval.
You can easily modify a patch sent to gerrit by you or even by someone
else. Just apply it locally using one of the possible ways to do it,
make a new local commit that fixes the issues reported by the
reviewers, then rebase the change by preserving the same Change-ID. We
recommend you to use the git rebase command in interactive mode,
Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master.
%
% Working with Gerrit
%
\section{Working with Gerrit}
\label{sec:gerrit}
If you are a coreboot user, not planning to contribute, you can skip this section.
\subsection{Get gerrit account}
You need to get an OpenID first. Currently Google account give you an OpenID. It means, if you have a gmail account, you have an OpenID. You can try to signed in.
Files under Documentation/ are licensed under CC-BY 4.0 terms, printed below.
As an exception, files under Documentation/ with a history older than 2017-05-24
might be under different licenses (but should be cleared up ASAP).
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You are suggested obtain the "Hardware Maintenance Manual" for your corresponding
model as a guidance. Some can be found from [Hardware Specifications of ThinkWiki].
[Hardware Specifications of ThinkWiki]: https://www.thinkwiki.org/wiki/Hardware_Specifications
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.jpg){kind=link}
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